adapter.h 8.1 KB

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  1. // Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
  2. /* SPDX-License-Identifier: GPL-2.0-only OR Apache-2.0 */
  3. #ifndef __ESP_NETWORK_ADAPTER__H
  4. #define __ESP_NETWORK_ADAPTER__H
  5. #define PRIO_Q_SERIAL 0
  6. #define PRIO_Q_BT 1
  7. #define PRIO_Q_OTHERS 2
  8. #define MAX_PRIORITY_QUEUES 3
  9. #define MAC_SIZE_BYTES 6
  10. /* ESP Payload Header Flags */
  11. #define MORE_FRAGMENT (1 << 0)
  12. /* Serial interface */
  13. #define SERIAL_IF_FILE "/dev/esps0"
  14. /* Protobuf related info */
  15. /* Endpoints registered must have same string length */
  16. #define RPC_EP_NAME_RSP "RPCRsp"
  17. #define RPC_EP_NAME_EVT "RPCEvt"
  18. #define H_SET_BIT(pos, val) (val|=(1<<pos))
  19. #define H_GET_BIT(pos, val) (val&(1<<pos)? 1: 0)
  20. /* Station config bitmasks */
  21. enum {
  22. STA_RM_ENABLED_BIT = 0,
  23. STA_BTM_ENABLED_BIT = 1,
  24. STA_MBO_ENABLED_BIT = 2,
  25. STA_FT_ENABLED_BIT = 3,
  26. STA_OWE_ENABLED_BIT = 4,
  27. STA_TRASITION_DISABLED_BIT = 5,
  28. STA_MAX_USED_BIT = 6,
  29. };
  30. #define WIFI_CONFIG_STA_RESERVED_BITMASK 0xFFC0
  31. #define WIFI_CONFIG_STA_GET_RESERVED_VAL(num) \
  32. ((num&WIFI_CONFIG_STA_RESERVED_BITMASK)>>STA_MAX_USED_BIT)
  33. #define WIFI_CONFIG_STA_SET_RESERVED_VAL(reserved_in,num_out) \
  34. (num_out|=(reserved_in << STA_MAX_USED_BIT));
  35. enum {
  36. WIFI_SCAN_AP_REC_phy_11b_BIT = 0,
  37. WIFI_SCAN_AP_REC_phy_11g_BIT = 1,
  38. WIFI_SCAN_AP_REC_phy_11n_BIT = 2,
  39. WIFI_SCAN_AP_REC_phy_lr_BIT = 3,
  40. WIFI_SCAN_AP_REC_phy_11ax_BIT = 4,
  41. WIFI_SCAN_AP_REC_wps_BIT = 5,
  42. WIFI_SCAN_AP_REC_ftm_responder_BIT = 6,
  43. WIFI_SCAN_AP_REC_ftm_initiator_BIT = 7,
  44. WIFI_SCAN_AP_REC_MAX_USED_BIT = 8,
  45. };
  46. #define WIFI_SCAN_AP_RESERVED_BITMASK 0xFF00
  47. #define WIFI_SCAN_AP_GET_RESERVED_VAL(num) \
  48. ((num&WIFI_SCAN_AP_RESERVED_BITMASK)>>WIFI_SCAN_AP_REC_MAX_USED_BIT)
  49. #define WIFI_SCAN_AP_SET_RESERVED_VAL(reserved_in,num_out) \
  50. (num_out|=(reserved_in << WIFI_SCAN_AP_REC_MAX_USED_BIT));
  51. enum {
  52. WIFI_STA_INFO_phy_11b_BIT = 0,
  53. WIFI_STA_INFO_phy_11g_BIT = 1,
  54. WIFI_STA_INFO_phy_11n_BIT = 2,
  55. WIFI_STA_INFO_phy_lr_BIT = 3,
  56. WIFI_STA_INFO_phy_11ax_BIT = 4,
  57. WIFI_STA_INFO_is_mesh_child_BIT = 5,
  58. WIFI_STA_INFO_MAX_USED_BIT = 6,
  59. };
  60. #define WIFI_STA_INFO_RESERVED_BITMASK 0xFFC0
  61. #define WIFI_STA_INFO_GET_RESERVED_VAL(num) \
  62. ((num&WIFI_STA_INFO_RESERVED_BITMASK)>>WIFI_STA_INFO_MAX_USED_BIT)
  63. #define WIFI_STA_INFO_SET_RESERVED_VAL(reserved_in,num_out) \
  64. (num_out|=(reserved_in << WIFI_STA_INFO_MAX_USED_BIT));
  65. /* WIFI HE AP Info bitmasks */
  66. enum {
  67. // WIFI_HE_AP_INFO_BSS_COLOR is six bits wide
  68. WIFI_HE_AP_INFO_partial_bss_color_BIT = 6,
  69. WIFI_HE_AP_INFO_bss_color_disabled_BIT = 7,
  70. WIFI_HE_AP_INFO_MAX_USED_BIT = 8,
  71. };
  72. #define WIFI_HE_AP_INFO_BSS_COLOR_BITS 0x3F
  73. /* WIFI HE Station Config bitmasks */
  74. enum {
  75. WIFI_HE_STA_CONFIG_he_dcm_set_BIT = 0,
  76. // WIFI_HE_STA_CONFIG_he_dcm_max_constellation_tx is two bits wide
  77. WIFI_HE_STA_CONFIG_he_dcm_max_constellation_tx_BITS = 1,
  78. // WIFI_HE_STA_CONFIG_he_dcm_max_constellation_rx is two bits wide
  79. WIFI_HE_STA_CONFIG_he_dcm_max_constellation_rx_BITS = 3,
  80. WIFI_HE_STA_CONFIG_he_mcs9_enabled_BIT = 5,
  81. WIFI_HE_STA_CONFIG_he_su_beamformee_disabled_BIT = 6,
  82. WIFI_HE_STA_CONFIG_he_trig_su_bmforming_feedback_disabled_BIT = 7,
  83. WIFI_HE_STA_CONFIG_he_trig_mu_bmforming_partial_feedback_disabled_BIT = 8,
  84. WIFI_HE_STA_CONFIG_he_trig_cqi_feedback_disabled_BIT = 9,
  85. WIFI_HE_STA_CONFIG_MAX_USED_BIT = 10,
  86. };
  87. #define WIFI_HE_STA_CONFIG_BITS 0xFC00
  88. #define WIFI_HE_STA_GET_RESERVED_VAL(num) \
  89. ((num&WIFI_HE_STA_CONFIG_BITS)>>WIFI_HE_STA_CONFIG_MAX_USED_BIT)
  90. #define WIFI_HE_STA_SET_RESERVED_VAL(reserved_in,num_out) \
  91. (num_out|=(reserved_in << WIFI_HE_STA_CONFIG_MAX_USED_BIT));
  92. #define H_FLOW_CTRL_NC 0
  93. #define H_FLOW_CTRL_ON 1
  94. #define H_FLOW_CTRL_OFF 2
  95. struct esp_payload_header {
  96. uint8_t if_type:4;
  97. uint8_t if_num:4;
  98. uint8_t flags;
  99. uint16_t len;
  100. uint16_t offset;
  101. uint16_t checksum;
  102. uint16_t seq_num;
  103. uint8_t throttle_cmd:2;
  104. uint8_t reserved2:6;
  105. /* Position of union field has to always be last,
  106. * this is required for hci_pkt_type */
  107. union {
  108. uint8_t reserved3;
  109. uint8_t hci_pkt_type; /* Packet type for HCI interface */
  110. uint8_t priv_pkt_type; /* Packet type for priv interface */
  111. };
  112. /* Do no add anything here */
  113. } __attribute__((packed));
  114. #define H_ESP_PAYLOAD_HEADER_OFFSET sizeof(struct esp_payload_header)
  115. typedef enum {
  116. ESP_INVALID_IF,
  117. ESP_STA_IF,
  118. ESP_AP_IF,
  119. ESP_SERIAL_IF,
  120. ESP_HCI_IF,
  121. ESP_PRIV_IF,
  122. ESP_TEST_IF,
  123. ESP_ETH_IF,
  124. ESP_MAX_IF,
  125. } esp_hosted_if_type_t;
  126. typedef enum {
  127. ESP_OPEN_DATA_PATH,
  128. ESP_CLOSE_DATA_PATH,
  129. ESP_RESET,
  130. ESP_MAX_HOST_INTERRUPT,
  131. } ESP_HOST_INTERRUPT;
  132. typedef enum {
  133. ESP_WLAN_SDIO_SUPPORT = (1 << 0),
  134. ESP_BT_UART_SUPPORT = (1 << 1), // HCI over UART
  135. ESP_BT_SDIO_SUPPORT = (1 << 2),
  136. ESP_BLE_ONLY_SUPPORT = (1 << 3),
  137. ESP_BR_EDR_ONLY_SUPPORT = (1 << 4),
  138. ESP_WLAN_SPI_SUPPORT = (1 << 5),
  139. ESP_BT_SPI_SUPPORT = (1 << 6),
  140. ESP_CHECKSUM_ENABLED = (1 << 7),
  141. } ESP_CAPABILITIES;
  142. typedef enum {
  143. // spi hd capabilities
  144. ESP_SPI_HD_INTERFACE_SUPPORT_2_DATA_LINES = (1 << 0),
  145. ESP_SPI_HD_INTERFACE_SUPPORT_4_DATA_LINES = (1 << 1),
  146. // leave a gap for future expansion
  147. // features supported
  148. ESP_WLAN_SUPPORT = (1 << 4),
  149. ESP_BT_INTERFACE_SUPPORT = (1 << 5), // bt supported over current interface
  150. // leave a gap for future expansion
  151. // Hosted UART interface
  152. ESP_WLAN_UART_SUPPORT = (1 << 8),
  153. ESP_BT_VHCI_UART_SUPPORT = (1 << 9), // VHCI over UART
  154. } ESP_EXTENDED_CAPABILITIES;
  155. typedef enum {
  156. ESP_TEST_RAW_TP_NONE = 0,
  157. ESP_TEST_RAW_TP = (1 << 0),
  158. ESP_TEST_RAW_TP__ESP_TO_HOST = (1 << 1),
  159. ESP_TEST_RAW_TP__HOST_TO_ESP = (1 << 2),
  160. ESP_TEST_RAW_TP__BIDIRECTIONAL = (1 << 3),
  161. } ESP_RAW_TP_MEASUREMENT;
  162. typedef enum {
  163. ESP_PACKET_TYPE_EVENT = 0x33,
  164. } ESP_PRIV_PACKET_TYPE;
  165. typedef enum {
  166. ESP_PRIV_EVENT_INIT = 0x22,
  167. } ESP_PRIV_EVENT_TYPE;
  168. typedef enum {
  169. ESP_PRIV_CAPABILITY=0x11,
  170. ESP_PRIV_FIRMWARE_CHIP_ID,
  171. ESP_PRIV_TEST_RAW_TP,
  172. ESP_PRIV_RX_Q_SIZE,
  173. ESP_PRIV_TX_Q_SIZE,
  174. ESP_PRIV_CAP_EXT, // extended capability (4 bytes)
  175. } ESP_PRIV_TAG_TYPE;
  176. typedef enum {
  177. HOST_CAPABILITIES=0x44,
  178. RCVD_ESP_FIRMWARE_CHIP_ID,
  179. SLV_CONFIG_TEST_RAW_TP,
  180. SLV_CONFIG_THROTTLE_HIGH_THRESHOLD,
  181. SLV_CONFIG_THROTTLE_LOW_THRESHOLD,
  182. } SLAVE_CONFIG_PRIV_TAG_TYPE;
  183. struct esp_priv_event {
  184. uint8_t event_type;
  185. uint8_t event_len;
  186. uint8_t event_data[0];
  187. }__attribute__((packed));
  188. #define SPI_HD_HOST_24_BIT_TX_INT 1
  189. /* use upper 8 bits of tx buf len register as interrupt control bits
  190. * host sends CMD9 to clear the register */
  191. #define SPI_HD_TX_BUF_LEN_MASK (0x00FFFFFF)
  192. #define SPI_HD_INT_MASK (3 << 24)
  193. #define SPI_HD_INT_START_THROTTLE (1 << 24)
  194. #define SPI_HD_INT_STOP_THROTTLE (1 << 25)
  195. /** Slave Registers used for SPI Half-Duplex mode transfers */
  196. typedef enum {
  197. SPI_HD_REG_SLAVE_READY = 0x00,
  198. SPI_HD_REG_MAX_TX_BUF_LEN = 0x04,
  199. SPI_HD_REG_MAX_RX_BUF_LEN = 0x08,
  200. SPI_HD_REG_TX_BUF_LEN = 0x0C, // updated when slave wants to tx data
  201. SPI_HD_REG_RX_BUF_LEN = 0x10, // updated when slave can rx data
  202. SPI_HD_REG_SLAVE_CTRL = 0x14, // to control the slave
  203. } SLAVE_CONFIG_SPI_HD_REGISTERS;
  204. typedef enum {
  205. SPI_HD_STATE_SLAVE_READY = 0xEE, // Slave SPI is ready
  206. } SLAVE_CONFIG_SPI_HD_STATE;
  207. // slave control bits
  208. typedef enum {
  209. SPI_HD_CTRL_DATAPATH_ON = (1 << 0),
  210. } SLAVE_CTRL_MASK;
  211. static inline uint16_t compute_checksum(uint8_t *buf, uint16_t len)
  212. {
  213. uint16_t checksum = 0;
  214. uint16_t i = 0;
  215. while(i < len) {
  216. checksum += buf[i];
  217. i++;
  218. }
  219. return checksum;
  220. }
  221. #endif