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adc.h

adc.h 54 KB
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  1. /**
    2. 

  2.  * \brief Component description for ADC
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_ADC_COMPONENT_H_
    25. 

  25. #define _SAMD21_ADC_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR ADC                                          */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
    32. 

  32. #define ADC_CTRLA_RESETVALUE                  _U_(0x00)                                            /**<  (ADC_CTRLA) Control A  Reset Value */
    33. 

  33. 

  34. #define ADC_CTRLA_SWRST_Pos                   _U_(0)                                               /**< (ADC_CTRLA) Software Reset Position */
    35. 

  35. #define ADC_CTRLA_SWRST_Msk                   (_U_(0x1) << ADC_CTRLA_SWRST_Pos)                    /**< (ADC_CTRLA) Software Reset Mask */
    36. 

  36. #define ADC_CTRLA_SWRST(value)                (ADC_CTRLA_SWRST_Msk & ((value) << ADC_CTRLA_SWRST_Pos))
    37. 

  37. #define ADC_CTRLA_ENABLE_Pos                  _U_(1)                                               /**< (ADC_CTRLA) Enable Position */
    38. 

  38. #define ADC_CTRLA_ENABLE_Msk                  (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)                   /**< (ADC_CTRLA) Enable Mask */
    39. 

  39. #define ADC_CTRLA_ENABLE(value)               (ADC_CTRLA_ENABLE_Msk & ((value) << ADC_CTRLA_ENABLE_Pos))
    40. 

  40. #define ADC_CTRLA_RUNSTDBY_Pos                _U_(2)                                               /**< (ADC_CTRLA) Run in Standby Position */
    41. 

  41. #define ADC_CTRLA_RUNSTDBY_Msk                (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)                 /**< (ADC_CTRLA) Run in Standby Mask */
    42. 

  42. #define ADC_CTRLA_RUNSTDBY(value)             (ADC_CTRLA_RUNSTDBY_Msk & ((value) << ADC_CTRLA_RUNSTDBY_Pos))
    43. 

  43. #define ADC_CTRLA_Msk                         _U_(0x07)                                            /**< (ADC_CTRLA) Register Mask  */
    44. 

  44. 

  45. 

  46. /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
    47. 

  47. #define ADC_REFCTRL_RESETVALUE                _U_(0x00)                                            /**<  (ADC_REFCTRL) Reference Control  Reset Value */
    48. 

  48. 

  49. #define ADC_REFCTRL_REFSEL_Pos                _U_(0)                                               /**< (ADC_REFCTRL) Reference Selection Position */
    50. 

  50. #define ADC_REFCTRL_REFSEL_Msk                (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)                 /**< (ADC_REFCTRL) Reference Selection Mask */
    51. 

  51. #define ADC_REFCTRL_REFSEL(value)             (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
    52. 

  52. #define   ADC_REFCTRL_REFSEL_INT1V_Val        _U_(0x0)                                             /**< (ADC_REFCTRL) 1.0V voltage reference  */
    53. 

  53. #define   ADC_REFCTRL_REFSEL_INTVCC0_Val      _U_(0x1)                                             /**< (ADC_REFCTRL) 1/1.48 VDDANA  */
    54. 

  54. #define   ADC_REFCTRL_REFSEL_INTVCC1_Val      _U_(0x2)                                             /**< (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V)  */
    55. 

  55. #define   ADC_REFCTRL_REFSEL_AREFA_Val        _U_(0x3)                                             /**< (ADC_REFCTRL) External reference A  */
    56. 

  56. #define   ADC_REFCTRL_REFSEL_AREFB_Val        _U_(0x4)                                             /**< (ADC_REFCTRL) External reference B  */
    57. 

  57. #define ADC_REFCTRL_REFSEL_INT1V              (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1.0V voltage reference Position  */
    58. 

  58. #define ADC_REFCTRL_REFSEL_INTVCC0            (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/1.48 VDDANA Position  */
    59. 

  59. #define ADC_REFCTRL_REFSEL_INTVCC1            (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) Position  */
    60. 

  60. #define ADC_REFCTRL_REFSEL_AREFA              (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External reference A Position  */
    61. 

  61. #define ADC_REFCTRL_REFSEL_AREFB              (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) /**< (ADC_REFCTRL) External reference B Position  */
    62. 

  62. #define ADC_REFCTRL_REFCOMP_Pos               _U_(7)                                               /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Position */
    63. 

  63. #define ADC_REFCTRL_REFCOMP_Msk               (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)                /**< (ADC_REFCTRL) Reference Buffer Offset Compensation Enable Mask */
    64. 

  64. #define ADC_REFCTRL_REFCOMP(value)            (ADC_REFCTRL_REFCOMP_Msk & ((value) << ADC_REFCTRL_REFCOMP_Pos))
    65. 

  65. #define ADC_REFCTRL_Msk                       _U_(0x8F)                                            /**< (ADC_REFCTRL) Register Mask  */
    66. 

  66. 

  67. 

  68. /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
    69. 

  69. #define ADC_AVGCTRL_RESETVALUE                _U_(0x00)                                            /**<  (ADC_AVGCTRL) Average Control  Reset Value */
    70. 

  70. 

  71. #define ADC_AVGCTRL_SAMPLENUM_Pos             _U_(0)                                               /**< (ADC_AVGCTRL) Number of Samples to be Collected Position */
    72. 

  72. #define ADC_AVGCTRL_SAMPLENUM_Msk             (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)              /**< (ADC_AVGCTRL) Number of Samples to be Collected Mask */
    73. 

  73. #define ADC_AVGCTRL_SAMPLENUM(value)          (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
    74. 

  74. #define   ADC_AVGCTRL_SAMPLENUM_1_Val         _U_(0x0)                                             /**< (ADC_AVGCTRL) 1 sample  */
    75. 

  75. #define   ADC_AVGCTRL_SAMPLENUM_2_Val         _U_(0x1)                                             /**< (ADC_AVGCTRL) 2 samples  */
    76. 

  76. #define   ADC_AVGCTRL_SAMPLENUM_4_Val         _U_(0x2)                                             /**< (ADC_AVGCTRL) 4 samples  */
    77. 

  77. #define   ADC_AVGCTRL_SAMPLENUM_8_Val         _U_(0x3)                                             /**< (ADC_AVGCTRL) 8 samples  */
    78. 

  78. #define   ADC_AVGCTRL_SAMPLENUM_16_Val        _U_(0x4)                                             /**< (ADC_AVGCTRL) 16 samples  */
    79. 

  79. #define   ADC_AVGCTRL_SAMPLENUM_32_Val        _U_(0x5)                                             /**< (ADC_AVGCTRL) 32 samples  */
    80. 

  80. #define   ADC_AVGCTRL_SAMPLENUM_64_Val        _U_(0x6)                                             /**< (ADC_AVGCTRL) 64 samples  */
    81. 

  81. #define   ADC_AVGCTRL_SAMPLENUM_128_Val       _U_(0x7)                                             /**< (ADC_AVGCTRL) 128 samples  */
    82. 

  82. #define   ADC_AVGCTRL_SAMPLENUM_256_Val       _U_(0x8)                                             /**< (ADC_AVGCTRL) 256 samples  */
    83. 

  83. #define   ADC_AVGCTRL_SAMPLENUM_512_Val       _U_(0x9)                                             /**< (ADC_AVGCTRL) 512 samples  */
    84. 

  84. #define   ADC_AVGCTRL_SAMPLENUM_1024_Val      _U_(0xA)                                             /**< (ADC_AVGCTRL) 1024 samples  */
    85. 

  85. #define ADC_AVGCTRL_SAMPLENUM_1               (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1 sample Position  */
    86. 

  86. #define ADC_AVGCTRL_SAMPLENUM_2               (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 2 samples Position  */
    87. 

  87. #define ADC_AVGCTRL_SAMPLENUM_4               (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 4 samples Position  */
    88. 

  88. #define ADC_AVGCTRL_SAMPLENUM_8               (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 8 samples Position  */
    89. 

  89. #define ADC_AVGCTRL_SAMPLENUM_16              (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 16 samples Position  */
    90. 

  90. #define ADC_AVGCTRL_SAMPLENUM_32              (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 32 samples Position  */
    91. 

  91. #define ADC_AVGCTRL_SAMPLENUM_64              (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 64 samples Position  */
    92. 

  92. #define ADC_AVGCTRL_SAMPLENUM_128             (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 128 samples Position  */
    93. 

  93. #define ADC_AVGCTRL_SAMPLENUM_256             (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 256 samples Position  */
    94. 

  94. #define ADC_AVGCTRL_SAMPLENUM_512             (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 512 samples Position  */
    95. 

  95. #define ADC_AVGCTRL_SAMPLENUM_1024            (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) /**< (ADC_AVGCTRL) 1024 samples Position  */
    96. 

  96. #define ADC_AVGCTRL_ADJRES_Pos                _U_(4)                                               /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Position */
    97. 

  97. #define ADC_AVGCTRL_ADJRES_Msk                (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)                 /**< (ADC_AVGCTRL) Adjusting Result / Division Coefficient Mask */
    98. 

  98. #define ADC_AVGCTRL_ADJRES(value)             (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
    99. 

  99. #define ADC_AVGCTRL_Msk                       _U_(0x7F)                                            /**< (ADC_AVGCTRL) Register Mask  */
    100. 

  100. 

  101. 

  102. /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
    103. 

  103. #define ADC_SAMPCTRL_RESETVALUE               _U_(0x00)                                            /**<  (ADC_SAMPCTRL) Sampling Time Control  Reset Value */
    104. 

  104. 

  105. #define ADC_SAMPCTRL_SAMPLEN_Pos              _U_(0)                                               /**< (ADC_SAMPCTRL) Sampling Time Length Position */
    106. 

  106. #define ADC_SAMPCTRL_SAMPLEN_Msk              (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)              /**< (ADC_SAMPCTRL) Sampling Time Length Mask */
    107. 

  107. #define ADC_SAMPCTRL_SAMPLEN(value)           (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
    108. 

  108. #define ADC_SAMPCTRL_Msk                      _U_(0x3F)                                            /**< (ADC_SAMPCTRL) Register Mask  */
    109. 

  109. 

  110. 

  111. /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
    112. 

  112. #define ADC_CTRLB_RESETVALUE                  _U_(0x00)                                            /**<  (ADC_CTRLB) Control B  Reset Value */
    113. 

  113. 

  114. #define ADC_CTRLB_DIFFMODE_Pos                _U_(0)                                               /**< (ADC_CTRLB) Differential Mode Position */
    115. 

  115. #define ADC_CTRLB_DIFFMODE_Msk                (_U_(0x1) << ADC_CTRLB_DIFFMODE_Pos)                 /**< (ADC_CTRLB) Differential Mode Mask */
    116. 

  116. #define ADC_CTRLB_DIFFMODE(value)             (ADC_CTRLB_DIFFMODE_Msk & ((value) << ADC_CTRLB_DIFFMODE_Pos))
    117. 

  117. #define ADC_CTRLB_LEFTADJ_Pos                 _U_(1)                                               /**< (ADC_CTRLB) Left-Adjusted Result Position */
    118. 

  118. #define ADC_CTRLB_LEFTADJ_Msk                 (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos)                  /**< (ADC_CTRLB) Left-Adjusted Result Mask */
    119. 

  119. #define ADC_CTRLB_LEFTADJ(value)              (ADC_CTRLB_LEFTADJ_Msk & ((value) << ADC_CTRLB_LEFTADJ_Pos))
    120. 

  120. #define ADC_CTRLB_FREERUN_Pos                 _U_(2)                                               /**< (ADC_CTRLB) Free Running Mode Position */
    121. 

  121. #define ADC_CTRLB_FREERUN_Msk                 (_U_(0x1) << ADC_CTRLB_FREERUN_Pos)                  /**< (ADC_CTRLB) Free Running Mode Mask */
    122. 

  122. #define ADC_CTRLB_FREERUN(value)              (ADC_CTRLB_FREERUN_Msk & ((value) << ADC_CTRLB_FREERUN_Pos))
    123. 

  123. #define ADC_CTRLB_CORREN_Pos                  _U_(3)                                               /**< (ADC_CTRLB) Digital Correction Logic Enabled Position */
    124. 

  124. #define ADC_CTRLB_CORREN_Msk                  (_U_(0x1) << ADC_CTRLB_CORREN_Pos)                   /**< (ADC_CTRLB) Digital Correction Logic Enabled Mask */
    125. 

  125. #define ADC_CTRLB_CORREN(value)               (ADC_CTRLB_CORREN_Msk & ((value) << ADC_CTRLB_CORREN_Pos))
    126. 

  126. #define ADC_CTRLB_RESSEL_Pos                  _U_(4)                                               /**< (ADC_CTRLB) Conversion Result Resolution Position */
    127. 

  127. #define ADC_CTRLB_RESSEL_Msk                  (_U_(0x3) << ADC_CTRLB_RESSEL_Pos)                   /**< (ADC_CTRLB) Conversion Result Resolution Mask */
    128. 

  128. #define ADC_CTRLB_RESSEL(value)               (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))
    129. 

  129. #define   ADC_CTRLB_RESSEL_12BIT_Val          _U_(0x0)                                             /**< (ADC_CTRLB) 12-bit result  */
    130. 

  130. #define   ADC_CTRLB_RESSEL_16BIT_Val          _U_(0x1)                                             /**< (ADC_CTRLB) 16-bit averaging mode  */
    131. 

  131. #define   ADC_CTRLB_RESSEL_10BIT_Val          _U_(0x2)                                             /**< (ADC_CTRLB) 10-bit result  */
    132. 

  132. #define   ADC_CTRLB_RESSEL_8BIT_Val           _U_(0x3)                                             /**< (ADC_CTRLB) 8-bit result  */
    133. 

  133. #define ADC_CTRLB_RESSEL_12BIT                (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 12-bit result Position  */
    134. 

  134. #define ADC_CTRLB_RESSEL_16BIT                (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 16-bit averaging mode Position  */
    135. 

  135. #define ADC_CTRLB_RESSEL_10BIT                (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) /**< (ADC_CTRLB) 10-bit result Position  */
    136. 

  136. #define ADC_CTRLB_RESSEL_8BIT                 (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos)  /**< (ADC_CTRLB) 8-bit result Position  */
    137. 

  137. #define ADC_CTRLB_PRESCALER_Pos               _U_(8)                                               /**< (ADC_CTRLB) Prescaler Configuration Position */
    138. 

  138. #define ADC_CTRLB_PRESCALER_Msk               (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos)                /**< (ADC_CTRLB) Prescaler Configuration Mask */
    139. 

  139. #define ADC_CTRLB_PRESCALER(value)            (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
    140. 

  140. #define   ADC_CTRLB_PRESCALER_DIV4_Val        _U_(0x0)                                             /**< (ADC_CTRLB) Peripheral clock divided by 4  */
    141. 

  141. #define   ADC_CTRLB_PRESCALER_DIV8_Val        _U_(0x1)                                             /**< (ADC_CTRLB) Peripheral clock divided by 8  */
    142. 

  142. #define   ADC_CTRLB_PRESCALER_DIV16_Val       _U_(0x2)                                             /**< (ADC_CTRLB) Peripheral clock divided by 16  */
    143. 

  143. #define   ADC_CTRLB_PRESCALER_DIV32_Val       _U_(0x3)                                             /**< (ADC_CTRLB) Peripheral clock divided by 32  */
    144. 

  144. #define   ADC_CTRLB_PRESCALER_DIV64_Val       _U_(0x4)                                             /**< (ADC_CTRLB) Peripheral clock divided by 64  */
    145. 

  145. #define   ADC_CTRLB_PRESCALER_DIV128_Val      _U_(0x5)                                             /**< (ADC_CTRLB) Peripheral clock divided by 128  */
    146. 

  146. #define   ADC_CTRLB_PRESCALER_DIV256_Val      _U_(0x6)                                             /**< (ADC_CTRLB) Peripheral clock divided by 256  */
    147. 

  147. #define   ADC_CTRLB_PRESCALER_DIV512_Val      _U_(0x7)                                             /**< (ADC_CTRLB) Peripheral clock divided by 512  */
    148. 

  148. #define ADC_CTRLB_PRESCALER_DIV4              (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 4 Position  */
    149. 

  149. #define ADC_CTRLB_PRESCALER_DIV8              (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 8 Position  */
    150. 

  150. #define ADC_CTRLB_PRESCALER_DIV16             (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 16 Position  */
    151. 

  151. #define ADC_CTRLB_PRESCALER_DIV32             (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 32 Position  */
    152. 

  152. #define ADC_CTRLB_PRESCALER_DIV64             (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 64 Position  */
    153. 

  153. #define ADC_CTRLB_PRESCALER_DIV128            (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 128 Position  */
    154. 

  154. #define ADC_CTRLB_PRESCALER_DIV256            (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 256 Position  */
    155. 

  155. #define ADC_CTRLB_PRESCALER_DIV512            (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) /**< (ADC_CTRLB) Peripheral clock divided by 512 Position  */
    156. 

  156. #define ADC_CTRLB_Msk                         _U_(0x073F)                                          /**< (ADC_CTRLB) Register Mask  */
    157. 

  157. 

  158. 

  159. /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
    160. 

  160. #define ADC_WINCTRL_RESETVALUE                _U_(0x00)                                            /**<  (ADC_WINCTRL) Window Monitor Control  Reset Value */
    161. 

  161. 

  162. #define ADC_WINCTRL_WINMODE_Pos               _U_(0)                                               /**< (ADC_WINCTRL) Window Monitor Mode Position */
    163. 

  163. #define ADC_WINCTRL_WINMODE_Msk               (_U_(0x7) << ADC_WINCTRL_WINMODE_Pos)                /**< (ADC_WINCTRL) Window Monitor Mode Mask */
    164. 

  164. #define ADC_WINCTRL_WINMODE(value)            (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))
    165. 

  165. #define   ADC_WINCTRL_WINMODE_DISABLE_Val     _U_(0x0)                                             /**< (ADC_WINCTRL) No window mode (default)  */
    166. 

  166. #define   ADC_WINCTRL_WINMODE_MODE1_Val       _U_(0x1)                                             /**< (ADC_WINCTRL) Mode 1: RESULT > WINLT  */
    167. 

  167. #define   ADC_WINCTRL_WINMODE_MODE2_Val       _U_(0x2)                                             /**< (ADC_WINCTRL) Mode 2: RESULT < WINUT  */
    168. 

  168. #define   ADC_WINCTRL_WINMODE_MODE3_Val       _U_(0x3)                                             /**< (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT  */
    169. 

  169. #define   ADC_WINCTRL_WINMODE_MODE4_Val       _U_(0x4)                                             /**< (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT)  */
    170. 

  170. #define ADC_WINCTRL_WINMODE_DISABLE           (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) /**< (ADC_WINCTRL) No window mode (default) Position  */
    171. 

  171. #define ADC_WINCTRL_WINMODE_MODE1             (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) /**< (ADC_WINCTRL) Mode 1: RESULT > WINLT Position  */
    172. 

  172. #define ADC_WINCTRL_WINMODE_MODE2             (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) /**< (ADC_WINCTRL) Mode 2: RESULT < WINUT Position  */
    173. 

  173. #define ADC_WINCTRL_WINMODE_MODE3             (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) /**< (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT Position  */
    174. 

  174. #define ADC_WINCTRL_WINMODE_MODE4             (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) /**< (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) Position  */
    175. 

  175. #define ADC_WINCTRL_Msk                       _U_(0x07)                                            /**< (ADC_WINCTRL) Register Mask  */
    176. 

  176. 

  177. 

  178. /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
    179. 

  179. #define ADC_SWTRIG_RESETVALUE                 _U_(0x00)                                            /**<  (ADC_SWTRIG) Software Trigger  Reset Value */
    180. 

  180. 

  181. #define ADC_SWTRIG_FLUSH_Pos                  _U_(0)                                               /**< (ADC_SWTRIG) ADC Conversion Flush Position */
    182. 

  182. #define ADC_SWTRIG_FLUSH_Msk                  (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)                   /**< (ADC_SWTRIG) ADC Conversion Flush Mask */
    183. 

  183. #define ADC_SWTRIG_FLUSH(value)               (ADC_SWTRIG_FLUSH_Msk & ((value) << ADC_SWTRIG_FLUSH_Pos))
    184. 

  184. #define ADC_SWTRIG_START_Pos                  _U_(1)                                               /**< (ADC_SWTRIG) ADC Start Conversion Position */
    185. 

  185. #define ADC_SWTRIG_START_Msk                  (_U_(0x1) << ADC_SWTRIG_START_Pos)                   /**< (ADC_SWTRIG) ADC Start Conversion Mask */
    186. 

  186. #define ADC_SWTRIG_START(value)               (ADC_SWTRIG_START_Msk & ((value) << ADC_SWTRIG_START_Pos))
    187. 

  187. #define ADC_SWTRIG_Msk                        _U_(0x03)                                            /**< (ADC_SWTRIG) Register Mask  */
    188. 

  188. 

  189. 

  190. /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
    191. 

  191. #define ADC_INPUTCTRL_RESETVALUE              _U_(0x00)                                            /**<  (ADC_INPUTCTRL) Input Control  Reset Value */
    192. 

  192. 

  193. #define ADC_INPUTCTRL_MUXPOS_Pos              _U_(0)                                               /**< (ADC_INPUTCTRL) Positive Mux Input Selection Position */
    194. 

  194. #define ADC_INPUTCTRL_MUXPOS_Msk              (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)              /**< (ADC_INPUTCTRL) Positive Mux Input Selection Mask */
    195. 

  195. #define ADC_INPUTCTRL_MUXPOS(value)           (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
    196. 

  196. #define   ADC_INPUTCTRL_MUXPOS_PIN0_Val       _U_(0x0)                                             /**< (ADC_INPUTCTRL) ADC AIN0 Pin  */
    197. 

  197. #define   ADC_INPUTCTRL_MUXPOS_PIN1_Val       _U_(0x1)                                             /**< (ADC_INPUTCTRL) ADC AIN1 Pin  */
    198. 

  198. #define   ADC_INPUTCTRL_MUXPOS_PIN2_Val       _U_(0x2)                                             /**< (ADC_INPUTCTRL) ADC AIN2 Pin  */
    199. 

  199. #define   ADC_INPUTCTRL_MUXPOS_PIN3_Val       _U_(0x3)                                             /**< (ADC_INPUTCTRL) ADC AIN3 Pin  */
    200. 

  200. #define   ADC_INPUTCTRL_MUXPOS_PIN4_Val       _U_(0x4)                                             /**< (ADC_INPUTCTRL) ADC AIN4 Pin  */
    201. 

  201. #define   ADC_INPUTCTRL_MUXPOS_PIN5_Val       _U_(0x5)                                             /**< (ADC_INPUTCTRL) ADC AIN5 Pin  */
    202. 

  202. #define   ADC_INPUTCTRL_MUXPOS_PIN6_Val       _U_(0x6)                                             /**< (ADC_INPUTCTRL) ADC AIN6 Pin  */
    203. 

  203. #define   ADC_INPUTCTRL_MUXPOS_PIN7_Val       _U_(0x7)                                             /**< (ADC_INPUTCTRL) ADC AIN7 Pin  */
    204. 

  204. #define   ADC_INPUTCTRL_MUXPOS_PIN8_Val       _U_(0x8)                                             /**< (ADC_INPUTCTRL) ADC AIN8 Pin  */
    205. 

  205. #define   ADC_INPUTCTRL_MUXPOS_PIN9_Val       _U_(0x9)                                             /**< (ADC_INPUTCTRL) ADC AIN9 Pin  */
    206. 

  206. #define   ADC_INPUTCTRL_MUXPOS_PIN10_Val      _U_(0xA)                                             /**< (ADC_INPUTCTRL) ADC AIN10 Pin  */
    207. 

  207. #define   ADC_INPUTCTRL_MUXPOS_PIN11_Val      _U_(0xB)                                             /**< (ADC_INPUTCTRL) ADC AIN11 Pin  */
    208. 

  208. #define   ADC_INPUTCTRL_MUXPOS_PIN12_Val      _U_(0xC)                                             /**< (ADC_INPUTCTRL) ADC AIN12 Pin  */
    209. 

  209. #define   ADC_INPUTCTRL_MUXPOS_PIN13_Val      _U_(0xD)                                             /**< (ADC_INPUTCTRL) ADC AIN13 Pin  */
    210. 

  210. #define   ADC_INPUTCTRL_MUXPOS_PIN14_Val      _U_(0xE)                                             /**< (ADC_INPUTCTRL) ADC AIN14 Pin  */
    211. 

  211. #define   ADC_INPUTCTRL_MUXPOS_PIN15_Val      _U_(0xF)                                             /**< (ADC_INPUTCTRL) ADC AIN15 Pin  */
    212. 

  212. #define   ADC_INPUTCTRL_MUXPOS_PIN16_Val      _U_(0x10)                                            /**< (ADC_INPUTCTRL) ADC AIN16 Pin  */
    213. 

  213. #define   ADC_INPUTCTRL_MUXPOS_PIN17_Val      _U_(0x11)                                            /**< (ADC_INPUTCTRL) ADC AIN17 Pin  */
    214. 

  214. #define   ADC_INPUTCTRL_MUXPOS_PIN18_Val      _U_(0x12)                                            /**< (ADC_INPUTCTRL) ADC AIN18 Pin  */
    215. 

  215. #define   ADC_INPUTCTRL_MUXPOS_PIN19_Val      _U_(0x13)                                            /**< (ADC_INPUTCTRL) ADC AIN19 Pin  */
    216. 

  216. #define   ADC_INPUTCTRL_MUXPOS_TEMP_Val       _U_(0x18)                                            /**< (ADC_INPUTCTRL) Temperature Reference  */
    217. 

  217. #define   ADC_INPUTCTRL_MUXPOS_BANDGAP_Val    _U_(0x19)                                            /**< (ADC_INPUTCTRL) Bandgap Voltage  */
    218. 

  218. #define   ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A)                                            /**< (ADC_INPUTCTRL) 1/4  Scaled Core Supply  */
    219. 

  219. #define   ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B)                                            /**< (ADC_INPUTCTRL) 1/4  Scaled I/O Supply  */
    220. 

  220. #define   ADC_INPUTCTRL_MUXPOS_DAC_Val        _U_(0x1C)                                            /**< (ADC_INPUTCTRL) DAC Output  */
    221. 

  221. #define ADC_INPUTCTRL_MUXPOS_PIN0             (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position  */
    222. 

  222. #define ADC_INPUTCTRL_MUXPOS_PIN1             (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position  */
    223. 

  223. #define ADC_INPUTCTRL_MUXPOS_PIN2             (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position  */
    224. 

  224. #define ADC_INPUTCTRL_MUXPOS_PIN3             (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position  */
    225. 

  225. #define ADC_INPUTCTRL_MUXPOS_PIN4             (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position  */
    226. 

  226. #define ADC_INPUTCTRL_MUXPOS_PIN5             (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position  */
    227. 

  227. #define ADC_INPUTCTRL_MUXPOS_PIN6             (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position  */
    228. 

  228. #define ADC_INPUTCTRL_MUXPOS_PIN7             (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position  */
    229. 

  229. #define ADC_INPUTCTRL_MUXPOS_PIN8             (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN8 Pin Position  */
    230. 

  230. #define ADC_INPUTCTRL_MUXPOS_PIN9             (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN9 Pin Position  */
    231. 

  231. #define ADC_INPUTCTRL_MUXPOS_PIN10            (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN10 Pin Position  */
    232. 

  232. #define ADC_INPUTCTRL_MUXPOS_PIN11            (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN11 Pin Position  */
    233. 

  233. #define ADC_INPUTCTRL_MUXPOS_PIN12            (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN12 Pin Position  */
    234. 

  234. #define ADC_INPUTCTRL_MUXPOS_PIN13            (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN13 Pin Position  */
    235. 

  235. #define ADC_INPUTCTRL_MUXPOS_PIN14            (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN14 Pin Position  */
    236. 

  236. #define ADC_INPUTCTRL_MUXPOS_PIN15            (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN15 Pin Position  */
    237. 

  237. #define ADC_INPUTCTRL_MUXPOS_PIN16            (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN16 Pin Position  */
    238. 

  238. #define ADC_INPUTCTRL_MUXPOS_PIN17            (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN17 Pin Position  */
    239. 

  239. #define ADC_INPUTCTRL_MUXPOS_PIN18            (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN18 Pin Position  */
    240. 

  240. #define ADC_INPUTCTRL_MUXPOS_PIN19            (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) ADC AIN19 Pin Position  */
    241. 

  241. #define ADC_INPUTCTRL_MUXPOS_TEMP             (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Temperature Reference Position  */
    242. 

  242. #define ADC_INPUTCTRL_MUXPOS_BANDGAP          (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) Bandgap Voltage Position  */
    243. 

  243. #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC    (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4  Scaled Core Supply Position  */
    244. 

  244. #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC      (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) 1/4  Scaled I/O Supply Position  */
    245. 

  245. #define ADC_INPUTCTRL_MUXPOS_DAC              (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) /**< (ADC_INPUTCTRL) DAC Output Position  */
    246. 

  246. #define ADC_INPUTCTRL_MUXNEG_Pos              _U_(8)                                               /**< (ADC_INPUTCTRL) Negative Mux Input Selection Position */
    247. 

  247. #define ADC_INPUTCTRL_MUXNEG_Msk              (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)              /**< (ADC_INPUTCTRL) Negative Mux Input Selection Mask */
    248. 

  248. #define ADC_INPUTCTRL_MUXNEG(value)           (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
    249. 

  249. #define   ADC_INPUTCTRL_MUXNEG_PIN0_Val       _U_(0x0)                                             /**< (ADC_INPUTCTRL) ADC AIN0 Pin  */
    250. 

  250. #define   ADC_INPUTCTRL_MUXNEG_PIN1_Val       _U_(0x1)                                             /**< (ADC_INPUTCTRL) ADC AIN1 Pin  */
    251. 

  251. #define   ADC_INPUTCTRL_MUXNEG_PIN2_Val       _U_(0x2)                                             /**< (ADC_INPUTCTRL) ADC AIN2 Pin  */
    252. 

  252. #define   ADC_INPUTCTRL_MUXNEG_PIN3_Val       _U_(0x3)                                             /**< (ADC_INPUTCTRL) ADC AIN3 Pin  */
    253. 

  253. #define   ADC_INPUTCTRL_MUXNEG_PIN4_Val       _U_(0x4)                                             /**< (ADC_INPUTCTRL) ADC AIN4 Pin  */
    254. 

  254. #define   ADC_INPUTCTRL_MUXNEG_PIN5_Val       _U_(0x5)                                             /**< (ADC_INPUTCTRL) ADC AIN5 Pin  */
    255. 

  255. #define   ADC_INPUTCTRL_MUXNEG_PIN6_Val       _U_(0x6)                                             /**< (ADC_INPUTCTRL) ADC AIN6 Pin  */
    256. 

  256. #define   ADC_INPUTCTRL_MUXNEG_PIN7_Val       _U_(0x7)                                             /**< (ADC_INPUTCTRL) ADC AIN7 Pin  */
    257. 

  257. #define   ADC_INPUTCTRL_MUXNEG_GND_Val        _U_(0x18)                                            /**< (ADC_INPUTCTRL) Internal Ground  */
    258. 

  258. #define   ADC_INPUTCTRL_MUXNEG_IOGND_Val      _U_(0x19)                                            /**< (ADC_INPUTCTRL) I/O Ground  */
    259. 

  259. #define ADC_INPUTCTRL_MUXNEG_PIN0             (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN0 Pin Position  */
    260. 

  260. #define ADC_INPUTCTRL_MUXNEG_PIN1             (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN1 Pin Position  */
    261. 

  261. #define ADC_INPUTCTRL_MUXNEG_PIN2             (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN2 Pin Position  */
    262. 

  262. #define ADC_INPUTCTRL_MUXNEG_PIN3             (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN3 Pin Position  */
    263. 

  263. #define ADC_INPUTCTRL_MUXNEG_PIN4             (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN4 Pin Position  */
    264. 

  264. #define ADC_INPUTCTRL_MUXNEG_PIN5             (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN5 Pin Position  */
    265. 

  265. #define ADC_INPUTCTRL_MUXNEG_PIN6             (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN6 Pin Position  */
    266. 

  266. #define ADC_INPUTCTRL_MUXNEG_PIN7             (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) ADC AIN7 Pin Position  */
    267. 

  267. #define ADC_INPUTCTRL_MUXNEG_GND              (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) Internal Ground Position  */
    268. 

  268. #define ADC_INPUTCTRL_MUXNEG_IOGND            (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) /**< (ADC_INPUTCTRL) I/O Ground Position  */
    269. 

  269. #define ADC_INPUTCTRL_INPUTSCAN_Pos           _U_(16)                                              /**< (ADC_INPUTCTRL) Number of Input Channels Included in Scan Position */
    270. 

  270. #define ADC_INPUTCTRL_INPUTSCAN_Msk           (_U_(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos)            /**< (ADC_INPUTCTRL) Number of Input Channels Included in Scan Mask */
    271. 

  271. #define ADC_INPUTCTRL_INPUTSCAN(value)        (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))
    272. 

  272. #define ADC_INPUTCTRL_INPUTOFFSET_Pos         _U_(20)                                              /**< (ADC_INPUTCTRL) Positive Mux Setting Offset Position */
    273. 

  273. #define ADC_INPUTCTRL_INPUTOFFSET_Msk         (_U_(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos)          /**< (ADC_INPUTCTRL) Positive Mux Setting Offset Mask */
    274. 

  274. #define ADC_INPUTCTRL_INPUTOFFSET(value)      (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))
    275. 

  275. #define ADC_INPUTCTRL_GAIN_Pos                _U_(24)                                              /**< (ADC_INPUTCTRL) Gain Factor Selection Position */
    276. 

  276. #define ADC_INPUTCTRL_GAIN_Msk                (_U_(0xF) << ADC_INPUTCTRL_GAIN_Pos)                 /**< (ADC_INPUTCTRL) Gain Factor Selection Mask */
    277. 

  277. #define ADC_INPUTCTRL_GAIN(value)             (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))
    278. 

  278. #define   ADC_INPUTCTRL_GAIN_1X_Val           _U_(0x0)                                             /**< (ADC_INPUTCTRL) 1x  */
    279. 

  279. #define   ADC_INPUTCTRL_GAIN_2X_Val           _U_(0x1)                                             /**< (ADC_INPUTCTRL) 2x  */
    280. 

  280. #define   ADC_INPUTCTRL_GAIN_4X_Val           _U_(0x2)                                             /**< (ADC_INPUTCTRL) 4x  */
    281. 

  281. #define   ADC_INPUTCTRL_GAIN_8X_Val           _U_(0x3)                                             /**< (ADC_INPUTCTRL) 8x  */
    282. 

  282. #define   ADC_INPUTCTRL_GAIN_16X_Val          _U_(0x4)                                             /**< (ADC_INPUTCTRL) 16x  */
    283. 

  283. #define   ADC_INPUTCTRL_GAIN_DIV2_Val         _U_(0xF)                                             /**< (ADC_INPUTCTRL) 1/2x  */
    284. 

  284. #define ADC_INPUTCTRL_GAIN_1X                 (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) /**< (ADC_INPUTCTRL) 1x Position  */
    285. 

  285. #define ADC_INPUTCTRL_GAIN_2X                 (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) /**< (ADC_INPUTCTRL) 2x Position  */
    286. 

  286. #define ADC_INPUTCTRL_GAIN_4X                 (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) /**< (ADC_INPUTCTRL) 4x Position  */
    287. 

  287. #define ADC_INPUTCTRL_GAIN_8X                 (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) /**< (ADC_INPUTCTRL) 8x Position  */
    288. 

  288. #define ADC_INPUTCTRL_GAIN_16X                (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) /**< (ADC_INPUTCTRL) 16x Position  */
    289. 

  289. #define ADC_INPUTCTRL_GAIN_DIV2               (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) /**< (ADC_INPUTCTRL) 1/2x Position  */
    290. 

  290. #define ADC_INPUTCTRL_Msk                     _U_(0x0FFF1F1F)                                      /**< (ADC_INPUTCTRL) Register Mask  */
    291. 

  291. 

  292. 

  293. /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
    294. 

  294. #define ADC_EVCTRL_RESETVALUE                 _U_(0x00)                                            /**<  (ADC_EVCTRL) Event Control  Reset Value */
    295. 

  295. 

  296. #define ADC_EVCTRL_STARTEI_Pos                _U_(0)                                               /**< (ADC_EVCTRL) Start Conversion Event In Position */
    297. 

  297. #define ADC_EVCTRL_STARTEI_Msk                (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)                 /**< (ADC_EVCTRL) Start Conversion Event In Mask */
    298. 

  298. #define ADC_EVCTRL_STARTEI(value)             (ADC_EVCTRL_STARTEI_Msk & ((value) << ADC_EVCTRL_STARTEI_Pos))
    299. 

  299. #define ADC_EVCTRL_SYNCEI_Pos                 _U_(1)                                               /**< (ADC_EVCTRL) Synchronization Event In Position */
    300. 

  300. #define ADC_EVCTRL_SYNCEI_Msk                 (_U_(0x1) << ADC_EVCTRL_SYNCEI_Pos)                  /**< (ADC_EVCTRL) Synchronization Event In Mask */
    301. 

  301. #define ADC_EVCTRL_SYNCEI(value)              (ADC_EVCTRL_SYNCEI_Msk & ((value) << ADC_EVCTRL_SYNCEI_Pos))
    302. 

  302. #define ADC_EVCTRL_RESRDYEO_Pos               _U_(4)                                               /**< (ADC_EVCTRL) Result Ready Event Out Position */
    303. 

  303. #define ADC_EVCTRL_RESRDYEO_Msk               (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)                /**< (ADC_EVCTRL) Result Ready Event Out Mask */
    304. 

  304. #define ADC_EVCTRL_RESRDYEO(value)            (ADC_EVCTRL_RESRDYEO_Msk & ((value) << ADC_EVCTRL_RESRDYEO_Pos))
    305. 

  305. #define ADC_EVCTRL_WINMONEO_Pos               _U_(5)                                               /**< (ADC_EVCTRL) Window Monitor Event Out Position */
    306. 

  306. #define ADC_EVCTRL_WINMONEO_Msk               (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)                /**< (ADC_EVCTRL) Window Monitor Event Out Mask */
    307. 

  307. #define ADC_EVCTRL_WINMONEO(value)            (ADC_EVCTRL_WINMONEO_Msk & ((value) << ADC_EVCTRL_WINMONEO_Pos))
    308. 

  308. #define ADC_EVCTRL_Msk                        _U_(0x33)                                            /**< (ADC_EVCTRL) Register Mask  */
    309. 

  309. 

  310. 

  311. /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
    312. 

  312. #define ADC_INTENCLR_RESETVALUE               _U_(0x00)                                            /**<  (ADC_INTENCLR) Interrupt Enable Clear  Reset Value */
    313. 

  313. 

  314. #define ADC_INTENCLR_RESRDY_Pos               _U_(0)                                               /**< (ADC_INTENCLR) Result Ready Interrupt Enable Position */
    315. 

  315. #define ADC_INTENCLR_RESRDY_Msk               (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)                /**< (ADC_INTENCLR) Result Ready Interrupt Enable Mask */
    316. 

  316. #define ADC_INTENCLR_RESRDY(value)            (ADC_INTENCLR_RESRDY_Msk & ((value) << ADC_INTENCLR_RESRDY_Pos))
    317. 

  317. #define ADC_INTENCLR_OVERRUN_Pos              _U_(1)                                               /**< (ADC_INTENCLR) Overrun Interrupt Enable Position */
    318. 

  318. #define ADC_INTENCLR_OVERRUN_Msk              (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)               /**< (ADC_INTENCLR) Overrun Interrupt Enable Mask */
    319. 

  319. #define ADC_INTENCLR_OVERRUN(value)           (ADC_INTENCLR_OVERRUN_Msk & ((value) << ADC_INTENCLR_OVERRUN_Pos))
    320. 

  320. #define ADC_INTENCLR_WINMON_Pos               _U_(2)                                               /**< (ADC_INTENCLR) Window Monitor Interrupt Enable Position */
    321. 

  321. #define ADC_INTENCLR_WINMON_Msk               (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)                /**< (ADC_INTENCLR) Window Monitor Interrupt Enable Mask */
    322. 

  322. #define ADC_INTENCLR_WINMON(value)            (ADC_INTENCLR_WINMON_Msk & ((value) << ADC_INTENCLR_WINMON_Pos))
    323. 

  323. #define ADC_INTENCLR_SYNCRDY_Pos              _U_(3)                                               /**< (ADC_INTENCLR) Synchronization Ready Interrupt Enable Position */
    324. 

  324. #define ADC_INTENCLR_SYNCRDY_Msk              (_U_(0x1) << ADC_INTENCLR_SYNCRDY_Pos)               /**< (ADC_INTENCLR) Synchronization Ready Interrupt Enable Mask */
    325. 

  325. #define ADC_INTENCLR_SYNCRDY(value)           (ADC_INTENCLR_SYNCRDY_Msk & ((value) << ADC_INTENCLR_SYNCRDY_Pos))
    326. 

  326. #define ADC_INTENCLR_Msk                      _U_(0x0F)                                            /**< (ADC_INTENCLR) Register Mask  */
    327. 

  327. 

  328. 

  329. /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
    330. 

  330. #define ADC_INTENSET_RESETVALUE               _U_(0x00)                                            /**<  (ADC_INTENSET) Interrupt Enable Set  Reset Value */
    331. 

  331. 

  332. #define ADC_INTENSET_RESRDY_Pos               _U_(0)                                               /**< (ADC_INTENSET) Result Ready Interrupt Enable Position */
    333. 

  333. #define ADC_INTENSET_RESRDY_Msk               (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)                /**< (ADC_INTENSET) Result Ready Interrupt Enable Mask */
    334. 

  334. #define ADC_INTENSET_RESRDY(value)            (ADC_INTENSET_RESRDY_Msk & ((value) << ADC_INTENSET_RESRDY_Pos))
    335. 

  335. #define ADC_INTENSET_OVERRUN_Pos              _U_(1)                                               /**< (ADC_INTENSET) Overrun Interrupt Enable Position */
    336. 

  336. #define ADC_INTENSET_OVERRUN_Msk              (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)               /**< (ADC_INTENSET) Overrun Interrupt Enable Mask */
    337. 

  337. #define ADC_INTENSET_OVERRUN(value)           (ADC_INTENSET_OVERRUN_Msk & ((value) << ADC_INTENSET_OVERRUN_Pos))
    338. 

  338. #define ADC_INTENSET_WINMON_Pos               _U_(2)                                               /**< (ADC_INTENSET) Window Monitor Interrupt Enable Position */
    339. 

  339. #define ADC_INTENSET_WINMON_Msk               (_U_(0x1) << ADC_INTENSET_WINMON_Pos)                /**< (ADC_INTENSET) Window Monitor Interrupt Enable Mask */
    340. 

  340. #define ADC_INTENSET_WINMON(value)            (ADC_INTENSET_WINMON_Msk & ((value) << ADC_INTENSET_WINMON_Pos))
    341. 

  341. #define ADC_INTENSET_SYNCRDY_Pos              _U_(3)                                               /**< (ADC_INTENSET) Synchronization Ready Interrupt Enable Position */
    342. 

  342. #define ADC_INTENSET_SYNCRDY_Msk              (_U_(0x1) << ADC_INTENSET_SYNCRDY_Pos)               /**< (ADC_INTENSET) Synchronization Ready Interrupt Enable Mask */
    343. 

  343. #define ADC_INTENSET_SYNCRDY(value)           (ADC_INTENSET_SYNCRDY_Msk & ((value) << ADC_INTENSET_SYNCRDY_Pos))
    344. 

  344. #define ADC_INTENSET_Msk                      _U_(0x0F)                                            /**< (ADC_INTENSET) Register Mask  */
    345. 

  345. 

  346. 

  347. /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
    348. 

  348. #define ADC_INTFLAG_RESETVALUE                _U_(0x00)                                            /**<  (ADC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    349. 

  349. 

  350. #define ADC_INTFLAG_RESRDY_Pos                _U_(0)                                               /**< (ADC_INTFLAG) Result Ready Position */
    351. 

  351. #define ADC_INTFLAG_RESRDY_Msk                (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)                 /**< (ADC_INTFLAG) Result Ready Mask */
    352. 

  352. #define ADC_INTFLAG_RESRDY(value)             (ADC_INTFLAG_RESRDY_Msk & ((value) << ADC_INTFLAG_RESRDY_Pos))
    353. 

  353. #define ADC_INTFLAG_OVERRUN_Pos               _U_(1)                                               /**< (ADC_INTFLAG) Overrun Position */
    354. 

  354. #define ADC_INTFLAG_OVERRUN_Msk               (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)                /**< (ADC_INTFLAG) Overrun Mask */
    355. 

  355. #define ADC_INTFLAG_OVERRUN(value)            (ADC_INTFLAG_OVERRUN_Msk & ((value) << ADC_INTFLAG_OVERRUN_Pos))
    356. 

  356. #define ADC_INTFLAG_WINMON_Pos                _U_(2)                                               /**< (ADC_INTFLAG) Window Monitor Position */
    357. 

  357. #define ADC_INTFLAG_WINMON_Msk                (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)                 /**< (ADC_INTFLAG) Window Monitor Mask */
    358. 

  358. #define ADC_INTFLAG_WINMON(value)             (ADC_INTFLAG_WINMON_Msk & ((value) << ADC_INTFLAG_WINMON_Pos))
    359. 

  359. #define ADC_INTFLAG_SYNCRDY_Pos               _U_(3)                                               /**< (ADC_INTFLAG) Synchronization Ready Position */
    360. 

  360. #define ADC_INTFLAG_SYNCRDY_Msk               (_U_(0x1) << ADC_INTFLAG_SYNCRDY_Pos)                /**< (ADC_INTFLAG) Synchronization Ready Mask */
    361. 

  361. #define ADC_INTFLAG_SYNCRDY(value)            (ADC_INTFLAG_SYNCRDY_Msk & ((value) << ADC_INTFLAG_SYNCRDY_Pos))
    362. 

  362. #define ADC_INTFLAG_Msk                       _U_(0x0F)                                            /**< (ADC_INTFLAG) Register Mask  */
    363. 

  363. 

  364. 

  365. /* -------- ADC_STATUS : (ADC Offset: 0x19) ( R/ 8) Status -------- */
    366. 

  366. #define ADC_STATUS_RESETVALUE                 _U_(0x00)                                            /**<  (ADC_STATUS) Status  Reset Value */
    367. 

  367. 

  368. #define ADC_STATUS_SYNCBUSY_Pos               _U_(7)                                               /**< (ADC_STATUS) Synchronization Busy Position */
    369. 

  369. #define ADC_STATUS_SYNCBUSY_Msk               (_U_(0x1) << ADC_STATUS_SYNCBUSY_Pos)                /**< (ADC_STATUS) Synchronization Busy Mask */
    370. 

  370. #define ADC_STATUS_SYNCBUSY(value)            (ADC_STATUS_SYNCBUSY_Msk & ((value) << ADC_STATUS_SYNCBUSY_Pos))
    371. 

  371. #define ADC_STATUS_Msk                        _U_(0x80)                                            /**< (ADC_STATUS) Register Mask  */
    372. 

  372. 

  373. 

  374. /* -------- ADC_RESULT : (ADC Offset: 0x1A) ( R/ 16) Result -------- */
    375. 

  375. #define ADC_RESULT_RESETVALUE                 _U_(0x00)                                            /**<  (ADC_RESULT) Result  Reset Value */
    376. 

  376. 

  377. #define ADC_RESULT_RESULT_Pos                 _U_(0)                                               /**< (ADC_RESULT) Result Conversion Value Position */
    378. 

  378. #define ADC_RESULT_RESULT_Msk                 (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)               /**< (ADC_RESULT) Result Conversion Value Mask */
    379. 

  379. #define ADC_RESULT_RESULT(value)              (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
    380. 

  380. #define ADC_RESULT_Msk                        _U_(0xFFFF)                                          /**< (ADC_RESULT) Register Mask  */
    381. 

  381. 

  382. 

  383. /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
    384. 

  384. #define ADC_WINLT_RESETVALUE                  _U_(0x00)                                            /**<  (ADC_WINLT) Window Monitor Lower Threshold  Reset Value */
    385. 

  385. 

  386. #define ADC_WINLT_WINLT_Pos                   _U_(0)                                               /**< (ADC_WINLT) Window Lower Threshold Position */
    387. 

  387. #define ADC_WINLT_WINLT_Msk                   (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)                 /**< (ADC_WINLT) Window Lower Threshold Mask */
    388. 

  388. #define ADC_WINLT_WINLT(value)                (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
    389. 

  389. #define ADC_WINLT_Msk                         _U_(0xFFFF)                                          /**< (ADC_WINLT) Register Mask  */
    390. 

  390. 

  391. 

  392. /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
    393. 

  393. #define ADC_WINUT_RESETVALUE                  _U_(0x00)                                            /**<  (ADC_WINUT) Window Monitor Upper Threshold  Reset Value */
    394. 

  394. 

  395. #define ADC_WINUT_WINUT_Pos                   _U_(0)                                               /**< (ADC_WINUT) Window Upper Threshold Position */
    396. 

  396. #define ADC_WINUT_WINUT_Msk                   (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)                 /**< (ADC_WINUT) Window Upper Threshold Mask */
    397. 

  397. #define ADC_WINUT_WINUT(value)                (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
    398. 

  398. #define ADC_WINUT_Msk                         _U_(0xFFFF)                                          /**< (ADC_WINUT) Register Mask  */
    399. 

  399. 

  400. 

  401. /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
    402. 

  402. #define ADC_GAINCORR_RESETVALUE               _U_(0x00)                                            /**<  (ADC_GAINCORR) Gain Correction  Reset Value */
    403. 

  403. 

  404. #define ADC_GAINCORR_GAINCORR_Pos             _U_(0)                                               /**< (ADC_GAINCORR) Gain Correction Value Position */
    405. 

  405. #define ADC_GAINCORR_GAINCORR_Msk             (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)            /**< (ADC_GAINCORR) Gain Correction Value Mask */
    406. 

  406. #define ADC_GAINCORR_GAINCORR(value)          (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
    407. 

  407. #define ADC_GAINCORR_Msk                      _U_(0x0FFF)                                          /**< (ADC_GAINCORR) Register Mask  */
    408. 

  408. 

  409. 

  410. /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
    411. 

  411. #define ADC_OFFSETCORR_RESETVALUE             _U_(0x00)                                            /**<  (ADC_OFFSETCORR) Offset Correction  Reset Value */
    412. 

  412. 

  413. #define ADC_OFFSETCORR_OFFSETCORR_Pos         _U_(0)                                               /**< (ADC_OFFSETCORR) Offset Correction Value Position */
    414. 

  414. #define ADC_OFFSETCORR_OFFSETCORR_Msk         (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)        /**< (ADC_OFFSETCORR) Offset Correction Value Mask */
    415. 

  415. #define ADC_OFFSETCORR_OFFSETCORR(value)      (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
    416. 

  416. #define ADC_OFFSETCORR_Msk                    _U_(0x0FFF)                                          /**< (ADC_OFFSETCORR) Register Mask  */
    417. 

  417. 

  418. 

  419. /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
    420. 

  420. #define ADC_CALIB_RESETVALUE                  _U_(0x00)                                            /**<  (ADC_CALIB) Calibration  Reset Value */
    421. 

  421. 

  422. #define ADC_CALIB_LINEARITY_CAL_Pos           _U_(0)                                               /**< (ADC_CALIB) Linearity Calibration Value Position */
    423. 

  423. #define ADC_CALIB_LINEARITY_CAL_Msk           (_U_(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos)           /**< (ADC_CALIB) Linearity Calibration Value Mask */
    424. 

  424. #define ADC_CALIB_LINEARITY_CAL(value)        (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))
    425. 

  425. #define ADC_CALIB_BIAS_CAL_Pos                _U_(8)                                               /**< (ADC_CALIB) Bias Calibration Value Position */
    426. 

  426. #define ADC_CALIB_BIAS_CAL_Msk                (_U_(0x7) << ADC_CALIB_BIAS_CAL_Pos)                 /**< (ADC_CALIB) Bias Calibration Value Mask */
    427. 

  427. #define ADC_CALIB_BIAS_CAL(value)             (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))
    428. 

  428. #define ADC_CALIB_Msk                         _U_(0x07FF)                                          /**< (ADC_CALIB) Register Mask  */
    429. 

  429. 

  430. 

  431. /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
    432. 

  432. #define ADC_DBGCTRL_RESETVALUE                _U_(0x00)                                            /**<  (ADC_DBGCTRL) Debug Control  Reset Value */
    433. 

  433. 

  434. #define ADC_DBGCTRL_DBGRUN_Pos                _U_(0)                                               /**< (ADC_DBGCTRL) Debug Run Position */
    435. 

  435. #define ADC_DBGCTRL_DBGRUN_Msk                (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)                 /**< (ADC_DBGCTRL) Debug Run Mask */
    436. 

  436. #define ADC_DBGCTRL_DBGRUN(value)             (ADC_DBGCTRL_DBGRUN_Msk & ((value) << ADC_DBGCTRL_DBGRUN_Pos))
    437. 

  437. #define ADC_DBGCTRL_Msk                       _U_(0x01)                                            /**< (ADC_DBGCTRL) Register Mask  */
    438. 

  438. 

  439. 

  440. /** \brief ADC register offsets definitions */
    441. 

  441. #define ADC_CTRLA_REG_OFST             (0x00)              /**< (ADC_CTRLA) Control A Offset */
    442. 

  442. #define ADC_REFCTRL_REG_OFST           (0x01)              /**< (ADC_REFCTRL) Reference Control Offset */
    443. 

  443. #define ADC_AVGCTRL_REG_OFST           (0x02)              /**< (ADC_AVGCTRL) Average Control Offset */
    444. 

  444. #define ADC_SAMPCTRL_REG_OFST          (0x03)              /**< (ADC_SAMPCTRL) Sampling Time Control Offset */
    445. 

  445. #define ADC_CTRLB_REG_OFST             (0x04)              /**< (ADC_CTRLB) Control B Offset */
    446. 

  446. #define ADC_WINCTRL_REG_OFST           (0x08)              /**< (ADC_WINCTRL) Window Monitor Control Offset */
    447. 

  447. #define ADC_SWTRIG_REG_OFST            (0x0C)              /**< (ADC_SWTRIG) Software Trigger Offset */
    448. 

  448. #define ADC_INPUTCTRL_REG_OFST         (0x10)              /**< (ADC_INPUTCTRL) Input Control Offset */
    449. 

  449. #define ADC_EVCTRL_REG_OFST            (0x14)              /**< (ADC_EVCTRL) Event Control Offset */
    450. 

  450. #define ADC_INTENCLR_REG_OFST          (0x16)              /**< (ADC_INTENCLR) Interrupt Enable Clear Offset */
    451. 

  451. #define ADC_INTENSET_REG_OFST          (0x17)              /**< (ADC_INTENSET) Interrupt Enable Set Offset */
    452. 

  452. #define ADC_INTFLAG_REG_OFST           (0x18)              /**< (ADC_INTFLAG) Interrupt Flag Status and Clear Offset */
    453. 

  453. #define ADC_STATUS_REG_OFST            (0x19)              /**< (ADC_STATUS) Status Offset */
    454. 

  454. #define ADC_RESULT_REG_OFST            (0x1A)              /**< (ADC_RESULT) Result Offset */
    455. 

  455. #define ADC_WINLT_REG_OFST             (0x1C)              /**< (ADC_WINLT) Window Monitor Lower Threshold Offset */
    456. 

  456. #define ADC_WINUT_REG_OFST             (0x20)              /**< (ADC_WINUT) Window Monitor Upper Threshold Offset */
    457. 

  457. #define ADC_GAINCORR_REG_OFST          (0x24)              /**< (ADC_GAINCORR) Gain Correction Offset */
    458. 

  458. #define ADC_OFFSETCORR_REG_OFST        (0x26)              /**< (ADC_OFFSETCORR) Offset Correction Offset */
    459. 

  459. #define ADC_CALIB_REG_OFST             (0x28)              /**< (ADC_CALIB) Calibration Offset */
    460. 

  460. #define ADC_DBGCTRL_REG_OFST           (0x2A)              /**< (ADC_DBGCTRL) Debug Control Offset */
    461. 

  461. 

  462. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    463. 

  463. /** \brief ADC register API structure */
    464. 

  464. typedef struct
    465. 

  465. {  /* Analog Digital Converter */
    466. 

  466.   __IO  uint8_t                        ADC_CTRLA;          /**< Offset: 0x00 (R/W  8) Control A */
    467. 

  467.   __IO  uint8_t                        ADC_REFCTRL;        /**< Offset: 0x01 (R/W  8) Reference Control */
    468. 

  468.   __IO  uint8_t                        ADC_AVGCTRL;        /**< Offset: 0x02 (R/W  8) Average Control */
    469. 

  469.   __IO  uint8_t                        ADC_SAMPCTRL;       /**< Offset: 0x03 (R/W  8) Sampling Time Control */
    470. 

  470.   __IO  uint16_t                       ADC_CTRLB;          /**< Offset: 0x04 (R/W  16) Control B */
    471. 

  471.   __I   uint8_t                        Reserved1[0x02];
    472. 

  472.   __IO  uint8_t                        ADC_WINCTRL;        /**< Offset: 0x08 (R/W  8) Window Monitor Control */
    473. 

  473.   __I   uint8_t                        Reserved2[0x03];
    474. 

  474.   __IO  uint8_t                        ADC_SWTRIG;         /**< Offset: 0x0C (R/W  8) Software Trigger */
    475. 

  475.   __I   uint8_t                        Reserved3[0x03];
    476. 

  476.   __IO  uint32_t                       ADC_INPUTCTRL;      /**< Offset: 0x10 (R/W  32) Input Control */
    477. 

  477.   __IO  uint8_t                        ADC_EVCTRL;         /**< Offset: 0x14 (R/W  8) Event Control */
    478. 

  478.   __I   uint8_t                        Reserved4[0x01];
    479. 

  479.   __IO  uint8_t                        ADC_INTENCLR;       /**< Offset: 0x16 (R/W  8) Interrupt Enable Clear */
    480. 

  480.   __IO  uint8_t                        ADC_INTENSET;       /**< Offset: 0x17 (R/W  8) Interrupt Enable Set */
    481. 

  481.   __IO  uint8_t                        ADC_INTFLAG;        /**< Offset: 0x18 (R/W  8) Interrupt Flag Status and Clear */
    482. 

  482.   __I   uint8_t                        ADC_STATUS;         /**< Offset: 0x19 (R/   8) Status */
    483. 

  483.   __I   uint16_t                       ADC_RESULT;         /**< Offset: 0x1A (R/   16) Result */
    484. 

  484.   __IO  uint16_t                       ADC_WINLT;          /**< Offset: 0x1C (R/W  16) Window Monitor Lower Threshold */
    485. 

  485.   __I   uint8_t                        Reserved5[0x02];
    486. 

  486.   __IO  uint16_t                       ADC_WINUT;          /**< Offset: 0x20 (R/W  16) Window Monitor Upper Threshold */
    487. 

  487.   __I   uint8_t                        Reserved6[0x02];
    488. 

  488.   __IO  uint16_t                       ADC_GAINCORR;       /**< Offset: 0x24 (R/W  16) Gain Correction */
    489. 

  489.   __IO  uint16_t                       ADC_OFFSETCORR;     /**< Offset: 0x26 (R/W  16) Offset Correction */
    490. 

  490.   __IO  uint16_t                       ADC_CALIB;          /**< Offset: 0x28 (R/W  16) Calibration */
    491. 

  491.   __IO  uint8_t                        ADC_DBGCTRL;        /**< Offset: 0x2A (R/W  8) Debug Control */
    492. 

  492. } adc_registers_t;
    493. 

  493. 

  494. 

  495. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    496. 

  496. #endif /* _SAMD21_ADC_COMPONENT_H_ */
    497.