Главная Обзор Помощь
Вход
FlyerInk
/
sdk-csp-atsamd21
зеркало из https://github-proxy.rt-thread.io/FlyerInk/sdk-csp-atsamd21.git
2
0
Ответвить 0
Файлы Задачи 0 Вики
Ветка: master
Ветки Метки
sdk-csp-atsamd2...
/
libraries
/
include
/
component
/
dsu.h

dsu.h 32 KB
Постоянная ссылка История Исходник

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350 
  1. /**
    2. 

  2.  * \brief Component description for DSU
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_DSU_COMPONENT_H_
    25. 

  25. #define _SAMD21_DSU_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR DSU                                          */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- DSU_CTRL : (DSU Offset: 0x00) ( /W 8) Control -------- */
    32. 

  32. #define DSU_CTRL_RESETVALUE                   _U_(0x00)                                            /**<  (DSU_CTRL) Control  Reset Value */
    33. 

  33. 

  34. #define DSU_CTRL_SWRST_Pos                    _U_(0)                                               /**< (DSU_CTRL) Software Reset Position */
    35. 

  35. #define DSU_CTRL_SWRST_Msk                    (_U_(0x1) << DSU_CTRL_SWRST_Pos)                     /**< (DSU_CTRL) Software Reset Mask */
    36. 

  36. #define DSU_CTRL_SWRST(value)                 (DSU_CTRL_SWRST_Msk & ((value) << DSU_CTRL_SWRST_Pos))
    37. 

  37. #define DSU_CTRL_CRC_Pos                      _U_(2)                                               /**< (DSU_CTRL) 32-bit Cyclic Redundancy Check Position */
    38. 

  38. #define DSU_CTRL_CRC_Msk                      (_U_(0x1) << DSU_CTRL_CRC_Pos)                       /**< (DSU_CTRL) 32-bit Cyclic Redundancy Check Mask */
    39. 

  39. #define DSU_CTRL_CRC(value)                   (DSU_CTRL_CRC_Msk & ((value) << DSU_CTRL_CRC_Pos))  
    40. 

  40. #define DSU_CTRL_MBIST_Pos                    _U_(3)                                               /**< (DSU_CTRL) Memory Built-In Self-Test Position */
    41. 

  41. #define DSU_CTRL_MBIST_Msk                    (_U_(0x1) << DSU_CTRL_MBIST_Pos)                     /**< (DSU_CTRL) Memory Built-In Self-Test Mask */
    42. 

  42. #define DSU_CTRL_MBIST(value)                 (DSU_CTRL_MBIST_Msk & ((value) << DSU_CTRL_MBIST_Pos))
    43. 

  43. #define DSU_CTRL_CE_Pos                       _U_(4)                                               /**< (DSU_CTRL) Chip Erase Position */
    44. 

  44. #define DSU_CTRL_CE_Msk                       (_U_(0x1) << DSU_CTRL_CE_Pos)                        /**< (DSU_CTRL) Chip Erase Mask */
    45. 

  45. #define DSU_CTRL_CE(value)                    (DSU_CTRL_CE_Msk & ((value) << DSU_CTRL_CE_Pos))    
    46. 

  46. #define DSU_CTRL_Msk                          _U_(0x1D)                                            /**< (DSU_CTRL) Register Mask  */
    47. 

  47. 

  48. 

  49. /* -------- DSU_STATUSA : (DSU Offset: 0x01) (R/W 8) Status A -------- */
    50. 

  50. #define DSU_STATUSA_RESETVALUE                _U_(0x00)                                            /**<  (DSU_STATUSA) Status A  Reset Value */
    51. 

  51. 

  52. #define DSU_STATUSA_DONE_Pos                  _U_(0)                                               /**< (DSU_STATUSA) Done Position */
    53. 

  53. #define DSU_STATUSA_DONE_Msk                  (_U_(0x1) << DSU_STATUSA_DONE_Pos)                   /**< (DSU_STATUSA) Done Mask */
    54. 

  54. #define DSU_STATUSA_DONE(value)               (DSU_STATUSA_DONE_Msk & ((value) << DSU_STATUSA_DONE_Pos))
    55. 

  55. #define DSU_STATUSA_CRSTEXT_Pos               _U_(1)                                               /**< (DSU_STATUSA) CPU Reset Phase Extension Position */
    56. 

  56. #define DSU_STATUSA_CRSTEXT_Msk               (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)                /**< (DSU_STATUSA) CPU Reset Phase Extension Mask */
    57. 

  57. #define DSU_STATUSA_CRSTEXT(value)            (DSU_STATUSA_CRSTEXT_Msk & ((value) << DSU_STATUSA_CRSTEXT_Pos))
    58. 

  58. #define DSU_STATUSA_BERR_Pos                  _U_(2)                                               /**< (DSU_STATUSA) Bus Error Position */
    59. 

  59. #define DSU_STATUSA_BERR_Msk                  (_U_(0x1) << DSU_STATUSA_BERR_Pos)                   /**< (DSU_STATUSA) Bus Error Mask */
    60. 

  60. #define DSU_STATUSA_BERR(value)               (DSU_STATUSA_BERR_Msk & ((value) << DSU_STATUSA_BERR_Pos))
    61. 

  61. #define DSU_STATUSA_FAIL_Pos                  _U_(3)                                               /**< (DSU_STATUSA) Failure Position */
    62. 

  62. #define DSU_STATUSA_FAIL_Msk                  (_U_(0x1) << DSU_STATUSA_FAIL_Pos)                   /**< (DSU_STATUSA) Failure Mask */
    63. 

  63. #define DSU_STATUSA_FAIL(value)               (DSU_STATUSA_FAIL_Msk & ((value) << DSU_STATUSA_FAIL_Pos))
    64. 

  64. #define DSU_STATUSA_PERR_Pos                  _U_(4)                                               /**< (DSU_STATUSA) Protection Error Position */
    65. 

  65. #define DSU_STATUSA_PERR_Msk                  (_U_(0x1) << DSU_STATUSA_PERR_Pos)                   /**< (DSU_STATUSA) Protection Error Mask */
    66. 

  66. #define DSU_STATUSA_PERR(value)               (DSU_STATUSA_PERR_Msk & ((value) << DSU_STATUSA_PERR_Pos))
    67. 

  67. #define DSU_STATUSA_Msk                       _U_(0x1F)                                            /**< (DSU_STATUSA) Register Mask  */
    68. 

  68. 

  69. 

  70. /* -------- DSU_STATUSB : (DSU Offset: 0x02) ( R/ 8) Status B -------- */
    71. 

  71. #define DSU_STATUSB_RESETVALUE                _U_(0x10)                                            /**<  (DSU_STATUSB) Status B  Reset Value */
    72. 

  72. 

  73. #define DSU_STATUSB_PROT_Pos                  _U_(0)                                               /**< (DSU_STATUSB) Protected Position */
    74. 

  74. #define DSU_STATUSB_PROT_Msk                  (_U_(0x1) << DSU_STATUSB_PROT_Pos)                   /**< (DSU_STATUSB) Protected Mask */
    75. 

  75. #define DSU_STATUSB_PROT(value)               (DSU_STATUSB_PROT_Msk & ((value) << DSU_STATUSB_PROT_Pos))
    76. 

  76. #define DSU_STATUSB_DBGPRES_Pos               _U_(1)                                               /**< (DSU_STATUSB) Debugger Present Position */
    77. 

  77. #define DSU_STATUSB_DBGPRES_Msk               (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)                /**< (DSU_STATUSB) Debugger Present Mask */
    78. 

  78. #define DSU_STATUSB_DBGPRES(value)            (DSU_STATUSB_DBGPRES_Msk & ((value) << DSU_STATUSB_DBGPRES_Pos))
    79. 

  79. #define DSU_STATUSB_DCCD0_Pos                 _U_(2)                                               /**< (DSU_STATUSB) Debug Communication Channel 0 Dirty Position */
    80. 

  80. #define DSU_STATUSB_DCCD0_Msk                 (_U_(0x1) << DSU_STATUSB_DCCD0_Pos)                  /**< (DSU_STATUSB) Debug Communication Channel 0 Dirty Mask */
    81. 

  81. #define DSU_STATUSB_DCCD0(value)              (DSU_STATUSB_DCCD0_Msk & ((value) << DSU_STATUSB_DCCD0_Pos))
    82. 

  82. #define DSU_STATUSB_DCCD1_Pos                 _U_(3)                                               /**< (DSU_STATUSB) Debug Communication Channel 1 Dirty Position */
    83. 

  83. #define DSU_STATUSB_DCCD1_Msk                 (_U_(0x1) << DSU_STATUSB_DCCD1_Pos)                  /**< (DSU_STATUSB) Debug Communication Channel 1 Dirty Mask */
    84. 

  84. #define DSU_STATUSB_DCCD1(value)              (DSU_STATUSB_DCCD1_Msk & ((value) << DSU_STATUSB_DCCD1_Pos))
    85. 

  85. #define DSU_STATUSB_HPE_Pos                   _U_(4)                                               /**< (DSU_STATUSB) Hot-Plugging Enable Position */
    86. 

  86. #define DSU_STATUSB_HPE_Msk                   (_U_(0x1) << DSU_STATUSB_HPE_Pos)                    /**< (DSU_STATUSB) Hot-Plugging Enable Mask */
    87. 

  87. #define DSU_STATUSB_HPE(value)                (DSU_STATUSB_HPE_Msk & ((value) << DSU_STATUSB_HPE_Pos))
    88. 

  88. #define DSU_STATUSB_Msk                       _U_(0x1F)                                            /**< (DSU_STATUSB) Register Mask  */
    89. 

  89. 

  90. #define DSU_STATUSB_DCCD_Pos                  _U_(2)                                               /**< (DSU_STATUSB Position) Debug Communication Channel x Dirty */
    91. 

  91. #define DSU_STATUSB_DCCD_Msk                  (_U_(0x3) << DSU_STATUSB_DCCD_Pos)                   /**< (DSU_STATUSB Mask) DCCD */
    92. 

  92. #define DSU_STATUSB_DCCD(value)               (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) 
    93. 

  93. 

  94. /* -------- DSU_ADDR : (DSU Offset: 0x04) (R/W 32) Address -------- */
    95. 

  95. #define DSU_ADDR_RESETVALUE                   _U_(0x00)                                            /**<  (DSU_ADDR) Address  Reset Value */
    96. 

  96. 

  97. #define DSU_ADDR_ADDR_Pos                     _U_(2)                                               /**< (DSU_ADDR) Address Position */
    98. 

  98. #define DSU_ADDR_ADDR_Msk                     (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)               /**< (DSU_ADDR) Address Mask */
    99. 

  99. #define DSU_ADDR_ADDR(value)                  (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
    100. 

  100. #define DSU_ADDR_Msk                          _U_(0xFFFFFFFC)                                      /**< (DSU_ADDR) Register Mask  */
    101. 

  101. 

  102. 

  103. /* -------- DSU_LENGTH : (DSU Offset: 0x08) (R/W 32) Length -------- */
    104. 

  104. #define DSU_LENGTH_RESETVALUE                 _U_(0x00)                                            /**<  (DSU_LENGTH) Length  Reset Value */
    105. 

  105. 

  106. #define DSU_LENGTH_LENGTH_Pos                 _U_(2)                                               /**< (DSU_LENGTH) Length Position */
    107. 

  107. #define DSU_LENGTH_LENGTH_Msk                 (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)           /**< (DSU_LENGTH) Length Mask */
    108. 

  108. #define DSU_LENGTH_LENGTH(value)              (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
    109. 

  109. #define DSU_LENGTH_Msk                        _U_(0xFFFFFFFC)                                      /**< (DSU_LENGTH) Register Mask  */
    110. 

  110. 

  111. 

  112. /* -------- DSU_DATA : (DSU Offset: 0x0C) (R/W 32) Data -------- */
    113. 

  113. #define DSU_DATA_RESETVALUE                   _U_(0x00)                                            /**<  (DSU_DATA) Data  Reset Value */
    114. 

  114. 

  115. #define DSU_DATA_DATA_Pos                     _U_(0)                                               /**< (DSU_DATA) Data Position */
    116. 

  116. #define DSU_DATA_DATA_Msk                     (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)               /**< (DSU_DATA) Data Mask */
    117. 

  117. #define DSU_DATA_DATA(value)                  (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
    118. 

  118. #define DSU_DATA_Msk                          _U_(0xFFFFFFFF)                                      /**< (DSU_DATA) Register Mask  */
    119. 

  119. 

  120. 

  121. /* -------- DSU_DCC : (DSU Offset: 0x10) (R/W 32) Debug Communication Channel n -------- */
    122. 

  122. #define DSU_DCC_RESETVALUE                    _U_(0x00)                                            /**<  (DSU_DCC) Debug Communication Channel n  Reset Value */
    123. 

  123. 

  124. #define DSU_DCC_DATA_Pos                      _U_(0)                                               /**< (DSU_DCC) Data Position */
    125. 

  125. #define DSU_DCC_DATA_Msk                      (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)                /**< (DSU_DCC) Data Mask */
    126. 

  126. #define DSU_DCC_DATA(value)                   (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))  
    127. 

  127. #define DSU_DCC_Msk                           _U_(0xFFFFFFFF)                                      /**< (DSU_DCC) Register Mask  */
    128. 

  128. 

  129. 

  130. /* -------- DSU_DID : (DSU Offset: 0x18) ( R/ 32) Device Identification -------- */
    131. 

  131. #define DSU_DID_RESETVALUE                    _U_(0x10010300)                                      /**<  (DSU_DID) Device Identification  Reset Value */
    132. 

  132. 

  133. #define DSU_DID_DEVSEL_Pos                    _U_(0)                                               /**< (DSU_DID) Device Select Position */
    134. 

  134. #define DSU_DID_DEVSEL_Msk                    (_U_(0xFF) << DSU_DID_DEVSEL_Pos)                    /**< (DSU_DID) Device Select Mask */
    135. 

  135. #define DSU_DID_DEVSEL(value)                 (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
    136. 

  136. #define DSU_DID_REVISION_Pos                  _U_(8)                                               /**< (DSU_DID) Revision Position */
    137. 

  137. #define DSU_DID_REVISION_Msk                  (_U_(0xF) << DSU_DID_REVISION_Pos)                   /**< (DSU_DID) Revision Mask */
    138. 

  138. #define DSU_DID_REVISION(value)               (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
    139. 

  139. #define DSU_DID_DIE_Pos                       _U_(12)                                              /**< (DSU_DID) Die Identification Position */
    140. 

  140. #define DSU_DID_DIE_Msk                       (_U_(0xF) << DSU_DID_DIE_Pos)                        /**< (DSU_DID) Die Identification Mask */
    141. 

  141. #define DSU_DID_DIE(value)                    (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))    
    142. 

  142. #define DSU_DID_SERIES_Pos                    _U_(16)                                              /**< (DSU_DID) Product Series Position */
    143. 

  143. #define DSU_DID_SERIES_Msk                    (_U_(0x3F) << DSU_DID_SERIES_Pos)                    /**< (DSU_DID) Product Series Mask */
    144. 

  144. #define DSU_DID_SERIES(value)                 (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
    145. 

  145. #define DSU_DID_FAMILY_Pos                    _U_(23)                                              /**< (DSU_DID) Product Family Position */
    146. 

  146. #define DSU_DID_FAMILY_Msk                    (_U_(0x1F) << DSU_DID_FAMILY_Pos)                    /**< (DSU_DID) Product Family Mask */
    147. 

  147. #define DSU_DID_FAMILY(value)                 (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
    148. 

  148. #define DSU_DID_PROCESSOR_Pos                 _U_(28)                                              /**< (DSU_DID) Processor Position */
    149. 

  149. #define DSU_DID_PROCESSOR_Msk                 (_U_(0xF) << DSU_DID_PROCESSOR_Pos)                  /**< (DSU_DID) Processor Mask */
    150. 

  150. #define DSU_DID_PROCESSOR(value)              (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
    151. 

  151. #define DSU_DID_Msk                           _U_(0xFFBFFFFF)                                      /**< (DSU_DID) Register Mask  */
    152. 

  152. 

  153. 

  154. /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) ( R/ 32) CoreSight ROM Table Entry 0 -------- */
    155. 

  155. #define DSU_ENTRY0_RESETVALUE                 _U_(0x9F9FC002)                                      /**<  (DSU_ENTRY0) CoreSight ROM Table Entry 0  Reset Value */
    156. 

  156. 

  157. #define DSU_ENTRY0_EPRES_Pos                  _U_(0)                                               /**< (DSU_ENTRY0) Entry Present Position */
    158. 

  158. #define DSU_ENTRY0_EPRES_Msk                  (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)                   /**< (DSU_ENTRY0) Entry Present Mask */
    159. 

  159. #define DSU_ENTRY0_EPRES(value)               (DSU_ENTRY0_EPRES_Msk & ((value) << DSU_ENTRY0_EPRES_Pos))
    160. 

  160. #define DSU_ENTRY0_FMT_Pos                    _U_(1)                                               /**< (DSU_ENTRY0) Format Position */
    161. 

  161. #define DSU_ENTRY0_FMT_Msk                    (_U_(0x1) << DSU_ENTRY0_FMT_Pos)                     /**< (DSU_ENTRY0) Format Mask */
    162. 

  162. #define DSU_ENTRY0_FMT(value)                 (DSU_ENTRY0_FMT_Msk & ((value) << DSU_ENTRY0_FMT_Pos))
    163. 

  163. #define DSU_ENTRY0_ADDOFF_Pos                 _U_(12)                                              /**< (DSU_ENTRY0) Address Offset Position */
    164. 

  164. #define DSU_ENTRY0_ADDOFF_Msk                 (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)              /**< (DSU_ENTRY0) Address Offset Mask */
    165. 

  165. #define DSU_ENTRY0_ADDOFF(value)              (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
    166. 

  166. #define DSU_ENTRY0_Msk                        _U_(0xFFFFF003)                                      /**< (DSU_ENTRY0) Register Mask  */
    167. 

  167. 

  168. 

  169. /* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) ( R/ 32) CoreSight ROM Table Entry 1 -------- */
    170. 

  170. #define DSU_ENTRY1_RESETVALUE                 _U_(0x3002)                                          /**<  (DSU_ENTRY1) CoreSight ROM Table Entry 1  Reset Value */
    171. 

  171. 

  172. #define DSU_ENTRY1_Msk                        _U_(0x00000000)                                      /**< (DSU_ENTRY1) Register Mask  */
    173. 

  173. 

  174. 

  175. /* -------- DSU_END : (DSU Offset: 0x1008) ( R/ 32) CoreSight ROM Table End -------- */
    176. 

  176. #define DSU_END_RESETVALUE                    _U_(0x00)                                            /**<  (DSU_END) CoreSight ROM Table End  Reset Value */
    177. 

  177. 

  178. #define DSU_END_END_Pos                       _U_(0)                                               /**< (DSU_END) End Marker Position */
    179. 

  179. #define DSU_END_END_Msk                       (_U_(0xFFFFFFFF) << DSU_END_END_Pos)                 /**< (DSU_END) End Marker Mask */
    180. 

  180. #define DSU_END_END(value)                    (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))    
    181. 

  181. #define DSU_END_Msk                           _U_(0xFFFFFFFF)                                      /**< (DSU_END) Register Mask  */
    182. 

  182. 

  183. 

  184. /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) ( R/ 32) CoreSight ROM Table Memory Type -------- */
    185. 

  185. #define DSU_MEMTYPE_RESETVALUE                _U_(0x00)                                            /**<  (DSU_MEMTYPE) CoreSight ROM Table Memory Type  Reset Value */
    186. 

  186. 

  187. #define DSU_MEMTYPE_SMEMP_Pos                 _U_(0)                                               /**< (DSU_MEMTYPE) System Memory Present Position */
    188. 

  188. #define DSU_MEMTYPE_SMEMP_Msk                 (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)                  /**< (DSU_MEMTYPE) System Memory Present Mask */
    189. 

  189. #define DSU_MEMTYPE_SMEMP(value)              (DSU_MEMTYPE_SMEMP_Msk & ((value) << DSU_MEMTYPE_SMEMP_Pos))
    190. 

  190. #define DSU_MEMTYPE_Msk                       _U_(0x00000001)                                      /**< (DSU_MEMTYPE) Register Mask  */
    191. 

  191. 

  192. 

  193. /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) ( R/ 32) Peripheral Identification 4 -------- */
    194. 

  194. #define DSU_PID4_RESETVALUE                   _U_(0x00)                                            /**<  (DSU_PID4) Peripheral Identification 4  Reset Value */
    195. 

  195. 

  196. #define DSU_PID4_JEPCC_Pos                    _U_(0)                                               /**< (DSU_PID4) JEP-106 Continuation Code Position */
    197. 

  197. #define DSU_PID4_JEPCC_Msk                    (_U_(0xF) << DSU_PID4_JEPCC_Pos)                     /**< (DSU_PID4) JEP-106 Continuation Code Mask */
    198. 

  198. #define DSU_PID4_JEPCC(value)                 (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
    199. 

  199. #define DSU_PID4_FKBC_Pos                     _U_(4)                                               /**< (DSU_PID4) 4KB Count Position */
    200. 

  200. #define DSU_PID4_FKBC_Msk                     (_U_(0xF) << DSU_PID4_FKBC_Pos)                      /**< (DSU_PID4) 4KB Count Mask */
    201. 

  201. #define DSU_PID4_FKBC(value)                  (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
    202. 

  202. #define DSU_PID4_Msk                          _U_(0x000000FF)                                      /**< (DSU_PID4) Register Mask  */
    203. 

  203. 

  204. 

  205. /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) ( R/ 32) Peripheral Identification 0 -------- */
    206. 

  206. #define DSU_PID0_RESETVALUE                   _U_(0xD0)                                            /**<  (DSU_PID0) Peripheral Identification 0  Reset Value */
    207. 

  207. 

  208. #define DSU_PID0_PARTNBL_Pos                  _U_(0)                                               /**< (DSU_PID0) Part Number Low Position */
    209. 

  209. #define DSU_PID0_PARTNBL_Msk                  (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)                  /**< (DSU_PID0) Part Number Low Mask */
    210. 

  210. #define DSU_PID0_PARTNBL(value)               (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
    211. 

  211. #define DSU_PID0_Msk                          _U_(0x000000FF)                                      /**< (DSU_PID0) Register Mask  */
    212. 

  212. 

  213. 

  214. /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) ( R/ 32) Peripheral Identification 1 -------- */
    215. 

  215. #define DSU_PID1_RESETVALUE                   _U_(0xFC)                                            /**<  (DSU_PID1) Peripheral Identification 1  Reset Value */
    216. 

  216. 

  217. #define DSU_PID1_PARTNBH_Pos                  _U_(0)                                               /**< (DSU_PID1) Part Number High Position */
    218. 

  218. #define DSU_PID1_PARTNBH_Msk                  (_U_(0xF) << DSU_PID1_PARTNBH_Pos)                   /**< (DSU_PID1) Part Number High Mask */
    219. 

  219. #define DSU_PID1_PARTNBH(value)               (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
    220. 

  220. #define DSU_PID1_JEPIDCL_Pos                  _U_(4)                                               /**< (DSU_PID1) Low part of the JEP-106 Identity Code Position */
    221. 

  221. #define DSU_PID1_JEPIDCL_Msk                  (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)                   /**< (DSU_PID1) Low part of the JEP-106 Identity Code Mask */
    222. 

  222. #define DSU_PID1_JEPIDCL(value)               (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
    223. 

  223. #define DSU_PID1_Msk                          _U_(0x000000FF)                                      /**< (DSU_PID1) Register Mask  */
    224. 

  224. 

  225. 

  226. /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) ( R/ 32) Peripheral Identification 2 -------- */
    227. 

  227. #define DSU_PID2_RESETVALUE                   _U_(0x09)                                            /**<  (DSU_PID2) Peripheral Identification 2  Reset Value */
    228. 

  228. 

  229. #define DSU_PID2_JEPIDCH_Pos                  _U_(0)                                               /**< (DSU_PID2) JEP-106 Identity Code High Position */
    230. 

  230. #define DSU_PID2_JEPIDCH_Msk                  (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)                   /**< (DSU_PID2) JEP-106 Identity Code High Mask */
    231. 

  231. #define DSU_PID2_JEPIDCH(value)               (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
    232. 

  232. #define DSU_PID2_JEPU_Pos                     _U_(3)                                               /**< (DSU_PID2) JEP-106 Identity Code is used Position */
    233. 

  233. #define DSU_PID2_JEPU_Msk                     (_U_(0x1) << DSU_PID2_JEPU_Pos)                      /**< (DSU_PID2) JEP-106 Identity Code is used Mask */
    234. 

  234. #define DSU_PID2_JEPU(value)                  (DSU_PID2_JEPU_Msk & ((value) << DSU_PID2_JEPU_Pos))
    235. 

  235. #define DSU_PID2_REVISION_Pos                 _U_(4)                                               /**< (DSU_PID2) Revision Number Position */
    236. 

  236. #define DSU_PID2_REVISION_Msk                 (_U_(0xF) << DSU_PID2_REVISION_Pos)                  /**< (DSU_PID2) Revision Number Mask */
    237. 

  237. #define DSU_PID2_REVISION(value)              (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
    238. 

  238. #define DSU_PID2_Msk                          _U_(0x000000FF)                                      /**< (DSU_PID2) Register Mask  */
    239. 

  239. 

  240. 

  241. /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) ( R/ 32) Peripheral Identification 3 -------- */
    242. 

  242. #define DSU_PID3_RESETVALUE                   _U_(0x00)                                            /**<  (DSU_PID3) Peripheral Identification 3  Reset Value */
    243. 

  243. 

  244. #define DSU_PID3_CUSMOD_Pos                   _U_(0)                                               /**< (DSU_PID3) ARM CUSMOD Position */
    245. 

  245. #define DSU_PID3_CUSMOD_Msk                   (_U_(0xF) << DSU_PID3_CUSMOD_Pos)                    /**< (DSU_PID3) ARM CUSMOD Mask */
    246. 

  246. #define DSU_PID3_CUSMOD(value)                (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
    247. 

  247. #define DSU_PID3_REVAND_Pos                   _U_(4)                                               /**< (DSU_PID3) Revision Number Position */
    248. 

  248. #define DSU_PID3_REVAND_Msk                   (_U_(0xF) << DSU_PID3_REVAND_Pos)                    /**< (DSU_PID3) Revision Number Mask */
    249. 

  249. #define DSU_PID3_REVAND(value)                (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
    250. 

  250. #define DSU_PID3_Msk                          _U_(0x000000FF)                                      /**< (DSU_PID3) Register Mask  */
    251. 

  251. 

  252. 

  253. /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) ( R/ 32) Component Identification 0 -------- */
    254. 

  254. #define DSU_CID0_RESETVALUE                   _U_(0x0D)                                            /**<  (DSU_CID0) Component Identification 0  Reset Value */
    255. 

  255. 

  256. #define DSU_CID0_PREAMBLEB0_Pos               _U_(0)                                               /**< (DSU_CID0) Preamble Byte 0 Position */
    257. 

  257. #define DSU_CID0_PREAMBLEB0_Msk               (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)               /**< (DSU_CID0) Preamble Byte 0 Mask */
    258. 

  258. #define DSU_CID0_PREAMBLEB0(value)            (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
    259. 

  259. #define DSU_CID0_Msk                          _U_(0x000000FF)                                      /**< (DSU_CID0) Register Mask  */
    260. 

  260. 

  261. 

  262. /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) ( R/ 32) Component Identification 1 -------- */
    263. 

  263. #define DSU_CID1_RESETVALUE                   _U_(0x10)                                            /**<  (DSU_CID1) Component Identification 1  Reset Value */
    264. 

  264. 

  265. #define DSU_CID1_PREAMBLE_Pos                 _U_(0)                                               /**< (DSU_CID1) Preamble Position */
    266. 

  266. #define DSU_CID1_PREAMBLE_Msk                 (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)                  /**< (DSU_CID1) Preamble Mask */
    267. 

  267. #define DSU_CID1_PREAMBLE(value)              (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
    268. 

  268. #define DSU_CID1_CCLASS_Pos                   _U_(4)                                               /**< (DSU_CID1) Component Class Position */
    269. 

  269. #define DSU_CID1_CCLASS_Msk                   (_U_(0xF) << DSU_CID1_CCLASS_Pos)                    /**< (DSU_CID1) Component Class Mask */
    270. 

  270. #define DSU_CID1_CCLASS(value)                (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
    271. 

  271. #define DSU_CID1_Msk                          _U_(0x000000FF)                                      /**< (DSU_CID1) Register Mask  */
    272. 

  272. 

  273. 

  274. /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) ( R/ 32) Component Identification 2 -------- */
    275. 

  275. #define DSU_CID2_RESETVALUE                   _U_(0x05)                                            /**<  (DSU_CID2) Component Identification 2  Reset Value */
    276. 

  276. 

  277. #define DSU_CID2_PREAMBLEB2_Pos               _U_(0)                                               /**< (DSU_CID2) Preamble Byte 2 Position */
    278. 

  278. #define DSU_CID2_PREAMBLEB2_Msk               (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)               /**< (DSU_CID2) Preamble Byte 2 Mask */
    279. 

  279. #define DSU_CID2_PREAMBLEB2(value)            (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
    280. 

  280. #define DSU_CID2_Msk                          _U_(0x000000FF)                                      /**< (DSU_CID2) Register Mask  */
    281. 

  281. 

  282. 

  283. /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) ( R/ 32) Component Identification 3 -------- */
    284. 

  284. #define DSU_CID3_RESETVALUE                   _U_(0xB1)                                            /**<  (DSU_CID3) Component Identification 3  Reset Value */
    285. 

  285. 

  286. #define DSU_CID3_PREAMBLEB3_Pos               _U_(0)                                               /**< (DSU_CID3) Preamble Byte 3 Position */
    287. 

  287. #define DSU_CID3_PREAMBLEB3_Msk               (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)               /**< (DSU_CID3) Preamble Byte 3 Mask */
    288. 

  288. #define DSU_CID3_PREAMBLEB3(value)            (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
    289. 

  289. #define DSU_CID3_Msk                          _U_(0x000000FF)                                      /**< (DSU_CID3) Register Mask  */
    290. 

  290. 

  291. 

  292. /** \brief DSU register offsets definitions */
    293. 

  293. #define DSU_CTRL_REG_OFST              (0x00)              /**< (DSU_CTRL) Control Offset */
    294. 

  294. #define DSU_STATUSA_REG_OFST           (0x01)              /**< (DSU_STATUSA) Status A Offset */
    295. 

  295. #define DSU_STATUSB_REG_OFST           (0x02)              /**< (DSU_STATUSB) Status B Offset */
    296. 

  296. #define DSU_ADDR_REG_OFST              (0x04)              /**< (DSU_ADDR) Address Offset */
    297. 

  297. #define DSU_LENGTH_REG_OFST            (0x08)              /**< (DSU_LENGTH) Length Offset */
    298. 

  298. #define DSU_DATA_REG_OFST              (0x0C)              /**< (DSU_DATA) Data Offset */
    299. 

  299. #define DSU_DCC_REG_OFST               (0x10)              /**< (DSU_DCC) Debug Communication Channel n Offset */
    300. 

  300. #define DSU_DCC0_REG_OFST              (0x10)              /**< (DSU_DCC0) Debug Communication Channel n Offset */
    301. 

  301. #define DSU_DCC1_REG_OFST              (0x14)              /**< (DSU_DCC1) Debug Communication Channel n Offset */
    302. 

  302. #define DSU_DID_REG_OFST               (0x18)              /**< (DSU_DID) Device Identification Offset */
    303. 

  303. #define DSU_ENTRY0_REG_OFST            (0x1000)            /**< (DSU_ENTRY0) CoreSight ROM Table Entry 0 Offset */
    304. 

  304. #define DSU_ENTRY1_REG_OFST            (0x1004)            /**< (DSU_ENTRY1) CoreSight ROM Table Entry 1 Offset */
    305. 

  305. #define DSU_END_REG_OFST               (0x1008)            /**< (DSU_END) CoreSight ROM Table End Offset */
    306. 

  306. #define DSU_MEMTYPE_REG_OFST           (0x1FCC)            /**< (DSU_MEMTYPE) CoreSight ROM Table Memory Type Offset */
    307. 

  307. #define DSU_PID4_REG_OFST              (0x1FD0)            /**< (DSU_PID4) Peripheral Identification 4 Offset */
    308. 

  308. #define DSU_PID0_REG_OFST              (0x1FE0)            /**< (DSU_PID0) Peripheral Identification 0 Offset */
    309. 

  309. #define DSU_PID1_REG_OFST              (0x1FE4)            /**< (DSU_PID1) Peripheral Identification 1 Offset */
    310. 

  310. #define DSU_PID2_REG_OFST              (0x1FE8)            /**< (DSU_PID2) Peripheral Identification 2 Offset */
    311. 

  311. #define DSU_PID3_REG_OFST              (0x1FEC)            /**< (DSU_PID3) Peripheral Identification 3 Offset */
    312. 

  312. #define DSU_CID0_REG_OFST              (0x1FF0)            /**< (DSU_CID0) Component Identification 0 Offset */
    313. 

  313. #define DSU_CID1_REG_OFST              (0x1FF4)            /**< (DSU_CID1) Component Identification 1 Offset */
    314. 

  314. #define DSU_CID2_REG_OFST              (0x1FF8)            /**< (DSU_CID2) Component Identification 2 Offset */
    315. 

  315. #define DSU_CID3_REG_OFST              (0x1FFC)            /**< (DSU_CID3) Component Identification 3 Offset */
    316. 

  316. 

  317. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    318. 

  318. /** \brief DSU register API structure */
    319. 

  319. typedef struct
    320. 

  320. {  /* Device Service Unit */
    321. 

  321.   __O   uint8_t                        DSU_CTRL;           /**< Offset: 0x00 ( /W  8) Control */
    322. 

  322.   __IO  uint8_t                        DSU_STATUSA;        /**< Offset: 0x01 (R/W  8) Status A */
    323. 

  323.   __I   uint8_t                        DSU_STATUSB;        /**< Offset: 0x02 (R/   8) Status B */
    324. 

  324.   __I   uint8_t                        Reserved1[0x01];
    325. 

  325.   __IO  uint32_t                       DSU_ADDR;           /**< Offset: 0x04 (R/W  32) Address */
    326. 

  326.   __IO  uint32_t                       DSU_LENGTH;         /**< Offset: 0x08 (R/W  32) Length */
    327. 

  327.   __IO  uint32_t                       DSU_DATA;           /**< Offset: 0x0C (R/W  32) Data */
    328. 

  328.   __IO  uint32_t                       DSU_DCC[2];         /**< Offset: 0x10 (R/W  32) Debug Communication Channel n */
    329. 

  329.   __I   uint32_t                       DSU_DID;            /**< Offset: 0x18 (R/   32) Device Identification */
    330. 

  330.   __I   uint8_t                        Reserved2[0xFE4];
    331. 

  331.   __I   uint32_t                       DSU_ENTRY0;         /**< Offset: 0x1000 (R/   32) CoreSight ROM Table Entry 0 */
    332. 

  332.   __I   uint32_t                       DSU_ENTRY1;         /**< Offset: 0x1004 (R/   32) CoreSight ROM Table Entry 1 */
    333. 

  333.   __I   uint32_t                       DSU_END;            /**< Offset: 0x1008 (R/   32) CoreSight ROM Table End */
    334. 

  334.   __I   uint8_t                        Reserved3[0xFC0];
    335. 

  335.   __I   uint32_t                       DSU_MEMTYPE;        /**< Offset: 0x1FCC (R/   32) CoreSight ROM Table Memory Type */
    336. 

  336.   __I   uint32_t                       DSU_PID4;           /**< Offset: 0x1FD0 (R/   32) Peripheral Identification 4 */
    337. 

  337.   __I   uint8_t                        Reserved4[0x0C];
    338. 

  338.   __I   uint32_t                       DSU_PID0;           /**< Offset: 0x1FE0 (R/   32) Peripheral Identification 0 */
    339. 

  339.   __I   uint32_t                       DSU_PID1;           /**< Offset: 0x1FE4 (R/   32) Peripheral Identification 1 */
    340. 

  340.   __I   uint32_t                       DSU_PID2;           /**< Offset: 0x1FE8 (R/   32) Peripheral Identification 2 */
    341. 

  341.   __I   uint32_t                       DSU_PID3;           /**< Offset: 0x1FEC (R/   32) Peripheral Identification 3 */
    342. 

  342.   __I   uint32_t                       DSU_CID0;           /**< Offset: 0x1FF0 (R/   32) Component Identification 0 */
    343. 

  343.   __I   uint32_t                       DSU_CID1;           /**< Offset: 0x1FF4 (R/   32) Component Identification 1 */
    344. 

  344.   __I   uint32_t                       DSU_CID2;           /**< Offset: 0x1FF8 (R/   32) Component Identification 2 */
    345. 

  345.   __I   uint32_t                       DSU_CID3;           /**< Offset: 0x1FFC (R/   32) Component Identification 3 */
    346. 

  346. } dsu_registers_t;
    347. 

  347. 

  348. 

  349. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    350. 

  350. #endif /* _SAMD21_DSU_COMPONENT_H_ */
    351.