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eic.h

eic.h 68 KB
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  1. /**
    2. 

  2.  * \brief Component description for EIC
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_EIC_COMPONENT_H_
    25. 

  25. #define _SAMD21_EIC_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR EIC                                          */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
    32. 

  32. #define EIC_CTRL_RESETVALUE                   _U_(0x00)                                            /**<  (EIC_CTRL) Control  Reset Value */
    33. 

  33. 

  34. #define EIC_CTRL_SWRST_Pos                    _U_(0)                                               /**< (EIC_CTRL) Software Reset Position */
    35. 

  35. #define EIC_CTRL_SWRST_Msk                    (_U_(0x1) << EIC_CTRL_SWRST_Pos)                     /**< (EIC_CTRL) Software Reset Mask */
    36. 

  36. #define EIC_CTRL_SWRST(value)                 (EIC_CTRL_SWRST_Msk & ((value) << EIC_CTRL_SWRST_Pos))
    37. 

  37. #define EIC_CTRL_ENABLE_Pos                   _U_(1)                                               /**< (EIC_CTRL) Enable Position */
    38. 

  38. #define EIC_CTRL_ENABLE_Msk                   (_U_(0x1) << EIC_CTRL_ENABLE_Pos)                    /**< (EIC_CTRL) Enable Mask */
    39. 

  39. #define EIC_CTRL_ENABLE(value)                (EIC_CTRL_ENABLE_Msk & ((value) << EIC_CTRL_ENABLE_Pos))
    40. 

  40. #define EIC_CTRL_Msk                          _U_(0x03)                                            /**< (EIC_CTRL) Register Mask  */
    41. 

  41. 

  42. 

  43. /* -------- EIC_STATUS : (EIC Offset: 0x01) ( R/ 8) Status -------- */
    44. 

  44. #define EIC_STATUS_RESETVALUE                 _U_(0x00)                                            /**<  (EIC_STATUS) Status  Reset Value */
    45. 

  45. 

  46. #define EIC_STATUS_SYNCBUSY_Pos               _U_(7)                                               /**< (EIC_STATUS) Synchronization Busy Position */
    47. 

  47. #define EIC_STATUS_SYNCBUSY_Msk               (_U_(0x1) << EIC_STATUS_SYNCBUSY_Pos)                /**< (EIC_STATUS) Synchronization Busy Mask */
    48. 

  48. #define EIC_STATUS_SYNCBUSY(value)            (EIC_STATUS_SYNCBUSY_Msk & ((value) << EIC_STATUS_SYNCBUSY_Pos))
    49. 

  49. #define EIC_STATUS_Msk                        _U_(0x80)                                            /**< (EIC_STATUS) Register Mask  */
    50. 

  50. 

  51. 

  52. /* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
    53. 

  53. #define EIC_NMICTRL_RESETVALUE                _U_(0x00)                                            /**<  (EIC_NMICTRL) Non-Maskable Interrupt Control  Reset Value */
    54. 

  54. 

  55. #define EIC_NMICTRL_NMISENSE_Pos              _U_(0)                                               /**< (EIC_NMICTRL) Non-Maskable Interrupt Sense Position */
    56. 

  56. #define EIC_NMICTRL_NMISENSE_Msk              (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)               /**< (EIC_NMICTRL) Non-Maskable Interrupt Sense Mask */
    57. 

  57. #define EIC_NMICTRL_NMISENSE(value)           (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
    58. 

  58. #define   EIC_NMICTRL_NMISENSE_NONE_Val       _U_(0x0)                                             /**< (EIC_NMICTRL) No detection  */
    59. 

  59. #define   EIC_NMICTRL_NMISENSE_RISE_Val       _U_(0x1)                                             /**< (EIC_NMICTRL) Rising-edge detection  */
    60. 

  60. #define   EIC_NMICTRL_NMISENSE_FALL_Val       _U_(0x2)                                             /**< (EIC_NMICTRL) Falling-edge detection  */
    61. 

  61. #define   EIC_NMICTRL_NMISENSE_BOTH_Val       _U_(0x3)                                             /**< (EIC_NMICTRL) Both-edges detection  */
    62. 

  62. #define   EIC_NMICTRL_NMISENSE_HIGH_Val       _U_(0x4)                                             /**< (EIC_NMICTRL) High-level detection  */
    63. 

  63. #define   EIC_NMICTRL_NMISENSE_LOW_Val        _U_(0x5)                                             /**< (EIC_NMICTRL) Low-level detection  */
    64. 

  64. #define EIC_NMICTRL_NMISENSE_NONE             (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) No detection Position  */
    65. 

  65. #define EIC_NMICTRL_NMISENSE_RISE             (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Rising-edge detection Position  */
    66. 

  66. #define EIC_NMICTRL_NMISENSE_FALL             (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Falling-edge detection Position  */
    67. 

  67. #define EIC_NMICTRL_NMISENSE_BOTH             (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Both-edges detection Position  */
    68. 

  68. #define EIC_NMICTRL_NMISENSE_HIGH             (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) High-level detection Position  */
    69. 

  69. #define EIC_NMICTRL_NMISENSE_LOW              (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos) /**< (EIC_NMICTRL) Low-level detection Position  */
    70. 

  70. #define EIC_NMICTRL_NMIFILTEN_Pos             _U_(3)                                               /**< (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Position */
    71. 

  71. #define EIC_NMICTRL_NMIFILTEN_Msk             (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)              /**< (EIC_NMICTRL) Non-Maskable Interrupt Filter Enable Mask */
    72. 

  72. #define EIC_NMICTRL_NMIFILTEN(value)          (EIC_NMICTRL_NMIFILTEN_Msk & ((value) << EIC_NMICTRL_NMIFILTEN_Pos))
    73. 

  73. #define EIC_NMICTRL_Msk                       _U_(0x0F)                                            /**< (EIC_NMICTRL) Register Mask  */
    74. 

  74. 

  75. 

  76. /* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
    77. 

  77. #define EIC_NMIFLAG_RESETVALUE                _U_(0x00)                                            /**<  (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear  Reset Value */
    78. 

  78. 

  79. #define EIC_NMIFLAG_NMI_Pos                   _U_(0)                                               /**< (EIC_NMIFLAG) Non-Maskable Interrupt Position */
    80. 

  80. #define EIC_NMIFLAG_NMI_Msk                   (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)                    /**< (EIC_NMIFLAG) Non-Maskable Interrupt Mask */
    81. 

  81. #define EIC_NMIFLAG_NMI(value)                (EIC_NMIFLAG_NMI_Msk & ((value) << EIC_NMIFLAG_NMI_Pos))
    82. 

  82. #define EIC_NMIFLAG_Msk                       _U_(0x01)                                            /**< (EIC_NMIFLAG) Register Mask  */
    83. 

  83. 

  84. 

  85. /* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
    86. 

  86. #define EIC_EVCTRL_RESETVALUE                 _U_(0x00)                                            /**<  (EIC_EVCTRL) Event Control  Reset Value */
    87. 

  87. 

  88. #define EIC_EVCTRL_EXTINTEO0_Pos              _U_(0)                                               /**< (EIC_EVCTRL) External Interrupt 0 Event Output Enable Position */
    89. 

  89. #define EIC_EVCTRL_EXTINTEO0_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO0_Pos)               /**< (EIC_EVCTRL) External Interrupt 0 Event Output Enable Mask */
    90. 

  90. #define EIC_EVCTRL_EXTINTEO0(value)           (EIC_EVCTRL_EXTINTEO0_Msk & ((value) << EIC_EVCTRL_EXTINTEO0_Pos))
    91. 

  91. #define EIC_EVCTRL_EXTINTEO1_Pos              _U_(1)                                               /**< (EIC_EVCTRL) External Interrupt 1 Event Output Enable Position */
    92. 

  92. #define EIC_EVCTRL_EXTINTEO1_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO1_Pos)               /**< (EIC_EVCTRL) External Interrupt 1 Event Output Enable Mask */
    93. 

  93. #define EIC_EVCTRL_EXTINTEO1(value)           (EIC_EVCTRL_EXTINTEO1_Msk & ((value) << EIC_EVCTRL_EXTINTEO1_Pos))
    94. 

  94. #define EIC_EVCTRL_EXTINTEO2_Pos              _U_(2)                                               /**< (EIC_EVCTRL) External Interrupt 2 Event Output Enable Position */
    95. 

  95. #define EIC_EVCTRL_EXTINTEO2_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO2_Pos)               /**< (EIC_EVCTRL) External Interrupt 2 Event Output Enable Mask */
    96. 

  96. #define EIC_EVCTRL_EXTINTEO2(value)           (EIC_EVCTRL_EXTINTEO2_Msk & ((value) << EIC_EVCTRL_EXTINTEO2_Pos))
    97. 

  97. #define EIC_EVCTRL_EXTINTEO3_Pos              _U_(3)                                               /**< (EIC_EVCTRL) External Interrupt 3 Event Output Enable Position */
    98. 

  98. #define EIC_EVCTRL_EXTINTEO3_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO3_Pos)               /**< (EIC_EVCTRL) External Interrupt 3 Event Output Enable Mask */
    99. 

  99. #define EIC_EVCTRL_EXTINTEO3(value)           (EIC_EVCTRL_EXTINTEO3_Msk & ((value) << EIC_EVCTRL_EXTINTEO3_Pos))
    100. 

  100. #define EIC_EVCTRL_EXTINTEO4_Pos              _U_(4)                                               /**< (EIC_EVCTRL) External Interrupt 4 Event Output Enable Position */
    101. 

  101. #define EIC_EVCTRL_EXTINTEO4_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO4_Pos)               /**< (EIC_EVCTRL) External Interrupt 4 Event Output Enable Mask */
    102. 

  102. #define EIC_EVCTRL_EXTINTEO4(value)           (EIC_EVCTRL_EXTINTEO4_Msk & ((value) << EIC_EVCTRL_EXTINTEO4_Pos))
    103. 

  103. #define EIC_EVCTRL_EXTINTEO5_Pos              _U_(5)                                               /**< (EIC_EVCTRL) External Interrupt 5 Event Output Enable Position */
    104. 

  104. #define EIC_EVCTRL_EXTINTEO5_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO5_Pos)               /**< (EIC_EVCTRL) External Interrupt 5 Event Output Enable Mask */
    105. 

  105. #define EIC_EVCTRL_EXTINTEO5(value)           (EIC_EVCTRL_EXTINTEO5_Msk & ((value) << EIC_EVCTRL_EXTINTEO5_Pos))
    106. 

  106. #define EIC_EVCTRL_EXTINTEO6_Pos              _U_(6)                                               /**< (EIC_EVCTRL) External Interrupt 6 Event Output Enable Position */
    107. 

  107. #define EIC_EVCTRL_EXTINTEO6_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO6_Pos)               /**< (EIC_EVCTRL) External Interrupt 6 Event Output Enable Mask */
    108. 

  108. #define EIC_EVCTRL_EXTINTEO6(value)           (EIC_EVCTRL_EXTINTEO6_Msk & ((value) << EIC_EVCTRL_EXTINTEO6_Pos))
    109. 

  109. #define EIC_EVCTRL_EXTINTEO7_Pos              _U_(7)                                               /**< (EIC_EVCTRL) External Interrupt 7 Event Output Enable Position */
    110. 

  110. #define EIC_EVCTRL_EXTINTEO7_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO7_Pos)               /**< (EIC_EVCTRL) External Interrupt 7 Event Output Enable Mask */
    111. 

  111. #define EIC_EVCTRL_EXTINTEO7(value)           (EIC_EVCTRL_EXTINTEO7_Msk & ((value) << EIC_EVCTRL_EXTINTEO7_Pos))
    112. 

  112. #define EIC_EVCTRL_EXTINTEO8_Pos              _U_(8)                                               /**< (EIC_EVCTRL) External Interrupt 8 Event Output Enable Position */
    113. 

  113. #define EIC_EVCTRL_EXTINTEO8_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO8_Pos)               /**< (EIC_EVCTRL) External Interrupt 8 Event Output Enable Mask */
    114. 

  114. #define EIC_EVCTRL_EXTINTEO8(value)           (EIC_EVCTRL_EXTINTEO8_Msk & ((value) << EIC_EVCTRL_EXTINTEO8_Pos))
    115. 

  115. #define EIC_EVCTRL_EXTINTEO9_Pos              _U_(9)                                               /**< (EIC_EVCTRL) External Interrupt 9 Event Output Enable Position */
    116. 

  116. #define EIC_EVCTRL_EXTINTEO9_Msk              (_U_(0x1) << EIC_EVCTRL_EXTINTEO9_Pos)               /**< (EIC_EVCTRL) External Interrupt 9 Event Output Enable Mask */
    117. 

  117. #define EIC_EVCTRL_EXTINTEO9(value)           (EIC_EVCTRL_EXTINTEO9_Msk & ((value) << EIC_EVCTRL_EXTINTEO9_Pos))
    118. 

  118. #define EIC_EVCTRL_EXTINTEO10_Pos             _U_(10)                                              /**< (EIC_EVCTRL) External Interrupt 10 Event Output Enable Position */
    119. 

  119. #define EIC_EVCTRL_EXTINTEO10_Msk             (_U_(0x1) << EIC_EVCTRL_EXTINTEO10_Pos)              /**< (EIC_EVCTRL) External Interrupt 10 Event Output Enable Mask */
    120. 

  120. #define EIC_EVCTRL_EXTINTEO10(value)          (EIC_EVCTRL_EXTINTEO10_Msk & ((value) << EIC_EVCTRL_EXTINTEO10_Pos))
    121. 

  121. #define EIC_EVCTRL_EXTINTEO11_Pos             _U_(11)                                              /**< (EIC_EVCTRL) External Interrupt 11 Event Output Enable Position */
    122. 

  122. #define EIC_EVCTRL_EXTINTEO11_Msk             (_U_(0x1) << EIC_EVCTRL_EXTINTEO11_Pos)              /**< (EIC_EVCTRL) External Interrupt 11 Event Output Enable Mask */
    123. 

  123. #define EIC_EVCTRL_EXTINTEO11(value)          (EIC_EVCTRL_EXTINTEO11_Msk & ((value) << EIC_EVCTRL_EXTINTEO11_Pos))
    124. 

  124. #define EIC_EVCTRL_EXTINTEO12_Pos             _U_(12)                                              /**< (EIC_EVCTRL) External Interrupt 12 Event Output Enable Position */
    125. 

  125. #define EIC_EVCTRL_EXTINTEO12_Msk             (_U_(0x1) << EIC_EVCTRL_EXTINTEO12_Pos)              /**< (EIC_EVCTRL) External Interrupt 12 Event Output Enable Mask */
    126. 

  126. #define EIC_EVCTRL_EXTINTEO12(value)          (EIC_EVCTRL_EXTINTEO12_Msk & ((value) << EIC_EVCTRL_EXTINTEO12_Pos))
    127. 

  127. #define EIC_EVCTRL_EXTINTEO13_Pos             _U_(13)                                              /**< (EIC_EVCTRL) External Interrupt 13 Event Output Enable Position */
    128. 

  128. #define EIC_EVCTRL_EXTINTEO13_Msk             (_U_(0x1) << EIC_EVCTRL_EXTINTEO13_Pos)              /**< (EIC_EVCTRL) External Interrupt 13 Event Output Enable Mask */
    129. 

  129. #define EIC_EVCTRL_EXTINTEO13(value)          (EIC_EVCTRL_EXTINTEO13_Msk & ((value) << EIC_EVCTRL_EXTINTEO13_Pos))
    130. 

  130. #define EIC_EVCTRL_EXTINTEO14_Pos             _U_(14)                                              /**< (EIC_EVCTRL) External Interrupt 14 Event Output Enable Position */
    131. 

  131. #define EIC_EVCTRL_EXTINTEO14_Msk             (_U_(0x1) << EIC_EVCTRL_EXTINTEO14_Pos)              /**< (EIC_EVCTRL) External Interrupt 14 Event Output Enable Mask */
    132. 

  132. #define EIC_EVCTRL_EXTINTEO14(value)          (EIC_EVCTRL_EXTINTEO14_Msk & ((value) << EIC_EVCTRL_EXTINTEO14_Pos))
    133. 

  133. #define EIC_EVCTRL_EXTINTEO15_Pos             _U_(15)                                              /**< (EIC_EVCTRL) External Interrupt 15 Event Output Enable Position */
    134. 

  134. #define EIC_EVCTRL_EXTINTEO15_Msk             (_U_(0x1) << EIC_EVCTRL_EXTINTEO15_Pos)              /**< (EIC_EVCTRL) External Interrupt 15 Event Output Enable Mask */
    135. 

  135. #define EIC_EVCTRL_EXTINTEO15(value)          (EIC_EVCTRL_EXTINTEO15_Msk & ((value) << EIC_EVCTRL_EXTINTEO15_Pos))
    136. 

  136. #define EIC_EVCTRL_Msk                        _U_(0x0000FFFF)                                      /**< (EIC_EVCTRL) Register Mask  */
    137. 

  137. 

  138. #define EIC_EVCTRL_EXTINTEO_Pos               _U_(0)                                               /**< (EIC_EVCTRL Position) External Interrupt x5 Event Output Enable */
    139. 

  139. #define EIC_EVCTRL_EXTINTEO_Msk               (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)             /**< (EIC_EVCTRL Mask) EXTINTEO */
    140. 

  140. #define EIC_EVCTRL_EXTINTEO(value)            (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos)) 
    141. 

  141. 

  142. /* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
    143. 

  143. #define EIC_INTENCLR_RESETVALUE               _U_(0x00)                                            /**<  (EIC_INTENCLR) Interrupt Enable Clear  Reset Value */
    144. 

  144. 

  145. #define EIC_INTENCLR_EXTINT0_Pos              _U_(0)                                               /**< (EIC_INTENCLR) External Interrupt 0 Enable Position */
    146. 

  146. #define EIC_INTENCLR_EXTINT0_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT0_Pos)               /**< (EIC_INTENCLR) External Interrupt 0 Enable Mask */
    147. 

  147. #define EIC_INTENCLR_EXTINT0(value)           (EIC_INTENCLR_EXTINT0_Msk & ((value) << EIC_INTENCLR_EXTINT0_Pos))
    148. 

  148. #define EIC_INTENCLR_EXTINT1_Pos              _U_(1)                                               /**< (EIC_INTENCLR) External Interrupt 1 Enable Position */
    149. 

  149. #define EIC_INTENCLR_EXTINT1_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT1_Pos)               /**< (EIC_INTENCLR) External Interrupt 1 Enable Mask */
    150. 

  150. #define EIC_INTENCLR_EXTINT1(value)           (EIC_INTENCLR_EXTINT1_Msk & ((value) << EIC_INTENCLR_EXTINT1_Pos))
    151. 

  151. #define EIC_INTENCLR_EXTINT2_Pos              _U_(2)                                               /**< (EIC_INTENCLR) External Interrupt 2 Enable Position */
    152. 

  152. #define EIC_INTENCLR_EXTINT2_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT2_Pos)               /**< (EIC_INTENCLR) External Interrupt 2 Enable Mask */
    153. 

  153. #define EIC_INTENCLR_EXTINT2(value)           (EIC_INTENCLR_EXTINT2_Msk & ((value) << EIC_INTENCLR_EXTINT2_Pos))
    154. 

  154. #define EIC_INTENCLR_EXTINT3_Pos              _U_(3)                                               /**< (EIC_INTENCLR) External Interrupt 3 Enable Position */
    155. 

  155. #define EIC_INTENCLR_EXTINT3_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT3_Pos)               /**< (EIC_INTENCLR) External Interrupt 3 Enable Mask */
    156. 

  156. #define EIC_INTENCLR_EXTINT3(value)           (EIC_INTENCLR_EXTINT3_Msk & ((value) << EIC_INTENCLR_EXTINT3_Pos))
    157. 

  157. #define EIC_INTENCLR_EXTINT4_Pos              _U_(4)                                               /**< (EIC_INTENCLR) External Interrupt 4 Enable Position */
    158. 

  158. #define EIC_INTENCLR_EXTINT4_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT4_Pos)               /**< (EIC_INTENCLR) External Interrupt 4 Enable Mask */
    159. 

  159. #define EIC_INTENCLR_EXTINT4(value)           (EIC_INTENCLR_EXTINT4_Msk & ((value) << EIC_INTENCLR_EXTINT4_Pos))
    160. 

  160. #define EIC_INTENCLR_EXTINT5_Pos              _U_(5)                                               /**< (EIC_INTENCLR) External Interrupt 5 Enable Position */
    161. 

  161. #define EIC_INTENCLR_EXTINT5_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT5_Pos)               /**< (EIC_INTENCLR) External Interrupt 5 Enable Mask */
    162. 

  162. #define EIC_INTENCLR_EXTINT5(value)           (EIC_INTENCLR_EXTINT5_Msk & ((value) << EIC_INTENCLR_EXTINT5_Pos))
    163. 

  163. #define EIC_INTENCLR_EXTINT6_Pos              _U_(6)                                               /**< (EIC_INTENCLR) External Interrupt 6 Enable Position */
    164. 

  164. #define EIC_INTENCLR_EXTINT6_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT6_Pos)               /**< (EIC_INTENCLR) External Interrupt 6 Enable Mask */
    165. 

  165. #define EIC_INTENCLR_EXTINT6(value)           (EIC_INTENCLR_EXTINT6_Msk & ((value) << EIC_INTENCLR_EXTINT6_Pos))
    166. 

  166. #define EIC_INTENCLR_EXTINT7_Pos              _U_(7)                                               /**< (EIC_INTENCLR) External Interrupt 7 Enable Position */
    167. 

  167. #define EIC_INTENCLR_EXTINT7_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT7_Pos)               /**< (EIC_INTENCLR) External Interrupt 7 Enable Mask */
    168. 

  168. #define EIC_INTENCLR_EXTINT7(value)           (EIC_INTENCLR_EXTINT7_Msk & ((value) << EIC_INTENCLR_EXTINT7_Pos))
    169. 

  169. #define EIC_INTENCLR_EXTINT8_Pos              _U_(8)                                               /**< (EIC_INTENCLR) External Interrupt 8 Enable Position */
    170. 

  170. #define EIC_INTENCLR_EXTINT8_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT8_Pos)               /**< (EIC_INTENCLR) External Interrupt 8 Enable Mask */
    171. 

  171. #define EIC_INTENCLR_EXTINT8(value)           (EIC_INTENCLR_EXTINT8_Msk & ((value) << EIC_INTENCLR_EXTINT8_Pos))
    172. 

  172. #define EIC_INTENCLR_EXTINT9_Pos              _U_(9)                                               /**< (EIC_INTENCLR) External Interrupt 9 Enable Position */
    173. 

  173. #define EIC_INTENCLR_EXTINT9_Msk              (_U_(0x1) << EIC_INTENCLR_EXTINT9_Pos)               /**< (EIC_INTENCLR) External Interrupt 9 Enable Mask */
    174. 

  174. #define EIC_INTENCLR_EXTINT9(value)           (EIC_INTENCLR_EXTINT9_Msk & ((value) << EIC_INTENCLR_EXTINT9_Pos))
    175. 

  175. #define EIC_INTENCLR_EXTINT10_Pos             _U_(10)                                              /**< (EIC_INTENCLR) External Interrupt 10 Enable Position */
    176. 

  176. #define EIC_INTENCLR_EXTINT10_Msk             (_U_(0x1) << EIC_INTENCLR_EXTINT10_Pos)              /**< (EIC_INTENCLR) External Interrupt 10 Enable Mask */
    177. 

  177. #define EIC_INTENCLR_EXTINT10(value)          (EIC_INTENCLR_EXTINT10_Msk & ((value) << EIC_INTENCLR_EXTINT10_Pos))
    178. 

  178. #define EIC_INTENCLR_EXTINT11_Pos             _U_(11)                                              /**< (EIC_INTENCLR) External Interrupt 11 Enable Position */
    179. 

  179. #define EIC_INTENCLR_EXTINT11_Msk             (_U_(0x1) << EIC_INTENCLR_EXTINT11_Pos)              /**< (EIC_INTENCLR) External Interrupt 11 Enable Mask */
    180. 

  180. #define EIC_INTENCLR_EXTINT11(value)          (EIC_INTENCLR_EXTINT11_Msk & ((value) << EIC_INTENCLR_EXTINT11_Pos))
    181. 

  181. #define EIC_INTENCLR_EXTINT12_Pos             _U_(12)                                              /**< (EIC_INTENCLR) External Interrupt 12 Enable Position */
    182. 

  182. #define EIC_INTENCLR_EXTINT12_Msk             (_U_(0x1) << EIC_INTENCLR_EXTINT12_Pos)              /**< (EIC_INTENCLR) External Interrupt 12 Enable Mask */
    183. 

  183. #define EIC_INTENCLR_EXTINT12(value)          (EIC_INTENCLR_EXTINT12_Msk & ((value) << EIC_INTENCLR_EXTINT12_Pos))
    184. 

  184. #define EIC_INTENCLR_EXTINT13_Pos             _U_(13)                                              /**< (EIC_INTENCLR) External Interrupt 13 Enable Position */
    185. 

  185. #define EIC_INTENCLR_EXTINT13_Msk             (_U_(0x1) << EIC_INTENCLR_EXTINT13_Pos)              /**< (EIC_INTENCLR) External Interrupt 13 Enable Mask */
    186. 

  186. #define EIC_INTENCLR_EXTINT13(value)          (EIC_INTENCLR_EXTINT13_Msk & ((value) << EIC_INTENCLR_EXTINT13_Pos))
    187. 

  187. #define EIC_INTENCLR_EXTINT14_Pos             _U_(14)                                              /**< (EIC_INTENCLR) External Interrupt 14 Enable Position */
    188. 

  188. #define EIC_INTENCLR_EXTINT14_Msk             (_U_(0x1) << EIC_INTENCLR_EXTINT14_Pos)              /**< (EIC_INTENCLR) External Interrupt 14 Enable Mask */
    189. 

  189. #define EIC_INTENCLR_EXTINT14(value)          (EIC_INTENCLR_EXTINT14_Msk & ((value) << EIC_INTENCLR_EXTINT14_Pos))
    190. 

  190. #define EIC_INTENCLR_EXTINT15_Pos             _U_(15)                                              /**< (EIC_INTENCLR) External Interrupt 15 Enable Position */
    191. 

  191. #define EIC_INTENCLR_EXTINT15_Msk             (_U_(0x1) << EIC_INTENCLR_EXTINT15_Pos)              /**< (EIC_INTENCLR) External Interrupt 15 Enable Mask */
    192. 

  192. #define EIC_INTENCLR_EXTINT15(value)          (EIC_INTENCLR_EXTINT15_Msk & ((value) << EIC_INTENCLR_EXTINT15_Pos))
    193. 

  193. #define EIC_INTENCLR_Msk                      _U_(0x0000FFFF)                                      /**< (EIC_INTENCLR) Register Mask  */
    194. 

  194. 

  195. #define EIC_INTENCLR_EXTINT_Pos               _U_(0)                                               /**< (EIC_INTENCLR Position) External Interrupt x5 Enable */
    196. 

  196. #define EIC_INTENCLR_EXTINT_Msk               (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)             /**< (EIC_INTENCLR Mask) EXTINT */
    197. 

  197. #define EIC_INTENCLR_EXTINT(value)            (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos)) 
    198. 

  198. 

  199. /* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
    200. 

  200. #define EIC_INTENSET_RESETVALUE               _U_(0x00)                                            /**<  (EIC_INTENSET) Interrupt Enable Set  Reset Value */
    201. 

  201. 

  202. #define EIC_INTENSET_EXTINT0_Pos              _U_(0)                                               /**< (EIC_INTENSET) External Interrupt 0 Enable Position */
    203. 

  203. #define EIC_INTENSET_EXTINT0_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT0_Pos)               /**< (EIC_INTENSET) External Interrupt 0 Enable Mask */
    204. 

  204. #define EIC_INTENSET_EXTINT0(value)           (EIC_INTENSET_EXTINT0_Msk & ((value) << EIC_INTENSET_EXTINT0_Pos))
    205. 

  205. #define EIC_INTENSET_EXTINT1_Pos              _U_(1)                                               /**< (EIC_INTENSET) External Interrupt 1 Enable Position */
    206. 

  206. #define EIC_INTENSET_EXTINT1_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT1_Pos)               /**< (EIC_INTENSET) External Interrupt 1 Enable Mask */
    207. 

  207. #define EIC_INTENSET_EXTINT1(value)           (EIC_INTENSET_EXTINT1_Msk & ((value) << EIC_INTENSET_EXTINT1_Pos))
    208. 

  208. #define EIC_INTENSET_EXTINT2_Pos              _U_(2)                                               /**< (EIC_INTENSET) External Interrupt 2 Enable Position */
    209. 

  209. #define EIC_INTENSET_EXTINT2_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT2_Pos)               /**< (EIC_INTENSET) External Interrupt 2 Enable Mask */
    210. 

  210. #define EIC_INTENSET_EXTINT2(value)           (EIC_INTENSET_EXTINT2_Msk & ((value) << EIC_INTENSET_EXTINT2_Pos))
    211. 

  211. #define EIC_INTENSET_EXTINT3_Pos              _U_(3)                                               /**< (EIC_INTENSET) External Interrupt 3 Enable Position */
    212. 

  212. #define EIC_INTENSET_EXTINT3_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT3_Pos)               /**< (EIC_INTENSET) External Interrupt 3 Enable Mask */
    213. 

  213. #define EIC_INTENSET_EXTINT3(value)           (EIC_INTENSET_EXTINT3_Msk & ((value) << EIC_INTENSET_EXTINT3_Pos))
    214. 

  214. #define EIC_INTENSET_EXTINT4_Pos              _U_(4)                                               /**< (EIC_INTENSET) External Interrupt 4 Enable Position */
    215. 

  215. #define EIC_INTENSET_EXTINT4_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT4_Pos)               /**< (EIC_INTENSET) External Interrupt 4 Enable Mask */
    216. 

  216. #define EIC_INTENSET_EXTINT4(value)           (EIC_INTENSET_EXTINT4_Msk & ((value) << EIC_INTENSET_EXTINT4_Pos))
    217. 

  217. #define EIC_INTENSET_EXTINT5_Pos              _U_(5)                                               /**< (EIC_INTENSET) External Interrupt 5 Enable Position */
    218. 

  218. #define EIC_INTENSET_EXTINT5_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT5_Pos)               /**< (EIC_INTENSET) External Interrupt 5 Enable Mask */
    219. 

  219. #define EIC_INTENSET_EXTINT5(value)           (EIC_INTENSET_EXTINT5_Msk & ((value) << EIC_INTENSET_EXTINT5_Pos))
    220. 

  220. #define EIC_INTENSET_EXTINT6_Pos              _U_(6)                                               /**< (EIC_INTENSET) External Interrupt 6 Enable Position */
    221. 

  221. #define EIC_INTENSET_EXTINT6_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT6_Pos)               /**< (EIC_INTENSET) External Interrupt 6 Enable Mask */
    222. 

  222. #define EIC_INTENSET_EXTINT6(value)           (EIC_INTENSET_EXTINT6_Msk & ((value) << EIC_INTENSET_EXTINT6_Pos))
    223. 

  223. #define EIC_INTENSET_EXTINT7_Pos              _U_(7)                                               /**< (EIC_INTENSET) External Interrupt 7 Enable Position */
    224. 

  224. #define EIC_INTENSET_EXTINT7_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT7_Pos)               /**< (EIC_INTENSET) External Interrupt 7 Enable Mask */
    225. 

  225. #define EIC_INTENSET_EXTINT7(value)           (EIC_INTENSET_EXTINT7_Msk & ((value) << EIC_INTENSET_EXTINT7_Pos))
    226. 

  226. #define EIC_INTENSET_EXTINT8_Pos              _U_(8)                                               /**< (EIC_INTENSET) External Interrupt 8 Enable Position */
    227. 

  227. #define EIC_INTENSET_EXTINT8_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT8_Pos)               /**< (EIC_INTENSET) External Interrupt 8 Enable Mask */
    228. 

  228. #define EIC_INTENSET_EXTINT8(value)           (EIC_INTENSET_EXTINT8_Msk & ((value) << EIC_INTENSET_EXTINT8_Pos))
    229. 

  229. #define EIC_INTENSET_EXTINT9_Pos              _U_(9)                                               /**< (EIC_INTENSET) External Interrupt 9 Enable Position */
    230. 

  230. #define EIC_INTENSET_EXTINT9_Msk              (_U_(0x1) << EIC_INTENSET_EXTINT9_Pos)               /**< (EIC_INTENSET) External Interrupt 9 Enable Mask */
    231. 

  231. #define EIC_INTENSET_EXTINT9(value)           (EIC_INTENSET_EXTINT9_Msk & ((value) << EIC_INTENSET_EXTINT9_Pos))
    232. 

  232. #define EIC_INTENSET_EXTINT10_Pos             _U_(10)                                              /**< (EIC_INTENSET) External Interrupt 10 Enable Position */
    233. 

  233. #define EIC_INTENSET_EXTINT10_Msk             (_U_(0x1) << EIC_INTENSET_EXTINT10_Pos)              /**< (EIC_INTENSET) External Interrupt 10 Enable Mask */
    234. 

  234. #define EIC_INTENSET_EXTINT10(value)          (EIC_INTENSET_EXTINT10_Msk & ((value) << EIC_INTENSET_EXTINT10_Pos))
    235. 

  235. #define EIC_INTENSET_EXTINT11_Pos             _U_(11)                                              /**< (EIC_INTENSET) External Interrupt 11 Enable Position */
    236. 

  236. #define EIC_INTENSET_EXTINT11_Msk             (_U_(0x1) << EIC_INTENSET_EXTINT11_Pos)              /**< (EIC_INTENSET) External Interrupt 11 Enable Mask */
    237. 

  237. #define EIC_INTENSET_EXTINT11(value)          (EIC_INTENSET_EXTINT11_Msk & ((value) << EIC_INTENSET_EXTINT11_Pos))
    238. 

  238. #define EIC_INTENSET_EXTINT12_Pos             _U_(12)                                              /**< (EIC_INTENSET) External Interrupt 12 Enable Position */
    239. 

  239. #define EIC_INTENSET_EXTINT12_Msk             (_U_(0x1) << EIC_INTENSET_EXTINT12_Pos)              /**< (EIC_INTENSET) External Interrupt 12 Enable Mask */
    240. 

  240. #define EIC_INTENSET_EXTINT12(value)          (EIC_INTENSET_EXTINT12_Msk & ((value) << EIC_INTENSET_EXTINT12_Pos))
    241. 

  241. #define EIC_INTENSET_EXTINT13_Pos             _U_(13)                                              /**< (EIC_INTENSET) External Interrupt 13 Enable Position */
    242. 

  242. #define EIC_INTENSET_EXTINT13_Msk             (_U_(0x1) << EIC_INTENSET_EXTINT13_Pos)              /**< (EIC_INTENSET) External Interrupt 13 Enable Mask */
    243. 

  243. #define EIC_INTENSET_EXTINT13(value)          (EIC_INTENSET_EXTINT13_Msk & ((value) << EIC_INTENSET_EXTINT13_Pos))
    244. 

  244. #define EIC_INTENSET_EXTINT14_Pos             _U_(14)                                              /**< (EIC_INTENSET) External Interrupt 14 Enable Position */
    245. 

  245. #define EIC_INTENSET_EXTINT14_Msk             (_U_(0x1) << EIC_INTENSET_EXTINT14_Pos)              /**< (EIC_INTENSET) External Interrupt 14 Enable Mask */
    246. 

  246. #define EIC_INTENSET_EXTINT14(value)          (EIC_INTENSET_EXTINT14_Msk & ((value) << EIC_INTENSET_EXTINT14_Pos))
    247. 

  247. #define EIC_INTENSET_EXTINT15_Pos             _U_(15)                                              /**< (EIC_INTENSET) External Interrupt 15 Enable Position */
    248. 

  248. #define EIC_INTENSET_EXTINT15_Msk             (_U_(0x1) << EIC_INTENSET_EXTINT15_Pos)              /**< (EIC_INTENSET) External Interrupt 15 Enable Mask */
    249. 

  249. #define EIC_INTENSET_EXTINT15(value)          (EIC_INTENSET_EXTINT15_Msk & ((value) << EIC_INTENSET_EXTINT15_Pos))
    250. 

  250. #define EIC_INTENSET_Msk                      _U_(0x0000FFFF)                                      /**< (EIC_INTENSET) Register Mask  */
    251. 

  251. 

  252. #define EIC_INTENSET_EXTINT_Pos               _U_(0)                                               /**< (EIC_INTENSET Position) External Interrupt x5 Enable */
    253. 

  253. #define EIC_INTENSET_EXTINT_Msk               (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)             /**< (EIC_INTENSET Mask) EXTINT */
    254. 

  254. #define EIC_INTENSET_EXTINT(value)            (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos)) 
    255. 

  255. 

  256. /* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
    257. 

  257. #define EIC_INTFLAG_RESETVALUE                _U_(0x00)                                            /**<  (EIC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    258. 

  258. 

  259. #define EIC_INTFLAG_EXTINT0_Pos               _U_(0)                                               /**< (EIC_INTFLAG) External Interrupt 0 Position */
    260. 

  260. #define EIC_INTFLAG_EXTINT0_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT0_Pos)                /**< (EIC_INTFLAG) External Interrupt 0 Mask */
    261. 

  261. #define EIC_INTFLAG_EXTINT0(value)            (EIC_INTFLAG_EXTINT0_Msk & ((value) << EIC_INTFLAG_EXTINT0_Pos))
    262. 

  262. #define EIC_INTFLAG_EXTINT1_Pos               _U_(1)                                               /**< (EIC_INTFLAG) External Interrupt 1 Position */
    263. 

  263. #define EIC_INTFLAG_EXTINT1_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT1_Pos)                /**< (EIC_INTFLAG) External Interrupt 1 Mask */
    264. 

  264. #define EIC_INTFLAG_EXTINT1(value)            (EIC_INTFLAG_EXTINT1_Msk & ((value) << EIC_INTFLAG_EXTINT1_Pos))
    265. 

  265. #define EIC_INTFLAG_EXTINT2_Pos               _U_(2)                                               /**< (EIC_INTFLAG) External Interrupt 2 Position */
    266. 

  266. #define EIC_INTFLAG_EXTINT2_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT2_Pos)                /**< (EIC_INTFLAG) External Interrupt 2 Mask */
    267. 

  267. #define EIC_INTFLAG_EXTINT2(value)            (EIC_INTFLAG_EXTINT2_Msk & ((value) << EIC_INTFLAG_EXTINT2_Pos))
    268. 

  268. #define EIC_INTFLAG_EXTINT3_Pos               _U_(3)                                               /**< (EIC_INTFLAG) External Interrupt 3 Position */
    269. 

  269. #define EIC_INTFLAG_EXTINT3_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT3_Pos)                /**< (EIC_INTFLAG) External Interrupt 3 Mask */
    270. 

  270. #define EIC_INTFLAG_EXTINT3(value)            (EIC_INTFLAG_EXTINT3_Msk & ((value) << EIC_INTFLAG_EXTINT3_Pos))
    271. 

  271. #define EIC_INTFLAG_EXTINT4_Pos               _U_(4)                                               /**< (EIC_INTFLAG) External Interrupt 4 Position */
    272. 

  272. #define EIC_INTFLAG_EXTINT4_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT4_Pos)                /**< (EIC_INTFLAG) External Interrupt 4 Mask */
    273. 

  273. #define EIC_INTFLAG_EXTINT4(value)            (EIC_INTFLAG_EXTINT4_Msk & ((value) << EIC_INTFLAG_EXTINT4_Pos))
    274. 

  274. #define EIC_INTFLAG_EXTINT5_Pos               _U_(5)                                               /**< (EIC_INTFLAG) External Interrupt 5 Position */
    275. 

  275. #define EIC_INTFLAG_EXTINT5_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT5_Pos)                /**< (EIC_INTFLAG) External Interrupt 5 Mask */
    276. 

  276. #define EIC_INTFLAG_EXTINT5(value)            (EIC_INTFLAG_EXTINT5_Msk & ((value) << EIC_INTFLAG_EXTINT5_Pos))
    277. 

  277. #define EIC_INTFLAG_EXTINT6_Pos               _U_(6)                                               /**< (EIC_INTFLAG) External Interrupt 6 Position */
    278. 

  278. #define EIC_INTFLAG_EXTINT6_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT6_Pos)                /**< (EIC_INTFLAG) External Interrupt 6 Mask */
    279. 

  279. #define EIC_INTFLAG_EXTINT6(value)            (EIC_INTFLAG_EXTINT6_Msk & ((value) << EIC_INTFLAG_EXTINT6_Pos))
    280. 

  280. #define EIC_INTFLAG_EXTINT7_Pos               _U_(7)                                               /**< (EIC_INTFLAG) External Interrupt 7 Position */
    281. 

  281. #define EIC_INTFLAG_EXTINT7_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT7_Pos)                /**< (EIC_INTFLAG) External Interrupt 7 Mask */
    282. 

  282. #define EIC_INTFLAG_EXTINT7(value)            (EIC_INTFLAG_EXTINT7_Msk & ((value) << EIC_INTFLAG_EXTINT7_Pos))
    283. 

  283. #define EIC_INTFLAG_EXTINT8_Pos               _U_(8)                                               /**< (EIC_INTFLAG) External Interrupt 8 Position */
    284. 

  284. #define EIC_INTFLAG_EXTINT8_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT8_Pos)                /**< (EIC_INTFLAG) External Interrupt 8 Mask */
    285. 

  285. #define EIC_INTFLAG_EXTINT8(value)            (EIC_INTFLAG_EXTINT8_Msk & ((value) << EIC_INTFLAG_EXTINT8_Pos))
    286. 

  286. #define EIC_INTFLAG_EXTINT9_Pos               _U_(9)                                               /**< (EIC_INTFLAG) External Interrupt 9 Position */
    287. 

  287. #define EIC_INTFLAG_EXTINT9_Msk               (_U_(0x1) << EIC_INTFLAG_EXTINT9_Pos)                /**< (EIC_INTFLAG) External Interrupt 9 Mask */
    288. 

  288. #define EIC_INTFLAG_EXTINT9(value)            (EIC_INTFLAG_EXTINT9_Msk & ((value) << EIC_INTFLAG_EXTINT9_Pos))
    289. 

  289. #define EIC_INTFLAG_EXTINT10_Pos              _U_(10)                                              /**< (EIC_INTFLAG) External Interrupt 10 Position */
    290. 

  290. #define EIC_INTFLAG_EXTINT10_Msk              (_U_(0x1) << EIC_INTFLAG_EXTINT10_Pos)               /**< (EIC_INTFLAG) External Interrupt 10 Mask */
    291. 

  291. #define EIC_INTFLAG_EXTINT10(value)           (EIC_INTFLAG_EXTINT10_Msk & ((value) << EIC_INTFLAG_EXTINT10_Pos))
    292. 

  292. #define EIC_INTFLAG_EXTINT11_Pos              _U_(11)                                              /**< (EIC_INTFLAG) External Interrupt 11 Position */
    293. 

  293. #define EIC_INTFLAG_EXTINT11_Msk              (_U_(0x1) << EIC_INTFLAG_EXTINT11_Pos)               /**< (EIC_INTFLAG) External Interrupt 11 Mask */
    294. 

  294. #define EIC_INTFLAG_EXTINT11(value)           (EIC_INTFLAG_EXTINT11_Msk & ((value) << EIC_INTFLAG_EXTINT11_Pos))
    295. 

  295. #define EIC_INTFLAG_EXTINT12_Pos              _U_(12)                                              /**< (EIC_INTFLAG) External Interrupt 12 Position */
    296. 

  296. #define EIC_INTFLAG_EXTINT12_Msk              (_U_(0x1) << EIC_INTFLAG_EXTINT12_Pos)               /**< (EIC_INTFLAG) External Interrupt 12 Mask */
    297. 

  297. #define EIC_INTFLAG_EXTINT12(value)           (EIC_INTFLAG_EXTINT12_Msk & ((value) << EIC_INTFLAG_EXTINT12_Pos))
    298. 

  298. #define EIC_INTFLAG_EXTINT13_Pos              _U_(13)                                              /**< (EIC_INTFLAG) External Interrupt 13 Position */
    299. 

  299. #define EIC_INTFLAG_EXTINT13_Msk              (_U_(0x1) << EIC_INTFLAG_EXTINT13_Pos)               /**< (EIC_INTFLAG) External Interrupt 13 Mask */
    300. 

  300. #define EIC_INTFLAG_EXTINT13(value)           (EIC_INTFLAG_EXTINT13_Msk & ((value) << EIC_INTFLAG_EXTINT13_Pos))
    301. 

  301. #define EIC_INTFLAG_EXTINT14_Pos              _U_(14)                                              /**< (EIC_INTFLAG) External Interrupt 14 Position */
    302. 

  302. #define EIC_INTFLAG_EXTINT14_Msk              (_U_(0x1) << EIC_INTFLAG_EXTINT14_Pos)               /**< (EIC_INTFLAG) External Interrupt 14 Mask */
    303. 

  303. #define EIC_INTFLAG_EXTINT14(value)           (EIC_INTFLAG_EXTINT14_Msk & ((value) << EIC_INTFLAG_EXTINT14_Pos))
    304. 

  304. #define EIC_INTFLAG_EXTINT15_Pos              _U_(15)                                              /**< (EIC_INTFLAG) External Interrupt 15 Position */
    305. 

  305. #define EIC_INTFLAG_EXTINT15_Msk              (_U_(0x1) << EIC_INTFLAG_EXTINT15_Pos)               /**< (EIC_INTFLAG) External Interrupt 15 Mask */
    306. 

  306. #define EIC_INTFLAG_EXTINT15(value)           (EIC_INTFLAG_EXTINT15_Msk & ((value) << EIC_INTFLAG_EXTINT15_Pos))
    307. 

  307. #define EIC_INTFLAG_Msk                       _U_(0x0000FFFF)                                      /**< (EIC_INTFLAG) Register Mask  */
    308. 

  308. 

  309. #define EIC_INTFLAG_EXTINT_Pos                _U_(0)                                               /**< (EIC_INTFLAG Position) External Interrupt x5 */
    310. 

  310. #define EIC_INTFLAG_EXTINT_Msk                (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)              /**< (EIC_INTFLAG Mask) EXTINT */
    311. 

  311. #define EIC_INTFLAG_EXTINT(value)             (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos)) 
    312. 

  312. 

  313. /* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
    314. 

  314. #define EIC_WAKEUP_RESETVALUE                 _U_(0x00)                                            /**<  (EIC_WAKEUP) Wake-Up Enable  Reset Value */
    315. 

  315. 

  316. #define EIC_WAKEUP_WAKEUPEN0_Pos              _U_(0)                                               /**< (EIC_WAKEUP) External Interrupt 0 Wake-up Enable Position */
    317. 

  317. #define EIC_WAKEUP_WAKEUPEN0_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN0_Pos)               /**< (EIC_WAKEUP) External Interrupt 0 Wake-up Enable Mask */
    318. 

  318. #define EIC_WAKEUP_WAKEUPEN0(value)           (EIC_WAKEUP_WAKEUPEN0_Msk & ((value) << EIC_WAKEUP_WAKEUPEN0_Pos))
    319. 

  319. #define EIC_WAKEUP_WAKEUPEN1_Pos              _U_(1)                                               /**< (EIC_WAKEUP) External Interrupt 1 Wake-up Enable Position */
    320. 

  320. #define EIC_WAKEUP_WAKEUPEN1_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN1_Pos)               /**< (EIC_WAKEUP) External Interrupt 1 Wake-up Enable Mask */
    321. 

  321. #define EIC_WAKEUP_WAKEUPEN1(value)           (EIC_WAKEUP_WAKEUPEN1_Msk & ((value) << EIC_WAKEUP_WAKEUPEN1_Pos))
    322. 

  322. #define EIC_WAKEUP_WAKEUPEN2_Pos              _U_(2)                                               /**< (EIC_WAKEUP) External Interrupt 2 Wake-up Enable Position */
    323. 

  323. #define EIC_WAKEUP_WAKEUPEN2_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN2_Pos)               /**< (EIC_WAKEUP) External Interrupt 2 Wake-up Enable Mask */
    324. 

  324. #define EIC_WAKEUP_WAKEUPEN2(value)           (EIC_WAKEUP_WAKEUPEN2_Msk & ((value) << EIC_WAKEUP_WAKEUPEN2_Pos))
    325. 

  325. #define EIC_WAKEUP_WAKEUPEN3_Pos              _U_(3)                                               /**< (EIC_WAKEUP) External Interrupt 3 Wake-up Enable Position */
    326. 

  326. #define EIC_WAKEUP_WAKEUPEN3_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN3_Pos)               /**< (EIC_WAKEUP) External Interrupt 3 Wake-up Enable Mask */
    327. 

  327. #define EIC_WAKEUP_WAKEUPEN3(value)           (EIC_WAKEUP_WAKEUPEN3_Msk & ((value) << EIC_WAKEUP_WAKEUPEN3_Pos))
    328. 

  328. #define EIC_WAKEUP_WAKEUPEN4_Pos              _U_(4)                                               /**< (EIC_WAKEUP) External Interrupt 4 Wake-up Enable Position */
    329. 

  329. #define EIC_WAKEUP_WAKEUPEN4_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN4_Pos)               /**< (EIC_WAKEUP) External Interrupt 4 Wake-up Enable Mask */
    330. 

  330. #define EIC_WAKEUP_WAKEUPEN4(value)           (EIC_WAKEUP_WAKEUPEN4_Msk & ((value) << EIC_WAKEUP_WAKEUPEN4_Pos))
    331. 

  331. #define EIC_WAKEUP_WAKEUPEN5_Pos              _U_(5)                                               /**< (EIC_WAKEUP) External Interrupt 5 Wake-up Enable Position */
    332. 

  332. #define EIC_WAKEUP_WAKEUPEN5_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN5_Pos)               /**< (EIC_WAKEUP) External Interrupt 5 Wake-up Enable Mask */
    333. 

  333. #define EIC_WAKEUP_WAKEUPEN5(value)           (EIC_WAKEUP_WAKEUPEN5_Msk & ((value) << EIC_WAKEUP_WAKEUPEN5_Pos))
    334. 

  334. #define EIC_WAKEUP_WAKEUPEN6_Pos              _U_(6)                                               /**< (EIC_WAKEUP) External Interrupt 6 Wake-up Enable Position */
    335. 

  335. #define EIC_WAKEUP_WAKEUPEN6_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN6_Pos)               /**< (EIC_WAKEUP) External Interrupt 6 Wake-up Enable Mask */
    336. 

  336. #define EIC_WAKEUP_WAKEUPEN6(value)           (EIC_WAKEUP_WAKEUPEN6_Msk & ((value) << EIC_WAKEUP_WAKEUPEN6_Pos))
    337. 

  337. #define EIC_WAKEUP_WAKEUPEN7_Pos              _U_(7)                                               /**< (EIC_WAKEUP) External Interrupt 7 Wake-up Enable Position */
    338. 

  338. #define EIC_WAKEUP_WAKEUPEN7_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN7_Pos)               /**< (EIC_WAKEUP) External Interrupt 7 Wake-up Enable Mask */
    339. 

  339. #define EIC_WAKEUP_WAKEUPEN7(value)           (EIC_WAKEUP_WAKEUPEN7_Msk & ((value) << EIC_WAKEUP_WAKEUPEN7_Pos))
    340. 

  340. #define EIC_WAKEUP_WAKEUPEN8_Pos              _U_(8)                                               /**< (EIC_WAKEUP) External Interrupt 8 Wake-up Enable Position */
    341. 

  341. #define EIC_WAKEUP_WAKEUPEN8_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN8_Pos)               /**< (EIC_WAKEUP) External Interrupt 8 Wake-up Enable Mask */
    342. 

  342. #define EIC_WAKEUP_WAKEUPEN8(value)           (EIC_WAKEUP_WAKEUPEN8_Msk & ((value) << EIC_WAKEUP_WAKEUPEN8_Pos))
    343. 

  343. #define EIC_WAKEUP_WAKEUPEN9_Pos              _U_(9)                                               /**< (EIC_WAKEUP) External Interrupt 9 Wake-up Enable Position */
    344. 

  344. #define EIC_WAKEUP_WAKEUPEN9_Msk              (_U_(0x1) << EIC_WAKEUP_WAKEUPEN9_Pos)               /**< (EIC_WAKEUP) External Interrupt 9 Wake-up Enable Mask */
    345. 

  345. #define EIC_WAKEUP_WAKEUPEN9(value)           (EIC_WAKEUP_WAKEUPEN9_Msk & ((value) << EIC_WAKEUP_WAKEUPEN9_Pos))
    346. 

  346. #define EIC_WAKEUP_WAKEUPEN10_Pos             _U_(10)                                              /**< (EIC_WAKEUP) External Interrupt 10 Wake-up Enable Position */
    347. 

  347. #define EIC_WAKEUP_WAKEUPEN10_Msk             (_U_(0x1) << EIC_WAKEUP_WAKEUPEN10_Pos)              /**< (EIC_WAKEUP) External Interrupt 10 Wake-up Enable Mask */
    348. 

  348. #define EIC_WAKEUP_WAKEUPEN10(value)          (EIC_WAKEUP_WAKEUPEN10_Msk & ((value) << EIC_WAKEUP_WAKEUPEN10_Pos))
    349. 

  349. #define EIC_WAKEUP_WAKEUPEN11_Pos             _U_(11)                                              /**< (EIC_WAKEUP) External Interrupt 11 Wake-up Enable Position */
    350. 

  350. #define EIC_WAKEUP_WAKEUPEN11_Msk             (_U_(0x1) << EIC_WAKEUP_WAKEUPEN11_Pos)              /**< (EIC_WAKEUP) External Interrupt 11 Wake-up Enable Mask */
    351. 

  351. #define EIC_WAKEUP_WAKEUPEN11(value)          (EIC_WAKEUP_WAKEUPEN11_Msk & ((value) << EIC_WAKEUP_WAKEUPEN11_Pos))
    352. 

  352. #define EIC_WAKEUP_WAKEUPEN12_Pos             _U_(12)                                              /**< (EIC_WAKEUP) External Interrupt 12 Wake-up Enable Position */
    353. 

  353. #define EIC_WAKEUP_WAKEUPEN12_Msk             (_U_(0x1) << EIC_WAKEUP_WAKEUPEN12_Pos)              /**< (EIC_WAKEUP) External Interrupt 12 Wake-up Enable Mask */
    354. 

  354. #define EIC_WAKEUP_WAKEUPEN12(value)          (EIC_WAKEUP_WAKEUPEN12_Msk & ((value) << EIC_WAKEUP_WAKEUPEN12_Pos))
    355. 

  355. #define EIC_WAKEUP_WAKEUPEN13_Pos             _U_(13)                                              /**< (EIC_WAKEUP) External Interrupt 13 Wake-up Enable Position */
    356. 

  356. #define EIC_WAKEUP_WAKEUPEN13_Msk             (_U_(0x1) << EIC_WAKEUP_WAKEUPEN13_Pos)              /**< (EIC_WAKEUP) External Interrupt 13 Wake-up Enable Mask */
    357. 

  357. #define EIC_WAKEUP_WAKEUPEN13(value)          (EIC_WAKEUP_WAKEUPEN13_Msk & ((value) << EIC_WAKEUP_WAKEUPEN13_Pos))
    358. 

  358. #define EIC_WAKEUP_WAKEUPEN14_Pos             _U_(14)                                              /**< (EIC_WAKEUP) External Interrupt 14 Wake-up Enable Position */
    359. 

  359. #define EIC_WAKEUP_WAKEUPEN14_Msk             (_U_(0x1) << EIC_WAKEUP_WAKEUPEN14_Pos)              /**< (EIC_WAKEUP) External Interrupt 14 Wake-up Enable Mask */
    360. 

  360. #define EIC_WAKEUP_WAKEUPEN14(value)          (EIC_WAKEUP_WAKEUPEN14_Msk & ((value) << EIC_WAKEUP_WAKEUPEN14_Pos))
    361. 

  361. #define EIC_WAKEUP_WAKEUPEN15_Pos             _U_(15)                                              /**< (EIC_WAKEUP) External Interrupt 15 Wake-up Enable Position */
    362. 

  362. #define EIC_WAKEUP_WAKEUPEN15_Msk             (_U_(0x1) << EIC_WAKEUP_WAKEUPEN15_Pos)              /**< (EIC_WAKEUP) External Interrupt 15 Wake-up Enable Mask */
    363. 

  363. #define EIC_WAKEUP_WAKEUPEN15(value)          (EIC_WAKEUP_WAKEUPEN15_Msk & ((value) << EIC_WAKEUP_WAKEUPEN15_Pos))
    364. 

  364. #define EIC_WAKEUP_Msk                        _U_(0x0000FFFF)                                      /**< (EIC_WAKEUP) Register Mask  */
    365. 

  365. 

  366. #define EIC_WAKEUP_WAKEUPEN_Pos               _U_(0)                                               /**< (EIC_WAKEUP Position) External Interrupt x5 Wake-up Enable */
    367. 

  367. #define EIC_WAKEUP_WAKEUPEN_Msk               (_U_(0xFFFF) << EIC_WAKEUP_WAKEUPEN_Pos)             /**< (EIC_WAKEUP Mask) WAKEUPEN */
    368. 

  368. #define EIC_WAKEUP_WAKEUPEN(value)            (EIC_WAKEUP_WAKEUPEN_Msk & ((value) << EIC_WAKEUP_WAKEUPEN_Pos)) 
    369. 

  369. 

  370. /* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
    371. 

  371. #define EIC_CONFIG_RESETVALUE                 _U_(0x00)                                            /**<  (EIC_CONFIG) Configuration n  Reset Value */
    372. 

  372. 

  373. #define EIC_CONFIG_SENSE0_Pos                 _U_(0)                                               /**< (EIC_CONFIG) Input Sense 0 Configuration Position */
    374. 

  374. #define EIC_CONFIG_SENSE0_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)                  /**< (EIC_CONFIG) Input Sense 0 Configuration Mask */
    375. 

  375. #define EIC_CONFIG_SENSE0(value)              (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
    376. 

  376. #define   EIC_CONFIG_SENSE0_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    377. 

  377. #define   EIC_CONFIG_SENSE0_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising-edge detection  */
    378. 

  378. #define   EIC_CONFIG_SENSE0_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling-edge detection  */
    379. 

  379. #define   EIC_CONFIG_SENSE0_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both-edges detection  */
    380. 

  380. #define   EIC_CONFIG_SENSE0_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High-level detection  */
    381. 

  381. #define   EIC_CONFIG_SENSE0_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low-level detection  */
    382. 

  382. #define EIC_CONFIG_SENSE0_NONE                (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) No detection Position  */
    383. 

  383. #define EIC_CONFIG_SENSE0_RISE                (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Rising-edge detection Position  */
    384. 

  384. #define EIC_CONFIG_SENSE0_FALL                (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Falling-edge detection Position  */
    385. 

  385. #define EIC_CONFIG_SENSE0_BOTH                (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Both-edges detection Position  */
    386. 

  386. #define EIC_CONFIG_SENSE0_HIGH                (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) High-level detection Position  */
    387. 

  387. #define EIC_CONFIG_SENSE0_LOW                 (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos) /**< (EIC_CONFIG) Low-level detection Position  */
    388. 

  388. #define EIC_CONFIG_FILTEN0_Pos                _U_(3)                                               /**< (EIC_CONFIG) Filter 0 Enable Position */
    389. 

  389. #define EIC_CONFIG_FILTEN0_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)                 /**< (EIC_CONFIG) Filter 0 Enable Mask */
    390. 

  390. #define EIC_CONFIG_FILTEN0(value)             (EIC_CONFIG_FILTEN0_Msk & ((value) << EIC_CONFIG_FILTEN0_Pos))
    391. 

  391. #define EIC_CONFIG_SENSE1_Pos                 _U_(4)                                               /**< (EIC_CONFIG) Input Sense 1 Configuration Position */
    392. 

  392. #define EIC_CONFIG_SENSE1_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)                  /**< (EIC_CONFIG) Input Sense 1 Configuration Mask */
    393. 

  393. #define EIC_CONFIG_SENSE1(value)              (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
    394. 

  394. #define   EIC_CONFIG_SENSE1_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    395. 

  395. #define   EIC_CONFIG_SENSE1_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    396. 

  396. #define   EIC_CONFIG_SENSE1_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    397. 

  397. #define   EIC_CONFIG_SENSE1_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    398. 

  398. #define   EIC_CONFIG_SENSE1_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    399. 

  399. #define   EIC_CONFIG_SENSE1_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    400. 

  400. #define EIC_CONFIG_SENSE1_NONE                (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) No detection Position  */
    401. 

  401. #define EIC_CONFIG_SENSE1_RISE                (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    402. 

  402. #define EIC_CONFIG_SENSE1_FALL                (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    403. 

  403. #define EIC_CONFIG_SENSE1_BOTH                (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    404. 

  404. #define EIC_CONFIG_SENSE1_HIGH                (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) High level detection Position  */
    405. 

  405. #define EIC_CONFIG_SENSE1_LOW                 (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    406. 

  406. #define EIC_CONFIG_FILTEN1_Pos                _U_(7)                                               /**< (EIC_CONFIG) Filter 1 Enable Position */
    407. 

  407. #define EIC_CONFIG_FILTEN1_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)                 /**< (EIC_CONFIG) Filter 1 Enable Mask */
    408. 

  408. #define EIC_CONFIG_FILTEN1(value)             (EIC_CONFIG_FILTEN1_Msk & ((value) << EIC_CONFIG_FILTEN1_Pos))
    409. 

  409. #define EIC_CONFIG_SENSE2_Pos                 _U_(8)                                               /**< (EIC_CONFIG) Input Sense 2 Configuration Position */
    410. 

  410. #define EIC_CONFIG_SENSE2_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)                  /**< (EIC_CONFIG) Input Sense 2 Configuration Mask */
    411. 

  411. #define EIC_CONFIG_SENSE2(value)              (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
    412. 

  412. #define   EIC_CONFIG_SENSE2_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    413. 

  413. #define   EIC_CONFIG_SENSE2_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    414. 

  414. #define   EIC_CONFIG_SENSE2_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    415. 

  415. #define   EIC_CONFIG_SENSE2_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    416. 

  416. #define   EIC_CONFIG_SENSE2_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    417. 

  417. #define   EIC_CONFIG_SENSE2_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    418. 

  418. #define EIC_CONFIG_SENSE2_NONE                (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) No detection Position  */
    419. 

  419. #define EIC_CONFIG_SENSE2_RISE                (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    420. 

  420. #define EIC_CONFIG_SENSE2_FALL                (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    421. 

  421. #define EIC_CONFIG_SENSE2_BOTH                (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    422. 

  422. #define EIC_CONFIG_SENSE2_HIGH                (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) High level detection Position  */
    423. 

  423. #define EIC_CONFIG_SENSE2_LOW                 (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    424. 

  424. #define EIC_CONFIG_FILTEN2_Pos                _U_(11)                                              /**< (EIC_CONFIG) Filter 2 Enable Position */
    425. 

  425. #define EIC_CONFIG_FILTEN2_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)                 /**< (EIC_CONFIG) Filter 2 Enable Mask */
    426. 

  426. #define EIC_CONFIG_FILTEN2(value)             (EIC_CONFIG_FILTEN2_Msk & ((value) << EIC_CONFIG_FILTEN2_Pos))
    427. 

  427. #define EIC_CONFIG_SENSE3_Pos                 _U_(12)                                              /**< (EIC_CONFIG) Input Sense 3 Configuration Position */
    428. 

  428. #define EIC_CONFIG_SENSE3_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)                  /**< (EIC_CONFIG) Input Sense 3 Configuration Mask */
    429. 

  429. #define EIC_CONFIG_SENSE3(value)              (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
    430. 

  430. #define   EIC_CONFIG_SENSE3_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    431. 

  431. #define   EIC_CONFIG_SENSE3_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    432. 

  432. #define   EIC_CONFIG_SENSE3_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    433. 

  433. #define   EIC_CONFIG_SENSE3_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    434. 

  434. #define   EIC_CONFIG_SENSE3_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    435. 

  435. #define   EIC_CONFIG_SENSE3_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    436. 

  436. #define EIC_CONFIG_SENSE3_NONE                (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) No detection Position  */
    437. 

  437. #define EIC_CONFIG_SENSE3_RISE                (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    438. 

  438. #define EIC_CONFIG_SENSE3_FALL                (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    439. 

  439. #define EIC_CONFIG_SENSE3_BOTH                (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    440. 

  440. #define EIC_CONFIG_SENSE3_HIGH                (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) High level detection Position  */
    441. 

  441. #define EIC_CONFIG_SENSE3_LOW                 (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    442. 

  442. #define EIC_CONFIG_FILTEN3_Pos                _U_(15)                                              /**< (EIC_CONFIG) Filter 3 Enable Position */
    443. 

  443. #define EIC_CONFIG_FILTEN3_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)                 /**< (EIC_CONFIG) Filter 3 Enable Mask */
    444. 

  444. #define EIC_CONFIG_FILTEN3(value)             (EIC_CONFIG_FILTEN3_Msk & ((value) << EIC_CONFIG_FILTEN3_Pos))
    445. 

  445. #define EIC_CONFIG_SENSE4_Pos                 _U_(16)                                              /**< (EIC_CONFIG) Input Sense 4 Configuration Position */
    446. 

  446. #define EIC_CONFIG_SENSE4_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)                  /**< (EIC_CONFIG) Input Sense 4 Configuration Mask */
    447. 

  447. #define EIC_CONFIG_SENSE4(value)              (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
    448. 

  448. #define   EIC_CONFIG_SENSE4_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    449. 

  449. #define   EIC_CONFIG_SENSE4_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    450. 

  450. #define   EIC_CONFIG_SENSE4_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    451. 

  451. #define   EIC_CONFIG_SENSE4_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    452. 

  452. #define   EIC_CONFIG_SENSE4_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    453. 

  453. #define   EIC_CONFIG_SENSE4_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    454. 

  454. #define EIC_CONFIG_SENSE4_NONE                (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) No detection Position  */
    455. 

  455. #define EIC_CONFIG_SENSE4_RISE                (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    456. 

  456. #define EIC_CONFIG_SENSE4_FALL                (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    457. 

  457. #define EIC_CONFIG_SENSE4_BOTH                (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    458. 

  458. #define EIC_CONFIG_SENSE4_HIGH                (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) High level detection Position  */
    459. 

  459. #define EIC_CONFIG_SENSE4_LOW                 (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    460. 

  460. #define EIC_CONFIG_FILTEN4_Pos                _U_(19)                                              /**< (EIC_CONFIG) Filter 4 Enable Position */
    461. 

  461. #define EIC_CONFIG_FILTEN4_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)                 /**< (EIC_CONFIG) Filter 4 Enable Mask */
    462. 

  462. #define EIC_CONFIG_FILTEN4(value)             (EIC_CONFIG_FILTEN4_Msk & ((value) << EIC_CONFIG_FILTEN4_Pos))
    463. 

  463. #define EIC_CONFIG_SENSE5_Pos                 _U_(20)                                              /**< (EIC_CONFIG) Input Sense 5 Configuration Position */
    464. 

  464. #define EIC_CONFIG_SENSE5_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)                  /**< (EIC_CONFIG) Input Sense 5 Configuration Mask */
    465. 

  465. #define EIC_CONFIG_SENSE5(value)              (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
    466. 

  466. #define   EIC_CONFIG_SENSE5_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    467. 

  467. #define   EIC_CONFIG_SENSE5_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    468. 

  468. #define   EIC_CONFIG_SENSE5_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    469. 

  469. #define   EIC_CONFIG_SENSE5_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    470. 

  470. #define   EIC_CONFIG_SENSE5_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    471. 

  471. #define   EIC_CONFIG_SENSE5_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    472. 

  472. #define EIC_CONFIG_SENSE5_NONE                (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) No detection Position  */
    473. 

  473. #define EIC_CONFIG_SENSE5_RISE                (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    474. 

  474. #define EIC_CONFIG_SENSE5_FALL                (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    475. 

  475. #define EIC_CONFIG_SENSE5_BOTH                (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    476. 

  476. #define EIC_CONFIG_SENSE5_HIGH                (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) High level detection Position  */
    477. 

  477. #define EIC_CONFIG_SENSE5_LOW                 (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    478. 

  478. #define EIC_CONFIG_FILTEN5_Pos                _U_(23)                                              /**< (EIC_CONFIG) Filter 5 Enable Position */
    479. 

  479. #define EIC_CONFIG_FILTEN5_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)                 /**< (EIC_CONFIG) Filter 5 Enable Mask */
    480. 

  480. #define EIC_CONFIG_FILTEN5(value)             (EIC_CONFIG_FILTEN5_Msk & ((value) << EIC_CONFIG_FILTEN5_Pos))
    481. 

  481. #define EIC_CONFIG_SENSE6_Pos                 _U_(24)                                              /**< (EIC_CONFIG) Input Sense 6 Configuration Position */
    482. 

  482. #define EIC_CONFIG_SENSE6_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)                  /**< (EIC_CONFIG) Input Sense 6 Configuration Mask */
    483. 

  483. #define EIC_CONFIG_SENSE6(value)              (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
    484. 

  484. #define   EIC_CONFIG_SENSE6_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    485. 

  485. #define   EIC_CONFIG_SENSE6_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    486. 

  486. #define   EIC_CONFIG_SENSE6_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    487. 

  487. #define   EIC_CONFIG_SENSE6_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    488. 

  488. #define   EIC_CONFIG_SENSE6_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    489. 

  489. #define   EIC_CONFIG_SENSE6_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    490. 

  490. #define EIC_CONFIG_SENSE6_NONE                (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) No detection Position  */
    491. 

  491. #define EIC_CONFIG_SENSE6_RISE                (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    492. 

  492. #define EIC_CONFIG_SENSE6_FALL                (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    493. 

  493. #define EIC_CONFIG_SENSE6_BOTH                (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    494. 

  494. #define EIC_CONFIG_SENSE6_HIGH                (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) High level detection Position  */
    495. 

  495. #define EIC_CONFIG_SENSE6_LOW                 (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    496. 

  496. #define EIC_CONFIG_FILTEN6_Pos                _U_(27)                                              /**< (EIC_CONFIG) Filter 6 Enable Position */
    497. 

  497. #define EIC_CONFIG_FILTEN6_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)                 /**< (EIC_CONFIG) Filter 6 Enable Mask */
    498. 

  498. #define EIC_CONFIG_FILTEN6(value)             (EIC_CONFIG_FILTEN6_Msk & ((value) << EIC_CONFIG_FILTEN6_Pos))
    499. 

  499. #define EIC_CONFIG_SENSE7_Pos                 _U_(28)                                              /**< (EIC_CONFIG) Input Sense 7 Configuration Position */
    500. 

  500. #define EIC_CONFIG_SENSE7_Msk                 (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)                  /**< (EIC_CONFIG) Input Sense 7 Configuration Mask */
    501. 

  501. #define EIC_CONFIG_SENSE7(value)              (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
    502. 

  502. #define   EIC_CONFIG_SENSE7_NONE_Val          _U_(0x0)                                             /**< (EIC_CONFIG) No detection  */
    503. 

  503. #define   EIC_CONFIG_SENSE7_RISE_Val          _U_(0x1)                                             /**< (EIC_CONFIG) Rising edge detection  */
    504. 

  504. #define   EIC_CONFIG_SENSE7_FALL_Val          _U_(0x2)                                             /**< (EIC_CONFIG) Falling edge detection  */
    505. 

  505. #define   EIC_CONFIG_SENSE7_BOTH_Val          _U_(0x3)                                             /**< (EIC_CONFIG) Both edges detection  */
    506. 

  506. #define   EIC_CONFIG_SENSE7_HIGH_Val          _U_(0x4)                                             /**< (EIC_CONFIG) High level detection  */
    507. 

  507. #define   EIC_CONFIG_SENSE7_LOW_Val           _U_(0x5)                                             /**< (EIC_CONFIG) Low level detection  */
    508. 

  508. #define EIC_CONFIG_SENSE7_NONE                (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) No detection Position  */
    509. 

  509. #define EIC_CONFIG_SENSE7_RISE                (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Rising edge detection Position  */
    510. 

  510. #define EIC_CONFIG_SENSE7_FALL                (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Falling edge detection Position  */
    511. 

  511. #define EIC_CONFIG_SENSE7_BOTH                (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Both edges detection Position  */
    512. 

  512. #define EIC_CONFIG_SENSE7_HIGH                (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) High level detection Position  */
    513. 

  513. #define EIC_CONFIG_SENSE7_LOW                 (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos) /**< (EIC_CONFIG) Low level detection Position  */
    514. 

  514. #define EIC_CONFIG_FILTEN7_Pos                _U_(31)                                              /**< (EIC_CONFIG) Filter 7 Enable Position */
    515. 

  515. #define EIC_CONFIG_FILTEN7_Msk                (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)                 /**< (EIC_CONFIG) Filter 7 Enable Mask */
    516. 

  516. #define EIC_CONFIG_FILTEN7(value)             (EIC_CONFIG_FILTEN7_Msk & ((value) << EIC_CONFIG_FILTEN7_Pos))
    517. 

  517. #define EIC_CONFIG_Msk                        _U_(0xFFFFFFFF)                                      /**< (EIC_CONFIG) Register Mask  */
    518. 

  518. 

  519. 

  520. /** \brief EIC register offsets definitions */
    521. 

  521. #define EIC_CTRL_REG_OFST              (0x00)              /**< (EIC_CTRL) Control Offset */
    522. 

  522. #define EIC_STATUS_REG_OFST            (0x01)              /**< (EIC_STATUS) Status Offset */
    523. 

  523. #define EIC_NMICTRL_REG_OFST           (0x02)              /**< (EIC_NMICTRL) Non-Maskable Interrupt Control Offset */
    524. 

  524. #define EIC_NMIFLAG_REG_OFST           (0x03)              /**< (EIC_NMIFLAG) Non-Maskable Interrupt Flag Status and Clear Offset */
    525. 

  525. #define EIC_EVCTRL_REG_OFST            (0x04)              /**< (EIC_EVCTRL) Event Control Offset */
    526. 

  526. #define EIC_INTENCLR_REG_OFST          (0x08)              /**< (EIC_INTENCLR) Interrupt Enable Clear Offset */
    527. 

  527. #define EIC_INTENSET_REG_OFST          (0x0C)              /**< (EIC_INTENSET) Interrupt Enable Set Offset */
    528. 

  528. #define EIC_INTFLAG_REG_OFST           (0x10)              /**< (EIC_INTFLAG) Interrupt Flag Status and Clear Offset */
    529. 

  529. #define EIC_WAKEUP_REG_OFST            (0x14)              /**< (EIC_WAKEUP) Wake-Up Enable Offset */
    530. 

  530. #define EIC_CONFIG_REG_OFST            (0x18)              /**< (EIC_CONFIG) Configuration n Offset */
    531. 

  531. #define EIC_CONFIG0_REG_OFST           (0x18)              /**< (EIC_CONFIG0) Configuration n Offset */
    532. 

  532. #define EIC_CONFIG1_REG_OFST           (0x1C)              /**< (EIC_CONFIG1) Configuration n Offset */
    533. 

  533. 

  534. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    535. 

  535. /** \brief EIC register API structure */
    536. 

  536. typedef struct
    537. 

  537. {  /* External Interrupt Controller */
    538. 

  538.   __IO  uint8_t                        EIC_CTRL;           /**< Offset: 0x00 (R/W  8) Control */
    539. 

  539.   __I   uint8_t                        EIC_STATUS;         /**< Offset: 0x01 (R/   8) Status */
    540. 

  540.   __IO  uint8_t                        EIC_NMICTRL;        /**< Offset: 0x02 (R/W  8) Non-Maskable Interrupt Control */
    541. 

  541.   __IO  uint8_t                        EIC_NMIFLAG;        /**< Offset: 0x03 (R/W  8) Non-Maskable Interrupt Flag Status and Clear */
    542. 

  542.   __IO  uint32_t                       EIC_EVCTRL;         /**< Offset: 0x04 (R/W  32) Event Control */
    543. 

  543.   __IO  uint32_t                       EIC_INTENCLR;       /**< Offset: 0x08 (R/W  32) Interrupt Enable Clear */
    544. 

  544.   __IO  uint32_t                       EIC_INTENSET;       /**< Offset: 0x0C (R/W  32) Interrupt Enable Set */
    545. 

  545.   __IO  uint32_t                       EIC_INTFLAG;        /**< Offset: 0x10 (R/W  32) Interrupt Flag Status and Clear */
    546. 

  546.   __IO  uint32_t                       EIC_WAKEUP;         /**< Offset: 0x14 (R/W  32) Wake-Up Enable */
    547. 

  547.   __IO  uint32_t                       EIC_CONFIG[2];      /**< Offset: 0x18 (R/W  32) Configuration n */
    548. 

  548. } eic_registers_t;
    549. 

  549. 

  550. 

  551. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    552. 

  552. #endif /* _SAMD21_EIC_COMPONENT_H_ */
    553.