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evsys.h

evsys.h 53 KB
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  1. /**
    2. 

  2.  * \brief Component description for EVSYS
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_EVSYS_COMPONENT_H_
    25. 

  25. #define _SAMD21_EVSYS_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR EVSYS                                        */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
    32. 

  32. #define EVSYS_CTRL_RESETVALUE                 _U_(0x00)                                            /**<  (EVSYS_CTRL) Control  Reset Value */
    33. 

  33. 

  34. #define EVSYS_CTRL_SWRST_Pos                  _U_(0)                                               /**< (EVSYS_CTRL) Software Reset Position */
    35. 

  35. #define EVSYS_CTRL_SWRST_Msk                  (_U_(0x1) << EVSYS_CTRL_SWRST_Pos)                   /**< (EVSYS_CTRL) Software Reset Mask */
    36. 

  36. #define EVSYS_CTRL_SWRST(value)               (EVSYS_CTRL_SWRST_Msk & ((value) << EVSYS_CTRL_SWRST_Pos))
    37. 

  37. #define EVSYS_CTRL_GCLKREQ_Pos                _U_(4)                                               /**< (EVSYS_CTRL) Generic Clock Requests Position */
    38. 

  38. #define EVSYS_CTRL_GCLKREQ_Msk                (_U_(0x1) << EVSYS_CTRL_GCLKREQ_Pos)                 /**< (EVSYS_CTRL) Generic Clock Requests Mask */
    39. 

  39. #define EVSYS_CTRL_GCLKREQ(value)             (EVSYS_CTRL_GCLKREQ_Msk & ((value) << EVSYS_CTRL_GCLKREQ_Pos))
    40. 

  40. #define EVSYS_CTRL_Msk                        _U_(0x11)                                            /**< (EVSYS_CTRL) Register Mask  */
    41. 

  41. 

  42. 

  43. /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
    44. 

  44. #define EVSYS_CHANNEL_RESETVALUE              _U_(0x00)                                            /**<  (EVSYS_CHANNEL) Channel  Reset Value */
    45. 

  45. 

  46. #define EVSYS_CHANNEL_CHANNEL_Pos             _U_(0)                                               /**< (EVSYS_CHANNEL) Channel Selection Position */
    47. 

  47. #define EVSYS_CHANNEL_CHANNEL_Msk             (_U_(0xF) << EVSYS_CHANNEL_CHANNEL_Pos)              /**< (EVSYS_CHANNEL) Channel Selection Mask */
    48. 

  48. #define EVSYS_CHANNEL_CHANNEL(value)          (EVSYS_CHANNEL_CHANNEL_Msk & ((value) << EVSYS_CHANNEL_CHANNEL_Pos))
    49. 

  49. #define EVSYS_CHANNEL_SWEVT_Pos               _U_(8)                                               /**< (EVSYS_CHANNEL) Software Event Position */
    50. 

  50. #define EVSYS_CHANNEL_SWEVT_Msk               (_U_(0x1) << EVSYS_CHANNEL_SWEVT_Pos)                /**< (EVSYS_CHANNEL) Software Event Mask */
    51. 

  51. #define EVSYS_CHANNEL_SWEVT(value)            (EVSYS_CHANNEL_SWEVT_Msk & ((value) << EVSYS_CHANNEL_SWEVT_Pos))
    52. 

  52. #define EVSYS_CHANNEL_EVGEN_Pos               _U_(16)                                              /**< (EVSYS_CHANNEL) Event Generator Selection Position */
    53. 

  53. #define EVSYS_CHANNEL_EVGEN_Msk               (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)               /**< (EVSYS_CHANNEL) Event Generator Selection Mask */
    54. 

  54. #define EVSYS_CHANNEL_EVGEN(value)            (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
    55. 

  55. #define EVSYS_CHANNEL_PATH_Pos                _U_(24)                                              /**< (EVSYS_CHANNEL) Path Selection Position */
    56. 

  56. #define EVSYS_CHANNEL_PATH_Msk                (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)                 /**< (EVSYS_CHANNEL) Path Selection Mask */
    57. 

  57. #define EVSYS_CHANNEL_PATH(value)             (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
    58. 

  58. #define   EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val  _U_(0x0)                                             /**< (EVSYS_CHANNEL) Synchronous path  */
    59. 

  59. #define   EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1)                                             /**< (EVSYS_CHANNEL) Resynchronized path  */
    60. 

  60. #define   EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2)                                             /**< (EVSYS_CHANNEL) Asynchronous path  */
    61. 

  61. #define EVSYS_CHANNEL_PATH_SYNCHRONOUS        (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Synchronous path Position  */
    62. 

  62. #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED     (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Resynchronized path Position  */
    63. 

  63. #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS       (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) /**< (EVSYS_CHANNEL) Asynchronous path Position  */
    64. 

  64. #define EVSYS_CHANNEL_EDGSEL_Pos              _U_(26)                                              /**< (EVSYS_CHANNEL) Edge Detection Selection Position */
    65. 

  65. #define EVSYS_CHANNEL_EDGSEL_Msk              (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)               /**< (EVSYS_CHANNEL) Edge Detection Selection Mask */
    66. 

  66. #define EVSYS_CHANNEL_EDGSEL(value)           (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
    67. 

  67. #define   EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0)                                             /**< (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path  */
    68. 

  68. #define   EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1)                                             /**< (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path  */
    69. 

  69. #define   EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2)                                             /**< (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path  */
    70. 

  70. #define   EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3)                                             /**< (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path  */
    71. 

  71. #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT    (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path Position  */
    72. 

  72. #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE      (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path Position  */
    73. 

  73. #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE     (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path Position  */
    74. 

  74. #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES       (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) /**< (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path Position  */
    75. 

  75. #define EVSYS_CHANNEL_Msk                     _U_(0x0F7F010F)                                      /**< (EVSYS_CHANNEL) Register Mask  */
    76. 

  76. 

  77. 

  78. /* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
    79. 

  79. #define EVSYS_USER_RESETVALUE                 _U_(0x00)                                            /**<  (EVSYS_USER) User Multiplexer  Reset Value */
    80. 

  80. 

  81. #define EVSYS_USER_USER_Pos                   _U_(0)                                               /**< (EVSYS_USER) User Multiplexer Selection Position */
    82. 

  82. #define EVSYS_USER_USER_Msk                   (_U_(0x1F) << EVSYS_USER_USER_Pos)                   /**< (EVSYS_USER) User Multiplexer Selection Mask */
    83. 

  83. #define EVSYS_USER_USER(value)                (EVSYS_USER_USER_Msk & ((value) << EVSYS_USER_USER_Pos))
    84. 

  84. #define EVSYS_USER_CHANNEL_Pos                _U_(8)                                               /**< (EVSYS_USER) Channel Event Selection Position */
    85. 

  85. #define EVSYS_USER_CHANNEL_Msk                (_U_(0x1F) << EVSYS_USER_CHANNEL_Pos)                /**< (EVSYS_USER) Channel Event Selection Mask */
    86. 

  86. #define EVSYS_USER_CHANNEL(value)             (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
    87. 

  87. #define   EVSYS_USER_CHANNEL_0_Val            _U_(0x0)                                             /**< (EVSYS_USER) No Channel Output Selected  */
    88. 

  88. #define EVSYS_USER_CHANNEL_0                  (EVSYS_USER_CHANNEL_0_Val << EVSYS_USER_CHANNEL_Pos) /**< (EVSYS_USER) No Channel Output Selected Position  */
    89. 

  89. #define EVSYS_USER_Msk                        _U_(0x1F1F)                                          /**< (EVSYS_USER) Register Mask  */
    90. 

  90. 

  91. 

  92. /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) ( R/ 32) Channel Status -------- */
    93. 

  93. #define EVSYS_CHSTATUS_RESETVALUE             _U_(0xF00FF)                                         /**<  (EVSYS_CHSTATUS) Channel Status  Reset Value */
    94. 

  94. 

  95. #define EVSYS_CHSTATUS_USRRDY0_Pos            _U_(0)                                               /**< (EVSYS_CHSTATUS) Channel 0 User Ready Position */
    96. 

  96. #define EVSYS_CHSTATUS_USRRDY0_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY0_Pos)             /**< (EVSYS_CHSTATUS) Channel 0 User Ready Mask */
    97. 

  97. #define EVSYS_CHSTATUS_USRRDY0(value)         (EVSYS_CHSTATUS_USRRDY0_Msk & ((value) << EVSYS_CHSTATUS_USRRDY0_Pos))
    98. 

  98. #define EVSYS_CHSTATUS_USRRDY1_Pos            _U_(1)                                               /**< (EVSYS_CHSTATUS) Channel 1 User Ready Position */
    99. 

  99. #define EVSYS_CHSTATUS_USRRDY1_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY1_Pos)             /**< (EVSYS_CHSTATUS) Channel 1 User Ready Mask */
    100. 

  100. #define EVSYS_CHSTATUS_USRRDY1(value)         (EVSYS_CHSTATUS_USRRDY1_Msk & ((value) << EVSYS_CHSTATUS_USRRDY1_Pos))
    101. 

  101. #define EVSYS_CHSTATUS_USRRDY2_Pos            _U_(2)                                               /**< (EVSYS_CHSTATUS) Channel 2 User Ready Position */
    102. 

  102. #define EVSYS_CHSTATUS_USRRDY2_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY2_Pos)             /**< (EVSYS_CHSTATUS) Channel 2 User Ready Mask */
    103. 

  103. #define EVSYS_CHSTATUS_USRRDY2(value)         (EVSYS_CHSTATUS_USRRDY2_Msk & ((value) << EVSYS_CHSTATUS_USRRDY2_Pos))
    104. 

  104. #define EVSYS_CHSTATUS_USRRDY3_Pos            _U_(3)                                               /**< (EVSYS_CHSTATUS) Channel 3 User Ready Position */
    105. 

  105. #define EVSYS_CHSTATUS_USRRDY3_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY3_Pos)             /**< (EVSYS_CHSTATUS) Channel 3 User Ready Mask */
    106. 

  106. #define EVSYS_CHSTATUS_USRRDY3(value)         (EVSYS_CHSTATUS_USRRDY3_Msk & ((value) << EVSYS_CHSTATUS_USRRDY3_Pos))
    107. 

  107. #define EVSYS_CHSTATUS_USRRDY4_Pos            _U_(4)                                               /**< (EVSYS_CHSTATUS) Channel 4 User Ready Position */
    108. 

  108. #define EVSYS_CHSTATUS_USRRDY4_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY4_Pos)             /**< (EVSYS_CHSTATUS) Channel 4 User Ready Mask */
    109. 

  109. #define EVSYS_CHSTATUS_USRRDY4(value)         (EVSYS_CHSTATUS_USRRDY4_Msk & ((value) << EVSYS_CHSTATUS_USRRDY4_Pos))
    110. 

  110. #define EVSYS_CHSTATUS_USRRDY5_Pos            _U_(5)                                               /**< (EVSYS_CHSTATUS) Channel 5 User Ready Position */
    111. 

  111. #define EVSYS_CHSTATUS_USRRDY5_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY5_Pos)             /**< (EVSYS_CHSTATUS) Channel 5 User Ready Mask */
    112. 

  112. #define EVSYS_CHSTATUS_USRRDY5(value)         (EVSYS_CHSTATUS_USRRDY5_Msk & ((value) << EVSYS_CHSTATUS_USRRDY5_Pos))
    113. 

  113. #define EVSYS_CHSTATUS_USRRDY6_Pos            _U_(6)                                               /**< (EVSYS_CHSTATUS) Channel 6 User Ready Position */
    114. 

  114. #define EVSYS_CHSTATUS_USRRDY6_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY6_Pos)             /**< (EVSYS_CHSTATUS) Channel 6 User Ready Mask */
    115. 

  115. #define EVSYS_CHSTATUS_USRRDY6(value)         (EVSYS_CHSTATUS_USRRDY6_Msk & ((value) << EVSYS_CHSTATUS_USRRDY6_Pos))
    116. 

  116. #define EVSYS_CHSTATUS_USRRDY7_Pos            _U_(7)                                               /**< (EVSYS_CHSTATUS) Channel 7 User Ready Position */
    117. 

  117. #define EVSYS_CHSTATUS_USRRDY7_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY7_Pos)             /**< (EVSYS_CHSTATUS) Channel 7 User Ready Mask */
    118. 

  118. #define EVSYS_CHSTATUS_USRRDY7(value)         (EVSYS_CHSTATUS_USRRDY7_Msk & ((value) << EVSYS_CHSTATUS_USRRDY7_Pos))
    119. 

  119. #define EVSYS_CHSTATUS_CHBUSY0_Pos            _U_(8)                                               /**< (EVSYS_CHSTATUS) Channel 0 Busy Position */
    120. 

  120. #define EVSYS_CHSTATUS_CHBUSY0_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY0_Pos)             /**< (EVSYS_CHSTATUS) Channel 0 Busy Mask */
    121. 

  121. #define EVSYS_CHSTATUS_CHBUSY0(value)         (EVSYS_CHSTATUS_CHBUSY0_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY0_Pos))
    122. 

  122. #define EVSYS_CHSTATUS_CHBUSY1_Pos            _U_(9)                                               /**< (EVSYS_CHSTATUS) Channel 1 Busy Position */
    123. 

  123. #define EVSYS_CHSTATUS_CHBUSY1_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY1_Pos)             /**< (EVSYS_CHSTATUS) Channel 1 Busy Mask */
    124. 

  124. #define EVSYS_CHSTATUS_CHBUSY1(value)         (EVSYS_CHSTATUS_CHBUSY1_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY1_Pos))
    125. 

  125. #define EVSYS_CHSTATUS_CHBUSY2_Pos            _U_(10)                                              /**< (EVSYS_CHSTATUS) Channel 2 Busy Position */
    126. 

  126. #define EVSYS_CHSTATUS_CHBUSY2_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY2_Pos)             /**< (EVSYS_CHSTATUS) Channel 2 Busy Mask */
    127. 

  127. #define EVSYS_CHSTATUS_CHBUSY2(value)         (EVSYS_CHSTATUS_CHBUSY2_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY2_Pos))
    128. 

  128. #define EVSYS_CHSTATUS_CHBUSY3_Pos            _U_(11)                                              /**< (EVSYS_CHSTATUS) Channel 3 Busy Position */
    129. 

  129. #define EVSYS_CHSTATUS_CHBUSY3_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY3_Pos)             /**< (EVSYS_CHSTATUS) Channel 3 Busy Mask */
    130. 

  130. #define EVSYS_CHSTATUS_CHBUSY3(value)         (EVSYS_CHSTATUS_CHBUSY3_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY3_Pos))
    131. 

  131. #define EVSYS_CHSTATUS_CHBUSY4_Pos            _U_(12)                                              /**< (EVSYS_CHSTATUS) Channel 4 Busy Position */
    132. 

  132. #define EVSYS_CHSTATUS_CHBUSY4_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY4_Pos)             /**< (EVSYS_CHSTATUS) Channel 4 Busy Mask */
    133. 

  133. #define EVSYS_CHSTATUS_CHBUSY4(value)         (EVSYS_CHSTATUS_CHBUSY4_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY4_Pos))
    134. 

  134. #define EVSYS_CHSTATUS_CHBUSY5_Pos            _U_(13)                                              /**< (EVSYS_CHSTATUS) Channel 5 Busy Position */
    135. 

  135. #define EVSYS_CHSTATUS_CHBUSY5_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY5_Pos)             /**< (EVSYS_CHSTATUS) Channel 5 Busy Mask */
    136. 

  136. #define EVSYS_CHSTATUS_CHBUSY5(value)         (EVSYS_CHSTATUS_CHBUSY5_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY5_Pos))
    137. 

  137. #define EVSYS_CHSTATUS_CHBUSY6_Pos            _U_(14)                                              /**< (EVSYS_CHSTATUS) Channel 6 Busy Position */
    138. 

  138. #define EVSYS_CHSTATUS_CHBUSY6_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY6_Pos)             /**< (EVSYS_CHSTATUS) Channel 6 Busy Mask */
    139. 

  139. #define EVSYS_CHSTATUS_CHBUSY6(value)         (EVSYS_CHSTATUS_CHBUSY6_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY6_Pos))
    140. 

  140. #define EVSYS_CHSTATUS_CHBUSY7_Pos            _U_(15)                                              /**< (EVSYS_CHSTATUS) Channel 7 Busy Position */
    141. 

  141. #define EVSYS_CHSTATUS_CHBUSY7_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY7_Pos)             /**< (EVSYS_CHSTATUS) Channel 7 Busy Mask */
    142. 

  142. #define EVSYS_CHSTATUS_CHBUSY7(value)         (EVSYS_CHSTATUS_CHBUSY7_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY7_Pos))
    143. 

  143. #define EVSYS_CHSTATUS_USRRDY8_Pos            _U_(16)                                              /**< (EVSYS_CHSTATUS) Channel 8 User Ready Position */
    144. 

  144. #define EVSYS_CHSTATUS_USRRDY8_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY8_Pos)             /**< (EVSYS_CHSTATUS) Channel 8 User Ready Mask */
    145. 

  145. #define EVSYS_CHSTATUS_USRRDY8(value)         (EVSYS_CHSTATUS_USRRDY8_Msk & ((value) << EVSYS_CHSTATUS_USRRDY8_Pos))
    146. 

  146. #define EVSYS_CHSTATUS_USRRDY9_Pos            _U_(17)                                              /**< (EVSYS_CHSTATUS) Channel 9 User Ready Position */
    147. 

  147. #define EVSYS_CHSTATUS_USRRDY9_Msk            (_U_(0x1) << EVSYS_CHSTATUS_USRRDY9_Pos)             /**< (EVSYS_CHSTATUS) Channel 9 User Ready Mask */
    148. 

  148. #define EVSYS_CHSTATUS_USRRDY9(value)         (EVSYS_CHSTATUS_USRRDY9_Msk & ((value) << EVSYS_CHSTATUS_USRRDY9_Pos))
    149. 

  149. #define EVSYS_CHSTATUS_USRRDY10_Pos           _U_(18)                                              /**< (EVSYS_CHSTATUS) Channel 10 User Ready Position */
    150. 

  150. #define EVSYS_CHSTATUS_USRRDY10_Msk           (_U_(0x1) << EVSYS_CHSTATUS_USRRDY10_Pos)            /**< (EVSYS_CHSTATUS) Channel 10 User Ready Mask */
    151. 

  151. #define EVSYS_CHSTATUS_USRRDY10(value)        (EVSYS_CHSTATUS_USRRDY10_Msk & ((value) << EVSYS_CHSTATUS_USRRDY10_Pos))
    152. 

  152. #define EVSYS_CHSTATUS_USRRDY11_Pos           _U_(19)                                              /**< (EVSYS_CHSTATUS) Channel 11 User Ready Position */
    153. 

  153. #define EVSYS_CHSTATUS_USRRDY11_Msk           (_U_(0x1) << EVSYS_CHSTATUS_USRRDY11_Pos)            /**< (EVSYS_CHSTATUS) Channel 11 User Ready Mask */
    154. 

  154. #define EVSYS_CHSTATUS_USRRDY11(value)        (EVSYS_CHSTATUS_USRRDY11_Msk & ((value) << EVSYS_CHSTATUS_USRRDY11_Pos))
    155. 

  155. #define EVSYS_CHSTATUS_CHBUSY8_Pos            _U_(24)                                              /**< (EVSYS_CHSTATUS) Channel 8 Busy Position */
    156. 

  156. #define EVSYS_CHSTATUS_CHBUSY8_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY8_Pos)             /**< (EVSYS_CHSTATUS) Channel 8 Busy Mask */
    157. 

  157. #define EVSYS_CHSTATUS_CHBUSY8(value)         (EVSYS_CHSTATUS_CHBUSY8_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY8_Pos))
    158. 

  158. #define EVSYS_CHSTATUS_CHBUSY9_Pos            _U_(25)                                              /**< (EVSYS_CHSTATUS) Channel 9 Busy Position */
    159. 

  159. #define EVSYS_CHSTATUS_CHBUSY9_Msk            (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY9_Pos)             /**< (EVSYS_CHSTATUS) Channel 9 Busy Mask */
    160. 

  160. #define EVSYS_CHSTATUS_CHBUSY9(value)         (EVSYS_CHSTATUS_CHBUSY9_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY9_Pos))
    161. 

  161. #define EVSYS_CHSTATUS_CHBUSY10_Pos           _U_(26)                                              /**< (EVSYS_CHSTATUS) Channel 10 Busy Position */
    162. 

  162. #define EVSYS_CHSTATUS_CHBUSY10_Msk           (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY10_Pos)            /**< (EVSYS_CHSTATUS) Channel 10 Busy Mask */
    163. 

  163. #define EVSYS_CHSTATUS_CHBUSY10(value)        (EVSYS_CHSTATUS_CHBUSY10_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY10_Pos))
    164. 

  164. #define EVSYS_CHSTATUS_CHBUSY11_Pos           _U_(27)                                              /**< (EVSYS_CHSTATUS) Channel 11 Busy Position */
    165. 

  165. #define EVSYS_CHSTATUS_CHBUSY11_Msk           (_U_(0x1) << EVSYS_CHSTATUS_CHBUSY11_Pos)            /**< (EVSYS_CHSTATUS) Channel 11 Busy Mask */
    166. 

  166. #define EVSYS_CHSTATUS_CHBUSY11(value)        (EVSYS_CHSTATUS_CHBUSY11_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY11_Pos))
    167. 

  167. #define EVSYS_CHSTATUS_Msk                    _U_(0x0F0FFFFF)                                      /**< (EVSYS_CHSTATUS) Register Mask  */
    168. 

  168. 

  169. 

  170. /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
    171. 

  171. #define EVSYS_INTENCLR_RESETVALUE             _U_(0x00)                                            /**<  (EVSYS_INTENCLR) Interrupt Enable Clear  Reset Value */
    172. 

  172. 

  173. #define EVSYS_INTENCLR_OVR0_Pos               _U_(0)                                               /**< (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable Position */
    174. 

  174. #define EVSYS_INTENCLR_OVR0_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR0_Pos)                /**< (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable Mask */
    175. 

  175. #define EVSYS_INTENCLR_OVR0(value)            (EVSYS_INTENCLR_OVR0_Msk & ((value) << EVSYS_INTENCLR_OVR0_Pos))
    176. 

  176. #define EVSYS_INTENCLR_OVR1_Pos               _U_(1)                                               /**< (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable Position */
    177. 

  177. #define EVSYS_INTENCLR_OVR1_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR1_Pos)                /**< (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable Mask */
    178. 

  178. #define EVSYS_INTENCLR_OVR1(value)            (EVSYS_INTENCLR_OVR1_Msk & ((value) << EVSYS_INTENCLR_OVR1_Pos))
    179. 

  179. #define EVSYS_INTENCLR_OVR2_Pos               _U_(2)                                               /**< (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable Position */
    180. 

  180. #define EVSYS_INTENCLR_OVR2_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR2_Pos)                /**< (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable Mask */
    181. 

  181. #define EVSYS_INTENCLR_OVR2(value)            (EVSYS_INTENCLR_OVR2_Msk & ((value) << EVSYS_INTENCLR_OVR2_Pos))
    182. 

  182. #define EVSYS_INTENCLR_OVR3_Pos               _U_(3)                                               /**< (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable Position */
    183. 

  183. #define EVSYS_INTENCLR_OVR3_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR3_Pos)                /**< (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable Mask */
    184. 

  184. #define EVSYS_INTENCLR_OVR3(value)            (EVSYS_INTENCLR_OVR3_Msk & ((value) << EVSYS_INTENCLR_OVR3_Pos))
    185. 

  185. #define EVSYS_INTENCLR_OVR4_Pos               _U_(4)                                               /**< (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable Position */
    186. 

  186. #define EVSYS_INTENCLR_OVR4_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR4_Pos)                /**< (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable Mask */
    187. 

  187. #define EVSYS_INTENCLR_OVR4(value)            (EVSYS_INTENCLR_OVR4_Msk & ((value) << EVSYS_INTENCLR_OVR4_Pos))
    188. 

  188. #define EVSYS_INTENCLR_OVR5_Pos               _U_(5)                                               /**< (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable Position */
    189. 

  189. #define EVSYS_INTENCLR_OVR5_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR5_Pos)                /**< (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable Mask */
    190. 

  190. #define EVSYS_INTENCLR_OVR5(value)            (EVSYS_INTENCLR_OVR5_Msk & ((value) << EVSYS_INTENCLR_OVR5_Pos))
    191. 

  191. #define EVSYS_INTENCLR_OVR6_Pos               _U_(6)                                               /**< (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable Position */
    192. 

  192. #define EVSYS_INTENCLR_OVR6_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR6_Pos)                /**< (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable Mask */
    193. 

  193. #define EVSYS_INTENCLR_OVR6(value)            (EVSYS_INTENCLR_OVR6_Msk & ((value) << EVSYS_INTENCLR_OVR6_Pos))
    194. 

  194. #define EVSYS_INTENCLR_OVR7_Pos               _U_(7)                                               /**< (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable Position */
    195. 

  195. #define EVSYS_INTENCLR_OVR7_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR7_Pos)                /**< (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable Mask */
    196. 

  196. #define EVSYS_INTENCLR_OVR7(value)            (EVSYS_INTENCLR_OVR7_Msk & ((value) << EVSYS_INTENCLR_OVR7_Pos))
    197. 

  197. #define EVSYS_INTENCLR_EVD0_Pos               _U_(8)                                               /**< (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable Position */
    198. 

  198. #define EVSYS_INTENCLR_EVD0_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD0_Pos)                /**< (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable Mask */
    199. 

  199. #define EVSYS_INTENCLR_EVD0(value)            (EVSYS_INTENCLR_EVD0_Msk & ((value) << EVSYS_INTENCLR_EVD0_Pos))
    200. 

  200. #define EVSYS_INTENCLR_EVD1_Pos               _U_(9)                                               /**< (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable Position */
    201. 

  201. #define EVSYS_INTENCLR_EVD1_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD1_Pos)                /**< (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable Mask */
    202. 

  202. #define EVSYS_INTENCLR_EVD1(value)            (EVSYS_INTENCLR_EVD1_Msk & ((value) << EVSYS_INTENCLR_EVD1_Pos))
    203. 

  203. #define EVSYS_INTENCLR_EVD2_Pos               _U_(10)                                              /**< (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable Position */
    204. 

  204. #define EVSYS_INTENCLR_EVD2_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD2_Pos)                /**< (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable Mask */
    205. 

  205. #define EVSYS_INTENCLR_EVD2(value)            (EVSYS_INTENCLR_EVD2_Msk & ((value) << EVSYS_INTENCLR_EVD2_Pos))
    206. 

  206. #define EVSYS_INTENCLR_EVD3_Pos               _U_(11)                                              /**< (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable Position */
    207. 

  207. #define EVSYS_INTENCLR_EVD3_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD3_Pos)                /**< (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable Mask */
    208. 

  208. #define EVSYS_INTENCLR_EVD3(value)            (EVSYS_INTENCLR_EVD3_Msk & ((value) << EVSYS_INTENCLR_EVD3_Pos))
    209. 

  209. #define EVSYS_INTENCLR_EVD4_Pos               _U_(12)                                              /**< (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable Position */
    210. 

  210. #define EVSYS_INTENCLR_EVD4_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD4_Pos)                /**< (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable Mask */
    211. 

  211. #define EVSYS_INTENCLR_EVD4(value)            (EVSYS_INTENCLR_EVD4_Msk & ((value) << EVSYS_INTENCLR_EVD4_Pos))
    212. 

  212. #define EVSYS_INTENCLR_EVD5_Pos               _U_(13)                                              /**< (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable Position */
    213. 

  213. #define EVSYS_INTENCLR_EVD5_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD5_Pos)                /**< (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable Mask */
    214. 

  214. #define EVSYS_INTENCLR_EVD5(value)            (EVSYS_INTENCLR_EVD5_Msk & ((value) << EVSYS_INTENCLR_EVD5_Pos))
    215. 

  215. #define EVSYS_INTENCLR_EVD6_Pos               _U_(14)                                              /**< (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable Position */
    216. 

  216. #define EVSYS_INTENCLR_EVD6_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD6_Pos)                /**< (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable Mask */
    217. 

  217. #define EVSYS_INTENCLR_EVD6(value)            (EVSYS_INTENCLR_EVD6_Msk & ((value) << EVSYS_INTENCLR_EVD6_Pos))
    218. 

  218. #define EVSYS_INTENCLR_EVD7_Pos               _U_(15)                                              /**< (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable Position */
    219. 

  219. #define EVSYS_INTENCLR_EVD7_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD7_Pos)                /**< (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable Mask */
    220. 

  220. #define EVSYS_INTENCLR_EVD7(value)            (EVSYS_INTENCLR_EVD7_Msk & ((value) << EVSYS_INTENCLR_EVD7_Pos))
    221. 

  221. #define EVSYS_INTENCLR_OVR8_Pos               _U_(16)                                              /**< (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable Position */
    222. 

  222. #define EVSYS_INTENCLR_OVR8_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR8_Pos)                /**< (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable Mask */
    223. 

  223. #define EVSYS_INTENCLR_OVR8(value)            (EVSYS_INTENCLR_OVR8_Msk & ((value) << EVSYS_INTENCLR_OVR8_Pos))
    224. 

  224. #define EVSYS_INTENCLR_OVR9_Pos               _U_(17)                                              /**< (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable Position */
    225. 

  225. #define EVSYS_INTENCLR_OVR9_Msk               (_U_(0x1) << EVSYS_INTENCLR_OVR9_Pos)                /**< (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable Mask */
    226. 

  226. #define EVSYS_INTENCLR_OVR9(value)            (EVSYS_INTENCLR_OVR9_Msk & ((value) << EVSYS_INTENCLR_OVR9_Pos))
    227. 

  227. #define EVSYS_INTENCLR_OVR10_Pos              _U_(18)                                              /**< (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable Position */
    228. 

  228. #define EVSYS_INTENCLR_OVR10_Msk              (_U_(0x1) << EVSYS_INTENCLR_OVR10_Pos)               /**< (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable Mask */
    229. 

  229. #define EVSYS_INTENCLR_OVR10(value)           (EVSYS_INTENCLR_OVR10_Msk & ((value) << EVSYS_INTENCLR_OVR10_Pos))
    230. 

  230. #define EVSYS_INTENCLR_OVR11_Pos              _U_(19)                                              /**< (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable Position */
    231. 

  231. #define EVSYS_INTENCLR_OVR11_Msk              (_U_(0x1) << EVSYS_INTENCLR_OVR11_Pos)               /**< (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable Mask */
    232. 

  232. #define EVSYS_INTENCLR_OVR11(value)           (EVSYS_INTENCLR_OVR11_Msk & ((value) << EVSYS_INTENCLR_OVR11_Pos))
    233. 

  233. #define EVSYS_INTENCLR_EVD8_Pos               _U_(24)                                              /**< (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable Position */
    234. 

  234. #define EVSYS_INTENCLR_EVD8_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD8_Pos)                /**< (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable Mask */
    235. 

  235. #define EVSYS_INTENCLR_EVD8(value)            (EVSYS_INTENCLR_EVD8_Msk & ((value) << EVSYS_INTENCLR_EVD8_Pos))
    236. 

  236. #define EVSYS_INTENCLR_EVD9_Pos               _U_(25)                                              /**< (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable Position */
    237. 

  237. #define EVSYS_INTENCLR_EVD9_Msk               (_U_(0x1) << EVSYS_INTENCLR_EVD9_Pos)                /**< (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable Mask */
    238. 

  238. #define EVSYS_INTENCLR_EVD9(value)            (EVSYS_INTENCLR_EVD9_Msk & ((value) << EVSYS_INTENCLR_EVD9_Pos))
    239. 

  239. #define EVSYS_INTENCLR_EVD10_Pos              _U_(26)                                              /**< (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable Position */
    240. 

  240. #define EVSYS_INTENCLR_EVD10_Msk              (_U_(0x1) << EVSYS_INTENCLR_EVD10_Pos)               /**< (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable Mask */
    241. 

  241. #define EVSYS_INTENCLR_EVD10(value)           (EVSYS_INTENCLR_EVD10_Msk & ((value) << EVSYS_INTENCLR_EVD10_Pos))
    242. 

  242. #define EVSYS_INTENCLR_EVD11_Pos              _U_(27)                                              /**< (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable Position */
    243. 

  243. #define EVSYS_INTENCLR_EVD11_Msk              (_U_(0x1) << EVSYS_INTENCLR_EVD11_Pos)               /**< (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable Mask */
    244. 

  244. #define EVSYS_INTENCLR_EVD11(value)           (EVSYS_INTENCLR_EVD11_Msk & ((value) << EVSYS_INTENCLR_EVD11_Pos))
    245. 

  245. #define EVSYS_INTENCLR_Msk                    _U_(0x0F0FFFFF)                                      /**< (EVSYS_INTENCLR) Register Mask  */
    246. 

  246. 

  247. 

  248. /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
    249. 

  249. #define EVSYS_INTENSET_RESETVALUE             _U_(0x00)                                            /**<  (EVSYS_INTENSET) Interrupt Enable Set  Reset Value */
    250. 

  250. 

  251. #define EVSYS_INTENSET_OVR0_Pos               _U_(0)                                               /**< (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable Position */
    252. 

  252. #define EVSYS_INTENSET_OVR0_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR0_Pos)                /**< (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable Mask */
    253. 

  253. #define EVSYS_INTENSET_OVR0(value)            (EVSYS_INTENSET_OVR0_Msk & ((value) << EVSYS_INTENSET_OVR0_Pos))
    254. 

  254. #define EVSYS_INTENSET_OVR1_Pos               _U_(1)                                               /**< (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable Position */
    255. 

  255. #define EVSYS_INTENSET_OVR1_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR1_Pos)                /**< (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable Mask */
    256. 

  256. #define EVSYS_INTENSET_OVR1(value)            (EVSYS_INTENSET_OVR1_Msk & ((value) << EVSYS_INTENSET_OVR1_Pos))
    257. 

  257. #define EVSYS_INTENSET_OVR2_Pos               _U_(2)                                               /**< (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable Position */
    258. 

  258. #define EVSYS_INTENSET_OVR2_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR2_Pos)                /**< (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable Mask */
    259. 

  259. #define EVSYS_INTENSET_OVR2(value)            (EVSYS_INTENSET_OVR2_Msk & ((value) << EVSYS_INTENSET_OVR2_Pos))
    260. 

  260. #define EVSYS_INTENSET_OVR3_Pos               _U_(3)                                               /**< (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable Position */
    261. 

  261. #define EVSYS_INTENSET_OVR3_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR3_Pos)                /**< (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable Mask */
    262. 

  262. #define EVSYS_INTENSET_OVR3(value)            (EVSYS_INTENSET_OVR3_Msk & ((value) << EVSYS_INTENSET_OVR3_Pos))
    263. 

  263. #define EVSYS_INTENSET_OVR4_Pos               _U_(4)                                               /**< (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable Position */
    264. 

  264. #define EVSYS_INTENSET_OVR4_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR4_Pos)                /**< (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable Mask */
    265. 

  265. #define EVSYS_INTENSET_OVR4(value)            (EVSYS_INTENSET_OVR4_Msk & ((value) << EVSYS_INTENSET_OVR4_Pos))
    266. 

  266. #define EVSYS_INTENSET_OVR5_Pos               _U_(5)                                               /**< (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable Position */
    267. 

  267. #define EVSYS_INTENSET_OVR5_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR5_Pos)                /**< (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable Mask */
    268. 

  268. #define EVSYS_INTENSET_OVR5(value)            (EVSYS_INTENSET_OVR5_Msk & ((value) << EVSYS_INTENSET_OVR5_Pos))
    269. 

  269. #define EVSYS_INTENSET_OVR6_Pos               _U_(6)                                               /**< (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable Position */
    270. 

  270. #define EVSYS_INTENSET_OVR6_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR6_Pos)                /**< (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable Mask */
    271. 

  271. #define EVSYS_INTENSET_OVR6(value)            (EVSYS_INTENSET_OVR6_Msk & ((value) << EVSYS_INTENSET_OVR6_Pos))
    272. 

  272. #define EVSYS_INTENSET_OVR7_Pos               _U_(7)                                               /**< (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable Position */
    273. 

  273. #define EVSYS_INTENSET_OVR7_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR7_Pos)                /**< (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable Mask */
    274. 

  274. #define EVSYS_INTENSET_OVR7(value)            (EVSYS_INTENSET_OVR7_Msk & ((value) << EVSYS_INTENSET_OVR7_Pos))
    275. 

  275. #define EVSYS_INTENSET_EVD0_Pos               _U_(8)                                               /**< (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable Position */
    276. 

  276. #define EVSYS_INTENSET_EVD0_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD0_Pos)                /**< (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable Mask */
    277. 

  277. #define EVSYS_INTENSET_EVD0(value)            (EVSYS_INTENSET_EVD0_Msk & ((value) << EVSYS_INTENSET_EVD0_Pos))
    278. 

  278. #define EVSYS_INTENSET_EVD1_Pos               _U_(9)                                               /**< (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable Position */
    279. 

  279. #define EVSYS_INTENSET_EVD1_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD1_Pos)                /**< (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable Mask */
    280. 

  280. #define EVSYS_INTENSET_EVD1(value)            (EVSYS_INTENSET_EVD1_Msk & ((value) << EVSYS_INTENSET_EVD1_Pos))
    281. 

  281. #define EVSYS_INTENSET_EVD2_Pos               _U_(10)                                              /**< (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable Position */
    282. 

  282. #define EVSYS_INTENSET_EVD2_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD2_Pos)                /**< (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable Mask */
    283. 

  283. #define EVSYS_INTENSET_EVD2(value)            (EVSYS_INTENSET_EVD2_Msk & ((value) << EVSYS_INTENSET_EVD2_Pos))
    284. 

  284. #define EVSYS_INTENSET_EVD3_Pos               _U_(11)                                              /**< (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable Position */
    285. 

  285. #define EVSYS_INTENSET_EVD3_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD3_Pos)                /**< (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable Mask */
    286. 

  286. #define EVSYS_INTENSET_EVD3(value)            (EVSYS_INTENSET_EVD3_Msk & ((value) << EVSYS_INTENSET_EVD3_Pos))
    287. 

  287. #define EVSYS_INTENSET_EVD4_Pos               _U_(12)                                              /**< (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable Position */
    288. 

  288. #define EVSYS_INTENSET_EVD4_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD4_Pos)                /**< (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable Mask */
    289. 

  289. #define EVSYS_INTENSET_EVD4(value)            (EVSYS_INTENSET_EVD4_Msk & ((value) << EVSYS_INTENSET_EVD4_Pos))
    290. 

  290. #define EVSYS_INTENSET_EVD5_Pos               _U_(13)                                              /**< (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable Position */
    291. 

  291. #define EVSYS_INTENSET_EVD5_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD5_Pos)                /**< (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable Mask */
    292. 

  292. #define EVSYS_INTENSET_EVD5(value)            (EVSYS_INTENSET_EVD5_Msk & ((value) << EVSYS_INTENSET_EVD5_Pos))
    293. 

  293. #define EVSYS_INTENSET_EVD6_Pos               _U_(14)                                              /**< (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable Position */
    294. 

  294. #define EVSYS_INTENSET_EVD6_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD6_Pos)                /**< (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable Mask */
    295. 

  295. #define EVSYS_INTENSET_EVD6(value)            (EVSYS_INTENSET_EVD6_Msk & ((value) << EVSYS_INTENSET_EVD6_Pos))
    296. 

  296. #define EVSYS_INTENSET_EVD7_Pos               _U_(15)                                              /**< (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable Position */
    297. 

  297. #define EVSYS_INTENSET_EVD7_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD7_Pos)                /**< (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable Mask */
    298. 

  298. #define EVSYS_INTENSET_EVD7(value)            (EVSYS_INTENSET_EVD7_Msk & ((value) << EVSYS_INTENSET_EVD7_Pos))
    299. 

  299. #define EVSYS_INTENSET_OVR8_Pos               _U_(16)                                              /**< (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable Position */
    300. 

  300. #define EVSYS_INTENSET_OVR8_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR8_Pos)                /**< (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable Mask */
    301. 

  301. #define EVSYS_INTENSET_OVR8(value)            (EVSYS_INTENSET_OVR8_Msk & ((value) << EVSYS_INTENSET_OVR8_Pos))
    302. 

  302. #define EVSYS_INTENSET_OVR9_Pos               _U_(17)                                              /**< (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable Position */
    303. 

  303. #define EVSYS_INTENSET_OVR9_Msk               (_U_(0x1) << EVSYS_INTENSET_OVR9_Pos)                /**< (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable Mask */
    304. 

  304. #define EVSYS_INTENSET_OVR9(value)            (EVSYS_INTENSET_OVR9_Msk & ((value) << EVSYS_INTENSET_OVR9_Pos))
    305. 

  305. #define EVSYS_INTENSET_OVR10_Pos              _U_(18)                                              /**< (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable Position */
    306. 

  306. #define EVSYS_INTENSET_OVR10_Msk              (_U_(0x1) << EVSYS_INTENSET_OVR10_Pos)               /**< (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable Mask */
    307. 

  307. #define EVSYS_INTENSET_OVR10(value)           (EVSYS_INTENSET_OVR10_Msk & ((value) << EVSYS_INTENSET_OVR10_Pos))
    308. 

  308. #define EVSYS_INTENSET_OVR11_Pos              _U_(19)                                              /**< (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable Position */
    309. 

  309. #define EVSYS_INTENSET_OVR11_Msk              (_U_(0x1) << EVSYS_INTENSET_OVR11_Pos)               /**< (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable Mask */
    310. 

  310. #define EVSYS_INTENSET_OVR11(value)           (EVSYS_INTENSET_OVR11_Msk & ((value) << EVSYS_INTENSET_OVR11_Pos))
    311. 

  311. #define EVSYS_INTENSET_EVD8_Pos               _U_(24)                                              /**< (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable Position */
    312. 

  312. #define EVSYS_INTENSET_EVD8_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD8_Pos)                /**< (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable Mask */
    313. 

  313. #define EVSYS_INTENSET_EVD8(value)            (EVSYS_INTENSET_EVD8_Msk & ((value) << EVSYS_INTENSET_EVD8_Pos))
    314. 

  314. #define EVSYS_INTENSET_EVD9_Pos               _U_(25)                                              /**< (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable Position */
    315. 

  315. #define EVSYS_INTENSET_EVD9_Msk               (_U_(0x1) << EVSYS_INTENSET_EVD9_Pos)                /**< (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable Mask */
    316. 

  316. #define EVSYS_INTENSET_EVD9(value)            (EVSYS_INTENSET_EVD9_Msk & ((value) << EVSYS_INTENSET_EVD9_Pos))
    317. 

  317. #define EVSYS_INTENSET_EVD10_Pos              _U_(26)                                              /**< (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable Position */
    318. 

  318. #define EVSYS_INTENSET_EVD10_Msk              (_U_(0x1) << EVSYS_INTENSET_EVD10_Pos)               /**< (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable Mask */
    319. 

  319. #define EVSYS_INTENSET_EVD10(value)           (EVSYS_INTENSET_EVD10_Msk & ((value) << EVSYS_INTENSET_EVD10_Pos))
    320. 

  320. #define EVSYS_INTENSET_EVD11_Pos              _U_(27)                                              /**< (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable Position */
    321. 

  321. #define EVSYS_INTENSET_EVD11_Msk              (_U_(0x1) << EVSYS_INTENSET_EVD11_Pos)               /**< (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable Mask */
    322. 

  322. #define EVSYS_INTENSET_EVD11(value)           (EVSYS_INTENSET_EVD11_Msk & ((value) << EVSYS_INTENSET_EVD11_Pos))
    323. 

  323. #define EVSYS_INTENSET_Msk                    _U_(0x0F0FFFFF)                                      /**< (EVSYS_INTENSET) Register Mask  */
    324. 

  324. 

  325. 

  326. /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
    327. 

  327. #define EVSYS_INTFLAG_RESETVALUE              _U_(0x00)                                            /**<  (EVSYS_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    328. 

  328. 

  329. #define EVSYS_INTFLAG_OVR0_Pos                _U_(0)                                               /**< (EVSYS_INTFLAG) Channel 0 Overrun Position */
    330. 

  330. #define EVSYS_INTFLAG_OVR0_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR0_Pos)                 /**< (EVSYS_INTFLAG) Channel 0 Overrun Mask */
    331. 

  331. #define EVSYS_INTFLAG_OVR0(value)             (EVSYS_INTFLAG_OVR0_Msk & ((value) << EVSYS_INTFLAG_OVR0_Pos))
    332. 

  332. #define EVSYS_INTFLAG_OVR1_Pos                _U_(1)                                               /**< (EVSYS_INTFLAG) Channel 1 Overrun Position */
    333. 

  333. #define EVSYS_INTFLAG_OVR1_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR1_Pos)                 /**< (EVSYS_INTFLAG) Channel 1 Overrun Mask */
    334. 

  334. #define EVSYS_INTFLAG_OVR1(value)             (EVSYS_INTFLAG_OVR1_Msk & ((value) << EVSYS_INTFLAG_OVR1_Pos))
    335. 

  335. #define EVSYS_INTFLAG_OVR2_Pos                _U_(2)                                               /**< (EVSYS_INTFLAG) Channel 2 Overrun Position */
    336. 

  336. #define EVSYS_INTFLAG_OVR2_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR2_Pos)                 /**< (EVSYS_INTFLAG) Channel 2 Overrun Mask */
    337. 

  337. #define EVSYS_INTFLAG_OVR2(value)             (EVSYS_INTFLAG_OVR2_Msk & ((value) << EVSYS_INTFLAG_OVR2_Pos))
    338. 

  338. #define EVSYS_INTFLAG_OVR3_Pos                _U_(3)                                               /**< (EVSYS_INTFLAG) Channel 3 Overrun Position */
    339. 

  339. #define EVSYS_INTFLAG_OVR3_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR3_Pos)                 /**< (EVSYS_INTFLAG) Channel 3 Overrun Mask */
    340. 

  340. #define EVSYS_INTFLAG_OVR3(value)             (EVSYS_INTFLAG_OVR3_Msk & ((value) << EVSYS_INTFLAG_OVR3_Pos))
    341. 

  341. #define EVSYS_INTFLAG_OVR4_Pos                _U_(4)                                               /**< (EVSYS_INTFLAG) Channel 4 Overrun Position */
    342. 

  342. #define EVSYS_INTFLAG_OVR4_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR4_Pos)                 /**< (EVSYS_INTFLAG) Channel 4 Overrun Mask */
    343. 

  343. #define EVSYS_INTFLAG_OVR4(value)             (EVSYS_INTFLAG_OVR4_Msk & ((value) << EVSYS_INTFLAG_OVR4_Pos))
    344. 

  344. #define EVSYS_INTFLAG_OVR5_Pos                _U_(5)                                               /**< (EVSYS_INTFLAG) Channel 5 Overrun Position */
    345. 

  345. #define EVSYS_INTFLAG_OVR5_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR5_Pos)                 /**< (EVSYS_INTFLAG) Channel 5 Overrun Mask */
    346. 

  346. #define EVSYS_INTFLAG_OVR5(value)             (EVSYS_INTFLAG_OVR5_Msk & ((value) << EVSYS_INTFLAG_OVR5_Pos))
    347. 

  347. #define EVSYS_INTFLAG_OVR6_Pos                _U_(6)                                               /**< (EVSYS_INTFLAG) Channel 6 Overrun Position */
    348. 

  348. #define EVSYS_INTFLAG_OVR6_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR6_Pos)                 /**< (EVSYS_INTFLAG) Channel 6 Overrun Mask */
    349. 

  349. #define EVSYS_INTFLAG_OVR6(value)             (EVSYS_INTFLAG_OVR6_Msk & ((value) << EVSYS_INTFLAG_OVR6_Pos))
    350. 

  350. #define EVSYS_INTFLAG_OVR7_Pos                _U_(7)                                               /**< (EVSYS_INTFLAG) Channel 7 Overrun Position */
    351. 

  351. #define EVSYS_INTFLAG_OVR7_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR7_Pos)                 /**< (EVSYS_INTFLAG) Channel 7 Overrun Mask */
    352. 

  352. #define EVSYS_INTFLAG_OVR7(value)             (EVSYS_INTFLAG_OVR7_Msk & ((value) << EVSYS_INTFLAG_OVR7_Pos))
    353. 

  353. #define EVSYS_INTFLAG_EVD0_Pos                _U_(8)                                               /**< (EVSYS_INTFLAG) Channel 0 Event Detection Position */
    354. 

  354. #define EVSYS_INTFLAG_EVD0_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD0_Pos)                 /**< (EVSYS_INTFLAG) Channel 0 Event Detection Mask */
    355. 

  355. #define EVSYS_INTFLAG_EVD0(value)             (EVSYS_INTFLAG_EVD0_Msk & ((value) << EVSYS_INTFLAG_EVD0_Pos))
    356. 

  356. #define EVSYS_INTFLAG_EVD1_Pos                _U_(9)                                               /**< (EVSYS_INTFLAG) Channel 1 Event Detection Position */
    357. 

  357. #define EVSYS_INTFLAG_EVD1_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD1_Pos)                 /**< (EVSYS_INTFLAG) Channel 1 Event Detection Mask */
    358. 

  358. #define EVSYS_INTFLAG_EVD1(value)             (EVSYS_INTFLAG_EVD1_Msk & ((value) << EVSYS_INTFLAG_EVD1_Pos))
    359. 

  359. #define EVSYS_INTFLAG_EVD2_Pos                _U_(10)                                              /**< (EVSYS_INTFLAG) Channel 2 Event Detection Position */
    360. 

  360. #define EVSYS_INTFLAG_EVD2_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD2_Pos)                 /**< (EVSYS_INTFLAG) Channel 2 Event Detection Mask */
    361. 

  361. #define EVSYS_INTFLAG_EVD2(value)             (EVSYS_INTFLAG_EVD2_Msk & ((value) << EVSYS_INTFLAG_EVD2_Pos))
    362. 

  362. #define EVSYS_INTFLAG_EVD3_Pos                _U_(11)                                              /**< (EVSYS_INTFLAG) Channel 3 Event Detection Position */
    363. 

  363. #define EVSYS_INTFLAG_EVD3_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD3_Pos)                 /**< (EVSYS_INTFLAG) Channel 3 Event Detection Mask */
    364. 

  364. #define EVSYS_INTFLAG_EVD3(value)             (EVSYS_INTFLAG_EVD3_Msk & ((value) << EVSYS_INTFLAG_EVD3_Pos))
    365. 

  365. #define EVSYS_INTFLAG_EVD4_Pos                _U_(12)                                              /**< (EVSYS_INTFLAG) Channel 4 Event Detection Position */
    366. 

  366. #define EVSYS_INTFLAG_EVD4_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD4_Pos)                 /**< (EVSYS_INTFLAG) Channel 4 Event Detection Mask */
    367. 

  367. #define EVSYS_INTFLAG_EVD4(value)             (EVSYS_INTFLAG_EVD4_Msk & ((value) << EVSYS_INTFLAG_EVD4_Pos))
    368. 

  368. #define EVSYS_INTFLAG_EVD5_Pos                _U_(13)                                              /**< (EVSYS_INTFLAG) Channel 5 Event Detection Position */
    369. 

  369. #define EVSYS_INTFLAG_EVD5_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD5_Pos)                 /**< (EVSYS_INTFLAG) Channel 5 Event Detection Mask */
    370. 

  370. #define EVSYS_INTFLAG_EVD5(value)             (EVSYS_INTFLAG_EVD5_Msk & ((value) << EVSYS_INTFLAG_EVD5_Pos))
    371. 

  371. #define EVSYS_INTFLAG_EVD6_Pos                _U_(14)                                              /**< (EVSYS_INTFLAG) Channel 6 Event Detection Position */
    372. 

  372. #define EVSYS_INTFLAG_EVD6_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD6_Pos)                 /**< (EVSYS_INTFLAG) Channel 6 Event Detection Mask */
    373. 

  373. #define EVSYS_INTFLAG_EVD6(value)             (EVSYS_INTFLAG_EVD6_Msk & ((value) << EVSYS_INTFLAG_EVD6_Pos))
    374. 

  374. #define EVSYS_INTFLAG_EVD7_Pos                _U_(15)                                              /**< (EVSYS_INTFLAG) Channel 7 Event Detection Position */
    375. 

  375. #define EVSYS_INTFLAG_EVD7_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD7_Pos)                 /**< (EVSYS_INTFLAG) Channel 7 Event Detection Mask */
    376. 

  376. #define EVSYS_INTFLAG_EVD7(value)             (EVSYS_INTFLAG_EVD7_Msk & ((value) << EVSYS_INTFLAG_EVD7_Pos))
    377. 

  377. #define EVSYS_INTFLAG_OVR8_Pos                _U_(16)                                              /**< (EVSYS_INTFLAG) Channel 8 Overrun Position */
    378. 

  378. #define EVSYS_INTFLAG_OVR8_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR8_Pos)                 /**< (EVSYS_INTFLAG) Channel 8 Overrun Mask */
    379. 

  379. #define EVSYS_INTFLAG_OVR8(value)             (EVSYS_INTFLAG_OVR8_Msk & ((value) << EVSYS_INTFLAG_OVR8_Pos))
    380. 

  380. #define EVSYS_INTFLAG_OVR9_Pos                _U_(17)                                              /**< (EVSYS_INTFLAG) Channel 9 Overrun Position */
    381. 

  381. #define EVSYS_INTFLAG_OVR9_Msk                (_U_(0x1) << EVSYS_INTFLAG_OVR9_Pos)                 /**< (EVSYS_INTFLAG) Channel 9 Overrun Mask */
    382. 

  382. #define EVSYS_INTFLAG_OVR9(value)             (EVSYS_INTFLAG_OVR9_Msk & ((value) << EVSYS_INTFLAG_OVR9_Pos))
    383. 

  383. #define EVSYS_INTFLAG_OVR10_Pos               _U_(18)                                              /**< (EVSYS_INTFLAG) Channel 10 Overrun Position */
    384. 

  384. #define EVSYS_INTFLAG_OVR10_Msk               (_U_(0x1) << EVSYS_INTFLAG_OVR10_Pos)                /**< (EVSYS_INTFLAG) Channel 10 Overrun Mask */
    385. 

  385. #define EVSYS_INTFLAG_OVR10(value)            (EVSYS_INTFLAG_OVR10_Msk & ((value) << EVSYS_INTFLAG_OVR10_Pos))
    386. 

  386. #define EVSYS_INTFLAG_OVR11_Pos               _U_(19)                                              /**< (EVSYS_INTFLAG) Channel 11 Overrun Position */
    387. 

  387. #define EVSYS_INTFLAG_OVR11_Msk               (_U_(0x1) << EVSYS_INTFLAG_OVR11_Pos)                /**< (EVSYS_INTFLAG) Channel 11 Overrun Mask */
    388. 

  388. #define EVSYS_INTFLAG_OVR11(value)            (EVSYS_INTFLAG_OVR11_Msk & ((value) << EVSYS_INTFLAG_OVR11_Pos))
    389. 

  389. #define EVSYS_INTFLAG_EVD8_Pos                _U_(24)                                              /**< (EVSYS_INTFLAG) Channel 8 Event Detection Position */
    390. 

  390. #define EVSYS_INTFLAG_EVD8_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD8_Pos)                 /**< (EVSYS_INTFLAG) Channel 8 Event Detection Mask */
    391. 

  391. #define EVSYS_INTFLAG_EVD8(value)             (EVSYS_INTFLAG_EVD8_Msk & ((value) << EVSYS_INTFLAG_EVD8_Pos))
    392. 

  392. #define EVSYS_INTFLAG_EVD9_Pos                _U_(25)                                              /**< (EVSYS_INTFLAG) Channel 9 Event Detection Position */
    393. 

  393. #define EVSYS_INTFLAG_EVD9_Msk                (_U_(0x1) << EVSYS_INTFLAG_EVD9_Pos)                 /**< (EVSYS_INTFLAG) Channel 9 Event Detection Mask */
    394. 

  394. #define EVSYS_INTFLAG_EVD9(value)             (EVSYS_INTFLAG_EVD9_Msk & ((value) << EVSYS_INTFLAG_EVD9_Pos))
    395. 

  395. #define EVSYS_INTFLAG_EVD10_Pos               _U_(26)                                              /**< (EVSYS_INTFLAG) Channel 10 Event Detection Position */
    396. 

  396. #define EVSYS_INTFLAG_EVD10_Msk               (_U_(0x1) << EVSYS_INTFLAG_EVD10_Pos)                /**< (EVSYS_INTFLAG) Channel 10 Event Detection Mask */
    397. 

  397. #define EVSYS_INTFLAG_EVD10(value)            (EVSYS_INTFLAG_EVD10_Msk & ((value) << EVSYS_INTFLAG_EVD10_Pos))
    398. 

  398. #define EVSYS_INTFLAG_EVD11_Pos               _U_(27)                                              /**< (EVSYS_INTFLAG) Channel 11 Event Detection Position */
    399. 

  399. #define EVSYS_INTFLAG_EVD11_Msk               (_U_(0x1) << EVSYS_INTFLAG_EVD11_Pos)                /**< (EVSYS_INTFLAG) Channel 11 Event Detection Mask */
    400. 

  400. #define EVSYS_INTFLAG_EVD11(value)            (EVSYS_INTFLAG_EVD11_Msk & ((value) << EVSYS_INTFLAG_EVD11_Pos))
    401. 

  401. #define EVSYS_INTFLAG_Msk                     _U_(0x0F0FFFFF)                                      /**< (EVSYS_INTFLAG) Register Mask  */
    402. 

  402. 

  403. 

  404. /** \brief EVSYS register offsets definitions */
    405. 

  405. #define EVSYS_CTRL_REG_OFST            (0x00)              /**< (EVSYS_CTRL) Control Offset */
    406. 

  406. #define EVSYS_CHANNEL_REG_OFST         (0x04)              /**< (EVSYS_CHANNEL) Channel Offset */
    407. 

  407. #define EVSYS_USER_REG_OFST            (0x08)              /**< (EVSYS_USER) User Multiplexer Offset */
    408. 

  408. #define EVSYS_CHSTATUS_REG_OFST        (0x0C)              /**< (EVSYS_CHSTATUS) Channel Status Offset */
    409. 

  409. #define EVSYS_INTENCLR_REG_OFST        (0x10)              /**< (EVSYS_INTENCLR) Interrupt Enable Clear Offset */
    410. 

  410. #define EVSYS_INTENSET_REG_OFST        (0x14)              /**< (EVSYS_INTENSET) Interrupt Enable Set Offset */
    411. 

  411. #define EVSYS_INTFLAG_REG_OFST         (0x18)              /**< (EVSYS_INTFLAG) Interrupt Flag Status and Clear Offset */
    412. 

  412. 

  413. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    414. 

  414. /** \brief EVSYS register API structure */
    415. 

  415. typedef struct
    416. 

  416. {  /* Event System Interface */
    417. 

  417.   __O   uint8_t                        EVSYS_CTRL;         /**< Offset: 0x00 ( /W  8) Control */
    418. 

  418.   __I   uint8_t                        Reserved1[0x03];
    419. 

  419.   __IO  uint32_t                       EVSYS_CHANNEL;      /**< Offset: 0x04 (R/W  32) Channel */
    420. 

  420.   __IO  uint16_t                       EVSYS_USER;         /**< Offset: 0x08 (R/W  16) User Multiplexer */
    421. 

  421.   __I   uint8_t                        Reserved2[0x02];
    422. 

  422.   __I   uint32_t                       EVSYS_CHSTATUS;     /**< Offset: 0x0C (R/   32) Channel Status */
    423. 

  423.   __IO  uint32_t                       EVSYS_INTENCLR;     /**< Offset: 0x10 (R/W  32) Interrupt Enable Clear */
    424. 

  424.   __IO  uint32_t                       EVSYS_INTENSET;     /**< Offset: 0x14 (R/W  32) Interrupt Enable Set */
    425. 

  425.   __IO  uint32_t                       EVSYS_INTFLAG;      /**< Offset: 0x18 (R/W  32) Interrupt Flag Status and Clear */
    426. 

  426. } evsys_registers_t;
    427. 

  427. 

  428. 

  429. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    430. 

  430. #endif /* _SAMD21_EVSYS_COMPONENT_H_ */
    431.