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gclk.h

gclk.h 27 KB
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  1. /**
    2. 

  2.  * \brief Component description for GCLK
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_GCLK_COMPONENT_H_
    25. 

  25. #define _SAMD21_GCLK_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR GCLK                                         */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- GCLK_CTRL : (GCLK Offset: 0x00) (R/W 8) Control -------- */
    32. 

  32. #define GCLK_CTRL_RESETVALUE                  _U_(0x00)                                            /**<  (GCLK_CTRL) Control  Reset Value */
    33. 

  33. 

  34. #define GCLK_CTRL_SWRST_Pos                   _U_(0)                                               /**< (GCLK_CTRL) Software Reset Position */
    35. 

  35. #define GCLK_CTRL_SWRST_Msk                   (_U_(0x1) << GCLK_CTRL_SWRST_Pos)                    /**< (GCLK_CTRL) Software Reset Mask */
    36. 

  36. #define GCLK_CTRL_SWRST(value)                (GCLK_CTRL_SWRST_Msk & ((value) << GCLK_CTRL_SWRST_Pos))
    37. 

  37. #define GCLK_CTRL_Msk                         _U_(0x01)                                            /**< (GCLK_CTRL) Register Mask  */
    38. 

  38. 

  39. 

  40. /* -------- GCLK_STATUS : (GCLK Offset: 0x01) ( R/ 8) Status -------- */
    41. 

  41. #define GCLK_STATUS_RESETVALUE                _U_(0x00)                                            /**<  (GCLK_STATUS) Status  Reset Value */
    42. 

  42. 

  43. #define GCLK_STATUS_SYNCBUSY_Pos              _U_(7)                                               /**< (GCLK_STATUS) Synchronization Busy Status Position */
    44. 

  44. #define GCLK_STATUS_SYNCBUSY_Msk              (_U_(0x1) << GCLK_STATUS_SYNCBUSY_Pos)               /**< (GCLK_STATUS) Synchronization Busy Status Mask */
    45. 

  45. #define GCLK_STATUS_SYNCBUSY(value)           (GCLK_STATUS_SYNCBUSY_Msk & ((value) << GCLK_STATUS_SYNCBUSY_Pos))
    46. 

  46. #define GCLK_STATUS_Msk                       _U_(0x80)                                            /**< (GCLK_STATUS) Register Mask  */
    47. 

  47. 

  48. 

  49. /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x02) (R/W 16) Generic Clock Control -------- */
    50. 

  50. #define GCLK_CLKCTRL_RESETVALUE               _U_(0x00)                                            /**<  (GCLK_CLKCTRL) Generic Clock Control  Reset Value */
    51. 

  51. 

  52. #define GCLK_CLKCTRL_ID_Pos                   _U_(0)                                               /**< (GCLK_CLKCTRL) Generic Clock Selection ID Position */
    53. 

  53. #define GCLK_CLKCTRL_ID_Msk                   (_U_(0x3F) << GCLK_CLKCTRL_ID_Pos)                   /**< (GCLK_CLKCTRL) Generic Clock Selection ID Mask */
    54. 

  54. #define GCLK_CLKCTRL_ID(value)                (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
    55. 

  55. #define   GCLK_CLKCTRL_ID_DFLL48_Val          _U_(0x0)                                             /**< (GCLK_CLKCTRL) DFLL48  */
    56. 

  56. #define   GCLK_CLKCTRL_ID_FDPLL_Val           _U_(0x1)                                             /**< (GCLK_CLKCTRL) FDPLL  */
    57. 

  57. #define   GCLK_CLKCTRL_ID_FDPLL32K_Val        _U_(0x2)                                             /**< (GCLK_CLKCTRL) FDPLL32K  */
    58. 

  58. #define   GCLK_CLKCTRL_ID_WDT_Val             _U_(0x3)                                             /**< (GCLK_CLKCTRL) WDT  */
    59. 

  59. #define   GCLK_CLKCTRL_ID_RTC_Val             _U_(0x4)                                             /**< (GCLK_CLKCTRL) RTC  */
    60. 

  60. #define   GCLK_CLKCTRL_ID_EIC_Val             _U_(0x5)                                             /**< (GCLK_CLKCTRL) EIC  */
    61. 

  61. #define   GCLK_CLKCTRL_ID_USB_Val             _U_(0x6)                                             /**< (GCLK_CLKCTRL) USB  */
    62. 

  62. #define   GCLK_CLKCTRL_ID_EVSYS_0_Val         _U_(0x7)                                             /**< (GCLK_CLKCTRL) EVSYS_0  */
    63. 

  63. #define   GCLK_CLKCTRL_ID_EVSYS_1_Val         _U_(0x8)                                             /**< (GCLK_CLKCTRL) EVSYS_1  */
    64. 

  64. #define   GCLK_CLKCTRL_ID_EVSYS_2_Val         _U_(0x9)                                             /**< (GCLK_CLKCTRL) EVSYS_2  */
    65. 

  65. #define   GCLK_CLKCTRL_ID_EVSYS_3_Val         _U_(0xA)                                             /**< (GCLK_CLKCTRL) EVSYS_3  */
    66. 

  66. #define   GCLK_CLKCTRL_ID_EVSYS_4_Val         _U_(0xB)                                             /**< (GCLK_CLKCTRL) EVSYS_4  */
    67. 

  67. #define   GCLK_CLKCTRL_ID_EVSYS_5_Val         _U_(0xC)                                             /**< (GCLK_CLKCTRL) EVSYS_5  */
    68. 

  68. #define   GCLK_CLKCTRL_ID_EVSYS_6_Val         _U_(0xD)                                             /**< (GCLK_CLKCTRL) EVSYS_6  */
    69. 

  69. #define   GCLK_CLKCTRL_ID_EVSYS_7_Val         _U_(0xE)                                             /**< (GCLK_CLKCTRL) EVSYS_7  */
    70. 

  70. #define   GCLK_CLKCTRL_ID_EVSYS_8_Val         _U_(0xF)                                             /**< (GCLK_CLKCTRL) EVSYS_8  */
    71. 

  71. #define   GCLK_CLKCTRL_ID_EVSYS_9_Val         _U_(0x10)                                            /**< (GCLK_CLKCTRL) EVSYS_9  */
    72. 

  72. #define   GCLK_CLKCTRL_ID_EVSYS_10_Val        _U_(0x11)                                            /**< (GCLK_CLKCTRL) EVSYS_10  */
    73. 

  73. #define   GCLK_CLKCTRL_ID_EVSYS_11_Val        _U_(0x12)                                            /**< (GCLK_CLKCTRL) EVSYS_11  */
    74. 

  74. #define   GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val    _U_(0x13)                                            /**< (GCLK_CLKCTRL) SERCOMX_SLOW  */
    75. 

  75. #define   GCLK_CLKCTRL_ID_SERCOM0_CORE_Val    _U_(0x14)                                            /**< (GCLK_CLKCTRL) SERCOM0_CORE  */
    76. 

  76. #define   GCLK_CLKCTRL_ID_SERCOM1_CORE_Val    _U_(0x15)                                            /**< (GCLK_CLKCTRL) SERCOM1_CORE  */
    77. 

  77. #define   GCLK_CLKCTRL_ID_SERCOM2_CORE_Val    _U_(0x16)                                            /**< (GCLK_CLKCTRL) SERCOM2_CORE  */
    78. 

  78. #define   GCLK_CLKCTRL_ID_SERCOM3_CORE_Val    _U_(0x17)                                            /**< (GCLK_CLKCTRL) SERCOM3_CORE  */
    79. 

  79. #define   GCLK_CLKCTRL_ID_SERCOM4_CORE_Val    _U_(0x18)                                            /**< (GCLK_CLKCTRL) SERCOM4_CORE  */
    80. 

  80. #define   GCLK_CLKCTRL_ID_SERCOM5_CORE_Val    _U_(0x19)                                            /**< (GCLK_CLKCTRL) SERCOM5_CORE  */
    81. 

  81. #define   GCLK_CLKCTRL_ID_TCC0_TCC1_Val       _U_(0x1A)                                            /**< (GCLK_CLKCTRL) TCC0_TCC1  */
    82. 

  82. #define   GCLK_CLKCTRL_ID_TCC2_TC3_Val        _U_(0x1B)                                            /**< (GCLK_CLKCTRL) TCC2_TC3  */
    83. 

  83. #define   GCLK_CLKCTRL_ID_TC4_TC5_Val         _U_(0x1C)                                            /**< (GCLK_CLKCTRL) TC4_TC5  */
    84. 

  84. #define   GCLK_CLKCTRL_ID_TC6_TC7_Val         _U_(0x1D)                                            /**< (GCLK_CLKCTRL) TC6_TC7  */
    85. 

  85. #define   GCLK_CLKCTRL_ID_ADC_Val             _U_(0x1E)                                            /**< (GCLK_CLKCTRL) ADC  */
    86. 

  86. #define   GCLK_CLKCTRL_ID_AC_DIG_Val          _U_(0x1F)                                            /**< (GCLK_CLKCTRL) AC_DIG  */
    87. 

  87. #define   GCLK_CLKCTRL_ID_AC_ANA_Val          _U_(0x20)                                            /**< (GCLK_CLKCTRL) AC_ANA  */
    88. 

  88. #define   GCLK_CLKCTRL_ID_DAC_Val             _U_(0x21)                                            /**< (GCLK_CLKCTRL) DAC  */
    89. 

  89. #define   GCLK_CLKCTRL_ID_I2S_0_Val           _U_(0x23)                                            /**< (GCLK_CLKCTRL) I2S_0  */
    90. 

  90. #define   GCLK_CLKCTRL_ID_I2S_1_Val           _U_(0x24)                                            /**< (GCLK_CLKCTRL) I2S_1  */
    91. 

  91. #define GCLK_CLKCTRL_ID_DFLL48                (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)  /**< (GCLK_CLKCTRL) DFLL48 Position  */
    92. 

  92. #define GCLK_CLKCTRL_ID_FDPLL                 (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)   /**< (GCLK_CLKCTRL) FDPLL Position  */
    93. 

  93. #define GCLK_CLKCTRL_ID_FDPLL32K              (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) FDPLL32K Position  */
    94. 

  94. #define GCLK_CLKCTRL_ID_WDT                   (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)     /**< (GCLK_CLKCTRL) WDT Position  */
    95. 

  95. #define GCLK_CLKCTRL_ID_RTC                   (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)     /**< (GCLK_CLKCTRL) RTC Position  */
    96. 

  96. #define GCLK_CLKCTRL_ID_EIC                   (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)     /**< (GCLK_CLKCTRL) EIC Position  */
    97. 

  97. #define GCLK_CLKCTRL_ID_USB                   (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)     /**< (GCLK_CLKCTRL) USB Position  */
    98. 

  98. #define GCLK_CLKCTRL_ID_EVSYS_0               (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_0 Position  */
    99. 

  99. #define GCLK_CLKCTRL_ID_EVSYS_1               (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_1 Position  */
    100. 

  100. #define GCLK_CLKCTRL_ID_EVSYS_2               (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_2 Position  */
    101. 

  101. #define GCLK_CLKCTRL_ID_EVSYS_3               (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_3 Position  */
    102. 

  102. #define GCLK_CLKCTRL_ID_EVSYS_4               (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_4 Position  */
    103. 

  103. #define GCLK_CLKCTRL_ID_EVSYS_5               (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_5 Position  */
    104. 

  104. #define GCLK_CLKCTRL_ID_EVSYS_6               (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_6 Position  */
    105. 

  105. #define GCLK_CLKCTRL_ID_EVSYS_7               (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_7 Position  */
    106. 

  106. #define GCLK_CLKCTRL_ID_EVSYS_8               (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_8 Position  */
    107. 

  107. #define GCLK_CLKCTRL_ID_EVSYS_9               (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_9 Position  */
    108. 

  108. #define GCLK_CLKCTRL_ID_EVSYS_10              (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_10 Position  */
    109. 

  109. #define GCLK_CLKCTRL_ID_EVSYS_11              (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) EVSYS_11 Position  */
    110. 

  110. #define GCLK_CLKCTRL_ID_SERCOMX_SLOW          (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOMX_SLOW Position  */
    111. 

  111. #define GCLK_CLKCTRL_ID_SERCOM0_CORE          (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOM0_CORE Position  */
    112. 

  112. #define GCLK_CLKCTRL_ID_SERCOM1_CORE          (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOM1_CORE Position  */
    113. 

  113. #define GCLK_CLKCTRL_ID_SERCOM2_CORE          (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOM2_CORE Position  */
    114. 

  114. #define GCLK_CLKCTRL_ID_SERCOM3_CORE          (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOM3_CORE Position  */
    115. 

  115. #define GCLK_CLKCTRL_ID_SERCOM4_CORE          (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOM4_CORE Position  */
    116. 

  116. #define GCLK_CLKCTRL_ID_SERCOM5_CORE          (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) SERCOM5_CORE Position  */
    117. 

  117. #define GCLK_CLKCTRL_ID_TCC0_TCC1             (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) TCC0_TCC1 Position  */
    118. 

  118. #define GCLK_CLKCTRL_ID_TCC2_TC3              (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) TCC2_TC3 Position  */
    119. 

  119. #define GCLK_CLKCTRL_ID_TC4_TC5               (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) TC4_TC5 Position  */
    120. 

  120. #define GCLK_CLKCTRL_ID_TC6_TC7               (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos) /**< (GCLK_CLKCTRL) TC6_TC7 Position  */
    121. 

  121. #define GCLK_CLKCTRL_ID_ADC                   (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)     /**< (GCLK_CLKCTRL) ADC Position  */
    122. 

  122. #define GCLK_CLKCTRL_ID_AC_DIG                (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)  /**< (GCLK_CLKCTRL) AC_DIG Position  */
    123. 

  123. #define GCLK_CLKCTRL_ID_AC_ANA                (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)  /**< (GCLK_CLKCTRL) AC_ANA Position  */
    124. 

  124. #define GCLK_CLKCTRL_ID_DAC                   (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)     /**< (GCLK_CLKCTRL) DAC Position  */
    125. 

  125. #define GCLK_CLKCTRL_ID_I2S_0                 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)   /**< (GCLK_CLKCTRL) I2S_0 Position  */
    126. 

  126. #define GCLK_CLKCTRL_ID_I2S_1                 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)   /**< (GCLK_CLKCTRL) I2S_1 Position  */
    127. 

  127. #define GCLK_CLKCTRL_GEN_Pos                  _U_(8)                                               /**< (GCLK_CLKCTRL) Generic Clock Generator Position */
    128. 

  128. #define GCLK_CLKCTRL_GEN_Msk                  (_U_(0xF) << GCLK_CLKCTRL_GEN_Pos)                   /**< (GCLK_CLKCTRL) Generic Clock Generator Mask */
    129. 

  129. #define GCLK_CLKCTRL_GEN(value)               (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
    130. 

  130. #define   GCLK_CLKCTRL_GEN_GCLK0_Val          _U_(0x0)                                             /**< (GCLK_CLKCTRL) Generic clock generator 0  */
    131. 

  131. #define   GCLK_CLKCTRL_GEN_GCLK1_Val          _U_(0x1)                                             /**< (GCLK_CLKCTRL) Generic clock generator 1  */
    132. 

  132. #define   GCLK_CLKCTRL_GEN_GCLK2_Val          _U_(0x2)                                             /**< (GCLK_CLKCTRL) Generic clock generator 2  */
    133. 

  133. #define   GCLK_CLKCTRL_GEN_GCLK3_Val          _U_(0x3)                                             /**< (GCLK_CLKCTRL) Generic clock generator 3  */
    134. 

  134. #define   GCLK_CLKCTRL_GEN_GCLK4_Val          _U_(0x4)                                             /**< (GCLK_CLKCTRL) Generic clock generator 4  */
    135. 

  135. #define   GCLK_CLKCTRL_GEN_GCLK5_Val          _U_(0x5)                                             /**< (GCLK_CLKCTRL) Generic clock generator 5  */
    136. 

  136. #define   GCLK_CLKCTRL_GEN_GCLK6_Val          _U_(0x6)                                             /**< (GCLK_CLKCTRL) Generic clock generator 6  */
    137. 

  137. #define   GCLK_CLKCTRL_GEN_GCLK7_Val          _U_(0x7)                                             /**< (GCLK_CLKCTRL) Generic clock generator 7  */
    138. 

  138. #define   GCLK_CLKCTRL_GEN_GCLK8_Val          _U_(0x8)                                             /**< (GCLK_CLKCTRL) Generic clock generator 8  */
    139. 

  139. #define GCLK_CLKCTRL_GEN_GCLK0                (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 0 Position  */
    140. 

  140. #define GCLK_CLKCTRL_GEN_GCLK1                (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 1 Position  */
    141. 

  141. #define GCLK_CLKCTRL_GEN_GCLK2                (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 2 Position  */
    142. 

  142. #define GCLK_CLKCTRL_GEN_GCLK3                (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 3 Position  */
    143. 

  143. #define GCLK_CLKCTRL_GEN_GCLK4                (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 4 Position  */
    144. 

  144. #define GCLK_CLKCTRL_GEN_GCLK5                (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 5 Position  */
    145. 

  145. #define GCLK_CLKCTRL_GEN_GCLK6                (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 6 Position  */
    146. 

  146. #define GCLK_CLKCTRL_GEN_GCLK7                (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 7 Position  */
    147. 

  147. #define GCLK_CLKCTRL_GEN_GCLK8                (GCLK_CLKCTRL_GEN_GCLK8_Val << GCLK_CLKCTRL_GEN_Pos) /**< (GCLK_CLKCTRL) Generic clock generator 8 Position  */
    148. 

  148. #define GCLK_CLKCTRL_CLKEN_Pos                _U_(14)                                              /**< (GCLK_CLKCTRL) Clock Enable Position */
    149. 

  149. #define GCLK_CLKCTRL_CLKEN_Msk                (_U_(0x1) << GCLK_CLKCTRL_CLKEN_Pos)                 /**< (GCLK_CLKCTRL) Clock Enable Mask */
    150. 

  150. #define GCLK_CLKCTRL_CLKEN(value)             (GCLK_CLKCTRL_CLKEN_Msk & ((value) << GCLK_CLKCTRL_CLKEN_Pos))
    151. 

  151. #define GCLK_CLKCTRL_WRTLOCK_Pos              _U_(15)                                              /**< (GCLK_CLKCTRL) Write Lock Position */
    152. 

  152. #define GCLK_CLKCTRL_WRTLOCK_Msk              (_U_(0x1) << GCLK_CLKCTRL_WRTLOCK_Pos)               /**< (GCLK_CLKCTRL) Write Lock Mask */
    153. 

  153. #define GCLK_CLKCTRL_WRTLOCK(value)           (GCLK_CLKCTRL_WRTLOCK_Msk & ((value) << GCLK_CLKCTRL_WRTLOCK_Pos))
    154. 

  154. #define GCLK_CLKCTRL_Msk                      _U_(0xCF3F)                                          /**< (GCLK_CLKCTRL) Register Mask  */
    155. 

  155. 

  156. 

  157. /* -------- GCLK_GENCTRL : (GCLK Offset: 0x04) (R/W 32) Generic Clock Generator Control -------- */
    158. 

  158. #define GCLK_GENCTRL_RESETVALUE               _U_(0x00)                                            /**<  (GCLK_GENCTRL) Generic Clock Generator Control  Reset Value */
    159. 

  159. 

  160. #define GCLK_GENCTRL_ID_Pos                   _U_(0)                                               /**< (GCLK_GENCTRL) Generic Clock Generator Selection Position */
    161. 

  161. #define GCLK_GENCTRL_ID_Msk                   (_U_(0xF) << GCLK_GENCTRL_ID_Pos)                    /**< (GCLK_GENCTRL) Generic Clock Generator Selection Mask */
    162. 

  162. #define GCLK_GENCTRL_ID(value)                (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
    163. 

  163. #define GCLK_GENCTRL_SRC_Pos                  _U_(8)                                               /**< (GCLK_GENCTRL) Source Select Position */
    164. 

  164. #define GCLK_GENCTRL_SRC_Msk                  (_U_(0x1F) << GCLK_GENCTRL_SRC_Pos)                  /**< (GCLK_GENCTRL) Source Select Mask */
    165. 

  165. #define GCLK_GENCTRL_SRC(value)               (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
    166. 

  166. #define   GCLK_GENCTRL_SRC_XOSC_Val           _U_(0x0)                                             /**< (GCLK_GENCTRL) XOSC oscillator output  */
    167. 

  167. #define   GCLK_GENCTRL_SRC_GCLKIN_Val         _U_(0x1)                                             /**< (GCLK_GENCTRL) Generator input pad  */
    168. 

  168. #define   GCLK_GENCTRL_SRC_GCLKGEN1_Val       _U_(0x2)                                             /**< (GCLK_GENCTRL) Generic clock generator 1 output  */
    169. 

  169. #define   GCLK_GENCTRL_SRC_OSCULP32K_Val      _U_(0x3)                                             /**< (GCLK_GENCTRL) OSCULP32K oscillator output  */
    170. 

  170. #define   GCLK_GENCTRL_SRC_OSC32K_Val         _U_(0x4)                                             /**< (GCLK_GENCTRL) OSC32K oscillator output  */
    171. 

  171. #define   GCLK_GENCTRL_SRC_XOSC32K_Val        _U_(0x5)                                             /**< (GCLK_GENCTRL) XOSC32K oscillator output  */
    172. 

  172. #define   GCLK_GENCTRL_SRC_OSC8M_Val          _U_(0x6)                                             /**< (GCLK_GENCTRL) OSC8M oscillator output  */
    173. 

  173. #define   GCLK_GENCTRL_SRC_DFLL48M_Val        _U_(0x7)                                             /**< (GCLK_GENCTRL) DFLL48M output  */
    174. 

  174. #define   GCLK_GENCTRL_SRC_DPLL96M_Val        _U_(0x8)                                             /**< (GCLK_GENCTRL) DPLL96M output  */
    175. 

  175. #define GCLK_GENCTRL_SRC_XOSC                 (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)  /**< (GCLK_GENCTRL) XOSC oscillator output Position  */
    176. 

  176. #define GCLK_GENCTRL_SRC_GCLKIN               (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generator input pad Position  */
    177. 

  177. #define GCLK_GENCTRL_SRC_GCLKGEN1             (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) Generic clock generator 1 output Position  */
    178. 

  178. #define GCLK_GENCTRL_SRC_OSCULP32K            (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) OSCULP32K oscillator output Position  */
    179. 

  179. #define GCLK_GENCTRL_SRC_OSC32K               (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) OSC32K oscillator output Position  */
    180. 

  180. #define GCLK_GENCTRL_SRC_XOSC32K              (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) XOSC32K oscillator output Position  */
    181. 

  181. #define GCLK_GENCTRL_SRC_OSC8M                (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) OSC8M oscillator output Position  */
    182. 

  182. #define GCLK_GENCTRL_SRC_DFLL48M              (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DFLL48M output Position  */
    183. 

  183. #define GCLK_GENCTRL_SRC_DPLL96M              (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos) /**< (GCLK_GENCTRL) DPLL96M output Position  */
    184. 

  184. #define GCLK_GENCTRL_GENEN_Pos                _U_(16)                                              /**< (GCLK_GENCTRL) Generic Clock Generator Enable Position */
    185. 

  185. #define GCLK_GENCTRL_GENEN_Msk                (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)                 /**< (GCLK_GENCTRL) Generic Clock Generator Enable Mask */
    186. 

  186. #define GCLK_GENCTRL_GENEN(value)             (GCLK_GENCTRL_GENEN_Msk & ((value) << GCLK_GENCTRL_GENEN_Pos))
    187. 

  187. #define GCLK_GENCTRL_IDC_Pos                  _U_(17)                                              /**< (GCLK_GENCTRL) Improve Duty Cycle Position */
    188. 

  188. #define GCLK_GENCTRL_IDC_Msk                  (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)                   /**< (GCLK_GENCTRL) Improve Duty Cycle Mask */
    189. 

  189. #define GCLK_GENCTRL_IDC(value)               (GCLK_GENCTRL_IDC_Msk & ((value) << GCLK_GENCTRL_IDC_Pos))
    190. 

  190. #define GCLK_GENCTRL_OOV_Pos                  _U_(18)                                              /**< (GCLK_GENCTRL) Output Off Value Position */
    191. 

  191. #define GCLK_GENCTRL_OOV_Msk                  (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)                   /**< (GCLK_GENCTRL) Output Off Value Mask */
    192. 

  192. #define GCLK_GENCTRL_OOV(value)               (GCLK_GENCTRL_OOV_Msk & ((value) << GCLK_GENCTRL_OOV_Pos))
    193. 

  193. #define GCLK_GENCTRL_OE_Pos                   _U_(19)                                              /**< (GCLK_GENCTRL) Output Enable Position */
    194. 

  194. #define GCLK_GENCTRL_OE_Msk                   (_U_(0x1) << GCLK_GENCTRL_OE_Pos)                    /**< (GCLK_GENCTRL) Output Enable Mask */
    195. 

  195. #define GCLK_GENCTRL_OE(value)                (GCLK_GENCTRL_OE_Msk & ((value) << GCLK_GENCTRL_OE_Pos))
    196. 

  196. #define GCLK_GENCTRL_DIVSEL_Pos               _U_(20)                                              /**< (GCLK_GENCTRL) Divide Selection Position */
    197. 

  197. #define GCLK_GENCTRL_DIVSEL_Msk               (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)                /**< (GCLK_GENCTRL) Divide Selection Mask */
    198. 

  198. #define GCLK_GENCTRL_DIVSEL(value)            (GCLK_GENCTRL_DIVSEL_Msk & ((value) << GCLK_GENCTRL_DIVSEL_Pos))
    199. 

  199. #define   GCLK_GENCTRL_DIVSEL_DIV1_Val        _U_(0x0)                                             /**< (GCLK_GENCTRL) Divide input directly by divider factor  */
    200. 

  200. #define   GCLK_GENCTRL_DIVSEL_DIV2_Val        _U_(0x1)                                             /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1)  */
    201. 

  201. #define GCLK_GENCTRL_DIVSEL_DIV1              (GCLK_GENCTRL_DIVSEL_DIV1_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input directly by divider factor Position  */
    202. 

  202. #define GCLK_GENCTRL_DIVSEL_DIV2              (GCLK_GENCTRL_DIVSEL_DIV2_Val << GCLK_GENCTRL_DIVSEL_Pos) /**< (GCLK_GENCTRL) Divide input by 2^(divider factor+ 1) Position  */
    203. 

  203. #define GCLK_GENCTRL_RUNSTDBY_Pos             _U_(21)                                              /**< (GCLK_GENCTRL) Run in Standby Position */
    204. 

  204. #define GCLK_GENCTRL_RUNSTDBY_Msk             (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)              /**< (GCLK_GENCTRL) Run in Standby Mask */
    205. 

  205. #define GCLK_GENCTRL_RUNSTDBY(value)          (GCLK_GENCTRL_RUNSTDBY_Msk & ((value) << GCLK_GENCTRL_RUNSTDBY_Pos))
    206. 

  206. #define GCLK_GENCTRL_Msk                      _U_(0x003F1F0F)                                      /**< (GCLK_GENCTRL) Register Mask  */
    207. 

  207. 

  208. 

  209. /* -------- GCLK_GENDIV : (GCLK Offset: 0x08) (R/W 32) Generic Clock Generator Division -------- */
    210. 

  210. #define GCLK_GENDIV_RESETVALUE                _U_(0x00)                                            /**<  (GCLK_GENDIV) Generic Clock Generator Division  Reset Value */
    211. 

  211. 

  212. #define GCLK_GENDIV_ID_Pos                    _U_(0)                                               /**< (GCLK_GENDIV) Generic Clock Generator Selection Position */
    213. 

  213. #define GCLK_GENDIV_ID_Msk                    (_U_(0xF) << GCLK_GENDIV_ID_Pos)                     /**< (GCLK_GENDIV) Generic Clock Generator Selection Mask */
    214. 

  214. #define GCLK_GENDIV_ID(value)                 (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
    215. 

  215. #define GCLK_GENDIV_DIV_Pos                   _U_(8)                                               /**< (GCLK_GENDIV) Division Factor Position */
    216. 

  216. #define GCLK_GENDIV_DIV_Msk                   (_U_(0xFFFF) << GCLK_GENDIV_DIV_Pos)                 /**< (GCLK_GENDIV) Division Factor Mask */
    217. 

  217. #define GCLK_GENDIV_DIV(value)                (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
    218. 

  218. #define GCLK_GENDIV_Msk                       _U_(0x00FFFF0F)                                      /**< (GCLK_GENDIV) Register Mask  */
    219. 

  219. 

  220. 

  221. /** \brief GCLK register offsets definitions */
    222. 

  222. #define GCLK_CTRL_REG_OFST             (0x00)              /**< (GCLK_CTRL) Control Offset */
    223. 

  223. #define GCLK_STATUS_REG_OFST           (0x01)              /**< (GCLK_STATUS) Status Offset */
    224. 

  224. #define GCLK_CLKCTRL_REG_OFST          (0x02)              /**< (GCLK_CLKCTRL) Generic Clock Control Offset */
    225. 

  225. #define GCLK_GENCTRL_REG_OFST          (0x04)              /**< (GCLK_GENCTRL) Generic Clock Generator Control Offset */
    226. 

  226. #define GCLK_GENDIV_REG_OFST           (0x08)              /**< (GCLK_GENDIV) Generic Clock Generator Division Offset */
    227. 

  227. 

  228. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    229. 

  229. /** \brief GCLK register API structure */
    230. 

  230. typedef struct
    231. 

  231. {  /* Generic Clock Generator */
    232. 

  232.   __IO  uint8_t                        GCLK_CTRL;          /**< Offset: 0x00 (R/W  8) Control */
    233. 

  233.   __I   uint8_t                        GCLK_STATUS;        /**< Offset: 0x01 (R/   8) Status */
    234. 

  234.   __IO  uint16_t                       GCLK_CLKCTRL;       /**< Offset: 0x02 (R/W  16) Generic Clock Control */
    235. 

  235.   __IO  uint32_t                       GCLK_GENCTRL;       /**< Offset: 0x04 (R/W  32) Generic Clock Generator Control */
    236. 

  236.   __IO  uint32_t                       GCLK_GENDIV;        /**< Offset: 0x08 (R/W  32) Generic Clock Generator Division */
    237. 

  237. } gclk_registers_t;
    238. 

  238. 

  239. 

  240. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    241. 

  241. #endif /* _SAMD21_GCLK_COMPONENT_H_ */
    242.