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i2s.h

i2s.h 60 KB
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  1. /**
    2. 

  2.  * \brief Component description for I2S
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_I2S_COMPONENT_H_
    25. 

  25. #define _SAMD21_I2S_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR I2S                                          */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
    32. 

  32. #define I2S_CTRLA_RESETVALUE                  _U_(0x00)                                            /**<  (I2S_CTRLA) Control A  Reset Value */
    33. 

  33. 

  34. #define I2S_CTRLA_SWRST_Pos                   _U_(0)                                               /**< (I2S_CTRLA) Software Reset Position */
    35. 

  35. #define I2S_CTRLA_SWRST_Msk                   (_U_(0x1) << I2S_CTRLA_SWRST_Pos)                    /**< (I2S_CTRLA) Software Reset Mask */
    36. 

  36. #define I2S_CTRLA_SWRST(value)                (I2S_CTRLA_SWRST_Msk & ((value) << I2S_CTRLA_SWRST_Pos))
    37. 

  37. #define I2S_CTRLA_ENABLE_Pos                  _U_(1)                                               /**< (I2S_CTRLA) Enable Position */
    38. 

  38. #define I2S_CTRLA_ENABLE_Msk                  (_U_(0x1) << I2S_CTRLA_ENABLE_Pos)                   /**< (I2S_CTRLA) Enable Mask */
    39. 

  39. #define I2S_CTRLA_ENABLE(value)               (I2S_CTRLA_ENABLE_Msk & ((value) << I2S_CTRLA_ENABLE_Pos))
    40. 

  40. #define I2S_CTRLA_CKEN0_Pos                   _U_(2)                                               /**< (I2S_CTRLA) Clock Unit 0 Enable Position */
    41. 

  41. #define I2S_CTRLA_CKEN0_Msk                   (_U_(0x1) << I2S_CTRLA_CKEN0_Pos)                    /**< (I2S_CTRLA) Clock Unit 0 Enable Mask */
    42. 

  42. #define I2S_CTRLA_CKEN0(value)                (I2S_CTRLA_CKEN0_Msk & ((value) << I2S_CTRLA_CKEN0_Pos))
    43. 

  43. #define I2S_CTRLA_CKEN1_Pos                   _U_(3)                                               /**< (I2S_CTRLA) Clock Unit 1 Enable Position */
    44. 

  44. #define I2S_CTRLA_CKEN1_Msk                   (_U_(0x1) << I2S_CTRLA_CKEN1_Pos)                    /**< (I2S_CTRLA) Clock Unit 1 Enable Mask */
    45. 

  45. #define I2S_CTRLA_CKEN1(value)                (I2S_CTRLA_CKEN1_Msk & ((value) << I2S_CTRLA_CKEN1_Pos))
    46. 

  46. #define I2S_CTRLA_SEREN0_Pos                  _U_(4)                                               /**< (I2S_CTRLA) Serializer 0 Enable Position */
    47. 

  47. #define I2S_CTRLA_SEREN0_Msk                  (_U_(0x1) << I2S_CTRLA_SEREN0_Pos)                   /**< (I2S_CTRLA) Serializer 0 Enable Mask */
    48. 

  48. #define I2S_CTRLA_SEREN0(value)               (I2S_CTRLA_SEREN0_Msk & ((value) << I2S_CTRLA_SEREN0_Pos))
    49. 

  49. #define I2S_CTRLA_SEREN1_Pos                  _U_(5)                                               /**< (I2S_CTRLA) Serializer 1 Enable Position */
    50. 

  50. #define I2S_CTRLA_SEREN1_Msk                  (_U_(0x1) << I2S_CTRLA_SEREN1_Pos)                   /**< (I2S_CTRLA) Serializer 1 Enable Mask */
    51. 

  51. #define I2S_CTRLA_SEREN1(value)               (I2S_CTRLA_SEREN1_Msk & ((value) << I2S_CTRLA_SEREN1_Pos))
    52. 

  52. #define I2S_CTRLA_Msk                         _U_(0x3F)                                            /**< (I2S_CTRLA) Register Mask  */
    53. 

  53. 

  54. #define I2S_CTRLA_CKEN_Pos                    _U_(2)                                               /**< (I2S_CTRLA Position) Clock Unit x Enable */
    55. 

  55. #define I2S_CTRLA_CKEN_Msk                    (_U_(0x3) << I2S_CTRLA_CKEN_Pos)                     /**< (I2S_CTRLA Mask) CKEN */
    56. 

  56. #define I2S_CTRLA_CKEN(value)                 (I2S_CTRLA_CKEN_Msk & ((value) << I2S_CTRLA_CKEN_Pos)) 
    57. 

  57. #define I2S_CTRLA_SEREN_Pos                   _U_(4)                                               /**< (I2S_CTRLA Position) Serializer x Enable */
    58. 

  58. #define I2S_CTRLA_SEREN_Msk                   (_U_(0x3) << I2S_CTRLA_SEREN_Pos)                    /**< (I2S_CTRLA Mask) SEREN */
    59. 

  59. #define I2S_CTRLA_SEREN(value)                (I2S_CTRLA_SEREN_Msk & ((value) << I2S_CTRLA_SEREN_Pos)) 
    60. 

  60. 

  61. /* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
    62. 

  62. #define I2S_CLKCTRL_RESETVALUE                _U_(0x00)                                            /**<  (I2S_CLKCTRL) Clock Unit n Control  Reset Value */
    63. 

  63. 

  64. #define I2S_CLKCTRL_SLOTSIZE_Pos              _U_(0)                                               /**< (I2S_CLKCTRL) Slot Size Position */
    65. 

  65. #define I2S_CLKCTRL_SLOTSIZE_Msk              (_U_(0x3) << I2S_CLKCTRL_SLOTSIZE_Pos)               /**< (I2S_CLKCTRL) Slot Size Mask */
    66. 

  66. #define I2S_CLKCTRL_SLOTSIZE(value)           (I2S_CLKCTRL_SLOTSIZE_Msk & ((value) << I2S_CLKCTRL_SLOTSIZE_Pos))
    67. 

  67. #define   I2S_CLKCTRL_SLOTSIZE_8_Val          _U_(0x0)                                             /**< (I2S_CLKCTRL) 8-bit Slot for Clock Unit n  */
    68. 

  68. #define   I2S_CLKCTRL_SLOTSIZE_16_Val         _U_(0x1)                                             /**< (I2S_CLKCTRL) 16-bit Slot for Clock Unit n  */
    69. 

  69. #define   I2S_CLKCTRL_SLOTSIZE_24_Val         _U_(0x2)                                             /**< (I2S_CLKCTRL) 24-bit Slot for Clock Unit n  */
    70. 

  70. #define   I2S_CLKCTRL_SLOTSIZE_32_Val         _U_(0x3)                                             /**< (I2S_CLKCTRL) 32-bit Slot for Clock Unit n  */
    71. 

  71. #define I2S_CLKCTRL_SLOTSIZE_8                (I2S_CLKCTRL_SLOTSIZE_8_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 8-bit Slot for Clock Unit n Position  */
    72. 

  72. #define I2S_CLKCTRL_SLOTSIZE_16               (I2S_CLKCTRL_SLOTSIZE_16_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 16-bit Slot for Clock Unit n Position  */
    73. 

  73. #define I2S_CLKCTRL_SLOTSIZE_24               (I2S_CLKCTRL_SLOTSIZE_24_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 24-bit Slot for Clock Unit n Position  */
    74. 

  74. #define I2S_CLKCTRL_SLOTSIZE_32               (I2S_CLKCTRL_SLOTSIZE_32_Val << I2S_CLKCTRL_SLOTSIZE_Pos) /**< (I2S_CLKCTRL) 32-bit Slot for Clock Unit n Position  */
    75. 

  75. #define I2S_CLKCTRL_NBSLOTS_Pos               _U_(2)                                               /**< (I2S_CLKCTRL) Number of Slots in Frame Position */
    76. 

  76. #define I2S_CLKCTRL_NBSLOTS_Msk               (_U_(0x7) << I2S_CLKCTRL_NBSLOTS_Pos)                /**< (I2S_CLKCTRL) Number of Slots in Frame Mask */
    77. 

  77. #define I2S_CLKCTRL_NBSLOTS(value)            (I2S_CLKCTRL_NBSLOTS_Msk & ((value) << I2S_CLKCTRL_NBSLOTS_Pos))
    78. 

  78. #define I2S_CLKCTRL_FSWIDTH_Pos               _U_(5)                                               /**< (I2S_CLKCTRL) Frame Sync Width Position */
    79. 

  79. #define I2S_CLKCTRL_FSWIDTH_Msk               (_U_(0x3) << I2S_CLKCTRL_FSWIDTH_Pos)                /**< (I2S_CLKCTRL) Frame Sync Width Mask */
    80. 

  80. #define I2S_CLKCTRL_FSWIDTH(value)            (I2S_CLKCTRL_FSWIDTH_Msk & ((value) << I2S_CLKCTRL_FSWIDTH_Pos))
    81. 

  81. #define   I2S_CLKCTRL_FSWIDTH_SLOT_Val        _U_(0x0)                                             /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol)  */
    82. 

  82. #define   I2S_CLKCTRL_FSWIDTH_HALF_Val        _U_(0x1)                                             /**< (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide  */
    83. 

  83. #define   I2S_CLKCTRL_FSWIDTH_BIT_Val         _U_(0x2)                                             /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide  */
    84. 

  84. #define   I2S_CLKCTRL_FSWIDTH_BURST_Val       _U_(0x3)                                             /**< (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested  */
    85. 

  85. #define I2S_CLKCTRL_FSWIDTH_SLOT              (I2S_CLKCTRL_FSWIDTH_SLOT_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Slot wide (default for I2S protocol) Position  */
    86. 

  86. #define I2S_CLKCTRL_FSWIDTH_HALF              (I2S_CLKCTRL_FSWIDTH_HALF_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Pulse is half a Frame wide Position  */
    87. 

  87. #define I2S_CLKCTRL_FSWIDTH_BIT               (I2S_CLKCTRL_FSWIDTH_BIT_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Frame Sync Pulse is 1 Bit wide Position  */
    88. 

  88. #define I2S_CLKCTRL_FSWIDTH_BURST             (I2S_CLKCTRL_FSWIDTH_BURST_Val << I2S_CLKCTRL_FSWIDTH_Pos) /**< (I2S_CLKCTRL) Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested Position  */
    89. 

  89. #define I2S_CLKCTRL_BITDELAY_Pos              _U_(7)                                               /**< (I2S_CLKCTRL) Data Delay from Frame Sync Position */
    90. 

  90. #define I2S_CLKCTRL_BITDELAY_Msk              (_U_(0x1) << I2S_CLKCTRL_BITDELAY_Pos)               /**< (I2S_CLKCTRL) Data Delay from Frame Sync Mask */
    91. 

  91. #define I2S_CLKCTRL_BITDELAY(value)           (I2S_CLKCTRL_BITDELAY_Msk & ((value) << I2S_CLKCTRL_BITDELAY_Pos))
    92. 

  92. #define   I2S_CLKCTRL_BITDELAY_LJ_Val         _U_(0x0)                                             /**< (I2S_CLKCTRL) Left Justified (0 Bit Delay)  */
    93. 

  93. #define   I2S_CLKCTRL_BITDELAY_I2S_Val        _U_(0x1)                                             /**< (I2S_CLKCTRL) I2S (1 Bit Delay)  */
    94. 

  94. #define I2S_CLKCTRL_BITDELAY_LJ               (I2S_CLKCTRL_BITDELAY_LJ_Val << I2S_CLKCTRL_BITDELAY_Pos) /**< (I2S_CLKCTRL) Left Justified (0 Bit Delay) Position  */
    95. 

  95. #define I2S_CLKCTRL_BITDELAY_I2S              (I2S_CLKCTRL_BITDELAY_I2S_Val << I2S_CLKCTRL_BITDELAY_Pos) /**< (I2S_CLKCTRL) I2S (1 Bit Delay) Position  */
    96. 

  96. #define I2S_CLKCTRL_FSSEL_Pos                 _U_(8)                                               /**< (I2S_CLKCTRL) Frame Sync Select Position */
    97. 

  97. #define I2S_CLKCTRL_FSSEL_Msk                 (_U_(0x1) << I2S_CLKCTRL_FSSEL_Pos)                  /**< (I2S_CLKCTRL) Frame Sync Select Mask */
    98. 

  98. #define I2S_CLKCTRL_FSSEL(value)              (I2S_CLKCTRL_FSSEL_Msk & ((value) << I2S_CLKCTRL_FSSEL_Pos))
    99. 

  99. #define   I2S_CLKCTRL_FSSEL_SCKDIV_Val        _U_(0x0)                                             /**< (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source  */
    100. 

  100. #define   I2S_CLKCTRL_FSSEL_FSPIN_Val         _U_(0x1)                                             /**< (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source  */
    101. 

  101. #define I2S_CLKCTRL_FSSEL_SCKDIV              (I2S_CLKCTRL_FSSEL_SCKDIV_Val << I2S_CLKCTRL_FSSEL_Pos) /**< (I2S_CLKCTRL) Divided Serial Clock n is used as Frame Sync n source Position  */
    102. 

  102. #define I2S_CLKCTRL_FSSEL_FSPIN               (I2S_CLKCTRL_FSSEL_FSPIN_Val << I2S_CLKCTRL_FSSEL_Pos) /**< (I2S_CLKCTRL) FSn input pin is used as Frame Sync n source Position  */
    103. 

  103. #define I2S_CLKCTRL_FSINV_Pos                 _U_(11)                                              /**< (I2S_CLKCTRL) Frame Sync Invert Position */
    104. 

  104. #define I2S_CLKCTRL_FSINV_Msk                 (_U_(0x1) << I2S_CLKCTRL_FSINV_Pos)                  /**< (I2S_CLKCTRL) Frame Sync Invert Mask */
    105. 

  105. #define I2S_CLKCTRL_FSINV(value)              (I2S_CLKCTRL_FSINV_Msk & ((value) << I2S_CLKCTRL_FSINV_Pos))
    106. 

  106. #define I2S_CLKCTRL_SCKSEL_Pos                _U_(12)                                              /**< (I2S_CLKCTRL) Serial Clock Select Position */
    107. 

  107. #define I2S_CLKCTRL_SCKSEL_Msk                (_U_(0x1) << I2S_CLKCTRL_SCKSEL_Pos)                 /**< (I2S_CLKCTRL) Serial Clock Select Mask */
    108. 

  108. #define I2S_CLKCTRL_SCKSEL(value)             (I2S_CLKCTRL_SCKSEL_Msk & ((value) << I2S_CLKCTRL_SCKSEL_Pos))
    109. 

  109. #define   I2S_CLKCTRL_SCKSEL_MCKDIV_Val       _U_(0x0)                                             /**< (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source  */
    110. 

  110. #define   I2S_CLKCTRL_SCKSEL_SCKPIN_Val       _U_(0x1)                                             /**< (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source  */
    111. 

  111. #define I2S_CLKCTRL_SCKSEL_MCKDIV             (I2S_CLKCTRL_SCKSEL_MCKDIV_Val << I2S_CLKCTRL_SCKSEL_Pos) /**< (I2S_CLKCTRL) Divided Master Clock n is used as Serial Clock n source Position  */
    112. 

  112. #define I2S_CLKCTRL_SCKSEL_SCKPIN             (I2S_CLKCTRL_SCKSEL_SCKPIN_Val << I2S_CLKCTRL_SCKSEL_Pos) /**< (I2S_CLKCTRL) SCKn input pin is used as Serial Clock n source Position  */
    113. 

  113. #define I2S_CLKCTRL_MCKSEL_Pos                _U_(16)                                              /**< (I2S_CLKCTRL) Master Clock Select Position */
    114. 

  114. #define I2S_CLKCTRL_MCKSEL_Msk                (_U_(0x1) << I2S_CLKCTRL_MCKSEL_Pos)                 /**< (I2S_CLKCTRL) Master Clock Select Mask */
    115. 

  115. #define I2S_CLKCTRL_MCKSEL(value)             (I2S_CLKCTRL_MCKSEL_Msk & ((value) << I2S_CLKCTRL_MCKSEL_Pos))
    116. 

  116. #define   I2S_CLKCTRL_MCKSEL_GCLK_Val         _U_(0x0)                                             /**< (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source  */
    117. 

  117. #define   I2S_CLKCTRL_MCKSEL_MCKPIN_Val       _U_(0x1)                                             /**< (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source  */
    118. 

  118. #define I2S_CLKCTRL_MCKSEL_GCLK               (I2S_CLKCTRL_MCKSEL_GCLK_Val << I2S_CLKCTRL_MCKSEL_Pos) /**< (I2S_CLKCTRL) GCLK_I2S_n is used as Master Clock n source Position  */
    119. 

  119. #define I2S_CLKCTRL_MCKSEL_MCKPIN             (I2S_CLKCTRL_MCKSEL_MCKPIN_Val << I2S_CLKCTRL_MCKSEL_Pos) /**< (I2S_CLKCTRL) MCKn input pin is used as Master Clock n source Position  */
    120. 

  120. #define I2S_CLKCTRL_MCKEN_Pos                 _U_(18)                                              /**< (I2S_CLKCTRL) Master Clock Enable Position */
    121. 

  121. #define I2S_CLKCTRL_MCKEN_Msk                 (_U_(0x1) << I2S_CLKCTRL_MCKEN_Pos)                  /**< (I2S_CLKCTRL) Master Clock Enable Mask */
    122. 

  122. #define I2S_CLKCTRL_MCKEN(value)              (I2S_CLKCTRL_MCKEN_Msk & ((value) << I2S_CLKCTRL_MCKEN_Pos))
    123. 

  123. #define I2S_CLKCTRL_MCKDIV_Pos                _U_(19)                                              /**< (I2S_CLKCTRL) Master Clock Division Factor Position */
    124. 

  124. #define I2S_CLKCTRL_MCKDIV_Msk                (_U_(0x1F) << I2S_CLKCTRL_MCKDIV_Pos)                /**< (I2S_CLKCTRL) Master Clock Division Factor Mask */
    125. 

  125. #define I2S_CLKCTRL_MCKDIV(value)             (I2S_CLKCTRL_MCKDIV_Msk & ((value) << I2S_CLKCTRL_MCKDIV_Pos))
    126. 

  126. #define I2S_CLKCTRL_MCKOUTDIV_Pos             _U_(24)                                              /**< (I2S_CLKCTRL) Master Clock Output Division Factor Position */
    127. 

  127. #define I2S_CLKCTRL_MCKOUTDIV_Msk             (_U_(0x1F) << I2S_CLKCTRL_MCKOUTDIV_Pos)             /**< (I2S_CLKCTRL) Master Clock Output Division Factor Mask */
    128. 

  128. #define I2S_CLKCTRL_MCKOUTDIV(value)          (I2S_CLKCTRL_MCKOUTDIV_Msk & ((value) << I2S_CLKCTRL_MCKOUTDIV_Pos))
    129. 

  129. #define I2S_CLKCTRL_FSOUTINV_Pos              _U_(29)                                              /**< (I2S_CLKCTRL) Frame Sync Output Invert Position */
    130. 

  130. #define I2S_CLKCTRL_FSOUTINV_Msk              (_U_(0x1) << I2S_CLKCTRL_FSOUTINV_Pos)               /**< (I2S_CLKCTRL) Frame Sync Output Invert Mask */
    131. 

  131. #define I2S_CLKCTRL_FSOUTINV(value)           (I2S_CLKCTRL_FSOUTINV_Msk & ((value) << I2S_CLKCTRL_FSOUTINV_Pos))
    132. 

  132. #define I2S_CLKCTRL_SCKOUTINV_Pos             _U_(30)                                              /**< (I2S_CLKCTRL) Serial Clock Output Invert Position */
    133. 

  133. #define I2S_CLKCTRL_SCKOUTINV_Msk             (_U_(0x1) << I2S_CLKCTRL_SCKOUTINV_Pos)              /**< (I2S_CLKCTRL) Serial Clock Output Invert Mask */
    134. 

  134. #define I2S_CLKCTRL_SCKOUTINV(value)          (I2S_CLKCTRL_SCKOUTINV_Msk & ((value) << I2S_CLKCTRL_SCKOUTINV_Pos))
    135. 

  135. #define I2S_CLKCTRL_MCKOUTINV_Pos             _U_(31)                                              /**< (I2S_CLKCTRL) Master Clock Output Invert Position */
    136. 

  136. #define I2S_CLKCTRL_MCKOUTINV_Msk             (_U_(0x1) << I2S_CLKCTRL_MCKOUTINV_Pos)              /**< (I2S_CLKCTRL) Master Clock Output Invert Mask */
    137. 

  137. #define I2S_CLKCTRL_MCKOUTINV(value)          (I2S_CLKCTRL_MCKOUTINV_Msk & ((value) << I2S_CLKCTRL_MCKOUTINV_Pos))
    138. 

  138. #define I2S_CLKCTRL_Msk                       _U_(0xFFFD19FF)                                      /**< (I2S_CLKCTRL) Register Mask  */
    139. 

  139. 

  140. 

  141. /* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
    142. 

  142. #define I2S_INTENCLR_RESETVALUE               _U_(0x00)                                            /**<  (I2S_INTENCLR) Interrupt Enable Clear  Reset Value */
    143. 

  143. 

  144. #define I2S_INTENCLR_RXRDY0_Pos               _U_(0)                                               /**< (I2S_INTENCLR) Receive Ready 0 Interrupt Enable Position */
    145. 

  145. #define I2S_INTENCLR_RXRDY0_Msk               (_U_(0x1) << I2S_INTENCLR_RXRDY0_Pos)                /**< (I2S_INTENCLR) Receive Ready 0 Interrupt Enable Mask */
    146. 

  146. #define I2S_INTENCLR_RXRDY0(value)            (I2S_INTENCLR_RXRDY0_Msk & ((value) << I2S_INTENCLR_RXRDY0_Pos))
    147. 

  147. #define I2S_INTENCLR_RXRDY1_Pos               _U_(1)                                               /**< (I2S_INTENCLR) Receive Ready 1 Interrupt Enable Position */
    148. 

  148. #define I2S_INTENCLR_RXRDY1_Msk               (_U_(0x1) << I2S_INTENCLR_RXRDY1_Pos)                /**< (I2S_INTENCLR) Receive Ready 1 Interrupt Enable Mask */
    149. 

  149. #define I2S_INTENCLR_RXRDY1(value)            (I2S_INTENCLR_RXRDY1_Msk & ((value) << I2S_INTENCLR_RXRDY1_Pos))
    150. 

  150. #define I2S_INTENCLR_RXOR0_Pos                _U_(4)                                               /**< (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable Position */
    151. 

  151. #define I2S_INTENCLR_RXOR0_Msk                (_U_(0x1) << I2S_INTENCLR_RXOR0_Pos)                 /**< (I2S_INTENCLR) Receive Overrun 0 Interrupt Enable Mask */
    152. 

  152. #define I2S_INTENCLR_RXOR0(value)             (I2S_INTENCLR_RXOR0_Msk & ((value) << I2S_INTENCLR_RXOR0_Pos))
    153. 

  153. #define I2S_INTENCLR_RXOR1_Pos                _U_(5)                                               /**< (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable Position */
    154. 

  154. #define I2S_INTENCLR_RXOR1_Msk                (_U_(0x1) << I2S_INTENCLR_RXOR1_Pos)                 /**< (I2S_INTENCLR) Receive Overrun 1 Interrupt Enable Mask */
    155. 

  155. #define I2S_INTENCLR_RXOR1(value)             (I2S_INTENCLR_RXOR1_Msk & ((value) << I2S_INTENCLR_RXOR1_Pos))
    156. 

  156. #define I2S_INTENCLR_TXRDY0_Pos               _U_(8)                                               /**< (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable Position */
    157. 

  157. #define I2S_INTENCLR_TXRDY0_Msk               (_U_(0x1) << I2S_INTENCLR_TXRDY0_Pos)                /**< (I2S_INTENCLR) Transmit Ready 0 Interrupt Enable Mask */
    158. 

  158. #define I2S_INTENCLR_TXRDY0(value)            (I2S_INTENCLR_TXRDY0_Msk & ((value) << I2S_INTENCLR_TXRDY0_Pos))
    159. 

  159. #define I2S_INTENCLR_TXRDY1_Pos               _U_(9)                                               /**< (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable Position */
    160. 

  160. #define I2S_INTENCLR_TXRDY1_Msk               (_U_(0x1) << I2S_INTENCLR_TXRDY1_Pos)                /**< (I2S_INTENCLR) Transmit Ready 1 Interrupt Enable Mask */
    161. 

  161. #define I2S_INTENCLR_TXRDY1(value)            (I2S_INTENCLR_TXRDY1_Msk & ((value) << I2S_INTENCLR_TXRDY1_Pos))
    162. 

  162. #define I2S_INTENCLR_TXUR0_Pos                _U_(12)                                              /**< (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable Position */
    163. 

  163. #define I2S_INTENCLR_TXUR0_Msk                (_U_(0x1) << I2S_INTENCLR_TXUR0_Pos)                 /**< (I2S_INTENCLR) Transmit Underrun 0 Interrupt Enable Mask */
    164. 

  164. #define I2S_INTENCLR_TXUR0(value)             (I2S_INTENCLR_TXUR0_Msk & ((value) << I2S_INTENCLR_TXUR0_Pos))
    165. 

  165. #define I2S_INTENCLR_TXUR1_Pos                _U_(13)                                              /**< (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable Position */
    166. 

  166. #define I2S_INTENCLR_TXUR1_Msk                (_U_(0x1) << I2S_INTENCLR_TXUR1_Pos)                 /**< (I2S_INTENCLR) Transmit Underrun 1 Interrupt Enable Mask */
    167. 

  167. #define I2S_INTENCLR_TXUR1(value)             (I2S_INTENCLR_TXUR1_Msk & ((value) << I2S_INTENCLR_TXUR1_Pos))
    168. 

  168. #define I2S_INTENCLR_Msk                      _U_(0x3333)                                          /**< (I2S_INTENCLR) Register Mask  */
    169. 

  169. 

  170. #define I2S_INTENCLR_RXRDY_Pos                _U_(0)                                               /**< (I2S_INTENCLR Position) Receive Ready x Interrupt Enable */
    171. 

  171. #define I2S_INTENCLR_RXRDY_Msk                (_U_(0x3) << I2S_INTENCLR_RXRDY_Pos)                 /**< (I2S_INTENCLR Mask) RXRDY */
    172. 

  172. #define I2S_INTENCLR_RXRDY(value)             (I2S_INTENCLR_RXRDY_Msk & ((value) << I2S_INTENCLR_RXRDY_Pos)) 
    173. 

  173. #define I2S_INTENCLR_RXOR_Pos                 _U_(4)                                               /**< (I2S_INTENCLR Position) Receive Overrun x Interrupt Enable */
    174. 

  174. #define I2S_INTENCLR_RXOR_Msk                 (_U_(0x3) << I2S_INTENCLR_RXOR_Pos)                  /**< (I2S_INTENCLR Mask) RXOR */
    175. 

  175. #define I2S_INTENCLR_RXOR(value)              (I2S_INTENCLR_RXOR_Msk & ((value) << I2S_INTENCLR_RXOR_Pos)) 
    176. 

  176. #define I2S_INTENCLR_TXRDY_Pos                _U_(8)                                               /**< (I2S_INTENCLR Position) Transmit Ready x Interrupt Enable */
    177. 

  177. #define I2S_INTENCLR_TXRDY_Msk                (_U_(0x3) << I2S_INTENCLR_TXRDY_Pos)                 /**< (I2S_INTENCLR Mask) TXRDY */
    178. 

  178. #define I2S_INTENCLR_TXRDY(value)             (I2S_INTENCLR_TXRDY_Msk & ((value) << I2S_INTENCLR_TXRDY_Pos)) 
    179. 

  179. #define I2S_INTENCLR_TXUR_Pos                 _U_(12)                                              /**< (I2S_INTENCLR Position) Transmit Underrun x Interrupt Enable */
    180. 

  180. #define I2S_INTENCLR_TXUR_Msk                 (_U_(0x3) << I2S_INTENCLR_TXUR_Pos)                  /**< (I2S_INTENCLR Mask) TXUR */
    181. 

  181. #define I2S_INTENCLR_TXUR(value)              (I2S_INTENCLR_TXUR_Msk & ((value) << I2S_INTENCLR_TXUR_Pos)) 
    182. 

  182. 

  183. /* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
    184. 

  184. #define I2S_INTENSET_RESETVALUE               _U_(0x00)                                            /**<  (I2S_INTENSET) Interrupt Enable Set  Reset Value */
    185. 

  185. 

  186. #define I2S_INTENSET_RXRDY0_Pos               _U_(0)                                               /**< (I2S_INTENSET) Receive Ready 0 Interrupt Enable Position */
    187. 

  187. #define I2S_INTENSET_RXRDY0_Msk               (_U_(0x1) << I2S_INTENSET_RXRDY0_Pos)                /**< (I2S_INTENSET) Receive Ready 0 Interrupt Enable Mask */
    188. 

  188. #define I2S_INTENSET_RXRDY0(value)            (I2S_INTENSET_RXRDY0_Msk & ((value) << I2S_INTENSET_RXRDY0_Pos))
    189. 

  189. #define I2S_INTENSET_RXRDY1_Pos               _U_(1)                                               /**< (I2S_INTENSET) Receive Ready 1 Interrupt Enable Position */
    190. 

  190. #define I2S_INTENSET_RXRDY1_Msk               (_U_(0x1) << I2S_INTENSET_RXRDY1_Pos)                /**< (I2S_INTENSET) Receive Ready 1 Interrupt Enable Mask */
    191. 

  191. #define I2S_INTENSET_RXRDY1(value)            (I2S_INTENSET_RXRDY1_Msk & ((value) << I2S_INTENSET_RXRDY1_Pos))
    192. 

  192. #define I2S_INTENSET_RXOR0_Pos                _U_(4)                                               /**< (I2S_INTENSET) Receive Overrun 0 Interrupt Enable Position */
    193. 

  193. #define I2S_INTENSET_RXOR0_Msk                (_U_(0x1) << I2S_INTENSET_RXOR0_Pos)                 /**< (I2S_INTENSET) Receive Overrun 0 Interrupt Enable Mask */
    194. 

  194. #define I2S_INTENSET_RXOR0(value)             (I2S_INTENSET_RXOR0_Msk & ((value) << I2S_INTENSET_RXOR0_Pos))
    195. 

  195. #define I2S_INTENSET_RXOR1_Pos                _U_(5)                                               /**< (I2S_INTENSET) Receive Overrun 1 Interrupt Enable Position */
    196. 

  196. #define I2S_INTENSET_RXOR1_Msk                (_U_(0x1) << I2S_INTENSET_RXOR1_Pos)                 /**< (I2S_INTENSET) Receive Overrun 1 Interrupt Enable Mask */
    197. 

  197. #define I2S_INTENSET_RXOR1(value)             (I2S_INTENSET_RXOR1_Msk & ((value) << I2S_INTENSET_RXOR1_Pos))
    198. 

  198. #define I2S_INTENSET_TXRDY0_Pos               _U_(8)                                               /**< (I2S_INTENSET) Transmit Ready 0 Interrupt Enable Position */
    199. 

  199. #define I2S_INTENSET_TXRDY0_Msk               (_U_(0x1) << I2S_INTENSET_TXRDY0_Pos)                /**< (I2S_INTENSET) Transmit Ready 0 Interrupt Enable Mask */
    200. 

  200. #define I2S_INTENSET_TXRDY0(value)            (I2S_INTENSET_TXRDY0_Msk & ((value) << I2S_INTENSET_TXRDY0_Pos))
    201. 

  201. #define I2S_INTENSET_TXRDY1_Pos               _U_(9)                                               /**< (I2S_INTENSET) Transmit Ready 1 Interrupt Enable Position */
    202. 

  202. #define I2S_INTENSET_TXRDY1_Msk               (_U_(0x1) << I2S_INTENSET_TXRDY1_Pos)                /**< (I2S_INTENSET) Transmit Ready 1 Interrupt Enable Mask */
    203. 

  203. #define I2S_INTENSET_TXRDY1(value)            (I2S_INTENSET_TXRDY1_Msk & ((value) << I2S_INTENSET_TXRDY1_Pos))
    204. 

  204. #define I2S_INTENSET_TXUR0_Pos                _U_(12)                                              /**< (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable Position */
    205. 

  205. #define I2S_INTENSET_TXUR0_Msk                (_U_(0x1) << I2S_INTENSET_TXUR0_Pos)                 /**< (I2S_INTENSET) Transmit Underrun 0 Interrupt Enable Mask */
    206. 

  206. #define I2S_INTENSET_TXUR0(value)             (I2S_INTENSET_TXUR0_Msk & ((value) << I2S_INTENSET_TXUR0_Pos))
    207. 

  207. #define I2S_INTENSET_TXUR1_Pos                _U_(13)                                              /**< (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable Position */
    208. 

  208. #define I2S_INTENSET_TXUR1_Msk                (_U_(0x1) << I2S_INTENSET_TXUR1_Pos)                 /**< (I2S_INTENSET) Transmit Underrun 1 Interrupt Enable Mask */
    209. 

  209. #define I2S_INTENSET_TXUR1(value)             (I2S_INTENSET_TXUR1_Msk & ((value) << I2S_INTENSET_TXUR1_Pos))
    210. 

  210. #define I2S_INTENSET_Msk                      _U_(0x3333)                                          /**< (I2S_INTENSET) Register Mask  */
    211. 

  211. 

  212. #define I2S_INTENSET_RXRDY_Pos                _U_(0)                                               /**< (I2S_INTENSET Position) Receive Ready x Interrupt Enable */
    213. 

  213. #define I2S_INTENSET_RXRDY_Msk                (_U_(0x3) << I2S_INTENSET_RXRDY_Pos)                 /**< (I2S_INTENSET Mask) RXRDY */
    214. 

  214. #define I2S_INTENSET_RXRDY(value)             (I2S_INTENSET_RXRDY_Msk & ((value) << I2S_INTENSET_RXRDY_Pos)) 
    215. 

  215. #define I2S_INTENSET_RXOR_Pos                 _U_(4)                                               /**< (I2S_INTENSET Position) Receive Overrun x Interrupt Enable */
    216. 

  216. #define I2S_INTENSET_RXOR_Msk                 (_U_(0x3) << I2S_INTENSET_RXOR_Pos)                  /**< (I2S_INTENSET Mask) RXOR */
    217. 

  217. #define I2S_INTENSET_RXOR(value)              (I2S_INTENSET_RXOR_Msk & ((value) << I2S_INTENSET_RXOR_Pos)) 
    218. 

  218. #define I2S_INTENSET_TXRDY_Pos                _U_(8)                                               /**< (I2S_INTENSET Position) Transmit Ready x Interrupt Enable */
    219. 

  219. #define I2S_INTENSET_TXRDY_Msk                (_U_(0x3) << I2S_INTENSET_TXRDY_Pos)                 /**< (I2S_INTENSET Mask) TXRDY */
    220. 

  220. #define I2S_INTENSET_TXRDY(value)             (I2S_INTENSET_TXRDY_Msk & ((value) << I2S_INTENSET_TXRDY_Pos)) 
    221. 

  221. #define I2S_INTENSET_TXUR_Pos                 _U_(12)                                              /**< (I2S_INTENSET Position) Transmit Underrun x Interrupt Enable */
    222. 

  222. #define I2S_INTENSET_TXUR_Msk                 (_U_(0x3) << I2S_INTENSET_TXUR_Pos)                  /**< (I2S_INTENSET Mask) TXUR */
    223. 

  223. #define I2S_INTENSET_TXUR(value)              (I2S_INTENSET_TXUR_Msk & ((value) << I2S_INTENSET_TXUR_Pos)) 
    224. 

  224. 

  225. /* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
    226. 

  226. #define I2S_INTFLAG_RESETVALUE                _U_(0x00)                                            /**<  (I2S_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    227. 

  227. 

  228. #define I2S_INTFLAG_RXRDY0_Pos                _U_(0)                                               /**< (I2S_INTFLAG) Receive Ready 0 Position */
    229. 

  229. #define I2S_INTFLAG_RXRDY0_Msk                (_U_(0x1) << I2S_INTFLAG_RXRDY0_Pos)                 /**< (I2S_INTFLAG) Receive Ready 0 Mask */
    230. 

  230. #define I2S_INTFLAG_RXRDY0(value)             (I2S_INTFLAG_RXRDY0_Msk & ((value) << I2S_INTFLAG_RXRDY0_Pos))
    231. 

  231. #define I2S_INTFLAG_RXRDY1_Pos                _U_(1)                                               /**< (I2S_INTFLAG) Receive Ready 1 Position */
    232. 

  232. #define I2S_INTFLAG_RXRDY1_Msk                (_U_(0x1) << I2S_INTFLAG_RXRDY1_Pos)                 /**< (I2S_INTFLAG) Receive Ready 1 Mask */
    233. 

  233. #define I2S_INTFLAG_RXRDY1(value)             (I2S_INTFLAG_RXRDY1_Msk & ((value) << I2S_INTFLAG_RXRDY1_Pos))
    234. 

  234. #define I2S_INTFLAG_RXOR0_Pos                 _U_(4)                                               /**< (I2S_INTFLAG) Receive Overrun 0 Position */
    235. 

  235. #define I2S_INTFLAG_RXOR0_Msk                 (_U_(0x1) << I2S_INTFLAG_RXOR0_Pos)                  /**< (I2S_INTFLAG) Receive Overrun 0 Mask */
    236. 

  236. #define I2S_INTFLAG_RXOR0(value)              (I2S_INTFLAG_RXOR0_Msk & ((value) << I2S_INTFLAG_RXOR0_Pos))
    237. 

  237. #define I2S_INTFLAG_RXOR1_Pos                 _U_(5)                                               /**< (I2S_INTFLAG) Receive Overrun 1 Position */
    238. 

  238. #define I2S_INTFLAG_RXOR1_Msk                 (_U_(0x1) << I2S_INTFLAG_RXOR1_Pos)                  /**< (I2S_INTFLAG) Receive Overrun 1 Mask */
    239. 

  239. #define I2S_INTFLAG_RXOR1(value)              (I2S_INTFLAG_RXOR1_Msk & ((value) << I2S_INTFLAG_RXOR1_Pos))
    240. 

  240. #define I2S_INTFLAG_TXRDY0_Pos                _U_(8)                                               /**< (I2S_INTFLAG) Transmit Ready 0 Position */
    241. 

  241. #define I2S_INTFLAG_TXRDY0_Msk                (_U_(0x1) << I2S_INTFLAG_TXRDY0_Pos)                 /**< (I2S_INTFLAG) Transmit Ready 0 Mask */
    242. 

  242. #define I2S_INTFLAG_TXRDY0(value)             (I2S_INTFLAG_TXRDY0_Msk & ((value) << I2S_INTFLAG_TXRDY0_Pos))
    243. 

  243. #define I2S_INTFLAG_TXRDY1_Pos                _U_(9)                                               /**< (I2S_INTFLAG) Transmit Ready 1 Position */
    244. 

  244. #define I2S_INTFLAG_TXRDY1_Msk                (_U_(0x1) << I2S_INTFLAG_TXRDY1_Pos)                 /**< (I2S_INTFLAG) Transmit Ready 1 Mask */
    245. 

  245. #define I2S_INTFLAG_TXRDY1(value)             (I2S_INTFLAG_TXRDY1_Msk & ((value) << I2S_INTFLAG_TXRDY1_Pos))
    246. 

  246. #define I2S_INTFLAG_TXUR0_Pos                 _U_(12)                                              /**< (I2S_INTFLAG) Transmit Underrun 0 Position */
    247. 

  247. #define I2S_INTFLAG_TXUR0_Msk                 (_U_(0x1) << I2S_INTFLAG_TXUR0_Pos)                  /**< (I2S_INTFLAG) Transmit Underrun 0 Mask */
    248. 

  248. #define I2S_INTFLAG_TXUR0(value)              (I2S_INTFLAG_TXUR0_Msk & ((value) << I2S_INTFLAG_TXUR0_Pos))
    249. 

  249. #define I2S_INTFLAG_TXUR1_Pos                 _U_(13)                                              /**< (I2S_INTFLAG) Transmit Underrun 1 Position */
    250. 

  250. #define I2S_INTFLAG_TXUR1_Msk                 (_U_(0x1) << I2S_INTFLAG_TXUR1_Pos)                  /**< (I2S_INTFLAG) Transmit Underrun 1 Mask */
    251. 

  251. #define I2S_INTFLAG_TXUR1(value)              (I2S_INTFLAG_TXUR1_Msk & ((value) << I2S_INTFLAG_TXUR1_Pos))
    252. 

  252. #define I2S_INTFLAG_Msk                       _U_(0x3333)                                          /**< (I2S_INTFLAG) Register Mask  */
    253. 

  253. 

  254. #define I2S_INTFLAG_RXRDY_Pos                 _U_(0)                                               /**< (I2S_INTFLAG Position) Receive Ready x */
    255. 

  255. #define I2S_INTFLAG_RXRDY_Msk                 (_U_(0x3) << I2S_INTFLAG_RXRDY_Pos)                  /**< (I2S_INTFLAG Mask) RXRDY */
    256. 

  256. #define I2S_INTFLAG_RXRDY(value)              (I2S_INTFLAG_RXRDY_Msk & ((value) << I2S_INTFLAG_RXRDY_Pos)) 
    257. 

  257. #define I2S_INTFLAG_RXOR_Pos                  _U_(4)                                               /**< (I2S_INTFLAG Position) Receive Overrun x */
    258. 

  258. #define I2S_INTFLAG_RXOR_Msk                  (_U_(0x3) << I2S_INTFLAG_RXOR_Pos)                   /**< (I2S_INTFLAG Mask) RXOR */
    259. 

  259. #define I2S_INTFLAG_RXOR(value)               (I2S_INTFLAG_RXOR_Msk & ((value) << I2S_INTFLAG_RXOR_Pos)) 
    260. 

  260. #define I2S_INTFLAG_TXRDY_Pos                 _U_(8)                                               /**< (I2S_INTFLAG Position) Transmit Ready x */
    261. 

  261. #define I2S_INTFLAG_TXRDY_Msk                 (_U_(0x3) << I2S_INTFLAG_TXRDY_Pos)                  /**< (I2S_INTFLAG Mask) TXRDY */
    262. 

  262. #define I2S_INTFLAG_TXRDY(value)              (I2S_INTFLAG_TXRDY_Msk & ((value) << I2S_INTFLAG_TXRDY_Pos)) 
    263. 

  263. #define I2S_INTFLAG_TXUR_Pos                  _U_(12)                                              /**< (I2S_INTFLAG Position) Transmit Underrun x */
    264. 

  264. #define I2S_INTFLAG_TXUR_Msk                  (_U_(0x3) << I2S_INTFLAG_TXUR_Pos)                   /**< (I2S_INTFLAG Mask) TXUR */
    265. 

  265. #define I2S_INTFLAG_TXUR(value)               (I2S_INTFLAG_TXUR_Msk & ((value) << I2S_INTFLAG_TXUR_Pos)) 
    266. 

  266. 

  267. /* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) ( R/ 16) Synchronization Status -------- */
    268. 

  268. #define I2S_SYNCBUSY_RESETVALUE               _U_(0x00)                                            /**<  (I2S_SYNCBUSY) Synchronization Status  Reset Value */
    269. 

  269. 

  270. #define I2S_SYNCBUSY_SWRST_Pos                _U_(0)                                               /**< (I2S_SYNCBUSY) Software Reset Synchronization Status Position */
    271. 

  271. #define I2S_SYNCBUSY_SWRST_Msk                (_U_(0x1) << I2S_SYNCBUSY_SWRST_Pos)                 /**< (I2S_SYNCBUSY) Software Reset Synchronization Status Mask */
    272. 

  272. #define I2S_SYNCBUSY_SWRST(value)             (I2S_SYNCBUSY_SWRST_Msk & ((value) << I2S_SYNCBUSY_SWRST_Pos))
    273. 

  273. #define I2S_SYNCBUSY_ENABLE_Pos               _U_(1)                                               /**< (I2S_SYNCBUSY) Enable Synchronization Status Position */
    274. 

  274. #define I2S_SYNCBUSY_ENABLE_Msk               (_U_(0x1) << I2S_SYNCBUSY_ENABLE_Pos)                /**< (I2S_SYNCBUSY) Enable Synchronization Status Mask */
    275. 

  275. #define I2S_SYNCBUSY_ENABLE(value)            (I2S_SYNCBUSY_ENABLE_Msk & ((value) << I2S_SYNCBUSY_ENABLE_Pos))
    276. 

  276. #define I2S_SYNCBUSY_CKEN0_Pos                _U_(2)                                               /**< (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status Position */
    277. 

  277. #define I2S_SYNCBUSY_CKEN0_Msk                (_U_(0x1) << I2S_SYNCBUSY_CKEN0_Pos)                 /**< (I2S_SYNCBUSY) Clock Unit 0 Enable Synchronization Status Mask */
    278. 

  278. #define I2S_SYNCBUSY_CKEN0(value)             (I2S_SYNCBUSY_CKEN0_Msk & ((value) << I2S_SYNCBUSY_CKEN0_Pos))
    279. 

  279. #define I2S_SYNCBUSY_CKEN1_Pos                _U_(3)                                               /**< (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status Position */
    280. 

  280. #define I2S_SYNCBUSY_CKEN1_Msk                (_U_(0x1) << I2S_SYNCBUSY_CKEN1_Pos)                 /**< (I2S_SYNCBUSY) Clock Unit 1 Enable Synchronization Status Mask */
    281. 

  281. #define I2S_SYNCBUSY_CKEN1(value)             (I2S_SYNCBUSY_CKEN1_Msk & ((value) << I2S_SYNCBUSY_CKEN1_Pos))
    282. 

  282. #define I2S_SYNCBUSY_SEREN0_Pos               _U_(4)                                               /**< (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status Position */
    283. 

  283. #define I2S_SYNCBUSY_SEREN0_Msk               (_U_(0x1) << I2S_SYNCBUSY_SEREN0_Pos)                /**< (I2S_SYNCBUSY) Serializer 0 Enable Synchronization Status Mask */
    284. 

  284. #define I2S_SYNCBUSY_SEREN0(value)            (I2S_SYNCBUSY_SEREN0_Msk & ((value) << I2S_SYNCBUSY_SEREN0_Pos))
    285. 

  285. #define I2S_SYNCBUSY_SEREN1_Pos               _U_(5)                                               /**< (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status Position */
    286. 

  286. #define I2S_SYNCBUSY_SEREN1_Msk               (_U_(0x1) << I2S_SYNCBUSY_SEREN1_Pos)                /**< (I2S_SYNCBUSY) Serializer 1 Enable Synchronization Status Mask */
    287. 

  287. #define I2S_SYNCBUSY_SEREN1(value)            (I2S_SYNCBUSY_SEREN1_Msk & ((value) << I2S_SYNCBUSY_SEREN1_Pos))
    288. 

  288. #define I2S_SYNCBUSY_DATA0_Pos                _U_(8)                                               /**< (I2S_SYNCBUSY) Data 0 Synchronization Status Position */
    289. 

  289. #define I2S_SYNCBUSY_DATA0_Msk                (_U_(0x1) << I2S_SYNCBUSY_DATA0_Pos)                 /**< (I2S_SYNCBUSY) Data 0 Synchronization Status Mask */
    290. 

  290. #define I2S_SYNCBUSY_DATA0(value)             (I2S_SYNCBUSY_DATA0_Msk & ((value) << I2S_SYNCBUSY_DATA0_Pos))
    291. 

  291. #define I2S_SYNCBUSY_DATA1_Pos                _U_(9)                                               /**< (I2S_SYNCBUSY) Data 1 Synchronization Status Position */
    292. 

  292. #define I2S_SYNCBUSY_DATA1_Msk                (_U_(0x1) << I2S_SYNCBUSY_DATA1_Pos)                 /**< (I2S_SYNCBUSY) Data 1 Synchronization Status Mask */
    293. 

  293. #define I2S_SYNCBUSY_DATA1(value)             (I2S_SYNCBUSY_DATA1_Msk & ((value) << I2S_SYNCBUSY_DATA1_Pos))
    294. 

  294. #define I2S_SYNCBUSY_Msk                      _U_(0x033F)                                          /**< (I2S_SYNCBUSY) Register Mask  */
    295. 

  295. 

  296. #define I2S_SYNCBUSY_CKEN_Pos                 _U_(2)                                               /**< (I2S_SYNCBUSY Position) Clock Unit x Enable Synchronization Status */
    297. 

  297. #define I2S_SYNCBUSY_CKEN_Msk                 (_U_(0x3) << I2S_SYNCBUSY_CKEN_Pos)                  /**< (I2S_SYNCBUSY Mask) CKEN */
    298. 

  298. #define I2S_SYNCBUSY_CKEN(value)              (I2S_SYNCBUSY_CKEN_Msk & ((value) << I2S_SYNCBUSY_CKEN_Pos)) 
    299. 

  299. #define I2S_SYNCBUSY_SEREN_Pos                _U_(4)                                               /**< (I2S_SYNCBUSY Position) Serializer x Enable Synchronization Status */
    300. 

  300. #define I2S_SYNCBUSY_SEREN_Msk                (_U_(0x3) << I2S_SYNCBUSY_SEREN_Pos)                 /**< (I2S_SYNCBUSY Mask) SEREN */
    301. 

  301. #define I2S_SYNCBUSY_SEREN(value)             (I2S_SYNCBUSY_SEREN_Msk & ((value) << I2S_SYNCBUSY_SEREN_Pos)) 
    302. 

  302. #define I2S_SYNCBUSY_DATA_Pos                 _U_(8)                                               /**< (I2S_SYNCBUSY Position) Data x Synchronization Status */
    303. 

  303. #define I2S_SYNCBUSY_DATA_Msk                 (_U_(0x3) << I2S_SYNCBUSY_DATA_Pos)                  /**< (I2S_SYNCBUSY Mask) DATA */
    304. 

  304. #define I2S_SYNCBUSY_DATA(value)              (I2S_SYNCBUSY_DATA_Msk & ((value) << I2S_SYNCBUSY_DATA_Pos)) 
    305. 

  305. 

  306. /* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
    307. 

  307. #define I2S_SERCTRL_RESETVALUE                _U_(0x00)                                            /**<  (I2S_SERCTRL) Serializer n Control  Reset Value */
    308. 

  308. 

  309. #define I2S_SERCTRL_SERMODE_Pos               _U_(0)                                               /**< (I2S_SERCTRL) Serializer Mode Position */
    310. 

  310. #define I2S_SERCTRL_SERMODE_Msk               (_U_(0x3) << I2S_SERCTRL_SERMODE_Pos)                /**< (I2S_SERCTRL) Serializer Mode Mask */
    311. 

  311. #define I2S_SERCTRL_SERMODE(value)            (I2S_SERCTRL_SERMODE_Msk & ((value) << I2S_SERCTRL_SERMODE_Pos))
    312. 

  312. #define   I2S_SERCTRL_SERMODE_RX_Val          _U_(0x0)                                             /**< (I2S_SERCTRL) Receive  */
    313. 

  313. #define   I2S_SERCTRL_SERMODE_TX_Val          _U_(0x1)                                             /**< (I2S_SERCTRL) Transmit  */
    314. 

  314. #define   I2S_SERCTRL_SERMODE_PDM2_Val        _U_(0x2)                                             /**< (I2S_SERCTRL) Receive one PDM data on each serial clock edge  */
    315. 

  315. #define I2S_SERCTRL_SERMODE_RX                (I2S_SERCTRL_SERMODE_RX_Val << I2S_SERCTRL_SERMODE_Pos) /**< (I2S_SERCTRL) Receive Position  */
    316. 

  316. #define I2S_SERCTRL_SERMODE_TX                (I2S_SERCTRL_SERMODE_TX_Val << I2S_SERCTRL_SERMODE_Pos) /**< (I2S_SERCTRL) Transmit Position  */
    317. 

  317. #define I2S_SERCTRL_SERMODE_PDM2              (I2S_SERCTRL_SERMODE_PDM2_Val << I2S_SERCTRL_SERMODE_Pos) /**< (I2S_SERCTRL) Receive one PDM data on each serial clock edge Position  */
    318. 

  318. #define I2S_SERCTRL_TXDEFAULT_Pos             _U_(2)                                               /**< (I2S_SERCTRL) Line Default Line when Slot Disabled Position */
    319. 

  319. #define I2S_SERCTRL_TXDEFAULT_Msk             (_U_(0x3) << I2S_SERCTRL_TXDEFAULT_Pos)              /**< (I2S_SERCTRL) Line Default Line when Slot Disabled Mask */
    320. 

  320. #define I2S_SERCTRL_TXDEFAULT(value)          (I2S_SERCTRL_TXDEFAULT_Msk & ((value) << I2S_SERCTRL_TXDEFAULT_Pos))
    321. 

  321. #define   I2S_SERCTRL_TXDEFAULT_ZERO_Val      _U_(0x0)                                             /**< (I2S_SERCTRL) Output Default Value is 0  */
    322. 

  322. #define   I2S_SERCTRL_TXDEFAULT_ONE_Val       _U_(0x1)                                             /**< (I2S_SERCTRL) Output Default Value is 1  */
    323. 

  323. #define   I2S_SERCTRL_TXDEFAULT_HIZ_Val       _U_(0x3)                                             /**< (I2S_SERCTRL) Output Default Value is high impedance  */
    324. 

  324. #define I2S_SERCTRL_TXDEFAULT_ZERO            (I2S_SERCTRL_TXDEFAULT_ZERO_Val << I2S_SERCTRL_TXDEFAULT_Pos) /**< (I2S_SERCTRL) Output Default Value is 0 Position  */
    325. 

  325. #define I2S_SERCTRL_TXDEFAULT_ONE             (I2S_SERCTRL_TXDEFAULT_ONE_Val << I2S_SERCTRL_TXDEFAULT_Pos) /**< (I2S_SERCTRL) Output Default Value is 1 Position  */
    326. 

  326. #define I2S_SERCTRL_TXDEFAULT_HIZ             (I2S_SERCTRL_TXDEFAULT_HIZ_Val << I2S_SERCTRL_TXDEFAULT_Pos) /**< (I2S_SERCTRL) Output Default Value is high impedance Position  */
    327. 

  327. #define I2S_SERCTRL_TXSAME_Pos                _U_(4)                                               /**< (I2S_SERCTRL) Transmit Data when Underrun Position */
    328. 

  328. #define I2S_SERCTRL_TXSAME_Msk                (_U_(0x1) << I2S_SERCTRL_TXSAME_Pos)                 /**< (I2S_SERCTRL) Transmit Data when Underrun Mask */
    329. 

  329. #define I2S_SERCTRL_TXSAME(value)             (I2S_SERCTRL_TXSAME_Msk & ((value) << I2S_SERCTRL_TXSAME_Pos))
    330. 

  330. #define   I2S_SERCTRL_TXSAME_ZERO_Val         _U_(0x0)                                             /**< (I2S_SERCTRL) Zero data transmitted in case of underrun  */
    331. 

  331. #define   I2S_SERCTRL_TXSAME_SAME_Val         _U_(0x1)                                             /**< (I2S_SERCTRL) Last data transmitted in case of underrun  */
    332. 

  332. #define I2S_SERCTRL_TXSAME_ZERO               (I2S_SERCTRL_TXSAME_ZERO_Val << I2S_SERCTRL_TXSAME_Pos) /**< (I2S_SERCTRL) Zero data transmitted in case of underrun Position  */
    333. 

  333. #define I2S_SERCTRL_TXSAME_SAME               (I2S_SERCTRL_TXSAME_SAME_Val << I2S_SERCTRL_TXSAME_Pos) /**< (I2S_SERCTRL) Last data transmitted in case of underrun Position  */
    334. 

  334. #define I2S_SERCTRL_CLKSEL_Pos                _U_(5)                                               /**< (I2S_SERCTRL) Clock Unit Selection Position */
    335. 

  335. #define I2S_SERCTRL_CLKSEL_Msk                (_U_(0x1) << I2S_SERCTRL_CLKSEL_Pos)                 /**< (I2S_SERCTRL) Clock Unit Selection Mask */
    336. 

  336. #define I2S_SERCTRL_CLKSEL(value)             (I2S_SERCTRL_CLKSEL_Msk & ((value) << I2S_SERCTRL_CLKSEL_Pos))
    337. 

  337. #define   I2S_SERCTRL_CLKSEL_CLK0_Val         _U_(0x0)                                             /**< (I2S_SERCTRL) Use Clock Unit 0  */
    338. 

  338. #define   I2S_SERCTRL_CLKSEL_CLK1_Val         _U_(0x1)                                             /**< (I2S_SERCTRL) Use Clock Unit 1  */
    339. 

  339. #define I2S_SERCTRL_CLKSEL_CLK0               (I2S_SERCTRL_CLKSEL_CLK0_Val << I2S_SERCTRL_CLKSEL_Pos) /**< (I2S_SERCTRL) Use Clock Unit 0 Position  */
    340. 

  340. #define I2S_SERCTRL_CLKSEL_CLK1               (I2S_SERCTRL_CLKSEL_CLK1_Val << I2S_SERCTRL_CLKSEL_Pos) /**< (I2S_SERCTRL) Use Clock Unit 1 Position  */
    341. 

  341. #define I2S_SERCTRL_SLOTADJ_Pos               _U_(7)                                               /**< (I2S_SERCTRL) Data Slot Formatting Adjust Position */
    342. 

  342. #define I2S_SERCTRL_SLOTADJ_Msk               (_U_(0x1) << I2S_SERCTRL_SLOTADJ_Pos)                /**< (I2S_SERCTRL) Data Slot Formatting Adjust Mask */
    343. 

  343. #define I2S_SERCTRL_SLOTADJ(value)            (I2S_SERCTRL_SLOTADJ_Msk & ((value) << I2S_SERCTRL_SLOTADJ_Pos))
    344. 

  344. #define   I2S_SERCTRL_SLOTADJ_RIGHT_Val       _U_(0x0)                                             /**< (I2S_SERCTRL) Data is right adjusted in slot  */
    345. 

  345. #define   I2S_SERCTRL_SLOTADJ_LEFT_Val        _U_(0x1)                                             /**< (I2S_SERCTRL) Data is left adjusted in slot  */
    346. 

  346. #define I2S_SERCTRL_SLOTADJ_RIGHT             (I2S_SERCTRL_SLOTADJ_RIGHT_Val << I2S_SERCTRL_SLOTADJ_Pos) /**< (I2S_SERCTRL) Data is right adjusted in slot Position  */
    347. 

  347. #define I2S_SERCTRL_SLOTADJ_LEFT              (I2S_SERCTRL_SLOTADJ_LEFT_Val << I2S_SERCTRL_SLOTADJ_Pos) /**< (I2S_SERCTRL) Data is left adjusted in slot Position  */
    348. 

  348. #define I2S_SERCTRL_DATASIZE_Pos              _U_(8)                                               /**< (I2S_SERCTRL) Data Word Size Position */
    349. 

  349. #define I2S_SERCTRL_DATASIZE_Msk              (_U_(0x7) << I2S_SERCTRL_DATASIZE_Pos)               /**< (I2S_SERCTRL) Data Word Size Mask */
    350. 

  350. #define I2S_SERCTRL_DATASIZE(value)           (I2S_SERCTRL_DATASIZE_Msk & ((value) << I2S_SERCTRL_DATASIZE_Pos))
    351. 

  351. #define   I2S_SERCTRL_DATASIZE_32_Val         _U_(0x0)                                             /**< (I2S_SERCTRL) 32 bits  */
    352. 

  352. #define   I2S_SERCTRL_DATASIZE_24_Val         _U_(0x1)                                             /**< (I2S_SERCTRL) 24 bits  */
    353. 

  353. #define   I2S_SERCTRL_DATASIZE_20_Val         _U_(0x2)                                             /**< (I2S_SERCTRL) 20 bits  */
    354. 

  354. #define   I2S_SERCTRL_DATASIZE_18_Val         _U_(0x3)                                             /**< (I2S_SERCTRL) 18 bits  */
    355. 

  355. #define   I2S_SERCTRL_DATASIZE_16_Val         _U_(0x4)                                             /**< (I2S_SERCTRL) 16 bits  */
    356. 

  356. #define   I2S_SERCTRL_DATASIZE_16C_Val        _U_(0x5)                                             /**< (I2S_SERCTRL) 16 bits compact stereo  */
    357. 

  357. #define   I2S_SERCTRL_DATASIZE_8_Val          _U_(0x6)                                             /**< (I2S_SERCTRL) 8 bits  */
    358. 

  358. #define   I2S_SERCTRL_DATASIZE_8C_Val         _U_(0x7)                                             /**< (I2S_SERCTRL) 8 bits compact stereo  */
    359. 

  359. #define I2S_SERCTRL_DATASIZE_32               (I2S_SERCTRL_DATASIZE_32_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 32 bits Position  */
    360. 

  360. #define I2S_SERCTRL_DATASIZE_24               (I2S_SERCTRL_DATASIZE_24_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 24 bits Position  */
    361. 

  361. #define I2S_SERCTRL_DATASIZE_20               (I2S_SERCTRL_DATASIZE_20_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 20 bits Position  */
    362. 

  362. #define I2S_SERCTRL_DATASIZE_18               (I2S_SERCTRL_DATASIZE_18_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 18 bits Position  */
    363. 

  363. #define I2S_SERCTRL_DATASIZE_16               (I2S_SERCTRL_DATASIZE_16_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 16 bits Position  */
    364. 

  364. #define I2S_SERCTRL_DATASIZE_16C              (I2S_SERCTRL_DATASIZE_16C_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 16 bits compact stereo Position  */
    365. 

  365. #define I2S_SERCTRL_DATASIZE_8                (I2S_SERCTRL_DATASIZE_8_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 8 bits Position  */
    366. 

  366. #define I2S_SERCTRL_DATASIZE_8C               (I2S_SERCTRL_DATASIZE_8C_Val << I2S_SERCTRL_DATASIZE_Pos) /**< (I2S_SERCTRL) 8 bits compact stereo Position  */
    367. 

  367. #define I2S_SERCTRL_WORDADJ_Pos               _U_(12)                                              /**< (I2S_SERCTRL) Data Word Formatting Adjust Position */
    368. 

  368. #define I2S_SERCTRL_WORDADJ_Msk               (_U_(0x1) << I2S_SERCTRL_WORDADJ_Pos)                /**< (I2S_SERCTRL) Data Word Formatting Adjust Mask */
    369. 

  369. #define I2S_SERCTRL_WORDADJ(value)            (I2S_SERCTRL_WORDADJ_Msk & ((value) << I2S_SERCTRL_WORDADJ_Pos))
    370. 

  370. #define   I2S_SERCTRL_WORDADJ_RIGHT_Val       _U_(0x0)                                             /**< (I2S_SERCTRL) Data is right adjusted in word  */
    371. 

  371. #define   I2S_SERCTRL_WORDADJ_LEFT_Val        _U_(0x1)                                             /**< (I2S_SERCTRL) Data is left adjusted in word  */
    372. 

  372. #define I2S_SERCTRL_WORDADJ_RIGHT             (I2S_SERCTRL_WORDADJ_RIGHT_Val << I2S_SERCTRL_WORDADJ_Pos) /**< (I2S_SERCTRL) Data is right adjusted in word Position  */
    373. 

  373. #define I2S_SERCTRL_WORDADJ_LEFT              (I2S_SERCTRL_WORDADJ_LEFT_Val << I2S_SERCTRL_WORDADJ_Pos) /**< (I2S_SERCTRL) Data is left adjusted in word Position  */
    374. 

  374. #define I2S_SERCTRL_EXTEND_Pos                _U_(13)                                              /**< (I2S_SERCTRL) Data Formatting Bit Extension Position */
    375. 

  375. #define I2S_SERCTRL_EXTEND_Msk                (_U_(0x3) << I2S_SERCTRL_EXTEND_Pos)                 /**< (I2S_SERCTRL) Data Formatting Bit Extension Mask */
    376. 

  376. #define I2S_SERCTRL_EXTEND(value)             (I2S_SERCTRL_EXTEND_Msk & ((value) << I2S_SERCTRL_EXTEND_Pos))
    377. 

  377. #define   I2S_SERCTRL_EXTEND_ZERO_Val         _U_(0x0)                                             /**< (I2S_SERCTRL) Extend with zeroes  */
    378. 

  378. #define   I2S_SERCTRL_EXTEND_ONE_Val          _U_(0x1)                                             /**< (I2S_SERCTRL) Extend with ones  */
    379. 

  379. #define   I2S_SERCTRL_EXTEND_MSBIT_Val        _U_(0x2)                                             /**< (I2S_SERCTRL) Extend with Most Significant Bit  */
    380. 

  380. #define   I2S_SERCTRL_EXTEND_LSBIT_Val        _U_(0x3)                                             /**< (I2S_SERCTRL) Extend with Least Significant Bit  */
    381. 

  381. #define I2S_SERCTRL_EXTEND_ZERO               (I2S_SERCTRL_EXTEND_ZERO_Val << I2S_SERCTRL_EXTEND_Pos) /**< (I2S_SERCTRL) Extend with zeroes Position  */
    382. 

  382. #define I2S_SERCTRL_EXTEND_ONE                (I2S_SERCTRL_EXTEND_ONE_Val << I2S_SERCTRL_EXTEND_Pos) /**< (I2S_SERCTRL) Extend with ones Position  */
    383. 

  383. #define I2S_SERCTRL_EXTEND_MSBIT              (I2S_SERCTRL_EXTEND_MSBIT_Val << I2S_SERCTRL_EXTEND_Pos) /**< (I2S_SERCTRL) Extend with Most Significant Bit Position  */
    384. 

  384. #define I2S_SERCTRL_EXTEND_LSBIT              (I2S_SERCTRL_EXTEND_LSBIT_Val << I2S_SERCTRL_EXTEND_Pos) /**< (I2S_SERCTRL) Extend with Least Significant Bit Position  */
    385. 

  385. #define I2S_SERCTRL_BITREV_Pos                _U_(15)                                              /**< (I2S_SERCTRL) Data Formatting Bit Reverse Position */
    386. 

  386. #define I2S_SERCTRL_BITREV_Msk                (_U_(0x1) << I2S_SERCTRL_BITREV_Pos)                 /**< (I2S_SERCTRL) Data Formatting Bit Reverse Mask */
    387. 

  387. #define I2S_SERCTRL_BITREV(value)             (I2S_SERCTRL_BITREV_Msk & ((value) << I2S_SERCTRL_BITREV_Pos))
    388. 

  388. #define   I2S_SERCTRL_BITREV_MSBIT_Val        _U_(0x0)                                             /**< (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)  */
    389. 

  389. #define   I2S_SERCTRL_BITREV_LSBIT_Val        _U_(0x1)                                             /**< (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first  */
    390. 

  390. #define I2S_SERCTRL_BITREV_MSBIT              (I2S_SERCTRL_BITREV_MSBIT_Val << I2S_SERCTRL_BITREV_Pos) /**< (I2S_SERCTRL) Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) Position  */
    391. 

  391. #define I2S_SERCTRL_BITREV_LSBIT              (I2S_SERCTRL_BITREV_LSBIT_Val << I2S_SERCTRL_BITREV_Pos) /**< (I2S_SERCTRL) Transfer Data Least Significant Bit (LSB) first Position  */
    392. 

  392. #define I2S_SERCTRL_SLOTDIS0_Pos              _U_(16)                                              /**< (I2S_SERCTRL) Slot 0 Disabled for this Serializer Position */
    393. 

  393. #define I2S_SERCTRL_SLOTDIS0_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS0_Pos)               /**< (I2S_SERCTRL) Slot 0 Disabled for this Serializer Mask */
    394. 

  394. #define I2S_SERCTRL_SLOTDIS0(value)           (I2S_SERCTRL_SLOTDIS0_Msk & ((value) << I2S_SERCTRL_SLOTDIS0_Pos))
    395. 

  395. #define I2S_SERCTRL_SLOTDIS1_Pos              _U_(17)                                              /**< (I2S_SERCTRL) Slot 1 Disabled for this Serializer Position */
    396. 

  396. #define I2S_SERCTRL_SLOTDIS1_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS1_Pos)               /**< (I2S_SERCTRL) Slot 1 Disabled for this Serializer Mask */
    397. 

  397. #define I2S_SERCTRL_SLOTDIS1(value)           (I2S_SERCTRL_SLOTDIS1_Msk & ((value) << I2S_SERCTRL_SLOTDIS1_Pos))
    398. 

  398. #define I2S_SERCTRL_SLOTDIS2_Pos              _U_(18)                                              /**< (I2S_SERCTRL) Slot 2 Disabled for this Serializer Position */
    399. 

  399. #define I2S_SERCTRL_SLOTDIS2_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS2_Pos)               /**< (I2S_SERCTRL) Slot 2 Disabled for this Serializer Mask */
    400. 

  400. #define I2S_SERCTRL_SLOTDIS2(value)           (I2S_SERCTRL_SLOTDIS2_Msk & ((value) << I2S_SERCTRL_SLOTDIS2_Pos))
    401. 

  401. #define I2S_SERCTRL_SLOTDIS3_Pos              _U_(19)                                              /**< (I2S_SERCTRL) Slot 3 Disabled for this Serializer Position */
    402. 

  402. #define I2S_SERCTRL_SLOTDIS3_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS3_Pos)               /**< (I2S_SERCTRL) Slot 3 Disabled for this Serializer Mask */
    403. 

  403. #define I2S_SERCTRL_SLOTDIS3(value)           (I2S_SERCTRL_SLOTDIS3_Msk & ((value) << I2S_SERCTRL_SLOTDIS3_Pos))
    404. 

  404. #define I2S_SERCTRL_SLOTDIS4_Pos              _U_(20)                                              /**< (I2S_SERCTRL) Slot 4 Disabled for this Serializer Position */
    405. 

  405. #define I2S_SERCTRL_SLOTDIS4_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS4_Pos)               /**< (I2S_SERCTRL) Slot 4 Disabled for this Serializer Mask */
    406. 

  406. #define I2S_SERCTRL_SLOTDIS4(value)           (I2S_SERCTRL_SLOTDIS4_Msk & ((value) << I2S_SERCTRL_SLOTDIS4_Pos))
    407. 

  407. #define I2S_SERCTRL_SLOTDIS5_Pos              _U_(21)                                              /**< (I2S_SERCTRL) Slot 5 Disabled for this Serializer Position */
    408. 

  408. #define I2S_SERCTRL_SLOTDIS5_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS5_Pos)               /**< (I2S_SERCTRL) Slot 5 Disabled for this Serializer Mask */
    409. 

  409. #define I2S_SERCTRL_SLOTDIS5(value)           (I2S_SERCTRL_SLOTDIS5_Msk & ((value) << I2S_SERCTRL_SLOTDIS5_Pos))
    410. 

  410. #define I2S_SERCTRL_SLOTDIS6_Pos              _U_(22)                                              /**< (I2S_SERCTRL) Slot 6 Disabled for this Serializer Position */
    411. 

  411. #define I2S_SERCTRL_SLOTDIS6_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS6_Pos)               /**< (I2S_SERCTRL) Slot 6 Disabled for this Serializer Mask */
    412. 

  412. #define I2S_SERCTRL_SLOTDIS6(value)           (I2S_SERCTRL_SLOTDIS6_Msk & ((value) << I2S_SERCTRL_SLOTDIS6_Pos))
    413. 

  413. #define I2S_SERCTRL_SLOTDIS7_Pos              _U_(23)                                              /**< (I2S_SERCTRL) Slot 7 Disabled for this Serializer Position */
    414. 

  414. #define I2S_SERCTRL_SLOTDIS7_Msk              (_U_(0x1) << I2S_SERCTRL_SLOTDIS7_Pos)               /**< (I2S_SERCTRL) Slot 7 Disabled for this Serializer Mask */
    415. 

  415. #define I2S_SERCTRL_SLOTDIS7(value)           (I2S_SERCTRL_SLOTDIS7_Msk & ((value) << I2S_SERCTRL_SLOTDIS7_Pos))
    416. 

  416. #define I2S_SERCTRL_MONO_Pos                  _U_(24)                                              /**< (I2S_SERCTRL) Mono Mode Position */
    417. 

  417. #define I2S_SERCTRL_MONO_Msk                  (_U_(0x1) << I2S_SERCTRL_MONO_Pos)                   /**< (I2S_SERCTRL) Mono Mode Mask */
    418. 

  418. #define I2S_SERCTRL_MONO(value)               (I2S_SERCTRL_MONO_Msk & ((value) << I2S_SERCTRL_MONO_Pos))
    419. 

  419. #define   I2S_SERCTRL_MONO_STEREO_Val         _U_(0x0)                                             /**< (I2S_SERCTRL) Normal mode  */
    420. 

  420. #define   I2S_SERCTRL_MONO_MONO_Val           _U_(0x1)                                             /**< (I2S_SERCTRL) Left channel data is duplicated to right channel  */
    421. 

  421. #define I2S_SERCTRL_MONO_STEREO               (I2S_SERCTRL_MONO_STEREO_Val << I2S_SERCTRL_MONO_Pos) /**< (I2S_SERCTRL) Normal mode Position  */
    422. 

  422. #define I2S_SERCTRL_MONO_MONO                 (I2S_SERCTRL_MONO_MONO_Val << I2S_SERCTRL_MONO_Pos)  /**< (I2S_SERCTRL) Left channel data is duplicated to right channel Position  */
    423. 

  423. #define I2S_SERCTRL_DMA_Pos                   _U_(25)                                              /**< (I2S_SERCTRL) Single or Multiple DMA Channels Position */
    424. 

  424. #define I2S_SERCTRL_DMA_Msk                   (_U_(0x1) << I2S_SERCTRL_DMA_Pos)                    /**< (I2S_SERCTRL) Single or Multiple DMA Channels Mask */
    425. 

  425. #define I2S_SERCTRL_DMA(value)                (I2S_SERCTRL_DMA_Msk & ((value) << I2S_SERCTRL_DMA_Pos))
    426. 

  426. #define   I2S_SERCTRL_DMA_SINGLE_Val          _U_(0x0)                                             /**< (I2S_SERCTRL) Single DMA channel  */
    427. 

  427. #define   I2S_SERCTRL_DMA_MULTIPLE_Val        _U_(0x1)                                             /**< (I2S_SERCTRL) One DMA channel per data channel  */
    428. 

  428. #define I2S_SERCTRL_DMA_SINGLE                (I2S_SERCTRL_DMA_SINGLE_Val << I2S_SERCTRL_DMA_Pos)  /**< (I2S_SERCTRL) Single DMA channel Position  */
    429. 

  429. #define I2S_SERCTRL_DMA_MULTIPLE              (I2S_SERCTRL_DMA_MULTIPLE_Val << I2S_SERCTRL_DMA_Pos) /**< (I2S_SERCTRL) One DMA channel per data channel Position  */
    430. 

  430. #define I2S_SERCTRL_RXLOOP_Pos                _U_(26)                                              /**< (I2S_SERCTRL) Loop-back Test Mode Position */
    431. 

  431. #define I2S_SERCTRL_RXLOOP_Msk                (_U_(0x1) << I2S_SERCTRL_RXLOOP_Pos)                 /**< (I2S_SERCTRL) Loop-back Test Mode Mask */
    432. 

  432. #define I2S_SERCTRL_RXLOOP(value)             (I2S_SERCTRL_RXLOOP_Msk & ((value) << I2S_SERCTRL_RXLOOP_Pos))
    433. 

  433. #define I2S_SERCTRL_Msk                       _U_(0x07FFF7BF)                                      /**< (I2S_SERCTRL) Register Mask  */
    434. 

  434. 

  435. #define I2S_SERCTRL_SLOTDIS_Pos               _U_(16)                                              /**< (I2S_SERCTRL Position) Slot x Disabled for this Serializer */
    436. 

  436. #define I2S_SERCTRL_SLOTDIS_Msk               (_U_(0xFF) << I2S_SERCTRL_SLOTDIS_Pos)               /**< (I2S_SERCTRL Mask) SLOTDIS */
    437. 

  437. #define I2S_SERCTRL_SLOTDIS(value)            (I2S_SERCTRL_SLOTDIS_Msk & ((value) << I2S_SERCTRL_SLOTDIS_Pos)) 
    438. 

  438. 

  439. /* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
    440. 

  440. #define I2S_DATA_RESETVALUE                   _U_(0x00)                                            /**<  (I2S_DATA) Data n  Reset Value */
    441. 

  441. 

  442. #define I2S_DATA_DATA_Pos                     _U_(0)                                               /**< (I2S_DATA) Sample Data Position */
    443. 

  443. #define I2S_DATA_DATA_Msk                     (_U_(0xFFFFFFFF) << I2S_DATA_DATA_Pos)               /**< (I2S_DATA) Sample Data Mask */
    444. 

  444. #define I2S_DATA_DATA(value)                  (I2S_DATA_DATA_Msk & ((value) << I2S_DATA_DATA_Pos))
    445. 

  445. #define I2S_DATA_Msk                          _U_(0xFFFFFFFF)                                      /**< (I2S_DATA) Register Mask  */
    446. 

  446. 

  447. 

  448. /** \brief I2S register offsets definitions */
    449. 

  449. #define I2S_CTRLA_REG_OFST             (0x00)              /**< (I2S_CTRLA) Control A Offset */
    450. 

  450. #define I2S_CLKCTRL_REG_OFST           (0x04)              /**< (I2S_CLKCTRL) Clock Unit n Control Offset */
    451. 

  451. #define I2S_CLKCTRL0_REG_OFST          (0x04)              /**< (I2S_CLKCTRL0) Clock Unit n Control Offset */
    452. 

  452. #define I2S_CLKCTRL1_REG_OFST          (0x08)              /**< (I2S_CLKCTRL1) Clock Unit n Control Offset */
    453. 

  453. #define I2S_INTENCLR_REG_OFST          (0x0C)              /**< (I2S_INTENCLR) Interrupt Enable Clear Offset */
    454. 

  454. #define I2S_INTENSET_REG_OFST          (0x10)              /**< (I2S_INTENSET) Interrupt Enable Set Offset */
    455. 

  455. #define I2S_INTFLAG_REG_OFST           (0x14)              /**< (I2S_INTFLAG) Interrupt Flag Status and Clear Offset */
    456. 

  456. #define I2S_SYNCBUSY_REG_OFST          (0x18)              /**< (I2S_SYNCBUSY) Synchronization Status Offset */
    457. 

  457. #define I2S_SERCTRL_REG_OFST           (0x20)              /**< (I2S_SERCTRL) Serializer n Control Offset */
    458. 

  458. #define I2S_SERCTRL0_REG_OFST          (0x20)              /**< (I2S_SERCTRL0) Serializer n Control Offset */
    459. 

  459. #define I2S_SERCTRL1_REG_OFST          (0x24)              /**< (I2S_SERCTRL1) Serializer n Control Offset */
    460. 

  460. #define I2S_DATA_REG_OFST              (0x30)              /**< (I2S_DATA) Data n Offset */
    461. 

  461. #define I2S_DATA0_REG_OFST             (0x30)              /**< (I2S_DATA0) Data n Offset */
    462. 

  462. #define I2S_DATA1_REG_OFST             (0x34)              /**< (I2S_DATA1) Data n Offset */
    463. 

  463. 

  464. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    465. 

  465. /** \brief I2S register API structure */
    466. 

  466. typedef struct
    467. 

  467. {  /* Inter-IC Sound Interface */
    468. 

  468.   __IO  uint8_t                        I2S_CTRLA;          /**< Offset: 0x00 (R/W  8) Control A */
    469. 

  469.   __I   uint8_t                        Reserved1[0x03];
    470. 

  470.   __IO  uint32_t                       I2S_CLKCTRL[2];     /**< Offset: 0x04 (R/W  32) Clock Unit n Control */
    471. 

  471.   __IO  uint16_t                       I2S_INTENCLR;       /**< Offset: 0x0C (R/W  16) Interrupt Enable Clear */
    472. 

  472.   __I   uint8_t                        Reserved2[0x02];
    473. 

  473.   __IO  uint16_t                       I2S_INTENSET;       /**< Offset: 0x10 (R/W  16) Interrupt Enable Set */
    474. 

  474.   __I   uint8_t                        Reserved3[0x02];
    475. 

  475.   __IO  uint16_t                       I2S_INTFLAG;        /**< Offset: 0x14 (R/W  16) Interrupt Flag Status and Clear */
    476. 

  476.   __I   uint8_t                        Reserved4[0x02];
    477. 

  477.   __I   uint16_t                       I2S_SYNCBUSY;       /**< Offset: 0x18 (R/   16) Synchronization Status */
    478. 

  478.   __I   uint8_t                        Reserved5[0x06];
    479. 

  479.   __IO  uint32_t                       I2S_SERCTRL[2];     /**< Offset: 0x20 (R/W  32) Serializer n Control */
    480. 

  480.   __I   uint8_t                        Reserved6[0x08];
    481. 

  481.   __IO  uint32_t                       I2S_DATA[2];        /**< Offset: 0x30 (R/W  32) Data n */
    482. 

  482. } i2s_registers_t;
    483. 

  483. 

  484. 

  485. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    486. 

  486. #endif /* _SAMD21_I2S_COMPONENT_H_ */
    487.