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pm.h

pm.h 45 KB
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  1. /**
    2. 

  2.  * \brief Component description for PM
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_PM_COMPONENT_H_
    25. 

  25. #define _SAMD21_PM_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR PM                                           */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
    32. 

  32. #define PM_CTRL_RESETVALUE                    _U_(0x00)                                            /**<  (PM_CTRL) Control  Reset Value */
    33. 

  33. 

  34. #define PM_CTRL_Msk                           _U_(0x00)                                            /**< (PM_CTRL) Register Mask  */
    35. 

  35. 

  36. 

  37. /* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
    38. 

  38. #define PM_SLEEP_RESETVALUE                   _U_(0x00)                                            /**<  (PM_SLEEP) Sleep Mode  Reset Value */
    39. 

  39. 

  40. #define PM_SLEEP_IDLE_Pos                     _U_(0)                                               /**< (PM_SLEEP) Idle Mode Configuration Position */
    41. 

  41. #define PM_SLEEP_IDLE_Msk                     (_U_(0x3) << PM_SLEEP_IDLE_Pos)                      /**< (PM_SLEEP) Idle Mode Configuration Mask */
    42. 

  42. #define PM_SLEEP_IDLE(value)                  (PM_SLEEP_IDLE_Msk & ((value) << PM_SLEEP_IDLE_Pos))
    43. 

  43. #define   PM_SLEEP_IDLE_CPU_Val               _U_(0x0)                                             /**< (PM_SLEEP) The CPU clock domain is stopped  */
    44. 

  44. #define   PM_SLEEP_IDLE_AHB_Val               _U_(0x1)                                             /**< (PM_SLEEP) The CPU and AHB clock domains are stopped  */
    45. 

  45. #define   PM_SLEEP_IDLE_APB_Val               _U_(0x2)                                             /**< (PM_SLEEP) The CPU, AHB and APB clock domains are stopped  */
    46. 

  46. #define PM_SLEEP_IDLE_CPU                     (PM_SLEEP_IDLE_CPU_Val << PM_SLEEP_IDLE_Pos)         /**< (PM_SLEEP) The CPU clock domain is stopped Position  */
    47. 

  47. #define PM_SLEEP_IDLE_AHB                     (PM_SLEEP_IDLE_AHB_Val << PM_SLEEP_IDLE_Pos)         /**< (PM_SLEEP) The CPU and AHB clock domains are stopped Position  */
    48. 

  48. #define PM_SLEEP_IDLE_APB                     (PM_SLEEP_IDLE_APB_Val << PM_SLEEP_IDLE_Pos)         /**< (PM_SLEEP) The CPU, AHB and APB clock domains are stopped Position  */
    49. 

  49. #define PM_SLEEP_Msk                          _U_(0x03)                                            /**< (PM_SLEEP) Register Mask  */
    50. 

  50. 

  51. 

  52. /* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
    53. 

  53. #define PM_CPUSEL_RESETVALUE                  _U_(0x00)                                            /**<  (PM_CPUSEL) CPU Clock Select  Reset Value */
    54. 

  54. 

  55. #define PM_CPUSEL_CPUDIV_Pos                  _U_(0)                                               /**< (PM_CPUSEL) CPU Prescaler Selection Position */
    56. 

  56. #define PM_CPUSEL_CPUDIV_Msk                  (_U_(0x7) << PM_CPUSEL_CPUDIV_Pos)                   /**< (PM_CPUSEL) CPU Prescaler Selection Mask */
    57. 

  57. #define PM_CPUSEL_CPUDIV(value)               (PM_CPUSEL_CPUDIV_Msk & ((value) << PM_CPUSEL_CPUDIV_Pos))
    58. 

  58. #define   PM_CPUSEL_CPUDIV_DIV1_Val           _U_(0x0)                                             /**< (PM_CPUSEL) Divide by 1  */
    59. 

  59. #define   PM_CPUSEL_CPUDIV_DIV2_Val           _U_(0x1)                                             /**< (PM_CPUSEL) Divide by 2  */
    60. 

  60. #define   PM_CPUSEL_CPUDIV_DIV4_Val           _U_(0x2)                                             /**< (PM_CPUSEL) Divide by 4  */
    61. 

  61. #define   PM_CPUSEL_CPUDIV_DIV8_Val           _U_(0x3)                                             /**< (PM_CPUSEL) Divide by 8  */
    62. 

  62. #define   PM_CPUSEL_CPUDIV_DIV16_Val          _U_(0x4)                                             /**< (PM_CPUSEL) Divide by 16  */
    63. 

  63. #define   PM_CPUSEL_CPUDIV_DIV32_Val          _U_(0x5)                                             /**< (PM_CPUSEL) Divide by 32  */
    64. 

  64. #define   PM_CPUSEL_CPUDIV_DIV64_Val          _U_(0x6)                                             /**< (PM_CPUSEL) Divide by 64  */
    65. 

  65. #define   PM_CPUSEL_CPUDIV_DIV128_Val         _U_(0x7)                                             /**< (PM_CPUSEL) Divide by 128  */
    66. 

  66. #define PM_CPUSEL_CPUDIV_DIV1                 (PM_CPUSEL_CPUDIV_DIV1_Val << PM_CPUSEL_CPUDIV_Pos)  /**< (PM_CPUSEL) Divide by 1 Position  */
    67. 

  67. #define PM_CPUSEL_CPUDIV_DIV2                 (PM_CPUSEL_CPUDIV_DIV2_Val << PM_CPUSEL_CPUDIV_Pos)  /**< (PM_CPUSEL) Divide by 2 Position  */
    68. 

  68. #define PM_CPUSEL_CPUDIV_DIV4                 (PM_CPUSEL_CPUDIV_DIV4_Val << PM_CPUSEL_CPUDIV_Pos)  /**< (PM_CPUSEL) Divide by 4 Position  */
    69. 

  69. #define PM_CPUSEL_CPUDIV_DIV8                 (PM_CPUSEL_CPUDIV_DIV8_Val << PM_CPUSEL_CPUDIV_Pos)  /**< (PM_CPUSEL) Divide by 8 Position  */
    70. 

  70. #define PM_CPUSEL_CPUDIV_DIV16                (PM_CPUSEL_CPUDIV_DIV16_Val << PM_CPUSEL_CPUDIV_Pos) /**< (PM_CPUSEL) Divide by 16 Position  */
    71. 

  71. #define PM_CPUSEL_CPUDIV_DIV32                (PM_CPUSEL_CPUDIV_DIV32_Val << PM_CPUSEL_CPUDIV_Pos) /**< (PM_CPUSEL) Divide by 32 Position  */
    72. 

  72. #define PM_CPUSEL_CPUDIV_DIV64                (PM_CPUSEL_CPUDIV_DIV64_Val << PM_CPUSEL_CPUDIV_Pos) /**< (PM_CPUSEL) Divide by 64 Position  */
    73. 

  73. #define PM_CPUSEL_CPUDIV_DIV128               (PM_CPUSEL_CPUDIV_DIV128_Val << PM_CPUSEL_CPUDIV_Pos) /**< (PM_CPUSEL) Divide by 128 Position  */
    74. 

  74. #define PM_CPUSEL_Msk                         _U_(0x07)                                            /**< (PM_CPUSEL) Register Mask  */
    75. 

  75. 

  76. 

  77. /* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
    78. 

  78. #define PM_APBASEL_RESETVALUE                 _U_(0x00)                                            /**<  (PM_APBASEL) APBA Clock Select  Reset Value */
    79. 

  79. 

  80. #define PM_APBASEL_APBADIV_Pos                _U_(0)                                               /**< (PM_APBASEL) APBA Prescaler Selection Position */
    81. 

  81. #define PM_APBASEL_APBADIV_Msk                (_U_(0x7) << PM_APBASEL_APBADIV_Pos)                 /**< (PM_APBASEL) APBA Prescaler Selection Mask */
    82. 

  82. #define PM_APBASEL_APBADIV(value)             (PM_APBASEL_APBADIV_Msk & ((value) << PM_APBASEL_APBADIV_Pos))
    83. 

  83. #define   PM_APBASEL_APBADIV_DIV1_Val         _U_(0x0)                                             /**< (PM_APBASEL) Divide by 1  */
    84. 

  84. #define   PM_APBASEL_APBADIV_DIV2_Val         _U_(0x1)                                             /**< (PM_APBASEL) Divide by 2  */
    85. 

  85. #define   PM_APBASEL_APBADIV_DIV4_Val         _U_(0x2)                                             /**< (PM_APBASEL) Divide by 4  */
    86. 

  86. #define   PM_APBASEL_APBADIV_DIV8_Val         _U_(0x3)                                             /**< (PM_APBASEL) Divide by 8  */
    87. 

  87. #define   PM_APBASEL_APBADIV_DIV16_Val        _U_(0x4)                                             /**< (PM_APBASEL) Divide by 16  */
    88. 

  88. #define   PM_APBASEL_APBADIV_DIV32_Val        _U_(0x5)                                             /**< (PM_APBASEL) Divide by 32  */
    89. 

  89. #define   PM_APBASEL_APBADIV_DIV64_Val        _U_(0x6)                                             /**< (PM_APBASEL) Divide by 64  */
    90. 

  90. #define   PM_APBASEL_APBADIV_DIV128_Val       _U_(0x7)                                             /**< (PM_APBASEL) Divide by 128  */
    91. 

  91. #define PM_APBASEL_APBADIV_DIV1               (PM_APBASEL_APBADIV_DIV1_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 1 Position  */
    92. 

  92. #define PM_APBASEL_APBADIV_DIV2               (PM_APBASEL_APBADIV_DIV2_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 2 Position  */
    93. 

  93. #define PM_APBASEL_APBADIV_DIV4               (PM_APBASEL_APBADIV_DIV4_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 4 Position  */
    94. 

  94. #define PM_APBASEL_APBADIV_DIV8               (PM_APBASEL_APBADIV_DIV8_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 8 Position  */
    95. 

  95. #define PM_APBASEL_APBADIV_DIV16              (PM_APBASEL_APBADIV_DIV16_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 16 Position  */
    96. 

  96. #define PM_APBASEL_APBADIV_DIV32              (PM_APBASEL_APBADIV_DIV32_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 32 Position  */
    97. 

  97. #define PM_APBASEL_APBADIV_DIV64              (PM_APBASEL_APBADIV_DIV64_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 64 Position  */
    98. 

  98. #define PM_APBASEL_APBADIV_DIV128             (PM_APBASEL_APBADIV_DIV128_Val << PM_APBASEL_APBADIV_Pos) /**< (PM_APBASEL) Divide by 128 Position  */
    99. 

  99. #define PM_APBASEL_Msk                        _U_(0x07)                                            /**< (PM_APBASEL) Register Mask  */
    100. 

  100. 

  101. 

  102. /* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
    103. 

  103. #define PM_APBBSEL_RESETVALUE                 _U_(0x00)                                            /**<  (PM_APBBSEL) APBB Clock Select  Reset Value */
    104. 

  104. 

  105. #define PM_APBBSEL_APBBDIV_Pos                _U_(0)                                               /**< (PM_APBBSEL) APBB Prescaler Selection Position */
    106. 

  106. #define PM_APBBSEL_APBBDIV_Msk                (_U_(0x7) << PM_APBBSEL_APBBDIV_Pos)                 /**< (PM_APBBSEL) APBB Prescaler Selection Mask */
    107. 

  107. #define PM_APBBSEL_APBBDIV(value)             (PM_APBBSEL_APBBDIV_Msk & ((value) << PM_APBBSEL_APBBDIV_Pos))
    108. 

  108. #define   PM_APBBSEL_APBBDIV_DIV1_Val         _U_(0x0)                                             /**< (PM_APBBSEL) Divide by 1  */
    109. 

  109. #define   PM_APBBSEL_APBBDIV_DIV2_Val         _U_(0x1)                                             /**< (PM_APBBSEL) Divide by 2  */
    110. 

  110. #define   PM_APBBSEL_APBBDIV_DIV4_Val         _U_(0x2)                                             /**< (PM_APBBSEL) Divide by 4  */
    111. 

  111. #define   PM_APBBSEL_APBBDIV_DIV8_Val         _U_(0x3)                                             /**< (PM_APBBSEL) Divide by 8  */
    112. 

  112. #define   PM_APBBSEL_APBBDIV_DIV16_Val        _U_(0x4)                                             /**< (PM_APBBSEL) Divide by 16  */
    113. 

  113. #define   PM_APBBSEL_APBBDIV_DIV32_Val        _U_(0x5)                                             /**< (PM_APBBSEL) Divide by 32  */
    114. 

  114. #define   PM_APBBSEL_APBBDIV_DIV64_Val        _U_(0x6)                                             /**< (PM_APBBSEL) Divide by 64  */
    115. 

  115. #define   PM_APBBSEL_APBBDIV_DIV128_Val       _U_(0x7)                                             /**< (PM_APBBSEL) Divide by 128  */
    116. 

  116. #define PM_APBBSEL_APBBDIV_DIV1               (PM_APBBSEL_APBBDIV_DIV1_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 1 Position  */
    117. 

  117. #define PM_APBBSEL_APBBDIV_DIV2               (PM_APBBSEL_APBBDIV_DIV2_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 2 Position  */
    118. 

  118. #define PM_APBBSEL_APBBDIV_DIV4               (PM_APBBSEL_APBBDIV_DIV4_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 4 Position  */
    119. 

  119. #define PM_APBBSEL_APBBDIV_DIV8               (PM_APBBSEL_APBBDIV_DIV8_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 8 Position  */
    120. 

  120. #define PM_APBBSEL_APBBDIV_DIV16              (PM_APBBSEL_APBBDIV_DIV16_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 16 Position  */
    121. 

  121. #define PM_APBBSEL_APBBDIV_DIV32              (PM_APBBSEL_APBBDIV_DIV32_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 32 Position  */
    122. 

  122. #define PM_APBBSEL_APBBDIV_DIV64              (PM_APBBSEL_APBBDIV_DIV64_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 64 Position  */
    123. 

  123. #define PM_APBBSEL_APBBDIV_DIV128             (PM_APBBSEL_APBBDIV_DIV128_Val << PM_APBBSEL_APBBDIV_Pos) /**< (PM_APBBSEL) Divide by 128 Position  */
    124. 

  124. #define PM_APBBSEL_Msk                        _U_(0x07)                                            /**< (PM_APBBSEL) Register Mask  */
    125. 

  125. 

  126. 

  127. /* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
    128. 

  128. #define PM_APBCSEL_RESETVALUE                 _U_(0x00)                                            /**<  (PM_APBCSEL) APBC Clock Select  Reset Value */
    129. 

  129. 

  130. #define PM_APBCSEL_APBCDIV_Pos                _U_(0)                                               /**< (PM_APBCSEL) APBC Prescaler Selection Position */
    131. 

  131. #define PM_APBCSEL_APBCDIV_Msk                (_U_(0x7) << PM_APBCSEL_APBCDIV_Pos)                 /**< (PM_APBCSEL) APBC Prescaler Selection Mask */
    132. 

  132. #define PM_APBCSEL_APBCDIV(value)             (PM_APBCSEL_APBCDIV_Msk & ((value) << PM_APBCSEL_APBCDIV_Pos))
    133. 

  133. #define   PM_APBCSEL_APBCDIV_DIV1_Val         _U_(0x0)                                             /**< (PM_APBCSEL) Divide by 1  */
    134. 

  134. #define   PM_APBCSEL_APBCDIV_DIV2_Val         _U_(0x1)                                             /**< (PM_APBCSEL) Divide by 2  */
    135. 

  135. #define   PM_APBCSEL_APBCDIV_DIV4_Val         _U_(0x2)                                             /**< (PM_APBCSEL) Divide by 4  */
    136. 

  136. #define   PM_APBCSEL_APBCDIV_DIV8_Val         _U_(0x3)                                             /**< (PM_APBCSEL) Divide by 8  */
    137. 

  137. #define   PM_APBCSEL_APBCDIV_DIV16_Val        _U_(0x4)                                             /**< (PM_APBCSEL) Divide by 16  */
    138. 

  138. #define   PM_APBCSEL_APBCDIV_DIV32_Val        _U_(0x5)                                             /**< (PM_APBCSEL) Divide by 32  */
    139. 

  139. #define   PM_APBCSEL_APBCDIV_DIV64_Val        _U_(0x6)                                             /**< (PM_APBCSEL) Divide by 64  */
    140. 

  140. #define   PM_APBCSEL_APBCDIV_DIV128_Val       _U_(0x7)                                             /**< (PM_APBCSEL) Divide by 128  */
    141. 

  141. #define PM_APBCSEL_APBCDIV_DIV1               (PM_APBCSEL_APBCDIV_DIV1_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 1 Position  */
    142. 

  142. #define PM_APBCSEL_APBCDIV_DIV2               (PM_APBCSEL_APBCDIV_DIV2_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 2 Position  */
    143. 

  143. #define PM_APBCSEL_APBCDIV_DIV4               (PM_APBCSEL_APBCDIV_DIV4_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 4 Position  */
    144. 

  144. #define PM_APBCSEL_APBCDIV_DIV8               (PM_APBCSEL_APBCDIV_DIV8_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 8 Position  */
    145. 

  145. #define PM_APBCSEL_APBCDIV_DIV16              (PM_APBCSEL_APBCDIV_DIV16_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 16 Position  */
    146. 

  146. #define PM_APBCSEL_APBCDIV_DIV32              (PM_APBCSEL_APBCDIV_DIV32_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 32 Position  */
    147. 

  147. #define PM_APBCSEL_APBCDIV_DIV64              (PM_APBCSEL_APBCDIV_DIV64_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 64 Position  */
    148. 

  148. #define PM_APBCSEL_APBCDIV_DIV128             (PM_APBCSEL_APBCDIV_DIV128_Val << PM_APBCSEL_APBCDIV_Pos) /**< (PM_APBCSEL) Divide by 128 Position  */
    149. 

  149. #define PM_APBCSEL_Msk                        _U_(0x07)                                            /**< (PM_APBCSEL) Register Mask  */
    150. 

  150. 

  151. 

  152. /* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
    153. 

  153. #define PM_AHBMASK_RESETVALUE                 _U_(0x7F)                                            /**<  (PM_AHBMASK) AHB Mask  Reset Value */
    154. 

  154. 

  155. #define PM_AHBMASK_HPB0_Pos                   _U_(0)                                               /**< (PM_AHBMASK) HPB0 AHB Clock Mask Position */
    156. 

  156. #define PM_AHBMASK_HPB0_Msk                   (_U_(0x1) << PM_AHBMASK_HPB0_Pos)                    /**< (PM_AHBMASK) HPB0 AHB Clock Mask Mask */
    157. 

  157. #define PM_AHBMASK_HPB0(value)                (PM_AHBMASK_HPB0_Msk & ((value) << PM_AHBMASK_HPB0_Pos))
    158. 

  158. #define PM_AHBMASK_HPB1_Pos                   _U_(1)                                               /**< (PM_AHBMASK) HPB1 AHB Clock Mask Position */
    159. 

  159. #define PM_AHBMASK_HPB1_Msk                   (_U_(0x1) << PM_AHBMASK_HPB1_Pos)                    /**< (PM_AHBMASK) HPB1 AHB Clock Mask Mask */
    160. 

  160. #define PM_AHBMASK_HPB1(value)                (PM_AHBMASK_HPB1_Msk & ((value) << PM_AHBMASK_HPB1_Pos))
    161. 

  161. #define PM_AHBMASK_HPB2_Pos                   _U_(2)                                               /**< (PM_AHBMASK) HPB2 AHB Clock Mask Position */
    162. 

  162. #define PM_AHBMASK_HPB2_Msk                   (_U_(0x1) << PM_AHBMASK_HPB2_Pos)                    /**< (PM_AHBMASK) HPB2 AHB Clock Mask Mask */
    163. 

  163. #define PM_AHBMASK_HPB2(value)                (PM_AHBMASK_HPB2_Msk & ((value) << PM_AHBMASK_HPB2_Pos))
    164. 

  164. #define PM_AHBMASK_DSU_Pos                    _U_(3)                                               /**< (PM_AHBMASK) DSU AHB Clock Mask Position */
    165. 

  165. #define PM_AHBMASK_DSU_Msk                    (_U_(0x1) << PM_AHBMASK_DSU_Pos)                     /**< (PM_AHBMASK) DSU AHB Clock Mask Mask */
    166. 

  166. #define PM_AHBMASK_DSU(value)                 (PM_AHBMASK_DSU_Msk & ((value) << PM_AHBMASK_DSU_Pos))
    167. 

  167. #define PM_AHBMASK_NVMCTRL_Pos                _U_(4)                                               /**< (PM_AHBMASK) NVMCTRL AHB Clock Mask Position */
    168. 

  168. #define PM_AHBMASK_NVMCTRL_Msk                (_U_(0x1) << PM_AHBMASK_NVMCTRL_Pos)                 /**< (PM_AHBMASK) NVMCTRL AHB Clock Mask Mask */
    169. 

  169. #define PM_AHBMASK_NVMCTRL(value)             (PM_AHBMASK_NVMCTRL_Msk & ((value) << PM_AHBMASK_NVMCTRL_Pos))
    170. 

  170. #define PM_AHBMASK_DMAC_Pos                   _U_(5)                                               /**< (PM_AHBMASK) DMAC AHB Clock Mask Position */
    171. 

  171. #define PM_AHBMASK_DMAC_Msk                   (_U_(0x1) << PM_AHBMASK_DMAC_Pos)                    /**< (PM_AHBMASK) DMAC AHB Clock Mask Mask */
    172. 

  172. #define PM_AHBMASK_DMAC(value)                (PM_AHBMASK_DMAC_Msk & ((value) << PM_AHBMASK_DMAC_Pos))
    173. 

  173. #define PM_AHBMASK_USB_Pos                    _U_(6)                                               /**< (PM_AHBMASK) USB AHB Clock Mask Position */
    174. 

  174. #define PM_AHBMASK_USB_Msk                    (_U_(0x1) << PM_AHBMASK_USB_Pos)                     /**< (PM_AHBMASK) USB AHB Clock Mask Mask */
    175. 

  175. #define PM_AHBMASK_USB(value)                 (PM_AHBMASK_USB_Msk & ((value) << PM_AHBMASK_USB_Pos))
    176. 

  176. #define PM_AHBMASK_Msk                        _U_(0x0000007F)                                      /**< (PM_AHBMASK) Register Mask  */
    177. 

  177. 

  178. #define PM_AHBMASK_HPB_Pos                    _U_(0)                                               /**< (PM_AHBMASK Position) HPBx AHB Clock Mask */
    179. 

  179. #define PM_AHBMASK_HPB_Msk                    (_U_(0x7) << PM_AHBMASK_HPB_Pos)                     /**< (PM_AHBMASK Mask) HPB */
    180. 

  180. #define PM_AHBMASK_HPB(value)                 (PM_AHBMASK_HPB_Msk & ((value) << PM_AHBMASK_HPB_Pos)) 
    181. 

  181. 

  182. /* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
    183. 

  183. #define PM_APBAMASK_RESETVALUE                _U_(0x7F)                                            /**<  (PM_APBAMASK) APBA Mask  Reset Value */
    184. 

  184. 

  185. #define PM_APBAMASK_PAC0_Pos                  _U_(0)                                               /**< (PM_APBAMASK) PAC0 APB Clock Enable Position */
    186. 

  186. #define PM_APBAMASK_PAC0_Msk                  (_U_(0x1) << PM_APBAMASK_PAC0_Pos)                   /**< (PM_APBAMASK) PAC0 APB Clock Enable Mask */
    187. 

  187. #define PM_APBAMASK_PAC0(value)               (PM_APBAMASK_PAC0_Msk & ((value) << PM_APBAMASK_PAC0_Pos))
    188. 

  188. #define PM_APBAMASK_PM_Pos                    _U_(1)                                               /**< (PM_APBAMASK) PM APB Clock Enable Position */
    189. 

  189. #define PM_APBAMASK_PM_Msk                    (_U_(0x1) << PM_APBAMASK_PM_Pos)                     /**< (PM_APBAMASK) PM APB Clock Enable Mask */
    190. 

  190. #define PM_APBAMASK_PM(value)                 (PM_APBAMASK_PM_Msk & ((value) << PM_APBAMASK_PM_Pos))
    191. 

  191. #define PM_APBAMASK_SYSCTRL_Pos               _U_(2)                                               /**< (PM_APBAMASK) SYSCTRL APB Clock Enable Position */
    192. 

  192. #define PM_APBAMASK_SYSCTRL_Msk               (_U_(0x1) << PM_APBAMASK_SYSCTRL_Pos)                /**< (PM_APBAMASK) SYSCTRL APB Clock Enable Mask */
    193. 

  193. #define PM_APBAMASK_SYSCTRL(value)            (PM_APBAMASK_SYSCTRL_Msk & ((value) << PM_APBAMASK_SYSCTRL_Pos))
    194. 

  194. #define PM_APBAMASK_GCLK_Pos                  _U_(3)                                               /**< (PM_APBAMASK) GCLK APB Clock Enable Position */
    195. 

  195. #define PM_APBAMASK_GCLK_Msk                  (_U_(0x1) << PM_APBAMASK_GCLK_Pos)                   /**< (PM_APBAMASK) GCLK APB Clock Enable Mask */
    196. 

  196. #define PM_APBAMASK_GCLK(value)               (PM_APBAMASK_GCLK_Msk & ((value) << PM_APBAMASK_GCLK_Pos))
    197. 

  197. #define PM_APBAMASK_WDT_Pos                   _U_(4)                                               /**< (PM_APBAMASK) WDT APB Clock Enable Position */
    198. 

  198. #define PM_APBAMASK_WDT_Msk                   (_U_(0x1) << PM_APBAMASK_WDT_Pos)                    /**< (PM_APBAMASK) WDT APB Clock Enable Mask */
    199. 

  199. #define PM_APBAMASK_WDT(value)                (PM_APBAMASK_WDT_Msk & ((value) << PM_APBAMASK_WDT_Pos))
    200. 

  200. #define PM_APBAMASK_RTC_Pos                   _U_(5)                                               /**< (PM_APBAMASK) RTC APB Clock Enable Position */
    201. 

  201. #define PM_APBAMASK_RTC_Msk                   (_U_(0x1) << PM_APBAMASK_RTC_Pos)                    /**< (PM_APBAMASK) RTC APB Clock Enable Mask */
    202. 

  202. #define PM_APBAMASK_RTC(value)                (PM_APBAMASK_RTC_Msk & ((value) << PM_APBAMASK_RTC_Pos))
    203. 

  203. #define PM_APBAMASK_EIC_Pos                   _U_(6)                                               /**< (PM_APBAMASK) EIC APB Clock Enable Position */
    204. 

  204. #define PM_APBAMASK_EIC_Msk                   (_U_(0x1) << PM_APBAMASK_EIC_Pos)                    /**< (PM_APBAMASK) EIC APB Clock Enable Mask */
    205. 

  205. #define PM_APBAMASK_EIC(value)                (PM_APBAMASK_EIC_Msk & ((value) << PM_APBAMASK_EIC_Pos))
    206. 

  206. #define PM_APBAMASK_Msk                       _U_(0x0000007F)                                      /**< (PM_APBAMASK) Register Mask  */
    207. 

  207. 

  208. #define PM_APBAMASK_PAC_Pos                   _U_(0)                                               /**< (PM_APBAMASK Position) PACx APB Clock Enable */
    209. 

  209. #define PM_APBAMASK_PAC_Msk                   (_U_(0x1) << PM_APBAMASK_PAC_Pos)                    /**< (PM_APBAMASK Mask) PAC */
    210. 

  210. #define PM_APBAMASK_PAC(value)                (PM_APBAMASK_PAC_Msk & ((value) << PM_APBAMASK_PAC_Pos)) 
    211. 

  211. 

  212. /* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
    213. 

  213. #define PM_APBBMASK_RESETVALUE                _U_(0x7F)                                            /**<  (PM_APBBMASK) APBB Mask  Reset Value */
    214. 

  214. 

  215. #define PM_APBBMASK_PAC1_Pos                  _U_(0)                                               /**< (PM_APBBMASK) PAC1 APB Clock Enable Position */
    216. 

  216. #define PM_APBBMASK_PAC1_Msk                  (_U_(0x1) << PM_APBBMASK_PAC1_Pos)                   /**< (PM_APBBMASK) PAC1 APB Clock Enable Mask */
    217. 

  217. #define PM_APBBMASK_PAC1(value)               (PM_APBBMASK_PAC1_Msk & ((value) << PM_APBBMASK_PAC1_Pos))
    218. 

  218. #define PM_APBBMASK_DSU_Pos                   _U_(1)                                               /**< (PM_APBBMASK) DSU APB Clock Enable Position */
    219. 

  219. #define PM_APBBMASK_DSU_Msk                   (_U_(0x1) << PM_APBBMASK_DSU_Pos)                    /**< (PM_APBBMASK) DSU APB Clock Enable Mask */
    220. 

  220. #define PM_APBBMASK_DSU(value)                (PM_APBBMASK_DSU_Msk & ((value) << PM_APBBMASK_DSU_Pos))
    221. 

  221. #define PM_APBBMASK_NVMCTRL_Pos               _U_(2)                                               /**< (PM_APBBMASK) NVMCTRL APB Clock Enable Position */
    222. 

  222. #define PM_APBBMASK_NVMCTRL_Msk               (_U_(0x1) << PM_APBBMASK_NVMCTRL_Pos)                /**< (PM_APBBMASK) NVMCTRL APB Clock Enable Mask */
    223. 

  223. #define PM_APBBMASK_NVMCTRL(value)            (PM_APBBMASK_NVMCTRL_Msk & ((value) << PM_APBBMASK_NVMCTRL_Pos))
    224. 

  224. #define PM_APBBMASK_PORT_Pos                  _U_(3)                                               /**< (PM_APBBMASK) PORT APB Clock Enable Position */
    225. 

  225. #define PM_APBBMASK_PORT_Msk                  (_U_(0x1) << PM_APBBMASK_PORT_Pos)                   /**< (PM_APBBMASK) PORT APB Clock Enable Mask */
    226. 

  226. #define PM_APBBMASK_PORT(value)               (PM_APBBMASK_PORT_Msk & ((value) << PM_APBBMASK_PORT_Pos))
    227. 

  227. #define PM_APBBMASK_DMAC_Pos                  _U_(4)                                               /**< (PM_APBBMASK) DMAC APB Clock Enable Position */
    228. 

  228. #define PM_APBBMASK_DMAC_Msk                  (_U_(0x1) << PM_APBBMASK_DMAC_Pos)                   /**< (PM_APBBMASK) DMAC APB Clock Enable Mask */
    229. 

  229. #define PM_APBBMASK_DMAC(value)               (PM_APBBMASK_DMAC_Msk & ((value) << PM_APBBMASK_DMAC_Pos))
    230. 

  230. #define PM_APBBMASK_USB_Pos                   _U_(5)                                               /**< (PM_APBBMASK) USB APB Clock Enable Position */
    231. 

  231. #define PM_APBBMASK_USB_Msk                   (_U_(0x1) << PM_APBBMASK_USB_Pos)                    /**< (PM_APBBMASK) USB APB Clock Enable Mask */
    232. 

  232. #define PM_APBBMASK_USB(value)                (PM_APBBMASK_USB_Msk & ((value) << PM_APBBMASK_USB_Pos))
    233. 

  233. #define PM_APBBMASK_HMATRIX_Pos               _U_(6)                                               /**< (PM_APBBMASK) HMATRIX APB Clock Enable Position */
    234. 

  234. #define PM_APBBMASK_HMATRIX_Msk               (_U_(0x1) << PM_APBBMASK_HMATRIX_Pos)                /**< (PM_APBBMASK) HMATRIX APB Clock Enable Mask */
    235. 

  235. #define PM_APBBMASK_HMATRIX(value)            (PM_APBBMASK_HMATRIX_Msk & ((value) << PM_APBBMASK_HMATRIX_Pos))
    236. 

  236. #define PM_APBBMASK_Msk                       _U_(0x0000007F)                                      /**< (PM_APBBMASK) Register Mask  */
    237. 

  237. 

  238. #define PM_APBBMASK_PAC_Pos                   _U_(0)                                               /**< (PM_APBBMASK Position) PACx APB Clock Enable */
    239. 

  239. #define PM_APBBMASK_PAC_Msk                   (_U_(0x1) << PM_APBBMASK_PAC_Pos)                    /**< (PM_APBBMASK Mask) PAC */
    240. 

  240. #define PM_APBBMASK_PAC(value)                (PM_APBBMASK_PAC_Msk & ((value) << PM_APBBMASK_PAC_Pos)) 
    241. 

  241. 

  242. /* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
    243. 

  243. #define PM_APBCMASK_RESETVALUE                _U_(0x10000)                                         /**<  (PM_APBCMASK) APBC Mask  Reset Value */
    244. 

  244. 

  245. #define PM_APBCMASK_PAC2_Pos                  _U_(0)                                               /**< (PM_APBCMASK) PAC2 APB Clock Enable Position */
    246. 

  246. #define PM_APBCMASK_PAC2_Msk                  (_U_(0x1) << PM_APBCMASK_PAC2_Pos)                   /**< (PM_APBCMASK) PAC2 APB Clock Enable Mask */
    247. 

  247. #define PM_APBCMASK_PAC2(value)               (PM_APBCMASK_PAC2_Msk & ((value) << PM_APBCMASK_PAC2_Pos))
    248. 

  248. #define PM_APBCMASK_EVSYS_Pos                 _U_(1)                                               /**< (PM_APBCMASK) EVSYS APB Clock Enable Position */
    249. 

  249. #define PM_APBCMASK_EVSYS_Msk                 (_U_(0x1) << PM_APBCMASK_EVSYS_Pos)                  /**< (PM_APBCMASK) EVSYS APB Clock Enable Mask */
    250. 

  250. #define PM_APBCMASK_EVSYS(value)              (PM_APBCMASK_EVSYS_Msk & ((value) << PM_APBCMASK_EVSYS_Pos))
    251. 

  251. #define PM_APBCMASK_SERCOM0_Pos               _U_(2)                                               /**< (PM_APBCMASK) SERCOM0 APB Clock Enable Position */
    252. 

  252. #define PM_APBCMASK_SERCOM0_Msk               (_U_(0x1) << PM_APBCMASK_SERCOM0_Pos)                /**< (PM_APBCMASK) SERCOM0 APB Clock Enable Mask */
    253. 

  253. #define PM_APBCMASK_SERCOM0(value)            (PM_APBCMASK_SERCOM0_Msk & ((value) << PM_APBCMASK_SERCOM0_Pos))
    254. 

  254. #define PM_APBCMASK_SERCOM1_Pos               _U_(3)                                               /**< (PM_APBCMASK) SERCOM1 APB Clock Enable Position */
    255. 

  255. #define PM_APBCMASK_SERCOM1_Msk               (_U_(0x1) << PM_APBCMASK_SERCOM1_Pos)                /**< (PM_APBCMASK) SERCOM1 APB Clock Enable Mask */
    256. 

  256. #define PM_APBCMASK_SERCOM1(value)            (PM_APBCMASK_SERCOM1_Msk & ((value) << PM_APBCMASK_SERCOM1_Pos))
    257. 

  257. #define PM_APBCMASK_SERCOM2_Pos               _U_(4)                                               /**< (PM_APBCMASK) SERCOM2 APB Clock Enable Position */
    258. 

  258. #define PM_APBCMASK_SERCOM2_Msk               (_U_(0x1) << PM_APBCMASK_SERCOM2_Pos)                /**< (PM_APBCMASK) SERCOM2 APB Clock Enable Mask */
    259. 

  259. #define PM_APBCMASK_SERCOM2(value)            (PM_APBCMASK_SERCOM2_Msk & ((value) << PM_APBCMASK_SERCOM2_Pos))
    260. 

  260. #define PM_APBCMASK_SERCOM3_Pos               _U_(5)                                               /**< (PM_APBCMASK) SERCOM3 APB Clock Enable Position */
    261. 

  261. #define PM_APBCMASK_SERCOM3_Msk               (_U_(0x1) << PM_APBCMASK_SERCOM3_Pos)                /**< (PM_APBCMASK) SERCOM3 APB Clock Enable Mask */
    262. 

  262. #define PM_APBCMASK_SERCOM3(value)            (PM_APBCMASK_SERCOM3_Msk & ((value) << PM_APBCMASK_SERCOM3_Pos))
    263. 

  263. #define PM_APBCMASK_SERCOM4_Pos               _U_(6)                                               /**< (PM_APBCMASK) SERCOM4 APB Clock Enable Position */
    264. 

  264. #define PM_APBCMASK_SERCOM4_Msk               (_U_(0x1) << PM_APBCMASK_SERCOM4_Pos)                /**< (PM_APBCMASK) SERCOM4 APB Clock Enable Mask */
    265. 

  265. #define PM_APBCMASK_SERCOM4(value)            (PM_APBCMASK_SERCOM4_Msk & ((value) << PM_APBCMASK_SERCOM4_Pos))
    266. 

  266. #define PM_APBCMASK_SERCOM5_Pos               _U_(7)                                               /**< (PM_APBCMASK) SERCOM5 APB Clock Enable Position */
    267. 

  267. #define PM_APBCMASK_SERCOM5_Msk               (_U_(0x1) << PM_APBCMASK_SERCOM5_Pos)                /**< (PM_APBCMASK) SERCOM5 APB Clock Enable Mask */
    268. 

  268. #define PM_APBCMASK_SERCOM5(value)            (PM_APBCMASK_SERCOM5_Msk & ((value) << PM_APBCMASK_SERCOM5_Pos))
    269. 

  269. #define PM_APBCMASK_TCC0_Pos                  _U_(8)                                               /**< (PM_APBCMASK) TCC0 APB Clock Enable Position */
    270. 

  270. #define PM_APBCMASK_TCC0_Msk                  (_U_(0x1) << PM_APBCMASK_TCC0_Pos)                   /**< (PM_APBCMASK) TCC0 APB Clock Enable Mask */
    271. 

  271. #define PM_APBCMASK_TCC0(value)               (PM_APBCMASK_TCC0_Msk & ((value) << PM_APBCMASK_TCC0_Pos))
    272. 

  272. #define PM_APBCMASK_TCC1_Pos                  _U_(9)                                               /**< (PM_APBCMASK) TCC1 APB Clock Enable Position */
    273. 

  273. #define PM_APBCMASK_TCC1_Msk                  (_U_(0x1) << PM_APBCMASK_TCC1_Pos)                   /**< (PM_APBCMASK) TCC1 APB Clock Enable Mask */
    274. 

  274. #define PM_APBCMASK_TCC1(value)               (PM_APBCMASK_TCC1_Msk & ((value) << PM_APBCMASK_TCC1_Pos))
    275. 

  275. #define PM_APBCMASK_TCC2_Pos                  _U_(10)                                              /**< (PM_APBCMASK) TCC2 APB Clock Enable Position */
    276. 

  276. #define PM_APBCMASK_TCC2_Msk                  (_U_(0x1) << PM_APBCMASK_TCC2_Pos)                   /**< (PM_APBCMASK) TCC2 APB Clock Enable Mask */
    277. 

  277. #define PM_APBCMASK_TCC2(value)               (PM_APBCMASK_TCC2_Msk & ((value) << PM_APBCMASK_TCC2_Pos))
    278. 

  278. #define PM_APBCMASK_TC3_Pos                   _U_(11)                                              /**< (PM_APBCMASK) TC3 APB Clock Enable Position */
    279. 

  279. #define PM_APBCMASK_TC3_Msk                   (_U_(0x1) << PM_APBCMASK_TC3_Pos)                    /**< (PM_APBCMASK) TC3 APB Clock Enable Mask */
    280. 

  280. #define PM_APBCMASK_TC3(value)                (PM_APBCMASK_TC3_Msk & ((value) << PM_APBCMASK_TC3_Pos))
    281. 

  281. #define PM_APBCMASK_TC4_Pos                   _U_(12)                                              /**< (PM_APBCMASK) TC4 APB Clock Enable Position */
    282. 

  282. #define PM_APBCMASK_TC4_Msk                   (_U_(0x1) << PM_APBCMASK_TC4_Pos)                    /**< (PM_APBCMASK) TC4 APB Clock Enable Mask */
    283. 

  283. #define PM_APBCMASK_TC4(value)                (PM_APBCMASK_TC4_Msk & ((value) << PM_APBCMASK_TC4_Pos))
    284. 

  284. #define PM_APBCMASK_TC5_Pos                   _U_(13)                                              /**< (PM_APBCMASK) TC5 APB Clock Enable Position */
    285. 

  285. #define PM_APBCMASK_TC5_Msk                   (_U_(0x1) << PM_APBCMASK_TC5_Pos)                    /**< (PM_APBCMASK) TC5 APB Clock Enable Mask */
    286. 

  286. #define PM_APBCMASK_TC5(value)                (PM_APBCMASK_TC5_Msk & ((value) << PM_APBCMASK_TC5_Pos))
    287. 

  287. #define PM_APBCMASK_TC6_Pos                   _U_(14)                                              /**< (PM_APBCMASK) TC6 APB Clock Enable Position */
    288. 

  288. #define PM_APBCMASK_TC6_Msk                   (_U_(0x1) << PM_APBCMASK_TC6_Pos)                    /**< (PM_APBCMASK) TC6 APB Clock Enable Mask */
    289. 

  289. #define PM_APBCMASK_TC6(value)                (PM_APBCMASK_TC6_Msk & ((value) << PM_APBCMASK_TC6_Pos))
    290. 

  290. #define PM_APBCMASK_TC7_Pos                   _U_(15)                                              /**< (PM_APBCMASK) TC7 APB Clock Enable Position */
    291. 

  291. #define PM_APBCMASK_TC7_Msk                   (_U_(0x1) << PM_APBCMASK_TC7_Pos)                    /**< (PM_APBCMASK) TC7 APB Clock Enable Mask */
    292. 

  292. #define PM_APBCMASK_TC7(value)                (PM_APBCMASK_TC7_Msk & ((value) << PM_APBCMASK_TC7_Pos))
    293. 

  293. #define PM_APBCMASK_ADC_Pos                   _U_(16)                                              /**< (PM_APBCMASK) ADC APB Clock Enable Position */
    294. 

  294. #define PM_APBCMASK_ADC_Msk                   (_U_(0x1) << PM_APBCMASK_ADC_Pos)                    /**< (PM_APBCMASK) ADC APB Clock Enable Mask */
    295. 

  295. #define PM_APBCMASK_ADC(value)                (PM_APBCMASK_ADC_Msk & ((value) << PM_APBCMASK_ADC_Pos))
    296. 

  296. #define PM_APBCMASK_AC_Pos                    _U_(17)                                              /**< (PM_APBCMASK) AC APB Clock Enable Position */
    297. 

  297. #define PM_APBCMASK_AC_Msk                    (_U_(0x1) << PM_APBCMASK_AC_Pos)                     /**< (PM_APBCMASK) AC APB Clock Enable Mask */
    298. 

  298. #define PM_APBCMASK_AC(value)                 (PM_APBCMASK_AC_Msk & ((value) << PM_APBCMASK_AC_Pos))
    299. 

  299. #define PM_APBCMASK_DAC_Pos                   _U_(18)                                              /**< (PM_APBCMASK) DAC APB Clock Enable Position */
    300. 

  300. #define PM_APBCMASK_DAC_Msk                   (_U_(0x1) << PM_APBCMASK_DAC_Pos)                    /**< (PM_APBCMASK) DAC APB Clock Enable Mask */
    301. 

  301. #define PM_APBCMASK_DAC(value)                (PM_APBCMASK_DAC_Msk & ((value) << PM_APBCMASK_DAC_Pos))
    302. 

  302. #define PM_APBCMASK_PTC_Pos                   _U_(19)                                              /**< (PM_APBCMASK) PTC APB Clock Enable Position */
    303. 

  303. #define PM_APBCMASK_PTC_Msk                   (_U_(0x1) << PM_APBCMASK_PTC_Pos)                    /**< (PM_APBCMASK) PTC APB Clock Enable Mask */
    304. 

  304. #define PM_APBCMASK_PTC(value)                (PM_APBCMASK_PTC_Msk & ((value) << PM_APBCMASK_PTC_Pos))
    305. 

  305. #define PM_APBCMASK_I2S_Pos                   _U_(20)                                              /**< (PM_APBCMASK) I2S APB Clock Enable Position */
    306. 

  306. #define PM_APBCMASK_I2S_Msk                   (_U_(0x1) << PM_APBCMASK_I2S_Pos)                    /**< (PM_APBCMASK) I2S APB Clock Enable Mask */
    307. 

  307. #define PM_APBCMASK_I2S(value)                (PM_APBCMASK_I2S_Msk & ((value) << PM_APBCMASK_I2S_Pos))
    308. 

  308. #define PM_APBCMASK_Msk                       _U_(0x001FFFFF)                                      /**< (PM_APBCMASK) Register Mask  */
    309. 

  309. 

  310. #define PM_APBCMASK_PAC_Pos                   _U_(0)                                               /**< (PM_APBCMASK Position) PAC2 APB Clock Enable */
    311. 

  311. #define PM_APBCMASK_PAC_Msk                   (_U_(0x1) << PM_APBCMASK_PAC_Pos)                    /**< (PM_APBCMASK Mask) PAC */
    312. 

  312. #define PM_APBCMASK_PAC(value)                (PM_APBCMASK_PAC_Msk & ((value) << PM_APBCMASK_PAC_Pos)) 
    313. 

  313. #define PM_APBCMASK_SERCOM_Pos                _U_(2)                                               /**< (PM_APBCMASK Position) SERCOMx APB Clock Enable */
    314. 

  314. #define PM_APBCMASK_SERCOM_Msk                (_U_(0x3F) << PM_APBCMASK_SERCOM_Pos)                /**< (PM_APBCMASK Mask) SERCOM */
    315. 

  315. #define PM_APBCMASK_SERCOM(value)             (PM_APBCMASK_SERCOM_Msk & ((value) << PM_APBCMASK_SERCOM_Pos)) 
    316. 

  316. #define PM_APBCMASK_TCC_Pos                   _U_(8)                                               /**< (PM_APBCMASK Position) TCCx APB Clock Enable */
    317. 

  317. #define PM_APBCMASK_TCC_Msk                   (_U_(0x7) << PM_APBCMASK_TCC_Pos)                    /**< (PM_APBCMASK Mask) TCC */
    318. 

  318. #define PM_APBCMASK_TCC(value)                (PM_APBCMASK_TCC_Msk & ((value) << PM_APBCMASK_TCC_Pos)) 
    319. 

  319. #define PM_APBCMASK_TC_Pos                    _U_(11)                                              /**< (PM_APBCMASK Position) TC3 APB Clock Enable */
    320. 

  320. #define PM_APBCMASK_TC_Msk                    (_U_(0x1F) << PM_APBCMASK_TC_Pos)                    /**< (PM_APBCMASK Mask) TC */
    321. 

  321. #define PM_APBCMASK_TC(value)                 (PM_APBCMASK_TC_Msk & ((value) << PM_APBCMASK_TC_Pos)) 
    322. 

  322. 

  323. /* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
    324. 

  324. #define PM_INTENCLR_RESETVALUE                _U_(0x00)                                            /**<  (PM_INTENCLR) Interrupt Enable Clear  Reset Value */
    325. 

  325. 

  326. #define PM_INTENCLR_CKRDY_Pos                 _U_(0)                                               /**< (PM_INTENCLR) Clock Ready Interrupt Enable Position */
    327. 

  327. #define PM_INTENCLR_CKRDY_Msk                 (_U_(0x1) << PM_INTENCLR_CKRDY_Pos)                  /**< (PM_INTENCLR) Clock Ready Interrupt Enable Mask */
    328. 

  328. #define PM_INTENCLR_CKRDY(value)              (PM_INTENCLR_CKRDY_Msk & ((value) << PM_INTENCLR_CKRDY_Pos))
    329. 

  329. #define PM_INTENCLR_Msk                       _U_(0x01)                                            /**< (PM_INTENCLR) Register Mask  */
    330. 

  330. 

  331. 

  332. /* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
    333. 

  333. #define PM_INTENSET_RESETVALUE                _U_(0x00)                                            /**<  (PM_INTENSET) Interrupt Enable Set  Reset Value */
    334. 

  334. 

  335. #define PM_INTENSET_CKRDY_Pos                 _U_(0)                                               /**< (PM_INTENSET) Clock Ready Interrupt Enable Position */
    336. 

  336. #define PM_INTENSET_CKRDY_Msk                 (_U_(0x1) << PM_INTENSET_CKRDY_Pos)                  /**< (PM_INTENSET) Clock Ready Interrupt Enable Mask */
    337. 

  337. #define PM_INTENSET_CKRDY(value)              (PM_INTENSET_CKRDY_Msk & ((value) << PM_INTENSET_CKRDY_Pos))
    338. 

  338. #define PM_INTENSET_Msk                       _U_(0x01)                                            /**< (PM_INTENSET) Register Mask  */
    339. 

  339. 

  340. 

  341. /* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
    342. 

  342. #define PM_INTFLAG_RESETVALUE                 _U_(0x00)                                            /**<  (PM_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    343. 

  343. 

  344. #define PM_INTFLAG_CKRDY_Pos                  _U_(0)                                               /**< (PM_INTFLAG) Clock Ready Position */
    345. 

  345. #define PM_INTFLAG_CKRDY_Msk                  (_U_(0x1) << PM_INTFLAG_CKRDY_Pos)                   /**< (PM_INTFLAG) Clock Ready Mask */
    346. 

  346. #define PM_INTFLAG_CKRDY(value)               (PM_INTFLAG_CKRDY_Msk & ((value) << PM_INTFLAG_CKRDY_Pos))
    347. 

  347. #define PM_INTFLAG_Msk                        _U_(0x01)                                            /**< (PM_INTFLAG) Register Mask  */
    348. 

  348. 

  349. 

  350. /* -------- PM_RCAUSE : (PM Offset: 0x38) ( R/ 8) Reset Cause -------- */
    351. 

  351. #define PM_RCAUSE_RESETVALUE                  _U_(0x01)                                            /**<  (PM_RCAUSE) Reset Cause  Reset Value */
    352. 

  352. 

  353. #define PM_RCAUSE_POR_Pos                     _U_(0)                                               /**< (PM_RCAUSE) Power On Reset Position */
    354. 

  354. #define PM_RCAUSE_POR_Msk                     (_U_(0x1) << PM_RCAUSE_POR_Pos)                      /**< (PM_RCAUSE) Power On Reset Mask */
    355. 

  355. #define PM_RCAUSE_POR(value)                  (PM_RCAUSE_POR_Msk & ((value) << PM_RCAUSE_POR_Pos))
    356. 

  356. #define PM_RCAUSE_BOD12_Pos                   _U_(1)                                               /**< (PM_RCAUSE) Brown Out 12 Detector Reset Position */
    357. 

  357. #define PM_RCAUSE_BOD12_Msk                   (_U_(0x1) << PM_RCAUSE_BOD12_Pos)                    /**< (PM_RCAUSE) Brown Out 12 Detector Reset Mask */
    358. 

  358. #define PM_RCAUSE_BOD12(value)                (PM_RCAUSE_BOD12_Msk & ((value) << PM_RCAUSE_BOD12_Pos))
    359. 

  359. #define PM_RCAUSE_BOD33_Pos                   _U_(2)                                               /**< (PM_RCAUSE) Brown Out 33 Detector Reset Position */
    360. 

  360. #define PM_RCAUSE_BOD33_Msk                   (_U_(0x1) << PM_RCAUSE_BOD33_Pos)                    /**< (PM_RCAUSE) Brown Out 33 Detector Reset Mask */
    361. 

  361. #define PM_RCAUSE_BOD33(value)                (PM_RCAUSE_BOD33_Msk & ((value) << PM_RCAUSE_BOD33_Pos))
    362. 

  362. #define PM_RCAUSE_EXT_Pos                     _U_(4)                                               /**< (PM_RCAUSE) External Reset Position */
    363. 

  363. #define PM_RCAUSE_EXT_Msk                     (_U_(0x1) << PM_RCAUSE_EXT_Pos)                      /**< (PM_RCAUSE) External Reset Mask */
    364. 

  364. #define PM_RCAUSE_EXT(value)                  (PM_RCAUSE_EXT_Msk & ((value) << PM_RCAUSE_EXT_Pos))
    365. 

  365. #define PM_RCAUSE_WDT_Pos                     _U_(5)                                               /**< (PM_RCAUSE) Watchdog Reset Position */
    366. 

  366. #define PM_RCAUSE_WDT_Msk                     (_U_(0x1) << PM_RCAUSE_WDT_Pos)                      /**< (PM_RCAUSE) Watchdog Reset Mask */
    367. 

  367. #define PM_RCAUSE_WDT(value)                  (PM_RCAUSE_WDT_Msk & ((value) << PM_RCAUSE_WDT_Pos))
    368. 

  368. #define PM_RCAUSE_SYST_Pos                    _U_(6)                                               /**< (PM_RCAUSE) System Reset Request Position */
    369. 

  369. #define PM_RCAUSE_SYST_Msk                    (_U_(0x1) << PM_RCAUSE_SYST_Pos)                     /**< (PM_RCAUSE) System Reset Request Mask */
    370. 

  370. #define PM_RCAUSE_SYST(value)                 (PM_RCAUSE_SYST_Msk & ((value) << PM_RCAUSE_SYST_Pos))
    371. 

  371. #define PM_RCAUSE_Msk                         _U_(0x77)                                            /**< (PM_RCAUSE) Register Mask  */
    372. 

  372. 

  373. #define PM_RCAUSE_BOD_Pos                     _U_(1)                                               /**< (PM_RCAUSE Position) Brown Out x2 Detector Reset */
    374. 

  374. #define PM_RCAUSE_BOD_Msk                     (_U_(0x3) << PM_RCAUSE_BOD_Pos)                      /**< (PM_RCAUSE Mask) BOD */
    375. 

  375. #define PM_RCAUSE_BOD(value)                  (PM_RCAUSE_BOD_Msk & ((value) << PM_RCAUSE_BOD_Pos)) 
    376. 

  376. 

  377. /** \brief PM register offsets definitions */
    378. 

  378. #define PM_CTRL_REG_OFST               (0x00)              /**< (PM_CTRL) Control Offset */
    379. 

  379. #define PM_SLEEP_REG_OFST              (0x01)              /**< (PM_SLEEP) Sleep Mode Offset */
    380. 

  380. #define PM_CPUSEL_REG_OFST             (0x08)              /**< (PM_CPUSEL) CPU Clock Select Offset */
    381. 

  381. #define PM_APBASEL_REG_OFST            (0x09)              /**< (PM_APBASEL) APBA Clock Select Offset */
    382. 

  382. #define PM_APBBSEL_REG_OFST            (0x0A)              /**< (PM_APBBSEL) APBB Clock Select Offset */
    383. 

  383. #define PM_APBCSEL_REG_OFST            (0x0B)              /**< (PM_APBCSEL) APBC Clock Select Offset */
    384. 

  384. #define PM_AHBMASK_REG_OFST            (0x14)              /**< (PM_AHBMASK) AHB Mask Offset */
    385. 

  385. #define PM_APBAMASK_REG_OFST           (0x18)              /**< (PM_APBAMASK) APBA Mask Offset */
    386. 

  386. #define PM_APBBMASK_REG_OFST           (0x1C)              /**< (PM_APBBMASK) APBB Mask Offset */
    387. 

  387. #define PM_APBCMASK_REG_OFST           (0x20)              /**< (PM_APBCMASK) APBC Mask Offset */
    388. 

  388. #define PM_INTENCLR_REG_OFST           (0x34)              /**< (PM_INTENCLR) Interrupt Enable Clear Offset */
    389. 

  389. #define PM_INTENSET_REG_OFST           (0x35)              /**< (PM_INTENSET) Interrupt Enable Set Offset */
    390. 

  390. #define PM_INTFLAG_REG_OFST            (0x36)              /**< (PM_INTFLAG) Interrupt Flag Status and Clear Offset */
    391. 

  391. #define PM_RCAUSE_REG_OFST             (0x38)              /**< (PM_RCAUSE) Reset Cause Offset */
    392. 

  392. 

  393. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    394. 

  394. /** \brief PM register API structure */
    395. 

  395. typedef struct
    396. 

  396. {  /* Power Manager */
    397. 

  397.   __IO  uint8_t                        PM_CTRL;            /**< Offset: 0x00 (R/W  8) Control */
    398. 

  398.   __IO  uint8_t                        PM_SLEEP;           /**< Offset: 0x01 (R/W  8) Sleep Mode */
    399. 

  399.   __I   uint8_t                        Reserved1[0x06];
    400. 

  400.   __IO  uint8_t                        PM_CPUSEL;          /**< Offset: 0x08 (R/W  8) CPU Clock Select */
    401. 

  401.   __IO  uint8_t                        PM_APBASEL;         /**< Offset: 0x09 (R/W  8) APBA Clock Select */
    402. 

  402.   __IO  uint8_t                        PM_APBBSEL;         /**< Offset: 0x0A (R/W  8) APBB Clock Select */
    403. 

  403.   __IO  uint8_t                        PM_APBCSEL;         /**< Offset: 0x0B (R/W  8) APBC Clock Select */
    404. 

  404.   __I   uint8_t                        Reserved2[0x08];
    405. 

  405.   __IO  uint32_t                       PM_AHBMASK;         /**< Offset: 0x14 (R/W  32) AHB Mask */
    406. 

  406.   __IO  uint32_t                       PM_APBAMASK;        /**< Offset: 0x18 (R/W  32) APBA Mask */
    407. 

  407.   __IO  uint32_t                       PM_APBBMASK;        /**< Offset: 0x1C (R/W  32) APBB Mask */
    408. 

  408.   __IO  uint32_t                       PM_APBCMASK;        /**< Offset: 0x20 (R/W  32) APBC Mask */
    409. 

  409.   __I   uint8_t                        Reserved3[0x10];
    410. 

  410.   __IO  uint8_t                        PM_INTENCLR;        /**< Offset: 0x34 (R/W  8) Interrupt Enable Clear */
    411. 

  411.   __IO  uint8_t                        PM_INTENSET;        /**< Offset: 0x35 (R/W  8) Interrupt Enable Set */
    412. 

  412.   __IO  uint8_t                        PM_INTFLAG;         /**< Offset: 0x36 (R/W  8) Interrupt Flag Status and Clear */
    413. 

  413.   __I   uint8_t                        Reserved4[0x01];
    414. 

  414.   __I   uint8_t                        PM_RCAUSE;          /**< Offset: 0x38 (R/   8) Reset Cause */
    415. 

  415. } pm_registers_t;
    416. 

  416. 

  417. 

  418. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    419. 

  419. #endif /* _SAMD21_PM_COMPONENT_H_ */
    420.