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sdk-csp-atsamd2...
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libraries
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include
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component
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port.h

port.h 30 KB
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  1. /**
    2. 

  2.  * \brief Component description for PORT
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_PORT_COMPONENT_H_
    25. 

  25. #define _SAMD21_PORT_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR PORT                                         */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) Data Direction -------- */
    32. 

  32. #define PORT_DIR_RESETVALUE                   _U_(0x00)                                            /**<  (PORT_DIR) Data Direction  Reset Value */
    33. 

  33. 

  34. #define PORT_DIR_DIR_Pos                      _U_(0)                                               /**< (PORT_DIR) Port Data Direction Position */
    35. 

  35. #define PORT_DIR_DIR_Msk                      (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)                /**< (PORT_DIR) Port Data Direction Mask */
    36. 

  36. #define PORT_DIR_DIR(value)                   (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))  
    37. 

  37. #define PORT_DIR_Msk                          _U_(0xFFFFFFFF)                                      /**< (PORT_DIR) Register Mask  */
    38. 

  38. 

  39. 

  40. /* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) Data Direction Clear -------- */
    41. 

  41. #define PORT_DIRCLR_RESETVALUE                _U_(0x00)                                            /**<  (PORT_DIRCLR) Data Direction Clear  Reset Value */
    42. 

  42. 

  43. #define PORT_DIRCLR_DIRCLR_Pos                _U_(0)                                               /**< (PORT_DIRCLR) Port Data Direction Clear Position */
    44. 

  44. #define PORT_DIRCLR_DIRCLR_Msk                (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)          /**< (PORT_DIRCLR) Port Data Direction Clear Mask */
    45. 

  45. #define PORT_DIRCLR_DIRCLR(value)             (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
    46. 

  46. #define PORT_DIRCLR_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_DIRCLR) Register Mask  */
    47. 

  47. 

  48. 

  49. /* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) Data Direction Set -------- */
    50. 

  50. #define PORT_DIRSET_RESETVALUE                _U_(0x00)                                            /**<  (PORT_DIRSET) Data Direction Set  Reset Value */
    51. 

  51. 

  52. #define PORT_DIRSET_DIRSET_Pos                _U_(0)                                               /**< (PORT_DIRSET) Port Data Direction Set Position */
    53. 

  53. #define PORT_DIRSET_DIRSET_Msk                (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)          /**< (PORT_DIRSET) Port Data Direction Set Mask */
    54. 

  54. #define PORT_DIRSET_DIRSET(value)             (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
    55. 

  55. #define PORT_DIRSET_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_DIRSET) Register Mask  */
    56. 

  56. 

  57. 

  58. /* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) Data Direction Toggle -------- */
    59. 

  59. #define PORT_DIRTGL_RESETVALUE                _U_(0x00)                                            /**<  (PORT_DIRTGL) Data Direction Toggle  Reset Value */
    60. 

  60. 

  61. #define PORT_DIRTGL_DIRTGL_Pos                _U_(0)                                               /**< (PORT_DIRTGL) Port Data Direction Toggle Position */
    62. 

  62. #define PORT_DIRTGL_DIRTGL_Msk                (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)          /**< (PORT_DIRTGL) Port Data Direction Toggle Mask */
    63. 

  63. #define PORT_DIRTGL_DIRTGL(value)             (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
    64. 

  64. #define PORT_DIRTGL_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_DIRTGL) Register Mask  */
    65. 

  65. 

  66. 

  67. /* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) Data Output Value -------- */
    68. 

  68. #define PORT_OUT_RESETVALUE                   _U_(0x00)                                            /**<  (PORT_OUT) Data Output Value  Reset Value */
    69. 

  69. 

  70. #define PORT_OUT_OUT_Pos                      _U_(0)                                               /**< (PORT_OUT) Port Data Output Value Position */
    71. 

  71. #define PORT_OUT_OUT_Msk                      (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)                /**< (PORT_OUT) Port Data Output Value Mask */
    72. 

  72. #define PORT_OUT_OUT(value)                   (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))  
    73. 

  73. #define PORT_OUT_Msk                          _U_(0xFFFFFFFF)                                      /**< (PORT_OUT) Register Mask  */
    74. 

  74. 

  75. 

  76. /* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) Data Output Value Clear -------- */
    77. 

  77. #define PORT_OUTCLR_RESETVALUE                _U_(0x00)                                            /**<  (PORT_OUTCLR) Data Output Value Clear  Reset Value */
    78. 

  78. 

  79. #define PORT_OUTCLR_OUTCLR_Pos                _U_(0)                                               /**< (PORT_OUTCLR) Port Data Output Value Clear Position */
    80. 

  80. #define PORT_OUTCLR_OUTCLR_Msk                (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)          /**< (PORT_OUTCLR) Port Data Output Value Clear Mask */
    81. 

  81. #define PORT_OUTCLR_OUTCLR(value)             (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
    82. 

  82. #define PORT_OUTCLR_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_OUTCLR) Register Mask  */
    83. 

  83. 

  84. 

  85. /* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) Data Output Value Set -------- */
    86. 

  86. #define PORT_OUTSET_RESETVALUE                _U_(0x00)                                            /**<  (PORT_OUTSET) Data Output Value Set  Reset Value */
    87. 

  87. 

  88. #define PORT_OUTSET_OUTSET_Pos                _U_(0)                                               /**< (PORT_OUTSET) Port Data Output Value Set Position */
    89. 

  89. #define PORT_OUTSET_OUTSET_Msk                (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)          /**< (PORT_OUTSET) Port Data Output Value Set Mask */
    90. 

  90. #define PORT_OUTSET_OUTSET(value)             (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
    91. 

  91. #define PORT_OUTSET_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_OUTSET) Register Mask  */
    92. 

  92. 

  93. 

  94. /* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) Data Output Value Toggle -------- */
    95. 

  95. #define PORT_OUTTGL_RESETVALUE                _U_(0x00)                                            /**<  (PORT_OUTTGL) Data Output Value Toggle  Reset Value */
    96. 

  96. 

  97. #define PORT_OUTTGL_OUTTGL_Pos                _U_(0)                                               /**< (PORT_OUTTGL) Port Data Output Value Toggle Position */
    98. 

  98. #define PORT_OUTTGL_OUTTGL_Msk                (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)          /**< (PORT_OUTTGL) Port Data Output Value Toggle Mask */
    99. 

  99. #define PORT_OUTTGL_OUTTGL(value)             (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
    100. 

  100. #define PORT_OUTTGL_Msk                       _U_(0xFFFFFFFF)                                      /**< (PORT_OUTTGL) Register Mask  */
    101. 

  101. 

  102. 

  103. /* -------- PORT_IN : (PORT Offset: 0x20) ( R/ 32) Data Input Value -------- */
    104. 

  104. #define PORT_IN_RESETVALUE                    _U_(0x00)                                            /**<  (PORT_IN) Data Input Value  Reset Value */
    105. 

  105. 

  106. #define PORT_IN_IN_Pos                        _U_(0)                                               /**< (PORT_IN) Port Data Input Value Position */
    107. 

  107. #define PORT_IN_IN_Msk                        (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)                  /**< (PORT_IN) Port Data Input Value Mask */
    108. 

  108. #define PORT_IN_IN(value)                     (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))      
    109. 

  109. #define PORT_IN_Msk                           _U_(0xFFFFFFFF)                                      /**< (PORT_IN) Register Mask  */
    110. 

  110. 

  111. 

  112. /* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) Control -------- */
    113. 

  113. #define PORT_CTRL_RESETVALUE                  _U_(0x00)                                            /**<  (PORT_CTRL) Control  Reset Value */
    114. 

  114. 

  115. #define PORT_CTRL_SAMPLING_Pos                _U_(0)                                               /**< (PORT_CTRL) Input Sampling Mode Position */
    116. 

  116. #define PORT_CTRL_SAMPLING_Msk                (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)          /**< (PORT_CTRL) Input Sampling Mode Mask */
    117. 

  117. #define PORT_CTRL_SAMPLING(value)             (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
    118. 

  118. #define PORT_CTRL_Msk                         _U_(0xFFFFFFFF)                                      /**< (PORT_CTRL) Register Mask  */
    119. 

  119. 

  120. 

  121. /* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) Write Configuration -------- */
    122. 

  122. #define PORT_WRCONFIG_RESETVALUE              _U_(0x00)                                            /**<  (PORT_WRCONFIG) Write Configuration  Reset Value */
    123. 

  123. 

  124. #define PORT_WRCONFIG_PINMASK_Pos             _U_(0)                                               /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Position */
    125. 

  125. #define PORT_WRCONFIG_PINMASK_Msk             (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)           /**< (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration Mask */
    126. 

  126. #define PORT_WRCONFIG_PINMASK(value)          (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
    127. 

  127. #define PORT_WRCONFIG_PMUXEN_Pos              _U_(16)                                              /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Position */
    128. 

  128. #define PORT_WRCONFIG_PMUXEN_Msk              (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)               /**< (PORT_WRCONFIG) Peripheral Multiplexer Enable Mask */
    129. 

  129. #define PORT_WRCONFIG_PMUXEN(value)           (PORT_WRCONFIG_PMUXEN_Msk & ((value) << PORT_WRCONFIG_PMUXEN_Pos))
    130. 

  130. #define PORT_WRCONFIG_INEN_Pos                _U_(17)                                              /**< (PORT_WRCONFIG) Input Enable Position */
    131. 

  131. #define PORT_WRCONFIG_INEN_Msk                (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)                 /**< (PORT_WRCONFIG) Input Enable Mask */
    132. 

  132. #define PORT_WRCONFIG_INEN(value)             (PORT_WRCONFIG_INEN_Msk & ((value) << PORT_WRCONFIG_INEN_Pos))
    133. 

  133. #define PORT_WRCONFIG_PULLEN_Pos              _U_(18)                                              /**< (PORT_WRCONFIG) Pull Enable Position */
    134. 

  134. #define PORT_WRCONFIG_PULLEN_Msk              (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)               /**< (PORT_WRCONFIG) Pull Enable Mask */
    135. 

  135. #define PORT_WRCONFIG_PULLEN(value)           (PORT_WRCONFIG_PULLEN_Msk & ((value) << PORT_WRCONFIG_PULLEN_Pos))
    136. 

  136. #define PORT_WRCONFIG_DRVSTR_Pos              _U_(22)                                              /**< (PORT_WRCONFIG) Output Driver Strength Selection Position */
    137. 

  137. #define PORT_WRCONFIG_DRVSTR_Msk              (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)               /**< (PORT_WRCONFIG) Output Driver Strength Selection Mask */
    138. 

  138. #define PORT_WRCONFIG_DRVSTR(value)           (PORT_WRCONFIG_DRVSTR_Msk & ((value) << PORT_WRCONFIG_DRVSTR_Pos))
    139. 

  139. #define PORT_WRCONFIG_PMUX_Pos                _U_(24)                                              /**< (PORT_WRCONFIG) Peripheral Multiplexing Position */
    140. 

  140. #define PORT_WRCONFIG_PMUX_Msk                (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)                 /**< (PORT_WRCONFIG) Peripheral Multiplexing Mask */
    141. 

  141. #define PORT_WRCONFIG_PMUX(value)             (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
    142. 

  142. #define PORT_WRCONFIG_WRPMUX_Pos              _U_(28)                                              /**< (PORT_WRCONFIG) Write PMUX Position */
    143. 

  143. #define PORT_WRCONFIG_WRPMUX_Msk              (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)               /**< (PORT_WRCONFIG) Write PMUX Mask */
    144. 

  144. #define PORT_WRCONFIG_WRPMUX(value)           (PORT_WRCONFIG_WRPMUX_Msk & ((value) << PORT_WRCONFIG_WRPMUX_Pos))
    145. 

  145. #define PORT_WRCONFIG_WRPINCFG_Pos            _U_(30)                                              /**< (PORT_WRCONFIG) Write PINCFG Position */
    146. 

  146. #define PORT_WRCONFIG_WRPINCFG_Msk            (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)             /**< (PORT_WRCONFIG) Write PINCFG Mask */
    147. 

  147. #define PORT_WRCONFIG_WRPINCFG(value)         (PORT_WRCONFIG_WRPINCFG_Msk & ((value) << PORT_WRCONFIG_WRPINCFG_Pos))
    148. 

  148. #define PORT_WRCONFIG_HWSEL_Pos               _U_(31)                                              /**< (PORT_WRCONFIG) Half-Word Select Position */
    149. 

  149. #define PORT_WRCONFIG_HWSEL_Msk               (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)                /**< (PORT_WRCONFIG) Half-Word Select Mask */
    150. 

  150. #define PORT_WRCONFIG_HWSEL(value)            (PORT_WRCONFIG_HWSEL_Msk & ((value) << PORT_WRCONFIG_HWSEL_Pos))
    151. 

  151. #define PORT_WRCONFIG_Msk                     _U_(0xDF47FFFF)                                      /**< (PORT_WRCONFIG) Register Mask  */
    152. 

  152. 

  153. 

  154. /* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) Peripheral Multiplexing n -------- */
    155. 

  155. #define PORT_PMUX_RESETVALUE                  _U_(0x00)                                            /**<  (PORT_PMUX) Peripheral Multiplexing n  Reset Value */
    156. 

  156. 

  157. #define PORT_PMUX_PMUXE_Pos                   _U_(0)                                               /**< (PORT_PMUX) Peripheral Multiplexing Even Position */
    158. 

  158. #define PORT_PMUX_PMUXE_Msk                   (_U_(0xF) << PORT_PMUX_PMUXE_Pos)                    /**< (PORT_PMUX) Peripheral Multiplexing Even Mask */
    159. 

  159. #define PORT_PMUX_PMUXE(value)                (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
    160. 

  160. #define   PORT_PMUX_PMUXE_A_Val               _U_(0x0)                                             /**< (PORT_PMUX) Peripheral function A selected  */
    161. 

  161. #define   PORT_PMUX_PMUXE_B_Val               _U_(0x1)                                             /**< (PORT_PMUX) Peripheral function B selected  */
    162. 

  162. #define   PORT_PMUX_PMUXE_C_Val               _U_(0x2)                                             /**< (PORT_PMUX) Peripheral function C selected  */
    163. 

  163. #define   PORT_PMUX_PMUXE_D_Val               _U_(0x3)                                             /**< (PORT_PMUX) Peripheral function D selected  */
    164. 

  164. #define   PORT_PMUX_PMUXE_E_Val               _U_(0x4)                                             /**< (PORT_PMUX) Peripheral function E selected  */
    165. 

  165. #define   PORT_PMUX_PMUXE_F_Val               _U_(0x5)                                             /**< (PORT_PMUX) Peripheral function F selected  */
    166. 

  166. #define   PORT_PMUX_PMUXE_G_Val               _U_(0x6)                                             /**< (PORT_PMUX) Peripheral function G selected  */
    167. 

  167. #define   PORT_PMUX_PMUXE_H_Val               _U_(0x7)                                             /**< (PORT_PMUX) Peripheral function H selected  */
    168. 

  168. #define PORT_PMUX_PMUXE_A                     (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function A selected Position  */
    169. 

  169. #define PORT_PMUX_PMUXE_B                     (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function B selected Position  */
    170. 

  170. #define PORT_PMUX_PMUXE_C                     (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function C selected Position  */
    171. 

  171. #define PORT_PMUX_PMUXE_D                     (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function D selected Position  */
    172. 

  172. #define PORT_PMUX_PMUXE_E                     (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function E selected Position  */
    173. 

  173. #define PORT_PMUX_PMUXE_F                     (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function F selected Position  */
    174. 

  174. #define PORT_PMUX_PMUXE_G                     (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function G selected Position  */
    175. 

  175. #define PORT_PMUX_PMUXE_H                     (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)       /**< (PORT_PMUX) Peripheral function H selected Position  */
    176. 

  176. #define PORT_PMUX_PMUXO_Pos                   _U_(4)                                               /**< (PORT_PMUX) Peripheral Multiplexing Odd Position */
    177. 

  177. #define PORT_PMUX_PMUXO_Msk                   (_U_(0xF) << PORT_PMUX_PMUXO_Pos)                    /**< (PORT_PMUX) Peripheral Multiplexing Odd Mask */
    178. 

  178. #define PORT_PMUX_PMUXO(value)                (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
    179. 

  179. #define   PORT_PMUX_PMUXO_A_Val               _U_(0x0)                                             /**< (PORT_PMUX) Peripheral function A selected  */
    180. 

  180. #define   PORT_PMUX_PMUXO_B_Val               _U_(0x1)                                             /**< (PORT_PMUX) Peripheral function B selected  */
    181. 

  181. #define   PORT_PMUX_PMUXO_C_Val               _U_(0x2)                                             /**< (PORT_PMUX) Peripheral function C selected  */
    182. 

  182. #define   PORT_PMUX_PMUXO_D_Val               _U_(0x3)                                             /**< (PORT_PMUX) Peripheral function D selected  */
    183. 

  183. #define   PORT_PMUX_PMUXO_E_Val               _U_(0x4)                                             /**< (PORT_PMUX) Peripheral function E selected  */
    184. 

  184. #define   PORT_PMUX_PMUXO_F_Val               _U_(0x5)                                             /**< (PORT_PMUX) Peripheral function F selected  */
    185. 

  185. #define   PORT_PMUX_PMUXO_G_Val               _U_(0x6)                                             /**< (PORT_PMUX) Peripheral function G selected  */
    186. 

  186. #define   PORT_PMUX_PMUXO_H_Val               _U_(0x7)                                             /**< (PORT_PMUX) Peripheral function H selected  */
    187. 

  187. #define PORT_PMUX_PMUXO_A                     (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function A selected Position  */
    188. 

  188. #define PORT_PMUX_PMUXO_B                     (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function B selected Position  */
    189. 

  189. #define PORT_PMUX_PMUXO_C                     (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function C selected Position  */
    190. 

  190. #define PORT_PMUX_PMUXO_D                     (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function D selected Position  */
    191. 

  191. #define PORT_PMUX_PMUXO_E                     (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function E selected Position  */
    192. 

  192. #define PORT_PMUX_PMUXO_F                     (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function F selected Position  */
    193. 

  193. #define PORT_PMUX_PMUXO_G                     (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function G selected Position  */
    194. 

  194. #define PORT_PMUX_PMUXO_H                     (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)       /**< (PORT_PMUX) Peripheral function H selected Position  */
    195. 

  195. #define PORT_PMUX_Msk                         _U_(0xFF)                                            /**< (PORT_PMUX) Register Mask  */
    196. 

  196. 

  197. 

  198. /* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) Pin Configuration n -------- */
    199. 

  199. #define PORT_PINCFG_RESETVALUE                _U_(0x00)                                            /**<  (PORT_PINCFG) Pin Configuration n  Reset Value */
    200. 

  200. 

  201. #define PORT_PINCFG_PMUXEN_Pos                _U_(0)                                               /**< (PORT_PINCFG) Peripheral Multiplexer Enable Position */
    202. 

  202. #define PORT_PINCFG_PMUXEN_Msk                (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)                 /**< (PORT_PINCFG) Peripheral Multiplexer Enable Mask */
    203. 

  203. #define PORT_PINCFG_PMUXEN(value)             (PORT_PINCFG_PMUXEN_Msk & ((value) << PORT_PINCFG_PMUXEN_Pos))
    204. 

  204. #define PORT_PINCFG_INEN_Pos                  _U_(1)                                               /**< (PORT_PINCFG) Input Enable Position */
    205. 

  205. #define PORT_PINCFG_INEN_Msk                  (_U_(0x1) << PORT_PINCFG_INEN_Pos)                   /**< (PORT_PINCFG) Input Enable Mask */
    206. 

  206. #define PORT_PINCFG_INEN(value)               (PORT_PINCFG_INEN_Msk & ((value) << PORT_PINCFG_INEN_Pos))
    207. 

  207. #define PORT_PINCFG_PULLEN_Pos                _U_(2)                                               /**< (PORT_PINCFG) Pull Enable Position */
    208. 

  208. #define PORT_PINCFG_PULLEN_Msk                (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)                 /**< (PORT_PINCFG) Pull Enable Mask */
    209. 

  209. #define PORT_PINCFG_PULLEN(value)             (PORT_PINCFG_PULLEN_Msk & ((value) << PORT_PINCFG_PULLEN_Pos))
    210. 

  210. #define PORT_PINCFG_DRVSTR_Pos                _U_(6)                                               /**< (PORT_PINCFG) Output Driver Strength Selection Position */
    211. 

  211. #define PORT_PINCFG_DRVSTR_Msk                (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)                 /**< (PORT_PINCFG) Output Driver Strength Selection Mask */
    212. 

  212. #define PORT_PINCFG_DRVSTR(value)             (PORT_PINCFG_DRVSTR_Msk & ((value) << PORT_PINCFG_DRVSTR_Pos))
    213. 

  213. #define PORT_PINCFG_Msk                       _U_(0x47)                                            /**< (PORT_PINCFG) Register Mask  */
    214. 

  214. 

  215. 

  216. /** \brief PORT register offsets definitions */
    217. 

  217. #define PORT_DIR_REG_OFST              (0x00)              /**< (PORT_DIR) Data Direction Offset */
    218. 

  218. #define PORT_DIRCLR_REG_OFST           (0x04)              /**< (PORT_DIRCLR) Data Direction Clear Offset */
    219. 

  219. #define PORT_DIRSET_REG_OFST           (0x08)              /**< (PORT_DIRSET) Data Direction Set Offset */
    220. 

  220. #define PORT_DIRTGL_REG_OFST           (0x0C)              /**< (PORT_DIRTGL) Data Direction Toggle Offset */
    221. 

  221. #define PORT_OUT_REG_OFST              (0x10)              /**< (PORT_OUT) Data Output Value Offset */
    222. 

  222. #define PORT_OUTCLR_REG_OFST           (0x14)              /**< (PORT_OUTCLR) Data Output Value Clear Offset */
    223. 

  223. #define PORT_OUTSET_REG_OFST           (0x18)              /**< (PORT_OUTSET) Data Output Value Set Offset */
    224. 

  224. #define PORT_OUTTGL_REG_OFST           (0x1C)              /**< (PORT_OUTTGL) Data Output Value Toggle Offset */
    225. 

  225. #define PORT_IN_REG_OFST               (0x20)              /**< (PORT_IN) Data Input Value Offset */
    226. 

  226. #define PORT_CTRL_REG_OFST             (0x24)              /**< (PORT_CTRL) Control Offset */
    227. 

  227. #define PORT_WRCONFIG_REG_OFST         (0x28)              /**< (PORT_WRCONFIG) Write Configuration Offset */
    228. 

  228. #define PORT_PMUX_REG_OFST             (0x30)              /**< (PORT_PMUX) Peripheral Multiplexing n Offset */
    229. 

  229. #define PORT_PMUX0_REG_OFST            (0x30)              /**< (PORT_PMUX0) Peripheral Multiplexing n Offset */
    230. 

  230. #define PORT_PMUX1_REG_OFST            (0x31)              /**< (PORT_PMUX1) Peripheral Multiplexing n Offset */
    231. 

  231. #define PORT_PMUX2_REG_OFST            (0x32)              /**< (PORT_PMUX2) Peripheral Multiplexing n Offset */
    232. 

  232. #define PORT_PMUX3_REG_OFST            (0x33)              /**< (PORT_PMUX3) Peripheral Multiplexing n Offset */
    233. 

  233. #define PORT_PMUX4_REG_OFST            (0x34)              /**< (PORT_PMUX4) Peripheral Multiplexing n Offset */
    234. 

  234. #define PORT_PMUX5_REG_OFST            (0x35)              /**< (PORT_PMUX5) Peripheral Multiplexing n Offset */
    235. 

  235. #define PORT_PMUX6_REG_OFST            (0x36)              /**< (PORT_PMUX6) Peripheral Multiplexing n Offset */
    236. 

  236. #define PORT_PMUX7_REG_OFST            (0x37)              /**< (PORT_PMUX7) Peripheral Multiplexing n Offset */
    237. 

  237. #define PORT_PMUX8_REG_OFST            (0x38)              /**< (PORT_PMUX8) Peripheral Multiplexing n Offset */
    238. 

  238. #define PORT_PMUX9_REG_OFST            (0x39)              /**< (PORT_PMUX9) Peripheral Multiplexing n Offset */
    239. 

  239. #define PORT_PMUX10_REG_OFST           (0x3A)              /**< (PORT_PMUX10) Peripheral Multiplexing n Offset */
    240. 

  240. #define PORT_PMUX11_REG_OFST           (0x3B)              /**< (PORT_PMUX11) Peripheral Multiplexing n Offset */
    241. 

  241. #define PORT_PMUX12_REG_OFST           (0x3C)              /**< (PORT_PMUX12) Peripheral Multiplexing n Offset */
    242. 

  242. #define PORT_PMUX13_REG_OFST           (0x3D)              /**< (PORT_PMUX13) Peripheral Multiplexing n Offset */
    243. 

  243. #define PORT_PMUX14_REG_OFST           (0x3E)              /**< (PORT_PMUX14) Peripheral Multiplexing n Offset */
    244. 

  244. #define PORT_PMUX15_REG_OFST           (0x3F)              /**< (PORT_PMUX15) Peripheral Multiplexing n Offset */
    245. 

  245. #define PORT_PINCFG_REG_OFST           (0x40)              /**< (PORT_PINCFG) Pin Configuration n Offset */
    246. 

  246. #define PORT_PINCFG0_REG_OFST          (0x40)              /**< (PORT_PINCFG0) Pin Configuration n Offset */
    247. 

  247. #define PORT_PINCFG1_REG_OFST          (0x41)              /**< (PORT_PINCFG1) Pin Configuration n Offset */
    248. 

  248. #define PORT_PINCFG2_REG_OFST          (0x42)              /**< (PORT_PINCFG2) Pin Configuration n Offset */
    249. 

  249. #define PORT_PINCFG3_REG_OFST          (0x43)              /**< (PORT_PINCFG3) Pin Configuration n Offset */
    250. 

  250. #define PORT_PINCFG4_REG_OFST          (0x44)              /**< (PORT_PINCFG4) Pin Configuration n Offset */
    251. 

  251. #define PORT_PINCFG5_REG_OFST          (0x45)              /**< (PORT_PINCFG5) Pin Configuration n Offset */
    252. 

  252. #define PORT_PINCFG6_REG_OFST          (0x46)              /**< (PORT_PINCFG6) Pin Configuration n Offset */
    253. 

  253. #define PORT_PINCFG7_REG_OFST          (0x47)              /**< (PORT_PINCFG7) Pin Configuration n Offset */
    254. 

  254. #define PORT_PINCFG8_REG_OFST          (0x48)              /**< (PORT_PINCFG8) Pin Configuration n Offset */
    255. 

  255. #define PORT_PINCFG9_REG_OFST          (0x49)              /**< (PORT_PINCFG9) Pin Configuration n Offset */
    256. 

  256. #define PORT_PINCFG10_REG_OFST         (0x4A)              /**< (PORT_PINCFG10) Pin Configuration n Offset */
    257. 

  257. #define PORT_PINCFG11_REG_OFST         (0x4B)              /**< (PORT_PINCFG11) Pin Configuration n Offset */
    258. 

  258. #define PORT_PINCFG12_REG_OFST         (0x4C)              /**< (PORT_PINCFG12) Pin Configuration n Offset */
    259. 

  259. #define PORT_PINCFG13_REG_OFST         (0x4D)              /**< (PORT_PINCFG13) Pin Configuration n Offset */
    260. 

  260. #define PORT_PINCFG14_REG_OFST         (0x4E)              /**< (PORT_PINCFG14) Pin Configuration n Offset */
    261. 

  261. #define PORT_PINCFG15_REG_OFST         (0x4F)              /**< (PORT_PINCFG15) Pin Configuration n Offset */
    262. 

  262. #define PORT_PINCFG16_REG_OFST         (0x50)              /**< (PORT_PINCFG16) Pin Configuration n Offset */
    263. 

  263. #define PORT_PINCFG17_REG_OFST         (0x51)              /**< (PORT_PINCFG17) Pin Configuration n Offset */
    264. 

  264. #define PORT_PINCFG18_REG_OFST         (0x52)              /**< (PORT_PINCFG18) Pin Configuration n Offset */
    265. 

  265. #define PORT_PINCFG19_REG_OFST         (0x53)              /**< (PORT_PINCFG19) Pin Configuration n Offset */
    266. 

  266. #define PORT_PINCFG20_REG_OFST         (0x54)              /**< (PORT_PINCFG20) Pin Configuration n Offset */
    267. 

  267. #define PORT_PINCFG21_REG_OFST         (0x55)              /**< (PORT_PINCFG21) Pin Configuration n Offset */
    268. 

  268. #define PORT_PINCFG22_REG_OFST         (0x56)              /**< (PORT_PINCFG22) Pin Configuration n Offset */
    269. 

  269. #define PORT_PINCFG23_REG_OFST         (0x57)              /**< (PORT_PINCFG23) Pin Configuration n Offset */
    270. 

  270. #define PORT_PINCFG24_REG_OFST         (0x58)              /**< (PORT_PINCFG24) Pin Configuration n Offset */
    271. 

  271. #define PORT_PINCFG25_REG_OFST         (0x59)              /**< (PORT_PINCFG25) Pin Configuration n Offset */
    272. 

  272. #define PORT_PINCFG26_REG_OFST         (0x5A)              /**< (PORT_PINCFG26) Pin Configuration n Offset */
    273. 

  273. #define PORT_PINCFG27_REG_OFST         (0x5B)              /**< (PORT_PINCFG27) Pin Configuration n Offset */
    274. 

  274. #define PORT_PINCFG28_REG_OFST         (0x5C)              /**< (PORT_PINCFG28) Pin Configuration n Offset */
    275. 

  275. #define PORT_PINCFG29_REG_OFST         (0x5D)              /**< (PORT_PINCFG29) Pin Configuration n Offset */
    276. 

  276. #define PORT_PINCFG30_REG_OFST         (0x5E)              /**< (PORT_PINCFG30) Pin Configuration n Offset */
    277. 

  277. #define PORT_PINCFG31_REG_OFST         (0x5F)              /**< (PORT_PINCFG31) Pin Configuration n Offset */
    278. 

  278. 

  279. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    280. 

  280. /** \brief GROUP register API structure */
    281. 

  281. typedef struct
    282. 

  282. {
    283. 

  283.   __IO  uint32_t                       PORT_DIR;           /**< Offset: 0x00 (R/W  32) Data Direction */
    284. 

  284.   __IO  uint32_t                       PORT_DIRCLR;        /**< Offset: 0x04 (R/W  32) Data Direction Clear */
    285. 

  285.   __IO  uint32_t                       PORT_DIRSET;        /**< Offset: 0x08 (R/W  32) Data Direction Set */
    286. 

  286.   __IO  uint32_t                       PORT_DIRTGL;        /**< Offset: 0x0C (R/W  32) Data Direction Toggle */
    287. 

  287.   __IO  uint32_t                       PORT_OUT;           /**< Offset: 0x10 (R/W  32) Data Output Value */
    288. 

  288.   __IO  uint32_t                       PORT_OUTCLR;        /**< Offset: 0x14 (R/W  32) Data Output Value Clear */
    289. 

  289.   __IO  uint32_t                       PORT_OUTSET;        /**< Offset: 0x18 (R/W  32) Data Output Value Set */
    290. 

  290.   __IO  uint32_t                       PORT_OUTTGL;        /**< Offset: 0x1C (R/W  32) Data Output Value Toggle */
    291. 

  291.   __I   uint32_t                       PORT_IN;            /**< Offset: 0x20 (R/   32) Data Input Value */
    292. 

  292.   __IO  uint32_t                       PORT_CTRL;          /**< Offset: 0x24 (R/W  32) Control */
    293. 

  293.   __O   uint32_t                       PORT_WRCONFIG;      /**< Offset: 0x28 ( /W  32) Write Configuration */
    294. 

  294.   __I   uint8_t                        Reserved1[0x04];
    295. 

  295.   __IO  uint8_t                        PORT_PMUX[16];      /**< Offset: 0x30 (R/W  8) Peripheral Multiplexing n */
    296. 

  296.   __IO  uint8_t                        PORT_PINCFG[32];    /**< Offset: 0x40 (R/W  8) Pin Configuration n */
    297. 

  297.   __I   uint8_t                        Reserved2[0x20];
    298. 

  298. } port_group_registers_t;
    299. 

  299. 

  300. #define PORT_GROUP_NUMBER _U_(2)
    301. 

  301. 

  302. /** \brief PORT register API structure */
    303. 

  303. typedef struct
    304. 

  304. {  /* Port Module */
    305. 

  305.         port_group_registers_t         GROUP[PORT_GROUP_NUMBER]; /**< Offset: 0x00  */
    306. 

  306. } port_registers_t;
    307. 

  307. 

  308. 

  309. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    310. 

  310. #endif /* _SAMD21_PORT_COMPONENT_H_ */
    311.