Home Explore Help
Sign In
FlyerInk
/
sdk-csp-atsamd21
mirror of https://github-proxy.rt-thread.io/FlyerInk/sdk-csp-atsamd21.git
2
0
Fork 0
Files Issues 0 Wiki
Branch: master
Branches Tags
sdk-csp-atsamd2...
/
libraries
/
include
/
component
/
sercom.h

sercom.h 233 KB
Permalink History Raw

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867 
  1. /**
    2. 

  2.  * \brief Component description for SERCOM
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_SERCOM_COMPONENT_H_
    25. 

  25. #define _SAMD21_SERCOM_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR SERCOM                                       */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM Control A -------- */
    32. 

  32. #define SERCOM_I2CM_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CM_CTRLA) I2CM Control A  Reset Value */
    33. 

  33. 

  34. #define SERCOM_I2CM_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_I2CM_CTRLA) Software Reset Position */
    35. 

  35. #define SERCOM_I2CM_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos)            /**< (SERCOM_I2CM_CTRLA) Software Reset Mask */
    36. 

  36. #define SERCOM_I2CM_CTRLA_SWRST(value)        (SERCOM_I2CM_CTRLA_SWRST_Msk & ((value) << SERCOM_I2CM_CTRLA_SWRST_Pos))
    37. 

  37. #define SERCOM_I2CM_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_I2CM_CTRLA) Enable Position */
    38. 

  38. #define SERCOM_I2CM_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos)           /**< (SERCOM_I2CM_CTRLA) Enable Mask */
    39. 

  39. #define SERCOM_I2CM_CTRLA_ENABLE(value)       (SERCOM_I2CM_CTRLA_ENABLE_Msk & ((value) << SERCOM_I2CM_CTRLA_ENABLE_Pos))
    40. 

  40. #define SERCOM_I2CM_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_I2CM_CTRLA) Operating Mode Position */
    41. 

  41. #define SERCOM_I2CM_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos)             /**< (SERCOM_I2CM_CTRLA) Operating Mode Mask */
    42. 

  42. #define SERCOM_I2CM_CTRLA_MODE(value)         (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos))
    43. 

  43. #define   SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) USART with external clock  */
    44. 

  44. #define   SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) USART with internal clock  */
    45. 

  45. #define   SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) SPI in slave operation  */
    46. 

  46. #define   SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_I2CM_CTRLA) SPI in master operation  */
    47. 

  47. #define   SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_I2CM_CTRLA) I2C slave operation  */
    48. 

  48. #define   SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_I2CM_CTRLA) I2C master operation  */
    49. 

  49. #define SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK  (SERCOM_I2CM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) USART with external clock Position  */
    50. 

  50. #define SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK  (SERCOM_I2CM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) USART with internal clock Position  */
    51. 

  51. #define SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE      (SERCOM_I2CM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) SPI in slave operation Position  */
    52. 

  52. #define SERCOM_I2CM_CTRLA_MODE_SPI_MASTER     (SERCOM_I2CM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) SPI in master operation Position  */
    53. 

  53. #define SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) I2C slave operation Position  */
    54. 

  54. #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CM_CTRLA_MODE_Pos) /**< (SERCOM_I2CM_CTRLA) I2C master operation Position  */
    55. 

  55. #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_I2CM_CTRLA) Run in Standby Position */
    56. 

  56. #define SERCOM_I2CM_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_I2CM_CTRLA) Run in Standby Mask */
    57. 

  57. #define SERCOM_I2CM_CTRLA_RUNSTDBY(value)     (SERCOM_I2CM_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos))
    58. 

  58. #define SERCOM_I2CM_CTRLA_PINOUT_Pos          _U_(16)                                              /**< (SERCOM_I2CM_CTRLA) Pin Usage Position */
    59. 

  59. #define SERCOM_I2CM_CTRLA_PINOUT_Msk          (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos)           /**< (SERCOM_I2CM_CTRLA) Pin Usage Mask */
    60. 

  60. #define SERCOM_I2CM_CTRLA_PINOUT(value)       (SERCOM_I2CM_CTRLA_PINOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_PINOUT_Pos))
    61. 

  61. #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos         _U_(20)                                              /**< (SERCOM_I2CM_CTRLA) SDA Hold Time Position */
    62. 

  62. #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk         (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)          /**< (SERCOM_I2CM_CTRLA) SDA Hold Time Mask */
    63. 

  63. #define SERCOM_I2CM_CTRLA_SDAHOLD(value)      (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos))
    64. 

  64. #define   SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) Disabled  */
    65. 

  65. #define   SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val  _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) 50-100ns hold time  */
    66. 

  66. #define   SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) 300-600ns hold time  */
    67. 

  67. #define   SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val _U_(0x3)                                             /**< (SERCOM_I2CM_CTRLA) 400-800ns hold time  */
    68. 

  68. #define SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE     (SERCOM_I2CM_CTRLA_SDAHOLD_DISABLE_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) Disabled Position  */
    69. 

  69. #define SERCOM_I2CM_CTRLA_SDAHOLD_75NS        (SERCOM_I2CM_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) 50-100ns hold time Position  */
    70. 

  70. #define SERCOM_I2CM_CTRLA_SDAHOLD_450NS       (SERCOM_I2CM_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) 300-600ns hold time Position  */
    71. 

  71. #define SERCOM_I2CM_CTRLA_SDAHOLD_600NS       (SERCOM_I2CM_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CM_CTRLA) 400-800ns hold time Position  */
    72. 

  72. #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos        _U_(22)                                              /**< (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Position */
    73. 

  73. #define SERCOM_I2CM_CTRLA_MEXTTOEN_Msk        (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos)         /**< (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout Mask */
    74. 

  74. #define SERCOM_I2CM_CTRLA_MEXTTOEN(value)     (SERCOM_I2CM_CTRLA_MEXTTOEN_Msk & ((value) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos))
    75. 

  75. #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos        _U_(23)                                              /**< (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Position */
    76. 

  76. #define SERCOM_I2CM_CTRLA_SEXTTOEN_Msk        (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos)         /**< (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout Mask */
    77. 

  77. #define SERCOM_I2CM_CTRLA_SEXTTOEN(value)     (SERCOM_I2CM_CTRLA_SEXTTOEN_Msk & ((value) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos))
    78. 

  78. #define SERCOM_I2CM_CTRLA_SPEED_Pos           _U_(24)                                              /**< (SERCOM_I2CM_CTRLA) Transfer Speed Position */
    79. 

  79. #define SERCOM_I2CM_CTRLA_SPEED_Msk           (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos)            /**< (SERCOM_I2CM_CTRLA) Transfer Speed Mask */
    80. 

  80. #define SERCOM_I2CM_CTRLA_SPEED(value)        (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos))
    81. 

  81. #define   SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz   */
    82. 

  82. #define   SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) Fast-mode Plus Upto 1MHz  */
    83. 

  83. #define   SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) High-speed mode Upto 3.4MHz  */
    84. 

  84. #define SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE (SERCOM_I2CM_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /**< (SERCOM_I2CM_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz  Position  */
    85. 

  85. #define SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE (SERCOM_I2CM_CTRLA_SPEED_FASTPLUS_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /**< (SERCOM_I2CM_CTRLA) Fast-mode Plus Upto 1MHz Position  */
    86. 

  86. #define SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE (SERCOM_I2CM_CTRLA_SPEED_HIGH_SPEED_MODE_Val << SERCOM_I2CM_CTRLA_SPEED_Pos) /**< (SERCOM_I2CM_CTRLA) High-speed mode Upto 3.4MHz Position  */
    87. 

  87. #define SERCOM_I2CM_CTRLA_SCLSM_Pos           _U_(27)                                              /**< (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Position */
    88. 

  88. #define SERCOM_I2CM_CTRLA_SCLSM_Msk           (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos)            /**< (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode Mask */
    89. 

  89. #define SERCOM_I2CM_CTRLA_SCLSM(value)        (SERCOM_I2CM_CTRLA_SCLSM_Msk & ((value) << SERCOM_I2CM_CTRLA_SCLSM_Pos))
    90. 

  90. #define SERCOM_I2CM_CTRLA_INACTOUT_Pos        _U_(28)                                              /**< (SERCOM_I2CM_CTRLA) Inactive Time-Out Position */
    91. 

  91. #define SERCOM_I2CM_CTRLA_INACTOUT_Msk        (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)         /**< (SERCOM_I2CM_CTRLA) Inactive Time-Out Mask */
    92. 

  92. #define SERCOM_I2CM_CTRLA_INACTOUT(value)     (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos))
    93. 

  93. #define   SERCOM_I2CM_CTRLA_INACTOUT_DISABLE_Val _U_(0x0)                                             /**< (SERCOM_I2CM_CTRLA) Disabled  */
    94. 

  94. #define   SERCOM_I2CM_CTRLA_INACTOUT_55US_Val _U_(0x1)                                             /**< (SERCOM_I2CM_CTRLA) 5-6 SCL Time-Out(50-60us)  */
    95. 

  95. #define   SERCOM_I2CM_CTRLA_INACTOUT_105US_Val _U_(0x2)                                             /**< (SERCOM_I2CM_CTRLA) 10-11 SCL Time-Out(100-110us)  */
    96. 

  96. #define   SERCOM_I2CM_CTRLA_INACTOUT_205US_Val _U_(0x3)                                             /**< (SERCOM_I2CM_CTRLA) 20-21 SCL Time-Out(200-210us)  */
    97. 

  97. #define SERCOM_I2CM_CTRLA_INACTOUT_DISABLE    (SERCOM_I2CM_CTRLA_INACTOUT_DISABLE_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) Disabled Position  */
    98. 

  98. #define SERCOM_I2CM_CTRLA_INACTOUT_55US       (SERCOM_I2CM_CTRLA_INACTOUT_55US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) 5-6 SCL Time-Out(50-60us) Position  */
    99. 

  99. #define SERCOM_I2CM_CTRLA_INACTOUT_105US      (SERCOM_I2CM_CTRLA_INACTOUT_105US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) 10-11 SCL Time-Out(100-110us) Position  */
    100. 

  100. #define SERCOM_I2CM_CTRLA_INACTOUT_205US      (SERCOM_I2CM_CTRLA_INACTOUT_205US_Val << SERCOM_I2CM_CTRLA_INACTOUT_Pos) /**< (SERCOM_I2CM_CTRLA) 20-21 SCL Time-Out(200-210us) Position  */
    101. 

  101. #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos       _U_(30)                                              /**< (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Position */
    102. 

  102. #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk       (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos)        /**< (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable Mask */
    103. 

  103. #define SERCOM_I2CM_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CM_CTRLA_LOWTOUTEN_Msk & ((value) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos))
    104. 

  104. #define SERCOM_I2CM_CTRLA_Msk                 _U_(0x7BF1009F)                                      /**< (SERCOM_I2CM_CTRLA) Register Mask  */
    105. 

  105. 

  106. 

  107. /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS Control A -------- */
    108. 

  108. #define SERCOM_I2CS_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CS_CTRLA) I2CS Control A  Reset Value */
    109. 

  109. 

  110. #define SERCOM_I2CS_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_I2CS_CTRLA) Software Reset Position */
    111. 

  111. #define SERCOM_I2CS_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos)            /**< (SERCOM_I2CS_CTRLA) Software Reset Mask */
    112. 

  112. #define SERCOM_I2CS_CTRLA_SWRST(value)        (SERCOM_I2CS_CTRLA_SWRST_Msk & ((value) << SERCOM_I2CS_CTRLA_SWRST_Pos))
    113. 

  113. #define SERCOM_I2CS_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_I2CS_CTRLA) Enable Position */
    114. 

  114. #define SERCOM_I2CS_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos)           /**< (SERCOM_I2CS_CTRLA) Enable Mask */
    115. 

  115. #define SERCOM_I2CS_CTRLA_ENABLE(value)       (SERCOM_I2CS_CTRLA_ENABLE_Msk & ((value) << SERCOM_I2CS_CTRLA_ENABLE_Pos))
    116. 

  116. #define SERCOM_I2CS_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_I2CS_CTRLA) Operating Mode Position */
    117. 

  117. #define SERCOM_I2CS_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos)             /**< (SERCOM_I2CS_CTRLA) Operating Mode Mask */
    118. 

  118. #define SERCOM_I2CS_CTRLA_MODE(value)         (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos))
    119. 

  119. #define   SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLA) USART with external clock  */
    120. 

  120. #define   SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLA) USART with internal clock  */
    121. 

  121. #define   SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_I2CS_CTRLA) SPI in slave operation  */
    122. 

  122. #define   SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_I2CS_CTRLA) SPI in master operation  */
    123. 

  123. #define   SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_I2CS_CTRLA) I2C slave operation  */
    124. 

  124. #define   SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_I2CS_CTRLA) I2C master operation  */
    125. 

  125. #define SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK  (SERCOM_I2CS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) USART with external clock Position  */
    126. 

  126. #define SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK  (SERCOM_I2CS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) USART with internal clock Position  */
    127. 

  127. #define SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE      (SERCOM_I2CS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) SPI in slave operation Position  */
    128. 

  128. #define SERCOM_I2CS_CTRLA_MODE_SPI_MASTER     (SERCOM_I2CS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) SPI in master operation Position  */
    129. 

  129. #define SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE      (SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) I2C slave operation Position  */
    130. 

  130. #define SERCOM_I2CS_CTRLA_MODE_I2C_MASTER     (SERCOM_I2CS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_I2CS_CTRLA_MODE_Pos) /**< (SERCOM_I2CS_CTRLA) I2C master operation Position  */
    131. 

  131. #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_I2CS_CTRLA) Run during Standby Position */
    132. 

  132. #define SERCOM_I2CS_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_I2CS_CTRLA) Run during Standby Mask */
    133. 

  133. #define SERCOM_I2CS_CTRLA_RUNSTDBY(value)     (SERCOM_I2CS_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos))
    134. 

  134. #define SERCOM_I2CS_CTRLA_PINOUT_Pos          _U_(16)                                              /**< (SERCOM_I2CS_CTRLA) Pin Usage Position */
    135. 

  135. #define SERCOM_I2CS_CTRLA_PINOUT_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos)           /**< (SERCOM_I2CS_CTRLA) Pin Usage Mask */
    136. 

  136. #define SERCOM_I2CS_CTRLA_PINOUT(value)       (SERCOM_I2CS_CTRLA_PINOUT_Msk & ((value) << SERCOM_I2CS_CTRLA_PINOUT_Pos))
    137. 

  137. #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos         _U_(20)                                              /**< (SERCOM_I2CS_CTRLA) SDA Hold Time Position */
    138. 

  138. #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk         (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)          /**< (SERCOM_I2CS_CTRLA) SDA Hold Time Mask */
    139. 

  139. #define SERCOM_I2CS_CTRLA_SDAHOLD(value)      (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))
    140. 

  140. #define   SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLA) Disabled  */
    141. 

  141. #define   SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val  _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLA) 50-100ns hold time  */
    142. 

  142. #define   SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val _U_(0x2)                                             /**< (SERCOM_I2CS_CTRLA) 300-600ns hold time  */
    143. 

  143. #define   SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val _U_(0x3)                                             /**< (SERCOM_I2CS_CTRLA) 400-800ns hold time  */
    144. 

  144. #define SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE     (SERCOM_I2CS_CTRLA_SDAHOLD_DISABLE_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) Disabled Position  */
    145. 

  145. #define SERCOM_I2CS_CTRLA_SDAHOLD_75NS        (SERCOM_I2CS_CTRLA_SDAHOLD_75NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) 50-100ns hold time Position  */
    146. 

  146. #define SERCOM_I2CS_CTRLA_SDAHOLD_450NS       (SERCOM_I2CS_CTRLA_SDAHOLD_450NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) 300-600ns hold time Position  */
    147. 

  147. #define SERCOM_I2CS_CTRLA_SDAHOLD_600NS       (SERCOM_I2CS_CTRLA_SDAHOLD_600NS_Val << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) /**< (SERCOM_I2CS_CTRLA) 400-800ns hold time Position  */
    148. 

  148. #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos        _U_(23)                                              /**< (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Position */
    149. 

  149. #define SERCOM_I2CS_CTRLA_SEXTTOEN_Msk        (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)         /**< (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout Mask */
    150. 

  150. #define SERCOM_I2CS_CTRLA_SEXTTOEN(value)     (SERCOM_I2CS_CTRLA_SEXTTOEN_Msk & ((value) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos))
    151. 

  151. #define SERCOM_I2CS_CTRLA_SPEED_Pos           _U_(24)                                              /**< (SERCOM_I2CS_CTRLA) Transfer Speed Position */
    152. 

  152. #define SERCOM_I2CS_CTRLA_SPEED_Msk           (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos)            /**< (SERCOM_I2CS_CTRLA) Transfer Speed Mask */
    153. 

  153. #define SERCOM_I2CS_CTRLA_SPEED(value)        (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos))
    154. 

  154. #define   SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val _U_(0x0)                                             /**< (SERCOM_I2CS_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz   */
    155. 

  155. #define   SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE_Val _U_(0x1)                                             /**< (SERCOM_I2CS_CTRLA) Fast-mode Plus Upto 1MHz  */
    156. 

  156. #define   SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE_Val _U_(0x2)                                             /**< (SERCOM_I2CS_CTRLA) High-speed mode Upto 3.4MHz  */
    157. 

  157. #define SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE (SERCOM_I2CS_CTRLA_SPEED_STANDARD_AND_FAST_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /**< (SERCOM_I2CS_CTRLA) Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz  Position  */
    158. 

  158. #define SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE (SERCOM_I2CS_CTRLA_SPEED_FASTPLUS_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /**< (SERCOM_I2CS_CTRLA) Fast-mode Plus Upto 1MHz Position  */
    159. 

  159. #define SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE (SERCOM_I2CS_CTRLA_SPEED_HIGH_SPEED_MODE_Val << SERCOM_I2CS_CTRLA_SPEED_Pos) /**< (SERCOM_I2CS_CTRLA) High-speed mode Upto 3.4MHz Position  */
    160. 

  160. #define SERCOM_I2CS_CTRLA_SCLSM_Pos           _U_(27)                                              /**< (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Position */
    161. 

  161. #define SERCOM_I2CS_CTRLA_SCLSM_Msk           (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos)            /**< (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode Mask */
    162. 

  162. #define SERCOM_I2CS_CTRLA_SCLSM(value)        (SERCOM_I2CS_CTRLA_SCLSM_Msk & ((value) << SERCOM_I2CS_CTRLA_SCLSM_Pos))
    163. 

  163. #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos       _U_(30)                                              /**< (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Position */
    164. 

  164. #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk       (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos)        /**< (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable Mask */
    165. 

  165. #define SERCOM_I2CS_CTRLA_LOWTOUTEN(value)    (SERCOM_I2CS_CTRLA_LOWTOUTEN_Msk & ((value) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos))
    166. 

  166. #define SERCOM_I2CS_CTRLA_Msk                 _U_(0x4BB1009F)                                      /**< (SERCOM_I2CS_CTRLA) Register Mask  */
    167. 

  167. 

  168. 

  169. /* -------- SERCOM_SPIM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPIM Control A -------- */
    170. 

  170. #define SERCOM_SPIM_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIM_CTRLA) SPIM Control A  Reset Value */
    171. 

  171. 

  172. #define SERCOM_SPIM_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_SPIM_CTRLA) Software Reset Position */
    173. 

  173. #define SERCOM_SPIM_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_SPIM_CTRLA_SWRST_Pos)            /**< (SERCOM_SPIM_CTRLA) Software Reset Mask */
    174. 

  174. #define SERCOM_SPIM_CTRLA_SWRST(value)        (SERCOM_SPIM_CTRLA_SWRST_Msk & ((value) << SERCOM_SPIM_CTRLA_SWRST_Pos))
    175. 

  175. #define SERCOM_SPIM_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_SPIM_CTRLA) Enable Position */
    176. 

  176. #define SERCOM_SPIM_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_SPIM_CTRLA_ENABLE_Pos)           /**< (SERCOM_SPIM_CTRLA) Enable Mask */
    177. 

  177. #define SERCOM_SPIM_CTRLA_ENABLE(value)       (SERCOM_SPIM_CTRLA_ENABLE_Msk & ((value) << SERCOM_SPIM_CTRLA_ENABLE_Pos))
    178. 

  178. #define SERCOM_SPIM_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_SPIM_CTRLA) Operating Mode Position */
    179. 

  179. #define SERCOM_SPIM_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_SPIM_CTRLA_MODE_Pos)             /**< (SERCOM_SPIM_CTRLA) Operating Mode Mask */
    180. 

  180. #define SERCOM_SPIM_CTRLA_MODE(value)         (SERCOM_SPIM_CTRLA_MODE_Msk & ((value) << SERCOM_SPIM_CTRLA_MODE_Pos))
    181. 

  181. #define   SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) USART with external clock  */
    182. 

  182. #define   SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) USART with internal clock  */
    183. 

  183. #define   SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) SPI in slave operation  */
    184. 

  184. #define   SERCOM_SPIM_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_SPIM_CTRLA) SPI in master operation  */
    185. 

  185. #define   SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_SPIM_CTRLA) I2C slave operation  */
    186. 

  186. #define   SERCOM_SPIM_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_SPIM_CTRLA) I2C master operation  */
    187. 

  187. #define SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK  (SERCOM_SPIM_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) USART with external clock Position  */
    188. 

  188. #define SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK  (SERCOM_SPIM_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) USART with internal clock Position  */
    189. 

  189. #define SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE      (SERCOM_SPIM_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) SPI in slave operation Position  */
    190. 

  190. #define SERCOM_SPIM_CTRLA_MODE_SPI_MASTER     (SERCOM_SPIM_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) SPI in master operation Position  */
    191. 

  191. #define SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE      (SERCOM_SPIM_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) I2C slave operation Position  */
    192. 

  192. #define SERCOM_SPIM_CTRLA_MODE_I2C_MASTER     (SERCOM_SPIM_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPIM_CTRLA_MODE_Pos) /**< (SERCOM_SPIM_CTRLA) I2C master operation Position  */
    193. 

  193. #define SERCOM_SPIM_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_SPIM_CTRLA) Run during Standby Position */
    194. 

  194. #define SERCOM_SPIM_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_SPIM_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_SPIM_CTRLA) Run during Standby Mask */
    195. 

  195. #define SERCOM_SPIM_CTRLA_RUNSTDBY(value)     (SERCOM_SPIM_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_SPIM_CTRLA_RUNSTDBY_Pos))
    196. 

  196. #define SERCOM_SPIM_CTRLA_IBON_Pos            _U_(8)                                               /**< (SERCOM_SPIM_CTRLA) Immediate Buffer Overflow Notification Position */
    197. 

  197. #define SERCOM_SPIM_CTRLA_IBON_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_IBON_Pos)             /**< (SERCOM_SPIM_CTRLA) Immediate Buffer Overflow Notification Mask */
    198. 

  198. #define SERCOM_SPIM_CTRLA_IBON(value)         (SERCOM_SPIM_CTRLA_IBON_Msk & ((value) << SERCOM_SPIM_CTRLA_IBON_Pos))
    199. 

  199. #define SERCOM_SPIM_CTRLA_DOPO_Pos            _U_(16)                                              /**< (SERCOM_SPIM_CTRLA) Data Out Pinout Position */
    200. 

  200. #define SERCOM_SPIM_CTRLA_DOPO_Msk            (_U_(0x3) << SERCOM_SPIM_CTRLA_DOPO_Pos)             /**< (SERCOM_SPIM_CTRLA) Data Out Pinout Mask */
    201. 

  201. #define SERCOM_SPIM_CTRLA_DOPO(value)         (SERCOM_SPIM_CTRLA_DOPO_Msk & ((value) << SERCOM_SPIM_CTRLA_DOPO_Pos))
    202. 

  202. #define   SERCOM_SPIM_CTRLA_DOPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
    203. 

  203. #define   SERCOM_SPIM_CTRLA_DOPO_PAD1_Val     _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) DO on PAD[2], SCK on PAD[3] and SS on PAD[1]  */
    204. 

  204. #define   SERCOM_SPIM_CTRLA_DOPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
    205. 

  205. #define   SERCOM_SPIM_CTRLA_DOPO_PAD3_Val     _U_(0x3)                                             /**< (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[3] and SS on PAD[1]  */
    206. 

  206. #define SERCOM_SPIM_CTRLA_DOPO_PAD0           (SERCOM_SPIM_CTRLA_DOPO_PAD0_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /**< (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position  */
    207. 

  207. #define SERCOM_SPIM_CTRLA_DOPO_PAD1           (SERCOM_SPIM_CTRLA_DOPO_PAD1_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /**< (SERCOM_SPIM_CTRLA) DO on PAD[2], SCK on PAD[3] and SS on PAD[1] Position  */
    208. 

  208. #define SERCOM_SPIM_CTRLA_DOPO_PAD2           (SERCOM_SPIM_CTRLA_DOPO_PAD2_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /**< (SERCOM_SPIM_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position  */
    209. 

  209. #define SERCOM_SPIM_CTRLA_DOPO_PAD3           (SERCOM_SPIM_CTRLA_DOPO_PAD3_Val << SERCOM_SPIM_CTRLA_DOPO_Pos) /**< (SERCOM_SPIM_CTRLA) DO on PAD[0], SCK on PAD[3] and SS on PAD[1] Position  */
    210. 

  210. #define SERCOM_SPIM_CTRLA_DIPO_Pos            _U_(20)                                              /**< (SERCOM_SPIM_CTRLA) Data In Pinout Position */
    211. 

  211. #define SERCOM_SPIM_CTRLA_DIPO_Msk            (_U_(0x3) << SERCOM_SPIM_CTRLA_DIPO_Pos)             /**< (SERCOM_SPIM_CTRLA) Data In Pinout Mask */
    212. 

  212. #define SERCOM_SPIM_CTRLA_DIPO(value)         (SERCOM_SPIM_CTRLA_DIPO_Msk & ((value) << SERCOM_SPIM_CTRLA_DIPO_Pos))
    213. 

  213. #define   SERCOM_SPIM_CTRLA_DIPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[0]  */
    214. 

  214. #define   SERCOM_SPIM_CTRLA_DIPO_PAD1_Val     _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[1]  */
    215. 

  215. #define   SERCOM_SPIM_CTRLA_DIPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[2]  */
    216. 

  216. #define   SERCOM_SPIM_CTRLA_DIPO_PAD3_Val     _U_(0x3)                                             /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[3]  */
    217. 

  217. #define SERCOM_SPIM_CTRLA_DIPO_PAD0           (SERCOM_SPIM_CTRLA_DIPO_PAD0_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[0] Position  */
    218. 

  218. #define SERCOM_SPIM_CTRLA_DIPO_PAD1           (SERCOM_SPIM_CTRLA_DIPO_PAD1_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[1] Position  */
    219. 

  219. #define SERCOM_SPIM_CTRLA_DIPO_PAD2           (SERCOM_SPIM_CTRLA_DIPO_PAD2_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[2] Position  */
    220. 

  220. #define SERCOM_SPIM_CTRLA_DIPO_PAD3           (SERCOM_SPIM_CTRLA_DIPO_PAD3_Val << SERCOM_SPIM_CTRLA_DIPO_Pos) /**< (SERCOM_SPIM_CTRLA) SERCOM PAD[3] Position  */
    221. 

  221. #define SERCOM_SPIM_CTRLA_FORM_Pos            _U_(24)                                              /**< (SERCOM_SPIM_CTRLA) Frame Format Position */
    222. 

  222. #define SERCOM_SPIM_CTRLA_FORM_Msk            (_U_(0xF) << SERCOM_SPIM_CTRLA_FORM_Pos)             /**< (SERCOM_SPIM_CTRLA) Frame Format Mask */
    223. 

  223. #define SERCOM_SPIM_CTRLA_FORM(value)         (SERCOM_SPIM_CTRLA_FORM_Msk & ((value) << SERCOM_SPIM_CTRLA_FORM_Pos))
    224. 

  224. #define   SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) SPI Frame  */
    225. 

  225. #define   SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLA) SPI Frame with Addr  */
    226. 

  226. #define SERCOM_SPIM_CTRLA_FORM_SPI_FRAME      (SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_Val << SERCOM_SPIM_CTRLA_FORM_Pos) /**< (SERCOM_SPIM_CTRLA) SPI Frame Position  */
    227. 

  227. #define SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR (SERCOM_SPIM_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val << SERCOM_SPIM_CTRLA_FORM_Pos) /**< (SERCOM_SPIM_CTRLA) SPI Frame with Addr Position  */
    228. 

  228. #define SERCOM_SPIM_CTRLA_CPHA_Pos            _U_(28)                                              /**< (SERCOM_SPIM_CTRLA) Clock Phase Position */
    229. 

  229. #define SERCOM_SPIM_CTRLA_CPHA_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_CPHA_Pos)             /**< (SERCOM_SPIM_CTRLA) Clock Phase Mask */
    230. 

  230. #define SERCOM_SPIM_CTRLA_CPHA(value)         (SERCOM_SPIM_CTRLA_CPHA_Msk & ((value) << SERCOM_SPIM_CTRLA_CPHA_Pos))
    231. 

  231. #define   SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
    232. 

  232. #define   SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
    233. 

  233. #define SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE   (SERCOM_SPIM_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPIM_CTRLA_CPHA_Pos) /**< (SERCOM_SPIM_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position  */
    234. 

  234. #define SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE  (SERCOM_SPIM_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPIM_CTRLA_CPHA_Pos) /**< (SERCOM_SPIM_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position  */
    235. 

  235. #define SERCOM_SPIM_CTRLA_CPOL_Pos            _U_(29)                                              /**< (SERCOM_SPIM_CTRLA) Clock Polarity Position */
    236. 

  236. #define SERCOM_SPIM_CTRLA_CPOL_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_CPOL_Pos)             /**< (SERCOM_SPIM_CTRLA) Clock Polarity Mask */
    237. 

  237. #define SERCOM_SPIM_CTRLA_CPOL(value)         (SERCOM_SPIM_CTRLA_CPOL_Msk & ((value) << SERCOM_SPIM_CTRLA_CPOL_Pos))
    238. 

  238. #define   SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) SCK is low when idle  */
    239. 

  239. #define   SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) SCK is high when idle  */
    240. 

  240. #define SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW       (SERCOM_SPIM_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_SPIM_CTRLA_CPOL_Pos) /**< (SERCOM_SPIM_CTRLA) SCK is low when idle Position  */
    241. 

  241. #define SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH      (SERCOM_SPIM_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_SPIM_CTRLA_CPOL_Pos) /**< (SERCOM_SPIM_CTRLA) SCK is high when idle Position  */
    242. 

  242. #define SERCOM_SPIM_CTRLA_DORD_Pos            _U_(30)                                              /**< (SERCOM_SPIM_CTRLA) Data Order Position */
    243. 

  243. #define SERCOM_SPIM_CTRLA_DORD_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLA_DORD_Pos)             /**< (SERCOM_SPIM_CTRLA) Data Order Mask */
    244. 

  244. #define SERCOM_SPIM_CTRLA_DORD(value)         (SERCOM_SPIM_CTRLA_DORD_Msk & ((value) << SERCOM_SPIM_CTRLA_DORD_Pos))
    245. 

  245. #define   SERCOM_SPIM_CTRLA_DORD_MSB_Val      _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLA) MSB is transferred first  */
    246. 

  246. #define   SERCOM_SPIM_CTRLA_DORD_LSB_Val      _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLA) LSB is transferred first  */
    247. 

  247. #define SERCOM_SPIM_CTRLA_DORD_MSB            (SERCOM_SPIM_CTRLA_DORD_MSB_Val << SERCOM_SPIM_CTRLA_DORD_Pos) /**< (SERCOM_SPIM_CTRLA) MSB is transferred first Position  */
    248. 

  248. #define SERCOM_SPIM_CTRLA_DORD_LSB            (SERCOM_SPIM_CTRLA_DORD_LSB_Val << SERCOM_SPIM_CTRLA_DORD_Pos) /**< (SERCOM_SPIM_CTRLA) LSB is transferred first Position  */
    249. 

  249. #define SERCOM_SPIM_CTRLA_Msk                 _U_(0x7F33019F)                                      /**< (SERCOM_SPIM_CTRLA) Register Mask  */
    250. 

  250. 

  251. 

  252. /* -------- SERCOM_SPIS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPIS Control A -------- */
    253. 

  253. #define SERCOM_SPIS_CTRLA_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIS_CTRLA) SPIS Control A  Reset Value */
    254. 

  254. 

  255. #define SERCOM_SPIS_CTRLA_SWRST_Pos           _U_(0)                                               /**< (SERCOM_SPIS_CTRLA) Software Reset Position */
    256. 

  256. #define SERCOM_SPIS_CTRLA_SWRST_Msk           (_U_(0x1) << SERCOM_SPIS_CTRLA_SWRST_Pos)            /**< (SERCOM_SPIS_CTRLA) Software Reset Mask */
    257. 

  257. #define SERCOM_SPIS_CTRLA_SWRST(value)        (SERCOM_SPIS_CTRLA_SWRST_Msk & ((value) << SERCOM_SPIS_CTRLA_SWRST_Pos))
    258. 

  258. #define SERCOM_SPIS_CTRLA_ENABLE_Pos          _U_(1)                                               /**< (SERCOM_SPIS_CTRLA) Enable Position */
    259. 

  259. #define SERCOM_SPIS_CTRLA_ENABLE_Msk          (_U_(0x1) << SERCOM_SPIS_CTRLA_ENABLE_Pos)           /**< (SERCOM_SPIS_CTRLA) Enable Mask */
    260. 

  260. #define SERCOM_SPIS_CTRLA_ENABLE(value)       (SERCOM_SPIS_CTRLA_ENABLE_Msk & ((value) << SERCOM_SPIS_CTRLA_ENABLE_Pos))
    261. 

  261. #define SERCOM_SPIS_CTRLA_MODE_Pos            _U_(2)                                               /**< (SERCOM_SPIS_CTRLA) Operating Mode Position */
    262. 

  262. #define SERCOM_SPIS_CTRLA_MODE_Msk            (_U_(0x7) << SERCOM_SPIS_CTRLA_MODE_Pos)             /**< (SERCOM_SPIS_CTRLA) Operating Mode Mask */
    263. 

  263. #define SERCOM_SPIS_CTRLA_MODE(value)         (SERCOM_SPIS_CTRLA_MODE_Msk & ((value) << SERCOM_SPIS_CTRLA_MODE_Pos))
    264. 

  264. #define   SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) USART with external clock  */
    265. 

  265. #define   SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) USART with internal clock  */
    266. 

  266. #define   SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) SPI in slave operation  */
    267. 

  267. #define   SERCOM_SPIS_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_SPIS_CTRLA) SPI in master operation  */
    268. 

  268. #define   SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_SPIS_CTRLA) I2C slave operation  */
    269. 

  269. #define   SERCOM_SPIS_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_SPIS_CTRLA) I2C master operation  */
    270. 

  270. #define SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK  (SERCOM_SPIS_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) USART with external clock Position  */
    271. 

  271. #define SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK  (SERCOM_SPIS_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) USART with internal clock Position  */
    272. 

  272. #define SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE      (SERCOM_SPIS_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) SPI in slave operation Position  */
    273. 

  273. #define SERCOM_SPIS_CTRLA_MODE_SPI_MASTER     (SERCOM_SPIS_CTRLA_MODE_SPI_MASTER_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) SPI in master operation Position  */
    274. 

  274. #define SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE      (SERCOM_SPIS_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) I2C slave operation Position  */
    275. 

  275. #define SERCOM_SPIS_CTRLA_MODE_I2C_MASTER     (SERCOM_SPIS_CTRLA_MODE_I2C_MASTER_Val << SERCOM_SPIS_CTRLA_MODE_Pos) /**< (SERCOM_SPIS_CTRLA) I2C master operation Position  */
    276. 

  276. #define SERCOM_SPIS_CTRLA_RUNSTDBY_Pos        _U_(7)                                               /**< (SERCOM_SPIS_CTRLA) Run during Standby Position */
    277. 

  277. #define SERCOM_SPIS_CTRLA_RUNSTDBY_Msk        (_U_(0x1) << SERCOM_SPIS_CTRLA_RUNSTDBY_Pos)         /**< (SERCOM_SPIS_CTRLA) Run during Standby Mask */
    278. 

  278. #define SERCOM_SPIS_CTRLA_RUNSTDBY(value)     (SERCOM_SPIS_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_SPIS_CTRLA_RUNSTDBY_Pos))
    279. 

  279. #define SERCOM_SPIS_CTRLA_IBON_Pos            _U_(8)                                               /**< (SERCOM_SPIS_CTRLA) Immediate Buffer Overflow Notification Position */
    280. 

  280. #define SERCOM_SPIS_CTRLA_IBON_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_IBON_Pos)             /**< (SERCOM_SPIS_CTRLA) Immediate Buffer Overflow Notification Mask */
    281. 

  281. #define SERCOM_SPIS_CTRLA_IBON(value)         (SERCOM_SPIS_CTRLA_IBON_Msk & ((value) << SERCOM_SPIS_CTRLA_IBON_Pos))
    282. 

  282. #define SERCOM_SPIS_CTRLA_DOPO_Pos            _U_(16)                                              /**< (SERCOM_SPIS_CTRLA) Data Out Pinout Position */
    283. 

  283. #define SERCOM_SPIS_CTRLA_DOPO_Msk            (_U_(0x3) << SERCOM_SPIS_CTRLA_DOPO_Pos)             /**< (SERCOM_SPIS_CTRLA) Data Out Pinout Mask */
    284. 

  284. #define SERCOM_SPIS_CTRLA_DOPO(value)         (SERCOM_SPIS_CTRLA_DOPO_Msk & ((value) << SERCOM_SPIS_CTRLA_DOPO_Pos))
    285. 

  285. #define   SERCOM_SPIS_CTRLA_DOPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2]  */
    286. 

  286. #define   SERCOM_SPIS_CTRLA_DOPO_PAD1_Val     _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) DO on PAD[2], SCK on PAD[3] and SS on PAD[1]  */
    287. 

  287. #define   SERCOM_SPIS_CTRLA_DOPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2]  */
    288. 

  288. #define   SERCOM_SPIS_CTRLA_DOPO_PAD3_Val     _U_(0x3)                                             /**< (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[3] and SS on PAD[1]  */
    289. 

  289. #define SERCOM_SPIS_CTRLA_DOPO_PAD0           (SERCOM_SPIS_CTRLA_DOPO_PAD0_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /**< (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[1] and SS on PAD[2] Position  */
    290. 

  290. #define SERCOM_SPIS_CTRLA_DOPO_PAD1           (SERCOM_SPIS_CTRLA_DOPO_PAD1_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /**< (SERCOM_SPIS_CTRLA) DO on PAD[2], SCK on PAD[3] and SS on PAD[1] Position  */
    291. 

  291. #define SERCOM_SPIS_CTRLA_DOPO_PAD2           (SERCOM_SPIS_CTRLA_DOPO_PAD2_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /**< (SERCOM_SPIS_CTRLA) DO on PAD[3], SCK on PAD[1] and SS on PAD[2] Position  */
    292. 

  292. #define SERCOM_SPIS_CTRLA_DOPO_PAD3           (SERCOM_SPIS_CTRLA_DOPO_PAD3_Val << SERCOM_SPIS_CTRLA_DOPO_Pos) /**< (SERCOM_SPIS_CTRLA) DO on PAD[0], SCK on PAD[3] and SS on PAD[1] Position  */
    293. 

  293. #define SERCOM_SPIS_CTRLA_DIPO_Pos            _U_(20)                                              /**< (SERCOM_SPIS_CTRLA) Data In Pinout Position */
    294. 

  294. #define SERCOM_SPIS_CTRLA_DIPO_Msk            (_U_(0x3) << SERCOM_SPIS_CTRLA_DIPO_Pos)             /**< (SERCOM_SPIS_CTRLA) Data In Pinout Mask */
    295. 

  295. #define SERCOM_SPIS_CTRLA_DIPO(value)         (SERCOM_SPIS_CTRLA_DIPO_Msk & ((value) << SERCOM_SPIS_CTRLA_DIPO_Pos))
    296. 

  296. #define   SERCOM_SPIS_CTRLA_DIPO_PAD0_Val     _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[0]  */
    297. 

  297. #define   SERCOM_SPIS_CTRLA_DIPO_PAD1_Val     _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[1]  */
    298. 

  298. #define   SERCOM_SPIS_CTRLA_DIPO_PAD2_Val     _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[2]  */
    299. 

  299. #define   SERCOM_SPIS_CTRLA_DIPO_PAD3_Val     _U_(0x3)                                             /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[3]  */
    300. 

  300. #define SERCOM_SPIS_CTRLA_DIPO_PAD0           (SERCOM_SPIS_CTRLA_DIPO_PAD0_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[0] Position  */
    301. 

  301. #define SERCOM_SPIS_CTRLA_DIPO_PAD1           (SERCOM_SPIS_CTRLA_DIPO_PAD1_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[1] Position  */
    302. 

  302. #define SERCOM_SPIS_CTRLA_DIPO_PAD2           (SERCOM_SPIS_CTRLA_DIPO_PAD2_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[2] Position  */
    303. 

  303. #define SERCOM_SPIS_CTRLA_DIPO_PAD3           (SERCOM_SPIS_CTRLA_DIPO_PAD3_Val << SERCOM_SPIS_CTRLA_DIPO_Pos) /**< (SERCOM_SPIS_CTRLA) SERCOM PAD[3] Position  */
    304. 

  304. #define SERCOM_SPIS_CTRLA_FORM_Pos            _U_(24)                                              /**< (SERCOM_SPIS_CTRLA) Frame Format Position */
    305. 

  305. #define SERCOM_SPIS_CTRLA_FORM_Msk            (_U_(0xF) << SERCOM_SPIS_CTRLA_FORM_Pos)             /**< (SERCOM_SPIS_CTRLA) Frame Format Mask */
    306. 

  306. #define SERCOM_SPIS_CTRLA_FORM(value)         (SERCOM_SPIS_CTRLA_FORM_Msk & ((value) << SERCOM_SPIS_CTRLA_FORM_Pos))
    307. 

  307. #define   SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) SPI Frame  */
    308. 

  308. #define   SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLA) SPI Frame with Addr  */
    309. 

  309. #define SERCOM_SPIS_CTRLA_FORM_SPI_FRAME      (SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_Val << SERCOM_SPIS_CTRLA_FORM_Pos) /**< (SERCOM_SPIS_CTRLA) SPI Frame Position  */
    310. 

  310. #define SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR (SERCOM_SPIS_CTRLA_FORM_SPI_FRAME_WITH_ADDR_Val << SERCOM_SPIS_CTRLA_FORM_Pos) /**< (SERCOM_SPIS_CTRLA) SPI Frame with Addr Position  */
    311. 

  311. #define SERCOM_SPIS_CTRLA_CPHA_Pos            _U_(28)                                              /**< (SERCOM_SPIS_CTRLA) Clock Phase Position */
    312. 

  312. #define SERCOM_SPIS_CTRLA_CPHA_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_CPHA_Pos)             /**< (SERCOM_SPIS_CTRLA) Clock Phase Mask */
    313. 

  313. #define SERCOM_SPIS_CTRLA_CPHA(value)         (SERCOM_SPIS_CTRLA_CPHA_Msk & ((value) << SERCOM_SPIS_CTRLA_CPHA_Pos))
    314. 

  314. #define   SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge  */
    315. 

  315. #define   SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge  */
    316. 

  316. #define SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE   (SERCOM_SPIS_CTRLA_CPHA_LEADING_EDGE_Val << SERCOM_SPIS_CTRLA_CPHA_Pos) /**< (SERCOM_SPIS_CTRLA) The data is sampled on a leading SCK edge and changed on a trailing SCK edge Position  */
    317. 

  317. #define SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE  (SERCOM_SPIS_CTRLA_CPHA_TRAILING_EDGE_Val << SERCOM_SPIS_CTRLA_CPHA_Pos) /**< (SERCOM_SPIS_CTRLA) The data is sampled on a trailing SCK edge and changed on a leading SCK edge Position  */
    318. 

  318. #define SERCOM_SPIS_CTRLA_CPOL_Pos            _U_(29)                                              /**< (SERCOM_SPIS_CTRLA) Clock Polarity Position */
    319. 

  319. #define SERCOM_SPIS_CTRLA_CPOL_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_CPOL_Pos)             /**< (SERCOM_SPIS_CTRLA) Clock Polarity Mask */
    320. 

  320. #define SERCOM_SPIS_CTRLA_CPOL(value)         (SERCOM_SPIS_CTRLA_CPOL_Msk & ((value) << SERCOM_SPIS_CTRLA_CPOL_Pos))
    321. 

  321. #define   SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) SCK is low when idle  */
    322. 

  322. #define   SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) SCK is high when idle  */
    323. 

  323. #define SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW       (SERCOM_SPIS_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_SPIS_CTRLA_CPOL_Pos) /**< (SERCOM_SPIS_CTRLA) SCK is low when idle Position  */
    324. 

  324. #define SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH      (SERCOM_SPIS_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_SPIS_CTRLA_CPOL_Pos) /**< (SERCOM_SPIS_CTRLA) SCK is high when idle Position  */
    325. 

  325. #define SERCOM_SPIS_CTRLA_DORD_Pos            _U_(30)                                              /**< (SERCOM_SPIS_CTRLA) Data Order Position */
    326. 

  326. #define SERCOM_SPIS_CTRLA_DORD_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLA_DORD_Pos)             /**< (SERCOM_SPIS_CTRLA) Data Order Mask */
    327. 

  327. #define SERCOM_SPIS_CTRLA_DORD(value)         (SERCOM_SPIS_CTRLA_DORD_Msk & ((value) << SERCOM_SPIS_CTRLA_DORD_Pos))
    328. 

  328. #define   SERCOM_SPIS_CTRLA_DORD_MSB_Val      _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLA) MSB is transferred first  */
    329. 

  329. #define   SERCOM_SPIS_CTRLA_DORD_LSB_Val      _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLA) LSB is transferred first  */
    330. 

  330. #define SERCOM_SPIS_CTRLA_DORD_MSB            (SERCOM_SPIS_CTRLA_DORD_MSB_Val << SERCOM_SPIS_CTRLA_DORD_Pos) /**< (SERCOM_SPIS_CTRLA) MSB is transferred first Position  */
    331. 

  331. #define SERCOM_SPIS_CTRLA_DORD_LSB            (SERCOM_SPIS_CTRLA_DORD_LSB_Val << SERCOM_SPIS_CTRLA_DORD_Pos) /**< (SERCOM_SPIS_CTRLA) LSB is transferred first Position  */
    332. 

  332. #define SERCOM_SPIS_CTRLA_Msk                 _U_(0x7F33019F)                                      /**< (SERCOM_SPIS_CTRLA) Register Mask  */
    333. 

  333. 

  334. 

  335. /* -------- SERCOM_USART_EXT_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART_EXT Control A -------- */
    336. 

  336. #define SERCOM_USART_EXT_CTRLA_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_EXT_CTRLA) USART_EXT Control A  Reset Value */
    337. 

  337. 

  338. #define SERCOM_USART_EXT_CTRLA_SWRST_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_CTRLA) Software Reset Position */
    339. 

  339. #define SERCOM_USART_EXT_CTRLA_SWRST_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLA_SWRST_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Software Reset Mask */
    340. 

  340. #define SERCOM_USART_EXT_CTRLA_SWRST(value)   (SERCOM_USART_EXT_CTRLA_SWRST_Msk & ((value) << SERCOM_USART_EXT_CTRLA_SWRST_Pos))
    341. 

  341. #define SERCOM_USART_EXT_CTRLA_ENABLE_Pos     _U_(1)                                               /**< (SERCOM_USART_EXT_CTRLA) Enable Position */
    342. 

  342. #define SERCOM_USART_EXT_CTRLA_ENABLE_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLA_ENABLE_Pos)      /**< (SERCOM_USART_EXT_CTRLA) Enable Mask */
    343. 

  343. #define SERCOM_USART_EXT_CTRLA_ENABLE(value)  (SERCOM_USART_EXT_CTRLA_ENABLE_Msk & ((value) << SERCOM_USART_EXT_CTRLA_ENABLE_Pos))
    344. 

  344. #define SERCOM_USART_EXT_CTRLA_MODE_Pos       _U_(2)                                               /**< (SERCOM_USART_EXT_CTRLA) Operating Mode Position */
    345. 

  345. #define SERCOM_USART_EXT_CTRLA_MODE_Msk       (_U_(0x7) << SERCOM_USART_EXT_CTRLA_MODE_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Operating Mode Mask */
    346. 

  346. #define SERCOM_USART_EXT_CTRLA_MODE(value)    (SERCOM_USART_EXT_CTRLA_MODE_Msk & ((value) << SERCOM_USART_EXT_CTRLA_MODE_Pos))
    347. 

  347. #define   SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) USART with external clock  */
    348. 

  348. #define   SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) USART with internal clock  */
    349. 

  349. #define   SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) SPI in slave operation  */
    350. 

  350. #define   SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) SPI in master operation  */
    351. 

  351. #define   SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_USART_EXT_CTRLA) I2C slave operation  */
    352. 

  352. #define   SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_USART_EXT_CTRLA) I2C master operation  */
    353. 

  353. #define SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_EXT_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART with external clock Position  */
    354. 

  354. #define SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_EXT_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART with internal clock Position  */
    355. 

  355. #define SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_EXT_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) SPI in slave operation Position  */
    356. 

  356. #define SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER (SERCOM_USART_EXT_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) SPI in master operation Position  */
    357. 

  357. #define SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_EXT_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) I2C slave operation Position  */
    358. 

  358. #define SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER (SERCOM_USART_EXT_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_EXT_CTRLA_MODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) I2C master operation Position  */
    359. 

  359. #define SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos   _U_(7)                                               /**< (SERCOM_USART_EXT_CTRLA) Run during Standby Position */
    360. 

  360. #define SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk   (_U_(0x1) << SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos)    /**< (SERCOM_USART_EXT_CTRLA) Run during Standby Mask */
    361. 

  361. #define SERCOM_USART_EXT_CTRLA_RUNSTDBY(value) (SERCOM_USART_EXT_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_USART_EXT_CTRLA_RUNSTDBY_Pos))
    362. 

  362. #define SERCOM_USART_EXT_CTRLA_IBON_Pos       _U_(8)                                               /**< (SERCOM_USART_EXT_CTRLA) Immediate Buffer Overflow Notification Position */
    363. 

  363. #define SERCOM_USART_EXT_CTRLA_IBON_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLA_IBON_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Immediate Buffer Overflow Notification Mask */
    364. 

  364. #define SERCOM_USART_EXT_CTRLA_IBON(value)    (SERCOM_USART_EXT_CTRLA_IBON_Msk & ((value) << SERCOM_USART_EXT_CTRLA_IBON_Pos))
    365. 

  365. #define SERCOM_USART_EXT_CTRLA_SAMPR_Pos      _U_(13)                                              /**< (SERCOM_USART_EXT_CTRLA) Sample Position */
    366. 

  366. #define SERCOM_USART_EXT_CTRLA_SAMPR_Msk      (_U_(0x7) << SERCOM_USART_EXT_CTRLA_SAMPR_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Sample Mask */
    367. 

  367. #define SERCOM_USART_EXT_CTRLA_SAMPR(value)   (SERCOM_USART_EXT_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_EXT_CTRLA_SAMPR_Pos))
    368. 

  368. #define   SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using arithmetic baudrate generation  */
    369. 

  369. #define   SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using fractional baudrate generation  */
    370. 

  370. #define   SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using arithmetic baudrate generation  */
    371. 

  371. #define   SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using fractional baudrate generation  */
    372. 

  372. #define   SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC_Val _U_(0x4)                                             /**< (SERCOM_USART_EXT_CTRLA) 3x over-sampling using arithmetic baudrate generation  */
    373. 

  373. #define SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_16X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using arithmetic baudrate generation Position  */
    374. 

  374. #define SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL (SERCOM_USART_EXT_CTRLA_SAMPR_16X_FRACTIONAL_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x over-sampling using fractional baudrate generation Position  */
    375. 

  375. #define SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_8X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using arithmetic baudrate generation Position  */
    376. 

  376. #define SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL (SERCOM_USART_EXT_CTRLA_SAMPR_8X_FRACTIONAL_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 8x over-sampling using fractional baudrate generation Position  */
    377. 

  377. #define SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC (SERCOM_USART_EXT_CTRLA_SAMPR_3X_ARITHMETIC_Val << SERCOM_USART_EXT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_EXT_CTRLA) 3x over-sampling using arithmetic baudrate generation Position  */
    378. 

  378. #define SERCOM_USART_EXT_CTRLA_TXPO_Pos       _U_(16)                                              /**< (SERCOM_USART_EXT_CTRLA) Transmit Data Pinout Position */
    379. 

  379. #define SERCOM_USART_EXT_CTRLA_TXPO_Msk       (_U_(0x3) << SERCOM_USART_EXT_CTRLA_TXPO_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Transmit Data Pinout Mask */
    380. 

  380. #define SERCOM_USART_EXT_CTRLA_TXPO(value)    (SERCOM_USART_EXT_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_EXT_CTRLA_TXPO_Pos))
    381. 

  381. #define   SERCOM_USART_EXT_CTRLA_TXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
    382. 

  382. #define   SERCOM_USART_EXT_CTRLA_TXPO_PAD1_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) PAD[2] = TxD; PAD[3] = XCK  */
    383. 

  383. #define   SERCOM_USART_EXT_CTRLA_TXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
    384. 

  384. #define SERCOM_USART_EXT_CTRLA_TXPO_PAD0      (SERCOM_USART_EXT_CTRLA_TXPO_PAD0_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position  */
    385. 

  385. #define SERCOM_USART_EXT_CTRLA_TXPO_PAD1      (SERCOM_USART_EXT_CTRLA_TXPO_PAD1_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) PAD[2] = TxD; PAD[3] = XCK Position  */
    386. 

  386. #define SERCOM_USART_EXT_CTRLA_TXPO_PAD2      (SERCOM_USART_EXT_CTRLA_TXPO_PAD2_Val << SERCOM_USART_EXT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position  */
    387. 

  387. #define SERCOM_USART_EXT_CTRLA_RXPO_Pos       _U_(20)                                              /**< (SERCOM_USART_EXT_CTRLA) Receive Data Pinout Position */
    388. 

  388. #define SERCOM_USART_EXT_CTRLA_RXPO_Msk       (_U_(0x3) << SERCOM_USART_EXT_CTRLA_RXPO_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Receive Data Pinout Mask */
    389. 

  389. #define SERCOM_USART_EXT_CTRLA_RXPO(value)    (SERCOM_USART_EXT_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_EXT_CTRLA_RXPO_Pos))
    390. 

  390. #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[0] is used for data reception  */
    391. 

  391. #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD1_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[1] is used for data reception  */
    392. 

  392. #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[2] is used for data reception  */
    393. 

  393. #define   SERCOM_USART_EXT_CTRLA_RXPO_PAD3_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[3] is used for data reception  */
    394. 

  394. #define SERCOM_USART_EXT_CTRLA_RXPO_PAD0      (SERCOM_USART_EXT_CTRLA_RXPO_PAD0_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[0] is used for data reception Position  */
    395. 

  395. #define SERCOM_USART_EXT_CTRLA_RXPO_PAD1      (SERCOM_USART_EXT_CTRLA_RXPO_PAD1_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[1] is used for data reception Position  */
    396. 

  396. #define SERCOM_USART_EXT_CTRLA_RXPO_PAD2      (SERCOM_USART_EXT_CTRLA_RXPO_PAD2_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[2] is used for data reception Position  */
    397. 

  397. #define SERCOM_USART_EXT_CTRLA_RXPO_PAD3      (SERCOM_USART_EXT_CTRLA_RXPO_PAD3_Val << SERCOM_USART_EXT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_EXT_CTRLA) SERCOM PAD[3] is used for data reception Position  */
    398. 

  398. #define SERCOM_USART_EXT_CTRLA_SAMPA_Pos      _U_(22)                                              /**< (SERCOM_USART_EXT_CTRLA) Sample Adjustment Position */
    399. 

  399. #define SERCOM_USART_EXT_CTRLA_SAMPA_Msk      (_U_(0x3) << SERCOM_USART_EXT_CTRLA_SAMPA_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Sample Adjustment Mask */
    400. 

  400. #define SERCOM_USART_EXT_CTRLA_SAMPA(value)   (SERCOM_USART_EXT_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_EXT_CTRLA_SAMPA_Pos))
    401. 

  401. #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5  */
    402. 

  402. #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6  */
    403. 

  403. #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2_Val _U_(0x2)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7  */
    404. 

  404. #define   SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3_Val _U_(0x3)                                             /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8  */
    405. 

  405. #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ0_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 Position  */
    406. 

  406. #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ1_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 Position  */
    407. 

  407. #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ2_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 Position  */
    408. 

  408. #define SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3     (SERCOM_USART_EXT_CTRLA_SAMPA_ADJ3_Val << SERCOM_USART_EXT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_EXT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 Position  */
    409. 

  409. #define SERCOM_USART_EXT_CTRLA_FORM_Pos       _U_(24)                                              /**< (SERCOM_USART_EXT_CTRLA) Frame Format Position */
    410. 

  410. #define SERCOM_USART_EXT_CTRLA_FORM_Msk       (_U_(0xF) << SERCOM_USART_EXT_CTRLA_FORM_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Frame Format Mask */
    411. 

  411. #define SERCOM_USART_EXT_CTRLA_FORM(value)    (SERCOM_USART_EXT_CTRLA_FORM_Msk & ((value) << SERCOM_USART_EXT_CTRLA_FORM_Pos))
    412. 

  412. #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) USART frame  */
    413. 

  413. #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) USART frame with parity  */
    414. 

  414. #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val _U_(0x4)                                             /**< (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud  */
    415. 

  415. #define   SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val _U_(0x5)                                             /**< (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud with parity  */
    416. 

  416. #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART frame Position  */
    417. 

  417. #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) USART frame with parity Position  */
    418. 

  418. #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud Position  */
    419. 

  419. #define SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY (SERCOM_USART_EXT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val << SERCOM_USART_EXT_CTRLA_FORM_Pos) /**< (SERCOM_USART_EXT_CTRLA) Auto-baud - break detection and auto-baud with parity Position  */
    420. 

  420. #define SERCOM_USART_EXT_CTRLA_CMODE_Pos      _U_(28)                                              /**< (SERCOM_USART_EXT_CTRLA) Communication Mode Position */
    421. 

  421. #define SERCOM_USART_EXT_CTRLA_CMODE_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLA_CMODE_Pos)       /**< (SERCOM_USART_EXT_CTRLA) Communication Mode Mask */
    422. 

  422. #define SERCOM_USART_EXT_CTRLA_CMODE(value)   (SERCOM_USART_EXT_CTRLA_CMODE_Msk & ((value) << SERCOM_USART_EXT_CTRLA_CMODE_Pos))
    423. 

  423. #define   SERCOM_USART_EXT_CTRLA_CMODE_ASYNC_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) Asynchronous Communication  */
    424. 

  424. #define   SERCOM_USART_EXT_CTRLA_CMODE_SYNC_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) Synchronous Communication  */
    425. 

  425. #define SERCOM_USART_EXT_CTRLA_CMODE_ASYNC    (SERCOM_USART_EXT_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_EXT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) Asynchronous Communication Position  */
    426. 

  426. #define SERCOM_USART_EXT_CTRLA_CMODE_SYNC     (SERCOM_USART_EXT_CTRLA_CMODE_SYNC_Val << SERCOM_USART_EXT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_EXT_CTRLA) Synchronous Communication Position  */
    427. 

  427. #define SERCOM_USART_EXT_CTRLA_CPOL_Pos       _U_(29)                                              /**< (SERCOM_USART_EXT_CTRLA) Clock Polarity Position */
    428. 

  428. #define SERCOM_USART_EXT_CTRLA_CPOL_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLA_CPOL_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Clock Polarity Mask */
    429. 

  429. #define SERCOM_USART_EXT_CTRLA_CPOL(value)    (SERCOM_USART_EXT_CTRLA_CPOL_Msk & ((value) << SERCOM_USART_EXT_CTRLA_CPOL_Pos))
    430. 

  430. #define   SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge  */
    431. 

  431. #define   SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge  */
    432. 

  432. #define SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW  (SERCOM_USART_EXT_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_USART_EXT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge Position  */
    433. 

  433. #define SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH (SERCOM_USART_EXT_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_USART_EXT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_EXT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge Position  */
    434. 

  434. #define SERCOM_USART_EXT_CTRLA_DORD_Pos       _U_(30)                                              /**< (SERCOM_USART_EXT_CTRLA) Data Order Position */
    435. 

  435. #define SERCOM_USART_EXT_CTRLA_DORD_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLA_DORD_Pos)        /**< (SERCOM_USART_EXT_CTRLA) Data Order Mask */
    436. 

  436. #define SERCOM_USART_EXT_CTRLA_DORD(value)    (SERCOM_USART_EXT_CTRLA_DORD_Msk & ((value) << SERCOM_USART_EXT_CTRLA_DORD_Pos))
    437. 

  437. #define   SERCOM_USART_EXT_CTRLA_DORD_MSB_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLA) MSB is transmitted first  */
    438. 

  438. #define   SERCOM_USART_EXT_CTRLA_DORD_LSB_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLA) LSB is transmitted first  */
    439. 

  439. #define SERCOM_USART_EXT_CTRLA_DORD_MSB       (SERCOM_USART_EXT_CTRLA_DORD_MSB_Val << SERCOM_USART_EXT_CTRLA_DORD_Pos) /**< (SERCOM_USART_EXT_CTRLA) MSB is transmitted first Position  */
    440. 

  440. #define SERCOM_USART_EXT_CTRLA_DORD_LSB       (SERCOM_USART_EXT_CTRLA_DORD_LSB_Val << SERCOM_USART_EXT_CTRLA_DORD_Pos) /**< (SERCOM_USART_EXT_CTRLA) LSB is transmitted first Position  */
    441. 

  441. #define SERCOM_USART_EXT_CTRLA_Msk            _U_(0x7FF3E19F)                                      /**< (SERCOM_USART_EXT_CTRLA) Register Mask  */
    442. 

  442. 

  443. 

  444. /* -------- SERCOM_USART_INT_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART_INT Control A -------- */
    445. 

  445. #define SERCOM_USART_INT_CTRLA_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_INT_CTRLA) USART_INT Control A  Reset Value */
    446. 

  446. 

  447. #define SERCOM_USART_INT_CTRLA_SWRST_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_CTRLA) Software Reset Position */
    448. 

  448. #define SERCOM_USART_INT_CTRLA_SWRST_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLA_SWRST_Pos)       /**< (SERCOM_USART_INT_CTRLA) Software Reset Mask */
    449. 

  449. #define SERCOM_USART_INT_CTRLA_SWRST(value)   (SERCOM_USART_INT_CTRLA_SWRST_Msk & ((value) << SERCOM_USART_INT_CTRLA_SWRST_Pos))
    450. 

  450. #define SERCOM_USART_INT_CTRLA_ENABLE_Pos     _U_(1)                                               /**< (SERCOM_USART_INT_CTRLA) Enable Position */
    451. 

  451. #define SERCOM_USART_INT_CTRLA_ENABLE_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLA_ENABLE_Pos)      /**< (SERCOM_USART_INT_CTRLA) Enable Mask */
    452. 

  452. #define SERCOM_USART_INT_CTRLA_ENABLE(value)  (SERCOM_USART_INT_CTRLA_ENABLE_Msk & ((value) << SERCOM_USART_INT_CTRLA_ENABLE_Pos))
    453. 

  453. #define SERCOM_USART_INT_CTRLA_MODE_Pos       _U_(2)                                               /**< (SERCOM_USART_INT_CTRLA) Operating Mode Position */
    454. 

  454. #define SERCOM_USART_INT_CTRLA_MODE_Msk       (_U_(0x7) << SERCOM_USART_INT_CTRLA_MODE_Pos)        /**< (SERCOM_USART_INT_CTRLA) Operating Mode Mask */
    455. 

  455. #define SERCOM_USART_INT_CTRLA_MODE(value)    (SERCOM_USART_INT_CTRLA_MODE_Msk & ((value) << SERCOM_USART_INT_CTRLA_MODE_Pos))
    456. 

  456. #define   SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) USART with external clock  */
    457. 

  457. #define   SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) USART with internal clock  */
    458. 

  458. #define   SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) SPI in slave operation  */
    459. 

  459. #define   SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) SPI in master operation  */
    460. 

  460. #define   SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE_Val _U_(0x4)                                             /**< (SERCOM_USART_INT_CTRLA) I2C slave operation  */
    461. 

  461. #define   SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER_Val _U_(0x5)                                             /**< (SERCOM_USART_INT_CTRLA) I2C master operation  */
    462. 

  462. #define SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK (SERCOM_USART_INT_CTRLA_MODE_USART_EXT_CLK_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) USART with external clock Position  */
    463. 

  463. #define SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK (SERCOM_USART_INT_CTRLA_MODE_USART_INT_CLK_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) USART with internal clock Position  */
    464. 

  464. #define SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE (SERCOM_USART_INT_CTRLA_MODE_SPI_SLAVE_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) SPI in slave operation Position  */
    465. 

  465. #define SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER (SERCOM_USART_INT_CTRLA_MODE_SPI_MASTER_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) SPI in master operation Position  */
    466. 

  466. #define SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE (SERCOM_USART_INT_CTRLA_MODE_I2C_SLAVE_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) I2C slave operation Position  */
    467. 

  467. #define SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER (SERCOM_USART_INT_CTRLA_MODE_I2C_MASTER_Val << SERCOM_USART_INT_CTRLA_MODE_Pos) /**< (SERCOM_USART_INT_CTRLA) I2C master operation Position  */
    468. 

  468. #define SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos   _U_(7)                                               /**< (SERCOM_USART_INT_CTRLA) Run during Standby Position */
    469. 

  469. #define SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk   (_U_(0x1) << SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos)    /**< (SERCOM_USART_INT_CTRLA) Run during Standby Mask */
    470. 

  470. #define SERCOM_USART_INT_CTRLA_RUNSTDBY(value) (SERCOM_USART_INT_CTRLA_RUNSTDBY_Msk & ((value) << SERCOM_USART_INT_CTRLA_RUNSTDBY_Pos))
    471. 

  471. #define SERCOM_USART_INT_CTRLA_IBON_Pos       _U_(8)                                               /**< (SERCOM_USART_INT_CTRLA) Immediate Buffer Overflow Notification Position */
    472. 

  472. #define SERCOM_USART_INT_CTRLA_IBON_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLA_IBON_Pos)        /**< (SERCOM_USART_INT_CTRLA) Immediate Buffer Overflow Notification Mask */
    473. 

  473. #define SERCOM_USART_INT_CTRLA_IBON(value)    (SERCOM_USART_INT_CTRLA_IBON_Msk & ((value) << SERCOM_USART_INT_CTRLA_IBON_Pos))
    474. 

  474. #define SERCOM_USART_INT_CTRLA_SAMPR_Pos      _U_(13)                                              /**< (SERCOM_USART_INT_CTRLA) Sample Position */
    475. 

  475. #define SERCOM_USART_INT_CTRLA_SAMPR_Msk      (_U_(0x7) << SERCOM_USART_INT_CTRLA_SAMPR_Pos)       /**< (SERCOM_USART_INT_CTRLA) Sample Mask */
    476. 

  476. #define SERCOM_USART_INT_CTRLA_SAMPR(value)   (SERCOM_USART_INT_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_INT_CTRLA_SAMPR_Pos))
    477. 

  477. #define   SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using arithmetic baudrate generation  */
    478. 

  478. #define   SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using fractional baudrate generation  */
    479. 

  479. #define   SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using arithmetic baudrate generation  */
    480. 

  480. #define   SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using fractional baudrate generation  */
    481. 

  481. #define   SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC_Val _U_(0x4)                                             /**< (SERCOM_USART_INT_CTRLA) 3x over-sampling using arithmetic baudrate generation  */
    482. 

  482. #define SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_16X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using arithmetic baudrate generation Position  */
    483. 

  483. #define SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL (SERCOM_USART_INT_CTRLA_SAMPR_16X_FRACTIONAL_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x over-sampling using fractional baudrate generation Position  */
    484. 

  484. #define SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_8X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using arithmetic baudrate generation Position  */
    485. 

  485. #define SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL (SERCOM_USART_INT_CTRLA_SAMPR_8X_FRACTIONAL_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 8x over-sampling using fractional baudrate generation Position  */
    486. 

  486. #define SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC (SERCOM_USART_INT_CTRLA_SAMPR_3X_ARITHMETIC_Val << SERCOM_USART_INT_CTRLA_SAMPR_Pos) /**< (SERCOM_USART_INT_CTRLA) 3x over-sampling using arithmetic baudrate generation Position  */
    487. 

  487. #define SERCOM_USART_INT_CTRLA_TXPO_Pos       _U_(16)                                              /**< (SERCOM_USART_INT_CTRLA) Transmit Data Pinout Position */
    488. 

  488. #define SERCOM_USART_INT_CTRLA_TXPO_Msk       (_U_(0x3) << SERCOM_USART_INT_CTRLA_TXPO_Pos)        /**< (SERCOM_USART_INT_CTRLA) Transmit Data Pinout Mask */
    489. 

  489. #define SERCOM_USART_INT_CTRLA_TXPO(value)    (SERCOM_USART_INT_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_INT_CTRLA_TXPO_Pos))
    490. 

  490. #define   SERCOM_USART_INT_CTRLA_TXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK  */
    491. 

  491. #define   SERCOM_USART_INT_CTRLA_TXPO_PAD1_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) PAD[2] = TxD; PAD[3] = XCK  */
    492. 

  492. #define   SERCOM_USART_INT_CTRLA_TXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS  */
    493. 

  493. #define SERCOM_USART_INT_CTRLA_TXPO_PAD0      (SERCOM_USART_INT_CTRLA_TXPO_PAD0_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[1] = XCK Position  */
    494. 

  494. #define SERCOM_USART_INT_CTRLA_TXPO_PAD1      (SERCOM_USART_INT_CTRLA_TXPO_PAD1_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) PAD[2] = TxD; PAD[3] = XCK Position  */
    495. 

  495. #define SERCOM_USART_INT_CTRLA_TXPO_PAD2      (SERCOM_USART_INT_CTRLA_TXPO_PAD2_Val << SERCOM_USART_INT_CTRLA_TXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS Position  */
    496. 

  496. #define SERCOM_USART_INT_CTRLA_RXPO_Pos       _U_(20)                                              /**< (SERCOM_USART_INT_CTRLA) Receive Data Pinout Position */
    497. 

  497. #define SERCOM_USART_INT_CTRLA_RXPO_Msk       (_U_(0x3) << SERCOM_USART_INT_CTRLA_RXPO_Pos)        /**< (SERCOM_USART_INT_CTRLA) Receive Data Pinout Mask */
    498. 

  498. #define SERCOM_USART_INT_CTRLA_RXPO(value)    (SERCOM_USART_INT_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_INT_CTRLA_RXPO_Pos))
    499. 

  499. #define   SERCOM_USART_INT_CTRLA_RXPO_PAD0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[0] is used for data reception  */
    500. 

  500. #define   SERCOM_USART_INT_CTRLA_RXPO_PAD1_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[1] is used for data reception  */
    501. 

  501. #define   SERCOM_USART_INT_CTRLA_RXPO_PAD2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[2] is used for data reception  */
    502. 

  502. #define   SERCOM_USART_INT_CTRLA_RXPO_PAD3_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[3] is used for data reception  */
    503. 

  503. #define SERCOM_USART_INT_CTRLA_RXPO_PAD0      (SERCOM_USART_INT_CTRLA_RXPO_PAD0_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[0] is used for data reception Position  */
    504. 

  504. #define SERCOM_USART_INT_CTRLA_RXPO_PAD1      (SERCOM_USART_INT_CTRLA_RXPO_PAD1_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[1] is used for data reception Position  */
    505. 

  505. #define SERCOM_USART_INT_CTRLA_RXPO_PAD2      (SERCOM_USART_INT_CTRLA_RXPO_PAD2_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[2] is used for data reception Position  */
    506. 

  506. #define SERCOM_USART_INT_CTRLA_RXPO_PAD3      (SERCOM_USART_INT_CTRLA_RXPO_PAD3_Val << SERCOM_USART_INT_CTRLA_RXPO_Pos) /**< (SERCOM_USART_INT_CTRLA) SERCOM PAD[3] is used for data reception Position  */
    507. 

  507. #define SERCOM_USART_INT_CTRLA_SAMPA_Pos      _U_(22)                                              /**< (SERCOM_USART_INT_CTRLA) Sample Adjustment Position */
    508. 

  508. #define SERCOM_USART_INT_CTRLA_SAMPA_Msk      (_U_(0x3) << SERCOM_USART_INT_CTRLA_SAMPA_Pos)       /**< (SERCOM_USART_INT_CTRLA) Sample Adjustment Mask */
    509. 

  509. #define SERCOM_USART_INT_CTRLA_SAMPA(value)   (SERCOM_USART_INT_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_INT_CTRLA_SAMPA_Pos))
    510. 

  510. #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ0_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5  */
    511. 

  511. #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ1_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6  */
    512. 

  512. #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ2_Val _U_(0x2)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7  */
    513. 

  513. #define   SERCOM_USART_INT_CTRLA_SAMPA_ADJ3_Val _U_(0x3)                                             /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8  */
    514. 

  514. #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ0     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ0_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-5 Position  */
    515. 

  515. #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ1     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ1_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-6 Position  */
    516. 

  516. #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ2     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ2_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-7 Position  */
    517. 

  517. #define SERCOM_USART_INT_CTRLA_SAMPA_ADJ3     (SERCOM_USART_INT_CTRLA_SAMPA_ADJ3_Val << SERCOM_USART_INT_CTRLA_SAMPA_Pos) /**< (SERCOM_USART_INT_CTRLA) 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 Position  */
    518. 

  518. #define SERCOM_USART_INT_CTRLA_FORM_Pos       _U_(24)                                              /**< (SERCOM_USART_INT_CTRLA) Frame Format Position */
    519. 

  519. #define SERCOM_USART_INT_CTRLA_FORM_Msk       (_U_(0xF) << SERCOM_USART_INT_CTRLA_FORM_Pos)        /**< (SERCOM_USART_INT_CTRLA) Frame Format Mask */
    520. 

  520. #define SERCOM_USART_INT_CTRLA_FORM(value)    (SERCOM_USART_INT_CTRLA_FORM_Msk & ((value) << SERCOM_USART_INT_CTRLA_FORM_Pos))
    521. 

  521. #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) USART frame  */
    522. 

  522. #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) USART frame with parity  */
    523. 

  523. #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val _U_(0x4)                                             /**< (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud  */
    524. 

  524. #define   SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val _U_(0x5)                                             /**< (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud with parity  */
    525. 

  525. #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_NO_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) USART frame Position  */
    526. 

  526. #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_WITH_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) USART frame with parity Position  */
    527. 

  527. #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_NO_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud Position  */
    528. 

  528. #define SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY (SERCOM_USART_INT_CTRLA_FORM_USART_FRAME_AUTO_BAUD_WITH_PARITY_Val << SERCOM_USART_INT_CTRLA_FORM_Pos) /**< (SERCOM_USART_INT_CTRLA) Auto-baud - break detection and auto-baud with parity Position  */
    529. 

  529. #define SERCOM_USART_INT_CTRLA_CMODE_Pos      _U_(28)                                              /**< (SERCOM_USART_INT_CTRLA) Communication Mode Position */
    530. 

  530. #define SERCOM_USART_INT_CTRLA_CMODE_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLA_CMODE_Pos)       /**< (SERCOM_USART_INT_CTRLA) Communication Mode Mask */
    531. 

  531. #define SERCOM_USART_INT_CTRLA_CMODE(value)   (SERCOM_USART_INT_CTRLA_CMODE_Msk & ((value) << SERCOM_USART_INT_CTRLA_CMODE_Pos))
    532. 

  532. #define   SERCOM_USART_INT_CTRLA_CMODE_ASYNC_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) Asynchronous Communication  */
    533. 

  533. #define   SERCOM_USART_INT_CTRLA_CMODE_SYNC_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) Synchronous Communication  */
    534. 

  534. #define SERCOM_USART_INT_CTRLA_CMODE_ASYNC    (SERCOM_USART_INT_CTRLA_CMODE_ASYNC_Val << SERCOM_USART_INT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_INT_CTRLA) Asynchronous Communication Position  */
    535. 

  535. #define SERCOM_USART_INT_CTRLA_CMODE_SYNC     (SERCOM_USART_INT_CTRLA_CMODE_SYNC_Val << SERCOM_USART_INT_CTRLA_CMODE_Pos) /**< (SERCOM_USART_INT_CTRLA) Synchronous Communication Position  */
    536. 

  536. #define SERCOM_USART_INT_CTRLA_CPOL_Pos       _U_(29)                                              /**< (SERCOM_USART_INT_CTRLA) Clock Polarity Position */
    537. 

  537. #define SERCOM_USART_INT_CTRLA_CPOL_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLA_CPOL_Pos)        /**< (SERCOM_USART_INT_CTRLA) Clock Polarity Mask */
    538. 

  538. #define SERCOM_USART_INT_CTRLA_CPOL(value)    (SERCOM_USART_INT_CTRLA_CPOL_Msk & ((value) << SERCOM_USART_INT_CTRLA_CPOL_Pos))
    539. 

  539. #define   SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge  */
    540. 

  540. #define   SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge  */
    541. 

  541. #define SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW  (SERCOM_USART_INT_CTRLA_CPOL_IDLE_LOW_Val << SERCOM_USART_INT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge Position  */
    542. 

  542. #define SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH (SERCOM_USART_INT_CTRLA_CPOL_IDLE_HIGH_Val << SERCOM_USART_INT_CTRLA_CPOL_Pos) /**< (SERCOM_USART_INT_CTRLA) TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge Position  */
    543. 

  543. #define SERCOM_USART_INT_CTRLA_DORD_Pos       _U_(30)                                              /**< (SERCOM_USART_INT_CTRLA) Data Order Position */
    544. 

  544. #define SERCOM_USART_INT_CTRLA_DORD_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLA_DORD_Pos)        /**< (SERCOM_USART_INT_CTRLA) Data Order Mask */
    545. 

  545. #define SERCOM_USART_INT_CTRLA_DORD(value)    (SERCOM_USART_INT_CTRLA_DORD_Msk & ((value) << SERCOM_USART_INT_CTRLA_DORD_Pos))
    546. 

  546. #define   SERCOM_USART_INT_CTRLA_DORD_MSB_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLA) MSB is transmitted first  */
    547. 

  547. #define   SERCOM_USART_INT_CTRLA_DORD_LSB_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLA) LSB is transmitted first  */
    548. 

  548. #define SERCOM_USART_INT_CTRLA_DORD_MSB       (SERCOM_USART_INT_CTRLA_DORD_MSB_Val << SERCOM_USART_INT_CTRLA_DORD_Pos) /**< (SERCOM_USART_INT_CTRLA) MSB is transmitted first Position  */
    549. 

  549. #define SERCOM_USART_INT_CTRLA_DORD_LSB       (SERCOM_USART_INT_CTRLA_DORD_LSB_Val << SERCOM_USART_INT_CTRLA_DORD_Pos) /**< (SERCOM_USART_INT_CTRLA) LSB is transmitted first Position  */
    550. 

  550. #define SERCOM_USART_INT_CTRLA_Msk            _U_(0x7FF3E19F)                                      /**< (SERCOM_USART_INT_CTRLA) Register Mask  */
    551. 

  551. 

  552. 

  553. /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM Control B -------- */
    554. 

  554. #define SERCOM_I2CM_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CM_CTRLB) I2CM Control B  Reset Value */
    555. 

  555. 

  556. #define SERCOM_I2CM_CTRLB_SMEN_Pos            _U_(8)                                               /**< (SERCOM_I2CM_CTRLB) Smart Mode Enable Position */
    557. 

  557. #define SERCOM_I2CM_CTRLB_SMEN_Msk            (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos)             /**< (SERCOM_I2CM_CTRLB) Smart Mode Enable Mask */
    558. 

  558. #define SERCOM_I2CM_CTRLB_SMEN(value)         (SERCOM_I2CM_CTRLB_SMEN_Msk & ((value) << SERCOM_I2CM_CTRLB_SMEN_Pos))
    559. 

  559. #define SERCOM_I2CM_CTRLB_QCEN_Pos            _U_(9)                                               /**< (SERCOM_I2CM_CTRLB) Quick Command Enable Position */
    560. 

  560. #define SERCOM_I2CM_CTRLB_QCEN_Msk            (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos)             /**< (SERCOM_I2CM_CTRLB) Quick Command Enable Mask */
    561. 

  561. #define SERCOM_I2CM_CTRLB_QCEN(value)         (SERCOM_I2CM_CTRLB_QCEN_Msk & ((value) << SERCOM_I2CM_CTRLB_QCEN_Pos))
    562. 

  562. #define SERCOM_I2CM_CTRLB_CMD_Pos             _U_(16)                                              /**< (SERCOM_I2CM_CTRLB) Command Position */
    563. 

  563. #define SERCOM_I2CM_CTRLB_CMD_Msk             (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos)              /**< (SERCOM_I2CM_CTRLB) Command Mask */
    564. 

  564. #define SERCOM_I2CM_CTRLB_CMD(value)          (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos))
    565. 

  565. #define SERCOM_I2CM_CTRLB_ACKACT_Pos          _U_(18)                                              /**< (SERCOM_I2CM_CTRLB) Acknowledge Action Position */
    566. 

  566. #define SERCOM_I2CM_CTRLB_ACKACT_Msk          (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos)           /**< (SERCOM_I2CM_CTRLB) Acknowledge Action Mask */
    567. 

  567. #define SERCOM_I2CM_CTRLB_ACKACT(value)       (SERCOM_I2CM_CTRLB_ACKACT_Msk & ((value) << SERCOM_I2CM_CTRLB_ACKACT_Pos))
    568. 

  568. #define SERCOM_I2CM_CTRLB_Msk                 _U_(0x00070300)                                      /**< (SERCOM_I2CM_CTRLB) Register Mask  */
    569. 

  569. 

  570. 

  571. /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS Control B -------- */
    572. 

  572. #define SERCOM_I2CS_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_I2CS_CTRLB) I2CS Control B  Reset Value */
    573. 

  573. 

  574. #define SERCOM_I2CS_CTRLB_SMEN_Pos            _U_(8)                                               /**< (SERCOM_I2CS_CTRLB) Smart Mode Enable Position */
    575. 

  575. #define SERCOM_I2CS_CTRLB_SMEN_Msk            (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos)             /**< (SERCOM_I2CS_CTRLB) Smart Mode Enable Mask */
    576. 

  576. #define SERCOM_I2CS_CTRLB_SMEN(value)         (SERCOM_I2CS_CTRLB_SMEN_Msk & ((value) << SERCOM_I2CS_CTRLB_SMEN_Pos))
    577. 

  577. #define SERCOM_I2CS_CTRLB_GCMD_Pos            _U_(9)                                               /**< (SERCOM_I2CS_CTRLB) PMBus Group Command Position */
    578. 

  578. #define SERCOM_I2CS_CTRLB_GCMD_Msk            (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos)             /**< (SERCOM_I2CS_CTRLB) PMBus Group Command Mask */
    579. 

  579. #define SERCOM_I2CS_CTRLB_GCMD(value)         (SERCOM_I2CS_CTRLB_GCMD_Msk & ((value) << SERCOM_I2CS_CTRLB_GCMD_Pos))
    580. 

  580. #define SERCOM_I2CS_CTRLB_AACKEN_Pos          _U_(10)                                              /**< (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge Position */
    581. 

  581. #define SERCOM_I2CS_CTRLB_AACKEN_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos)           /**< (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge Mask */
    582. 

  582. #define SERCOM_I2CS_CTRLB_AACKEN(value)       (SERCOM_I2CS_CTRLB_AACKEN_Msk & ((value) << SERCOM_I2CS_CTRLB_AACKEN_Pos))
    583. 

  583. #define SERCOM_I2CS_CTRLB_AMODE_Pos           _U_(14)                                              /**< (SERCOM_I2CS_CTRLB) Address Mode Position */
    584. 

  584. #define SERCOM_I2CS_CTRLB_AMODE_Msk           (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos)            /**< (SERCOM_I2CS_CTRLB) Address Mode Mask */
    585. 

  585. #define SERCOM_I2CS_CTRLB_AMODE(value)        (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos))
    586. 

  586. #define SERCOM_I2CS_CTRLB_CMD_Pos             _U_(16)                                              /**< (SERCOM_I2CS_CTRLB) Command Position */
    587. 

  587. #define SERCOM_I2CS_CTRLB_CMD_Msk             (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos)              /**< (SERCOM_I2CS_CTRLB) Command Mask */
    588. 

  588. #define SERCOM_I2CS_CTRLB_CMD(value)          (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos))
    589. 

  589. #define SERCOM_I2CS_CTRLB_ACKACT_Pos          _U_(18)                                              /**< (SERCOM_I2CS_CTRLB) Acknowledge Action Position */
    590. 

  590. #define SERCOM_I2CS_CTRLB_ACKACT_Msk          (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos)           /**< (SERCOM_I2CS_CTRLB) Acknowledge Action Mask */
    591. 

  591. #define SERCOM_I2CS_CTRLB_ACKACT(value)       (SERCOM_I2CS_CTRLB_ACKACT_Msk & ((value) << SERCOM_I2CS_CTRLB_ACKACT_Pos))
    592. 

  592. #define SERCOM_I2CS_CTRLB_Msk                 _U_(0x0007C700)                                      /**< (SERCOM_I2CS_CTRLB) Register Mask  */
    593. 

  593. 

  594. 

  595. /* -------- SERCOM_SPIM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPIM Control B -------- */
    596. 

  596. #define SERCOM_SPIM_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIM_CTRLB) SPIM Control B  Reset Value */
    597. 

  597. 

  598. #define SERCOM_SPIM_CTRLB_CHSIZE_Pos          _U_(0)                                               /**< (SERCOM_SPIM_CTRLB) Character Size Position */
    599. 

  599. #define SERCOM_SPIM_CTRLB_CHSIZE_Msk          (_U_(0x7) << SERCOM_SPIM_CTRLB_CHSIZE_Pos)           /**< (SERCOM_SPIM_CTRLB) Character Size Mask */
    600. 

  600. #define SERCOM_SPIM_CTRLB_CHSIZE(value)       (SERCOM_SPIM_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPIM_CTRLB_CHSIZE_Pos))
    601. 

  601. #define   SERCOM_SPIM_CTRLB_CHSIZE_8_BIT_Val  _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLB) 8 bits  */
    602. 

  602. #define   SERCOM_SPIM_CTRLB_CHSIZE_9_BIT_Val  _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLB) 9 bits  */
    603. 

  603. #define SERCOM_SPIM_CTRLB_CHSIZE_8_BIT        (SERCOM_SPIM_CTRLB_CHSIZE_8_BIT_Val << SERCOM_SPIM_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIM_CTRLB) 8 bits Position  */
    604. 

  604. #define SERCOM_SPIM_CTRLB_CHSIZE_9_BIT        (SERCOM_SPIM_CTRLB_CHSIZE_9_BIT_Val << SERCOM_SPIM_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIM_CTRLB) 9 bits Position  */
    605. 

  605. #define SERCOM_SPIM_CTRLB_PLOADEN_Pos         _U_(6)                                               /**< (SERCOM_SPIM_CTRLB) Data Preload Enable Position */
    606. 

  606. #define SERCOM_SPIM_CTRLB_PLOADEN_Msk         (_U_(0x1) << SERCOM_SPIM_CTRLB_PLOADEN_Pos)          /**< (SERCOM_SPIM_CTRLB) Data Preload Enable Mask */
    607. 

  607. #define SERCOM_SPIM_CTRLB_PLOADEN(value)      (SERCOM_SPIM_CTRLB_PLOADEN_Msk & ((value) << SERCOM_SPIM_CTRLB_PLOADEN_Pos))
    608. 

  608. #define SERCOM_SPIM_CTRLB_SSDE_Pos            _U_(9)                                               /**< (SERCOM_SPIM_CTRLB) Slave Select Low Detect Enable Position */
    609. 

  609. #define SERCOM_SPIM_CTRLB_SSDE_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLB_SSDE_Pos)             /**< (SERCOM_SPIM_CTRLB) Slave Select Low Detect Enable Mask */
    610. 

  610. #define SERCOM_SPIM_CTRLB_SSDE(value)         (SERCOM_SPIM_CTRLB_SSDE_Msk & ((value) << SERCOM_SPIM_CTRLB_SSDE_Pos))
    611. 

  611. #define SERCOM_SPIM_CTRLB_MSSEN_Pos           _U_(13)                                              /**< (SERCOM_SPIM_CTRLB) Master Slave Select Enable Position */
    612. 

  612. #define SERCOM_SPIM_CTRLB_MSSEN_Msk           (_U_(0x1) << SERCOM_SPIM_CTRLB_MSSEN_Pos)            /**< (SERCOM_SPIM_CTRLB) Master Slave Select Enable Mask */
    613. 

  613. #define SERCOM_SPIM_CTRLB_MSSEN(value)        (SERCOM_SPIM_CTRLB_MSSEN_Msk & ((value) << SERCOM_SPIM_CTRLB_MSSEN_Pos))
    614. 

  614. #define SERCOM_SPIM_CTRLB_AMODE_Pos           _U_(14)                                              /**< (SERCOM_SPIM_CTRLB) Address Mode Position */
    615. 

  615. #define SERCOM_SPIM_CTRLB_AMODE_Msk           (_U_(0x3) << SERCOM_SPIM_CTRLB_AMODE_Pos)            /**< (SERCOM_SPIM_CTRLB) Address Mode Mask */
    616. 

  616. #define SERCOM_SPIM_CTRLB_AMODE(value)        (SERCOM_SPIM_CTRLB_AMODE_Msk & ((value) << SERCOM_SPIM_CTRLB_AMODE_Pos))
    617. 

  617. #define   SERCOM_SPIM_CTRLB_AMODE_MASK_Val    _U_(0x0)                                             /**< (SERCOM_SPIM_CTRLB) SPI Address mask   */
    618. 

  618. #define   SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES_Val _U_(0x1)                                             /**< (SERCOM_SPIM_CTRLB) Two unique Addressess  */
    619. 

  619. #define   SERCOM_SPIM_CTRLB_AMODE_RANGE_Val   _U_(0x2)                                             /**< (SERCOM_SPIM_CTRLB) Address Range  */
    620. 

  620. #define SERCOM_SPIM_CTRLB_AMODE_MASK          (SERCOM_SPIM_CTRLB_AMODE_MASK_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /**< (SERCOM_SPIM_CTRLB) SPI Address mask  Position  */
    621. 

  621. #define SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES   (SERCOM_SPIM_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /**< (SERCOM_SPIM_CTRLB) Two unique Addressess Position  */
    622. 

  622. #define SERCOM_SPIM_CTRLB_AMODE_RANGE         (SERCOM_SPIM_CTRLB_AMODE_RANGE_Val << SERCOM_SPIM_CTRLB_AMODE_Pos) /**< (SERCOM_SPIM_CTRLB) Address Range Position  */
    623. 

  623. #define SERCOM_SPIM_CTRLB_RXEN_Pos            _U_(17)                                              /**< (SERCOM_SPIM_CTRLB) Receiver Enable Position */
    624. 

  624. #define SERCOM_SPIM_CTRLB_RXEN_Msk            (_U_(0x1) << SERCOM_SPIM_CTRLB_RXEN_Pos)             /**< (SERCOM_SPIM_CTRLB) Receiver Enable Mask */
    625. 

  625. #define SERCOM_SPIM_CTRLB_RXEN(value)         (SERCOM_SPIM_CTRLB_RXEN_Msk & ((value) << SERCOM_SPIM_CTRLB_RXEN_Pos))
    626. 

  626. #define SERCOM_SPIM_CTRLB_Msk                 _U_(0x0002E247)                                      /**< (SERCOM_SPIM_CTRLB) Register Mask  */
    627. 

  627. 

  628. 

  629. /* -------- SERCOM_SPIS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPIS Control B -------- */
    630. 

  630. #define SERCOM_SPIS_CTRLB_RESETVALUE          _U_(0x00)                                            /**<  (SERCOM_SPIS_CTRLB) SPIS Control B  Reset Value */
    631. 

  631. 

  632. #define SERCOM_SPIS_CTRLB_CHSIZE_Pos          _U_(0)                                               /**< (SERCOM_SPIS_CTRLB) Character Size Position */
    633. 

  633. #define SERCOM_SPIS_CTRLB_CHSIZE_Msk          (_U_(0x7) << SERCOM_SPIS_CTRLB_CHSIZE_Pos)           /**< (SERCOM_SPIS_CTRLB) Character Size Mask */
    634. 

  634. #define SERCOM_SPIS_CTRLB_CHSIZE(value)       (SERCOM_SPIS_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPIS_CTRLB_CHSIZE_Pos))
    635. 

  635. #define   SERCOM_SPIS_CTRLB_CHSIZE_8_BIT_Val  _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLB) 8 bits  */
    636. 

  636. #define   SERCOM_SPIS_CTRLB_CHSIZE_9_BIT_Val  _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLB) 9 bits  */
    637. 

  637. #define SERCOM_SPIS_CTRLB_CHSIZE_8_BIT        (SERCOM_SPIS_CTRLB_CHSIZE_8_BIT_Val << SERCOM_SPIS_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIS_CTRLB) 8 bits Position  */
    638. 

  638. #define SERCOM_SPIS_CTRLB_CHSIZE_9_BIT        (SERCOM_SPIS_CTRLB_CHSIZE_9_BIT_Val << SERCOM_SPIS_CTRLB_CHSIZE_Pos) /**< (SERCOM_SPIS_CTRLB) 9 bits Position  */
    639. 

  639. #define SERCOM_SPIS_CTRLB_PLOADEN_Pos         _U_(6)                                               /**< (SERCOM_SPIS_CTRLB) Data Preload Enable Position */
    640. 

  640. #define SERCOM_SPIS_CTRLB_PLOADEN_Msk         (_U_(0x1) << SERCOM_SPIS_CTRLB_PLOADEN_Pos)          /**< (SERCOM_SPIS_CTRLB) Data Preload Enable Mask */
    641. 

  641. #define SERCOM_SPIS_CTRLB_PLOADEN(value)      (SERCOM_SPIS_CTRLB_PLOADEN_Msk & ((value) << SERCOM_SPIS_CTRLB_PLOADEN_Pos))
    642. 

  642. #define SERCOM_SPIS_CTRLB_SSDE_Pos            _U_(9)                                               /**< (SERCOM_SPIS_CTRLB) Slave Select Low Detect Enable Position */
    643. 

  643. #define SERCOM_SPIS_CTRLB_SSDE_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLB_SSDE_Pos)             /**< (SERCOM_SPIS_CTRLB) Slave Select Low Detect Enable Mask */
    644. 

  644. #define SERCOM_SPIS_CTRLB_SSDE(value)         (SERCOM_SPIS_CTRLB_SSDE_Msk & ((value) << SERCOM_SPIS_CTRLB_SSDE_Pos))
    645. 

  645. #define SERCOM_SPIS_CTRLB_MSSEN_Pos           _U_(13)                                              /**< (SERCOM_SPIS_CTRLB) Master Slave Select Enable Position */
    646. 

  646. #define SERCOM_SPIS_CTRLB_MSSEN_Msk           (_U_(0x1) << SERCOM_SPIS_CTRLB_MSSEN_Pos)            /**< (SERCOM_SPIS_CTRLB) Master Slave Select Enable Mask */
    647. 

  647. #define SERCOM_SPIS_CTRLB_MSSEN(value)        (SERCOM_SPIS_CTRLB_MSSEN_Msk & ((value) << SERCOM_SPIS_CTRLB_MSSEN_Pos))
    648. 

  648. #define SERCOM_SPIS_CTRLB_AMODE_Pos           _U_(14)                                              /**< (SERCOM_SPIS_CTRLB) Address Mode Position */
    649. 

  649. #define SERCOM_SPIS_CTRLB_AMODE_Msk           (_U_(0x3) << SERCOM_SPIS_CTRLB_AMODE_Pos)            /**< (SERCOM_SPIS_CTRLB) Address Mode Mask */
    650. 

  650. #define SERCOM_SPIS_CTRLB_AMODE(value)        (SERCOM_SPIS_CTRLB_AMODE_Msk & ((value) << SERCOM_SPIS_CTRLB_AMODE_Pos))
    651. 

  651. #define   SERCOM_SPIS_CTRLB_AMODE_MASK_Val    _U_(0x0)                                             /**< (SERCOM_SPIS_CTRLB) SPI Address mask   */
    652. 

  652. #define   SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES_Val _U_(0x1)                                             /**< (SERCOM_SPIS_CTRLB) Two unique Addressess  */
    653. 

  653. #define   SERCOM_SPIS_CTRLB_AMODE_RANGE_Val   _U_(0x2)                                             /**< (SERCOM_SPIS_CTRLB) Address Range  */
    654. 

  654. #define SERCOM_SPIS_CTRLB_AMODE_MASK          (SERCOM_SPIS_CTRLB_AMODE_MASK_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /**< (SERCOM_SPIS_CTRLB) SPI Address mask  Position  */
    655. 

  655. #define SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES   (SERCOM_SPIS_CTRLB_AMODE_2_ADDRESSES_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /**< (SERCOM_SPIS_CTRLB) Two unique Addressess Position  */
    656. 

  656. #define SERCOM_SPIS_CTRLB_AMODE_RANGE         (SERCOM_SPIS_CTRLB_AMODE_RANGE_Val << SERCOM_SPIS_CTRLB_AMODE_Pos) /**< (SERCOM_SPIS_CTRLB) Address Range Position  */
    657. 

  657. #define SERCOM_SPIS_CTRLB_RXEN_Pos            _U_(17)                                              /**< (SERCOM_SPIS_CTRLB) Receiver Enable Position */
    658. 

  658. #define SERCOM_SPIS_CTRLB_RXEN_Msk            (_U_(0x1) << SERCOM_SPIS_CTRLB_RXEN_Pos)             /**< (SERCOM_SPIS_CTRLB) Receiver Enable Mask */
    659. 

  659. #define SERCOM_SPIS_CTRLB_RXEN(value)         (SERCOM_SPIS_CTRLB_RXEN_Msk & ((value) << SERCOM_SPIS_CTRLB_RXEN_Pos))
    660. 

  660. #define SERCOM_SPIS_CTRLB_Msk                 _U_(0x0002E247)                                      /**< (SERCOM_SPIS_CTRLB) Register Mask  */
    661. 

  661. 

  662. 

  663. /* -------- SERCOM_USART_EXT_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART_EXT Control B -------- */
    664. 

  664. #define SERCOM_USART_EXT_CTRLB_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_EXT_CTRLB) USART_EXT Control B  Reset Value */
    665. 

  665. 

  666. #define SERCOM_USART_EXT_CTRLB_CHSIZE_Pos     _U_(0)                                               /**< (SERCOM_USART_EXT_CTRLB) Character Size Position */
    667. 

  667. #define SERCOM_USART_EXT_CTRLB_CHSIZE_Msk     (_U_(0x7) << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos)      /**< (SERCOM_USART_EXT_CTRLB) Character Size Mask */
    668. 

  668. #define SERCOM_USART_EXT_CTRLB_CHSIZE(value)  (SERCOM_USART_EXT_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos))
    669. 

  669. #define   SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) 8 Bits  */
    670. 

  670. #define   SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) 9 Bits  */
    671. 

  671. #define   SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT_Val _U_(0x5)                                             /**< (SERCOM_USART_EXT_CTRLB) 5 Bits  */
    672. 

  672. #define   SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT_Val _U_(0x6)                                             /**< (SERCOM_USART_EXT_CTRLB) 6 Bits  */
    673. 

  673. #define   SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT_Val _U_(0x7)                                             /**< (SERCOM_USART_EXT_CTRLB) 7 Bits  */
    674. 

  674. #define SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_8_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 8 Bits Position  */
    675. 

  675. #define SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_9_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 9 Bits Position  */
    676. 

  676. #define SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_5_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 5 Bits Position  */
    677. 

  677. #define SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_6_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 6 Bits Position  */
    678. 

  678. #define SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT   (SERCOM_USART_EXT_CTRLB_CHSIZE_7_BIT_Val << SERCOM_USART_EXT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_EXT_CTRLB) 7 Bits Position  */
    679. 

  679. #define SERCOM_USART_EXT_CTRLB_SBMODE_Pos     _U_(6)                                               /**< (SERCOM_USART_EXT_CTRLB) Stop Bit Mode Position */
    680. 

  680. #define SERCOM_USART_EXT_CTRLB_SBMODE_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLB_SBMODE_Pos)      /**< (SERCOM_USART_EXT_CTRLB) Stop Bit Mode Mask */
    681. 

  681. #define SERCOM_USART_EXT_CTRLB_SBMODE(value)  (SERCOM_USART_EXT_CTRLB_SBMODE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_SBMODE_Pos))
    682. 

  682. #define   SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) One Stop Bit  */
    683. 

  683. #define   SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) Two Stop Bits  */
    684. 

  684. #define SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT   (SERCOM_USART_EXT_CTRLB_SBMODE_1_BIT_Val << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) One Stop Bit Position  */
    685. 

  685. #define SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT   (SERCOM_USART_EXT_CTRLB_SBMODE_2_BIT_Val << SERCOM_USART_EXT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) Two Stop Bits Position  */
    686. 

  686. #define SERCOM_USART_EXT_CTRLB_COLDEN_Pos     _U_(8)                                               /**< (SERCOM_USART_EXT_CTRLB) Collision Detection Enable Position */
    687. 

  687. #define SERCOM_USART_EXT_CTRLB_COLDEN_Msk     (_U_(0x1) << SERCOM_USART_EXT_CTRLB_COLDEN_Pos)      /**< (SERCOM_USART_EXT_CTRLB) Collision Detection Enable Mask */
    688. 

  688. #define SERCOM_USART_EXT_CTRLB_COLDEN(value)  (SERCOM_USART_EXT_CTRLB_COLDEN_Msk & ((value) << SERCOM_USART_EXT_CTRLB_COLDEN_Pos))
    689. 

  689. #define SERCOM_USART_EXT_CTRLB_SFDE_Pos       _U_(9)                                               /**< (SERCOM_USART_EXT_CTRLB) Start of Frame Detection Enable Position */
    690. 

  690. #define SERCOM_USART_EXT_CTRLB_SFDE_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLB_SFDE_Pos)        /**< (SERCOM_USART_EXT_CTRLB) Start of Frame Detection Enable Mask */
    691. 

  691. #define SERCOM_USART_EXT_CTRLB_SFDE(value)    (SERCOM_USART_EXT_CTRLB_SFDE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_SFDE_Pos))
    692. 

  692. #define SERCOM_USART_EXT_CTRLB_ENC_Pos        _U_(10)                                              /**< (SERCOM_USART_EXT_CTRLB) Encoding Format Position */
    693. 

  693. #define SERCOM_USART_EXT_CTRLB_ENC_Msk        (_U_(0x1) << SERCOM_USART_EXT_CTRLB_ENC_Pos)         /**< (SERCOM_USART_EXT_CTRLB) Encoding Format Mask */
    694. 

  694. #define SERCOM_USART_EXT_CTRLB_ENC(value)     (SERCOM_USART_EXT_CTRLB_ENC_Msk & ((value) << SERCOM_USART_EXT_CTRLB_ENC_Pos))
    695. 

  695. #define SERCOM_USART_EXT_CTRLB_PMODE_Pos      _U_(13)                                              /**< (SERCOM_USART_EXT_CTRLB) Parity Mode Position */
    696. 

  696. #define SERCOM_USART_EXT_CTRLB_PMODE_Msk      (_U_(0x1) << SERCOM_USART_EXT_CTRLB_PMODE_Pos)       /**< (SERCOM_USART_EXT_CTRLB) Parity Mode Mask */
    697. 

  697. #define SERCOM_USART_EXT_CTRLB_PMODE(value)   (SERCOM_USART_EXT_CTRLB_PMODE_Msk & ((value) << SERCOM_USART_EXT_CTRLB_PMODE_Pos))
    698. 

  698. #define   SERCOM_USART_EXT_CTRLB_PMODE_EVEN_Val _U_(0x0)                                             /**< (SERCOM_USART_EXT_CTRLB) Even Parity  */
    699. 

  699. #define   SERCOM_USART_EXT_CTRLB_PMODE_ODD_Val _U_(0x1)                                             /**< (SERCOM_USART_EXT_CTRLB) Odd Parity  */
    700. 

  700. #define SERCOM_USART_EXT_CTRLB_PMODE_EVEN     (SERCOM_USART_EXT_CTRLB_PMODE_EVEN_Val << SERCOM_USART_EXT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) Even Parity Position  */
    701. 

  701. #define SERCOM_USART_EXT_CTRLB_PMODE_ODD      (SERCOM_USART_EXT_CTRLB_PMODE_ODD_Val << SERCOM_USART_EXT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_EXT_CTRLB) Odd Parity Position  */
    702. 

  702. #define SERCOM_USART_EXT_CTRLB_TXEN_Pos       _U_(16)                                              /**< (SERCOM_USART_EXT_CTRLB) Transmitter Enable Position */
    703. 

  703. #define SERCOM_USART_EXT_CTRLB_TXEN_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLB_TXEN_Pos)        /**< (SERCOM_USART_EXT_CTRLB) Transmitter Enable Mask */
    704. 

  704. #define SERCOM_USART_EXT_CTRLB_TXEN(value)    (SERCOM_USART_EXT_CTRLB_TXEN_Msk & ((value) << SERCOM_USART_EXT_CTRLB_TXEN_Pos))
    705. 

  705. #define SERCOM_USART_EXT_CTRLB_RXEN_Pos       _U_(17)                                              /**< (SERCOM_USART_EXT_CTRLB) Receiver Enable Position */
    706. 

  706. #define SERCOM_USART_EXT_CTRLB_RXEN_Msk       (_U_(0x1) << SERCOM_USART_EXT_CTRLB_RXEN_Pos)        /**< (SERCOM_USART_EXT_CTRLB) Receiver Enable Mask */
    707. 

  707. #define SERCOM_USART_EXT_CTRLB_RXEN(value)    (SERCOM_USART_EXT_CTRLB_RXEN_Msk & ((value) << SERCOM_USART_EXT_CTRLB_RXEN_Pos))
    708. 

  708. #define SERCOM_USART_EXT_CTRLB_Msk            _U_(0x00032747)                                      /**< (SERCOM_USART_EXT_CTRLB) Register Mask  */
    709. 

  709. 

  710. 

  711. /* -------- SERCOM_USART_INT_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART_INT Control B -------- */
    712. 

  712. #define SERCOM_USART_INT_CTRLB_RESETVALUE     _U_(0x00)                                            /**<  (SERCOM_USART_INT_CTRLB) USART_INT Control B  Reset Value */
    713. 

  713. 

  714. #define SERCOM_USART_INT_CTRLB_CHSIZE_Pos     _U_(0)                                               /**< (SERCOM_USART_INT_CTRLB) Character Size Position */
    715. 

  715. #define SERCOM_USART_INT_CTRLB_CHSIZE_Msk     (_U_(0x7) << SERCOM_USART_INT_CTRLB_CHSIZE_Pos)      /**< (SERCOM_USART_INT_CTRLB) Character Size Mask */
    716. 

  716. #define SERCOM_USART_INT_CTRLB_CHSIZE(value)  (SERCOM_USART_INT_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_INT_CTRLB_CHSIZE_Pos))
    717. 

  717. #define   SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) 8 Bits  */
    718. 

  718. #define   SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) 9 Bits  */
    719. 

  719. #define   SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT_Val _U_(0x5)                                             /**< (SERCOM_USART_INT_CTRLB) 5 Bits  */
    720. 

  720. #define   SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT_Val _U_(0x6)                                             /**< (SERCOM_USART_INT_CTRLB) 6 Bits  */
    721. 

  721. #define   SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT_Val _U_(0x7)                                             /**< (SERCOM_USART_INT_CTRLB) 7 Bits  */
    722. 

  722. #define SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_8_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 8 Bits Position  */
    723. 

  723. #define SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_9_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 9 Bits Position  */
    724. 

  724. #define SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_5_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 5 Bits Position  */
    725. 

  725. #define SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_6_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 6 Bits Position  */
    726. 

  726. #define SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT   (SERCOM_USART_INT_CTRLB_CHSIZE_7_BIT_Val << SERCOM_USART_INT_CTRLB_CHSIZE_Pos) /**< (SERCOM_USART_INT_CTRLB) 7 Bits Position  */
    727. 

  727. #define SERCOM_USART_INT_CTRLB_SBMODE_Pos     _U_(6)                                               /**< (SERCOM_USART_INT_CTRLB) Stop Bit Mode Position */
    728. 

  728. #define SERCOM_USART_INT_CTRLB_SBMODE_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLB_SBMODE_Pos)      /**< (SERCOM_USART_INT_CTRLB) Stop Bit Mode Mask */
    729. 

  729. #define SERCOM_USART_INT_CTRLB_SBMODE(value)  (SERCOM_USART_INT_CTRLB_SBMODE_Msk & ((value) << SERCOM_USART_INT_CTRLB_SBMODE_Pos))
    730. 

  730. #define   SERCOM_USART_INT_CTRLB_SBMODE_1_BIT_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) One Stop Bit  */
    731. 

  731. #define   SERCOM_USART_INT_CTRLB_SBMODE_2_BIT_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) Two Stop Bits  */
    732. 

  732. #define SERCOM_USART_INT_CTRLB_SBMODE_1_BIT   (SERCOM_USART_INT_CTRLB_SBMODE_1_BIT_Val << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) One Stop Bit Position  */
    733. 

  733. #define SERCOM_USART_INT_CTRLB_SBMODE_2_BIT   (SERCOM_USART_INT_CTRLB_SBMODE_2_BIT_Val << SERCOM_USART_INT_CTRLB_SBMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) Two Stop Bits Position  */
    734. 

  734. #define SERCOM_USART_INT_CTRLB_COLDEN_Pos     _U_(8)                                               /**< (SERCOM_USART_INT_CTRLB) Collision Detection Enable Position */
    735. 

  735. #define SERCOM_USART_INT_CTRLB_COLDEN_Msk     (_U_(0x1) << SERCOM_USART_INT_CTRLB_COLDEN_Pos)      /**< (SERCOM_USART_INT_CTRLB) Collision Detection Enable Mask */
    736. 

  736. #define SERCOM_USART_INT_CTRLB_COLDEN(value)  (SERCOM_USART_INT_CTRLB_COLDEN_Msk & ((value) << SERCOM_USART_INT_CTRLB_COLDEN_Pos))
    737. 

  737. #define SERCOM_USART_INT_CTRLB_SFDE_Pos       _U_(9)                                               /**< (SERCOM_USART_INT_CTRLB) Start of Frame Detection Enable Position */
    738. 

  738. #define SERCOM_USART_INT_CTRLB_SFDE_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLB_SFDE_Pos)        /**< (SERCOM_USART_INT_CTRLB) Start of Frame Detection Enable Mask */
    739. 

  739. #define SERCOM_USART_INT_CTRLB_SFDE(value)    (SERCOM_USART_INT_CTRLB_SFDE_Msk & ((value) << SERCOM_USART_INT_CTRLB_SFDE_Pos))
    740. 

  740. #define SERCOM_USART_INT_CTRLB_ENC_Pos        _U_(10)                                              /**< (SERCOM_USART_INT_CTRLB) Encoding Format Position */
    741. 

  741. #define SERCOM_USART_INT_CTRLB_ENC_Msk        (_U_(0x1) << SERCOM_USART_INT_CTRLB_ENC_Pos)         /**< (SERCOM_USART_INT_CTRLB) Encoding Format Mask */
    742. 

  742. #define SERCOM_USART_INT_CTRLB_ENC(value)     (SERCOM_USART_INT_CTRLB_ENC_Msk & ((value) << SERCOM_USART_INT_CTRLB_ENC_Pos))
    743. 

  743. #define SERCOM_USART_INT_CTRLB_PMODE_Pos      _U_(13)                                              /**< (SERCOM_USART_INT_CTRLB) Parity Mode Position */
    744. 

  744. #define SERCOM_USART_INT_CTRLB_PMODE_Msk      (_U_(0x1) << SERCOM_USART_INT_CTRLB_PMODE_Pos)       /**< (SERCOM_USART_INT_CTRLB) Parity Mode Mask */
    745. 

  745. #define SERCOM_USART_INT_CTRLB_PMODE(value)   (SERCOM_USART_INT_CTRLB_PMODE_Msk & ((value) << SERCOM_USART_INT_CTRLB_PMODE_Pos))
    746. 

  746. #define   SERCOM_USART_INT_CTRLB_PMODE_EVEN_Val _U_(0x0)                                             /**< (SERCOM_USART_INT_CTRLB) Even Parity  */
    747. 

  747. #define   SERCOM_USART_INT_CTRLB_PMODE_ODD_Val _U_(0x1)                                             /**< (SERCOM_USART_INT_CTRLB) Odd Parity  */
    748. 

  748. #define SERCOM_USART_INT_CTRLB_PMODE_EVEN     (SERCOM_USART_INT_CTRLB_PMODE_EVEN_Val << SERCOM_USART_INT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) Even Parity Position  */
    749. 

  749. #define SERCOM_USART_INT_CTRLB_PMODE_ODD      (SERCOM_USART_INT_CTRLB_PMODE_ODD_Val << SERCOM_USART_INT_CTRLB_PMODE_Pos) /**< (SERCOM_USART_INT_CTRLB) Odd Parity Position  */
    750. 

  750. #define SERCOM_USART_INT_CTRLB_TXEN_Pos       _U_(16)                                              /**< (SERCOM_USART_INT_CTRLB) Transmitter Enable Position */
    751. 

  751. #define SERCOM_USART_INT_CTRLB_TXEN_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLB_TXEN_Pos)        /**< (SERCOM_USART_INT_CTRLB) Transmitter Enable Mask */
    752. 

  752. #define SERCOM_USART_INT_CTRLB_TXEN(value)    (SERCOM_USART_INT_CTRLB_TXEN_Msk & ((value) << SERCOM_USART_INT_CTRLB_TXEN_Pos))
    753. 

  753. #define SERCOM_USART_INT_CTRLB_RXEN_Pos       _U_(17)                                              /**< (SERCOM_USART_INT_CTRLB) Receiver Enable Position */
    754. 

  754. #define SERCOM_USART_INT_CTRLB_RXEN_Msk       (_U_(0x1) << SERCOM_USART_INT_CTRLB_RXEN_Pos)        /**< (SERCOM_USART_INT_CTRLB) Receiver Enable Mask */
    755. 

  755. #define SERCOM_USART_INT_CTRLB_RXEN(value)    (SERCOM_USART_INT_CTRLB_RXEN_Msk & ((value) << SERCOM_USART_INT_CTRLB_RXEN_Pos))
    756. 

  756. #define SERCOM_USART_INT_CTRLB_Msk            _U_(0x00032747)                                      /**< (SERCOM_USART_INT_CTRLB) Register Mask  */
    757. 

  757. 

  758. 

  759. /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM Baud Rate -------- */
    760. 

  760. #define SERCOM_I2CM_BAUD_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CM_BAUD) I2CM Baud Rate  Reset Value */
    761. 

  761. 

  762. #define SERCOM_I2CM_BAUD_BAUD_Pos             _U_(0)                                               /**< (SERCOM_I2CM_BAUD) Baud Rate Value Position */
    763. 

  763. #define SERCOM_I2CM_BAUD_BAUD_Msk             (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos)             /**< (SERCOM_I2CM_BAUD) Baud Rate Value Mask */
    764. 

  764. #define SERCOM_I2CM_BAUD_BAUD(value)          (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos))
    765. 

  765. #define SERCOM_I2CM_BAUD_BAUDLOW_Pos          _U_(8)                                               /**< (SERCOM_I2CM_BAUD) Baud Rate Value Low Position */
    766. 

  766. #define SERCOM_I2CM_BAUD_BAUDLOW_Msk          (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)          /**< (SERCOM_I2CM_BAUD) Baud Rate Value Low Mask */
    767. 

  767. #define SERCOM_I2CM_BAUD_BAUDLOW(value)       (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos))
    768. 

  768. #define SERCOM_I2CM_BAUD_HSBAUD_Pos           _U_(16)                                              /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Position */
    769. 

  769. #define SERCOM_I2CM_BAUD_HSBAUD_Msk           (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos)           /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Mask */
    770. 

  770. #define SERCOM_I2CM_BAUD_HSBAUD(value)        (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos))
    771. 

  771. #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos        _U_(24)                                              /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Position */
    772. 

  772. #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk        (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)        /**< (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low Mask */
    773. 

  773. #define SERCOM_I2CM_BAUD_HSBAUDLOW(value)     (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos))
    774. 

  774. #define SERCOM_I2CM_BAUD_Msk                  _U_(0xFFFFFFFF)                                      /**< (SERCOM_I2CM_BAUD) Register Mask  */
    775. 

  775. 

  776. 

  777. /* -------- SERCOM_SPIM_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPIM Baud Rate -------- */
    778. 

  778. #define SERCOM_SPIM_BAUD_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIM_BAUD) SPIM Baud Rate  Reset Value */
    779. 

  779. 

  780. #define SERCOM_SPIM_BAUD_BAUD_Pos             _U_(0)                                               /**< (SERCOM_SPIM_BAUD) Baud Rate Value Position */
    781. 

  781. #define SERCOM_SPIM_BAUD_BAUD_Msk             (_U_(0xFF) << SERCOM_SPIM_BAUD_BAUD_Pos)             /**< (SERCOM_SPIM_BAUD) Baud Rate Value Mask */
    782. 

  782. #define SERCOM_SPIM_BAUD_BAUD(value)          (SERCOM_SPIM_BAUD_BAUD_Msk & ((value) << SERCOM_SPIM_BAUD_BAUD_Pos))
    783. 

  783. #define SERCOM_SPIM_BAUD_Msk                  _U_(0xFF)                                            /**< (SERCOM_SPIM_BAUD) Register Mask  */
    784. 

  784. 

  785. 

  786. /* -------- SERCOM_SPIS_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPIS Baud Rate -------- */
    787. 

  787. #define SERCOM_SPIS_BAUD_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIS_BAUD) SPIS Baud Rate  Reset Value */
    788. 

  788. 

  789. #define SERCOM_SPIS_BAUD_BAUD_Pos             _U_(0)                                               /**< (SERCOM_SPIS_BAUD) Baud Rate Value Position */
    790. 

  790. #define SERCOM_SPIS_BAUD_BAUD_Msk             (_U_(0xFF) << SERCOM_SPIS_BAUD_BAUD_Pos)             /**< (SERCOM_SPIS_BAUD) Baud Rate Value Mask */
    791. 

  791. #define SERCOM_SPIS_BAUD_BAUD(value)          (SERCOM_SPIS_BAUD_BAUD_Msk & ((value) << SERCOM_SPIS_BAUD_BAUD_Pos))
    792. 

  792. #define SERCOM_SPIS_BAUD_Msk                  _U_(0xFF)                                            /**< (SERCOM_SPIS_BAUD) Register Mask  */
    793. 

  793. 

  794. 

  795. /* -------- SERCOM_USART_EXT_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART_EXT Baud Rate -------- */
    796. 

  796. #define SERCOM_USART_EXT_BAUD_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_EXT_BAUD) USART_EXT Baud Rate  Reset Value */
    797. 

  797. 

  798. #define SERCOM_USART_EXT_BAUD_BAUD_Pos        _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
    799. 

  799. #define SERCOM_USART_EXT_BAUD_BAUD_Msk        (_U_(0xFFFF) << SERCOM_USART_EXT_BAUD_BAUD_Pos)      /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
    800. 

  800. #define SERCOM_USART_EXT_BAUD_BAUD(value)     (SERCOM_USART_EXT_BAUD_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_BAUD_Pos))
    801. 

  801. #define SERCOM_USART_EXT_BAUD_Msk             _U_(0xFFFF)                                          /**< (SERCOM_USART_EXT_BAUD) Register Mask  */
    802. 

  802. 

  803. /* FRAC mode */
    804. 

  804. #define SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos   _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
    805. 

  805. #define SERCOM_USART_EXT_BAUD_FRAC_BAUD_Msk   (_U_(0x1FFF) << SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos) /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
    806. 

  806. #define SERCOM_USART_EXT_BAUD_FRAC_BAUD(value) (SERCOM_USART_EXT_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRAC_BAUD_Pos))
    807. 

  807. #define SERCOM_USART_EXT_BAUD_FRAC_FP_Pos     _U_(13)                                              /**< (SERCOM_USART_EXT_BAUD) Fractional Part Position */
    808. 

  808. #define SERCOM_USART_EXT_BAUD_FRAC_FP_Msk     (_U_(0x7) << SERCOM_USART_EXT_BAUD_FRAC_FP_Pos)      /**< (SERCOM_USART_EXT_BAUD) Fractional Part Mask */
    809. 

  809. #define SERCOM_USART_EXT_BAUD_FRAC_FP(value)  (SERCOM_USART_EXT_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRAC_FP_Pos))
    810. 

  810. #define SERCOM_USART_EXT_BAUD_FRAC_Msk        _U_(0xFFFF)                                           /**< (SERCOM_USART_EXT_BAUD_FRAC) Register Mask  */
    811. 

  811. 

  812. /* FRACFP mode */
    813. 

  813. #define SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
    814. 

  814. #define SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos) /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
    815. 

  815. #define SERCOM_USART_EXT_BAUD_FRACFP_BAUD(value) (SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRACFP_BAUD_Pos))
    816. 

  816. #define SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos   _U_(13)                                              /**< (SERCOM_USART_EXT_BAUD) Fractional Part Position */
    817. 

  817. #define SERCOM_USART_EXT_BAUD_FRACFP_FP_Msk   (_U_(0x7) << SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos)    /**< (SERCOM_USART_EXT_BAUD) Fractional Part Mask */
    818. 

  818. #define SERCOM_USART_EXT_BAUD_FRACFP_FP(value) (SERCOM_USART_EXT_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_EXT_BAUD_FRACFP_FP_Pos))
    819. 

  819. #define SERCOM_USART_EXT_BAUD_FRACFP_Msk      _U_(0xFFFF)                                           /**< (SERCOM_USART_EXT_BAUD_FRACFP) Register Mask  */
    820. 

  820. 

  821. /* USARTFP mode */
    822. 

  822. #define SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Position */
    823. 

  823. #define SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos) /**< (SERCOM_USART_EXT_BAUD) Baud Rate Value Mask */
    824. 

  824. #define SERCOM_USART_EXT_BAUD_USARTFP_BAUD(value) (SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_EXT_BAUD_USARTFP_BAUD_Pos))
    825. 

  825. #define SERCOM_USART_EXT_BAUD_USARTFP_Msk     _U_(0xFFFF)                                           /**< (SERCOM_USART_EXT_BAUD_USARTFP) Register Mask  */
    826. 

  826. 

  827. 

  828. /* -------- SERCOM_USART_INT_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART_INT Baud Rate -------- */
    829. 

  829. #define SERCOM_USART_INT_BAUD_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_INT_BAUD) USART_INT Baud Rate  Reset Value */
    830. 

  830. 

  831. #define SERCOM_USART_INT_BAUD_BAUD_Pos        _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
    832. 

  832. #define SERCOM_USART_INT_BAUD_BAUD_Msk        (_U_(0xFFFF) << SERCOM_USART_INT_BAUD_BAUD_Pos)      /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
    833. 

  833. #define SERCOM_USART_INT_BAUD_BAUD(value)     (SERCOM_USART_INT_BAUD_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_BAUD_Pos))
    834. 

  834. #define SERCOM_USART_INT_BAUD_Msk             _U_(0xFFFF)                                          /**< (SERCOM_USART_INT_BAUD) Register Mask  */
    835. 

  835. 

  836. /* FRAC mode */
    837. 

  837. #define SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos   _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
    838. 

  838. #define SERCOM_USART_INT_BAUD_FRAC_BAUD_Msk   (_U_(0x1FFF) << SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos) /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
    839. 

  839. #define SERCOM_USART_INT_BAUD_FRAC_BAUD(value) (SERCOM_USART_INT_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_FRAC_BAUD_Pos))
    840. 

  840. #define SERCOM_USART_INT_BAUD_FRAC_FP_Pos     _U_(13)                                              /**< (SERCOM_USART_INT_BAUD) Fractional Part Position */
    841. 

  841. #define SERCOM_USART_INT_BAUD_FRAC_FP_Msk     (_U_(0x7) << SERCOM_USART_INT_BAUD_FRAC_FP_Pos)      /**< (SERCOM_USART_INT_BAUD) Fractional Part Mask */
    842. 

  842. #define SERCOM_USART_INT_BAUD_FRAC_FP(value)  (SERCOM_USART_INT_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_INT_BAUD_FRAC_FP_Pos))
    843. 

  843. #define SERCOM_USART_INT_BAUD_FRAC_Msk        _U_(0xFFFF)                                           /**< (SERCOM_USART_INT_BAUD_FRAC) Register Mask  */
    844. 

  844. 

  845. /* FRACFP mode */
    846. 

  846. #define SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
    847. 

  847. #define SERCOM_USART_INT_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos) /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
    848. 

  848. #define SERCOM_USART_INT_BAUD_FRACFP_BAUD(value) (SERCOM_USART_INT_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_FRACFP_BAUD_Pos))
    849. 

  849. #define SERCOM_USART_INT_BAUD_FRACFP_FP_Pos   _U_(13)                                              /**< (SERCOM_USART_INT_BAUD) Fractional Part Position */
    850. 

  850. #define SERCOM_USART_INT_BAUD_FRACFP_FP_Msk   (_U_(0x7) << SERCOM_USART_INT_BAUD_FRACFP_FP_Pos)    /**< (SERCOM_USART_INT_BAUD) Fractional Part Mask */
    851. 

  851. #define SERCOM_USART_INT_BAUD_FRACFP_FP(value) (SERCOM_USART_INT_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_INT_BAUD_FRACFP_FP_Pos))
    852. 

  852. #define SERCOM_USART_INT_BAUD_FRACFP_Msk      _U_(0xFFFF)                                           /**< (SERCOM_USART_INT_BAUD_FRACFP) Register Mask  */
    853. 

  853. 

  854. /* USARTFP mode */
    855. 

  855. #define SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos _U_(0)                                               /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Position */
    856. 

  856. #define SERCOM_USART_INT_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos) /**< (SERCOM_USART_INT_BAUD) Baud Rate Value Mask */
    857. 

  857. #define SERCOM_USART_INT_BAUD_USARTFP_BAUD(value) (SERCOM_USART_INT_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_INT_BAUD_USARTFP_BAUD_Pos))
    858. 

  858. #define SERCOM_USART_INT_BAUD_USARTFP_Msk     _U_(0xFFFF)                                           /**< (SERCOM_USART_INT_BAUD_USARTFP) Register Mask  */
    859. 

  859. 

  860. 

  861. /* -------- SERCOM_USART_EXT_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART_EXT Receive Pulse Length -------- */
    862. 

  862. #define SERCOM_USART_EXT_RXPL_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_EXT_RXPL) USART_EXT Receive Pulse Length  Reset Value */
    863. 

  863. 

  864. #define SERCOM_USART_EXT_RXPL_RXPL_Pos        _U_(0)                                               /**< (SERCOM_USART_EXT_RXPL) Receive Pulse Length Position */
    865. 

  865. #define SERCOM_USART_EXT_RXPL_RXPL_Msk        (_U_(0xFF) << SERCOM_USART_EXT_RXPL_RXPL_Pos)        /**< (SERCOM_USART_EXT_RXPL) Receive Pulse Length Mask */
    866. 

  866. #define SERCOM_USART_EXT_RXPL_RXPL(value)     (SERCOM_USART_EXT_RXPL_RXPL_Msk & ((value) << SERCOM_USART_EXT_RXPL_RXPL_Pos))
    867. 

  867. #define SERCOM_USART_EXT_RXPL_Msk             _U_(0xFF)                                            /**< (SERCOM_USART_EXT_RXPL) Register Mask  */
    868. 

  868. 

  869. 

  870. /* -------- SERCOM_USART_INT_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART_INT Receive Pulse Length -------- */
    871. 

  871. #define SERCOM_USART_INT_RXPL_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_INT_RXPL) USART_INT Receive Pulse Length  Reset Value */
    872. 

  872. 

  873. #define SERCOM_USART_INT_RXPL_RXPL_Pos        _U_(0)                                               /**< (SERCOM_USART_INT_RXPL) Receive Pulse Length Position */
    874. 

  874. #define SERCOM_USART_INT_RXPL_RXPL_Msk        (_U_(0xFF) << SERCOM_USART_INT_RXPL_RXPL_Pos)        /**< (SERCOM_USART_INT_RXPL) Receive Pulse Length Mask */
    875. 

  875. #define SERCOM_USART_INT_RXPL_RXPL(value)     (SERCOM_USART_INT_RXPL_RXPL_Msk & ((value) << SERCOM_USART_INT_RXPL_RXPL_Pos))
    876. 

  876. #define SERCOM_USART_INT_RXPL_Msk             _U_(0xFF)                                            /**< (SERCOM_USART_INT_RXPL) Register Mask  */
    877. 

  877. 

  878. 

  879. /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM Interrupt Enable Clear -------- */
    880. 

  880. #define SERCOM_I2CM_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear  Reset Value */
    881. 

  881. 

  882. #define SERCOM_I2CM_INTENCLR_MB_Pos           _U_(0)                                               /**< (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Position */
    883. 

  883. #define SERCOM_I2CM_INTENCLR_MB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos)            /**< (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable Mask */
    884. 

  884. #define SERCOM_I2CM_INTENCLR_MB(value)        (SERCOM_I2CM_INTENCLR_MB_Msk & ((value) << SERCOM_I2CM_INTENCLR_MB_Pos))
    885. 

  885. #define SERCOM_I2CM_INTENCLR_SB_Pos           _U_(1)                                               /**< (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Position */
    886. 

  886. #define SERCOM_I2CM_INTENCLR_SB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos)            /**< (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable Mask */
    887. 

  887. #define SERCOM_I2CM_INTENCLR_SB(value)        (SERCOM_I2CM_INTENCLR_SB_Msk & ((value) << SERCOM_I2CM_INTENCLR_SB_Pos))
    888. 

  888. #define SERCOM_I2CM_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Position */
    889. 

  889. #define SERCOM_I2CM_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos)         /**< (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable Mask */
    890. 

  890. #define SERCOM_I2CM_INTENCLR_ERROR(value)     (SERCOM_I2CM_INTENCLR_ERROR_Msk & ((value) << SERCOM_I2CM_INTENCLR_ERROR_Pos))
    891. 

  891. #define SERCOM_I2CM_INTENCLR_Msk              _U_(0x83)                                            /**< (SERCOM_I2CM_INTENCLR) Register Mask  */
    892. 

  892. 

  893. 

  894. /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS Interrupt Enable Clear -------- */
    895. 

  895. #define SERCOM_I2CS_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear  Reset Value */
    896. 

  896. 

  897. #define SERCOM_I2CS_INTENCLR_PREC_Pos         _U_(0)                                               /**< (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Position */
    898. 

  898. #define SERCOM_I2CS_INTENCLR_PREC_Msk         (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos)          /**< (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable Mask */
    899. 

  899. #define SERCOM_I2CS_INTENCLR_PREC(value)      (SERCOM_I2CS_INTENCLR_PREC_Msk & ((value) << SERCOM_I2CS_INTENCLR_PREC_Pos))
    900. 

  900. #define SERCOM_I2CS_INTENCLR_AMATCH_Pos       _U_(1)                                               /**< (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Position */
    901. 

  901. #define SERCOM_I2CS_INTENCLR_AMATCH_Msk       (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos)        /**< (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable Mask */
    902. 

  902. #define SERCOM_I2CS_INTENCLR_AMATCH(value)    (SERCOM_I2CS_INTENCLR_AMATCH_Msk & ((value) << SERCOM_I2CS_INTENCLR_AMATCH_Pos))
    903. 

  903. #define SERCOM_I2CS_INTENCLR_DRDY_Pos         _U_(2)                                               /**< (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Position */
    904. 

  904. #define SERCOM_I2CS_INTENCLR_DRDY_Msk         (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos)          /**< (SERCOM_I2CS_INTENCLR) Data Interrupt Disable Mask */
    905. 

  905. #define SERCOM_I2CS_INTENCLR_DRDY(value)      (SERCOM_I2CS_INTENCLR_DRDY_Msk & ((value) << SERCOM_I2CS_INTENCLR_DRDY_Pos))
    906. 

  906. #define SERCOM_I2CS_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Position */
    907. 

  907. #define SERCOM_I2CS_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos)         /**< (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable Mask */
    908. 

  908. #define SERCOM_I2CS_INTENCLR_ERROR(value)     (SERCOM_I2CS_INTENCLR_ERROR_Msk & ((value) << SERCOM_I2CS_INTENCLR_ERROR_Pos))
    909. 

  909. #define SERCOM_I2CS_INTENCLR_Msk              _U_(0x87)                                            /**< (SERCOM_I2CS_INTENCLR) Register Mask  */
    910. 

  910. 

  911. 

  912. /* -------- SERCOM_SPIM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPIM Interrupt Enable Clear -------- */
    913. 

  913. #define SERCOM_SPIM_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIM_INTENCLR) SPIM Interrupt Enable Clear  Reset Value */
    914. 

  914. 

  915. #define SERCOM_SPIM_INTENCLR_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIM_INTENCLR) Data Register Empty Interrupt Disable Position */
    916. 

  916. #define SERCOM_SPIM_INTENCLR_DRE_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_DRE_Pos)           /**< (SERCOM_SPIM_INTENCLR) Data Register Empty Interrupt Disable Mask */
    917. 

  917. #define SERCOM_SPIM_INTENCLR_DRE(value)       (SERCOM_SPIM_INTENCLR_DRE_Msk & ((value) << SERCOM_SPIM_INTENCLR_DRE_Pos))
    918. 

  918. #define SERCOM_SPIM_INTENCLR_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIM_INTENCLR) Transmit Complete Interrupt Disable Position */
    919. 

  919. #define SERCOM_SPIM_INTENCLR_TXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_TXC_Pos)           /**< (SERCOM_SPIM_INTENCLR) Transmit Complete Interrupt Disable Mask */
    920. 

  920. #define SERCOM_SPIM_INTENCLR_TXC(value)       (SERCOM_SPIM_INTENCLR_TXC_Msk & ((value) << SERCOM_SPIM_INTENCLR_TXC_Pos))
    921. 

  921. #define SERCOM_SPIM_INTENCLR_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIM_INTENCLR) Receive Complete Interrupt Disable Position */
    922. 

  922. #define SERCOM_SPIM_INTENCLR_RXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_RXC_Pos)           /**< (SERCOM_SPIM_INTENCLR) Receive Complete Interrupt Disable Mask */
    923. 

  923. #define SERCOM_SPIM_INTENCLR_RXC(value)       (SERCOM_SPIM_INTENCLR_RXC_Msk & ((value) << SERCOM_SPIM_INTENCLR_RXC_Pos))
    924. 

  924. #define SERCOM_SPIM_INTENCLR_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIM_INTENCLR) Slave Select Low Interrupt Disable Position */
    925. 

  925. #define SERCOM_SPIM_INTENCLR_SSL_Msk          (_U_(0x1) << SERCOM_SPIM_INTENCLR_SSL_Pos)           /**< (SERCOM_SPIM_INTENCLR) Slave Select Low Interrupt Disable Mask */
    926. 

  926. #define SERCOM_SPIM_INTENCLR_SSL(value)       (SERCOM_SPIM_INTENCLR_SSL_Msk & ((value) << SERCOM_SPIM_INTENCLR_SSL_Pos))
    927. 

  927. #define SERCOM_SPIM_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIM_INTENCLR) Combined Error Interrupt Disable Position */
    928. 

  928. #define SERCOM_SPIM_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_SPIM_INTENCLR_ERROR_Pos)         /**< (SERCOM_SPIM_INTENCLR) Combined Error Interrupt Disable Mask */
    929. 

  929. #define SERCOM_SPIM_INTENCLR_ERROR(value)     (SERCOM_SPIM_INTENCLR_ERROR_Msk & ((value) << SERCOM_SPIM_INTENCLR_ERROR_Pos))
    930. 

  930. #define SERCOM_SPIM_INTENCLR_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIM_INTENCLR) Register Mask  */
    931. 

  931. 

  932. 

  933. /* -------- SERCOM_SPIS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPIS Interrupt Enable Clear -------- */
    934. 

  934. #define SERCOM_SPIS_INTENCLR_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIS_INTENCLR) SPIS Interrupt Enable Clear  Reset Value */
    935. 

  935. 

  936. #define SERCOM_SPIS_INTENCLR_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIS_INTENCLR) Data Register Empty Interrupt Disable Position */
    937. 

  937. #define SERCOM_SPIS_INTENCLR_DRE_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_DRE_Pos)           /**< (SERCOM_SPIS_INTENCLR) Data Register Empty Interrupt Disable Mask */
    938. 

  938. #define SERCOM_SPIS_INTENCLR_DRE(value)       (SERCOM_SPIS_INTENCLR_DRE_Msk & ((value) << SERCOM_SPIS_INTENCLR_DRE_Pos))
    939. 

  939. #define SERCOM_SPIS_INTENCLR_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIS_INTENCLR) Transmit Complete Interrupt Disable Position */
    940. 

  940. #define SERCOM_SPIS_INTENCLR_TXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_TXC_Pos)           /**< (SERCOM_SPIS_INTENCLR) Transmit Complete Interrupt Disable Mask */
    941. 

  941. #define SERCOM_SPIS_INTENCLR_TXC(value)       (SERCOM_SPIS_INTENCLR_TXC_Msk & ((value) << SERCOM_SPIS_INTENCLR_TXC_Pos))
    942. 

  942. #define SERCOM_SPIS_INTENCLR_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIS_INTENCLR) Receive Complete Interrupt Disable Position */
    943. 

  943. #define SERCOM_SPIS_INTENCLR_RXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_RXC_Pos)           /**< (SERCOM_SPIS_INTENCLR) Receive Complete Interrupt Disable Mask */
    944. 

  944. #define SERCOM_SPIS_INTENCLR_RXC(value)       (SERCOM_SPIS_INTENCLR_RXC_Msk & ((value) << SERCOM_SPIS_INTENCLR_RXC_Pos))
    945. 

  945. #define SERCOM_SPIS_INTENCLR_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIS_INTENCLR) Slave Select Low Interrupt Disable Position */
    946. 

  946. #define SERCOM_SPIS_INTENCLR_SSL_Msk          (_U_(0x1) << SERCOM_SPIS_INTENCLR_SSL_Pos)           /**< (SERCOM_SPIS_INTENCLR) Slave Select Low Interrupt Disable Mask */
    947. 

  947. #define SERCOM_SPIS_INTENCLR_SSL(value)       (SERCOM_SPIS_INTENCLR_SSL_Msk & ((value) << SERCOM_SPIS_INTENCLR_SSL_Pos))
    948. 

  948. #define SERCOM_SPIS_INTENCLR_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIS_INTENCLR) Combined Error Interrupt Disable Position */
    949. 

  949. #define SERCOM_SPIS_INTENCLR_ERROR_Msk        (_U_(0x1) << SERCOM_SPIS_INTENCLR_ERROR_Pos)         /**< (SERCOM_SPIS_INTENCLR) Combined Error Interrupt Disable Mask */
    950. 

  950. #define SERCOM_SPIS_INTENCLR_ERROR(value)     (SERCOM_SPIS_INTENCLR_ERROR_Msk & ((value) << SERCOM_SPIS_INTENCLR_ERROR_Pos))
    951. 

  951. #define SERCOM_SPIS_INTENCLR_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIS_INTENCLR) Register Mask  */
    952. 

  952. 

  953. 

  954. /* -------- SERCOM_USART_EXT_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART_EXT Interrupt Enable Clear -------- */
    955. 

  955. #define SERCOM_USART_EXT_INTENCLR_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_INTENCLR) USART_EXT Interrupt Enable Clear  Reset Value */
    956. 

  956. 

  957. #define SERCOM_USART_EXT_INTENCLR_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_EXT_INTENCLR) Data Register Empty Interrupt Disable Position */
    958. 

  958. #define SERCOM_USART_EXT_INTENCLR_DRE_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_DRE_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Data Register Empty Interrupt Disable Mask */
    959. 

  959. #define SERCOM_USART_EXT_INTENCLR_DRE(value)  (SERCOM_USART_EXT_INTENCLR_DRE_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_DRE_Pos))
    960. 

  960. #define SERCOM_USART_EXT_INTENCLR_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_EXT_INTENCLR) Transmit Complete Interrupt Disable Position */
    961. 

  961. #define SERCOM_USART_EXT_INTENCLR_TXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_TXC_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Transmit Complete Interrupt Disable Mask */
    962. 

  962. #define SERCOM_USART_EXT_INTENCLR_TXC(value)  (SERCOM_USART_EXT_INTENCLR_TXC_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_TXC_Pos))
    963. 

  963. #define SERCOM_USART_EXT_INTENCLR_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_EXT_INTENCLR) Receive Complete Interrupt Disable Position */
    964. 

  964. #define SERCOM_USART_EXT_INTENCLR_RXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_RXC_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Receive Complete Interrupt Disable Mask */
    965. 

  965. #define SERCOM_USART_EXT_INTENCLR_RXC(value)  (SERCOM_USART_EXT_INTENCLR_RXC_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_RXC_Pos))
    966. 

  966. #define SERCOM_USART_EXT_INTENCLR_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_EXT_INTENCLR) Receive Start Interrupt Disable Position */
    967. 

  967. #define SERCOM_USART_EXT_INTENCLR_RXS_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_RXS_Pos)      /**< (SERCOM_USART_EXT_INTENCLR) Receive Start Interrupt Disable Mask */
    968. 

  968. #define SERCOM_USART_EXT_INTENCLR_RXS(value)  (SERCOM_USART_EXT_INTENCLR_RXS_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_RXS_Pos))
    969. 

  969. #define SERCOM_USART_EXT_INTENCLR_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_EXT_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
    970. 

  970. #define SERCOM_USART_EXT_INTENCLR_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_CTSIC_Pos)    /**< (SERCOM_USART_EXT_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
    971. 

  971. #define SERCOM_USART_EXT_INTENCLR_CTSIC(value) (SERCOM_USART_EXT_INTENCLR_CTSIC_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_CTSIC_Pos))
    972. 

  972. #define SERCOM_USART_EXT_INTENCLR_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_EXT_INTENCLR) Break Received Interrupt Disable Position */
    973. 

  973. #define SERCOM_USART_EXT_INTENCLR_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_RXBRK_Pos)    /**< (SERCOM_USART_EXT_INTENCLR) Break Received Interrupt Disable Mask */
    974. 

  974. #define SERCOM_USART_EXT_INTENCLR_RXBRK(value) (SERCOM_USART_EXT_INTENCLR_RXBRK_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_RXBRK_Pos))
    975. 

  975. #define SERCOM_USART_EXT_INTENCLR_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_EXT_INTENCLR) Combined Error Interrupt Disable Position */
    976. 

  976. #define SERCOM_USART_EXT_INTENCLR_ERROR_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENCLR_ERROR_Pos)    /**< (SERCOM_USART_EXT_INTENCLR) Combined Error Interrupt Disable Mask */
    977. 

  977. #define SERCOM_USART_EXT_INTENCLR_ERROR(value) (SERCOM_USART_EXT_INTENCLR_ERROR_Msk & ((value) << SERCOM_USART_EXT_INTENCLR_ERROR_Pos))
    978. 

  978. #define SERCOM_USART_EXT_INTENCLR_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_EXT_INTENCLR) Register Mask  */
    979. 

  979. 

  980. 

  981. /* -------- SERCOM_USART_INT_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART_INT Interrupt Enable Clear -------- */
    982. 

  982. #define SERCOM_USART_INT_INTENCLR_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_INTENCLR) USART_INT Interrupt Enable Clear  Reset Value */
    983. 

  983. 

  984. #define SERCOM_USART_INT_INTENCLR_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_INT_INTENCLR) Data Register Empty Interrupt Disable Position */
    985. 

  985. #define SERCOM_USART_INT_INTENCLR_DRE_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_DRE_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Data Register Empty Interrupt Disable Mask */
    986. 

  986. #define SERCOM_USART_INT_INTENCLR_DRE(value)  (SERCOM_USART_INT_INTENCLR_DRE_Msk & ((value) << SERCOM_USART_INT_INTENCLR_DRE_Pos))
    987. 

  987. #define SERCOM_USART_INT_INTENCLR_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_INT_INTENCLR) Transmit Complete Interrupt Disable Position */
    988. 

  988. #define SERCOM_USART_INT_INTENCLR_TXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_TXC_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Transmit Complete Interrupt Disable Mask */
    989. 

  989. #define SERCOM_USART_INT_INTENCLR_TXC(value)  (SERCOM_USART_INT_INTENCLR_TXC_Msk & ((value) << SERCOM_USART_INT_INTENCLR_TXC_Pos))
    990. 

  990. #define SERCOM_USART_INT_INTENCLR_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_INT_INTENCLR) Receive Complete Interrupt Disable Position */
    991. 

  991. #define SERCOM_USART_INT_INTENCLR_RXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_RXC_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Receive Complete Interrupt Disable Mask */
    992. 

  992. #define SERCOM_USART_INT_INTENCLR_RXC(value)  (SERCOM_USART_INT_INTENCLR_RXC_Msk & ((value) << SERCOM_USART_INT_INTENCLR_RXC_Pos))
    993. 

  993. #define SERCOM_USART_INT_INTENCLR_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_INT_INTENCLR) Receive Start Interrupt Disable Position */
    994. 

  994. #define SERCOM_USART_INT_INTENCLR_RXS_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENCLR_RXS_Pos)      /**< (SERCOM_USART_INT_INTENCLR) Receive Start Interrupt Disable Mask */
    995. 

  995. #define SERCOM_USART_INT_INTENCLR_RXS(value)  (SERCOM_USART_INT_INTENCLR_RXS_Msk & ((value) << SERCOM_USART_INT_INTENCLR_RXS_Pos))
    996. 

  996. #define SERCOM_USART_INT_INTENCLR_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_INT_INTENCLR) Clear To Send Input Change Interrupt Disable Position */
    997. 

  997. #define SERCOM_USART_INT_INTENCLR_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENCLR_CTSIC_Pos)    /**< (SERCOM_USART_INT_INTENCLR) Clear To Send Input Change Interrupt Disable Mask */
    998. 

  998. #define SERCOM_USART_INT_INTENCLR_CTSIC(value) (SERCOM_USART_INT_INTENCLR_CTSIC_Msk & ((value) << SERCOM_USART_INT_INTENCLR_CTSIC_Pos))
    999. 

  999. #define SERCOM_USART_INT_INTENCLR_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_INT_INTENCLR) Break Received Interrupt Disable Position */
    1000. 

  1000. #define SERCOM_USART_INT_INTENCLR_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENCLR_RXBRK_Pos)    /**< (SERCOM_USART_INT_INTENCLR) Break Received Interrupt Disable Mask */
    1001. 

  1001. #define SERCOM_USART_INT_INTENCLR_RXBRK(value) (SERCOM_USART_INT_INTENCLR_RXBRK_Msk & ((value) << SERCOM_USART_INT_INTENCLR_RXBRK_Pos))
    1002. 

  1002. #define SERCOM_USART_INT_INTENCLR_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_INT_INTENCLR) Combined Error Interrupt Disable Position */
    1003. 

  1003. #define SERCOM_USART_INT_INTENCLR_ERROR_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENCLR_ERROR_Pos)    /**< (SERCOM_USART_INT_INTENCLR) Combined Error Interrupt Disable Mask */
    1004. 

  1004. #define SERCOM_USART_INT_INTENCLR_ERROR(value) (SERCOM_USART_INT_INTENCLR_ERROR_Msk & ((value) << SERCOM_USART_INT_INTENCLR_ERROR_Pos))
    1005. 

  1005. #define SERCOM_USART_INT_INTENCLR_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_INT_INTENCLR) Register Mask  */
    1006. 

  1006. 

  1007. 

  1008. /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM Interrupt Enable Set -------- */
    1009. 

  1009. #define SERCOM_I2CM_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set  Reset Value */
    1010. 

  1010. 

  1011. #define SERCOM_I2CM_INTENSET_MB_Pos           _U_(0)                                               /**< (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Position */
    1012. 

  1012. #define SERCOM_I2CM_INTENSET_MB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos)            /**< (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable Mask */
    1013. 

  1013. #define SERCOM_I2CM_INTENSET_MB(value)        (SERCOM_I2CM_INTENSET_MB_Msk & ((value) << SERCOM_I2CM_INTENSET_MB_Pos))
    1014. 

  1014. #define SERCOM_I2CM_INTENSET_SB_Pos           _U_(1)                                               /**< (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Position */
    1015. 

  1015. #define SERCOM_I2CM_INTENSET_SB_Msk           (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos)            /**< (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable Mask */
    1016. 

  1016. #define SERCOM_I2CM_INTENSET_SB(value)        (SERCOM_I2CM_INTENSET_SB_Msk & ((value) << SERCOM_I2CM_INTENSET_SB_Pos))
    1017. 

  1017. #define SERCOM_I2CM_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Position */
    1018. 

  1018. #define SERCOM_I2CM_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos)         /**< (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable Mask */
    1019. 

  1019. #define SERCOM_I2CM_INTENSET_ERROR(value)     (SERCOM_I2CM_INTENSET_ERROR_Msk & ((value) << SERCOM_I2CM_INTENSET_ERROR_Pos))
    1020. 

  1020. #define SERCOM_I2CM_INTENSET_Msk              _U_(0x83)                                            /**< (SERCOM_I2CM_INTENSET) Register Mask  */
    1021. 

  1021. 

  1022. 

  1023. /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS Interrupt Enable Set -------- */
    1024. 

  1024. #define SERCOM_I2CS_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set  Reset Value */
    1025. 

  1025. 

  1026. #define SERCOM_I2CS_INTENSET_PREC_Pos         _U_(0)                                               /**< (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Position */
    1027. 

  1027. #define SERCOM_I2CS_INTENSET_PREC_Msk         (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos)          /**< (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable Mask */
    1028. 

  1028. #define SERCOM_I2CS_INTENSET_PREC(value)      (SERCOM_I2CS_INTENSET_PREC_Msk & ((value) << SERCOM_I2CS_INTENSET_PREC_Pos))
    1029. 

  1029. #define SERCOM_I2CS_INTENSET_AMATCH_Pos       _U_(1)                                               /**< (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Position */
    1030. 

  1030. #define SERCOM_I2CS_INTENSET_AMATCH_Msk       (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos)        /**< (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable Mask */
    1031. 

  1031. #define SERCOM_I2CS_INTENSET_AMATCH(value)    (SERCOM_I2CS_INTENSET_AMATCH_Msk & ((value) << SERCOM_I2CS_INTENSET_AMATCH_Pos))
    1032. 

  1032. #define SERCOM_I2CS_INTENSET_DRDY_Pos         _U_(2)                                               /**< (SERCOM_I2CS_INTENSET) Data Interrupt Enable Position */
    1033. 

  1033. #define SERCOM_I2CS_INTENSET_DRDY_Msk         (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos)          /**< (SERCOM_I2CS_INTENSET) Data Interrupt Enable Mask */
    1034. 

  1034. #define SERCOM_I2CS_INTENSET_DRDY(value)      (SERCOM_I2CS_INTENSET_DRDY_Msk & ((value) << SERCOM_I2CS_INTENSET_DRDY_Pos))
    1035. 

  1035. #define SERCOM_I2CS_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Position */
    1036. 

  1036. #define SERCOM_I2CS_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos)         /**< (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable Mask */
    1037. 

  1037. #define SERCOM_I2CS_INTENSET_ERROR(value)     (SERCOM_I2CS_INTENSET_ERROR_Msk & ((value) << SERCOM_I2CS_INTENSET_ERROR_Pos))
    1038. 

  1038. #define SERCOM_I2CS_INTENSET_Msk              _U_(0x87)                                            /**< (SERCOM_I2CS_INTENSET) Register Mask  */
    1039. 

  1039. 

  1040. 

  1041. /* -------- SERCOM_SPIM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPIM Interrupt Enable Set -------- */
    1042. 

  1042. #define SERCOM_SPIM_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIM_INTENSET) SPIM Interrupt Enable Set  Reset Value */
    1043. 

  1043. 

  1044. #define SERCOM_SPIM_INTENSET_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIM_INTENSET) Data Register Empty Interrupt Enable Position */
    1045. 

  1045. #define SERCOM_SPIM_INTENSET_DRE_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_DRE_Pos)           /**< (SERCOM_SPIM_INTENSET) Data Register Empty Interrupt Enable Mask */
    1046. 

  1046. #define SERCOM_SPIM_INTENSET_DRE(value)       (SERCOM_SPIM_INTENSET_DRE_Msk & ((value) << SERCOM_SPIM_INTENSET_DRE_Pos))
    1047. 

  1047. #define SERCOM_SPIM_INTENSET_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIM_INTENSET) Transmit Complete Interrupt Enable Position */
    1048. 

  1048. #define SERCOM_SPIM_INTENSET_TXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_TXC_Pos)           /**< (SERCOM_SPIM_INTENSET) Transmit Complete Interrupt Enable Mask */
    1049. 

  1049. #define SERCOM_SPIM_INTENSET_TXC(value)       (SERCOM_SPIM_INTENSET_TXC_Msk & ((value) << SERCOM_SPIM_INTENSET_TXC_Pos))
    1050. 

  1050. #define SERCOM_SPIM_INTENSET_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIM_INTENSET) Receive Complete Interrupt Enable Position */
    1051. 

  1051. #define SERCOM_SPIM_INTENSET_RXC_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_RXC_Pos)           /**< (SERCOM_SPIM_INTENSET) Receive Complete Interrupt Enable Mask */
    1052. 

  1052. #define SERCOM_SPIM_INTENSET_RXC(value)       (SERCOM_SPIM_INTENSET_RXC_Msk & ((value) << SERCOM_SPIM_INTENSET_RXC_Pos))
    1053. 

  1053. #define SERCOM_SPIM_INTENSET_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIM_INTENSET) Slave Select Low Interrupt Enable Position */
    1054. 

  1054. #define SERCOM_SPIM_INTENSET_SSL_Msk          (_U_(0x1) << SERCOM_SPIM_INTENSET_SSL_Pos)           /**< (SERCOM_SPIM_INTENSET) Slave Select Low Interrupt Enable Mask */
    1055. 

  1055. #define SERCOM_SPIM_INTENSET_SSL(value)       (SERCOM_SPIM_INTENSET_SSL_Msk & ((value) << SERCOM_SPIM_INTENSET_SSL_Pos))
    1056. 

  1056. #define SERCOM_SPIM_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIM_INTENSET) Combined Error Interrupt Enable Position */
    1057. 

  1057. #define SERCOM_SPIM_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_SPIM_INTENSET_ERROR_Pos)         /**< (SERCOM_SPIM_INTENSET) Combined Error Interrupt Enable Mask */
    1058. 

  1058. #define SERCOM_SPIM_INTENSET_ERROR(value)     (SERCOM_SPIM_INTENSET_ERROR_Msk & ((value) << SERCOM_SPIM_INTENSET_ERROR_Pos))
    1059. 

  1059. #define SERCOM_SPIM_INTENSET_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIM_INTENSET) Register Mask  */
    1060. 

  1060. 

  1061. 

  1062. /* -------- SERCOM_SPIS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPIS Interrupt Enable Set -------- */
    1063. 

  1063. #define SERCOM_SPIS_INTENSET_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIS_INTENSET) SPIS Interrupt Enable Set  Reset Value */
    1064. 

  1064. 

  1065. #define SERCOM_SPIS_INTENSET_DRE_Pos          _U_(0)                                               /**< (SERCOM_SPIS_INTENSET) Data Register Empty Interrupt Enable Position */
    1066. 

  1066. #define SERCOM_SPIS_INTENSET_DRE_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_DRE_Pos)           /**< (SERCOM_SPIS_INTENSET) Data Register Empty Interrupt Enable Mask */
    1067. 

  1067. #define SERCOM_SPIS_INTENSET_DRE(value)       (SERCOM_SPIS_INTENSET_DRE_Msk & ((value) << SERCOM_SPIS_INTENSET_DRE_Pos))
    1068. 

  1068. #define SERCOM_SPIS_INTENSET_TXC_Pos          _U_(1)                                               /**< (SERCOM_SPIS_INTENSET) Transmit Complete Interrupt Enable Position */
    1069. 

  1069. #define SERCOM_SPIS_INTENSET_TXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_TXC_Pos)           /**< (SERCOM_SPIS_INTENSET) Transmit Complete Interrupt Enable Mask */
    1070. 

  1070. #define SERCOM_SPIS_INTENSET_TXC(value)       (SERCOM_SPIS_INTENSET_TXC_Msk & ((value) << SERCOM_SPIS_INTENSET_TXC_Pos))
    1071. 

  1071. #define SERCOM_SPIS_INTENSET_RXC_Pos          _U_(2)                                               /**< (SERCOM_SPIS_INTENSET) Receive Complete Interrupt Enable Position */
    1072. 

  1072. #define SERCOM_SPIS_INTENSET_RXC_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_RXC_Pos)           /**< (SERCOM_SPIS_INTENSET) Receive Complete Interrupt Enable Mask */
    1073. 

  1073. #define SERCOM_SPIS_INTENSET_RXC(value)       (SERCOM_SPIS_INTENSET_RXC_Msk & ((value) << SERCOM_SPIS_INTENSET_RXC_Pos))
    1074. 

  1074. #define SERCOM_SPIS_INTENSET_SSL_Pos          _U_(3)                                               /**< (SERCOM_SPIS_INTENSET) Slave Select Low Interrupt Enable Position */
    1075. 

  1075. #define SERCOM_SPIS_INTENSET_SSL_Msk          (_U_(0x1) << SERCOM_SPIS_INTENSET_SSL_Pos)           /**< (SERCOM_SPIS_INTENSET) Slave Select Low Interrupt Enable Mask */
    1076. 

  1076. #define SERCOM_SPIS_INTENSET_SSL(value)       (SERCOM_SPIS_INTENSET_SSL_Msk & ((value) << SERCOM_SPIS_INTENSET_SSL_Pos))
    1077. 

  1077. #define SERCOM_SPIS_INTENSET_ERROR_Pos        _U_(7)                                               /**< (SERCOM_SPIS_INTENSET) Combined Error Interrupt Enable Position */
    1078. 

  1078. #define SERCOM_SPIS_INTENSET_ERROR_Msk        (_U_(0x1) << SERCOM_SPIS_INTENSET_ERROR_Pos)         /**< (SERCOM_SPIS_INTENSET) Combined Error Interrupt Enable Mask */
    1079. 

  1079. #define SERCOM_SPIS_INTENSET_ERROR(value)     (SERCOM_SPIS_INTENSET_ERROR_Msk & ((value) << SERCOM_SPIS_INTENSET_ERROR_Pos))
    1080. 

  1080. #define SERCOM_SPIS_INTENSET_Msk              _U_(0x8F)                                            /**< (SERCOM_SPIS_INTENSET) Register Mask  */
    1081. 

  1081. 

  1082. 

  1083. /* -------- SERCOM_USART_EXT_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART_EXT Interrupt Enable Set -------- */
    1084. 

  1084. #define SERCOM_USART_EXT_INTENSET_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_INTENSET) USART_EXT Interrupt Enable Set  Reset Value */
    1085. 

  1085. 

  1086. #define SERCOM_USART_EXT_INTENSET_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_EXT_INTENSET) Data Register Empty Interrupt Enable Position */
    1087. 

  1087. #define SERCOM_USART_EXT_INTENSET_DRE_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_DRE_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Data Register Empty Interrupt Enable Mask */
    1088. 

  1088. #define SERCOM_USART_EXT_INTENSET_DRE(value)  (SERCOM_USART_EXT_INTENSET_DRE_Msk & ((value) << SERCOM_USART_EXT_INTENSET_DRE_Pos))
    1089. 

  1089. #define SERCOM_USART_EXT_INTENSET_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_EXT_INTENSET) Transmit Complete Interrupt Enable Position */
    1090. 

  1090. #define SERCOM_USART_EXT_INTENSET_TXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_TXC_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Transmit Complete Interrupt Enable Mask */
    1091. 

  1091. #define SERCOM_USART_EXT_INTENSET_TXC(value)  (SERCOM_USART_EXT_INTENSET_TXC_Msk & ((value) << SERCOM_USART_EXT_INTENSET_TXC_Pos))
    1092. 

  1092. #define SERCOM_USART_EXT_INTENSET_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_EXT_INTENSET) Receive Complete Interrupt Enable Position */
    1093. 

  1093. #define SERCOM_USART_EXT_INTENSET_RXC_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_RXC_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Receive Complete Interrupt Enable Mask */
    1094. 

  1094. #define SERCOM_USART_EXT_INTENSET_RXC(value)  (SERCOM_USART_EXT_INTENSET_RXC_Msk & ((value) << SERCOM_USART_EXT_INTENSET_RXC_Pos))
    1095. 

  1095. #define SERCOM_USART_EXT_INTENSET_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_EXT_INTENSET) Receive Start Interrupt Enable Position */
    1096. 

  1096. #define SERCOM_USART_EXT_INTENSET_RXS_Msk     (_U_(0x1) << SERCOM_USART_EXT_INTENSET_RXS_Pos)      /**< (SERCOM_USART_EXT_INTENSET) Receive Start Interrupt Enable Mask */
    1097. 

  1097. #define SERCOM_USART_EXT_INTENSET_RXS(value)  (SERCOM_USART_EXT_INTENSET_RXS_Msk & ((value) << SERCOM_USART_EXT_INTENSET_RXS_Pos))
    1098. 

  1098. #define SERCOM_USART_EXT_INTENSET_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_EXT_INTENSET) Clear To Send Input Change Interrupt Enable Position */
    1099. 

  1099. #define SERCOM_USART_EXT_INTENSET_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENSET_CTSIC_Pos)    /**< (SERCOM_USART_EXT_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
    1100. 

  1100. #define SERCOM_USART_EXT_INTENSET_CTSIC(value) (SERCOM_USART_EXT_INTENSET_CTSIC_Msk & ((value) << SERCOM_USART_EXT_INTENSET_CTSIC_Pos))
    1101. 

  1101. #define SERCOM_USART_EXT_INTENSET_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_EXT_INTENSET) Break Received Interrupt Enable Position */
    1102. 

  1102. #define SERCOM_USART_EXT_INTENSET_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENSET_RXBRK_Pos)    /**< (SERCOM_USART_EXT_INTENSET) Break Received Interrupt Enable Mask */
    1103. 

  1103. #define SERCOM_USART_EXT_INTENSET_RXBRK(value) (SERCOM_USART_EXT_INTENSET_RXBRK_Msk & ((value) << SERCOM_USART_EXT_INTENSET_RXBRK_Pos))
    1104. 

  1104. #define SERCOM_USART_EXT_INTENSET_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_EXT_INTENSET) Combined Error Interrupt Enable Position */
    1105. 

  1105. #define SERCOM_USART_EXT_INTENSET_ERROR_Msk   (_U_(0x1) << SERCOM_USART_EXT_INTENSET_ERROR_Pos)    /**< (SERCOM_USART_EXT_INTENSET) Combined Error Interrupt Enable Mask */
    1106. 

  1106. #define SERCOM_USART_EXT_INTENSET_ERROR(value) (SERCOM_USART_EXT_INTENSET_ERROR_Msk & ((value) << SERCOM_USART_EXT_INTENSET_ERROR_Pos))
    1107. 

  1107. #define SERCOM_USART_EXT_INTENSET_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_EXT_INTENSET) Register Mask  */
    1108. 

  1108. 

  1109. 

  1110. /* -------- SERCOM_USART_INT_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART_INT Interrupt Enable Set -------- */
    1111. 

  1111. #define SERCOM_USART_INT_INTENSET_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_INTENSET) USART_INT Interrupt Enable Set  Reset Value */
    1112. 

  1112. 

  1113. #define SERCOM_USART_INT_INTENSET_DRE_Pos     _U_(0)                                               /**< (SERCOM_USART_INT_INTENSET) Data Register Empty Interrupt Enable Position */
    1114. 

  1114. #define SERCOM_USART_INT_INTENSET_DRE_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_DRE_Pos)      /**< (SERCOM_USART_INT_INTENSET) Data Register Empty Interrupt Enable Mask */
    1115. 

  1115. #define SERCOM_USART_INT_INTENSET_DRE(value)  (SERCOM_USART_INT_INTENSET_DRE_Msk & ((value) << SERCOM_USART_INT_INTENSET_DRE_Pos))
    1116. 

  1116. #define SERCOM_USART_INT_INTENSET_TXC_Pos     _U_(1)                                               /**< (SERCOM_USART_INT_INTENSET) Transmit Complete Interrupt Enable Position */
    1117. 

  1117. #define SERCOM_USART_INT_INTENSET_TXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_TXC_Pos)      /**< (SERCOM_USART_INT_INTENSET) Transmit Complete Interrupt Enable Mask */
    1118. 

  1118. #define SERCOM_USART_INT_INTENSET_TXC(value)  (SERCOM_USART_INT_INTENSET_TXC_Msk & ((value) << SERCOM_USART_INT_INTENSET_TXC_Pos))
    1119. 

  1119. #define SERCOM_USART_INT_INTENSET_RXC_Pos     _U_(2)                                               /**< (SERCOM_USART_INT_INTENSET) Receive Complete Interrupt Enable Position */
    1120. 

  1120. #define SERCOM_USART_INT_INTENSET_RXC_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_RXC_Pos)      /**< (SERCOM_USART_INT_INTENSET) Receive Complete Interrupt Enable Mask */
    1121. 

  1121. #define SERCOM_USART_INT_INTENSET_RXC(value)  (SERCOM_USART_INT_INTENSET_RXC_Msk & ((value) << SERCOM_USART_INT_INTENSET_RXC_Pos))
    1122. 

  1122. #define SERCOM_USART_INT_INTENSET_RXS_Pos     _U_(3)                                               /**< (SERCOM_USART_INT_INTENSET) Receive Start Interrupt Enable Position */
    1123. 

  1123. #define SERCOM_USART_INT_INTENSET_RXS_Msk     (_U_(0x1) << SERCOM_USART_INT_INTENSET_RXS_Pos)      /**< (SERCOM_USART_INT_INTENSET) Receive Start Interrupt Enable Mask */
    1124. 

  1124. #define SERCOM_USART_INT_INTENSET_RXS(value)  (SERCOM_USART_INT_INTENSET_RXS_Msk & ((value) << SERCOM_USART_INT_INTENSET_RXS_Pos))
    1125. 

  1125. #define SERCOM_USART_INT_INTENSET_CTSIC_Pos   _U_(4)                                               /**< (SERCOM_USART_INT_INTENSET) Clear To Send Input Change Interrupt Enable Position */
    1126. 

  1126. #define SERCOM_USART_INT_INTENSET_CTSIC_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENSET_CTSIC_Pos)    /**< (SERCOM_USART_INT_INTENSET) Clear To Send Input Change Interrupt Enable Mask */
    1127. 

  1127. #define SERCOM_USART_INT_INTENSET_CTSIC(value) (SERCOM_USART_INT_INTENSET_CTSIC_Msk & ((value) << SERCOM_USART_INT_INTENSET_CTSIC_Pos))
    1128. 

  1128. #define SERCOM_USART_INT_INTENSET_RXBRK_Pos   _U_(5)                                               /**< (SERCOM_USART_INT_INTENSET) Break Received Interrupt Enable Position */
    1129. 

  1129. #define SERCOM_USART_INT_INTENSET_RXBRK_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENSET_RXBRK_Pos)    /**< (SERCOM_USART_INT_INTENSET) Break Received Interrupt Enable Mask */
    1130. 

  1130. #define SERCOM_USART_INT_INTENSET_RXBRK(value) (SERCOM_USART_INT_INTENSET_RXBRK_Msk & ((value) << SERCOM_USART_INT_INTENSET_RXBRK_Pos))
    1131. 

  1131. #define SERCOM_USART_INT_INTENSET_ERROR_Pos   _U_(7)                                               /**< (SERCOM_USART_INT_INTENSET) Combined Error Interrupt Enable Position */
    1132. 

  1132. #define SERCOM_USART_INT_INTENSET_ERROR_Msk   (_U_(0x1) << SERCOM_USART_INT_INTENSET_ERROR_Pos)    /**< (SERCOM_USART_INT_INTENSET) Combined Error Interrupt Enable Mask */
    1133. 

  1133. #define SERCOM_USART_INT_INTENSET_ERROR(value) (SERCOM_USART_INT_INTENSET_ERROR_Msk & ((value) << SERCOM_USART_INT_INTENSET_ERROR_Pos))
    1134. 

  1134. #define SERCOM_USART_INT_INTENSET_Msk         _U_(0xBF)                                            /**< (SERCOM_USART_INT_INTENSET) Register Mask  */
    1135. 

  1135. 

  1136. 

  1137. /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM Interrupt Flag Status and Clear -------- */
    1138. 

  1138. #define SERCOM_I2CM_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear  Reset Value */
    1139. 

  1139. 

  1140. #define SERCOM_I2CM_INTFLAG_MB_Pos            _U_(0)                                               /**< (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Position */
    1141. 

  1141. #define SERCOM_I2CM_INTFLAG_MB_Msk            (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos)             /**< (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt Mask */
    1142. 

  1142. #define SERCOM_I2CM_INTFLAG_MB(value)         (SERCOM_I2CM_INTFLAG_MB_Msk & ((value) << SERCOM_I2CM_INTFLAG_MB_Pos))
    1143. 

  1143. #define SERCOM_I2CM_INTFLAG_SB_Pos            _U_(1)                                               /**< (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Position */
    1144. 

  1144. #define SERCOM_I2CM_INTFLAG_SB_Msk            (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos)             /**< (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt Mask */
    1145. 

  1145. #define SERCOM_I2CM_INTFLAG_SB(value)         (SERCOM_I2CM_INTFLAG_SB_Msk & ((value) << SERCOM_I2CM_INTFLAG_SB_Pos))
    1146. 

  1146. #define SERCOM_I2CM_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Position */
    1147. 

  1147. #define SERCOM_I2CM_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos)          /**< (SERCOM_I2CM_INTFLAG) Combined Error Interrupt Mask */
    1148. 

  1148. #define SERCOM_I2CM_INTFLAG_ERROR(value)      (SERCOM_I2CM_INTFLAG_ERROR_Msk & ((value) << SERCOM_I2CM_INTFLAG_ERROR_Pos))
    1149. 

  1149. #define SERCOM_I2CM_INTFLAG_Msk               _U_(0x83)                                            /**< (SERCOM_I2CM_INTFLAG) Register Mask  */
    1150. 

  1150. 

  1151. 

  1152. /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS Interrupt Flag Status and Clear -------- */
    1153. 

  1153. #define SERCOM_I2CS_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear  Reset Value */
    1154. 

  1154. 

  1155. #define SERCOM_I2CS_INTFLAG_PREC_Pos          _U_(0)                                               /**< (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Position */
    1156. 

  1156. #define SERCOM_I2CS_INTFLAG_PREC_Msk          (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos)           /**< (SERCOM_I2CS_INTFLAG) Stop Received Interrupt Mask */
    1157. 

  1157. #define SERCOM_I2CS_INTFLAG_PREC(value)       (SERCOM_I2CS_INTFLAG_PREC_Msk & ((value) << SERCOM_I2CS_INTFLAG_PREC_Pos))
    1158. 

  1158. #define SERCOM_I2CS_INTFLAG_AMATCH_Pos        _U_(1)                                               /**< (SERCOM_I2CS_INTFLAG) Address Match Interrupt Position */
    1159. 

  1159. #define SERCOM_I2CS_INTFLAG_AMATCH_Msk        (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos)         /**< (SERCOM_I2CS_INTFLAG) Address Match Interrupt Mask */
    1160. 

  1160. #define SERCOM_I2CS_INTFLAG_AMATCH(value)     (SERCOM_I2CS_INTFLAG_AMATCH_Msk & ((value) << SERCOM_I2CS_INTFLAG_AMATCH_Pos))
    1161. 

  1161. #define SERCOM_I2CS_INTFLAG_DRDY_Pos          _U_(2)                                               /**< (SERCOM_I2CS_INTFLAG) Data Interrupt Position */
    1162. 

  1162. #define SERCOM_I2CS_INTFLAG_DRDY_Msk          (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos)           /**< (SERCOM_I2CS_INTFLAG) Data Interrupt Mask */
    1163. 

  1163. #define SERCOM_I2CS_INTFLAG_DRDY(value)       (SERCOM_I2CS_INTFLAG_DRDY_Msk & ((value) << SERCOM_I2CS_INTFLAG_DRDY_Pos))
    1164. 

  1164. #define SERCOM_I2CS_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Position */
    1165. 

  1165. #define SERCOM_I2CS_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos)          /**< (SERCOM_I2CS_INTFLAG) Combined Error Interrupt Mask */
    1166. 

  1166. #define SERCOM_I2CS_INTFLAG_ERROR(value)      (SERCOM_I2CS_INTFLAG_ERROR_Msk & ((value) << SERCOM_I2CS_INTFLAG_ERROR_Pos))
    1167. 

  1167. #define SERCOM_I2CS_INTFLAG_Msk               _U_(0x87)                                            /**< (SERCOM_I2CS_INTFLAG) Register Mask  */
    1168. 

  1168. 

  1169. 

  1170. /* -------- SERCOM_SPIM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPIM Interrupt Flag Status and Clear -------- */
    1171. 

  1171. #define SERCOM_SPIM_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIM_INTFLAG) SPIM Interrupt Flag Status and Clear  Reset Value */
    1172. 

  1172. 

  1173. #define SERCOM_SPIM_INTFLAG_DRE_Pos           _U_(0)                                               /**< (SERCOM_SPIM_INTFLAG) Data Register Empty Interrupt Position */
    1174. 

  1174. #define SERCOM_SPIM_INTFLAG_DRE_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_DRE_Pos)            /**< (SERCOM_SPIM_INTFLAG) Data Register Empty Interrupt Mask */
    1175. 

  1175. #define SERCOM_SPIM_INTFLAG_DRE(value)        (SERCOM_SPIM_INTFLAG_DRE_Msk & ((value) << SERCOM_SPIM_INTFLAG_DRE_Pos))
    1176. 

  1176. #define SERCOM_SPIM_INTFLAG_TXC_Pos           _U_(1)                                               /**< (SERCOM_SPIM_INTFLAG) Transmit Complete Interrupt Position */
    1177. 

  1177. #define SERCOM_SPIM_INTFLAG_TXC_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_TXC_Pos)            /**< (SERCOM_SPIM_INTFLAG) Transmit Complete Interrupt Mask */
    1178. 

  1178. #define SERCOM_SPIM_INTFLAG_TXC(value)        (SERCOM_SPIM_INTFLAG_TXC_Msk & ((value) << SERCOM_SPIM_INTFLAG_TXC_Pos))
    1179. 

  1179. #define SERCOM_SPIM_INTFLAG_RXC_Pos           _U_(2)                                               /**< (SERCOM_SPIM_INTFLAG) Receive Complete Interrupt Position */
    1180. 

  1180. #define SERCOM_SPIM_INTFLAG_RXC_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_RXC_Pos)            /**< (SERCOM_SPIM_INTFLAG) Receive Complete Interrupt Mask */
    1181. 

  1181. #define SERCOM_SPIM_INTFLAG_RXC(value)        (SERCOM_SPIM_INTFLAG_RXC_Msk & ((value) << SERCOM_SPIM_INTFLAG_RXC_Pos))
    1182. 

  1182. #define SERCOM_SPIM_INTFLAG_SSL_Pos           _U_(3)                                               /**< (SERCOM_SPIM_INTFLAG) Slave Select Low Interrupt Flag Position */
    1183. 

  1183. #define SERCOM_SPIM_INTFLAG_SSL_Msk           (_U_(0x1) << SERCOM_SPIM_INTFLAG_SSL_Pos)            /**< (SERCOM_SPIM_INTFLAG) Slave Select Low Interrupt Flag Mask */
    1184. 

  1184. #define SERCOM_SPIM_INTFLAG_SSL(value)        (SERCOM_SPIM_INTFLAG_SSL_Msk & ((value) << SERCOM_SPIM_INTFLAG_SSL_Pos))
    1185. 

  1185. #define SERCOM_SPIM_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_SPIM_INTFLAG) Combined Error Interrupt Position */
    1186. 

  1186. #define SERCOM_SPIM_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_SPIM_INTFLAG_ERROR_Pos)          /**< (SERCOM_SPIM_INTFLAG) Combined Error Interrupt Mask */
    1187. 

  1187. #define SERCOM_SPIM_INTFLAG_ERROR(value)      (SERCOM_SPIM_INTFLAG_ERROR_Msk & ((value) << SERCOM_SPIM_INTFLAG_ERROR_Pos))
    1188. 

  1188. #define SERCOM_SPIM_INTFLAG_Msk               _U_(0x8F)                                            /**< (SERCOM_SPIM_INTFLAG) Register Mask  */
    1189. 

  1189. 

  1190. 

  1191. /* -------- SERCOM_SPIS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPIS Interrupt Flag Status and Clear -------- */
    1192. 

  1192. #define SERCOM_SPIS_INTFLAG_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIS_INTFLAG) SPIS Interrupt Flag Status and Clear  Reset Value */
    1193. 

  1193. 

  1194. #define SERCOM_SPIS_INTFLAG_DRE_Pos           _U_(0)                                               /**< (SERCOM_SPIS_INTFLAG) Data Register Empty Interrupt Position */
    1195. 

  1195. #define SERCOM_SPIS_INTFLAG_DRE_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_DRE_Pos)            /**< (SERCOM_SPIS_INTFLAG) Data Register Empty Interrupt Mask */
    1196. 

  1196. #define SERCOM_SPIS_INTFLAG_DRE(value)        (SERCOM_SPIS_INTFLAG_DRE_Msk & ((value) << SERCOM_SPIS_INTFLAG_DRE_Pos))
    1197. 

  1197. #define SERCOM_SPIS_INTFLAG_TXC_Pos           _U_(1)                                               /**< (SERCOM_SPIS_INTFLAG) Transmit Complete Interrupt Position */
    1198. 

  1198. #define SERCOM_SPIS_INTFLAG_TXC_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_TXC_Pos)            /**< (SERCOM_SPIS_INTFLAG) Transmit Complete Interrupt Mask */
    1199. 

  1199. #define SERCOM_SPIS_INTFLAG_TXC(value)        (SERCOM_SPIS_INTFLAG_TXC_Msk & ((value) << SERCOM_SPIS_INTFLAG_TXC_Pos))
    1200. 

  1200. #define SERCOM_SPIS_INTFLAG_RXC_Pos           _U_(2)                                               /**< (SERCOM_SPIS_INTFLAG) Receive Complete Interrupt Position */
    1201. 

  1201. #define SERCOM_SPIS_INTFLAG_RXC_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_RXC_Pos)            /**< (SERCOM_SPIS_INTFLAG) Receive Complete Interrupt Mask */
    1202. 

  1202. #define SERCOM_SPIS_INTFLAG_RXC(value)        (SERCOM_SPIS_INTFLAG_RXC_Msk & ((value) << SERCOM_SPIS_INTFLAG_RXC_Pos))
    1203. 

  1203. #define SERCOM_SPIS_INTFLAG_SSL_Pos           _U_(3)                                               /**< (SERCOM_SPIS_INTFLAG) Slave Select Low Interrupt Flag Position */
    1204. 

  1204. #define SERCOM_SPIS_INTFLAG_SSL_Msk           (_U_(0x1) << SERCOM_SPIS_INTFLAG_SSL_Pos)            /**< (SERCOM_SPIS_INTFLAG) Slave Select Low Interrupt Flag Mask */
    1205. 

  1205. #define SERCOM_SPIS_INTFLAG_SSL(value)        (SERCOM_SPIS_INTFLAG_SSL_Msk & ((value) << SERCOM_SPIS_INTFLAG_SSL_Pos))
    1206. 

  1206. #define SERCOM_SPIS_INTFLAG_ERROR_Pos         _U_(7)                                               /**< (SERCOM_SPIS_INTFLAG) Combined Error Interrupt Position */
    1207. 

  1207. #define SERCOM_SPIS_INTFLAG_ERROR_Msk         (_U_(0x1) << SERCOM_SPIS_INTFLAG_ERROR_Pos)          /**< (SERCOM_SPIS_INTFLAG) Combined Error Interrupt Mask */
    1208. 

  1208. #define SERCOM_SPIS_INTFLAG_ERROR(value)      (SERCOM_SPIS_INTFLAG_ERROR_Msk & ((value) << SERCOM_SPIS_INTFLAG_ERROR_Pos))
    1209. 

  1209. #define SERCOM_SPIS_INTFLAG_Msk               _U_(0x8F)                                            /**< (SERCOM_SPIS_INTFLAG) Register Mask  */
    1210. 

  1210. 

  1211. 

  1212. /* -------- SERCOM_USART_EXT_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART_EXT Interrupt Flag Status and Clear -------- */
    1213. 

  1213. #define SERCOM_USART_EXT_INTFLAG_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_EXT_INTFLAG) USART_EXT Interrupt Flag Status and Clear  Reset Value */
    1214. 

  1214. 

  1215. #define SERCOM_USART_EXT_INTFLAG_DRE_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_INTFLAG) Data Register Empty Interrupt Position */
    1216. 

  1216. #define SERCOM_USART_EXT_INTFLAG_DRE_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_DRE_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Data Register Empty Interrupt Mask */
    1217. 

  1217. #define SERCOM_USART_EXT_INTFLAG_DRE(value)   (SERCOM_USART_EXT_INTFLAG_DRE_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_DRE_Pos))
    1218. 

  1218. #define SERCOM_USART_EXT_INTFLAG_TXC_Pos      _U_(1)                                               /**< (SERCOM_USART_EXT_INTFLAG) Transmit Complete Interrupt Position */
    1219. 

  1219. #define SERCOM_USART_EXT_INTFLAG_TXC_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_TXC_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Transmit Complete Interrupt Mask */
    1220. 

  1220. #define SERCOM_USART_EXT_INTFLAG_TXC(value)   (SERCOM_USART_EXT_INTFLAG_TXC_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_TXC_Pos))
    1221. 

  1221. #define SERCOM_USART_EXT_INTFLAG_RXC_Pos      _U_(2)                                               /**< (SERCOM_USART_EXT_INTFLAG) Receive Complete Interrupt Position */
    1222. 

  1222. #define SERCOM_USART_EXT_INTFLAG_RXC_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_RXC_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Receive Complete Interrupt Mask */
    1223. 

  1223. #define SERCOM_USART_EXT_INTFLAG_RXC(value)   (SERCOM_USART_EXT_INTFLAG_RXC_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_RXC_Pos))
    1224. 

  1224. #define SERCOM_USART_EXT_INTFLAG_RXS_Pos      _U_(3)                                               /**< (SERCOM_USART_EXT_INTFLAG) Receive Start Interrupt Position */
    1225. 

  1225. #define SERCOM_USART_EXT_INTFLAG_RXS_Msk      (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_RXS_Pos)       /**< (SERCOM_USART_EXT_INTFLAG) Receive Start Interrupt Mask */
    1226. 

  1226. #define SERCOM_USART_EXT_INTFLAG_RXS(value)   (SERCOM_USART_EXT_INTFLAG_RXS_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_RXS_Pos))
    1227. 

  1227. #define SERCOM_USART_EXT_INTFLAG_CTSIC_Pos    _U_(4)                                               /**< (SERCOM_USART_EXT_INTFLAG) Clear To Send Input Change Interrupt Position */
    1228. 

  1228. #define SERCOM_USART_EXT_INTFLAG_CTSIC_Msk    (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_CTSIC_Pos)     /**< (SERCOM_USART_EXT_INTFLAG) Clear To Send Input Change Interrupt Mask */
    1229. 

  1229. #define SERCOM_USART_EXT_INTFLAG_CTSIC(value) (SERCOM_USART_EXT_INTFLAG_CTSIC_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_CTSIC_Pos))
    1230. 

  1230. #define SERCOM_USART_EXT_INTFLAG_RXBRK_Pos    _U_(5)                                               /**< (SERCOM_USART_EXT_INTFLAG) Break Received Interrupt Position */
    1231. 

  1231. #define SERCOM_USART_EXT_INTFLAG_RXBRK_Msk    (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_RXBRK_Pos)     /**< (SERCOM_USART_EXT_INTFLAG) Break Received Interrupt Mask */
    1232. 

  1232. #define SERCOM_USART_EXT_INTFLAG_RXBRK(value) (SERCOM_USART_EXT_INTFLAG_RXBRK_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_RXBRK_Pos))
    1233. 

  1233. #define SERCOM_USART_EXT_INTFLAG_ERROR_Pos    _U_(7)                                               /**< (SERCOM_USART_EXT_INTFLAG) Combined Error Interrupt Position */
    1234. 

  1234. #define SERCOM_USART_EXT_INTFLAG_ERROR_Msk    (_U_(0x1) << SERCOM_USART_EXT_INTFLAG_ERROR_Pos)     /**< (SERCOM_USART_EXT_INTFLAG) Combined Error Interrupt Mask */
    1235. 

  1235. #define SERCOM_USART_EXT_INTFLAG_ERROR(value) (SERCOM_USART_EXT_INTFLAG_ERROR_Msk & ((value) << SERCOM_USART_EXT_INTFLAG_ERROR_Pos))
    1236. 

  1236. #define SERCOM_USART_EXT_INTFLAG_Msk          _U_(0xBF)                                            /**< (SERCOM_USART_EXT_INTFLAG) Register Mask  */
    1237. 

  1237. 

  1238. 

  1239. /* -------- SERCOM_USART_INT_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART_INT Interrupt Flag Status and Clear -------- */
    1240. 

  1240. #define SERCOM_USART_INT_INTFLAG_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_INT_INTFLAG) USART_INT Interrupt Flag Status and Clear  Reset Value */
    1241. 

  1241. 

  1242. #define SERCOM_USART_INT_INTFLAG_DRE_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_INTFLAG) Data Register Empty Interrupt Position */
    1243. 

  1243. #define SERCOM_USART_INT_INTFLAG_DRE_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_DRE_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Data Register Empty Interrupt Mask */
    1244. 

  1244. #define SERCOM_USART_INT_INTFLAG_DRE(value)   (SERCOM_USART_INT_INTFLAG_DRE_Msk & ((value) << SERCOM_USART_INT_INTFLAG_DRE_Pos))
    1245. 

  1245. #define SERCOM_USART_INT_INTFLAG_TXC_Pos      _U_(1)                                               /**< (SERCOM_USART_INT_INTFLAG) Transmit Complete Interrupt Position */
    1246. 

  1246. #define SERCOM_USART_INT_INTFLAG_TXC_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_TXC_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Transmit Complete Interrupt Mask */
    1247. 

  1247. #define SERCOM_USART_INT_INTFLAG_TXC(value)   (SERCOM_USART_INT_INTFLAG_TXC_Msk & ((value) << SERCOM_USART_INT_INTFLAG_TXC_Pos))
    1248. 

  1248. #define SERCOM_USART_INT_INTFLAG_RXC_Pos      _U_(2)                                               /**< (SERCOM_USART_INT_INTFLAG) Receive Complete Interrupt Position */
    1249. 

  1249. #define SERCOM_USART_INT_INTFLAG_RXC_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_RXC_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Receive Complete Interrupt Mask */
    1250. 

  1250. #define SERCOM_USART_INT_INTFLAG_RXC(value)   (SERCOM_USART_INT_INTFLAG_RXC_Msk & ((value) << SERCOM_USART_INT_INTFLAG_RXC_Pos))
    1251. 

  1251. #define SERCOM_USART_INT_INTFLAG_RXS_Pos      _U_(3)                                               /**< (SERCOM_USART_INT_INTFLAG) Receive Start Interrupt Position */
    1252. 

  1252. #define SERCOM_USART_INT_INTFLAG_RXS_Msk      (_U_(0x1) << SERCOM_USART_INT_INTFLAG_RXS_Pos)       /**< (SERCOM_USART_INT_INTFLAG) Receive Start Interrupt Mask */
    1253. 

  1253. #define SERCOM_USART_INT_INTFLAG_RXS(value)   (SERCOM_USART_INT_INTFLAG_RXS_Msk & ((value) << SERCOM_USART_INT_INTFLAG_RXS_Pos))
    1254. 

  1254. #define SERCOM_USART_INT_INTFLAG_CTSIC_Pos    _U_(4)                                               /**< (SERCOM_USART_INT_INTFLAG) Clear To Send Input Change Interrupt Position */
    1255. 

  1255. #define SERCOM_USART_INT_INTFLAG_CTSIC_Msk    (_U_(0x1) << SERCOM_USART_INT_INTFLAG_CTSIC_Pos)     /**< (SERCOM_USART_INT_INTFLAG) Clear To Send Input Change Interrupt Mask */
    1256. 

  1256. #define SERCOM_USART_INT_INTFLAG_CTSIC(value) (SERCOM_USART_INT_INTFLAG_CTSIC_Msk & ((value) << SERCOM_USART_INT_INTFLAG_CTSIC_Pos))
    1257. 

  1257. #define SERCOM_USART_INT_INTFLAG_RXBRK_Pos    _U_(5)                                               /**< (SERCOM_USART_INT_INTFLAG) Break Received Interrupt Position */
    1258. 

  1258. #define SERCOM_USART_INT_INTFLAG_RXBRK_Msk    (_U_(0x1) << SERCOM_USART_INT_INTFLAG_RXBRK_Pos)     /**< (SERCOM_USART_INT_INTFLAG) Break Received Interrupt Mask */
    1259. 

  1259. #define SERCOM_USART_INT_INTFLAG_RXBRK(value) (SERCOM_USART_INT_INTFLAG_RXBRK_Msk & ((value) << SERCOM_USART_INT_INTFLAG_RXBRK_Pos))
    1260. 

  1260. #define SERCOM_USART_INT_INTFLAG_ERROR_Pos    _U_(7)                                               /**< (SERCOM_USART_INT_INTFLAG) Combined Error Interrupt Position */
    1261. 

  1261. #define SERCOM_USART_INT_INTFLAG_ERROR_Msk    (_U_(0x1) << SERCOM_USART_INT_INTFLAG_ERROR_Pos)     /**< (SERCOM_USART_INT_INTFLAG) Combined Error Interrupt Mask */
    1262. 

  1262. #define SERCOM_USART_INT_INTFLAG_ERROR(value) (SERCOM_USART_INT_INTFLAG_ERROR_Msk & ((value) << SERCOM_USART_INT_INTFLAG_ERROR_Pos))
    1263. 

  1263. #define SERCOM_USART_INT_INTFLAG_Msk          _U_(0xBF)                                            /**< (SERCOM_USART_INT_INTFLAG) Register Mask  */
    1264. 

  1264. 

  1265. 

  1266. /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM Status -------- */
    1267. 

  1267. #define SERCOM_I2CM_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_I2CM_STATUS) I2CM Status  Reset Value */
    1268. 

  1268. 

  1269. #define SERCOM_I2CM_STATUS_BUSERR_Pos         _U_(0)                                               /**< (SERCOM_I2CM_STATUS) Bus Error Position */
    1270. 

  1270. #define SERCOM_I2CM_STATUS_BUSERR_Msk         (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos)          /**< (SERCOM_I2CM_STATUS) Bus Error Mask */
    1271. 

  1271. #define SERCOM_I2CM_STATUS_BUSERR(value)      (SERCOM_I2CM_STATUS_BUSERR_Msk & ((value) << SERCOM_I2CM_STATUS_BUSERR_Pos))
    1272. 

  1272. #define SERCOM_I2CM_STATUS_ARBLOST_Pos        _U_(1)                                               /**< (SERCOM_I2CM_STATUS) Arbitration Lost Position */
    1273. 

  1273. #define SERCOM_I2CM_STATUS_ARBLOST_Msk        (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos)         /**< (SERCOM_I2CM_STATUS) Arbitration Lost Mask */
    1274. 

  1274. #define SERCOM_I2CM_STATUS_ARBLOST(value)     (SERCOM_I2CM_STATUS_ARBLOST_Msk & ((value) << SERCOM_I2CM_STATUS_ARBLOST_Pos))
    1275. 

  1275. #define SERCOM_I2CM_STATUS_RXNACK_Pos         _U_(2)                                               /**< (SERCOM_I2CM_STATUS) Received Not Acknowledge Position */
    1276. 

  1276. #define SERCOM_I2CM_STATUS_RXNACK_Msk         (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos)          /**< (SERCOM_I2CM_STATUS) Received Not Acknowledge Mask */
    1277. 

  1277. #define SERCOM_I2CM_STATUS_RXNACK(value)      (SERCOM_I2CM_STATUS_RXNACK_Msk & ((value) << SERCOM_I2CM_STATUS_RXNACK_Pos))
    1278. 

  1278. #define SERCOM_I2CM_STATUS_BUSSTATE_Pos       _U_(4)                                               /**< (SERCOM_I2CM_STATUS) Bus State Position */
    1279. 

  1279. #define SERCOM_I2CM_STATUS_BUSSTATE_Msk       (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)        /**< (SERCOM_I2CM_STATUS) Bus State Mask */
    1280. 

  1280. #define SERCOM_I2CM_STATUS_BUSSTATE(value)    (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos))
    1281. 

  1281. #define SERCOM_I2CM_STATUS_LOWTOUT_Pos        _U_(6)                                               /**< (SERCOM_I2CM_STATUS) SCL Low Timeout Position */
    1282. 

  1282. #define SERCOM_I2CM_STATUS_LOWTOUT_Msk        (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos)         /**< (SERCOM_I2CM_STATUS) SCL Low Timeout Mask */
    1283. 

  1283. #define SERCOM_I2CM_STATUS_LOWTOUT(value)     (SERCOM_I2CM_STATUS_LOWTOUT_Msk & ((value) << SERCOM_I2CM_STATUS_LOWTOUT_Pos))
    1284. 

  1284. #define SERCOM_I2CM_STATUS_CLKHOLD_Pos        _U_(7)                                               /**< (SERCOM_I2CM_STATUS) Clock Hold Position */
    1285. 

  1285. #define SERCOM_I2CM_STATUS_CLKHOLD_Msk        (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos)         /**< (SERCOM_I2CM_STATUS) Clock Hold Mask */
    1286. 

  1286. #define SERCOM_I2CM_STATUS_CLKHOLD(value)     (SERCOM_I2CM_STATUS_CLKHOLD_Msk & ((value) << SERCOM_I2CM_STATUS_CLKHOLD_Pos))
    1287. 

  1287. #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos       _U_(8)                                               /**< (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Position */
    1288. 

  1288. #define SERCOM_I2CM_STATUS_MEXTTOUT_Msk       (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos)        /**< (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout Mask */
    1289. 

  1289. #define SERCOM_I2CM_STATUS_MEXTTOUT(value)    (SERCOM_I2CM_STATUS_MEXTTOUT_Msk & ((value) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos))
    1290. 

  1290. #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos       _U_(9)                                               /**< (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Position */
    1291. 

  1291. #define SERCOM_I2CM_STATUS_SEXTTOUT_Msk       (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos)        /**< (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout Mask */
    1292. 

  1292. #define SERCOM_I2CM_STATUS_SEXTTOUT(value)    (SERCOM_I2CM_STATUS_SEXTTOUT_Msk & ((value) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos))
    1293. 

  1293. #define SERCOM_I2CM_STATUS_LENERR_Pos         _U_(10)                                              /**< (SERCOM_I2CM_STATUS) Length Error Position */
    1294. 

  1294. #define SERCOM_I2CM_STATUS_LENERR_Msk         (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos)          /**< (SERCOM_I2CM_STATUS) Length Error Mask */
    1295. 

  1295. #define SERCOM_I2CM_STATUS_LENERR(value)      (SERCOM_I2CM_STATUS_LENERR_Msk & ((value) << SERCOM_I2CM_STATUS_LENERR_Pos))
    1296. 

  1296. #define SERCOM_I2CM_STATUS_Msk                _U_(0x07F7)                                          /**< (SERCOM_I2CM_STATUS) Register Mask  */
    1297. 

  1297. 

  1298. 

  1299. /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS Status -------- */
    1300. 

  1300. #define SERCOM_I2CS_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_I2CS_STATUS) I2CS Status  Reset Value */
    1301. 

  1301. 

  1302. #define SERCOM_I2CS_STATUS_BUSERR_Pos         _U_(0)                                               /**< (SERCOM_I2CS_STATUS) Bus Error Position */
    1303. 

  1303. #define SERCOM_I2CS_STATUS_BUSERR_Msk         (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos)          /**< (SERCOM_I2CS_STATUS) Bus Error Mask */
    1304. 

  1304. #define SERCOM_I2CS_STATUS_BUSERR(value)      (SERCOM_I2CS_STATUS_BUSERR_Msk & ((value) << SERCOM_I2CS_STATUS_BUSERR_Pos))
    1305. 

  1305. #define SERCOM_I2CS_STATUS_COLL_Pos           _U_(1)                                               /**< (SERCOM_I2CS_STATUS) Transmit Collision Position */
    1306. 

  1306. #define SERCOM_I2CS_STATUS_COLL_Msk           (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos)            /**< (SERCOM_I2CS_STATUS) Transmit Collision Mask */
    1307. 

  1307. #define SERCOM_I2CS_STATUS_COLL(value)        (SERCOM_I2CS_STATUS_COLL_Msk & ((value) << SERCOM_I2CS_STATUS_COLL_Pos))
    1308. 

  1308. #define SERCOM_I2CS_STATUS_RXNACK_Pos         _U_(2)                                               /**< (SERCOM_I2CS_STATUS) Received Not Acknowledge Position */
    1309. 

  1309. #define SERCOM_I2CS_STATUS_RXNACK_Msk         (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos)          /**< (SERCOM_I2CS_STATUS) Received Not Acknowledge Mask */
    1310. 

  1310. #define SERCOM_I2CS_STATUS_RXNACK(value)      (SERCOM_I2CS_STATUS_RXNACK_Msk & ((value) << SERCOM_I2CS_STATUS_RXNACK_Pos))
    1311. 

  1311. #define SERCOM_I2CS_STATUS_DIR_Pos            _U_(3)                                               /**< (SERCOM_I2CS_STATUS) Read/Write Direction Position */
    1312. 

  1312. #define SERCOM_I2CS_STATUS_DIR_Msk            (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos)             /**< (SERCOM_I2CS_STATUS) Read/Write Direction Mask */
    1313. 

  1313. #define SERCOM_I2CS_STATUS_DIR(value)         (SERCOM_I2CS_STATUS_DIR_Msk & ((value) << SERCOM_I2CS_STATUS_DIR_Pos))
    1314. 

  1314. #define SERCOM_I2CS_STATUS_SR_Pos             _U_(4)                                               /**< (SERCOM_I2CS_STATUS) Repeated Start Position */
    1315. 

  1315. #define SERCOM_I2CS_STATUS_SR_Msk             (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos)              /**< (SERCOM_I2CS_STATUS) Repeated Start Mask */
    1316. 

  1316. #define SERCOM_I2CS_STATUS_SR(value)          (SERCOM_I2CS_STATUS_SR_Msk & ((value) << SERCOM_I2CS_STATUS_SR_Pos))
    1317. 

  1317. #define SERCOM_I2CS_STATUS_LOWTOUT_Pos        _U_(6)                                               /**< (SERCOM_I2CS_STATUS) SCL Low Timeout Position */
    1318. 

  1318. #define SERCOM_I2CS_STATUS_LOWTOUT_Msk        (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos)         /**< (SERCOM_I2CS_STATUS) SCL Low Timeout Mask */
    1319. 

  1319. #define SERCOM_I2CS_STATUS_LOWTOUT(value)     (SERCOM_I2CS_STATUS_LOWTOUT_Msk & ((value) << SERCOM_I2CS_STATUS_LOWTOUT_Pos))
    1320. 

  1320. #define SERCOM_I2CS_STATUS_CLKHOLD_Pos        _U_(7)                                               /**< (SERCOM_I2CS_STATUS) Clock Hold Position */
    1321. 

  1321. #define SERCOM_I2CS_STATUS_CLKHOLD_Msk        (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos)         /**< (SERCOM_I2CS_STATUS) Clock Hold Mask */
    1322. 

  1322. #define SERCOM_I2CS_STATUS_CLKHOLD(value)     (SERCOM_I2CS_STATUS_CLKHOLD_Msk & ((value) << SERCOM_I2CS_STATUS_CLKHOLD_Pos))
    1323. 

  1323. #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos       _U_(9)                                               /**< (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Position */
    1324. 

  1324. #define SERCOM_I2CS_STATUS_SEXTTOUT_Msk       (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos)        /**< (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout Mask */
    1325. 

  1325. #define SERCOM_I2CS_STATUS_SEXTTOUT(value)    (SERCOM_I2CS_STATUS_SEXTTOUT_Msk & ((value) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos))
    1326. 

  1326. #define SERCOM_I2CS_STATUS_HS_Pos             _U_(10)                                              /**< (SERCOM_I2CS_STATUS) High Speed Position */
    1327. 

  1327. #define SERCOM_I2CS_STATUS_HS_Msk             (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos)              /**< (SERCOM_I2CS_STATUS) High Speed Mask */
    1328. 

  1328. #define SERCOM_I2CS_STATUS_HS(value)          (SERCOM_I2CS_STATUS_HS_Msk & ((value) << SERCOM_I2CS_STATUS_HS_Pos))
    1329. 

  1329. #define SERCOM_I2CS_STATUS_Msk                _U_(0x06DF)                                          /**< (SERCOM_I2CS_STATUS) Register Mask  */
    1330. 

  1330. 

  1331. 

  1332. /* -------- SERCOM_SPIM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPIM Status -------- */
    1333. 

  1333. #define SERCOM_SPIM_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_SPIM_STATUS) SPIM Status  Reset Value */
    1334. 

  1334. 

  1335. #define SERCOM_SPIM_STATUS_BUFOVF_Pos         _U_(2)                                               /**< (SERCOM_SPIM_STATUS) Buffer Overflow Position */
    1336. 

  1336. #define SERCOM_SPIM_STATUS_BUFOVF_Msk         (_U_(0x1) << SERCOM_SPIM_STATUS_BUFOVF_Pos)          /**< (SERCOM_SPIM_STATUS) Buffer Overflow Mask */
    1337. 

  1337. #define SERCOM_SPIM_STATUS_BUFOVF(value)      (SERCOM_SPIM_STATUS_BUFOVF_Msk & ((value) << SERCOM_SPIM_STATUS_BUFOVF_Pos))
    1338. 

  1338. #define SERCOM_SPIM_STATUS_Msk                _U_(0x0004)                                          /**< (SERCOM_SPIM_STATUS) Register Mask  */
    1339. 

  1339. 

  1340. 

  1341. /* -------- SERCOM_SPIS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPIS Status -------- */
    1342. 

  1342. #define SERCOM_SPIS_STATUS_RESETVALUE         _U_(0x00)                                            /**<  (SERCOM_SPIS_STATUS) SPIS Status  Reset Value */
    1343. 

  1343. 

  1344. #define SERCOM_SPIS_STATUS_BUFOVF_Pos         _U_(2)                                               /**< (SERCOM_SPIS_STATUS) Buffer Overflow Position */
    1345. 

  1345. #define SERCOM_SPIS_STATUS_BUFOVF_Msk         (_U_(0x1) << SERCOM_SPIS_STATUS_BUFOVF_Pos)          /**< (SERCOM_SPIS_STATUS) Buffer Overflow Mask */
    1346. 

  1346. #define SERCOM_SPIS_STATUS_BUFOVF(value)      (SERCOM_SPIS_STATUS_BUFOVF_Msk & ((value) << SERCOM_SPIS_STATUS_BUFOVF_Pos))
    1347. 

  1347. #define SERCOM_SPIS_STATUS_Msk                _U_(0x0004)                                          /**< (SERCOM_SPIS_STATUS) Register Mask  */
    1348. 

  1348. 

  1349. 

  1350. /* -------- SERCOM_USART_EXT_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART_EXT Status -------- */
    1351. 

  1351. #define SERCOM_USART_EXT_STATUS_RESETVALUE    _U_(0x00)                                            /**<  (SERCOM_USART_EXT_STATUS) USART_EXT Status  Reset Value */
    1352. 

  1352. 

  1353. #define SERCOM_USART_EXT_STATUS_PERR_Pos      _U_(0)                                               /**< (SERCOM_USART_EXT_STATUS) Parity Error Position */
    1354. 

  1354. #define SERCOM_USART_EXT_STATUS_PERR_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_PERR_Pos)       /**< (SERCOM_USART_EXT_STATUS) Parity Error Mask */
    1355. 

  1355. #define SERCOM_USART_EXT_STATUS_PERR(value)   (SERCOM_USART_EXT_STATUS_PERR_Msk & ((value) << SERCOM_USART_EXT_STATUS_PERR_Pos))
    1356. 

  1356. #define SERCOM_USART_EXT_STATUS_FERR_Pos      _U_(1)                                               /**< (SERCOM_USART_EXT_STATUS) Frame Error Position */
    1357. 

  1357. #define SERCOM_USART_EXT_STATUS_FERR_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_FERR_Pos)       /**< (SERCOM_USART_EXT_STATUS) Frame Error Mask */
    1358. 

  1358. #define SERCOM_USART_EXT_STATUS_FERR(value)   (SERCOM_USART_EXT_STATUS_FERR_Msk & ((value) << SERCOM_USART_EXT_STATUS_FERR_Pos))
    1359. 

  1359. #define SERCOM_USART_EXT_STATUS_BUFOVF_Pos    _U_(2)                                               /**< (SERCOM_USART_EXT_STATUS) Buffer Overflow Position */
    1360. 

  1360. #define SERCOM_USART_EXT_STATUS_BUFOVF_Msk    (_U_(0x1) << SERCOM_USART_EXT_STATUS_BUFOVF_Pos)     /**< (SERCOM_USART_EXT_STATUS) Buffer Overflow Mask */
    1361. 

  1361. #define SERCOM_USART_EXT_STATUS_BUFOVF(value) (SERCOM_USART_EXT_STATUS_BUFOVF_Msk & ((value) << SERCOM_USART_EXT_STATUS_BUFOVF_Pos))
    1362. 

  1362. #define SERCOM_USART_EXT_STATUS_CTS_Pos       _U_(3)                                               /**< (SERCOM_USART_EXT_STATUS) Clear To Send Position */
    1363. 

  1363. #define SERCOM_USART_EXT_STATUS_CTS_Msk       (_U_(0x1) << SERCOM_USART_EXT_STATUS_CTS_Pos)        /**< (SERCOM_USART_EXT_STATUS) Clear To Send Mask */
    1364. 

  1364. #define SERCOM_USART_EXT_STATUS_CTS(value)    (SERCOM_USART_EXT_STATUS_CTS_Msk & ((value) << SERCOM_USART_EXT_STATUS_CTS_Pos))
    1365. 

  1365. #define SERCOM_USART_EXT_STATUS_ISF_Pos       _U_(4)                                               /**< (SERCOM_USART_EXT_STATUS) Inconsistent Sync Field Position */
    1366. 

  1366. #define SERCOM_USART_EXT_STATUS_ISF_Msk       (_U_(0x1) << SERCOM_USART_EXT_STATUS_ISF_Pos)        /**< (SERCOM_USART_EXT_STATUS) Inconsistent Sync Field Mask */
    1367. 

  1367. #define SERCOM_USART_EXT_STATUS_ISF(value)    (SERCOM_USART_EXT_STATUS_ISF_Msk & ((value) << SERCOM_USART_EXT_STATUS_ISF_Pos))
    1368. 

  1368. #define SERCOM_USART_EXT_STATUS_COLL_Pos      _U_(5)                                               /**< (SERCOM_USART_EXT_STATUS) Collision Detected Position */
    1369. 

  1369. #define SERCOM_USART_EXT_STATUS_COLL_Msk      (_U_(0x1) << SERCOM_USART_EXT_STATUS_COLL_Pos)       /**< (SERCOM_USART_EXT_STATUS) Collision Detected Mask */
    1370. 

  1370. #define SERCOM_USART_EXT_STATUS_COLL(value)   (SERCOM_USART_EXT_STATUS_COLL_Msk & ((value) << SERCOM_USART_EXT_STATUS_COLL_Pos))
    1371. 

  1371. #define SERCOM_USART_EXT_STATUS_TXE_Pos       _U_(6)                                               /**< (SERCOM_USART_EXT_STATUS) Transmitter Empty Position */
    1372. 

  1372. #define SERCOM_USART_EXT_STATUS_TXE_Msk       (_U_(0x1) << SERCOM_USART_EXT_STATUS_TXE_Pos)        /**< (SERCOM_USART_EXT_STATUS) Transmitter Empty Mask */
    1373. 

  1373. #define SERCOM_USART_EXT_STATUS_TXE(value)    (SERCOM_USART_EXT_STATUS_TXE_Msk & ((value) << SERCOM_USART_EXT_STATUS_TXE_Pos))
    1374. 

  1374. #define SERCOM_USART_EXT_STATUS_Msk           _U_(0x007F)                                          /**< (SERCOM_USART_EXT_STATUS) Register Mask  */
    1375. 

  1375. 

  1376. 

  1377. /* -------- SERCOM_USART_INT_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART_INT Status -------- */
    1378. 

  1378. #define SERCOM_USART_INT_STATUS_RESETVALUE    _U_(0x00)                                            /**<  (SERCOM_USART_INT_STATUS) USART_INT Status  Reset Value */
    1379. 

  1379. 

  1380. #define SERCOM_USART_INT_STATUS_PERR_Pos      _U_(0)                                               /**< (SERCOM_USART_INT_STATUS) Parity Error Position */
    1381. 

  1381. #define SERCOM_USART_INT_STATUS_PERR_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_PERR_Pos)       /**< (SERCOM_USART_INT_STATUS) Parity Error Mask */
    1382. 

  1382. #define SERCOM_USART_INT_STATUS_PERR(value)   (SERCOM_USART_INT_STATUS_PERR_Msk & ((value) << SERCOM_USART_INT_STATUS_PERR_Pos))
    1383. 

  1383. #define SERCOM_USART_INT_STATUS_FERR_Pos      _U_(1)                                               /**< (SERCOM_USART_INT_STATUS) Frame Error Position */
    1384. 

  1384. #define SERCOM_USART_INT_STATUS_FERR_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_FERR_Pos)       /**< (SERCOM_USART_INT_STATUS) Frame Error Mask */
    1385. 

  1385. #define SERCOM_USART_INT_STATUS_FERR(value)   (SERCOM_USART_INT_STATUS_FERR_Msk & ((value) << SERCOM_USART_INT_STATUS_FERR_Pos))
    1386. 

  1386. #define SERCOM_USART_INT_STATUS_BUFOVF_Pos    _U_(2)                                               /**< (SERCOM_USART_INT_STATUS) Buffer Overflow Position */
    1387. 

  1387. #define SERCOM_USART_INT_STATUS_BUFOVF_Msk    (_U_(0x1) << SERCOM_USART_INT_STATUS_BUFOVF_Pos)     /**< (SERCOM_USART_INT_STATUS) Buffer Overflow Mask */
    1388. 

  1388. #define SERCOM_USART_INT_STATUS_BUFOVF(value) (SERCOM_USART_INT_STATUS_BUFOVF_Msk & ((value) << SERCOM_USART_INT_STATUS_BUFOVF_Pos))
    1389. 

  1389. #define SERCOM_USART_INT_STATUS_CTS_Pos       _U_(3)                                               /**< (SERCOM_USART_INT_STATUS) Clear To Send Position */
    1390. 

  1390. #define SERCOM_USART_INT_STATUS_CTS_Msk       (_U_(0x1) << SERCOM_USART_INT_STATUS_CTS_Pos)        /**< (SERCOM_USART_INT_STATUS) Clear To Send Mask */
    1391. 

  1391. #define SERCOM_USART_INT_STATUS_CTS(value)    (SERCOM_USART_INT_STATUS_CTS_Msk & ((value) << SERCOM_USART_INT_STATUS_CTS_Pos))
    1392. 

  1392. #define SERCOM_USART_INT_STATUS_ISF_Pos       _U_(4)                                               /**< (SERCOM_USART_INT_STATUS) Inconsistent Sync Field Position */
    1393. 

  1393. #define SERCOM_USART_INT_STATUS_ISF_Msk       (_U_(0x1) << SERCOM_USART_INT_STATUS_ISF_Pos)        /**< (SERCOM_USART_INT_STATUS) Inconsistent Sync Field Mask */
    1394. 

  1394. #define SERCOM_USART_INT_STATUS_ISF(value)    (SERCOM_USART_INT_STATUS_ISF_Msk & ((value) << SERCOM_USART_INT_STATUS_ISF_Pos))
    1395. 

  1395. #define SERCOM_USART_INT_STATUS_COLL_Pos      _U_(5)                                               /**< (SERCOM_USART_INT_STATUS) Collision Detected Position */
    1396. 

  1396. #define SERCOM_USART_INT_STATUS_COLL_Msk      (_U_(0x1) << SERCOM_USART_INT_STATUS_COLL_Pos)       /**< (SERCOM_USART_INT_STATUS) Collision Detected Mask */
    1397. 

  1397. #define SERCOM_USART_INT_STATUS_COLL(value)   (SERCOM_USART_INT_STATUS_COLL_Msk & ((value) << SERCOM_USART_INT_STATUS_COLL_Pos))
    1398. 

  1398. #define SERCOM_USART_INT_STATUS_TXE_Pos       _U_(6)                                               /**< (SERCOM_USART_INT_STATUS) Transmitter Empty Position */
    1399. 

  1399. #define SERCOM_USART_INT_STATUS_TXE_Msk       (_U_(0x1) << SERCOM_USART_INT_STATUS_TXE_Pos)        /**< (SERCOM_USART_INT_STATUS) Transmitter Empty Mask */
    1400. 

  1400. #define SERCOM_USART_INT_STATUS_TXE(value)    (SERCOM_USART_INT_STATUS_TXE_Msk & ((value) << SERCOM_USART_INT_STATUS_TXE_Pos))
    1401. 

  1401. #define SERCOM_USART_INT_STATUS_Msk           _U_(0x007F)                                          /**< (SERCOM_USART_INT_STATUS) Register Mask  */
    1402. 

  1402. 

  1403. 

  1404. /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CM Synchronization Busy -------- */
    1405. 

  1405. #define SERCOM_I2CM_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy  Reset Value */
    1406. 

  1406. 

  1407. #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Position */
    1408. 

  1408. #define SERCOM_I2CM_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy Mask */
    1409. 

  1409. #define SERCOM_I2CM_SYNCBUSY_SWRST(value)     (SERCOM_I2CM_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos))
    1410. 

  1410. #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
    1411. 

  1411. #define SERCOM_I2CM_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
    1412. 

  1412. #define SERCOM_I2CM_SYNCBUSY_ENABLE(value)    (SERCOM_I2CM_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos))
    1413. 

  1413. #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos        _U_(2)                                               /**< (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Position */
    1414. 

  1414. #define SERCOM_I2CM_SYNCBUSY_SYSOP_Msk        (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos)         /**< (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy Mask */
    1415. 

  1415. #define SERCOM_I2CM_SYNCBUSY_SYSOP(value)     (SERCOM_I2CM_SYNCBUSY_SYSOP_Msk & ((value) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos))
    1416. 

  1416. #define SERCOM_I2CM_SYNCBUSY_Msk              _U_(0x00000007)                                      /**< (SERCOM_I2CM_SYNCBUSY) Register Mask  */
    1417. 

  1417. 

  1418. 

  1419. /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) I2CS Synchronization Busy -------- */
    1420. 

  1420. #define SERCOM_I2CS_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy  Reset Value */
    1421. 

  1421. 

  1422. #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Position */
    1423. 

  1423. #define SERCOM_I2CS_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy Mask */
    1424. 

  1424. #define SERCOM_I2CS_SYNCBUSY_SWRST(value)     (SERCOM_I2CS_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos))
    1425. 

  1425. #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
    1426. 

  1426. #define SERCOM_I2CS_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
    1427. 

  1427. #define SERCOM_I2CS_SYNCBUSY_ENABLE(value)    (SERCOM_I2CS_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos))
    1428. 

  1428. #define SERCOM_I2CS_SYNCBUSY_Msk              _U_(0x00000003)                                      /**< (SERCOM_I2CS_SYNCBUSY) Register Mask  */
    1429. 

  1429. 

  1430. 

  1431. /* -------- SERCOM_SPIM_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPIM Synchronization Busy -------- */
    1432. 

  1432. #define SERCOM_SPIM_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIM_SYNCBUSY) SPIM Synchronization Busy  Reset Value */
    1433. 

  1433. 

  1434. #define SERCOM_SPIM_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_SPIM_SYNCBUSY) Software Reset Synchronization Busy Position */
    1435. 

  1435. #define SERCOM_SPIM_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_SPIM_SYNCBUSY) Software Reset Synchronization Busy Mask */
    1436. 

  1436. #define SERCOM_SPIM_SYNCBUSY_SWRST(value)     (SERCOM_SPIM_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_SWRST_Pos))
    1437. 

  1437. #define SERCOM_SPIM_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_SPIM_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
    1438. 

  1438. #define SERCOM_SPIM_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_SPIM_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
    1439. 

  1439. #define SERCOM_SPIM_SYNCBUSY_ENABLE(value)    (SERCOM_SPIM_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_ENABLE_Pos))
    1440. 

  1440. #define SERCOM_SPIM_SYNCBUSY_CTRLB_Pos        _U_(2)                                               /**< (SERCOM_SPIM_SYNCBUSY) CTRLB Synchronization Busy Position */
    1441. 

  1441. #define SERCOM_SPIM_SYNCBUSY_CTRLB_Msk        (_U_(0x1) << SERCOM_SPIM_SYNCBUSY_CTRLB_Pos)         /**< (SERCOM_SPIM_SYNCBUSY) CTRLB Synchronization Busy Mask */
    1442. 

  1442. #define SERCOM_SPIM_SYNCBUSY_CTRLB(value)     (SERCOM_SPIM_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_SPIM_SYNCBUSY_CTRLB_Pos))
    1443. 

  1443. #define SERCOM_SPIM_SYNCBUSY_Msk              _U_(0x00000007)                                      /**< (SERCOM_SPIM_SYNCBUSY) Register Mask  */
    1444. 

  1444. 

  1445. 

  1446. /* -------- SERCOM_SPIS_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) SPIS Synchronization Busy -------- */
    1447. 

  1447. #define SERCOM_SPIS_SYNCBUSY_RESETVALUE       _U_(0x00)                                            /**<  (SERCOM_SPIS_SYNCBUSY) SPIS Synchronization Busy  Reset Value */
    1448. 

  1448. 

  1449. #define SERCOM_SPIS_SYNCBUSY_SWRST_Pos        _U_(0)                                               /**< (SERCOM_SPIS_SYNCBUSY) Software Reset Synchronization Busy Position */
    1450. 

  1450. #define SERCOM_SPIS_SYNCBUSY_SWRST_Msk        (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_SWRST_Pos)         /**< (SERCOM_SPIS_SYNCBUSY) Software Reset Synchronization Busy Mask */
    1451. 

  1451. #define SERCOM_SPIS_SYNCBUSY_SWRST(value)     (SERCOM_SPIS_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_SWRST_Pos))
    1452. 

  1452. #define SERCOM_SPIS_SYNCBUSY_ENABLE_Pos       _U_(1)                                               /**< (SERCOM_SPIS_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
    1453. 

  1453. #define SERCOM_SPIS_SYNCBUSY_ENABLE_Msk       (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_ENABLE_Pos)        /**< (SERCOM_SPIS_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
    1454. 

  1454. #define SERCOM_SPIS_SYNCBUSY_ENABLE(value)    (SERCOM_SPIS_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_ENABLE_Pos))
    1455. 

  1455. #define SERCOM_SPIS_SYNCBUSY_CTRLB_Pos        _U_(2)                                               /**< (SERCOM_SPIS_SYNCBUSY) CTRLB Synchronization Busy Position */
    1456. 

  1456. #define SERCOM_SPIS_SYNCBUSY_CTRLB_Msk        (_U_(0x1) << SERCOM_SPIS_SYNCBUSY_CTRLB_Pos)         /**< (SERCOM_SPIS_SYNCBUSY) CTRLB Synchronization Busy Mask */
    1457. 

  1457. #define SERCOM_SPIS_SYNCBUSY_CTRLB(value)     (SERCOM_SPIS_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_SPIS_SYNCBUSY_CTRLB_Pos))
    1458. 

  1458. #define SERCOM_SPIS_SYNCBUSY_Msk              _U_(0x00000007)                                      /**< (SERCOM_SPIS_SYNCBUSY) Register Mask  */
    1459. 

  1459. 

  1460. 

  1461. /* -------- SERCOM_USART_EXT_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART_EXT Synchronization Busy -------- */
    1462. 

  1462. #define SERCOM_USART_EXT_SYNCBUSY_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_EXT_SYNCBUSY) USART_EXT Synchronization Busy  Reset Value */
    1463. 

  1463. 

  1464. #define SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos   _U_(0)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) Software Reset Synchronization Busy Position */
    1465. 

  1465. #define SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk   (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos)    /**< (SERCOM_USART_EXT_SYNCBUSY) Software Reset Synchronization Busy Mask */
    1466. 

  1466. #define SERCOM_USART_EXT_SYNCBUSY_SWRST(value) (SERCOM_USART_EXT_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_SWRST_Pos))
    1467. 

  1467. #define SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos  _U_(1)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
    1468. 

  1468. #define SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk  (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos)   /**< (SERCOM_USART_EXT_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
    1469. 

  1469. #define SERCOM_USART_EXT_SYNCBUSY_ENABLE(value) (SERCOM_USART_EXT_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_ENABLE_Pos))
    1470. 

  1470. #define SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos   _U_(2)                                               /**< (SERCOM_USART_EXT_SYNCBUSY) CTRLB Synchronization Busy Position */
    1471. 

  1471. #define SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk   (_U_(0x1) << SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos)    /**< (SERCOM_USART_EXT_SYNCBUSY) CTRLB Synchronization Busy Mask */
    1472. 

  1472. #define SERCOM_USART_EXT_SYNCBUSY_CTRLB(value) (SERCOM_USART_EXT_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_USART_EXT_SYNCBUSY_CTRLB_Pos))
    1473. 

  1473. #define SERCOM_USART_EXT_SYNCBUSY_Msk         _U_(0x00000007)                                      /**< (SERCOM_USART_EXT_SYNCBUSY) Register Mask  */
    1474. 

  1474. 

  1475. 

  1476. /* -------- SERCOM_USART_INT_SYNCBUSY : (SERCOM Offset: 0x1C) ( R/ 32) USART_INT Synchronization Busy -------- */
    1477. 

  1477. #define SERCOM_USART_INT_SYNCBUSY_RESETVALUE  _U_(0x00)                                            /**<  (SERCOM_USART_INT_SYNCBUSY) USART_INT Synchronization Busy  Reset Value */
    1478. 

  1478. 

  1479. #define SERCOM_USART_INT_SYNCBUSY_SWRST_Pos   _U_(0)                                               /**< (SERCOM_USART_INT_SYNCBUSY) Software Reset Synchronization Busy Position */
    1480. 

  1480. #define SERCOM_USART_INT_SYNCBUSY_SWRST_Msk   (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_SWRST_Pos)    /**< (SERCOM_USART_INT_SYNCBUSY) Software Reset Synchronization Busy Mask */
    1481. 

  1481. #define SERCOM_USART_INT_SYNCBUSY_SWRST(value) (SERCOM_USART_INT_SYNCBUSY_SWRST_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_SWRST_Pos))
    1482. 

  1482. #define SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos  _U_(1)                                               /**< (SERCOM_USART_INT_SYNCBUSY) SERCOM Enable Synchronization Busy Position */
    1483. 

  1483. #define SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk  (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos)   /**< (SERCOM_USART_INT_SYNCBUSY) SERCOM Enable Synchronization Busy Mask */
    1484. 

  1484. #define SERCOM_USART_INT_SYNCBUSY_ENABLE(value) (SERCOM_USART_INT_SYNCBUSY_ENABLE_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_ENABLE_Pos))
    1485. 

  1485. #define SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos   _U_(2)                                               /**< (SERCOM_USART_INT_SYNCBUSY) CTRLB Synchronization Busy Position */
    1486. 

  1486. #define SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk   (_U_(0x1) << SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos)    /**< (SERCOM_USART_INT_SYNCBUSY) CTRLB Synchronization Busy Mask */
    1487. 

  1487. #define SERCOM_USART_INT_SYNCBUSY_CTRLB(value) (SERCOM_USART_INT_SYNCBUSY_CTRLB_Msk & ((value) << SERCOM_USART_INT_SYNCBUSY_CTRLB_Pos))
    1488. 

  1488. #define SERCOM_USART_INT_SYNCBUSY_Msk         _U_(0x00000007)                                      /**< (SERCOM_USART_INT_SYNCBUSY) Register Mask  */
    1489. 

  1489. 

  1490. 

  1491. /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM Address -------- */
    1492. 

  1492. #define SERCOM_I2CM_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CM_ADDR) I2CM Address  Reset Value */
    1493. 

  1493. 

  1494. #define SERCOM_I2CM_ADDR_ADDR_Pos             _U_(0)                                               /**< (SERCOM_I2CM_ADDR) Address Value Position */
    1495. 

  1495. #define SERCOM_I2CM_ADDR_ADDR_Msk             (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos)            /**< (SERCOM_I2CM_ADDR) Address Value Mask */
    1496. 

  1496. #define SERCOM_I2CM_ADDR_ADDR(value)          (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos))
    1497. 

  1497. #define SERCOM_I2CM_ADDR_LENEN_Pos            _U_(13)                                              /**< (SERCOM_I2CM_ADDR) Length Enable Position */
    1498. 

  1498. #define SERCOM_I2CM_ADDR_LENEN_Msk            (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos)             /**< (SERCOM_I2CM_ADDR) Length Enable Mask */
    1499. 

  1499. #define SERCOM_I2CM_ADDR_LENEN(value)         (SERCOM_I2CM_ADDR_LENEN_Msk & ((value) << SERCOM_I2CM_ADDR_LENEN_Pos))
    1500. 

  1500. #define SERCOM_I2CM_ADDR_HS_Pos               _U_(14)                                              /**< (SERCOM_I2CM_ADDR) High Speed Mode Position */
    1501. 

  1501. #define SERCOM_I2CM_ADDR_HS_Msk               (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos)                /**< (SERCOM_I2CM_ADDR) High Speed Mode Mask */
    1502. 

  1502. #define SERCOM_I2CM_ADDR_HS(value)            (SERCOM_I2CM_ADDR_HS_Msk & ((value) << SERCOM_I2CM_ADDR_HS_Pos))
    1503. 

  1503. #define SERCOM_I2CM_ADDR_TENBITEN_Pos         _U_(15)                                              /**< (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Position */
    1504. 

  1504. #define SERCOM_I2CM_ADDR_TENBITEN_Msk         (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos)          /**< (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable Mask */
    1505. 

  1505. #define SERCOM_I2CM_ADDR_TENBITEN(value)      (SERCOM_I2CM_ADDR_TENBITEN_Msk & ((value) << SERCOM_I2CM_ADDR_TENBITEN_Pos))
    1506. 

  1506. #define SERCOM_I2CM_ADDR_LEN_Pos              _U_(16)                                              /**< (SERCOM_I2CM_ADDR) Length Position */
    1507. 

  1507. #define SERCOM_I2CM_ADDR_LEN_Msk              (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos)              /**< (SERCOM_I2CM_ADDR) Length Mask */
    1508. 

  1508. #define SERCOM_I2CM_ADDR_LEN(value)           (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos))
    1509. 

  1509. #define SERCOM_I2CM_ADDR_Msk                  _U_(0x00FFE7FF)                                      /**< (SERCOM_I2CM_ADDR) Register Mask  */
    1510. 

  1510. 

  1511. 

  1512. /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS Address -------- */
    1513. 

  1513. #define SERCOM_I2CS_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CS_ADDR) I2CS Address  Reset Value */
    1514. 

  1514. 

  1515. #define SERCOM_I2CS_ADDR_GENCEN_Pos           _U_(0)                                               /**< (SERCOM_I2CS_ADDR) General Call Address Enable Position */
    1516. 

  1516. #define SERCOM_I2CS_ADDR_GENCEN_Msk           (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos)            /**< (SERCOM_I2CS_ADDR) General Call Address Enable Mask */
    1517. 

  1517. #define SERCOM_I2CS_ADDR_GENCEN(value)        (SERCOM_I2CS_ADDR_GENCEN_Msk & ((value) << SERCOM_I2CS_ADDR_GENCEN_Pos))
    1518. 

  1518. #define SERCOM_I2CS_ADDR_ADDR_Pos             _U_(1)                                               /**< (SERCOM_I2CS_ADDR) Address Value Position */
    1519. 

  1519. #define SERCOM_I2CS_ADDR_ADDR_Msk             (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos)            /**< (SERCOM_I2CS_ADDR) Address Value Mask */
    1520. 

  1520. #define SERCOM_I2CS_ADDR_ADDR(value)          (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos))
    1521. 

  1521. #define SERCOM_I2CS_ADDR_TENBITEN_Pos         _U_(15)                                              /**< (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Position */
    1522. 

  1522. #define SERCOM_I2CS_ADDR_TENBITEN_Msk         (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos)          /**< (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable Mask */
    1523. 

  1523. #define SERCOM_I2CS_ADDR_TENBITEN(value)      (SERCOM_I2CS_ADDR_TENBITEN_Msk & ((value) << SERCOM_I2CS_ADDR_TENBITEN_Pos))
    1524. 

  1524. #define SERCOM_I2CS_ADDR_ADDRMASK_Pos         _U_(17)                                              /**< (SERCOM_I2CS_ADDR) Address Mask Position */
    1525. 

  1525. #define SERCOM_I2CS_ADDR_ADDRMASK_Msk         (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)        /**< (SERCOM_I2CS_ADDR) Address Mask Mask */
    1526. 

  1526. #define SERCOM_I2CS_ADDR_ADDRMASK(value)      (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos))
    1527. 

  1527. #define SERCOM_I2CS_ADDR_Msk                  _U_(0x07FE87FF)                                      /**< (SERCOM_I2CS_ADDR) Register Mask  */
    1528. 

  1528. 

  1529. 

  1530. /* -------- SERCOM_SPIM_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPIM Address -------- */
    1531. 

  1531. #define SERCOM_SPIM_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIM_ADDR) SPIM Address  Reset Value */
    1532. 

  1532. 

  1533. #define SERCOM_SPIM_ADDR_ADDR_Pos             _U_(0)                                               /**< (SERCOM_SPIM_ADDR) Address Value Position */
    1534. 

  1534. #define SERCOM_SPIM_ADDR_ADDR_Msk             (_U_(0xFF) << SERCOM_SPIM_ADDR_ADDR_Pos)             /**< (SERCOM_SPIM_ADDR) Address Value Mask */
    1535. 

  1535. #define SERCOM_SPIM_ADDR_ADDR(value)          (SERCOM_SPIM_ADDR_ADDR_Msk & ((value) << SERCOM_SPIM_ADDR_ADDR_Pos))
    1536. 

  1536. #define SERCOM_SPIM_ADDR_ADDRMASK_Pos         _U_(16)                                              /**< (SERCOM_SPIM_ADDR) Address Mask Position */
    1537. 

  1537. #define SERCOM_SPIM_ADDR_ADDRMASK_Msk         (_U_(0xFF) << SERCOM_SPIM_ADDR_ADDRMASK_Pos)         /**< (SERCOM_SPIM_ADDR) Address Mask Mask */
    1538. 

  1538. #define SERCOM_SPIM_ADDR_ADDRMASK(value)      (SERCOM_SPIM_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPIM_ADDR_ADDRMASK_Pos))
    1539. 

  1539. #define SERCOM_SPIM_ADDR_Msk                  _U_(0x00FF00FF)                                      /**< (SERCOM_SPIM_ADDR) Register Mask  */
    1540. 

  1540. 

  1541. 

  1542. /* -------- SERCOM_SPIS_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPIS Address -------- */
    1543. 

  1543. #define SERCOM_SPIS_ADDR_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIS_ADDR) SPIS Address  Reset Value */
    1544. 

  1544. 

  1545. #define SERCOM_SPIS_ADDR_ADDR_Pos             _U_(0)                                               /**< (SERCOM_SPIS_ADDR) Address Value Position */
    1546. 

  1546. #define SERCOM_SPIS_ADDR_ADDR_Msk             (_U_(0xFF) << SERCOM_SPIS_ADDR_ADDR_Pos)             /**< (SERCOM_SPIS_ADDR) Address Value Mask */
    1547. 

  1547. #define SERCOM_SPIS_ADDR_ADDR(value)          (SERCOM_SPIS_ADDR_ADDR_Msk & ((value) << SERCOM_SPIS_ADDR_ADDR_Pos))
    1548. 

  1548. #define SERCOM_SPIS_ADDR_ADDRMASK_Pos         _U_(16)                                              /**< (SERCOM_SPIS_ADDR) Address Mask Position */
    1549. 

  1549. #define SERCOM_SPIS_ADDR_ADDRMASK_Msk         (_U_(0xFF) << SERCOM_SPIS_ADDR_ADDRMASK_Pos)         /**< (SERCOM_SPIS_ADDR) Address Mask Mask */
    1550. 

  1550. #define SERCOM_SPIS_ADDR_ADDRMASK(value)      (SERCOM_SPIS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPIS_ADDR_ADDRMASK_Pos))
    1551. 

  1551. #define SERCOM_SPIS_ADDR_Msk                  _U_(0x00FF00FF)                                      /**< (SERCOM_SPIS_ADDR) Register Mask  */
    1552. 

  1552. 

  1553. 

  1554. /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM Data -------- */
    1555. 

  1555. #define SERCOM_I2CM_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CM_DATA) I2CM Data  Reset Value */
    1556. 

  1556. 

  1557. #define SERCOM_I2CM_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_I2CM_DATA) Data Value Position */
    1558. 

  1558. #define SERCOM_I2CM_DATA_DATA_Msk             (_U_(0xFF) << SERCOM_I2CM_DATA_DATA_Pos)             /**< (SERCOM_I2CM_DATA) Data Value Mask */
    1559. 

  1559. #define SERCOM_I2CM_DATA_DATA(value)          (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos))
    1560. 

  1560. #define SERCOM_I2CM_DATA_Msk                  _U_(0xFF)                                            /**< (SERCOM_I2CM_DATA) Register Mask  */
    1561. 

  1561. 

  1562. 

  1563. /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS Data -------- */
    1564. 

  1564. #define SERCOM_I2CS_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_I2CS_DATA) I2CS Data  Reset Value */
    1565. 

  1565. 

  1566. #define SERCOM_I2CS_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_I2CS_DATA) Data Value Position */
    1567. 

  1567. #define SERCOM_I2CS_DATA_DATA_Msk             (_U_(0xFF) << SERCOM_I2CS_DATA_DATA_Pos)             /**< (SERCOM_I2CS_DATA) Data Value Mask */
    1568. 

  1568. #define SERCOM_I2CS_DATA_DATA(value)          (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos))
    1569. 

  1569. #define SERCOM_I2CS_DATA_Msk                  _U_(0xFF)                                            /**< (SERCOM_I2CS_DATA) Register Mask  */
    1570. 

  1570. 

  1571. 

  1572. /* -------- SERCOM_SPIM_DATA : (SERCOM Offset: 0x28) (R/W 32) SPIM Data -------- */
    1573. 

  1573. #define SERCOM_SPIM_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIM_DATA) SPIM Data  Reset Value */
    1574. 

  1574. 

  1575. #define SERCOM_SPIM_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_SPIM_DATA) Data Value Position */
    1576. 

  1576. #define SERCOM_SPIM_DATA_DATA_Msk             (_U_(0x1FF) << SERCOM_SPIM_DATA_DATA_Pos)            /**< (SERCOM_SPIM_DATA) Data Value Mask */
    1577. 

  1577. #define SERCOM_SPIM_DATA_DATA(value)          (SERCOM_SPIM_DATA_DATA_Msk & ((value) << SERCOM_SPIM_DATA_DATA_Pos))
    1578. 

  1578. #define SERCOM_SPIM_DATA_Msk                  _U_(0x000001FF)                                      /**< (SERCOM_SPIM_DATA) Register Mask  */
    1579. 

  1579. 

  1580. 

  1581. /* -------- SERCOM_SPIS_DATA : (SERCOM Offset: 0x28) (R/W 32) SPIS Data -------- */
    1582. 

  1582. #define SERCOM_SPIS_DATA_RESETVALUE           _U_(0x00)                                            /**<  (SERCOM_SPIS_DATA) SPIS Data  Reset Value */
    1583. 

  1583. 

  1584. #define SERCOM_SPIS_DATA_DATA_Pos             _U_(0)                                               /**< (SERCOM_SPIS_DATA) Data Value Position */
    1585. 

  1585. #define SERCOM_SPIS_DATA_DATA_Msk             (_U_(0x1FF) << SERCOM_SPIS_DATA_DATA_Pos)            /**< (SERCOM_SPIS_DATA) Data Value Mask */
    1586. 

  1586. #define SERCOM_SPIS_DATA_DATA(value)          (SERCOM_SPIS_DATA_DATA_Msk & ((value) << SERCOM_SPIS_DATA_DATA_Pos))
    1587. 

  1587. #define SERCOM_SPIS_DATA_Msk                  _U_(0x000001FF)                                      /**< (SERCOM_SPIS_DATA) Register Mask  */
    1588. 

  1588. 

  1589. 

  1590. /* -------- SERCOM_USART_EXT_DATA : (SERCOM Offset: 0x28) (R/W 16) USART_EXT Data -------- */
    1591. 

  1591. #define SERCOM_USART_EXT_DATA_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_EXT_DATA) USART_EXT Data  Reset Value */
    1592. 

  1592. 

  1593. #define SERCOM_USART_EXT_DATA_DATA_Pos        _U_(0)                                               /**< (SERCOM_USART_EXT_DATA) Data Value Position */
    1594. 

  1594. #define SERCOM_USART_EXT_DATA_DATA_Msk        (_U_(0x1FF) << SERCOM_USART_EXT_DATA_DATA_Pos)       /**< (SERCOM_USART_EXT_DATA) Data Value Mask */
    1595. 

  1595. #define SERCOM_USART_EXT_DATA_DATA(value)     (SERCOM_USART_EXT_DATA_DATA_Msk & ((value) << SERCOM_USART_EXT_DATA_DATA_Pos))
    1596. 

  1596. #define SERCOM_USART_EXT_DATA_Msk             _U_(0x01FF)                                          /**< (SERCOM_USART_EXT_DATA) Register Mask  */
    1597. 

  1597. 

  1598. 

  1599. /* -------- SERCOM_USART_INT_DATA : (SERCOM Offset: 0x28) (R/W 16) USART_INT Data -------- */
    1600. 

  1600. #define SERCOM_USART_INT_DATA_RESETVALUE      _U_(0x00)                                            /**<  (SERCOM_USART_INT_DATA) USART_INT Data  Reset Value */
    1601. 

  1601. 

  1602. #define SERCOM_USART_INT_DATA_DATA_Pos        _U_(0)                                               /**< (SERCOM_USART_INT_DATA) Data Value Position */
    1603. 

  1603. #define SERCOM_USART_INT_DATA_DATA_Msk        (_U_(0x1FF) << SERCOM_USART_INT_DATA_DATA_Pos)       /**< (SERCOM_USART_INT_DATA) Data Value Mask */
    1604. 

  1604. #define SERCOM_USART_INT_DATA_DATA(value)     (SERCOM_USART_INT_DATA_DATA_Msk & ((value) << SERCOM_USART_INT_DATA_DATA_Pos))
    1605. 

  1605. #define SERCOM_USART_INT_DATA_Msk             _U_(0x01FF)                                          /**< (SERCOM_USART_INT_DATA) Register Mask  */
    1606. 

  1606. 

  1607. 

  1608. /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM Debug Control -------- */
    1609. 

  1609. #define SERCOM_I2CM_DBGCTRL_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_I2CM_DBGCTRL) I2CM Debug Control  Reset Value */
    1610. 

  1610. 

  1611. #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos       _U_(0)                                               /**< (SERCOM_I2CM_DBGCTRL) Debug Mode Position */
    1612. 

  1612. #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk       (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos)        /**< (SERCOM_I2CM_DBGCTRL) Debug Mode Mask */
    1613. 

  1613. #define SERCOM_I2CM_DBGCTRL_DBGSTOP(value)    (SERCOM_I2CM_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos))
    1614. 

  1614. #define SERCOM_I2CM_DBGCTRL_Msk               _U_(0x01)                                            /**< (SERCOM_I2CM_DBGCTRL) Register Mask  */
    1615. 

  1615. 

  1616. 

  1617. /* -------- SERCOM_SPIM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPIM Debug Control -------- */
    1618. 

  1618. #define SERCOM_SPIM_DBGCTRL_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIM_DBGCTRL) SPIM Debug Control  Reset Value */
    1619. 

  1619. 

  1620. #define SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos       _U_(0)                                               /**< (SERCOM_SPIM_DBGCTRL) Debug Mode Position */
    1621. 

  1621. #define SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk       (_U_(0x1) << SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos)        /**< (SERCOM_SPIM_DBGCTRL) Debug Mode Mask */
    1622. 

  1622. #define SERCOM_SPIM_DBGCTRL_DBGSTOP(value)    (SERCOM_SPIM_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_SPIM_DBGCTRL_DBGSTOP_Pos))
    1623. 

  1623. #define SERCOM_SPIM_DBGCTRL_Msk               _U_(0x01)                                            /**< (SERCOM_SPIM_DBGCTRL) Register Mask  */
    1624. 

  1624. 

  1625. 

  1626. /* -------- SERCOM_SPIS_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPIS Debug Control -------- */
    1627. 

  1627. #define SERCOM_SPIS_DBGCTRL_RESETVALUE        _U_(0x00)                                            /**<  (SERCOM_SPIS_DBGCTRL) SPIS Debug Control  Reset Value */
    1628. 

  1628. 

  1629. #define SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos       _U_(0)                                               /**< (SERCOM_SPIS_DBGCTRL) Debug Mode Position */
    1630. 

  1630. #define SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk       (_U_(0x1) << SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos)        /**< (SERCOM_SPIS_DBGCTRL) Debug Mode Mask */
    1631. 

  1631. #define SERCOM_SPIS_DBGCTRL_DBGSTOP(value)    (SERCOM_SPIS_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_SPIS_DBGCTRL_DBGSTOP_Pos))
    1632. 

  1632. #define SERCOM_SPIS_DBGCTRL_Msk               _U_(0x01)                                            /**< (SERCOM_SPIS_DBGCTRL) Register Mask  */
    1633. 

  1633. 

  1634. 

  1635. /* -------- SERCOM_USART_EXT_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART_EXT Debug Control -------- */
    1636. 

  1636. #define SERCOM_USART_EXT_DBGCTRL_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_EXT_DBGCTRL) USART_EXT Debug Control  Reset Value */
    1637. 

  1637. 

  1638. #define SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos  _U_(0)                                               /**< (SERCOM_USART_EXT_DBGCTRL) Debug Mode Position */
    1639. 

  1639. #define SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk  (_U_(0x1) << SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos)   /**< (SERCOM_USART_EXT_DBGCTRL) Debug Mode Mask */
    1640. 

  1640. #define SERCOM_USART_EXT_DBGCTRL_DBGSTOP(value) (SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_USART_EXT_DBGCTRL_DBGSTOP_Pos))
    1641. 

  1641. #define SERCOM_USART_EXT_DBGCTRL_Msk          _U_(0x01)                                            /**< (SERCOM_USART_EXT_DBGCTRL) Register Mask  */
    1642. 

  1642. 

  1643. 

  1644. /* -------- SERCOM_USART_INT_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART_INT Debug Control -------- */
    1645. 

  1645. #define SERCOM_USART_INT_DBGCTRL_RESETVALUE   _U_(0x00)                                            /**<  (SERCOM_USART_INT_DBGCTRL) USART_INT Debug Control  Reset Value */
    1646. 

  1646. 

  1647. #define SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos  _U_(0)                                               /**< (SERCOM_USART_INT_DBGCTRL) Debug Mode Position */
    1648. 

  1648. #define SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk  (_U_(0x1) << SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos)   /**< (SERCOM_USART_INT_DBGCTRL) Debug Mode Mask */
    1649. 

  1649. #define SERCOM_USART_INT_DBGCTRL_DBGSTOP(value) (SERCOM_USART_INT_DBGCTRL_DBGSTOP_Msk & ((value) << SERCOM_USART_INT_DBGCTRL_DBGSTOP_Pos))
    1650. 

  1650. #define SERCOM_USART_INT_DBGCTRL_Msk          _U_(0x01)                                            /**< (SERCOM_USART_INT_DBGCTRL) Register Mask  */
    1651. 

  1651. 

  1652. 

  1653. /** \brief SERCOM register offsets definitions */
    1654. 

  1654. #define SERCOM_I2CM_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_I2CM_CTRLA) I2CM Control A Offset */
    1655. 

  1655. #define SERCOM_I2CS_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_I2CS_CTRLA) I2CS Control A Offset */
    1656. 

  1656. #define SERCOM_SPIM_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_SPIM_CTRLA) SPIM Control A Offset */
    1657. 

  1657. #define SERCOM_SPIS_CTRLA_REG_OFST     (0x00)              /**< (SERCOM_SPIS_CTRLA) SPIS Control A Offset */
    1658. 

  1658. #define SERCOM_USART_EXT_CTRLA_REG_OFST (0x00)              /**< (SERCOM_USART_EXT_CTRLA) USART_EXT Control A Offset */
    1659. 

  1659. #define SERCOM_USART_INT_CTRLA_REG_OFST (0x00)              /**< (SERCOM_USART_INT_CTRLA) USART_INT Control A Offset */
    1660. 

  1660. #define SERCOM_I2CM_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_I2CM_CTRLB) I2CM Control B Offset */
    1661. 

  1661. #define SERCOM_I2CS_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_I2CS_CTRLB) I2CS Control B Offset */
    1662. 

  1662. #define SERCOM_SPIM_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_SPIM_CTRLB) SPIM Control B Offset */
    1663. 

  1663. #define SERCOM_SPIS_CTRLB_REG_OFST     (0x04)              /**< (SERCOM_SPIS_CTRLB) SPIS Control B Offset */
    1664. 

  1664. #define SERCOM_USART_EXT_CTRLB_REG_OFST (0x04)              /**< (SERCOM_USART_EXT_CTRLB) USART_EXT Control B Offset */
    1665. 

  1665. #define SERCOM_USART_INT_CTRLB_REG_OFST (0x04)              /**< (SERCOM_USART_INT_CTRLB) USART_INT Control B Offset */
    1666. 

  1666. #define SERCOM_I2CM_BAUD_REG_OFST      (0x0C)              /**< (SERCOM_I2CM_BAUD) I2CM Baud Rate Offset */
    1667. 

  1667. #define SERCOM_SPIM_BAUD_REG_OFST      (0x0C)              /**< (SERCOM_SPIM_BAUD) SPIM Baud Rate Offset */
    1668. 

  1668. #define SERCOM_SPIS_BAUD_REG_OFST      (0x0C)              /**< (SERCOM_SPIS_BAUD) SPIS Baud Rate Offset */
    1669. 

  1669. #define SERCOM_USART_EXT_BAUD_REG_OFST (0x0C)              /**< (SERCOM_USART_EXT_BAUD) USART_EXT Baud Rate Offset */
    1670. 

  1670. #define SERCOM_USART_INT_BAUD_REG_OFST (0x0C)              /**< (SERCOM_USART_INT_BAUD) USART_INT Baud Rate Offset */
    1671. 

  1671. #define SERCOM_USART_EXT_RXPL_REG_OFST (0x0E)              /**< (SERCOM_USART_EXT_RXPL) USART_EXT Receive Pulse Length Offset */
    1672. 

  1672. #define SERCOM_USART_INT_RXPL_REG_OFST (0x0E)              /**< (SERCOM_USART_INT_RXPL) USART_INT Receive Pulse Length Offset */
    1673. 

  1673. #define SERCOM_I2CM_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_I2CM_INTENCLR) I2CM Interrupt Enable Clear Offset */
    1674. 

  1674. #define SERCOM_I2CS_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_I2CS_INTENCLR) I2CS Interrupt Enable Clear Offset */
    1675. 

  1675. #define SERCOM_SPIM_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_SPIM_INTENCLR) SPIM Interrupt Enable Clear Offset */
    1676. 

  1676. #define SERCOM_SPIS_INTENCLR_REG_OFST  (0x14)              /**< (SERCOM_SPIS_INTENCLR) SPIS Interrupt Enable Clear Offset */
    1677. 

  1677. #define SERCOM_USART_EXT_INTENCLR_REG_OFST (0x14)              /**< (SERCOM_USART_EXT_INTENCLR) USART_EXT Interrupt Enable Clear Offset */
    1678. 

  1678. #define SERCOM_USART_INT_INTENCLR_REG_OFST (0x14)              /**< (SERCOM_USART_INT_INTENCLR) USART_INT Interrupt Enable Clear Offset */
    1679. 

  1679. #define SERCOM_I2CM_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_I2CM_INTENSET) I2CM Interrupt Enable Set Offset */
    1680. 

  1680. #define SERCOM_I2CS_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_I2CS_INTENSET) I2CS Interrupt Enable Set Offset */
    1681. 

  1681. #define SERCOM_SPIM_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_SPIM_INTENSET) SPIM Interrupt Enable Set Offset */
    1682. 

  1682. #define SERCOM_SPIS_INTENSET_REG_OFST  (0x16)              /**< (SERCOM_SPIS_INTENSET) SPIS Interrupt Enable Set Offset */
    1683. 

  1683. #define SERCOM_USART_EXT_INTENSET_REG_OFST (0x16)              /**< (SERCOM_USART_EXT_INTENSET) USART_EXT Interrupt Enable Set Offset */
    1684. 

  1684. #define SERCOM_USART_INT_INTENSET_REG_OFST (0x16)              /**< (SERCOM_USART_INT_INTENSET) USART_INT Interrupt Enable Set Offset */
    1685. 

  1685. #define SERCOM_I2CM_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_I2CM_INTFLAG) I2CM Interrupt Flag Status and Clear Offset */
    1686. 

  1686. #define SERCOM_I2CS_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_I2CS_INTFLAG) I2CS Interrupt Flag Status and Clear Offset */
    1687. 

  1687. #define SERCOM_SPIM_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_SPIM_INTFLAG) SPIM Interrupt Flag Status and Clear Offset */
    1688. 

  1688. #define SERCOM_SPIS_INTFLAG_REG_OFST   (0x18)              /**< (SERCOM_SPIS_INTFLAG) SPIS Interrupt Flag Status and Clear Offset */
    1689. 

  1689. #define SERCOM_USART_EXT_INTFLAG_REG_OFST (0x18)              /**< (SERCOM_USART_EXT_INTFLAG) USART_EXT Interrupt Flag Status and Clear Offset */
    1690. 

  1690. #define SERCOM_USART_INT_INTFLAG_REG_OFST (0x18)              /**< (SERCOM_USART_INT_INTFLAG) USART_INT Interrupt Flag Status and Clear Offset */
    1691. 

  1691. #define SERCOM_I2CM_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_I2CM_STATUS) I2CM Status Offset */
    1692. 

  1692. #define SERCOM_I2CS_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_I2CS_STATUS) I2CS Status Offset */
    1693. 

  1693. #define SERCOM_SPIM_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_SPIM_STATUS) SPIM Status Offset */
    1694. 

  1694. #define SERCOM_SPIS_STATUS_REG_OFST    (0x1A)              /**< (SERCOM_SPIS_STATUS) SPIS Status Offset */
    1695. 

  1695. #define SERCOM_USART_EXT_STATUS_REG_OFST (0x1A)              /**< (SERCOM_USART_EXT_STATUS) USART_EXT Status Offset */
    1696. 

  1696. #define SERCOM_USART_INT_STATUS_REG_OFST (0x1A)              /**< (SERCOM_USART_INT_STATUS) USART_INT Status Offset */
    1697. 

  1697. #define SERCOM_I2CM_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_I2CM_SYNCBUSY) I2CM Synchronization Busy Offset */
    1698. 

  1698. #define SERCOM_I2CS_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_I2CS_SYNCBUSY) I2CS Synchronization Busy Offset */
    1699. 

  1699. #define SERCOM_SPIM_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_SPIM_SYNCBUSY) SPIM Synchronization Busy Offset */
    1700. 

  1700. #define SERCOM_SPIS_SYNCBUSY_REG_OFST  (0x1C)              /**< (SERCOM_SPIS_SYNCBUSY) SPIS Synchronization Busy Offset */
    1701. 

  1701. #define SERCOM_USART_EXT_SYNCBUSY_REG_OFST (0x1C)              /**< (SERCOM_USART_EXT_SYNCBUSY) USART_EXT Synchronization Busy Offset */
    1702. 

  1702. #define SERCOM_USART_INT_SYNCBUSY_REG_OFST (0x1C)              /**< (SERCOM_USART_INT_SYNCBUSY) USART_INT Synchronization Busy Offset */
    1703. 

  1703. #define SERCOM_I2CM_ADDR_REG_OFST      (0x24)              /**< (SERCOM_I2CM_ADDR) I2CM Address Offset */
    1704. 

  1704. #define SERCOM_I2CS_ADDR_REG_OFST      (0x24)              /**< (SERCOM_I2CS_ADDR) I2CS Address Offset */
    1705. 

  1705. #define SERCOM_SPIM_ADDR_REG_OFST      (0x24)              /**< (SERCOM_SPIM_ADDR) SPIM Address Offset */
    1706. 

  1706. #define SERCOM_SPIS_ADDR_REG_OFST      (0x24)              /**< (SERCOM_SPIS_ADDR) SPIS Address Offset */
    1707. 

  1707. #define SERCOM_I2CM_DATA_REG_OFST      (0x28)              /**< (SERCOM_I2CM_DATA) I2CM Data Offset */
    1708. 

  1708. #define SERCOM_I2CS_DATA_REG_OFST      (0x28)              /**< (SERCOM_I2CS_DATA) I2CS Data Offset */
    1709. 

  1709. #define SERCOM_SPIM_DATA_REG_OFST      (0x28)              /**< (SERCOM_SPIM_DATA) SPIM Data Offset */
    1710. 

  1710. #define SERCOM_SPIS_DATA_REG_OFST      (0x28)              /**< (SERCOM_SPIS_DATA) SPIS Data Offset */
    1711. 

  1711. #define SERCOM_USART_EXT_DATA_REG_OFST (0x28)              /**< (SERCOM_USART_EXT_DATA) USART_EXT Data Offset */
    1712. 

  1712. #define SERCOM_USART_INT_DATA_REG_OFST (0x28)              /**< (SERCOM_USART_INT_DATA) USART_INT Data Offset */
    1713. 

  1713. #define SERCOM_I2CM_DBGCTRL_REG_OFST   (0x30)              /**< (SERCOM_I2CM_DBGCTRL) I2CM Debug Control Offset */
    1714. 

  1714. #define SERCOM_SPIM_DBGCTRL_REG_OFST   (0x30)              /**< (SERCOM_SPIM_DBGCTRL) SPIM Debug Control Offset */
    1715. 

  1715. #define SERCOM_SPIS_DBGCTRL_REG_OFST   (0x30)              /**< (SERCOM_SPIS_DBGCTRL) SPIS Debug Control Offset */
    1716. 

  1716. #define SERCOM_USART_EXT_DBGCTRL_REG_OFST (0x30)              /**< (SERCOM_USART_EXT_DBGCTRL) USART_EXT Debug Control Offset */
    1717. 

  1717. #define SERCOM_USART_INT_DBGCTRL_REG_OFST (0x30)              /**< (SERCOM_USART_INT_DBGCTRL) USART_INT Debug Control Offset */
    1718. 

  1718. 

  1719. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    1720. 

  1720. /** \brief SERCOM register API structure */
    1721. 

  1721. typedef struct
    1722. 

  1722. {  /* Serial Communication Interface */
    1723. 

  1723.   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) I2CM Control A */
    1724. 

  1724.   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) I2CM Control B */
    1725. 

  1725.   __I   uint8_t                        Reserved1[0x04];
    1726. 

  1726.   __IO  uint32_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  32) I2CM Baud Rate */
    1727. 

  1727.   __I   uint8_t                        Reserved2[0x04];
    1728. 

  1728.   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) I2CM Interrupt Enable Clear */
    1729. 

  1729.   __I   uint8_t                        Reserved3[0x01];
    1730. 

  1730.   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) I2CM Interrupt Enable Set */
    1731. 

  1731.   __I   uint8_t                        Reserved4[0x01];
    1732. 

  1732.   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) I2CM Interrupt Flag Status and Clear */
    1733. 

  1733.   __I   uint8_t                        Reserved5[0x01];
    1734. 

  1734.   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) I2CM Status */
    1735. 

  1735.   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) I2CM Synchronization Busy */
    1736. 

  1736.   __I   uint8_t                        Reserved6[0x04];
    1737. 

  1737.   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) I2CM Address */
    1738. 

  1738.   __IO  uint8_t                        SERCOM_DATA;        /**< Offset: 0x28 (R/W  8) I2CM Data */
    1739. 

  1739.   __I   uint8_t                        Reserved7[0x07];
    1740. 

  1740.   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) I2CM Debug Control */
    1741. 

  1741. } sercom_i2cm_registers_t;
    1742. 

  1742. 

  1743. /** \brief SERCOM register API structure */
    1744. 

  1744. typedef struct
    1745. 

  1745. {  /* Serial Communication Interface */
    1746. 

  1746.   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) I2CS Control A */
    1747. 

  1747.   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) I2CS Control B */
    1748. 

  1748.   __I   uint8_t                        Reserved1[0x0C];
    1749. 

  1749.   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) I2CS Interrupt Enable Clear */
    1750. 

  1750.   __I   uint8_t                        Reserved2[0x01];
    1751. 

  1751.   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) I2CS Interrupt Enable Set */
    1752. 

  1752.   __I   uint8_t                        Reserved3[0x01];
    1753. 

  1753.   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) I2CS Interrupt Flag Status and Clear */
    1754. 

  1754.   __I   uint8_t                        Reserved4[0x01];
    1755. 

  1755.   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) I2CS Status */
    1756. 

  1756.   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) I2CS Synchronization Busy */
    1757. 

  1757.   __I   uint8_t                        Reserved5[0x04];
    1758. 

  1758.   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) I2CS Address */
    1759. 

  1759.   __IO  uint8_t                        SERCOM_DATA;        /**< Offset: 0x28 (R/W  8) I2CS Data */
    1760. 

  1760. } sercom_i2cs_registers_t;
    1761. 

  1761. 

  1762. /** \brief SERCOM register API structure */
    1763. 

  1763. typedef struct
    1764. 

  1764. {  /* Serial Communication Interface */
    1765. 

  1765.   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) SPIS Control A */
    1766. 

  1766.   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) SPIS Control B */
    1767. 

  1767.   __I   uint8_t                        Reserved1[0x04];
    1768. 

  1768.   __IO  uint8_t                        SERCOM_BAUD;        /**< Offset: 0x0C (R/W  8) SPIS Baud Rate */
    1769. 

  1769.   __I   uint8_t                        Reserved2[0x07];
    1770. 

  1770.   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) SPIS Interrupt Enable Clear */
    1771. 

  1771.   __I   uint8_t                        Reserved3[0x01];
    1772. 

  1772.   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) SPIS Interrupt Enable Set */
    1773. 

  1773.   __I   uint8_t                        Reserved4[0x01];
    1774. 

  1774.   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) SPIS Interrupt Flag Status and Clear */
    1775. 

  1775.   __I   uint8_t                        Reserved5[0x01];
    1776. 

  1776.   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) SPIS Status */
    1777. 

  1777.   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) SPIS Synchronization Busy */
    1778. 

  1778.   __I   uint8_t                        Reserved6[0x04];
    1779. 

  1779.   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) SPIS Address */
    1780. 

  1780.   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) SPIS Data */
    1781. 

  1781.   __I   uint8_t                        Reserved7[0x04];
    1782. 

  1782.   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) SPIS Debug Control */
    1783. 

  1783. } sercom_spis_registers_t;
    1784. 

  1784. 

  1785. /** \brief SERCOM register API structure */
    1786. 

  1786. typedef struct
    1787. 

  1787. {  /* Serial Communication Interface */
    1788. 

  1788.   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) SPIM Control A */
    1789. 

  1789.   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) SPIM Control B */
    1790. 

  1790.   __I   uint8_t                        Reserved1[0x04];
    1791. 

  1791.   __IO  uint8_t                        SERCOM_BAUD;        /**< Offset: 0x0C (R/W  8) SPIM Baud Rate */
    1792. 

  1792.   __I   uint8_t                        Reserved2[0x07];
    1793. 

  1793.   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) SPIM Interrupt Enable Clear */
    1794. 

  1794.   __I   uint8_t                        Reserved3[0x01];
    1795. 

  1795.   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) SPIM Interrupt Enable Set */
    1796. 

  1796.   __I   uint8_t                        Reserved4[0x01];
    1797. 

  1797.   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) SPIM Interrupt Flag Status and Clear */
    1798. 

  1798.   __I   uint8_t                        Reserved5[0x01];
    1799. 

  1799.   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) SPIM Status */
    1800. 

  1800.   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) SPIM Synchronization Busy */
    1801. 

  1801.   __I   uint8_t                        Reserved6[0x04];
    1802. 

  1802.   __IO  uint32_t                       SERCOM_ADDR;        /**< Offset: 0x24 (R/W  32) SPIM Address */
    1803. 

  1803.   __IO  uint32_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  32) SPIM Data */
    1804. 

  1804.   __I   uint8_t                        Reserved7[0x04];
    1805. 

  1805.   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) SPIM Debug Control */
    1806. 

  1806. } sercom_spim_registers_t;
    1807. 

  1807. 

  1808. /** \brief SERCOM register API structure */
    1809. 

  1809. typedef struct
    1810. 

  1810. {  /* Serial Communication Interface */
    1811. 

  1811.   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) USART_EXT Control A */
    1812. 

  1812.   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) USART_EXT Control B */
    1813. 

  1813.   __I   uint8_t                        Reserved1[0x04];
    1814. 

  1814.   __IO  uint16_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  16) USART_EXT Baud Rate */
    1815. 

  1815.   __IO  uint8_t                        SERCOM_RXPL;        /**< Offset: 0x0E (R/W  8) USART_EXT Receive Pulse Length */
    1816. 

  1816.   __I   uint8_t                        Reserved2[0x05];
    1817. 

  1817.   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) USART_EXT Interrupt Enable Clear */
    1818. 

  1818.   __I   uint8_t                        Reserved3[0x01];
    1819. 

  1819.   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) USART_EXT Interrupt Enable Set */
    1820. 

  1820.   __I   uint8_t                        Reserved4[0x01];
    1821. 

  1821.   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) USART_EXT Interrupt Flag Status and Clear */
    1822. 

  1822.   __I   uint8_t                        Reserved5[0x01];
    1823. 

  1823.   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) USART_EXT Status */
    1824. 

  1824.   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) USART_EXT Synchronization Busy */
    1825. 

  1825.   __I   uint8_t                        Reserved6[0x08];
    1826. 

  1826.   __IO  uint16_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  16) USART_EXT Data */
    1827. 

  1827.   __I   uint8_t                        Reserved7[0x06];
    1828. 

  1828.   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) USART_EXT Debug Control */
    1829. 

  1829. } sercom_usart_ext_registers_t;
    1830. 

  1830. 

  1831. /** \brief SERCOM register API structure */
    1832. 

  1832. typedef struct
    1833. 

  1833. {  /* Serial Communication Interface */
    1834. 

  1834.   __IO  uint32_t                       SERCOM_CTRLA;       /**< Offset: 0x00 (R/W  32) USART_INT Control A */
    1835. 

  1835.   __IO  uint32_t                       SERCOM_CTRLB;       /**< Offset: 0x04 (R/W  32) USART_INT Control B */
    1836. 

  1836.   __I   uint8_t                        Reserved1[0x04];
    1837. 

  1837.   __IO  uint16_t                       SERCOM_BAUD;        /**< Offset: 0x0C (R/W  16) USART_INT Baud Rate */
    1838. 

  1838.   __IO  uint8_t                        SERCOM_RXPL;        /**< Offset: 0x0E (R/W  8) USART_INT Receive Pulse Length */
    1839. 

  1839.   __I   uint8_t                        Reserved2[0x05];
    1840. 

  1840.   __IO  uint8_t                        SERCOM_INTENCLR;    /**< Offset: 0x14 (R/W  8) USART_INT Interrupt Enable Clear */
    1841. 

  1841.   __I   uint8_t                        Reserved3[0x01];
    1842. 

  1842.   __IO  uint8_t                        SERCOM_INTENSET;    /**< Offset: 0x16 (R/W  8) USART_INT Interrupt Enable Set */
    1843. 

  1843.   __I   uint8_t                        Reserved4[0x01];
    1844. 

  1844.   __IO  uint8_t                        SERCOM_INTFLAG;     /**< Offset: 0x18 (R/W  8) USART_INT Interrupt Flag Status and Clear */
    1845. 

  1845.   __I   uint8_t                        Reserved5[0x01];
    1846. 

  1846.   __IO  uint16_t                       SERCOM_STATUS;      /**< Offset: 0x1A (R/W  16) USART_INT Status */
    1847. 

  1847.   __I   uint32_t                       SERCOM_SYNCBUSY;    /**< Offset: 0x1C (R/   32) USART_INT Synchronization Busy */
    1848. 

  1848.   __I   uint8_t                        Reserved6[0x08];
    1849. 

  1849.   __IO  uint16_t                       SERCOM_DATA;        /**< Offset: 0x28 (R/W  16) USART_INT Data */
    1850. 

  1850.   __I   uint8_t                        Reserved7[0x06];
    1851. 

  1851.   __IO  uint8_t                        SERCOM_DBGCTRL;     /**< Offset: 0x30 (R/W  8) USART_INT Debug Control */
    1852. 

  1852. } sercom_usart_int_registers_t;
    1853. 

  1853. 

  1854. /** \brief SERCOM hardware registers */
    1855. 

  1855. typedef union
    1856. 

  1856. {  /* Serial Communication Interface */
    1857. 

  1857.        sercom_i2cm_registers_t        I2CM;           /**< I2C Master Mode */
    1858. 

  1858.        sercom_i2cs_registers_t        I2CS;           /**< I2C Slave Mode */
    1859. 

  1859.        sercom_spis_registers_t        SPIS;           /**< SPI Slave Mode */
    1860. 

  1860.        sercom_spim_registers_t        SPIM;           /**< SPI Master Mode */
    1861. 

  1861.        sercom_usart_ext_registers_t   USART_EXT;      /**< USART EXTERNAL CLOCK Mode */
    1862. 

  1862.        sercom_usart_int_registers_t   USART_INT;      /**< USART INTERNAL CLOCK Mode */
    1863. 

  1863. } sercom_registers_t;
    1864. 

  1864. 

  1865. 

  1866. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    1867. 

  1867. #endif /* _SAMD21_SERCOM_COMPONENT_H_ */
    1868.