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sdk-csp-atsamd2...
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tc.h

tc.h 48 KB
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  1. /**
    2. 

  2.  * \brief Component description for TC
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_TC_COMPONENT_H_
    25. 

  25. #define _SAMD21_TC_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR TC                                           */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
    32. 

  32. #define TC_CTRLA_RESETVALUE                   _U_(0x00)                                            /**<  (TC_CTRLA) Control A  Reset Value */
    33. 

  33. 

  34. #define TC_CTRLA_SWRST_Pos                    _U_(0)                                               /**< (TC_CTRLA) Software Reset Position */
    35. 

  35. #define TC_CTRLA_SWRST_Msk                    (_U_(0x1) << TC_CTRLA_SWRST_Pos)                     /**< (TC_CTRLA) Software Reset Mask */
    36. 

  36. #define TC_CTRLA_SWRST(value)                 (TC_CTRLA_SWRST_Msk & ((value) << TC_CTRLA_SWRST_Pos))
    37. 

  37. #define TC_CTRLA_ENABLE_Pos                   _U_(1)                                               /**< (TC_CTRLA) Enable Position */
    38. 

  38. #define TC_CTRLA_ENABLE_Msk                   (_U_(0x1) << TC_CTRLA_ENABLE_Pos)                    /**< (TC_CTRLA) Enable Mask */
    39. 

  39. #define TC_CTRLA_ENABLE(value)                (TC_CTRLA_ENABLE_Msk & ((value) << TC_CTRLA_ENABLE_Pos))
    40. 

  40. #define TC_CTRLA_MODE_Pos                     _U_(2)                                               /**< (TC_CTRLA) TC Mode Position */
    41. 

  41. #define TC_CTRLA_MODE_Msk                     (_U_(0x3) << TC_CTRLA_MODE_Pos)                      /**< (TC_CTRLA) TC Mode Mask */
    42. 

  42. #define TC_CTRLA_MODE(value)                  (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
    43. 

  43. #define   TC_CTRLA_MODE_COUNT16_Val           _U_(0x0)                                             /**< (TC_CTRLA) Counter in 16-bit mode  */
    44. 

  44. #define   TC_CTRLA_MODE_COUNT8_Val            _U_(0x1)                                             /**< (TC_CTRLA) Counter in 8-bit mode  */
    45. 

  45. #define   TC_CTRLA_MODE_COUNT32_Val           _U_(0x2)                                             /**< (TC_CTRLA) Counter in 32-bit mode  */
    46. 

  46. #define TC_CTRLA_MODE_COUNT16                 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)     /**< (TC_CTRLA) Counter in 16-bit mode Position  */
    47. 

  47. #define TC_CTRLA_MODE_COUNT8                  (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)      /**< (TC_CTRLA) Counter in 8-bit mode Position  */
    48. 

  48. #define TC_CTRLA_MODE_COUNT32                 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)     /**< (TC_CTRLA) Counter in 32-bit mode Position  */
    49. 

  49. #define TC_CTRLA_WAVEGEN_Pos                  _U_(5)                                               /**< (TC_CTRLA) Waveform Generation Operation Position */
    50. 

  50. #define TC_CTRLA_WAVEGEN_Msk                  (_U_(0x3) << TC_CTRLA_WAVEGEN_Pos)                   /**< (TC_CTRLA) Waveform Generation Operation Mask */
    51. 

  51. #define TC_CTRLA_WAVEGEN(value)               (TC_CTRLA_WAVEGEN_Msk & ((value) << TC_CTRLA_WAVEGEN_Pos))
    52. 

  52. #define   TC_CTRLA_WAVEGEN_NFRQ_Val           _U_(0x0)                                             /**< (TC_CTRLA)   */
    53. 

  53. #define   TC_CTRLA_WAVEGEN_MFRQ_Val           _U_(0x1)                                             /**< (TC_CTRLA)   */
    54. 

  54. #define   TC_CTRLA_WAVEGEN_NPWM_Val           _U_(0x2)                                             /**< (TC_CTRLA)   */
    55. 

  55. #define   TC_CTRLA_WAVEGEN_MPWM_Val           _U_(0x3)                                             /**< (TC_CTRLA)   */
    56. 

  56. #define TC_CTRLA_WAVEGEN_NFRQ                 (TC_CTRLA_WAVEGEN_NFRQ_Val << TC_CTRLA_WAVEGEN_Pos)  /**< (TC_CTRLA)  Position  */
    57. 

  57. #define TC_CTRLA_WAVEGEN_MFRQ                 (TC_CTRLA_WAVEGEN_MFRQ_Val << TC_CTRLA_WAVEGEN_Pos)  /**< (TC_CTRLA)  Position  */
    58. 

  58. #define TC_CTRLA_WAVEGEN_NPWM                 (TC_CTRLA_WAVEGEN_NPWM_Val << TC_CTRLA_WAVEGEN_Pos)  /**< (TC_CTRLA)  Position  */
    59. 

  59. #define TC_CTRLA_WAVEGEN_MPWM                 (TC_CTRLA_WAVEGEN_MPWM_Val << TC_CTRLA_WAVEGEN_Pos)  /**< (TC_CTRLA)  Position  */
    60. 

  60. #define TC_CTRLA_PRESCALER_Pos                _U_(8)                                               /**< (TC_CTRLA) Prescaler Position */
    61. 

  61. #define TC_CTRLA_PRESCALER_Msk                (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)                 /**< (TC_CTRLA) Prescaler Mask */
    62. 

  62. #define TC_CTRLA_PRESCALER(value)             (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
    63. 

  63. #define   TC_CTRLA_PRESCALER_DIV1_Val         _U_(0x0)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC  */
    64. 

  64. #define   TC_CTRLA_PRESCALER_DIV2_Val         _U_(0x1)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/2  */
    65. 

  65. #define   TC_CTRLA_PRESCALER_DIV4_Val         _U_(0x2)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/4  */
    66. 

  66. #define   TC_CTRLA_PRESCALER_DIV8_Val         _U_(0x3)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/8  */
    67. 

  67. #define   TC_CTRLA_PRESCALER_DIV16_Val        _U_(0x4)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/16  */
    68. 

  68. #define   TC_CTRLA_PRESCALER_DIV64_Val        _U_(0x5)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/64  */
    69. 

  69. #define   TC_CTRLA_PRESCALER_DIV256_Val       _U_(0x6)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/256  */
    70. 

  70. #define   TC_CTRLA_PRESCALER_DIV1024_Val      _U_(0x7)                                             /**< (TC_CTRLA) Prescaler: GCLK_TC/1024  */
    71. 

  71. #define TC_CTRLA_PRESCALER_DIV1               (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC Position  */
    72. 

  72. #define TC_CTRLA_PRESCALER_DIV2               (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/2 Position  */
    73. 

  73. #define TC_CTRLA_PRESCALER_DIV4               (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/4 Position  */
    74. 

  74. #define TC_CTRLA_PRESCALER_DIV8               (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/8 Position  */
    75. 

  75. #define TC_CTRLA_PRESCALER_DIV16              (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/16 Position  */
    76. 

  76. #define TC_CTRLA_PRESCALER_DIV64              (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/64 Position  */
    77. 

  77. #define TC_CTRLA_PRESCALER_DIV256             (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/256 Position  */
    78. 

  78. #define TC_CTRLA_PRESCALER_DIV1024            (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) /**< (TC_CTRLA) Prescaler: GCLK_TC/1024 Position  */
    79. 

  79. #define TC_CTRLA_RUNSTDBY_Pos                 _U_(11)                                              /**< (TC_CTRLA) Run in Standby Position */
    80. 

  80. #define TC_CTRLA_RUNSTDBY_Msk                 (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)                  /**< (TC_CTRLA) Run in Standby Mask */
    81. 

  81. #define TC_CTRLA_RUNSTDBY(value)              (TC_CTRLA_RUNSTDBY_Msk & ((value) << TC_CTRLA_RUNSTDBY_Pos))
    82. 

  82. #define TC_CTRLA_PRESCSYNC_Pos                _U_(12)                                              /**< (TC_CTRLA) Prescaler and Counter Synchronization Position */
    83. 

  83. #define TC_CTRLA_PRESCSYNC_Msk                (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)                 /**< (TC_CTRLA) Prescaler and Counter Synchronization Mask */
    84. 

  84. #define TC_CTRLA_PRESCSYNC(value)             (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
    85. 

  85. #define   TC_CTRLA_PRESCSYNC_GCLK_Val         _U_(0x0)                                             /**< (TC_CTRLA) Reload or reset the counter on next generic clock  */
    86. 

  86. #define   TC_CTRLA_PRESCSYNC_PRESC_Val        _U_(0x1)                                             /**< (TC_CTRLA) Reload or reset the counter on next prescaler clock  */
    87. 

  87. #define   TC_CTRLA_PRESCSYNC_RESYNC_Val       _U_(0x2)                                             /**< (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter  */
    88. 

  88. #define TC_CTRLA_PRESCSYNC_GCLK               (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next generic clock Position  */
    89. 

  89. #define TC_CTRLA_PRESCSYNC_PRESC              (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next prescaler clock Position  */
    90. 

  90. #define TC_CTRLA_PRESCSYNC_RESYNC             (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) /**< (TC_CTRLA) Reload or reset the counter on next generic clock. Reset the prescaler counter Position  */
    91. 

  91. #define TC_CTRLA_Msk                          _U_(0x3F6F)                                          /**< (TC_CTRLA) Register Mask  */
    92. 

  92. 

  93. 

  94. /* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
    95. 

  95. #define TC_READREQ_RESETVALUE                 _U_(0x00)                                            /**<  (TC_READREQ) Read Request  Reset Value */
    96. 

  96. 

  97. #define TC_READREQ_ADDR_Pos                   _U_(0)                                               /**< (TC_READREQ) Address Position */
    98. 

  98. #define TC_READREQ_ADDR_Msk                   (_U_(0x1F) << TC_READREQ_ADDR_Pos)                   /**< (TC_READREQ) Address Mask */
    99. 

  99. #define TC_READREQ_ADDR(value)                (TC_READREQ_ADDR_Msk & ((value) << TC_READREQ_ADDR_Pos))
    100. 

  100. #define TC_READREQ_RCONT_Pos                  _U_(14)                                              /**< (TC_READREQ) Read Continuously Position */
    101. 

  101. #define TC_READREQ_RCONT_Msk                  (_U_(0x1) << TC_READREQ_RCONT_Pos)                   /**< (TC_READREQ) Read Continuously Mask */
    102. 

  102. #define TC_READREQ_RCONT(value)               (TC_READREQ_RCONT_Msk & ((value) << TC_READREQ_RCONT_Pos))
    103. 

  103. #define TC_READREQ_RREQ_Pos                   _U_(15)                                              /**< (TC_READREQ) Read Request Position */
    104. 

  104. #define TC_READREQ_RREQ_Msk                   (_U_(0x1) << TC_READREQ_RREQ_Pos)                    /**< (TC_READREQ) Read Request Mask */
    105. 

  105. #define TC_READREQ_RREQ(value)                (TC_READREQ_RREQ_Msk & ((value) << TC_READREQ_RREQ_Pos))
    106. 

  106. #define TC_READREQ_Msk                        _U_(0xC01F)                                          /**< (TC_READREQ) Register Mask  */
    107. 

  107. 

  108. 

  109. /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
    110. 

  110. #define TC_CTRLBCLR_RESETVALUE                _U_(0x02)                                            /**<  (TC_CTRLBCLR) Control B Clear  Reset Value */
    111. 

  111. 

  112. #define TC_CTRLBCLR_DIR_Pos                   _U_(0)                                               /**< (TC_CTRLBCLR) Counter Direction Position */
    113. 

  113. #define TC_CTRLBCLR_DIR_Msk                   (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)                    /**< (TC_CTRLBCLR) Counter Direction Mask */
    114. 

  114. #define TC_CTRLBCLR_DIR(value)                (TC_CTRLBCLR_DIR_Msk & ((value) << TC_CTRLBCLR_DIR_Pos))
    115. 

  115. #define TC_CTRLBCLR_ONESHOT_Pos               _U_(2)                                               /**< (TC_CTRLBCLR) One-Shot Position */
    116. 

  116. #define TC_CTRLBCLR_ONESHOT_Msk               (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)                /**< (TC_CTRLBCLR) One-Shot Mask */
    117. 

  117. #define TC_CTRLBCLR_ONESHOT(value)            (TC_CTRLBCLR_ONESHOT_Msk & ((value) << TC_CTRLBCLR_ONESHOT_Pos))
    118. 

  118. #define TC_CTRLBCLR_CMD_Pos                   _U_(6)                                               /**< (TC_CTRLBCLR) Command Position */
    119. 

  119. #define TC_CTRLBCLR_CMD_Msk                   (_U_(0x3) << TC_CTRLBCLR_CMD_Pos)                    /**< (TC_CTRLBCLR) Command Mask */
    120. 

  120. #define TC_CTRLBCLR_CMD(value)                (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
    121. 

  121. #define   TC_CTRLBCLR_CMD_NONE_Val            _U_(0x0)                                             /**< (TC_CTRLBCLR) No action  */
    122. 

  122. #define   TC_CTRLBCLR_CMD_RETRIGGER_Val       _U_(0x1)                                             /**< (TC_CTRLBCLR) Force a start, restart or retrigger  */
    123. 

  123. #define   TC_CTRLBCLR_CMD_STOP_Val            _U_(0x2)                                             /**< (TC_CTRLBCLR) Force a stop  */
    124. 

  124. #define TC_CTRLBCLR_CMD_NONE                  (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)    /**< (TC_CTRLBCLR) No action Position  */
    125. 

  125. #define TC_CTRLBCLR_CMD_RETRIGGER             (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) /**< (TC_CTRLBCLR) Force a start, restart or retrigger Position  */
    126. 

  126. #define TC_CTRLBCLR_CMD_STOP                  (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)    /**< (TC_CTRLBCLR) Force a stop Position  */
    127. 

  127. #define TC_CTRLBCLR_Msk                       _U_(0xC5)                                            /**< (TC_CTRLBCLR) Register Mask  */
    128. 

  128. 

  129. 

  130. /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
    131. 

  131. #define TC_CTRLBSET_RESETVALUE                _U_(0x00)                                            /**<  (TC_CTRLBSET) Control B Set  Reset Value */
    132. 

  132. 

  133. #define TC_CTRLBSET_DIR_Pos                   _U_(0)                                               /**< (TC_CTRLBSET) Counter Direction Position */
    134. 

  134. #define TC_CTRLBSET_DIR_Msk                   (_U_(0x1) << TC_CTRLBSET_DIR_Pos)                    /**< (TC_CTRLBSET) Counter Direction Mask */
    135. 

  135. #define TC_CTRLBSET_DIR(value)                (TC_CTRLBSET_DIR_Msk & ((value) << TC_CTRLBSET_DIR_Pos))
    136. 

  136. #define TC_CTRLBSET_ONESHOT_Pos               _U_(2)                                               /**< (TC_CTRLBSET) One-Shot Position */
    137. 

  137. #define TC_CTRLBSET_ONESHOT_Msk               (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)                /**< (TC_CTRLBSET) One-Shot Mask */
    138. 

  138. #define TC_CTRLBSET_ONESHOT(value)            (TC_CTRLBSET_ONESHOT_Msk & ((value) << TC_CTRLBSET_ONESHOT_Pos))
    139. 

  139. #define TC_CTRLBSET_CMD_Pos                   _U_(6)                                               /**< (TC_CTRLBSET) Command Position */
    140. 

  140. #define TC_CTRLBSET_CMD_Msk                   (_U_(0x3) << TC_CTRLBSET_CMD_Pos)                    /**< (TC_CTRLBSET) Command Mask */
    141. 

  141. #define TC_CTRLBSET_CMD(value)                (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
    142. 

  142. #define   TC_CTRLBSET_CMD_NONE_Val            _U_(0x0)                                             /**< (TC_CTRLBSET) No action  */
    143. 

  143. #define   TC_CTRLBSET_CMD_RETRIGGER_Val       _U_(0x1)                                             /**< (TC_CTRLBSET) Force a start, restart or retrigger  */
    144. 

  144. #define   TC_CTRLBSET_CMD_STOP_Val            _U_(0x2)                                             /**< (TC_CTRLBSET) Force a stop  */
    145. 

  145. #define TC_CTRLBSET_CMD_NONE                  (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)    /**< (TC_CTRLBSET) No action Position  */
    146. 

  146. #define TC_CTRLBSET_CMD_RETRIGGER             (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) /**< (TC_CTRLBSET) Force a start, restart or retrigger Position  */
    147. 

  147. #define TC_CTRLBSET_CMD_STOP                  (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)    /**< (TC_CTRLBSET) Force a stop Position  */
    148. 

  148. #define TC_CTRLBSET_Msk                       _U_(0xC5)                                            /**< (TC_CTRLBSET) Register Mask  */
    149. 

  149. 

  150. 

  151. /* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
    152. 

  152. #define TC_CTRLC_RESETVALUE                   _U_(0x00)                                            /**<  (TC_CTRLC) Control C  Reset Value */
    153. 

  153. 

  154. #define TC_CTRLC_INVEN0_Pos                   _U_(0)                                               /**< (TC_CTRLC) Output Waveform 0 Invert Enable Position */
    155. 

  155. #define TC_CTRLC_INVEN0_Msk                   (_U_(0x1) << TC_CTRLC_INVEN0_Pos)                    /**< (TC_CTRLC) Output Waveform 0 Invert Enable Mask */
    156. 

  156. #define TC_CTRLC_INVEN0(value)                (TC_CTRLC_INVEN0_Msk & ((value) << TC_CTRLC_INVEN0_Pos))
    157. 

  157. #define TC_CTRLC_INVEN1_Pos                   _U_(1)                                               /**< (TC_CTRLC) Output Waveform 1 Invert Enable Position */
    158. 

  158. #define TC_CTRLC_INVEN1_Msk                   (_U_(0x1) << TC_CTRLC_INVEN1_Pos)                    /**< (TC_CTRLC) Output Waveform 1 Invert Enable Mask */
    159. 

  159. #define TC_CTRLC_INVEN1(value)                (TC_CTRLC_INVEN1_Msk & ((value) << TC_CTRLC_INVEN1_Pos))
    160. 

  160. #define TC_CTRLC_CPTEN0_Pos                   _U_(4)                                               /**< (TC_CTRLC) Capture Channel 0 Enable Position */
    161. 

  161. #define TC_CTRLC_CPTEN0_Msk                   (_U_(0x1) << TC_CTRLC_CPTEN0_Pos)                    /**< (TC_CTRLC) Capture Channel 0 Enable Mask */
    162. 

  162. #define TC_CTRLC_CPTEN0(value)                (TC_CTRLC_CPTEN0_Msk & ((value) << TC_CTRLC_CPTEN0_Pos))
    163. 

  163. #define TC_CTRLC_CPTEN1_Pos                   _U_(5)                                               /**< (TC_CTRLC) Capture Channel 1 Enable Position */
    164. 

  164. #define TC_CTRLC_CPTEN1_Msk                   (_U_(0x1) << TC_CTRLC_CPTEN1_Pos)                    /**< (TC_CTRLC) Capture Channel 1 Enable Mask */
    165. 

  165. #define TC_CTRLC_CPTEN1(value)                (TC_CTRLC_CPTEN1_Msk & ((value) << TC_CTRLC_CPTEN1_Pos))
    166. 

  166. #define TC_CTRLC_Msk                          _U_(0x33)                                            /**< (TC_CTRLC) Register Mask  */
    167. 

  167. 

  168. #define TC_CTRLC_INVEN_Pos                    _U_(0)                                               /**< (TC_CTRLC Position) Output Waveform x Invert Enable */
    169. 

  169. #define TC_CTRLC_INVEN_Msk                    (_U_(0x3) << TC_CTRLC_INVEN_Pos)                     /**< (TC_CTRLC Mask) INVEN */
    170. 

  170. #define TC_CTRLC_INVEN(value)                 (TC_CTRLC_INVEN_Msk & ((value) << TC_CTRLC_INVEN_Pos)) 
    171. 

  171. #define TC_CTRLC_CPTEN_Pos                    _U_(4)                                               /**< (TC_CTRLC Position) Capture Channel x Enable */
    172. 

  172. #define TC_CTRLC_CPTEN_Msk                    (_U_(0x3) << TC_CTRLC_CPTEN_Pos)                     /**< (TC_CTRLC Mask) CPTEN */
    173. 

  173. #define TC_CTRLC_CPTEN(value)                 (TC_CTRLC_CPTEN_Msk & ((value) << TC_CTRLC_CPTEN_Pos)) 
    174. 

  174. 

  175. /* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
    176. 

  176. #define TC_DBGCTRL_RESETVALUE                 _U_(0x00)                                            /**<  (TC_DBGCTRL) Debug Control  Reset Value */
    177. 

  177. 

  178. #define TC_DBGCTRL_DBGRUN_Pos                 _U_(0)                                               /**< (TC_DBGCTRL) Debug Run Mode Position */
    179. 

  179. #define TC_DBGCTRL_DBGRUN_Msk                 (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)                  /**< (TC_DBGCTRL) Debug Run Mode Mask */
    180. 

  180. #define TC_DBGCTRL_DBGRUN(value)              (TC_DBGCTRL_DBGRUN_Msk & ((value) << TC_DBGCTRL_DBGRUN_Pos))
    181. 

  181. #define TC_DBGCTRL_Msk                        _U_(0x01)                                            /**< (TC_DBGCTRL) Register Mask  */
    182. 

  182. 

  183. 

  184. /* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
    185. 

  185. #define TC_EVCTRL_RESETVALUE                  _U_(0x00)                                            /**<  (TC_EVCTRL) Event Control  Reset Value */
    186. 

  186. 

  187. #define TC_EVCTRL_EVACT_Pos                   _U_(0)                                               /**< (TC_EVCTRL) Event Action Position */
    188. 

  188. #define TC_EVCTRL_EVACT_Msk                   (_U_(0x7) << TC_EVCTRL_EVACT_Pos)                    /**< (TC_EVCTRL) Event Action Mask */
    189. 

  189. #define TC_EVCTRL_EVACT(value)                (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
    190. 

  190. #define   TC_EVCTRL_EVACT_OFF_Val             _U_(0x0)                                             /**< (TC_EVCTRL) Event action disabled  */
    191. 

  191. #define   TC_EVCTRL_EVACT_RETRIGGER_Val       _U_(0x1)                                             /**< (TC_EVCTRL) Start, restart or retrigger TC on event  */
    192. 

  192. #define   TC_EVCTRL_EVACT_COUNT_Val           _U_(0x2)                                             /**< (TC_EVCTRL) Count on event  */
    193. 

  193. #define   TC_EVCTRL_EVACT_START_Val           _U_(0x3)                                             /**< (TC_EVCTRL) Start TC on event  */
    194. 

  194. #define   TC_EVCTRL_EVACT_PPW_Val             _U_(0x5)                                             /**< (TC_EVCTRL) Period captured in CC0, pulse width in CC1  */
    195. 

  195. #define   TC_EVCTRL_EVACT_PWP_Val             _U_(0x6)                                             /**< (TC_EVCTRL) Period captured in CC1, pulse width in CC0  */
    196. 

  196. #define TC_EVCTRL_EVACT_OFF                   (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)     /**< (TC_EVCTRL) Event action disabled Position  */
    197. 

  197. #define TC_EVCTRL_EVACT_RETRIGGER             (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) /**< (TC_EVCTRL) Start, restart or retrigger TC on event Position  */
    198. 

  198. #define TC_EVCTRL_EVACT_COUNT                 (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)   /**< (TC_EVCTRL) Count on event Position  */
    199. 

  199. #define TC_EVCTRL_EVACT_START                 (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)   /**< (TC_EVCTRL) Start TC on event Position  */
    200. 

  200. #define TC_EVCTRL_EVACT_PPW                   (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)     /**< (TC_EVCTRL) Period captured in CC0, pulse width in CC1 Position  */
    201. 

  201. #define TC_EVCTRL_EVACT_PWP                   (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)     /**< (TC_EVCTRL) Period captured in CC1, pulse width in CC0 Position  */
    202. 

  202. #define TC_EVCTRL_TCINV_Pos                   _U_(4)                                               /**< (TC_EVCTRL) TC Inverted Event Input Position */
    203. 

  203. #define TC_EVCTRL_TCINV_Msk                   (_U_(0x1) << TC_EVCTRL_TCINV_Pos)                    /**< (TC_EVCTRL) TC Inverted Event Input Mask */
    204. 

  204. #define TC_EVCTRL_TCINV(value)                (TC_EVCTRL_TCINV_Msk & ((value) << TC_EVCTRL_TCINV_Pos))
    205. 

  205. #define TC_EVCTRL_TCEI_Pos                    _U_(5)                                               /**< (TC_EVCTRL) TC Event Input Position */
    206. 

  206. #define TC_EVCTRL_TCEI_Msk                    (_U_(0x1) << TC_EVCTRL_TCEI_Pos)                     /**< (TC_EVCTRL) TC Event Input Mask */
    207. 

  207. #define TC_EVCTRL_TCEI(value)                 (TC_EVCTRL_TCEI_Msk & ((value) << TC_EVCTRL_TCEI_Pos))
    208. 

  208. #define TC_EVCTRL_OVFEO_Pos                   _U_(8)                                               /**< (TC_EVCTRL) Overflow/Underflow Event Output Enable Position */
    209. 

  209. #define TC_EVCTRL_OVFEO_Msk                   (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)                    /**< (TC_EVCTRL) Overflow/Underflow Event Output Enable Mask */
    210. 

  210. #define TC_EVCTRL_OVFEO(value)                (TC_EVCTRL_OVFEO_Msk & ((value) << TC_EVCTRL_OVFEO_Pos))
    211. 

  211. #define TC_EVCTRL_MCEO0_Pos                   _U_(12)                                              /**< (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable Position */
    212. 

  212. #define TC_EVCTRL_MCEO0_Msk                   (_U_(0x1) << TC_EVCTRL_MCEO0_Pos)                    /**< (TC_EVCTRL) Match or Capture Channel 0 Event Output Enable Mask */
    213. 

  213. #define TC_EVCTRL_MCEO0(value)                (TC_EVCTRL_MCEO0_Msk & ((value) << TC_EVCTRL_MCEO0_Pos))
    214. 

  214. #define TC_EVCTRL_MCEO1_Pos                   _U_(13)                                              /**< (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable Position */
    215. 

  215. #define TC_EVCTRL_MCEO1_Msk                   (_U_(0x1) << TC_EVCTRL_MCEO1_Pos)                    /**< (TC_EVCTRL) Match or Capture Channel 1 Event Output Enable Mask */
    216. 

  216. #define TC_EVCTRL_MCEO1(value)                (TC_EVCTRL_MCEO1_Msk & ((value) << TC_EVCTRL_MCEO1_Pos))
    217. 

  217. #define TC_EVCTRL_Msk                         _U_(0x3137)                                          /**< (TC_EVCTRL) Register Mask  */
    218. 

  218. 

  219. #define TC_EVCTRL_MCEO_Pos                    _U_(12)                                              /**< (TC_EVCTRL Position) Match or Capture Channel x Event Output Enable */
    220. 

  220. #define TC_EVCTRL_MCEO_Msk                    (_U_(0x3) << TC_EVCTRL_MCEO_Pos)                     /**< (TC_EVCTRL Mask) MCEO */
    221. 

  221. #define TC_EVCTRL_MCEO(value)                 (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) 
    222. 

  222. 

  223. /* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
    224. 

  224. #define TC_INTENCLR_RESETVALUE                _U_(0x00)                                            /**<  (TC_INTENCLR) Interrupt Enable Clear  Reset Value */
    225. 

  225. 

  226. #define TC_INTENCLR_OVF_Pos                   _U_(0)                                               /**< (TC_INTENCLR) Overflow Interrupt Enable Position */
    227. 

  227. #define TC_INTENCLR_OVF_Msk                   (_U_(0x1) << TC_INTENCLR_OVF_Pos)                    /**< (TC_INTENCLR) Overflow Interrupt Enable Mask */
    228. 

  228. #define TC_INTENCLR_OVF(value)                (TC_INTENCLR_OVF_Msk & ((value) << TC_INTENCLR_OVF_Pos))
    229. 

  229. #define TC_INTENCLR_ERR_Pos                   _U_(1)                                               /**< (TC_INTENCLR) Error Interrupt Enable Position */
    230. 

  230. #define TC_INTENCLR_ERR_Msk                   (_U_(0x1) << TC_INTENCLR_ERR_Pos)                    /**< (TC_INTENCLR) Error Interrupt Enable Mask */
    231. 

  231. #define TC_INTENCLR_ERR(value)                (TC_INTENCLR_ERR_Msk & ((value) << TC_INTENCLR_ERR_Pos))
    232. 

  232. #define TC_INTENCLR_SYNCRDY_Pos               _U_(3)                                               /**< (TC_INTENCLR) Synchronization Ready Interrupt Enable Position */
    233. 

  233. #define TC_INTENCLR_SYNCRDY_Msk               (_U_(0x1) << TC_INTENCLR_SYNCRDY_Pos)                /**< (TC_INTENCLR) Synchronization Ready Interrupt Enable Mask */
    234. 

  234. #define TC_INTENCLR_SYNCRDY(value)            (TC_INTENCLR_SYNCRDY_Msk & ((value) << TC_INTENCLR_SYNCRDY_Pos))
    235. 

  235. #define TC_INTENCLR_MC0_Pos                   _U_(4)                                               /**< (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Position */
    236. 

  236. #define TC_INTENCLR_MC0_Msk                   (_U_(0x1) << TC_INTENCLR_MC0_Pos)                    /**< (TC_INTENCLR) Match or Capture Channel 0 Interrupt Enable Mask */
    237. 

  237. #define TC_INTENCLR_MC0(value)                (TC_INTENCLR_MC0_Msk & ((value) << TC_INTENCLR_MC0_Pos))
    238. 

  238. #define TC_INTENCLR_MC1_Pos                   _U_(5)                                               /**< (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Position */
    239. 

  239. #define TC_INTENCLR_MC1_Msk                   (_U_(0x1) << TC_INTENCLR_MC1_Pos)                    /**< (TC_INTENCLR) Match or Capture Channel 1 Interrupt Enable Mask */
    240. 

  240. #define TC_INTENCLR_MC1(value)                (TC_INTENCLR_MC1_Msk & ((value) << TC_INTENCLR_MC1_Pos))
    241. 

  241. #define TC_INTENCLR_Msk                       _U_(0x3B)                                            /**< (TC_INTENCLR) Register Mask  */
    242. 

  242. 

  243. #define TC_INTENCLR_MC_Pos                    _U_(4)                                               /**< (TC_INTENCLR Position) Match or Capture Channel x Interrupt Enable */
    244. 

  244. #define TC_INTENCLR_MC_Msk                    (_U_(0x3) << TC_INTENCLR_MC_Pos)                     /**< (TC_INTENCLR Mask) MC */
    245. 

  245. #define TC_INTENCLR_MC(value)                 (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) 
    246. 

  246. 

  247. /* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
    248. 

  248. #define TC_INTENSET_RESETVALUE                _U_(0x00)                                            /**<  (TC_INTENSET) Interrupt Enable Set  Reset Value */
    249. 

  249. 

  250. #define TC_INTENSET_OVF_Pos                   _U_(0)                                               /**< (TC_INTENSET) Overflow Interrupt Enable Position */
    251. 

  251. #define TC_INTENSET_OVF_Msk                   (_U_(0x1) << TC_INTENSET_OVF_Pos)                    /**< (TC_INTENSET) Overflow Interrupt Enable Mask */
    252. 

  252. #define TC_INTENSET_OVF(value)                (TC_INTENSET_OVF_Msk & ((value) << TC_INTENSET_OVF_Pos))
    253. 

  253. #define TC_INTENSET_ERR_Pos                   _U_(1)                                               /**< (TC_INTENSET) Error Interrupt Enable Position */
    254. 

  254. #define TC_INTENSET_ERR_Msk                   (_U_(0x1) << TC_INTENSET_ERR_Pos)                    /**< (TC_INTENSET) Error Interrupt Enable Mask */
    255. 

  255. #define TC_INTENSET_ERR(value)                (TC_INTENSET_ERR_Msk & ((value) << TC_INTENSET_ERR_Pos))
    256. 

  256. #define TC_INTENSET_SYNCRDY_Pos               _U_(3)                                               /**< (TC_INTENSET) Synchronization Ready Interrupt Enable Position */
    257. 

  257. #define TC_INTENSET_SYNCRDY_Msk               (_U_(0x1) << TC_INTENSET_SYNCRDY_Pos)                /**< (TC_INTENSET) Synchronization Ready Interrupt Enable Mask */
    258. 

  258. #define TC_INTENSET_SYNCRDY(value)            (TC_INTENSET_SYNCRDY_Msk & ((value) << TC_INTENSET_SYNCRDY_Pos))
    259. 

  259. #define TC_INTENSET_MC0_Pos                   _U_(4)                                               /**< (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable Position */
    260. 

  260. #define TC_INTENSET_MC0_Msk                   (_U_(0x1) << TC_INTENSET_MC0_Pos)                    /**< (TC_INTENSET) Match or Capture Channel 0 Interrupt Enable Mask */
    261. 

  261. #define TC_INTENSET_MC0(value)                (TC_INTENSET_MC0_Msk & ((value) << TC_INTENSET_MC0_Pos))
    262. 

  262. #define TC_INTENSET_MC1_Pos                   _U_(5)                                               /**< (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable Position */
    263. 

  263. #define TC_INTENSET_MC1_Msk                   (_U_(0x1) << TC_INTENSET_MC1_Pos)                    /**< (TC_INTENSET) Match or Capture Channel 1 Interrupt Enable Mask */
    264. 

  264. #define TC_INTENSET_MC1(value)                (TC_INTENSET_MC1_Msk & ((value) << TC_INTENSET_MC1_Pos))
    265. 

  265. #define TC_INTENSET_Msk                       _U_(0x3B)                                            /**< (TC_INTENSET) Register Mask  */
    266. 

  266. 

  267. #define TC_INTENSET_MC_Pos                    _U_(4)                                               /**< (TC_INTENSET Position) Match or Capture Channel x Interrupt Enable */
    268. 

  268. #define TC_INTENSET_MC_Msk                    (_U_(0x3) << TC_INTENSET_MC_Pos)                     /**< (TC_INTENSET Mask) MC */
    269. 

  269. #define TC_INTENSET_MC(value)                 (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)) 
    270. 

  270. 

  271. /* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
    272. 

  272. #define TC_INTFLAG_RESETVALUE                 _U_(0x00)                                            /**<  (TC_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    273. 

  273. 

  274. #define TC_INTFLAG_OVF_Pos                    _U_(0)                                               /**< (TC_INTFLAG) Overflow Position */
    275. 

  275. #define TC_INTFLAG_OVF_Msk                    (_U_(0x1) << TC_INTFLAG_OVF_Pos)                     /**< (TC_INTFLAG) Overflow Mask */
    276. 

  276. #define TC_INTFLAG_OVF(value)                 (TC_INTFLAG_OVF_Msk & ((value) << TC_INTFLAG_OVF_Pos))
    277. 

  277. #define TC_INTFLAG_ERR_Pos                    _U_(1)                                               /**< (TC_INTFLAG) Error Position */
    278. 

  278. #define TC_INTFLAG_ERR_Msk                    (_U_(0x1) << TC_INTFLAG_ERR_Pos)                     /**< (TC_INTFLAG) Error Mask */
    279. 

  279. #define TC_INTFLAG_ERR(value)                 (TC_INTFLAG_ERR_Msk & ((value) << TC_INTFLAG_ERR_Pos))
    280. 

  280. #define TC_INTFLAG_SYNCRDY_Pos                _U_(3)                                               /**< (TC_INTFLAG) Synchronization Ready Position */
    281. 

  281. #define TC_INTFLAG_SYNCRDY_Msk                (_U_(0x1) << TC_INTFLAG_SYNCRDY_Pos)                 /**< (TC_INTFLAG) Synchronization Ready Mask */
    282. 

  282. #define TC_INTFLAG_SYNCRDY(value)             (TC_INTFLAG_SYNCRDY_Msk & ((value) << TC_INTFLAG_SYNCRDY_Pos))
    283. 

  283. #define TC_INTFLAG_MC0_Pos                    _U_(4)                                               /**< (TC_INTFLAG) Match or Capture Channel 0 Position */
    284. 

  284. #define TC_INTFLAG_MC0_Msk                    (_U_(0x1) << TC_INTFLAG_MC0_Pos)                     /**< (TC_INTFLAG) Match or Capture Channel 0 Mask */
    285. 

  285. #define TC_INTFLAG_MC0(value)                 (TC_INTFLAG_MC0_Msk & ((value) << TC_INTFLAG_MC0_Pos))
    286. 

  286. #define TC_INTFLAG_MC1_Pos                    _U_(5)                                               /**< (TC_INTFLAG) Match or Capture Channel 1 Position */
    287. 

  287. #define TC_INTFLAG_MC1_Msk                    (_U_(0x1) << TC_INTFLAG_MC1_Pos)                     /**< (TC_INTFLAG) Match or Capture Channel 1 Mask */
    288. 

  288. #define TC_INTFLAG_MC1(value)                 (TC_INTFLAG_MC1_Msk & ((value) << TC_INTFLAG_MC1_Pos))
    289. 

  289. #define TC_INTFLAG_Msk                        _U_(0x3B)                                            /**< (TC_INTFLAG) Register Mask  */
    290. 

  290. 

  291. #define TC_INTFLAG_MC_Pos                     _U_(4)                                               /**< (TC_INTFLAG Position) Match or Capture Channel x */
    292. 

  292. #define TC_INTFLAG_MC_Msk                     (_U_(0x3) << TC_INTFLAG_MC_Pos)                      /**< (TC_INTFLAG Mask) MC */
    293. 

  293. #define TC_INTFLAG_MC(value)                  (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)) 
    294. 

  294. 

  295. /* -------- TC_STATUS : (TC Offset: 0x0F) ( R/ 8) Status -------- */
    296. 

  296. #define TC_STATUS_RESETVALUE                  _U_(0x08)                                            /**<  (TC_STATUS) Status  Reset Value */
    297. 

  297. 

  298. #define TC_STATUS_STOP_Pos                    _U_(3)                                               /**< (TC_STATUS) Stop Position */
    299. 

  299. #define TC_STATUS_STOP_Msk                    (_U_(0x1) << TC_STATUS_STOP_Pos)                     /**< (TC_STATUS) Stop Mask */
    300. 

  300. #define TC_STATUS_STOP(value)                 (TC_STATUS_STOP_Msk & ((value) << TC_STATUS_STOP_Pos))
    301. 

  301. #define TC_STATUS_SLAVE_Pos                   _U_(4)                                               /**< (TC_STATUS) Slave Position */
    302. 

  302. #define TC_STATUS_SLAVE_Msk                   (_U_(0x1) << TC_STATUS_SLAVE_Pos)                    /**< (TC_STATUS) Slave Mask */
    303. 

  303. #define TC_STATUS_SLAVE(value)                (TC_STATUS_SLAVE_Msk & ((value) << TC_STATUS_SLAVE_Pos))
    304. 

  304. #define TC_STATUS_SYNCBUSY_Pos                _U_(7)                                               /**< (TC_STATUS) Synchronization Busy Position */
    305. 

  305. #define TC_STATUS_SYNCBUSY_Msk                (_U_(0x1) << TC_STATUS_SYNCBUSY_Pos)                 /**< (TC_STATUS) Synchronization Busy Mask */
    306. 

  306. #define TC_STATUS_SYNCBUSY(value)             (TC_STATUS_SYNCBUSY_Msk & ((value) << TC_STATUS_SYNCBUSY_Pos))
    307. 

  307. #define TC_STATUS_Msk                         _U_(0x98)                                            /**< (TC_STATUS) Register Mask  */
    308. 

  308. 

  309. 

  310. /* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 Counter Value -------- */
    311. 

  311. #define TC_COUNT8_COUNT_RESETVALUE            _U_(0x00)                                            /**<  (TC_COUNT8_COUNT) COUNT8 Counter Value  Reset Value */
    312. 

  312. 

  313. #define TC_COUNT8_COUNT_COUNT_Pos             _U_(0)                                               /**< (TC_COUNT8_COUNT) Counter Value Position */
    314. 

  314. #define TC_COUNT8_COUNT_COUNT_Msk             (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)             /**< (TC_COUNT8_COUNT) Counter Value Mask */
    315. 

  315. #define TC_COUNT8_COUNT_COUNT(value)          (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
    316. 

  316. #define TC_COUNT8_COUNT_Msk                   _U_(0xFF)                                            /**< (TC_COUNT8_COUNT) Register Mask  */
    317. 

  317. 

  318. 

  319. /* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 Counter Value -------- */
    320. 

  320. #define TC_COUNT16_COUNT_RESETVALUE           _U_(0x00)                                            /**<  (TC_COUNT16_COUNT) COUNT16 Counter Value  Reset Value */
    321. 

  321. 

  322. #define TC_COUNT16_COUNT_COUNT_Pos            _U_(0)                                               /**< (TC_COUNT16_COUNT) Count Value Position */
    323. 

  323. #define TC_COUNT16_COUNT_COUNT_Msk            (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)          /**< (TC_COUNT16_COUNT) Count Value Mask */
    324. 

  324. #define TC_COUNT16_COUNT_COUNT(value)         (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
    325. 

  325. #define TC_COUNT16_COUNT_Msk                  _U_(0xFFFF)                                          /**< (TC_COUNT16_COUNT) Register Mask  */
    326. 

  326. 

  327. 

  328. /* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 Counter Value -------- */
    329. 

  329. #define TC_COUNT32_COUNT_RESETVALUE           _U_(0x00)                                            /**<  (TC_COUNT32_COUNT) COUNT32 Counter Value  Reset Value */
    330. 

  330. 

  331. #define TC_COUNT32_COUNT_COUNT_Pos            _U_(0)                                               /**< (TC_COUNT32_COUNT) Count Value Position */
    332. 

  332. #define TC_COUNT32_COUNT_COUNT_Msk            (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)      /**< (TC_COUNT32_COUNT) Count Value Mask */
    333. 

  333. #define TC_COUNT32_COUNT_COUNT(value)         (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
    334. 

  334. #define TC_COUNT32_COUNT_Msk                  _U_(0xFFFFFFFF)                                      /**< (TC_COUNT32_COUNT) Register Mask  */
    335. 

  335. 

  336. 

  337. /* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 Period Value -------- */
    338. 

  338. #define TC_COUNT8_PER_RESETVALUE              _U_(0xFF)                                            /**<  (TC_COUNT8_PER) COUNT8 Period Value  Reset Value */
    339. 

  339. 

  340. #define TC_COUNT8_PER_PER_Pos                 _U_(0)                                               /**< (TC_COUNT8_PER) Period Value Position */
    341. 

  341. #define TC_COUNT8_PER_PER_Msk                 (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)                 /**< (TC_COUNT8_PER) Period Value Mask */
    342. 

  342. #define TC_COUNT8_PER_PER(value)              (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
    343. 

  343. #define TC_COUNT8_PER_Msk                     _U_(0xFF)                                            /**< (TC_COUNT8_PER) Register Mask  */
    344. 

  344. 

  345. 

  346. /* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 Compare/Capture -------- */
    347. 

  347. #define TC_COUNT8_CC_RESETVALUE               _U_(0x00)                                            /**<  (TC_COUNT8_CC) COUNT8 Compare/Capture  Reset Value */
    348. 

  348. 

  349. #define TC_COUNT8_CC_CC_Pos                   _U_(0)                                               /**< (TC_COUNT8_CC) Compare/Capture Value Position */
    350. 

  350. #define TC_COUNT8_CC_CC_Msk                   (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)                   /**< (TC_COUNT8_CC) Compare/Capture Value Mask */
    351. 

  351. #define TC_COUNT8_CC_CC(value)                (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
    352. 

  352. #define TC_COUNT8_CC_Msk                      _U_(0xFF)                                            /**< (TC_COUNT8_CC) Register Mask  */
    353. 

  353. 

  354. 

  355. /* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 Compare/Capture -------- */
    356. 

  356. #define TC_COUNT16_CC_RESETVALUE              _U_(0x00)                                            /**<  (TC_COUNT16_CC) COUNT16 Compare/Capture  Reset Value */
    357. 

  357. 

  358. #define TC_COUNT16_CC_CC_Pos                  _U_(0)                                               /**< (TC_COUNT16_CC) Compare/Capture Value Position */
    359. 

  359. #define TC_COUNT16_CC_CC_Msk                  (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)                /**< (TC_COUNT16_CC) Compare/Capture Value Mask */
    360. 

  360. #define TC_COUNT16_CC_CC(value)               (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
    361. 

  361. #define TC_COUNT16_CC_Msk                     _U_(0xFFFF)                                          /**< (TC_COUNT16_CC) Register Mask  */
    362. 

  362. 

  363. 

  364. /* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 Compare/Capture -------- */
    365. 

  365. #define TC_COUNT32_CC_RESETVALUE              _U_(0x00)                                            /**<  (TC_COUNT32_CC) COUNT32 Compare/Capture  Reset Value */
    366. 

  366. 

  367. #define TC_COUNT32_CC_CC_Pos                  _U_(0)                                               /**< (TC_COUNT32_CC) Compare/Capture Value Position */
    368. 

  368. #define TC_COUNT32_CC_CC_Msk                  (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)            /**< (TC_COUNT32_CC) Compare/Capture Value Mask */
    369. 

  369. #define TC_COUNT32_CC_CC(value)               (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
    370. 

  370. #define TC_COUNT32_CC_Msk                     _U_(0xFFFFFFFF)                                      /**< (TC_COUNT32_CC) Register Mask  */
    371. 

  371. 

  372. 

  373. /** \brief TC register offsets definitions */
    374. 

  374. #define TC_CTRLA_REG_OFST              (0x00)              /**< (TC_CTRLA) Control A Offset */
    375. 

  375. #define TC_READREQ_REG_OFST            (0x02)              /**< (TC_READREQ) Read Request Offset */
    376. 

  376. #define TC_CTRLBCLR_REG_OFST           (0x04)              /**< (TC_CTRLBCLR) Control B Clear Offset */
    377. 

  377. #define TC_CTRLBSET_REG_OFST           (0x05)              /**< (TC_CTRLBSET) Control B Set Offset */
    378. 

  378. #define TC_CTRLC_REG_OFST              (0x06)              /**< (TC_CTRLC) Control C Offset */
    379. 

  379. #define TC_DBGCTRL_REG_OFST            (0x08)              /**< (TC_DBGCTRL) Debug Control Offset */
    380. 

  380. #define TC_EVCTRL_REG_OFST             (0x0A)              /**< (TC_EVCTRL) Event Control Offset */
    381. 

  381. #define TC_INTENCLR_REG_OFST           (0x0C)              /**< (TC_INTENCLR) Interrupt Enable Clear Offset */
    382. 

  382. #define TC_INTENSET_REG_OFST           (0x0D)              /**< (TC_INTENSET) Interrupt Enable Set Offset */
    383. 

  383. #define TC_INTFLAG_REG_OFST            (0x0E)              /**< (TC_INTFLAG) Interrupt Flag Status and Clear Offset */
    384. 

  384. #define TC_STATUS_REG_OFST             (0x0F)              /**< (TC_STATUS) Status Offset */
    385. 

  385. #define TC_COUNT8_COUNT_REG_OFST       (0x10)              /**< (TC_COUNT8_COUNT) COUNT8 Counter Value Offset */
    386. 

  386. #define TC_COUNT16_COUNT_REG_OFST      (0x10)              /**< (TC_COUNT16_COUNT) COUNT16 Counter Value Offset */
    387. 

  387. #define TC_COUNT32_COUNT_REG_OFST      (0x10)              /**< (TC_COUNT32_COUNT) COUNT32 Counter Value Offset */
    388. 

  388. #define TC_COUNT8_PER_REG_OFST         (0x14)              /**< (TC_COUNT8_PER) COUNT8 Period Value Offset */
    389. 

  389. #define TC_COUNT8_CC_REG_OFST          (0x18)              /**< (TC_COUNT8_CC) COUNT8 Compare/Capture Offset */
    390. 

  390. #define TC_COUNT8_CC0_REG_OFST         (0x18)              /**< (TC_COUNT8_CC0) COUNT8 Compare/Capture Offset */
    391. 

  391. #define TC_COUNT8_CC1_REG_OFST         (0x19)              /**< (TC_COUNT8_CC1) COUNT8 Compare/Capture Offset */
    392. 

  392. #define TC_COUNT16_CC_REG_OFST         (0x18)              /**< (TC_COUNT16_CC) COUNT16 Compare/Capture Offset */
    393. 

  393. #define TC_COUNT16_CC0_REG_OFST        (0x18)              /**< (TC_COUNT16_CC0) COUNT16 Compare/Capture Offset */
    394. 

  394. #define TC_COUNT16_CC1_REG_OFST        (0x1A)              /**< (TC_COUNT16_CC1) COUNT16 Compare/Capture Offset */
    395. 

  395. #define TC_COUNT32_CC_REG_OFST         (0x18)              /**< (TC_COUNT32_CC) COUNT32 Compare/Capture Offset */
    396. 

  396. #define TC_COUNT32_CC0_REG_OFST        (0x18)              /**< (TC_COUNT32_CC0) COUNT32 Compare/Capture Offset */
    397. 

  397. #define TC_COUNT32_CC1_REG_OFST        (0x1C)              /**< (TC_COUNT32_CC1) COUNT32 Compare/Capture Offset */
    398. 

  398. 

  399. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    400. 

  400. /** \brief TC register API structure */
    401. 

  401. typedef struct
    402. 

  402. {  /* Basic Timer Counter */
    403. 

  403.   __IO  uint16_t                       TC_CTRLA;           /**< Offset: 0x00 (R/W  16) Control A */
    404. 

  404.   __IO  uint16_t                       TC_READREQ;         /**< Offset: 0x02 (R/W  16) Read Request */
    405. 

  405.   __IO  uint8_t                        TC_CTRLBCLR;        /**< Offset: 0x04 (R/W  8) Control B Clear */
    406. 

  406.   __IO  uint8_t                        TC_CTRLBSET;        /**< Offset: 0x05 (R/W  8) Control B Set */
    407. 

  407.   __IO  uint8_t                        TC_CTRLC;           /**< Offset: 0x06 (R/W  8) Control C */
    408. 

  408.   __I   uint8_t                        Reserved1[0x01];
    409. 

  409.   __IO  uint8_t                        TC_DBGCTRL;         /**< Offset: 0x08 (R/W  8) Debug Control */
    410. 

  410.   __I   uint8_t                        Reserved2[0x01];
    411. 

  411.   __IO  uint16_t                       TC_EVCTRL;          /**< Offset: 0x0A (R/W  16) Event Control */
    412. 

  412.   __IO  uint8_t                        TC_INTENCLR;        /**< Offset: 0x0C (R/W  8) Interrupt Enable Clear */
    413. 

  413.   __IO  uint8_t                        TC_INTENSET;        /**< Offset: 0x0D (R/W  8) Interrupt Enable Set */
    414. 

  414.   __IO  uint8_t                        TC_INTFLAG;         /**< Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
    415. 

  415.   __I   uint8_t                        TC_STATUS;          /**< Offset: 0x0F (R/   8) Status */
    416. 

  416.   __IO  uint8_t                        TC_COUNT;           /**< Offset: 0x10 (R/W  8) COUNT8 Counter Value */
    417. 

  417.   __I   uint8_t                        Reserved3[0x03];
    418. 

  418.   __IO  uint8_t                        TC_PER;             /**< Offset: 0x14 (R/W  8) COUNT8 Period Value */
    419. 

  419.   __I   uint8_t                        Reserved4[0x03];
    420. 

  420.   __IO  uint8_t                        TC_CC[2];           /**< Offset: 0x18 (R/W  8) COUNT8 Compare/Capture */
    421. 

  421. } tc_count8_registers_t;
    422. 

  422. 

  423. /** \brief TC register API structure */
    424. 

  424. typedef struct
    425. 

  425. {  /* Basic Timer Counter */
    426. 

  426.   __IO  uint16_t                       TC_CTRLA;           /**< Offset: 0x00 (R/W  16) Control A */
    427. 

  427.   __IO  uint16_t                       TC_READREQ;         /**< Offset: 0x02 (R/W  16) Read Request */
    428. 

  428.   __IO  uint8_t                        TC_CTRLBCLR;        /**< Offset: 0x04 (R/W  8) Control B Clear */
    429. 

  429.   __IO  uint8_t                        TC_CTRLBSET;        /**< Offset: 0x05 (R/W  8) Control B Set */
    430. 

  430.   __IO  uint8_t                        TC_CTRLC;           /**< Offset: 0x06 (R/W  8) Control C */
    431. 

  431.   __I   uint8_t                        Reserved1[0x01];
    432. 

  432.   __IO  uint8_t                        TC_DBGCTRL;         /**< Offset: 0x08 (R/W  8) Debug Control */
    433. 

  433.   __I   uint8_t                        Reserved2[0x01];
    434. 

  434.   __IO  uint16_t                       TC_EVCTRL;          /**< Offset: 0x0A (R/W  16) Event Control */
    435. 

  435.   __IO  uint8_t                        TC_INTENCLR;        /**< Offset: 0x0C (R/W  8) Interrupt Enable Clear */
    436. 

  436.   __IO  uint8_t                        TC_INTENSET;        /**< Offset: 0x0D (R/W  8) Interrupt Enable Set */
    437. 

  437.   __IO  uint8_t                        TC_INTFLAG;         /**< Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
    438. 

  438.   __I   uint8_t                        TC_STATUS;          /**< Offset: 0x0F (R/   8) Status */
    439. 

  439.   __IO  uint16_t                       TC_COUNT;           /**< Offset: 0x10 (R/W  16) COUNT16 Counter Value */
    440. 

  440.   __I   uint8_t                        Reserved3[0x06];
    441. 

  441.   __IO  uint16_t                       TC_CC[2];           /**< Offset: 0x18 (R/W  16) COUNT16 Compare/Capture */
    442. 

  442. } tc_count16_registers_t;
    443. 

  443. 

  444. /** \brief TC register API structure */
    445. 

  445. typedef struct
    446. 

  446. {  /* Basic Timer Counter */
    447. 

  447.   __IO  uint16_t                       TC_CTRLA;           /**< Offset: 0x00 (R/W  16) Control A */
    448. 

  448.   __IO  uint16_t                       TC_READREQ;         /**< Offset: 0x02 (R/W  16) Read Request */
    449. 

  449.   __IO  uint8_t                        TC_CTRLBCLR;        /**< Offset: 0x04 (R/W  8) Control B Clear */
    450. 

  450.   __IO  uint8_t                        TC_CTRLBSET;        /**< Offset: 0x05 (R/W  8) Control B Set */
    451. 

  451.   __IO  uint8_t                        TC_CTRLC;           /**< Offset: 0x06 (R/W  8) Control C */
    452. 

  452.   __I   uint8_t                        Reserved1[0x01];
    453. 

  453.   __IO  uint8_t                        TC_DBGCTRL;         /**< Offset: 0x08 (R/W  8) Debug Control */
    454. 

  454.   __I   uint8_t                        Reserved2[0x01];
    455. 

  455.   __IO  uint16_t                       TC_EVCTRL;          /**< Offset: 0x0A (R/W  16) Event Control */
    456. 

  456.   __IO  uint8_t                        TC_INTENCLR;        /**< Offset: 0x0C (R/W  8) Interrupt Enable Clear */
    457. 

  457.   __IO  uint8_t                        TC_INTENSET;        /**< Offset: 0x0D (R/W  8) Interrupt Enable Set */
    458. 

  458.   __IO  uint8_t                        TC_INTFLAG;         /**< Offset: 0x0E (R/W  8) Interrupt Flag Status and Clear */
    459. 

  459.   __I   uint8_t                        TC_STATUS;          /**< Offset: 0x0F (R/   8) Status */
    460. 

  460.   __IO  uint32_t                       TC_COUNT;           /**< Offset: 0x10 (R/W  32) COUNT32 Counter Value */
    461. 

  461.   __I   uint8_t                        Reserved3[0x04];
    462. 

  462.   __IO  uint32_t                       TC_CC[2];           /**< Offset: 0x18 (R/W  32) COUNT32 Compare/Capture */
    463. 

  463. } tc_count32_registers_t;
    464. 

  464. 

  465. /** \brief TC hardware registers */
    466. 

  466. typedef union
    467. 

  467. {  /* Basic Timer Counter */
    468. 

  468.        tc_count8_registers_t          COUNT8;         /**< 8-bit Counter Mode */
    469. 

  469.        tc_count16_registers_t         COUNT16;        /**< 16-bit Counter Mode */
    470. 

  470.        tc_count32_registers_t         COUNT32;        /**< 32-bit Counter Mode */
    471. 

  471. } tc_registers_t;
    472. 

  472. 

  473. 

  474. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    475. 

  475. #endif /* _SAMD21_TC_COMPONENT_H_ */
    476.