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wdt.h

wdt.h 21 KB
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  1. /**
    2. 

  2.  * \brief Component description for WDT
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
    5. 

  5.  *
    6. 

  6.  * Subject to your compliance with these terms, you may use Microchip software and any derivatives
    7. 

  7.  * exclusively with Microchip products. It is your responsibility to comply with third party license
    8. 

  8.  * terms applicable to your use of third party software (including open source software) that may
    9. 

  9.  * accompany Microchip software.
    10. 

  10.  *
    11. 

  11.  * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
    12. 

  12.  * APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
    13. 

  13.  * FITNESS FOR A PARTICULAR PURPOSE.
    14. 

  14.  *
    15. 

  15.  * IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
    16. 

  16.  * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
    17. 

  17.  * MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
    18. 

  18.  * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
    19. 

  19.  * EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
    20. 

  20.  *
    21. 

  21.  */
    22. 

  22. 

  23. /* file generated from device description version 2019-11-25T06:52:33Z */
    24. 

  24. #ifndef _SAMD21_WDT_COMPONENT_H_
    25. 

  25. #define _SAMD21_WDT_COMPONENT_H_
    26. 

  26. 

  27. /* ************************************************************************** */
    28. 

  28. /*   SOFTWARE API DEFINITION FOR WDT                                          */
    29. 

  29. /* ************************************************************************** */
    30. 

  30. 

  31. /* -------- WDT_CTRL : (WDT Offset: 0x00) (R/W 8) Control -------- */
    32. 

  32. #define WDT_CTRL_RESETVALUE                   _U_(0x00)                                            /**<  (WDT_CTRL) Control  Reset Value */
    33. 

  33. 

  34. #define WDT_CTRL_ENABLE_Pos                   _U_(1)                                               /**< (WDT_CTRL) Enable Position */
    35. 

  35. #define WDT_CTRL_ENABLE_Msk                   (_U_(0x1) << WDT_CTRL_ENABLE_Pos)                    /**< (WDT_CTRL) Enable Mask */
    36. 

  36. #define WDT_CTRL_ENABLE(value)                (WDT_CTRL_ENABLE_Msk & ((value) << WDT_CTRL_ENABLE_Pos))
    37. 

  37. #define WDT_CTRL_WEN_Pos                      _U_(2)                                               /**< (WDT_CTRL) Watchdog Timer Window Mode Enable Position */
    38. 

  38. #define WDT_CTRL_WEN_Msk                      (_U_(0x1) << WDT_CTRL_WEN_Pos)                       /**< (WDT_CTRL) Watchdog Timer Window Mode Enable Mask */
    39. 

  39. #define WDT_CTRL_WEN(value)                   (WDT_CTRL_WEN_Msk & ((value) << WDT_CTRL_WEN_Pos))  
    40. 

  40. #define WDT_CTRL_ALWAYSON_Pos                 _U_(7)                                               /**< (WDT_CTRL) Always-On Position */
    41. 

  41. #define WDT_CTRL_ALWAYSON_Msk                 (_U_(0x1) << WDT_CTRL_ALWAYSON_Pos)                  /**< (WDT_CTRL) Always-On Mask */
    42. 

  42. #define WDT_CTRL_ALWAYSON(value)              (WDT_CTRL_ALWAYSON_Msk & ((value) << WDT_CTRL_ALWAYSON_Pos))
    43. 

  43. #define WDT_CTRL_Msk                          _U_(0x86)                                            /**< (WDT_CTRL) Register Mask  */
    44. 

  44. 

  45. 

  46. /* -------- WDT_CONFIG : (WDT Offset: 0x01) (R/W 8) Configuration -------- */
    47. 

  47. #define WDT_CONFIG_RESETVALUE                 _U_(0xBB)                                            /**<  (WDT_CONFIG) Configuration  Reset Value */
    48. 

  48. 

  49. #define WDT_CONFIG_PER_Pos                    _U_(0)                                               /**< (WDT_CONFIG) Time-Out Period Position */
    50. 

  50. #define WDT_CONFIG_PER_Msk                    (_U_(0xF) << WDT_CONFIG_PER_Pos)                     /**< (WDT_CONFIG) Time-Out Period Mask */
    51. 

  51. #define WDT_CONFIG_PER(value)                 (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
    52. 

  52. #define   WDT_CONFIG_PER_8_Val                _U_(0x0)                                             /**< (WDT_CONFIG) 8 clock cycles  */
    53. 

  53. #define   WDT_CONFIG_PER_16_Val               _U_(0x1)                                             /**< (WDT_CONFIG) 16 clock cycles  */
    54. 

  54. #define   WDT_CONFIG_PER_32_Val               _U_(0x2)                                             /**< (WDT_CONFIG) 32 clock cycles  */
    55. 

  55. #define   WDT_CONFIG_PER_64_Val               _U_(0x3)                                             /**< (WDT_CONFIG) 64 clock cycles  */
    56. 

  56. #define   WDT_CONFIG_PER_128_Val              _U_(0x4)                                             /**< (WDT_CONFIG) 128 clock cycles  */
    57. 

  57. #define   WDT_CONFIG_PER_256_Val              _U_(0x5)                                             /**< (WDT_CONFIG) 256 clock cycles  */
    58. 

  58. #define   WDT_CONFIG_PER_512_Val              _U_(0x6)                                             /**< (WDT_CONFIG) 512 clock cycles  */
    59. 

  59. #define   WDT_CONFIG_PER_1K_Val               _U_(0x7)                                             /**< (WDT_CONFIG) 1024 clock cycles  */
    60. 

  60. #define   WDT_CONFIG_PER_2K_Val               _U_(0x8)                                             /**< (WDT_CONFIG) 2048 clock cycles  */
    61. 

  61. #define   WDT_CONFIG_PER_4K_Val               _U_(0x9)                                             /**< (WDT_CONFIG) 4096 clock cycles  */
    62. 

  62. #define   WDT_CONFIG_PER_8K_Val               _U_(0xA)                                             /**< (WDT_CONFIG) 8192 clock cycles  */
    63. 

  63. #define   WDT_CONFIG_PER_16K_Val              _U_(0xB)                                             /**< (WDT_CONFIG) 16384 clock cycles  */
    64. 

  64. #define WDT_CONFIG_PER_8                      (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)         /**< (WDT_CONFIG) 8 clock cycles Position  */
    65. 

  65. #define WDT_CONFIG_PER_16                     (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 16 clock cycles Position  */
    66. 

  66. #define WDT_CONFIG_PER_32                     (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 32 clock cycles Position  */
    67. 

  67. #define WDT_CONFIG_PER_64                     (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 64 clock cycles Position  */
    68. 

  68. #define WDT_CONFIG_PER_128                    (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)       /**< (WDT_CONFIG) 128 clock cycles Position  */
    69. 

  69. #define WDT_CONFIG_PER_256                    (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)       /**< (WDT_CONFIG) 256 clock cycles Position  */
    70. 

  70. #define WDT_CONFIG_PER_512                    (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)       /**< (WDT_CONFIG) 512 clock cycles Position  */
    71. 

  71. #define WDT_CONFIG_PER_1K                     (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 1024 clock cycles Position  */
    72. 

  72. #define WDT_CONFIG_PER_2K                     (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 2048 clock cycles Position  */
    73. 

  73. #define WDT_CONFIG_PER_4K                     (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 4096 clock cycles Position  */
    74. 

  74. #define WDT_CONFIG_PER_8K                     (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)        /**< (WDT_CONFIG) 8192 clock cycles Position  */
    75. 

  75. #define WDT_CONFIG_PER_16K                    (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)       /**< (WDT_CONFIG) 16384 clock cycles Position  */
    76. 

  76. #define WDT_CONFIG_WINDOW_Pos                 _U_(4)                                               /**< (WDT_CONFIG) Window Mode Time-Out Period Position */
    77. 

  77. #define WDT_CONFIG_WINDOW_Msk                 (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)                  /**< (WDT_CONFIG) Window Mode Time-Out Period Mask */
    78. 

  78. #define WDT_CONFIG_WINDOW(value)              (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
    79. 

  79. #define   WDT_CONFIG_WINDOW_8_Val             _U_(0x0)                                             /**< (WDT_CONFIG) 8 clock cycles  */
    80. 

  80. #define   WDT_CONFIG_WINDOW_16_Val            _U_(0x1)                                             /**< (WDT_CONFIG) 16 clock cycles  */
    81. 

  81. #define   WDT_CONFIG_WINDOW_32_Val            _U_(0x2)                                             /**< (WDT_CONFIG) 32 clock cycles  */
    82. 

  82. #define   WDT_CONFIG_WINDOW_64_Val            _U_(0x3)                                             /**< (WDT_CONFIG) 64 clock cycles  */
    83. 

  83. #define   WDT_CONFIG_WINDOW_128_Val           _U_(0x4)                                             /**< (WDT_CONFIG) 128 clock cycles  */
    84. 

  84. #define   WDT_CONFIG_WINDOW_256_Val           _U_(0x5)                                             /**< (WDT_CONFIG) 256 clock cycles  */
    85. 

  85. #define   WDT_CONFIG_WINDOW_512_Val           _U_(0x6)                                             /**< (WDT_CONFIG) 512 clock cycles  */
    86. 

  86. #define   WDT_CONFIG_WINDOW_1K_Val            _U_(0x7)                                             /**< (WDT_CONFIG) 1024 clock cycles  */
    87. 

  87. #define   WDT_CONFIG_WINDOW_2K_Val            _U_(0x8)                                             /**< (WDT_CONFIG) 2048 clock cycles  */
    88. 

  88. #define   WDT_CONFIG_WINDOW_4K_Val            _U_(0x9)                                             /**< (WDT_CONFIG) 4096 clock cycles  */
    89. 

  89. #define   WDT_CONFIG_WINDOW_8K_Val            _U_(0xA)                                             /**< (WDT_CONFIG) 8192 clock cycles  */
    90. 

  90. #define   WDT_CONFIG_WINDOW_16K_Val           _U_(0xB)                                             /**< (WDT_CONFIG) 16384 clock cycles  */
    91. 

  91. #define WDT_CONFIG_WINDOW_8                   (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)   /**< (WDT_CONFIG) 8 clock cycles Position  */
    92. 

  92. #define WDT_CONFIG_WINDOW_16                  (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 16 clock cycles Position  */
    93. 

  93. #define WDT_CONFIG_WINDOW_32                  (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 32 clock cycles Position  */
    94. 

  94. #define WDT_CONFIG_WINDOW_64                  (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 64 clock cycles Position  */
    95. 

  95. #define WDT_CONFIG_WINDOW_128                 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 128 clock cycles Position  */
    96. 

  96. #define WDT_CONFIG_WINDOW_256                 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 256 clock cycles Position  */
    97. 

  97. #define WDT_CONFIG_WINDOW_512                 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 512 clock cycles Position  */
    98. 

  98. #define WDT_CONFIG_WINDOW_1K                  (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 1024 clock cycles Position  */
    99. 

  99. #define WDT_CONFIG_WINDOW_2K                  (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 2048 clock cycles Position  */
    100. 

  100. #define WDT_CONFIG_WINDOW_4K                  (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 4096 clock cycles Position  */
    101. 

  101. #define WDT_CONFIG_WINDOW_8K                  (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)  /**< (WDT_CONFIG) 8192 clock cycles Position  */
    102. 

  102. #define WDT_CONFIG_WINDOW_16K                 (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos) /**< (WDT_CONFIG) 16384 clock cycles Position  */
    103. 

  103. #define WDT_CONFIG_Msk                        _U_(0xFF)                                            /**< (WDT_CONFIG) Register Mask  */
    104. 

  104. 

  105. 

  106. /* -------- WDT_EWCTRL : (WDT Offset: 0x02) (R/W 8) Early Warning Interrupt Control -------- */
    107. 

  107. #define WDT_EWCTRL_RESETVALUE                 _U_(0x0B)                                            /**<  (WDT_EWCTRL) Early Warning Interrupt Control  Reset Value */
    108. 

  108. 

  109. #define WDT_EWCTRL_EWOFFSET_Pos               _U_(0)                                               /**< (WDT_EWCTRL) Early Warning Interrupt Time Offset Position */
    110. 

  110. #define WDT_EWCTRL_EWOFFSET_Msk               (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)                /**< (WDT_EWCTRL) Early Warning Interrupt Time Offset Mask */
    111. 

  111. #define WDT_EWCTRL_EWOFFSET(value)            (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
    112. 

  112. #define   WDT_EWCTRL_EWOFFSET_8_Val           _U_(0x0)                                             /**< (WDT_EWCTRL) 8 clock cycles  */
    113. 

  113. #define   WDT_EWCTRL_EWOFFSET_16_Val          _U_(0x1)                                             /**< (WDT_EWCTRL) 16 clock cycles  */
    114. 

  114. #define   WDT_EWCTRL_EWOFFSET_32_Val          _U_(0x2)                                             /**< (WDT_EWCTRL) 32 clock cycles  */
    115. 

  115. #define   WDT_EWCTRL_EWOFFSET_64_Val          _U_(0x3)                                             /**< (WDT_EWCTRL) 64 clock cycles  */
    116. 

  116. #define   WDT_EWCTRL_EWOFFSET_128_Val         _U_(0x4)                                             /**< (WDT_EWCTRL) 128 clock cycles  */
    117. 

  117. #define   WDT_EWCTRL_EWOFFSET_256_Val         _U_(0x5)                                             /**< (WDT_EWCTRL) 256 clock cycles  */
    118. 

  118. #define   WDT_EWCTRL_EWOFFSET_512_Val         _U_(0x6)                                             /**< (WDT_EWCTRL) 512 clock cycles  */
    119. 

  119. #define   WDT_EWCTRL_EWOFFSET_1K_Val          _U_(0x7)                                             /**< (WDT_EWCTRL) 1024 clock cycles  */
    120. 

  120. #define   WDT_EWCTRL_EWOFFSET_2K_Val          _U_(0x8)                                             /**< (WDT_EWCTRL) 2048 clock cycles  */
    121. 

  121. #define   WDT_EWCTRL_EWOFFSET_4K_Val          _U_(0x9)                                             /**< (WDT_EWCTRL) 4096 clock cycles  */
    122. 

  122. #define   WDT_EWCTRL_EWOFFSET_8K_Val          _U_(0xA)                                             /**< (WDT_EWCTRL) 8192 clock cycles  */
    123. 

  123. #define   WDT_EWCTRL_EWOFFSET_16K_Val         _U_(0xB)                                             /**< (WDT_EWCTRL) 16384 clock cycles  */
    124. 

  124. #define WDT_EWCTRL_EWOFFSET_8                 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 8 clock cycles Position  */
    125. 

  125. #define WDT_EWCTRL_EWOFFSET_16                (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 16 clock cycles Position  */
    126. 

  126. #define WDT_EWCTRL_EWOFFSET_32                (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 32 clock cycles Position  */
    127. 

  127. #define WDT_EWCTRL_EWOFFSET_64                (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 64 clock cycles Position  */
    128. 

  128. #define WDT_EWCTRL_EWOFFSET_128               (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 128 clock cycles Position  */
    129. 

  129. #define WDT_EWCTRL_EWOFFSET_256               (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 256 clock cycles Position  */
    130. 

  130. #define WDT_EWCTRL_EWOFFSET_512               (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 512 clock cycles Position  */
    131. 

  131. #define WDT_EWCTRL_EWOFFSET_1K                (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 1024 clock cycles Position  */
    132. 

  132. #define WDT_EWCTRL_EWOFFSET_2K                (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 2048 clock cycles Position  */
    133. 

  133. #define WDT_EWCTRL_EWOFFSET_4K                (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 4096 clock cycles Position  */
    134. 

  134. #define WDT_EWCTRL_EWOFFSET_8K                (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 8192 clock cycles Position  */
    135. 

  135. #define WDT_EWCTRL_EWOFFSET_16K               (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos) /**< (WDT_EWCTRL) 16384 clock cycles Position  */
    136. 

  136. #define WDT_EWCTRL_Msk                        _U_(0x0F)                                            /**< (WDT_EWCTRL) Register Mask  */
    137. 

  137. 

  138. 

  139. /* -------- WDT_INTENCLR : (WDT Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
    140. 

  140. #define WDT_INTENCLR_RESETVALUE               _U_(0x00)                                            /**<  (WDT_INTENCLR) Interrupt Enable Clear  Reset Value */
    141. 

  141. 

  142. #define WDT_INTENCLR_EW_Pos                   _U_(0)                                               /**< (WDT_INTENCLR) Early Warning Interrupt Enable Position */
    143. 

  143. #define WDT_INTENCLR_EW_Msk                   (_U_(0x1) << WDT_INTENCLR_EW_Pos)                    /**< (WDT_INTENCLR) Early Warning Interrupt Enable Mask */
    144. 

  144. #define WDT_INTENCLR_EW(value)                (WDT_INTENCLR_EW_Msk & ((value) << WDT_INTENCLR_EW_Pos))
    145. 

  145. #define WDT_INTENCLR_Msk                      _U_(0x01)                                            /**< (WDT_INTENCLR) Register Mask  */
    146. 

  146. 

  147. 

  148. /* -------- WDT_INTENSET : (WDT Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
    149. 

  149. #define WDT_INTENSET_RESETVALUE               _U_(0x00)                                            /**<  (WDT_INTENSET) Interrupt Enable Set  Reset Value */
    150. 

  150. 

  151. #define WDT_INTENSET_EW_Pos                   _U_(0)                                               /**< (WDT_INTENSET) Early Warning Interrupt Enable Position */
    152. 

  152. #define WDT_INTENSET_EW_Msk                   (_U_(0x1) << WDT_INTENSET_EW_Pos)                    /**< (WDT_INTENSET) Early Warning Interrupt Enable Mask */
    153. 

  153. #define WDT_INTENSET_EW(value)                (WDT_INTENSET_EW_Msk & ((value) << WDT_INTENSET_EW_Pos))
    154. 

  154. #define WDT_INTENSET_Msk                      _U_(0x01)                                            /**< (WDT_INTENSET) Register Mask  */
    155. 

  155. 

  156. 

  157. /* -------- WDT_INTFLAG : (WDT Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
    158. 

  158. #define WDT_INTFLAG_RESETVALUE                _U_(0x00)                                            /**<  (WDT_INTFLAG) Interrupt Flag Status and Clear  Reset Value */
    159. 

  159. 

  160. #define WDT_INTFLAG_EW_Pos                    _U_(0)                                               /**< (WDT_INTFLAG) Early Warning Position */
    161. 

  161. #define WDT_INTFLAG_EW_Msk                    (_U_(0x1) << WDT_INTFLAG_EW_Pos)                     /**< (WDT_INTFLAG) Early Warning Mask */
    162. 

  162. #define WDT_INTFLAG_EW(value)                 (WDT_INTFLAG_EW_Msk & ((value) << WDT_INTFLAG_EW_Pos))
    163. 

  163. #define WDT_INTFLAG_Msk                       _U_(0x01)                                            /**< (WDT_INTFLAG) Register Mask  */
    164. 

  164. 

  165. 

  166. /* -------- WDT_STATUS : (WDT Offset: 0x07) ( R/ 8) Status -------- */
    167. 

  167. #define WDT_STATUS_RESETVALUE                 _U_(0x00)                                            /**<  (WDT_STATUS) Status  Reset Value */
    168. 

  168. 

  169. #define WDT_STATUS_SYNCBUSY_Pos               _U_(7)                                               /**< (WDT_STATUS) Synchronization Busy Position */
    170. 

  170. #define WDT_STATUS_SYNCBUSY_Msk               (_U_(0x1) << WDT_STATUS_SYNCBUSY_Pos)                /**< (WDT_STATUS) Synchronization Busy Mask */
    171. 

  171. #define WDT_STATUS_SYNCBUSY(value)            (WDT_STATUS_SYNCBUSY_Msk & ((value) << WDT_STATUS_SYNCBUSY_Pos))
    172. 

  172. #define WDT_STATUS_Msk                        _U_(0x80)                                            /**< (WDT_STATUS) Register Mask  */
    173. 

  173. 

  174. 

  175. /* -------- WDT_CLEAR : (WDT Offset: 0x08) ( /W 8) Clear -------- */
    176. 

  176. #define WDT_CLEAR_RESETVALUE                  _U_(0x00)                                            /**<  (WDT_CLEAR) Clear  Reset Value */
    177. 

  177. 

  178. #define WDT_CLEAR_CLEAR_Pos                   _U_(0)                                               /**< (WDT_CLEAR) Watchdog Clear Position */
    179. 

  179. #define WDT_CLEAR_CLEAR_Msk                   (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)                   /**< (WDT_CLEAR) Watchdog Clear Mask */
    180. 

  180. #define WDT_CLEAR_CLEAR(value)                (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
    181. 

  181. #define   WDT_CLEAR_CLEAR_KEY_Val             _U_(0xA5)                                            /**< (WDT_CLEAR) Clear Key  */
    182. 

  182. #define WDT_CLEAR_CLEAR_KEY                   (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)     /**< (WDT_CLEAR) Clear Key Position  */
    183. 

  183. #define WDT_CLEAR_Msk                         _U_(0xFF)                                            /**< (WDT_CLEAR) Register Mask  */
    184. 

  184. 

  185. 

  186. /** \brief WDT register offsets definitions */
    187. 

  187. #define WDT_CTRL_REG_OFST              (0x00)              /**< (WDT_CTRL) Control Offset */
    188. 

  188. #define WDT_CONFIG_REG_OFST            (0x01)              /**< (WDT_CONFIG) Configuration Offset */
    189. 

  189. #define WDT_EWCTRL_REG_OFST            (0x02)              /**< (WDT_EWCTRL) Early Warning Interrupt Control Offset */
    190. 

  190. #define WDT_INTENCLR_REG_OFST          (0x04)              /**< (WDT_INTENCLR) Interrupt Enable Clear Offset */
    191. 

  191. #define WDT_INTENSET_REG_OFST          (0x05)              /**< (WDT_INTENSET) Interrupt Enable Set Offset */
    192. 

  192. #define WDT_INTFLAG_REG_OFST           (0x06)              /**< (WDT_INTFLAG) Interrupt Flag Status and Clear Offset */
    193. 

  193. #define WDT_STATUS_REG_OFST            (0x07)              /**< (WDT_STATUS) Status Offset */
    194. 

  194. #define WDT_CLEAR_REG_OFST             (0x08)              /**< (WDT_CLEAR) Clear Offset */
    195. 

  195. 

  196. #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
    197. 

  197. /** \brief WDT register API structure */
    198. 

  198. typedef struct
    199. 

  199. {  /* Watchdog Timer */
    200. 

  200.   __IO  uint8_t                        WDT_CTRL;           /**< Offset: 0x00 (R/W  8) Control */
    201. 

  201.   __IO  uint8_t                        WDT_CONFIG;         /**< Offset: 0x01 (R/W  8) Configuration */
    202. 

  202.   __IO  uint8_t                        WDT_EWCTRL;         /**< Offset: 0x02 (R/W  8) Early Warning Interrupt Control */
    203. 

  203.   __I   uint8_t                        Reserved1[0x01];
    204. 

  204.   __IO  uint8_t                        WDT_INTENCLR;       /**< Offset: 0x04 (R/W  8) Interrupt Enable Clear */
    205. 

  205.   __IO  uint8_t                        WDT_INTENSET;       /**< Offset: 0x05 (R/W  8) Interrupt Enable Set */
    206. 

  206.   __IO  uint8_t                        WDT_INTFLAG;        /**< Offset: 0x06 (R/W  8) Interrupt Flag Status and Clear */
    207. 

  207.   __I   uint8_t                        WDT_STATUS;         /**< Offset: 0x07 (R/   8) Status */
    208. 

  208.   __O   uint8_t                        WDT_CLEAR;          /**< Offset: 0x08 ( /W  8) Clear */
    209. 

  209. } wdt_registers_t;
    210. 

  210. 

  211. 

  212. #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
    213. 

  213. #endif /* _SAMD21_WDT_COMPONENT_H_ */
    214.