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kopia lustrzana https://github.com/RT-Thread-Studio/sdk-bsp-psoc_e84-edgi-talk


			
				
					
						
						
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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a> &#124;
<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle"><div class="title">Async Transfer Utility Library</div></div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p >Async Transfer Utility Library provides an implementation of data transfer functions in which the calling application initiates the data transfer on the desired communication peripheral and then the data transfer happens in the background without the application involvement. </p>
<p >This library does not have direct knowledge of the underlying communication peripheral being used and the users of the library shall set up the necessary interface needed to support the background transfer on the specific communication peripheral</p>
<p ><b>Features:</b></p><ul>
<li>Both read and write transfers can be performed.</li>
<li>Transfers can performed via either CPU copy or DMA.</li>
<li>One transfer in each of direction (read and write) can be pending at the same time.</li>
<li>A callback can be invoked on completion of a transfer.</li>
<li>It is possible to query whether an async-transfer instance is available in a given direction.</li>
<li>An in-progress transfer can be aborted.</li>
<li>Repeated transfers can be performed without re-initializing.</li>
<li>Multiple instances of the async transfer library can co-exist, managing different communications interfaces.</li>
</ul>
<h1><a class="anchor" id="group_mtb_async_transfer_prerequisites"></a>
Prerequisites</h1>
<p >Setup the interfaces necessary to communicate to the underlying hardware. <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a>.</p>
<p >Allocate the memory for the context structure and set-up the underlying communication inteface's using <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a></p>
<p >For CPU based transfers, the user of async transfer must arrange for <a class="el" href="group__group__mtb__async__transfer.html#gadddf2fa4b6834900cf44825fb6465520">mtb_async_transfer_process_fifo_level_event</a> to be invoked, (e.g. by registering an interrupt handler) when FIFO reaches the desired level on the underlying communications interface.</p>
<p >For DMA based transfers, the user of async transfer must arrange for <a class="el" href="group__group__mtb__async__transfer.html#ga9102ce8d1c784a6fc1f55676998f3a8a">mtb_async_transfer_process_dma_complete</a> to be invoked, (e.g. by registering an interrupt handler) when FIFO reaches the desired level on the underlying communications interface.</p>
<p >Set up the callback to be invoked when the async transfer is complete using <a class="el" href="group__group__mtb__async__transfer.html#gaf3e152b2e23e0f0571171b7487b3f224">mtb_async_transfer_register_callback</a></p>
<h1><a class="anchor" id="group_mtb_async_transfer_code_snippets"></a>
Code Snippets</h1>
<p >Init sequence for configuring the async tranfer in CPU mode </p><div class="fragment"><div class="line"> </div>
<div class="line"><span class="comment">/* UART interrupt handler */</span></div>
<div class="line"><span class="keywordtype">void</span> uart_interrupt_handler(<span class="keywordtype">void</span>)</div>
<div class="line">{</div>
<div class="line"><span class="preprocessor">    #if defined(COMPONENT_MTB_HAL)</span></div>
<div class="line">    <span class="comment">/* If using the HAL UART */</span></div>
<div class="line">    mtb_hal_uart_process_interrupt(&amp;uart_obj);</div>
<div class="line"><span class="preprocessor">    #else</span></div>
<div class="line">    <a class="code hl_enumeration" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a> direction = (<a class="code hl_enumeration" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a>)0;</div>
<div class="line">    <span class="comment">/* If using PDL UART */</span></div>
<div class="line">    uint32_t txMasked = Cy_SCB_GetTxInterruptStatusMasked(UART_HW);</div>
<div class="line">    uint32_t rxMasked = Cy_SCB_GetRxInterruptStatusMasked(UART_HW);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* RX FIFO level event  */</span></div>
<div class="line">    <span class="keywordflow">if</span> (0u != (CY_SCB_UART_RX_TRIGGER &amp; rxMasked))</div>
<div class="line">    {</div>
<div class="line">        direction = <a class="code hl_enumvalue" href="group__group__mtb__async__transfer__enums.html#ggae10e0bbbd0c13cc5d8451a56bd23f721ad7b9031f4713373a5ae7c35d2100d816">MTB_ASYNC_TRANSFER_DIRECTION_READ</a>;</div>
<div class="line">    }</div>
<div class="line">    <span class="comment">/* TX FIFO level event  */</span></div>
<div class="line">    <span class="keywordflow">if</span> (0u != (CY_SCB_UART_TX_TRIGGER &amp; txMasked))</div>
<div class="line">    {</div>
<div class="line">        direction |= <a class="code hl_enumvalue" href="group__group__mtb__async__transfer__enums.html#ggae10e0bbbd0c13cc5d8451a56bd23f721a7ef9615b6e794c1b0b2ad553b079e724">MTB_ASYNC_TRANSFER_DIRECTION_WRITE</a>;</div>
<div class="line">    }</div>
<div class="line">    <span class="keywordflow">if</span> (direction)</div>
<div class="line">    {</div>
<div class="line">        result =</div>
<div class="line">            <a class="code hl_function" href="group__group__mtb__async__transfer.html#gadddf2fa4b6834900cf44825fb6465520">mtb_async_transfer_process_fifo_level_event</a>(async_context,</div>
<div class="line">                                                        (<a class="code hl_enumeration" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a>)direction);</div>
<div class="line">    }</div>
<div class="line"><span class="preprocessor">    #endif </span><span class="comment">// if defined(COMPONENT_MTB_HAL)</span></div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// uart_get_num_tx_fifo</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line">uint32_t uart_get_num_tx_fifo(<span class="keywordtype">void</span>* inst_ref)</div>
<div class="line">{</div>
<div class="line">    <span class="keywordflow">return</span> Cy_SCB_GetFifoSize((CySCB_Type*)inst_ref) - Cy_SCB_UART_GetNumInTxFifo(</div>
<div class="line">        (CySCB_Type*)inst_ref);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> uart_enable_rx_event(<span class="keywordtype">void</span>* inst_ref, <span class="keywordtype">bool</span> enable)</div>
<div class="line">{</div>
<div class="line">    uint32_t rx_mask = Cy_SCB_GetRxInterruptMask((CySCB_Type*)inst_ref);</div>
<div class="line">    rx_mask = (enable ? (rx_mask | CY_SCB_UART_RX_TRIGGER) : (rx_mask &amp; ~CY_SCB_UART_RX_TRIGGER));</div>
<div class="line">    Cy_SCB_SetRxInterruptMask((CySCB_Type*)inst_ref, rx_mask);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> uart_enable_tx_event(<span class="keywordtype">void</span>* inst_ref, <span class="keywordtype">bool</span> enable)</div>
<div class="line">{</div>
<div class="line">    uint32_t tx_mask = Cy_SCB_GetTxInterruptMask((CySCB_Type*)inst_ref);</div>
<div class="line">    tx_mask &amp;= ~CY_SCB_UART_TX_DONE;</div>
<div class="line">    tx_mask = (enable ? (tx_mask | CY_SCB_UART_TX_TRIGGER) : (tx_mask &amp; ~CY_SCB_UART_TX_TRIGGER));</div>
<div class="line">    Cy_SCB_SetTxInterruptMask((CySCB_Type*)inst_ref, tx_mask);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line">uint32_t uart_get_rx_transfer_len(<span class="keywordtype">void</span>* inst_ref)</div>
<div class="line">{</div>
<div class="line">    <span class="comment">/* RX transfer length is half of the fifo size when flow control is not enabled.</span></div>
<div class="line"><span class="comment">       When RTS flow control is enabled return the RTS fifo level */</span></div>
<div class="line">    <span class="keywordflow">return</span> (Cy_SCB_GetFifoSize((CySCB_Type*)inst_ref)/2);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line">uint32_t uart_get_tx_transfer_len(<span class="keywordtype">void</span>* inst_ref)</div>
<div class="line">{</div>
<div class="line">    CY_ASSERT(NULL != inst_ref);</div>
<div class="line">    <span class="comment">/* TX transfer length is half of the fifo size */</span></div>
<div class="line">    <span class="keywordflow">return</span> (Cy_SCB_GetFifoSize((CySCB_Type*)inst_ref)/2);</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// uart_get_transfer_width</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line">uint32_t uart_get_transfer_width(CySCB_Type* base)</div>
<div class="line">{</div>
<div class="line">    uint32_t transfer_width = 0;</div>
<div class="line"> </div>
<div class="line">    uint8_t mem_width = _FLD2VAL(SCB_CTRL_MEM_WIDTH, SCB_CTRL(base));</div>
<div class="line">    <span class="keywordflow">if</span> (CY_SCB_MEM_WIDTH_BYTE == mem_width)</div>
<div class="line">    {</div>
<div class="line">        transfer_width = 1;</div>
<div class="line">    }</div>
<div class="line">    <span class="keywordflow">else</span> <span class="keywordflow">if</span> (CY_SCB_MEM_WIDTH_HALFWORD == mem_width)</div>
<div class="line">    {</div>
<div class="line">        transfer_width = 2;</div>
<div class="line">    }</div>
<div class="line">    <span class="keywordflow">else</span></div>
<div class="line">    {</div>
<div class="line">        transfer_width = 4;</div>
<div class="line">    }</div>
<div class="line">    <span class="keywordflow">return</span> transfer_width;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// snippet_async_transfer_init</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"> </div>
<div class="line"><span class="keywordtype">void</span> snippet_async_transfer_cpu_mode(<span class="keywordtype">void</span>)</div>
<div class="line">{</div>
<div class="line">    <span class="comment">/* Snippet example using the UART peripheral driver configured to</span></div>
<div class="line"><span class="comment">       use async transfer library in cpu mode  */</span></div>
<div class="line"><span class="preprocessor">    #define INT_PRIORITY    3</span></div>
<div class="line"> </div>
<div class="line">    cy_rslt_t                         result;</div>
<div class="line">    cy_stc_scb_uart_context_t         uart_context;</div>
<div class="line">    <a class="code hl_struct" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a>    interface;</div>
<div class="line">    <span class="comment">/* Pre-requisites</span></div>
<div class="line"><span class="comment">       1. Initialize the communication peripheral</span></div>
<div class="line"><span class="comment">       2. Configure and enable the FIFO level interrupts.</span></div>
<div class="line"><span class="comment">     */</span></div>
<div class="line">    result = (cy_rslt_t)Cy_SCB_UART_Init(UART_HW, &amp;UART_config, &amp;uart_context);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">//Optional. If using the HAL UART</span></div>
<div class="line">    result = mtb_hal_uart_setup(&amp;uart_obj, &amp;UART_hal_config, &amp;uart_context, NULL);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// The UART interrupt handler registration</span></div>
<div class="line">    <span class="comment">// UART_IRQ generated by configurator, named &lt;alias&gt;_IRQ</span></div>
<div class="line">    cy_stc_sysint_t intr_cfg = { .intrSrc = UART_IRQ, .intrPriority = INT_PRIORITY };</div>
<div class="line">    Cy_SysInt_Init(&amp;intr_cfg, uart_interrupt_handler);</div>
<div class="line">    NVIC_EnableIRQ(UART_IRQ);</div>
<div class="line"> </div>
<div class="line">    Cy_SCB_UART_Enable(UART_HW);</div>
<div class="line"> </div>
<div class="line">    memset(&amp;interface, 0, <span class="keyword">sizeof</span>(<a class="code hl_struct" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a>));</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Setup the interface parameters with the communication peripheral parameters */</span></div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#ad393fcae19339846cc98de24f99bb48f">rx_addr</a> = (uint32_t*)&amp;(UART_HW-&gt;RX_FIFO_RD);</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a8717fd34ec30b4927e1e7f27198a5b9b">tx_addr</a> = (uint32_t*)&amp;(UART_HW-&gt;TX_FIFO_WR);</div>
<div class="line">    <span class="comment">/*Set this directly to the communications peripheral object.*/</span></div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a4759ceb034df644da6ec95074d9fab9d">inst_ref</a> = UART_HW;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a6700d7056c007f225b75512df2ab6101">get_num_rx_fifo</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga8da955cf4475bcb81bd2d4da8b530b8d">mtb_async_transfer_get_num_fifo_t</a>)Cy_SCB_UART_GetNumInRxFifo;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#ae27025d1194254682cdbb2589a7e09d6">get_num_tx_fifo</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga8da955cf4475bcb81bd2d4da8b530b8d">mtb_async_transfer_get_num_fifo_t</a>)uart_get_num_tx_fifo;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#abc2fb6c290c50cd9c2d0c7258976d664">set_rx_fifo_level</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga5b9d27c64c0295597435384aad21af94">mtb_async_transfer_set_fifo_level_t</a>)Cy_SCB_SetRxFifoLevel;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a63f08554036e8dc284e4cfcc71dde869">set_tx_fifo_level</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga5b9d27c64c0295597435384aad21af94">mtb_async_transfer_set_fifo_level_t</a>)Cy_SCB_SetTxFifoLevel;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a5c7fe3b7b2ee9962c2aab11ad773cc09">enable_rx_event</a> = uart_enable_rx_event;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a7a9ee2fc5ccbbab7bd33f90c54e6ca6a">enable_tx_event</a> = uart_enable_tx_event;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#afb123c395bc38c33747531701044df34">get_rx_transfer_len</a> = uart_get_rx_transfer_len;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a578028b3acec771cc0c44d6cfc57e00b">get_tx_transfer_len</a> = uart_get_tx_transfer_len;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a9c5b141007261b64ef99aad35a64cbf6">transfer_width</a> = uart_get_transfer_width(UART_HW); <span class="comment">/* Read from config</span></div>
<div class="line"><span class="comment">                                                                               registers */</span></div>
<div class="line"> </div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a36dd368bdfce3a9a3373fc585f55eb26">enter_critical_section</a> = Cy_SysLib_EnterCriticalSection;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a5bdb20d4b55105941f81ecc905c84f8b">exit_critical_section</a> = Cy_SysLib_ExitCriticalSection;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Initialialize the async transfer lib */</span></div>
<div class="line">    result = <a class="code hl_function" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a>(&amp;async_context, &amp;interface);</div>
<div class="line">    (void)result;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="ttc" id="agroup__group__mtb__async__transfer__enums_html_gae10e0bbbd0c13cc5d8451a56bd23f721"><div class="ttname"><a href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a></div><div class="ttdeci">mtb_async_transfer_direction_t</div><div class="ttdoc">Async Transfer direction</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:143</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__enums_html_ggae10e0bbbd0c13cc5d8451a56bd23f721a7ef9615b6e794c1b0b2ad553b079e724"><div class="ttname"><a href="group__group__mtb__async__transfer__enums.html#ggae10e0bbbd0c13cc5d8451a56bd23f721a7ef9615b6e794c1b0b2ad553b079e724">MTB_ASYNC_TRANSFER_DIRECTION_WRITE</a></div><div class="ttdeci">@ MTB_ASYNC_TRANSFER_DIRECTION_WRITE</div><div class="ttdoc">Write Transfer.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:145</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__enums_html_ggae10e0bbbd0c13cc5d8451a56bd23f721ad7b9031f4713373a5ae7c35d2100d816"><div class="ttname"><a href="group__group__mtb__async__transfer__enums.html#ggae10e0bbbd0c13cc5d8451a56bd23f721ad7b9031f4713373a5ae7c35d2100d816">MTB_ASYNC_TRANSFER_DIRECTION_READ</a></div><div class="ttdeci">@ MTB_ASYNC_TRANSFER_DIRECTION_READ</div><div class="ttdoc">Read Transfer.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:144</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__function__pointers_html_ga5b9d27c64c0295597435384aad21af94"><div class="ttname"><a href="group__group__mtb__async__transfer__function__pointers.html#ga5b9d27c64c0295597435384aad21af94">mtb_async_transfer_set_fifo_level_t</a></div><div class="ttdeci">void(* mtb_async_transfer_set_fifo_level_t)(void *inst_ref, uint32_t level)</div><div class="ttdoc">Function pointer to set the fifo level for triggering an interrupt when the number of elements in the...</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:175</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__function__pointers_html_ga8da955cf4475bcb81bd2d4da8b530b8d"><div class="ttname"><a href="group__group__mtb__async__transfer__function__pointers.html#ga8da955cf4475bcb81bd2d4da8b530b8d">mtb_async_transfer_get_num_fifo_t</a></div><div class="ttdeci">uint32_t(* mtb_async_transfer_get_num_fifo_t)(void *inst_ref)</div><div class="ttdoc">Function pointer for returning the number of elements that can be read from the FIFO in case of rx or...</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:166</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a36dd368bdfce3a9a3373fc585f55eb26"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a36dd368bdfce3a9a3373fc585f55eb26">mtb_async_transfer_interface_t::enter_critical_section</a></div><div class="ttdeci">mtb_async_transfer_enter_critical_section_t enter_critical_section</div><div class="ttdoc">Function to enter critical section.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:315</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a4759ceb034df644da6ec95074d9fab9d"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a4759ceb034df644da6ec95074d9fab9d">mtb_async_transfer_interface_t::inst_ref</a></div><div class="ttdeci">void * inst_ref</div><div class="ttdoc">The opaque pointer that is passed as the first argument to all non-DMA functions.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:258</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a578028b3acec771cc0c44d6cfc57e00b"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a578028b3acec771cc0c44d6cfc57e00b">mtb_async_transfer_interface_t::get_tx_transfer_len</a></div><div class="ttdeci">mtb_async_transfer_get_len_t get_tx_transfer_len</div><div class="ttdoc">Number of elements that the peripheral interface can transmit in a single transfer.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:294</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a5bdb20d4b55105941f81ecc905c84f8b"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a5bdb20d4b55105941f81ecc905c84f8b">mtb_async_transfer_interface_t::exit_critical_section</a></div><div class="ttdeci">mtb_async_transfer_exit_critical_section_t exit_critical_section</div><div class="ttdoc">Function to exit critical section.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:318</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a5c7fe3b7b2ee9962c2aab11ad773cc09"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a5c7fe3b7b2ee9962c2aab11ad773cc09">mtb_async_transfer_interface_t::enable_rx_event</a></div><div class="ttdeci">mtb_async_transfer_set_enabled_t enable_rx_event</div><div class="ttdoc">Function to enable/disable RX FIFO level interrupt event.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:279</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a63f08554036e8dc284e4cfcc71dde869"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a63f08554036e8dc284e4cfcc71dde869">mtb_async_transfer_interface_t::set_tx_fifo_level</a></div><div class="ttdeci">mtb_async_transfer_set_fifo_level_t set_tx_fifo_level</div><div class="ttdoc">Function to set the TX FIFO level below which the interrupt is triggered.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:276</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a6700d7056c007f225b75512df2ab6101"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a6700d7056c007f225b75512df2ab6101">mtb_async_transfer_interface_t::get_num_rx_fifo</a></div><div class="ttdeci">mtb_async_transfer_get_num_fifo_t get_num_rx_fifo</div><div class="ttdoc">Function to get the number of elements available in the RX FIFO.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:267</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a7a9ee2fc5ccbbab7bd33f90c54e6ca6a"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a7a9ee2fc5ccbbab7bd33f90c54e6ca6a">mtb_async_transfer_interface_t::enable_tx_event</a></div><div class="ttdeci">mtb_async_transfer_set_enabled_t enable_tx_event</div><div class="ttdoc">Function to enable/disable TX FIFO level interrupt event.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:282</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a8717fd34ec30b4927e1e7f27198a5b9b"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a8717fd34ec30b4927e1e7f27198a5b9b">mtb_async_transfer_interface_t::tx_addr</a></div><div class="ttdeci">volatile uint32_t * tx_addr</div><div class="ttdoc">Pointer to the write data destination address.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:264</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a9c5b141007261b64ef99aad35a64cbf6"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a9c5b141007261b64ef99aad35a64cbf6">mtb_async_transfer_interface_t::transfer_width</a></div><div class="ttdeci">uint32_t transfer_width</div><div class="ttdoc">Width, in bytes, of each FIFO element.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:297</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_abc2fb6c290c50cd9c2d0c7258976d664"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#abc2fb6c290c50cd9c2d0c7258976d664">mtb_async_transfer_interface_t::set_rx_fifo_level</a></div><div class="ttdeci">mtb_async_transfer_set_fifo_level_t set_rx_fifo_level</div><div class="ttdoc">Function to set the RX FIFO level above which the interrupt is triggered.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:273</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_ad393fcae19339846cc98de24f99bb48f"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#ad393fcae19339846cc98de24f99bb48f">mtb_async_transfer_interface_t::rx_addr</a></div><div class="ttdeci">volatile uint32_t * rx_addr</div><div class="ttdoc">Pointer to the read data source address.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:261</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_ae27025d1194254682cdbb2589a7e09d6"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#ae27025d1194254682cdbb2589a7e09d6">mtb_async_transfer_interface_t::get_num_tx_fifo</a></div><div class="ttdeci">mtb_async_transfer_get_num_fifo_t get_num_tx_fifo</div><div class="ttdoc">Function to get the number of elements that can be written to the TX FIFO.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:270</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_afb123c395bc38c33747531701044df34"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#afb123c395bc38c33747531701044df34">mtb_async_transfer_interface_t::get_rx_transfer_len</a></div><div class="ttdeci">mtb_async_transfer_get_len_t get_rx_transfer_len</div><div class="ttdoc">Number of elements that the peripheral interface can receive in a single transfer.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:291</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_structmtb__async__transfer__interface__t"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a></div><div class="ttdoc">Async Transfer interface data structure.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:254</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer_html_ga44c0d4c223daff0e24eca2253c0875ff"><div class="ttname"><a href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a></div><div class="ttdeci">cy_rslt_t mtb_async_transfer_init(mtb_async_transfer_context_t *context, const mtb_async_transfer_interface_t *iface)</div><div class="ttdoc">Initializes an async transfer library instance.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.c:439</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer_html_gadddf2fa4b6834900cf44825fb6465520"><div class="ttname"><a href="group__group__mtb__async__transfer.html#gadddf2fa4b6834900cf44825fb6465520">mtb_async_transfer_process_fifo_level_event</a></div><div class="ttdeci">cy_rslt_t mtb_async_transfer_process_fifo_level_event(mtb_async_transfer_context_t *context, mtb_async_transfer_direction_t direction)</div><div class="ttdoc">Handler for when the FIFO in the peripheral reaches the trigger level.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.c:648</div></div>
</div><!-- fragment --><p >Init sequence for configuring the async tranfer in DMA mode </p><div class="fragment"><div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// dma_interrupt_handler</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="keywordtype">void</span> dma_interrupt_handler(<span class="keywordtype">void</span>)</div>
<div class="line">{</div>
<div class="line">    cy_rslt_t result;</div>
<div class="line"><span class="preprocessor">    #if defined(COMPONENT_MTB_HAL)</span></div>
<div class="line">    <span class="comment">//If using the HAL DMA</span></div>
<div class="line">    mtb_hal_dma_process_interrupt(&amp;dma_obj);</div>
<div class="line"><span class="preprocessor">    #else</span></div>
<div class="line">    cy_en_dma_intr_cause_t cause = Cy_DMA_Channel_GetStatus(DMA_HW, DMA_CHANNEL);</div>
<div class="line">    Cy_DMA_Channel_ClearInterrupt(DMA_HW, DMA_CHANNEL);</div>
<div class="line">    <span class="keywordflow">if</span> (cause == CY_DMA_INTR_CAUSE_COMPLETION)</div>
<div class="line">    {</div>
<div class="line">        <span class="comment">/* Select the direction as read or write based on if the DMA channel is configured for read</span></div>
<div class="line"><span class="comment">           or write */</span></div>
<div class="line">        result = <a class="code hl_function" href="group__group__mtb__async__transfer.html#ga9102ce8d1c784a6fc1f55676998f3a8a">mtb_async_transfer_process_dma_complete</a>(&amp;async_context,</div>
<div class="line">                                                         <a class="code hl_enumvalue" href="group__group__mtb__async__transfer__enums.html#ggae10e0bbbd0c13cc5d8451a56bd23f721ad7b9031f4713373a5ae7c35d2100d816">MTB_ASYNC_TRANSFER_DIRECTION_READ</a>);</div>
<div class="line">    }</div>
<div class="line"><span class="preprocessor">    #endif </span><span class="comment">// if defined(COMPONENT_MTB_HAL)</span></div>
<div class="line"><span class="comment"></span>    (void)result;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// uart_dma_set_src_addr</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line">cy_rslt_t uart_dma_set_src_addr(<span class="keywordtype">void</span>* dma_ref, <span class="keywordtype">void</span>* addr)</div>
<div class="line">{</div>
<div class="line">    Cy_DMA_Descriptor_SetSrcAddress((cy_stc_dma_descriptor_t*)dma_ref, addr);</div>
<div class="line">    <span class="keywordflow">return</span> CY_RSLT_SUCCESS;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// uart_dma_set_dest_addr</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line">cy_rslt_t uart_dma_set_dest_addr(<span class="keywordtype">void</span>* dma_ref, <span class="keywordtype">void</span>* addr)</div>
<div class="line">{</div>
<div class="line">    Cy_DMA_Descriptor_SetDstAddress((cy_stc_dma_descriptor_t*)dma_ref, addr);</div>
<div class="line">    <span class="keywordflow">return</span> CY_RSLT_SUCCESS;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// uart_dma_set_len</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line">cy_rslt_t uart_dma_set_len(<span class="keywordtype">void</span>* dma_ref, <span class="keywordtype">size_t</span> len)</div>
<div class="line">{</div>
<div class="line">    <span class="comment">//Set the length based on the descriptor type</span></div>
<div class="line">    Cy_DMA_Descriptor_SetXloopDataCount((cy_stc_dma_descriptor_t*)dma_ref, len);</div>
<div class="line">    <span class="keywordflow">return</span> CY_RSLT_SUCCESS;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// uart_dma_enable_rx</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="keywordtype">void</span> uart_dma_enable_rx(<span class="keywordtype">void</span>* dma_ref, <span class="keywordtype">bool</span> enable)</div>
<div class="line">{</div>
<div class="line">    enable ? Cy_DMA_Channel_Enable(DMA_HW, DMA_CHANNEL) : Cy_DMA_Channel_Disable(DMA_HW,</div>
<div class="line">                                                                                 DMA_CHANNEL);</div>
<div class="line">    (void)dma_ref;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="comment">// snippet_async_transfer_dma_mode</span></div>
<div class="line"><span class="comment">//--------------------------------------------------------------------------------------------------</span></div>
<div class="line"><span class="keywordtype">void</span> snippet_async_transfer_dma_mode(<span class="keywordtype">void</span>)</div>
<div class="line">{</div>
<div class="line">    <span class="comment">/* Snippet example using the UART peripheral driver configured to</span></div>
<div class="line"><span class="comment">       use async transfer library in dma mode  */</span></div>
<div class="line"><span class="preprocessor">    #define INT_PRIORITY    3</span></div>
<div class="line"> </div>
<div class="line">    cy_rslt_t                         result;</div>
<div class="line">    cy_en_dma_status_t                status;</div>
<div class="line">    cy_stc_scb_uart_context_t         uart_context;</div>
<div class="line">    <a class="code hl_struct" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a>    interface;</div>
<div class="line">    <span class="comment">/* Pre-requisites</span></div>
<div class="line"><span class="comment">       1. Initialize the communication peripheral</span></div>
<div class="line"><span class="comment">       2. Configure and enable the FIFO level interrupts.</span></div>
<div class="line"><span class="comment">       3. Configure and enable the DMA channels if DMA mode async transfer is desired</span></div>
<div class="line"><span class="comment">       4. Configure the routing between the communication peripheral and DMA if DMA mode async</span></div>
<div class="line"><span class="comment">          transfer is desired</span></div>
<div class="line"><span class="comment">     */</span></div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Setting up the descriptor and the channel */</span></div>
<div class="line">    status = Cy_DMA_Descriptor_Init(&amp;dma_Descriptor_0, &amp;dma_Descriptor_0_config);</div>
<div class="line">    status =  Cy_DMA_Channel_Init(DMA_HW, DMA_CHANNEL, &amp;dma_channelConfig);</div>
<div class="line">    Cy_DMA_Channel_SetInterruptMask(DMA_HW, DMA_CHANNEL, CY_DMA_INTR_MASK);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">//Optional. If using the HAL DMA</span></div>
<div class="line">    result = mtb_hal_dma_setup(&amp;dma_obj, &amp;dma_hal_config);</div>
<div class="line"> </div>
<div class="line">    cy_stc_sysint_t dma_intr_cfg = { .intrSrc = DMA_IRQ, .intrPriority = INT_PRIORITY };</div>
<div class="line">    Cy_SysInt_Init(&amp;dma_intr_cfg, dma_interrupt_handler);</div>
<div class="line">    NVIC_EnableIRQ(DMA_IRQ);</div>
<div class="line"> </div>
<div class="line">    Cy_DMA_Enable(DMA_HW);</div>
<div class="line"> </div>
<div class="line">    result = (cy_rslt_t)Cy_SCB_UART_Init(UART_HW, &amp;UART_config, &amp;uart_context);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">//Optional. If using the HAL UART</span></div>
<div class="line">    result = mtb_hal_uart_setup(&amp;uart_obj, &amp;UART_hal_config, &amp;uart_context, NULL);</div>
<div class="line"> </div>
<div class="line">    <span class="comment">// The UART interrupt handler registration</span></div>
<div class="line">    <span class="comment">// UART_IRQ generated by configurator, named &lt;alias&gt;_IRQ</span></div>
<div class="line">    cy_stc_sysint_t intr_cfg = { .intrSrc = UART_IRQ, .intrPriority = INT_PRIORITY };</div>
<div class="line">    Cy_SysInt_Init(&amp;intr_cfg, uart_interrupt_handler);</div>
<div class="line">    NVIC_EnableIRQ(UART_IRQ);</div>
<div class="line"> </div>
<div class="line">    Cy_SCB_UART_Enable(UART_HW);</div>
<div class="line"> </div>
<div class="line">    memset(&amp;interface, 0, <span class="keyword">sizeof</span>(<a class="code hl_struct" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a>));</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Setup the interface parameters with the communication peripheral parameters */</span></div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#ad393fcae19339846cc98de24f99bb48f">rx_addr</a> = (uint32_t*)&amp;(UART_HW-&gt;RX_FIFO_RD);</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a8717fd34ec30b4927e1e7f27198a5b9b">tx_addr</a> = (uint32_t*)&amp;(UART_HW-&gt;TX_FIFO_WR);</div>
<div class="line">    <span class="comment">/* Set this directly to the communications peripheral object.*/</span></div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a4759ceb034df644da6ec95074d9fab9d">inst_ref</a> = UART_HW;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a6700d7056c007f225b75512df2ab6101">get_num_rx_fifo</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga8da955cf4475bcb81bd2d4da8b530b8d">mtb_async_transfer_get_num_fifo_t</a>)Cy_SCB_UART_GetNumInRxFifo;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#ae27025d1194254682cdbb2589a7e09d6">get_num_tx_fifo</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga8da955cf4475bcb81bd2d4da8b530b8d">mtb_async_transfer_get_num_fifo_t</a>)uart_get_num_tx_fifo;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#abc2fb6c290c50cd9c2d0c7258976d664">set_rx_fifo_level</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga5b9d27c64c0295597435384aad21af94">mtb_async_transfer_set_fifo_level_t</a>)Cy_SCB_SetRxFifoLevel;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a63f08554036e8dc284e4cfcc71dde869">set_tx_fifo_level</a> = (<a class="code hl_typedef" href="group__group__mtb__async__transfer__function__pointers.html#ga5b9d27c64c0295597435384aad21af94">mtb_async_transfer_set_fifo_level_t</a>)Cy_SCB_SetTxFifoLevel;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a5c7fe3b7b2ee9962c2aab11ad773cc09">enable_rx_event</a> = uart_enable_rx_event;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a7a9ee2fc5ccbbab7bd33f90c54e6ca6a">enable_tx_event</a> = uart_enable_tx_event;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#afb123c395bc38c33747531701044df34">get_rx_transfer_len</a> = uart_get_rx_transfer_len;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a578028b3acec771cc0c44d6cfc57e00b">get_tx_transfer_len</a> = uart_get_tx_transfer_len;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a9c5b141007261b64ef99aad35a64cbf6">transfer_width</a> = uart_get_transfer_width(UART_HW); <span class="comment">/* Read from config</span></div>
<div class="line"><span class="comment">                                                                               registers */</span></div>
<div class="line"> </div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a36dd368bdfce3a9a3373fc585f55eb26">enter_critical_section</a> = Cy_SysLib_EnterCriticalSection;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a5bdb20d4b55105941f81ecc905c84f8b">exit_critical_section</a> = Cy_SysLib_ExitCriticalSection;</div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* DMA specfic interface parameters */</span></div>
<div class="line">    <span class="comment">/* Using the PDL functions. Use HAL DMA functions when HAL drivers are used */</span></div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#aa54850049bd0ba9bf2d9048329083961">dma_rx_ref</a> = &amp;dma_Descriptor_0; <span class="comment">//Use HAL DMA object when HAL DMA is used</span></div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a74a2ece59a31f699b4a0d237886aa8b4">dma_tx_ref</a> = NULL; <span class="comment">//Set if tx dma is needed</span></div>
<div class="line"> </div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a1cbde243e4144720eabe1a1d7f8e1dbe">dma_set_length</a> = uart_dma_set_len;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a5ae6d025097787de4728fb28454de11a">dma_set_src</a> = uart_dma_set_src_addr;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#ab830086929b982a803ba369d6ffb0343">dma_set_dest</a> = uart_dma_set_dest_addr;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a1af0776a6c375b6a98faf8dba9809da4">dma_enable_rx</a> = uart_dma_enable_rx;</div>
<div class="line">    interface.<a class="code hl_variable" href="group__group__mtb__async__transfer__structures.html#a5288537c73f66ce24159d7f3bbf758bc">dma_enable_tx</a> = NULL; <span class="comment">//Set if tx dma is needed</span></div>
<div class="line"> </div>
<div class="line">    <span class="comment">/* Initialize the async transfer lib */</span></div>
<div class="line">    result = <a class="code hl_function" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a>(&amp;async_context, &amp;interface);</div>
<div class="line">    (void)status;</div>
<div class="line">    (void)result;</div>
<div class="line">}</div>
<div class="line"> </div>
<div class="line"> </div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a1af0776a6c375b6a98faf8dba9809da4"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a1af0776a6c375b6a98faf8dba9809da4">mtb_async_transfer_interface_t::dma_enable_rx</a></div><div class="ttdeci">mtb_async_transfer_set_enabled_t dma_enable_rx</div><div class="ttdoc">Function to enable/disable RX DMA event and RX DMA channel.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:285</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a1cbde243e4144720eabe1a1d7f8e1dbe"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a1cbde243e4144720eabe1a1d7f8e1dbe">mtb_async_transfer_interface_t::dma_set_length</a></div><div class="ttdeci">mtb_async_transfer_dma_set_len_t dma_set_length</div><div class="ttdoc">Function to set the DMA transfer length.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:306</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a5288537c73f66ce24159d7f3bbf758bc"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a5288537c73f66ce24159d7f3bbf758bc">mtb_async_transfer_interface_t::dma_enable_tx</a></div><div class="ttdeci">mtb_async_transfer_set_enabled_t dma_enable_tx</div><div class="ttdoc">Function to enable/disable TX DMA event and TX DMA channel.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:288</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a5ae6d025097787de4728fb28454de11a"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a5ae6d025097787de4728fb28454de11a">mtb_async_transfer_interface_t::dma_set_src</a></div><div class="ttdeci">mtb_async_transfer_dma_set_addr_t dma_set_src</div><div class="ttdoc">Function to set the DMA source address.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:309</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_a74a2ece59a31f699b4a0d237886aa8b4"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#a74a2ece59a31f699b4a0d237886aa8b4">mtb_async_transfer_interface_t::dma_tx_ref</a></div><div class="ttdeci">void * dma_tx_ref</div><div class="ttdoc">Opaque pointer that is passed as the first argument when operating on the TX DMA.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:303</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_aa54850049bd0ba9bf2d9048329083961"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#aa54850049bd0ba9bf2d9048329083961">mtb_async_transfer_interface_t::dma_rx_ref</a></div><div class="ttdeci">void * dma_rx_ref</div><div class="ttdoc">Opaque pointer that is passed as the first argument when operating on the RX DMA.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:300</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer__structures_html_ab830086929b982a803ba369d6ffb0343"><div class="ttname"><a href="group__group__mtb__async__transfer__structures.html#ab830086929b982a803ba369d6ffb0343">mtb_async_transfer_interface_t::dma_set_dest</a></div><div class="ttdeci">mtb_async_transfer_dma_set_addr_t dma_set_dest</div><div class="ttdoc">Function to set the DMA destination address.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.h:312</div></div>
<div class="ttc" id="agroup__group__mtb__async__transfer_html_ga9102ce8d1c784a6fc1f55676998f3a8a"><div class="ttname"><a href="group__group__mtb__async__transfer.html#ga9102ce8d1c784a6fc1f55676998f3a8a">mtb_async_transfer_process_dma_complete</a></div><div class="ttdeci">cy_rslt_t mtb_async_transfer_process_dma_complete(mtb_async_transfer_context_t *context, mtb_async_transfer_direction_t direction)</div><div class="ttdoc">Handler for when a DMA transfer is complete.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.c:678</div></div>
</div><!-- fragment --><p >Read operation </p><div class="fragment"><div class="line">    result = <a class="code hl_function" href="group__group__mtb__async__transfer.html#ga8e9f690b2c935c52fe6129fa5e968887">mtb_async_transfer_read</a>(&amp;async_context, rx_buffer, <span class="keyword">sizeof</span>(rx_buffer));</div>
<div class="ttc" id="agroup__group__mtb__async__transfer_html_ga8e9f690b2c935c52fe6129fa5e968887"><div class="ttname"><a href="group__group__mtb__async__transfer.html#ga8e9f690b2c935c52fe6129fa5e968887">mtb_async_transfer_read</a></div><div class="ttdeci">cy_rslt_t mtb_async_transfer_read(mtb_async_transfer_context_t *context, void *dest, size_t length)</div><div class="ttdoc">Reads data from the peripheral to the memory in the background.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.c:457</div></div>
</div><!-- fragment --><p >Write operation </p><div class="fragment"><div class="line">    result = <a class="code hl_function" href="group__group__mtb__async__transfer.html#ga8bc39198390d84a9b472b4aa6a8ea162">mtb_async_transfer_write</a>(&amp;async_context, tx_buffer, <span class="keyword">sizeof</span>(tx_buffer));</div>
<div class="ttc" id="agroup__group__mtb__async__transfer_html_ga8bc39198390d84a9b472b4aa6a8ea162"><div class="ttname"><a href="group__group__mtb__async__transfer.html#ga8bc39198390d84a9b472b4aa6a8ea162">mtb_async_transfer_write</a></div><div class="ttdeci">cy_rslt_t mtb_async_transfer_write(mtb_async_transfer_context_t *context, void *source, uint32_t length)</div><div class="ttdoc">Writes data from memory to the peripheral in the background.</div><div class="ttdef"><b>Definition:</b> mtb_async_transfer.c:505</div></div>
</div><!-- fragment --> <table class="memberdecls">
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API Reference</h2></td></tr>
<tr class="memitem:group__group__mtb__async__transfer__enums"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer__enums.html">Enumerated Types</a></td></tr>
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<tr class="memitem:group__group__mtb__async__transfer__function__pointers"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer__function__pointers.html">Function Pointers</a></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__mtb__async__transfer__structures"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer__structures.html">Data Structures</a></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:gaa68b8fd89143d1b916a6ada6d64bdaad"><td class="memItemLeft" align="right" valign="top"><a id="gaa68b8fd89143d1b916a6ada6d64bdaad" name="gaa68b8fd89143d1b916a6ada6d64bdaad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MTB_ASYNC_TRANSFER_BAD_PARAM_ERROR</b>&#160;&#160;&#160;    CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_ASYNC_TRANSFER, 0)</td></tr>
<tr class="memdesc:gaa68b8fd89143d1b916a6ada6d64bdaad"><td class="mdescLeft">&#160;</td><td class="mdescRight">An invalid parameter value is passed in. <br /></td></tr>
<tr class="separator:gaa68b8fd89143d1b916a6ada6d64bdaad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4c2df25acc23075002e3eeff7d5c6d7"><td class="memItemLeft" align="right" valign="top"><a id="gac4c2df25acc23075002e3eeff7d5c6d7" name="gac4c2df25acc23075002e3eeff7d5c6d7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MTB_ASYNC_TRANSFER_READ_BUSY</b>&#160;&#160;&#160;    CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_ASYNC_TRANSFER, 1)</td></tr>
<tr class="memdesc:gac4c2df25acc23075002e3eeff7d5c6d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">A read transfer is already in progress. <br /></td></tr>
<tr class="separator:gac4c2df25acc23075002e3eeff7d5c6d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8df1e31939609ecf640ec260330a0237"><td class="memItemLeft" align="right" valign="top"><a id="ga8df1e31939609ecf640ec260330a0237" name="ga8df1e31939609ecf640ec260330a0237"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MTB_ASYNC_TRANSFER_WRITE_BUSY</b>&#160;&#160;&#160;    CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_ASYNC_TRANSFER, 2)</td></tr>
<tr class="memdesc:ga8df1e31939609ecf640ec260330a0237"><td class="mdescLeft">&#160;</td><td class="mdescRight">A write transfer is already in progress. <br /></td></tr>
<tr class="separator:ga8df1e31939609ecf640ec260330a0237"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4a647f2f4ce6aec62f60fe2315716e0"><td class="memItemLeft" align="right" valign="top"><a id="gac4a647f2f4ce6aec62f60fe2315716e0" name="gac4a647f2f4ce6aec62f60fe2315716e0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MTB_ASYNC_TRANSFER_READ_ERROR</b>&#160;&#160;&#160;    CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_ASYNC_TRANSFER, 3)</td></tr>
<tr class="memdesc:gac4a647f2f4ce6aec62f60fe2315716e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">An error occurred when performing read transfer. <br /></td></tr>
<tr class="separator:gac4a647f2f4ce6aec62f60fe2315716e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga33d97fac7eb47391707bc753bfd70e4f"><td class="memItemLeft" align="right" valign="top"><a id="ga33d97fac7eb47391707bc753bfd70e4f" name="ga33d97fac7eb47391707bc753bfd70e4f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MTB_ASYNC_TRANSFER_WRITE_ERROR</b>&#160;&#160;&#160;    CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_ASYNC_TRANSFER, 4)</td></tr>
<tr class="memdesc:ga33d97fac7eb47391707bc753bfd70e4f"><td class="mdescLeft">&#160;</td><td class="mdescRight">An error occurred when performing write transfer. <br /></td></tr>
<tr class="separator:ga33d97fac7eb47391707bc753bfd70e4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b34a731ec3563558eecaf4d101fad74"><td class="memItemLeft" align="right" valign="top"><a id="ga8b34a731ec3563558eecaf4d101fad74" name="ga8b34a731ec3563558eecaf4d101fad74"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>MTB_ASYNC_TRANSFER_READ_WRITE_ERROR</b>&#160;&#160;&#160;    CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_MIDDLEWARE_ASYNC_TRANSFER, 5)</td></tr>
<tr class="memdesc:ga8b34a731ec3563558eecaf4d101fad74"><td class="mdescLeft">&#160;</td><td class="mdescRight">An error occurred when performing both read and write transfer. <br /></td></tr>
<tr class="separator:ga8b34a731ec3563558eecaf4d101fad74"><td class="memSeparator" colspan="2">&#160;</td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga44c0d4c223daff0e24eca2253c0875ff"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context, const <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a> *iface)</td></tr>
<tr class="memdesc:ga44c0d4c223daff0e24eca2253c0875ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initializes an async transfer library instance.  <a href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">More...</a><br /></td></tr>
<tr class="separator:ga44c0d4c223daff0e24eca2253c0875ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8e9f690b2c935c52fe6129fa5e968887"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#ga8e9f690b2c935c52fe6129fa5e968887">mtb_async_transfer_read</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context, void *dest, size_t length)</td></tr>
<tr class="memdesc:ga8e9f690b2c935c52fe6129fa5e968887"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads data from the peripheral to the memory in the background.  <a href="group__group__mtb__async__transfer.html#ga8e9f690b2c935c52fe6129fa5e968887">More...</a><br /></td></tr>
<tr class="separator:ga8e9f690b2c935c52fe6129fa5e968887"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bc39198390d84a9b472b4aa6a8ea162"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#ga8bc39198390d84a9b472b4aa6a8ea162">mtb_async_transfer_write</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context, void *source, uint32_t length)</td></tr>
<tr class="memdesc:ga8bc39198390d84a9b472b4aa6a8ea162"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes data from memory to the peripheral in the background.  <a href="group__group__mtb__async__transfer.html#ga8bc39198390d84a9b472b4aa6a8ea162">More...</a><br /></td></tr>
<tr class="separator:ga8bc39198390d84a9b472b4aa6a8ea162"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a8749266d4d6510222cc14b9ae088b8"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#ga5a8749266d4d6510222cc14b9ae088b8">mtb_async_transfer_available_read</a> (const <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context)</td></tr>
<tr class="memdesc:ga5a8749266d4d6510222cc14b9ae088b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks whether the async-transfer instance is available to start a read transfer.  <a href="group__group__mtb__async__transfer.html#ga5a8749266d4d6510222cc14b9ae088b8">More...</a><br /></td></tr>
<tr class="separator:ga5a8749266d4d6510222cc14b9ae088b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1ee1eb7b2db5b01cc47cefcae27bb14d"><td class="memItemLeft" align="right" valign="top">bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#ga1ee1eb7b2db5b01cc47cefcae27bb14d">mtb_async_transfer_available_write</a> (const <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context)</td></tr>
<tr class="memdesc:ga1ee1eb7b2db5b01cc47cefcae27bb14d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks whether the async-transfer instance is available to start a write transfer.  <a href="group__group__mtb__async__transfer.html#ga1ee1eb7b2db5b01cc47cefcae27bb14d">More...</a><br /></td></tr>
<tr class="separator:ga1ee1eb7b2db5b01cc47cefcae27bb14d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafd6cd2b1728769d406fa0bbbab1a7dd7"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#gafd6cd2b1728769d406fa0bbbab1a7dd7">mtb_async_transfer_abort_read</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context)</td></tr>
<tr class="memdesc:gafd6cd2b1728769d406fa0bbbab1a7dd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stops an in-progress read transfer.  <a href="group__group__mtb__async__transfer.html#gafd6cd2b1728769d406fa0bbbab1a7dd7">More...</a><br /></td></tr>
<tr class="separator:gafd6cd2b1728769d406fa0bbbab1a7dd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaada97628e8ba9c95fd6f49d352869669"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#gaada97628e8ba9c95fd6f49d352869669">mtb_async_transfer_abort_write</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context)</td></tr>
<tr class="memdesc:gaada97628e8ba9c95fd6f49d352869669"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stops an in-progress write transfer.  <a href="group__group__mtb__async__transfer.html#gaada97628e8ba9c95fd6f49d352869669">More...</a><br /></td></tr>
<tr class="separator:gaada97628e8ba9c95fd6f49d352869669"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3e152b2e23e0f0571171b7487b3f224"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#gaf3e152b2e23e0f0571171b7487b3f224">mtb_async_transfer_register_callback</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context, <a class="el" href="group__group__mtb__async__transfer__function__pointers.html#gae29ede22b598970e2306b6bbbf221a12">mtb_async_transfer_event_callback_t</a> callback, void *arg)</td></tr>
<tr class="memdesc:gaf3e152b2e23e0f0571171b7487b3f224"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register a callback to be invoked when a transfer is complete.  <a href="group__group__mtb__async__transfer.html#gaf3e152b2e23e0f0571171b7487b3f224">More...</a><br /></td></tr>
<tr class="separator:gaf3e152b2e23e0f0571171b7487b3f224"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadddf2fa4b6834900cf44825fb6465520"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#gadddf2fa4b6834900cf44825fb6465520">mtb_async_transfer_process_fifo_level_event</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context, <a class="el" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a> direction)</td></tr>
<tr class="memdesc:gadddf2fa4b6834900cf44825fb6465520"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handler for when the FIFO in the peripheral reaches the trigger level.  <a href="group__group__mtb__async__transfer.html#gadddf2fa4b6834900cf44825fb6465520">More...</a><br /></td></tr>
<tr class="separator:gadddf2fa4b6834900cf44825fb6465520"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9102ce8d1c784a6fc1f55676998f3a8a"><td class="memItemLeft" align="right" valign="top">cy_rslt_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__mtb__async__transfer.html#ga9102ce8d1c784a6fc1f55676998f3a8a">mtb_async_transfer_process_dma_complete</a> (<a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *context, <a class="el" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a> direction)</td></tr>
<tr class="memdesc:ga9102ce8d1c784a6fc1f55676998f3a8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Handler for when a DMA transfer is complete.  <a href="group__group__mtb__async__transfer.html#ga9102ce8d1c784a6fc1f55676998f3a8a">More...</a><br /></td></tr>
<tr class="separator:ga9102ce8d1c784a6fc1f55676998f3a8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Function Documentation</h2>
<a id="ga44c0d4c223daff0e24eca2253c0875ff" name="ga44c0d4c223daff0e24eca2253c0875ff"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga44c0d4c223daff0e24eca2253c0875ff">&#9670;&nbsp;</a></span>mtb_async_transfer_init()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_init </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">const <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__interface__t">mtb_async_transfer_interface_t</a> *&#160;</td>
          <td class="paramname"><em>iface</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Initializes an async transfer library instance. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>Stores state that async-transfer needs to track between calls. The caller must allocate memory for this struct but should not depend on its contents. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">iface</td><td>Defines the interaction between this async-transfer instance and the peripheral that it is transferring data to/from.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>It <em>is</em> safe to free <code>iface</code> or let it go out of scope after this function returns </dd></dl>
<dl class="section return"><dt>Returns</dt><dd>the status of the initialization </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8e9f690b2c935c52fe6129fa5e968887">&#9670;&nbsp;</a></span>mtb_async_transfer_read()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_read </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>dest</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">size_t&#160;</td>
          <td class="paramname"><em>length</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reads data from the peripheral to the memory in the background. </p>
<p >If D-cache is enabled and DMA is used, the user needs to make sure that the dest pointer passed to the mtb_async_transfer_read function points to a buffer which is aligned to the cache line size (__SCB_DCACHE_LINE_SIZE). The length of buffer data must be a multiple of the cache line size to ensure cache coherency. CY_ALIGN(__SCB_DCACHE_LINE_SIZE) macro can be used for alignment.</p>
<p >Refer to <a class="el" href="index.html#DCACHE_Management">DCACHE_Management</a> for more information.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> </td></tr>
    <tr><td class="paramdir">[in,out]</td><td class="paramname">dest</td><td>Pointer to the buffer to which the data read from the peripheral should be stored. This buffer must remain valid for the duration of the transfer, and its contents should not be accessed until the read transfer is complete. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>Length, in bytes, of the data that is to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies the RX FIFO level depending on the number of bytes to receive. User is expected to set it back to the original RX FIFO level after the read is complete, if desired.</dd></dl>
<dl class="section return"><dt>Returns</dt><dd>the status of starting the read <br  />
 </dd></dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga8bc39198390d84a9b472b4aa6a8ea162">&#9670;&nbsp;</a></span>mtb_async_transfer_write()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_write </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>source</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>length</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Writes data from memory to the peripheral in the background. </p>
<p >If D-cache is enabled and DMA is used, the user needs to make sure that the source pointer passed to the mtb_async_transfer_write function points to a buffer which is aligned to the cache line size (__SCB_DCACHE_LINE_SIZE). The length of buffer data must be a multiple of the cache line size to ensure cache coherency. CY_ALIGN(__SCB_DCACHE_LINE_SIZE) macro can be used for alignment.</p>
<p >Refer to <a class="el" href="index.html#DCACHE_Management">DCACHE_Management</a> for more information.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">source</td><td>Pointer to the data that is to be written to the peripheral This buffer must remain valid for the duration of the transfer, and its contents should not be accessed until the write transfer is complete. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">length</td><td>Length, in bytes, of the data that is to be written to the peripheral</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies the TX FIFO level depending on the number of bytes to transmit. User is expected to set it back to the original TX FIFO level after the write is complete, if desired.</dd></dl>
<dl class="section return"><dt>Returns</dt><dd>the status of starting the write </dd></dl>

</div>
</div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga5a8749266d4d6510222cc14b9ae088b8">&#9670;&nbsp;</a></span>mtb_async_transfer_available_read()</h2>

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          <td class="memname">bool mtb_async_transfer_available_read </td>
          <td>(</td>
          <td class="paramtype">const <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Checks whether the async-transfer instance is available to start a read transfer. </p>
<p >An instance is available to start a read transfer if there is no read transfer currently waiting to complete</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>True if a read transfer can be started, false if there is a read transfer in progress </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1ee1eb7b2db5b01cc47cefcae27bb14d">&#9670;&nbsp;</a></span>mtb_async_transfer_available_write()</h2>

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          <td class="memname">bool mtb_async_transfer_available_write </td>
          <td>(</td>
          <td class="paramtype">const <a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Checks whether the async-transfer instance is available to start a write transfer. </p>
<p >An instance is available to start a write transfer if there is no write transfer currently waiting to complete</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>True if a write transfer can be started, false if there is a write transfer in progress </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gafd6cd2b1728769d406fa0bbbab1a7dd7">&#9670;&nbsp;</a></span>mtb_async_transfer_abort_read()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_abort_read </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stops an in-progress read transfer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the status of aborting the read </dd></dl>

</div>
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<h2 class="memtitle"><span class="permalink"><a href="#gaada97628e8ba9c95fd6f49d352869669">&#9670;&nbsp;</a></span>mtb_async_transfer_abort_write()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_abort_write </td>
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          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stops an in-progress write transfer. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> </td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This only aborts the transfer of data into the hardware FIFO. Data which was already written into the FIFO may still be written even after this function returns.</dd></dl>
<dl class="section return"><dt>Returns</dt><dd>the status of aborting the write </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf3e152b2e23e0f0571171b7487b3f224">&#9670;&nbsp;</a></span>mtb_async_transfer_register_callback()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_register_callback </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__function__pointers.html#gae29ede22b598970e2306b6bbbf221a12">mtb_async_transfer_event_callback_t</a>&#160;</td>
          <td class="paramname"><em>callback</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>arg</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Register a callback to be invoked when a transfer is complete. </p>
<dl class="section note"><dt>Note</dt><dd>For read, "complete" means that the requested amount of data has been copied into the destination buffer. For write, "complete" means that the requested amount of data has been written into the buffer in the peripheral.It does not mean that all of the data has been sent out over the communications interface. Such a status should be checked via the driver for the underlying peripheral.</dd></dl>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">callback</td><td>The callback to register. This will replace any previously registered callback. A value of <code>NULL</code> for this parameter will result in no callback being registered. </td></tr>
    <tr><td class="paramdir">[in,out]</td><td class="paramname">arg</td><td>An arbitrary pointer, which will be passed to the callback when it is invoked.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the status of registering the callback</dd></dl>
<p>Register a callback to be invoked when a transfer is complete. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gadddf2fa4b6834900cf44825fb6465520">&#9670;&nbsp;</a></span>mtb_async_transfer_process_fifo_level_event()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_process_fifo_level_event </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a>&#160;</td>
          <td class="paramname"><em>direction</em>&#160;</td>
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          <td>)</td>
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<p>Handler for when the FIFO in the peripheral reaches the trigger level. </p>
<p >The user of async-transfer must arrange for this function to be invoked (e.g. by registering an interrupt handler) when this event occurs</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">direction</td><td>The direction (read or write) in which this event occurred</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the status of handling the event </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9102ce8d1c784a6fc1f55676998f3a8a">&#9670;&nbsp;</a></span>mtb_async_transfer_process_dma_complete()</h2>

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          <td class="memname">cy_rslt_t mtb_async_transfer_process_dma_complete </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__structures.html#structmtb__async__transfer__context__t">mtb_async_transfer_context_t</a> *&#160;</td>
          <td class="paramname"><em>context</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="group__group__mtb__async__transfer__enums.html#gae10e0bbbd0c13cc5d8451a56bd23f721">mtb_async_transfer_direction_t</a>&#160;</td>
          <td class="paramname"><em>direction</em>&#160;</td>
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          <td>)</td>
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<p>Handler for when a DMA transfer is complete. </p>
<p >The user of async-transfer must arrange for this function to be invoked (e.g. by registering an interrupt handler) when this event occurs</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in,out]</td><td class="paramname">context</td><td>The context object for this peripheral that was populated by <a class="el" href="group__group__mtb__async__transfer.html#ga44c0d4c223daff0e24eca2253c0875ff">mtb_async_transfer_init</a> </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">direction</td><td>The direction (read or write) in which this event occurred</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>the status of handling the event </dd></dl>

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