sdk-csp-stm32h7/RealThread_STM32H7.yaml

---
vendor: RealThread
dvendor: STMicroelectronics
name: STM32H7
yaml_version: 2
version: 0.2.0
type: Chip_Support_Packages
family_name: STM32
series:
  description: |-
    The STM32H7 series now includes dual-core microcontrollers with Arm Cortex-M7 and Cortex-M4 cores able to run up to 480 MHz and 240 MHz respectively.
    Our single-core Cortex®-M7 STM32H7 series also benefits from this frequency increase and can now run up to 480 MHz as well.
    Dual-core STM32H7 microcontrollers are available with an embedded SMPS for improved dynamic power efficiency.

    Extended temperature range support up to 125 °C (*) (ambient) will be available for certain devices for use in harsh environments including industrial applications.

    STM32H7 devices embedding a crypto/hash processor support security services such as Secure Firmware Install and Secure Boot – Secure Firmware Upgrade allowing the installation of new application code in a secured manner.

    All the other features that have made single-core STM32H7 MCUs a success are still available in the dual-core versions.
    The STM32H7 series remains more than ever the microcontroller with an embedded Flash memory offering the highest performance on the market.
  series_name: STM32H7
  peripheral: {}
  sub_series:
  - sub_series_name: STM32H742
    cpu_info:
      max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H742AGIx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742AGIx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742AIIx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742AIIx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742BGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742BGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742BITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742BITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742IGKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742IGKx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742IGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742IGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742IIKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742IIKx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742IITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742IITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742VGHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742VGHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742VGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742VGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742VIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742VIHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742VITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742VITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742XGHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742XGHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742XIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742XIHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742ZGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742ZGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H742ZITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H742ZITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - file: documents\DM00314099.pdf
      title: STM32H742, STM32H743/753 and STM32H750 Reference Manual
    - file: documents\DS12110.pdf
      title: STM32H742xI/G STM32H743xI/G Data Sheet
    svd:
      file: debug\svd\STM32H742x.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H742xx
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h742xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h742xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00060000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00008000'
      init: '0'
      default: '1'
    - name: RAM_D2S2
      access: rwx
      start: '0x30020000'
      size: '0x00004000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  - sub_series_name: STM32H743
    cpu_info:
      max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H743AGIx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743AGIx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743AIIx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743AIIx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743BGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743BGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743BITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743BITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743IGKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743IGKx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743IGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743IGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743IIKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743IIKx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743IITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743IITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743VGHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743VGHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743VGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743VGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743VIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743VIHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743VITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743VITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743XGHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743XGHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743XIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743XIHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743ZGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743ZGTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H743ZITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H743ZITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DM00314099.pdf
      title: STM32H742, STM32H743/753 and STM32H750 Reference Manual
    - file: documents\DS12110.pdf
      title: STM32H742xI/G STM32H743xI/G Data Sheet
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    svd:
      file: debug\svd\STM32H743.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H743xx
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h743xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h743xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00048000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  - sub_series_name: STM32H753
    cpu_info:
      max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H753AIIx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753AIIx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753BITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753BITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753IIKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753IIKx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753IITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753IITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753VIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753VIHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753VITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753VITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753XIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753XIHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H753ZITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H753ZITx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - file: documents\DM00314099.pdf
      title: STM32H742, STM32H743/753 and STM32H750 Reference Manual
    - file: documents\DS12117.pdf
      title: STM32H753 Data Sheet
    svd:
      file: debug\svd\STM32H753.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H753xx
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h753xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h753xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00048000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  - sub_series_name: STM32H750
    cpu_info:
      max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H750IBKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H750IBKx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H750IBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H750IBTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H750ZBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H750ZBTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H750VBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H750VBTx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H750XBHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H750XBHx\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - file: documents\DM00314099.pdf
      title: STM32H742, STM32H743/753 and STM32H750 Reference Manual
    - file: documents\DS12556.pdf
      title: STM32H750VB STM32H750IB STM32H750XB Data Sheet
    svd:
      file: debug\svd\STM32H750x.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H750xx
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h750xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h750xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00048000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  - sub_series_name: STM32H745
    cpu_info:
    - max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM7
    - max_clock: '240000000'
      core: Cortex-M4
      fpu: SP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM4
    chips:
    - chip_name: STM32H745BGTx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745BGTx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745BGTx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745BITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745BITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745BITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745IGKx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IGKx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IGKx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745IGTx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IGTx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IGTx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745IIKx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IIKx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IIKx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745IITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745IITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745XGHx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745XGHx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745XGHx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745XIHx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745XIHx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745XIHx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745ZGTx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745ZGTx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745ZGTx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H745ZITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745ZITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H745ZITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    ui:
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM7
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM4
    docs:
    - cpu_name: CM4
      file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - cpu_name: CM4
      file: documents\DUI0553B_cortex_m4_dgug.pdf
      title: Cortex-M4 Generic User Guide
    - file: documents\DM00176879.pdf
      title: STM32H745/755 and STM32H747/757 Reference Manual
    - file: documents\DS12923.pdf
      title: STM32H745xI/G Data Sheet
    svd:
    - cpu_name: CM7
      file: debug\svd\STM32H745_CM7.svd
    - cpu_name: CM4
      file: debug\svd\STM32H745_CM4.svd
    compiler:
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H745xx
        - CORE_CM7
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h745xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h745xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM7
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H745xx
        - CORE_CM4
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h745xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h745xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM4
    memory:
    - cpu_name: CM7
      name: DTCMRAM
      access: rw
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D1
      access: rw
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D3
      access: rw
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    - cpu_name: CM4
      name: RAM_D2
      access: rw
      id: IRAM1
      start: '0x10000000'
      size: '0x00048000'
      init: '0'
      default: '1'
    project_type:
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM7
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM4
  - sub_series_name: STM32H755
    cpu_info:
    - max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM7
    - max_clock: '240000000'
      core: Cortex-M4
      fpu: SP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM4
    chips:
    - chip_name: STM32H755BITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755BITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755BITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H755IIKx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755IIKx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755IIKx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H755IITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755IITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755IITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H755XIHx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755XIHx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755XIHx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H755ZITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755ZITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H755ZITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    ui:
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM7
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM4
    docs:
    - cpu_name: CM4
      file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - cpu_name: CM4
      file: documents\DUI0553B_cortex_m4_dgug.pdf
      title: Cortex-M4 Generic User Guide
    - file: documents\DM00176879.pdf
      title: STM32H745/755 and STM32H747/757 Reference Manual
    - file: documents\DS12919.pdf
      title: STM32H755xI Data Sheet
    svd:
    - cpu_name: CM7
      file: debug\svd\STM32H755_CM7.svd
    - cpu_name: CM4
      file: debug\svd\STM32H755_CM4.svd
    compiler:
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H755xx
        - CORE_CM7
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h755xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h755xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM7
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H755xx
        - CORE_CM4
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h755xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h755xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM4
    memory:
    - cpu_name: CM7
      name: DTCMRAM
      access: rw
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D1
      access: rw
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D3
      access: rw
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    - cpu_name: CM4
      name: RAM_D2
      access: rw
      id: IRAM1
      start: '0x10000000'
      size: '0x00030000'
      init: '0'
      default: '1'
    - cpu_name: CM4
      name: RAM_D2S3
      access: rw
      id: IRAM2
      start: '0x10040000'
      size: '0x00008000'
      init: '0'
      default: '1'
    project_type:
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM7
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM4
  - sub_series_name: STM32H747
    cpu_info:
    - max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM7
    - max_clock: '240000000'
      core: Cortex-M4
      fpu: SP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM4
    chips:
    - chip_name: STM32H747AGIx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747AGIx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747AGIx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747AIIx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747AIIx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747AIIx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747BGTx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747BGTx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747BGTx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747BITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747BITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747BITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747IGTx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747IGTx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747IGTx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747IITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747IITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747IITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747XGHx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747XGHx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747XGHx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747XIHx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747XIHx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747XIHx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H747ZIYx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747ZIYx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H747ZIYx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    ui:
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM7
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM4
    docs:
    - cpu_name: CM4
      file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - cpu_name: CM4
      file: documents\DUI0553B_cortex_m4_dgug.pdf
      title: Cortex-M4 Generic User Guide
    - file: documents\DM00176879.pdf
      title: STM32H745/755 and STM32H747/757 Reference Manual
    - file: documents\DS12930.pdf
      title: STM32H747xI/G Data Sheet
    svd:
    - cpu_name: CM7
      file: debug\svd\STM32H747_CM7.svd
    - cpu_name: CM4
      file: debug\svd\STM32H747_CM4.svd
    compiler:
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H747xx
        - CORE_CM7
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h747xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h747xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM7
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H747xx
        - CORE_CM4
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h747xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h747xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM4
    memory:
    - cpu_name: CM7
      name: DTCMRAM
      access: rw
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D1
      access: rw
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D3
      access: rw
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    - cpu_name: CM4
      id: IRAM1
      start: '0x10000000'
      size: '0x00048000'
      init: '0'
      default: '1'
    project_type:
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM7
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM4
  - sub_series_name: STM32H757
    cpu_info:
    - max_clock: '480000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM7
    - max_clock: '240000000'
      core: Cortex-M4
      fpu: SP_FPU
      mpu: MPU
      endian: Little-endian
      cpu_name: CM4
    chips:
    - chip_name: STM32H757AIIx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757AIIx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757AIIx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H757BITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757BITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757BITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H757IITx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757IITx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757IITx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H757XIHx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757XIHx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757XIHx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    - chip_name: STM32H757ZIYx
      peripheral: {}
      memory:
      - cpu_name: CM7
        name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00100000'
        default: '1'
      - cpu_name: CM4
        name: FLASH_Bank2
        access: rx
        id: IROM1
        start: '0x08100000'
        size: '0x00100000'
        default: '1'
      compiler:
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757ZIYx\CM7\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM7
      - gcc:
          entry_point: entry
          link_script: linkscripts\STM32H757ZIYx\CM4\link.lds
          marco: []
          files: []
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        cpu_name: CM4
    ui:
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM7
    - uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
      cpu_name: CM4
    docs:
    - cpu_name: CM4
      file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - cpu_name: CM4
      file: documents\DUI0553B_cortex_m4_dgug.pdf
      title: Cortex-M4 Generic User Guide
    - file: documents\DM00176879.pdf
      title: STM32H745/755 and STM32H747/757 Reference Manual
    - file: documents\DS12931.pdf
      title: STM32H757xI Data Sheet
    svd:
    - cpu_name: CM7
      file: debug\svd\STM32H757_CM7.svd
    - cpu_name: CM4
      file: debug\svd\STM32H757_CM4.svd
    compiler:
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H757xx
        - CORE_CM7
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h757xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h757xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM7
    - gcc:
        entry_point: none
        link_script: none
        marco:
        - STM32H757xx
        - CORE_CM4
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h757xx.S
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h757xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      cpu_name: CM4
    memory:
    - cpu_name: CM7
      name: DTCMRAM
      access: rw
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D1
      access: rw
      id: IRAM2
      start: '0x24000000'
      size: '0x00080000'
      init: '0'
      default: '1'
    - cpu_name: CM7
      name: RAM_D3
      access: rw
      start: '0x38000000'
      size: '0x00010000'
      init: '0'
      default: '1'
    - cpu_name: CM4
      name: RAM_D2
      access: rw
      id: IRAM1
      start: '0x10000000'
      size: '0x00030000'
      init: '0'
      default: '1'
    - cpu_name: CM4
      name: RAM_D2S3
      access: rw
      id: IRAM2
      start: '0x10040000'
      size: '0x00008000'
      init: '0'
      default: '1'
    project_type:
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM7
    - bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
      cpu_name: CM4
  - sub_series_name: STM32H7A3
    cpu_info:
      max_clock: '280000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H7A3IIKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IIKx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IIKxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IIKxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IITx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IITxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IITxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3NIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3NIHx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3RITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3RITx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VITx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VITxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VITxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VIHx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VIHxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VIHxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3ZITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3ZITx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3ZITxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3ZITxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3QIYxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3QIYxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3LIHxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3LIHxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3AIIxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3AIIxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3ZGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3ZGTx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3ZGTxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3ZGTxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3NGHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3NGHx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VGHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VGHx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VGHxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VGHxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VGTx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3VGTxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3VGTxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3RGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3RGTx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3LGHxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3LGHxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IGKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IGKx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IGKxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IGKxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IGTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IGTx\link.lds
          marco:
          - STM32H7A3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3IGTxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3IGTxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7A3AGIxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00080000'
        default: '1'
      - name: FLASH_Bank2
        access: rx
        id: IROM2
        start: '0x08100000'
        size: '0x00080000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7A3AGIxQ\link.lds
          marco:
          - STM32H7A3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7a3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7a3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - file: documents\DM00463927.pdf
      title: STM32H7A3/B3 and STM32H7B0 Value line Reference Manual
    - file: documents\DS13195.pdf
      title: STM32H7A3xI/G Data Sheet
    svd:
      file: debug\svd\STM32H7A3x.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco: []
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00100000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00008000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  - sub_series_name: STM32H7B3
    cpu_info:
      max_clock: '280000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H7B3AIIxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3AIIxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3LIHxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3LIHxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3IIKx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3IIKx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3IIKxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3IIKxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3IITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3IITx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3IITxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3IITxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3NIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3NIHx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3RITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3RITx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3VITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3VITx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3VITxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3VITxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3VIHx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3VIHx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3VIHxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3VIHxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3ZITx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3ZITx\link.lds
          marco:
          - STM32H7B3xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3ZITxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3ZITxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B3QIYxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00200000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B3QIYxQ\link.lds
          marco:
          - STM32H7B3xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b3xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b3xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - file: documents\DM00463927.pdf
      title: STM32H7A3/B3 and STM32H7B0 Value line Reference Manual
    - file: documents\DS13139.pdf
      title: STM32H7B3xI/G Data Sheet
    svd:
      file: debug\svd\STM32H7B3x.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco: []
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00100000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00008000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  - sub_series_name: STM32H7B0
    cpu_info:
      max_clock: '280000000'
      core: Cortex-M7
      fpu: DP_FPU
      mpu: MPU
      endian: Little-endian
    chips:
    - chip_name: STM32H7B0RBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B0RBTx\link.lds
          marco:
          - STM32H7B0xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b0xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b0xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B0VBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B0VBTx\link.lds
          marco:
          - STM32H7B0xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b0xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b0xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B0ZBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B0ZBTx\link.lds
          marco:
          - STM32H7B0xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b0xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b0xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B0IBTx
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B0IBTx\link.lds
          marco:
          - STM32H7B0xx
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b0xx.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b0xx.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B0IBKxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B0IBKxQ\link.lds
          marco:
          - STM32H7B0xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b0xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b0xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    - chip_name: STM32H7B0ABIxQ
      peripheral: {}
      memory:
      - name: FLASH_Bank1
        access: rx
        id: IROM1
        start: '0x08000000'
        size: '0x00020000'
        default: '1'
      compiler:
        gcc:
          entry_point: entry
          link_script: linkscripts\STM32H7B0ABIxQ\link.lds
          marco:
          - STM32H7B0xxQ
          files:
          - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\gcc\startup_stm32h7b0xxq.S
          - libraries\CMSIS\Lib\GCC
          - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7b0xxq.h
        armcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
        iarcc:
          entry_point: none
          link_script: none
          marco: []
          files: []
    ui:
      uart:
        default_value: UART3
        prompt_message_en: select one uart as console output interface
        prompt_message_zh: 选择一个串口作为控制台信息输出接口
      tx_pin:
        default_value: PD8
        prompt_message_en: 'set the tx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]",eg. PD8,PB6 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称, 名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8,
          PB6
      rx_pin:
        default_value: PD9
        prompt_message_en: 'set the rx pin name of the console device interface, the
          value should be with a format"P+[port name][pin number]", eg. PD9, PB7 '
        prompt_message_zh: 设置控制台设备的数据发送引脚的名称，名称应该具有以下格式“P+[端口名称][端口编号]”, 比如：PD8, PB6
    docs:
    - file: documents\DUI0646B_cortex_m7_dgug.pdf
      title: Cortex-M7 Generic User Guide
    - file: documents\DM00463927.pdf
      title: STM32H7A3/B3 and STM32H7B0 Value line Reference Manual
    - file: documents\DS13196.pdf
      title: STM32H7B0xB Data Sheet
    svd:
      file: debug\svd\STM32H7B0x.svd
    compiler:
      gcc:
        entry_point: none
        link_script: none
        marco: []
        files:
        - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h
        - libraries\CMSIS\Lib\GCC
      armcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
      iarcc:
        entry_point: none
        link_script: none
        marco: []
        files: []
    memory:
    - name: DTCMRAM
      access: rwx
      id: IRAM1
      start: '0x20000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D1
      access: rwx
      id: IRAM2
      start: '0x24000000'
      size: '0x00100000'
      init: '0'
      default: '1'
    - name: RAM_D2
      access: rwx
      start: '0x30000000'
      size: '0x00020000'
      init: '0'
      default: '1'
    - name: RAM_D3
      access: rwx
      start: '0x38000000'
      size: '0x00008000'
      init: '0'
      default: '1'
    project_type:
      bare_metal:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          sysTick: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\baremetal
      rtt_nano:
        function_map:
          clk_init: none
          uart_init: none
          putc: none
          getc: none
          sysTick: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\nano
      rtt:
        function_map:
          rt_hw_board_init;: none
          rt_hw_serial_register: none
          rt_hw_pin_register: none
          heap_init: none
        marco:
        - SOC_FAMILY_STM32
        - SOC_SERIES_STM32H7
        - USE_HAL_DRIVER
        source_files:
        - drivers\rtt
  docs: {}
  source_files:
    file:
    - libraries\STM32H7xx_HAL_Driver
    - libraries\CMSIS\Include
    - libraries\CMSIS\RTOS
    - libraries\CMSIS\Device\ST\STM32H7xx\Source\Templates\system_stm32h7xx.c
    - libraries\CMSIS\Device\ST\STM32H7xx\Include\stm32h7xx.h
    - libraries\CMSIS\Device\ST\STM32H7xx\Include\system_stm32h7xx.h
  boards:
  - bversion: Rev.B
    board_name: STM32H743I-EVAL
    sub_series_name: STM32H743
    chip_name: STM32H743XIHx
    bvendor: STMicroelectronics
    description: STMicroelectronics STM32H743I-EVAL Evaluation Board Support and Examples
    small_image: documents\boards\stm32h743i-eval_small.png
    big_image: documents\boards\stm32h743i-eval_large.png
    sale_contact: http://www.st.com/stonline/contactus/contacts/index.php
    buy_url: taobao.com
    rx_name: PA10
    tx_name: PA9
    clock_source: HSE
    source_freq: '8000000'
    target_freq: '240000000'
    uart_name: UART1
    debugger: ST-LINK
    debug_interface: SWD
    docs:
    - file: documents\boards\stm32h743i-eval.pdf
      title: Data brief
      category: manual
    - file: documents\boards\stm32h743i-eval_gerber.zip
      title: Gerber Files
      category: other
    board_info:
    - name: ''
      value: On-board ST-LINK/V2
    - name: ''
      value: 8M x 32-bit SDRAM
    - name: ''
      value: 1M x 16-bit SRAM
    - name: ''
      value: 8M x 16-bit Nor Flash
    - name: ''
      value: 512-Mbit Quad-SPI NOR Flash
    - name: ''
      value: Extensionheader2x33with2.54mmPitch
    - name: ''
      value: 10/100 Ethernet Port
    - name: On-board button number
      value: '2'
    - name: On-board LED number
      value: '4'
    - name: ''
      value: 4-inch 800x480 TFT color LCD with capacitive touch panel
    examples:
    - name: Blink
      description: example 1
      project: none
    - name: Echo
      description: example 2
      project: none
  - bversion: Rev.ES
    board_name: STM32H747I-EVAL
    sub_series_name: STM32H747
    chip_name: STM32H747XIHx
    bvendor: STMicroelectronics
    description: STMicroelectronics STM32H747I-EVAL Evaluation Board Support and Examples
    small_image: documents\boards\stm32h747i-eval_small.jpg
    big_image: documents\boards\stm32h747i-eval_large.jpg
    sale_contact: http://www.st.com/stonline/contactus/contacts/index.php
    buy_url: taobao.com
    rx_name: PA10
    tx_name: PA9
    clock_source: HSE
    source_freq: '8000000'
    target_freq: '240000000'
    uart_name: UART1
    debugger: ST-LINK
    debug_interface: SWD
    docs:
    - file: documents\boards\stm32h747i-eval.pdf
      title: STM32H747I_EVAL Data Brief
      category: manual
    board_info:
    - name: ''
      value: On-board ST-LINK/V2
    - name: ''
      value: 8M x 32-bit SDRAM
    - name: ''
      value: 1M x 16-bit SRAM
    - name: ''
      value: 8M x 16-bit Nor Flash
    - name: ''
      value: 1-Gbit Twin Quad-SPI or two 512-Mbit Quad-SPI NOR Flash memories
    - name: ''
      value: Extensionheader2x33with2.54mmPitch
    - name: ''
      value: 10/100 Ethernet Port
    - name: On-board button number
      value: 3 , Push-Buttons for Reset, Wakeup/Tamper or Key
    - name: On-board LED number
      value: '4'
    - name: ''
      value: 4-inch 800x480 TFT color LCD with MIPI DSI interface and capacitive touchpanel
    examples:
    - name: Blink
      description: example 1
      project: none
    - name: Echo
      description: example 2
      project: none
  - bversion: Rev.A
    board_name: STM32H7B3I-EVAL
    sub_series_name: STM32H7B3
    chip_name: STM32H7B3LIHxQ
    bvendor: STMicroelectronics
    description: STMicroelectronics STM32H7B3I-EVAL Evaluation Board Support and Examples
    small_image: documents\boards\stm32h7b3i-eval_small.png
    big_image: documents\boards\stm32h7b3i-eval_large.png
    sale_contact: http://www.st.com/stonline/contactus/contacts/index.php
    buy_url: taobao.com
    rx_name: PA10
    tx_name: PA9
    clock_source: HSE
    source_freq: '8000000'
    target_freq: '240000000'
    uart_name: UART1
    debugger: ST-LINK
    debug_interface: SWD
    docs:
    - file: documents\boards\stm32h747i-eval.pdf
      title: STM32H747I_EVAL Data Brief
      category: manual
    board_info:
    - name: ''
      value: On-board ST-LINK/V3E
    - name: ''
      value: 8M x 32-bit SDRAM
    - name: ''
      value: 1M x 16-bit SRAM
    - name: ''
      value: 8M x 16-bit Nor Flash
    - name: ''
      value: 512-Mbit Octal-SPI NOR Flash
    - name: ''
      value: Extensionheader2x33with2.54mmPitch
    - name: ''
      value: 10/100 Ethernet Port
    - name: On-board button number
      value: 3 , Push-Buttons for Reset, Wakeup, Tamper
    - name: On-board LED number
      value: '4'
    - name: GLCD
      value: 4-inch 800x480 TFT color LCD with MIPI DSI interface and capacitive touchpanel
    - name: MIC
      value: 2 ST MEMS microphones
    examples:
    - name: Blink
      description: example 1
      project: none
    - name: Echo
      description: example 2
      project: none