【增加】版本控制

Signed-off-by: armink <armink.ztl@gmail.com>

ST-LINK_gdbserver.bat

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+@echo off
+cmd /K "ST-LINK_gdbserver.exe -c config.txt || echo GDB server exited"

config.txt

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+###############################################################
+#### ST-LINK_gdbserver - Sample Configuration File
+#### Each Line Contains one argument
+#### Comment lines begin with #
+####
+#### Use option -c <config-file> to start with config file
+####  ST-LINK_gdbserver -c config.txt
+####
+#### Using STM32F4_Discovery, 168MHz, SWO Clock 1000 MHz.
+####  ST-LINK_gdbserver.exe -e -d -z 61235 -a 168000000 -b 168
+####
+#### Programming elf file
+####  ST-LINK_gdbserver.exe -e -d -j C:\dev\workspace\MyProg\Debug\MyProg.elf
+####
+#### Get option information
+####  ST-LINK_gdbserver.exe -h
+####
+###############################################################
+
+###############################################################
+#  -e                 : Enables persistant mode
+###############################################################
+-e
+
+###############################################################
+#  -f <Log-File>      : Name of log file. Please make sure
+#                       that directory not is write protected.
+#                     : Example
+-f debug.log
+###############################################################
+
+###############################################################
+#  -l <Log-Level>     : Logging level between 0 & 31
+#          0            Disables logging
+#          >=1          Enables logging of error messages
+#          >=2          Adds warning messages
+#          >=4          Adds communication specific messages
+#          >=8          Adds all information messages
+#          >=16         Adds all HW specific messages
+###############################################################
+#-l 31
+
+###############################################################
+#  -p <Port-Number>   : TCP-Listen Port-Number.
+###############################################################
+-p 61234
+
+###############################################################
+#  -v                 : Enables verbose mode
+###############################################################
+#-v
+
+###############################################################
+#  -r <delay-sec>     : Maximum Delay in status refresh
+###############################################################
+-r 15
+
+###############################################################
+# -d                  : Enables SWD mode
+###############################################################
+-d

tools/Data_Base/STM32_Prog_DB.xml

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+<?xml version="1.0" encoding="UTF-8"?>
+<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
+
+<!-- Device: 0x483 -->
+	<Device>
+		<DeviceID>0x483</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M7</CPU>
+		<Name>STM32H723xx/STM32H725xx</Name>
+		<Series>STM32H7</Series>
+		<Description>ARM 32-bit Cortex-M7 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- Security extension available -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+					</SecurityEx>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- Security extension not available -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+					</SecurityEx>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
+					<Dummy>
+						<ReadRegister address="0x08000000"	mask="0x0"	value="0x0"/>
+					</Dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1024 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x20000" address="0x24000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x20000" address="0x24000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF1E880" default="0x100000"/>
+				<!-- 1MB Single Bank -->
+				<Configuration config="0,1">
+					<Parameters name="1 MBytes Single Bank Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x20000" address="0x08000000"	occurence="0x8"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x134" address="0x5200201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR OFF</Val>
+										<Val value="0x1">BOR level1: 2.1V</Val>
+										<Val value="0x2">BOR level2: 2.4 V</Val>
+										<Val value="0x3">BOR level3: 2.7 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">reset level is set to 0.0 V</Val>
+										<Val value="0x1">reset level is set to 2.1 V</Val>
+										<Val value="0x2">reset level is set to 2.4 V</Val>
+										<Val value="0x3">reset level is set to 2.7 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG1_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IO_HSLV</Name>
+									<Description/>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
+										<Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
+										<Val value="0x1">Independent watchdog is running in STOP mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_SDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
+										<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
+									</Values>
+								</Bit>
+								<Bit	config="0,1">
+									<Name>SECURITY</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security feature disabled</Val>
+										<Val value="0x1">Security feature enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG1_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IO_HSLV</Name>
+									<Description/>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Product working in the full voltage range, I/O speed optimization at low-voltage disabled</Val>
+										<Val value="0x1">Product operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
+										<Val value="0x1">Independent watchdog is running in STOP mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_SDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
+										<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
+									</Values>
+								</Bit>
+								<Bit	config="0,1,2,4,6">
+									<Name>SECURITY</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Security feature disabled</Val>
+										<Val value="0x1">Security feature enabled</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>SWAP_BANK_OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">after boot loading, no swap for user sectors</Val>
+										<Val value="0x1">after boot loading, user sectors swapped</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FBOOT7_CUR" size="0x4" address="0x52002040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_CM7_ADD0</Name>
+									<Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_CM7_ADD1</Name>
+									<Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FBOOT7_PRG" size="0x4" address="0x52002044"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_CM7_ADD0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_CM7_ADD1</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FPRAR_CUR_A" size="0x4" address="0x52002028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START</Name>
+									<Description>Flash Bank PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END</Name>
+									<Description>Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_PRG_A" size="0x4" address="0x5200202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START</Name>
+									<Description>Flash Bank PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END</Name>
+									<Description>Flash Bank PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Protection</Name>
+						<Field>
+							<Parameters name="FSCAR_CUR_A" size="0x4" address="0x52002030"/>
+							<AssignedBits>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_START1</Name>
+									<Description>Flash Bank 1 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_END1</Name>
+									<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>DMES1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_PRG_A" size="0x4" address="0x52002034"/>
+							<AssignedBits>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_START1</Name>
+									<Description>Flash Bank 1 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_END1</Name>
+									<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>DMES1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_CUR_B" size="0x4" address="0x52002130"/>
+							<AssignedBits>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_START2</Name>
+									<Description>Flash Bank 2 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_END2</Name>
+									<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>DMES2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_PRG_B" size="0x4" address="0x52002134"/>
+							<AssignedBits>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_START2</Name>
+									<Description>Flash Bank 2 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_END2</Name>
+									<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>DMES2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>DTCM RAM Protection</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ST_RAM_SIZE</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">2  KB reserved to ST code</Val>
+										<Val value="0x1">4  KB reserved to ST code</Val>
+										<Val value="0x2">8  KB reserved to ST code</Val>
+										<Val value="0x3">16 KB reserved to ST code</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ST_RAM_SIZE</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">2  KB reserved to ST code</Val>
+										<Val value="0x1">4  KB reserved to ST code</Val>
+										<Val value="0x2">8  KB reserved to ST code</Val>
+										<Val value="0x3">16 KB reserved to ST code</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FWPSN_CUR_A" size="0x4" address="0x52002038"/>
+							<AssignedBits>
+								<Bit config="0,1">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_PRG_A" size="0x4" address="0x5200203C"/>
+							<AssignedBits>
+								<Bit config="0,1">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>TCM_AXI Shared Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTSR2_CUR" size="0x4" address="0x52002070"/>
+							<AssignedBits>
+								<Bit>
+									<Name>TCM_AXI_SHARED_CFG</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">64 KB ITCM : 320KB system AXI</Val>
+										<Val value="0x1">128KB ITCM : 256KB system AXI</Val>
+										<Val value="0x2">192KB ITCM : 192KB system AXI</Val>
+										<Val value="0x3">256KB ITCM : 128KB system AXI</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>CPU_FREQ_BOOST</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Feature disabled</Val>
+										<Val value="0x1">CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM)</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTSR2_PRG" size="0x4" address="0x52002074"/>
+							<AssignedBits>
+								<Bit>
+									<Name>TCM_AXI_SHARED_CFG</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+							        <Values>
+										<Val value="0x0">64KB ITCM : 320KB system AXI</Val>
+										<Val value="0x1">128KB ITCM : 256KB system AXI</Val>
+										<Val value="0x2">192KB ITCM : 192KB system AXI</Val>
+										<Val value="0x3">256KB ITCM : 128KB system AXI</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>CPU_FREQ_BOOST</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Feature disabled</Val>
+										<Val value="0x1">CPU can operate at a boosted Fmax frequency (no more ECC on I/DTCM)</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	<!-- Device: 0x496  -->
+	<Device>
+		<DeviceID>0x496</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+/M4</CPU>
+		<Name>STM32WB35xx</Name>
+		<Series>STM32WB</Series>
+		<Description>ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 192 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x80000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 128 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 128 Bytes Data MirrorOptionBytes" size="0x80" address="0x1FFF8000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x80" address="0x1FFF8000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x58004020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from code area if BOOT0=0 otherwise system Flash</Val>
+										<Val value="0x1">Boot from code area if BOOT0=0 otherwise embedded SRAM</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Stop mode</Val>
+										<Val value="0x1">No reset generated when entering the Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Standby mode</Val>
+										<Val value="0x1">No reset generated when entering the Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRSTSHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDGSW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWGDSTDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSTOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independent watchdog</Val>
+										<Val value="0x1">Software independent watchdog</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_IPCCBR" size="0x4" address="0x5800403C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IPCCDBA</Name>
+									<Description>IPCC mailbox data buffer base address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Security Configuration Option bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ESE</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security disabled</Val>
+										<Val value="0x1">Security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SFR" size="0x4" address="0x58004080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SFSA</Name>
+									<Description>Secure Flash start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FSD</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">System and Flash secure</Val>
+										<Val value="0x1">System and Flash non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DDS</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 debug access enabled</Val>
+										<Val value="0x1">CPU2 debug access disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SRRVR" size="0x4" address="0x58004084"/>
+							<AssignedBits>
+								<Bit>
+									<Name>C2OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SBRV will address SRAM2</Val>
+										<Val value="0x1">SBRV will address Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NBRSD</Name>
+									<Description>If FSD=1 : SRAM2b is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2b is secure</Val>
+										<Val value="0x1">SRAM2b is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SNBRSA</Name>
+									<Description>SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BRSD</Name>
+									<Description>If FSD=1 : SRAM2a is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2a is secure</Val>
+										<Val value="0x1">SRAM2a is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SBRSA</Name>
+									<Description>SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SBRV</Name>
+									<Description>Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="PCROP1ASR" size="0x4" address="0x58004024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1AER" size="0x4" address="0x58004028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BSR" size="0x4" address="0x58004034"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BER" size="0x4" address="0x58004038"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x5800402C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x58004030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x80" address="0x1FFF8000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from code area if BOOT0=0 otherwise system Flash</Val>
+										<Val value="0x1">Boot from code area if BOOT0=0 otherwise embedded SRAM</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Stop mode</Val>
+										<Val value="0x1">No reset generated when entering the Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Standby mode</Val>
+										<Val value="0x1">No reset generated when entering the Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRSTSHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDGSW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWGDSTDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSTOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independent watchdog</Val>
+										<Val value="0x1">Software independent watchdog</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_IPCCBR" size="0x4" address="0x1FFF8068"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IPCCDBA</Name>
+									<Description>IPCC mailbox data buffer base address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Security Configuration Option bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ESE</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security disabled</Val>
+										<Val value="0x1">Security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SFR" size="0x4" address="0x1FFF8070"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SFSA</Name>
+									<Description>Secure Flash start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FSD</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">System and Flash secure</Val>
+										<Val value="0x1">System and Flash non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DDS</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 debug access enabled</Val>
+										<Val value="0x1">CPU2 debug access disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SRRVR" size="0x4" address="0x1FFF8078"/>
+							<AssignedBits>
+								<Bit>
+									<Name>C2OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SBRV will address SRAM2</Val>
+										<Val value="0x1">SBRV will address Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NBRSD</Name>
+									<Description>If FSD=1 : SRAM2b is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2b is secure</Val>
+										<Val value="0x1">SRAM2b is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SNBRSA</Name>
+									<Description>SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BRSD</Name>
+									<Description>If FSD=1: SRAM2a is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2a is secure</Val>
+										<Val value="0x1">SRAM2a is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SBRSA</Name>
+									<Description>SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SBRV</Name>
+									<Description>Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x12</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="PCROP1ASR" size="0x4" address="0x1FFF8008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1AER" size="0x4" address="0x1FFF8010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BSR" size="0x4" address="0x1FFF8028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BER" size="0x4" address="0x1FFF8030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF8018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF8020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+		<!-- Device: 0x469 -->
+	<Device>
+		<DeviceID>0x469</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32G47x/G48x</Name>
+		<Series>STM32G4</Series>
+		<Description>Category 3 devices, ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">	
+						<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x1">	
+						<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x2">	
+					<dummy> <ReadRegister address="0x20000000"	mask="0" value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">	
+					<DBANK reference="0x0"> <ReadRegister address="0x1FFF7800"	mask="0x10000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x1">	
+					<DBANK reference="0x1"> <ReadRegister address="0x1FFF7800"	mask="0x10000"	value="0x10000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x2">	
+					<dummy> <ReadRegister address="0x20000000"	mask="0" value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x18000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x18000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x80000"/>
+				<!-- 1MB dual Bank -->
+				<Configuration config="0">  <!-- single Bank -->
+					<Parameters name=" 512 Kbyte Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1,2"> <!-- dual Bank -->
+					<Parameters name=" 512 Kbyte Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x08040000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 64 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 64 Bytes Data MirrorOptionBytes" size="0x40" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x24" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x1C" address="0x1FFFF808"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, no debug</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit reference="DualBank">
+									<Name>DBANK</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description>SRAM1 and CCM SRAM parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM1 and CCM SRAM parity check enable</Val>
+										<Val value="0x1">SRAM1 and CCM SRAM parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>CCMSRAM_RST</Name>
+									<Description>CCM SRAM Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CCM SRAM erased when a system reset occurs</Val>
+										<Val value="0x1">CCM SRAM is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PB8/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description></Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000008"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x40022044"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000008"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08040008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x40022050"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+				<Parameters name="Bank 3" size="0x8" address="0x40022070"/>
+					<Category>
+						<Name>Secure Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_SECR1" size="0x4" address="0x40022070"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SEC_SIZE1</Name>
+									<Description>sets the number of pages used in the bank 1 securable area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>Unique boot entry point</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.</Val>
+										<Val value="0x1">the boot will be done from user flash only, whatever the RDP level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_SECR2" size="0x4" address="0x40022074"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SEC_SIZE2</Name>
+									<Description>sets the number of pages used in the bank 2 securable area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, no debug</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit reference="DualBank">
+									<Name>DBANK</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description>SRAM1 and CCM SRAM parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM1 and CCM SRAM parity check enable</Val>
+										<Val value="0x1">SRAM1 and CCM SRAM parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>CCMSRAM_RST</Name>
+									<Description>CCM SRAM Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CCM SRAM erased when a system reset occurs</Val>
+										<Val value="0x1">CCM SRAM is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PB8/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description></Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000008"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SECR1" size="0x4" address="0x1FFF7828"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SEC_SIZE1</Name>
+									<Description>sets the number of pages used in the bank 1 securable area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>Unique boot entry point</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.</Val>
+										<Val value="0x1">the boot will be done from user flash only, whatever the RDP level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x1C" address="0x1FFFF808"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x1FFFF810"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08080008"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x1FFFF818"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x1FFFF820"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="0">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="1,2">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Protection</Name>
+						<Field>
+							<Parameters name="FLASH_SECR2" size="0x4" address="0x1FFFF828"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SEC_SIZE2</Name>
+									<Description>sets the number of pages used in the bank 2 securable area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+<!-- Device: 0x468 -->
+	<Device>
+		<DeviceID>0x468</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32G43x/G44x</Name>
+		<Series>STM32G4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x5000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x5000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x20000"/>
+				<!-- 1MB dual Bank -->
+				<Configuration>  <!-- single Bank -->
+					<Parameters name=" 128 Kbyte Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 36 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 36 Bytes Data MirrorOptionBytes" size="0x54" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x54" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, no debug</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description>SRAM1 and CCM SRAM parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM1 and CCM SRAM parity check enable</Val>
+										<Val value="0x1">SRAM1 and CCM SRAM parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>CCMSRAM_RST</Name>
+									<Description>CCM SRAM Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CCM SRAM erased when a system reset occurs</Val>
+										<Val value="0x1">CCM SRAM is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PB8/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description></Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+				<Parameters name="Bank 2" size="0x4" address="0x40022070"/>
+					<Category>
+						<Name>Secure Protection</Name>
+						<Field>
+							<Parameters name="FLASH_SECR1" size="0x4" address="0x40022070"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SEC_SIZE1</Name>
+									<Description>sets the number of pages used in the bank 1 securable area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>Unique boot entry point</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.</Val>
+										<Val value="0x1">the boot will be done from user flash only, whatever the RDP level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, no debug</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description>SRAM1 and CCM SRAM parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM1 and CCM SRAM parity check enable</Val>
+										<Val value="0x1">SRAM1 and CCM SRAM parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>CCMSRAM_RST</Name>
+									<Description>CCM SRAM Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CCM SRAM erased when a system reset occurs</Val>
+										<Val value="0x1">CCM SRAM is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PB8/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description></Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x4" address="0x1FFF7828"/>
+					<Category>
+						<Name>Secure Protection</Name>
+						<Field>
+							<Parameters name="FLASH_SECR1" size="0x4" address="0x1FFF7828"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SEC_SIZE1</Name>
+									<Description>sets the number of pages used in the bank 1 securable area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>Unique boot entry point</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">This bit can be reset by SW only in level0. In level 1, an RDP level regression will reset this bit, which will force a mass erase of the flash.</Val>
+										<Val value="0x1">the boot will be done from user flash only, whatever the RDP level</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+<!-- Device: 0x497  -->
+	<Device>
+		<DeviceID>0x497</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+/M4</CPU>
+		<Name>STM32WLxx</Name>
+		<Series>STM32WL</Series>
+		<Description>ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 192 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x40000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x40</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 104 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 104 Bytes Data MirrorOptionBytes" size="0x68" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x68" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x58004020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from code area if BOOT0=0 otherwise system Flash</Val>
+										<Val value="0x1">Boot from code area if BOOT0=0 otherwise embedded SRAM</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Stop mode</Val>
+										<Val value="0x1">No reset generated when entering the Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Standby mode</Val>
+										<Val value="0x1">No reset generated when entering the Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRSTSHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDGSW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWGDSTDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSTOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independent watchdog</Val>
+										<Val value="0x1">Software independent watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>C1BOOTLOCK</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU1 CM4 Unique Boot entry lock disabled</Val>
+										<Val value="0x1">CPU1 CM4 Unique Boot entry lock enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>C2BOOTLOCK</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 CM0+ Unique Boot entry lock disabled</Val>
+										<Val value="0x1">CPU2 CM0+ Unique Boot entry lock enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_IPCCBR" size="0x1" address="0x5800403C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IPCCDBA</Name>
+									<Description>IPCC mailbox data buffer base address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Security Configuration Option bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ESE</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Security disabled</Val>
+										<Val value="0x1">Security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SFR" size="0x4" address="0x58004080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SFSA</Name>
+									<Description>This bit can only be accessed by software when HDPADIS = 0. When FSD=0: system and Flash secure. SFSA[6:0] contain the start address of the first 2 kB page of the secure Flash area.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FSD</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">System and Flash secure</Val>
+										<Val value="0x1">System and Flash non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DDS</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 debug access enabled</Val>
+										<Val value="0x1">CPU2 debug access disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SHDPSA</Name>
+									<Description>SHDPSA[6:0] contain the start address of the first 2 kB page of the User Flash Sticky hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash Sticky hide protection area enabled.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>HDPAD</Name>
+									<Description>User Flash Sticky hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									
+								</Bit>
+								<Bit>
+									<Name>SPI3SD</Name>
+									<Description>SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">FSD=0 and SPI3SD=0: SPI3 security enabled</Val>
+										<Val value="0x1">FSD=0 and SPI3SD=1: SPI3 security disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SRRVR" size="0x4" address="0x58004084"/>
+							<AssignedBits>
+								<Bit>
+									<Name>C2OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SBRV will address SRAM2</Val>
+										<Val value="0x1">SBRV will address Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NBRSD</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2b is secure if FSD=0 and non-secure otherwise</Val>
+										<Val value="0x1">SRAM2b is non-secure if FSD=0 and secure otherwise</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SNBRSA</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BRSD</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2a is secure if FSD=0 and non-secure otherwise</Val>
+										<Val value="0x1">SRAM2b is non-secure if FSD=0 and secure otherwise</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SBRSA</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SBRV</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="PCROP1ASR" size="0x4" address="0x58004024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1AER" size="0x4" address="0x58004028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BSR" size="0x4" address="0x58004034"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BER" size="0x4" address="0x58004038"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x5800402C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x58004030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x68" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from code area if BOOT0=0 otherwise system Flash</Val>
+										<Val value="0x1">Boot from code area if BOOT0=0 otherwise embedded SRAM</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Stop mode</Val>
+										<Val value="0x1">No reset generated when entering the Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Standby mode</Val>
+										<Val value="0x1">No reset generated when entering the Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRSTSHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDGSW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWGDSTDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSTOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independent watchdog</Val>
+										<Val value="0x1">Software independent watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>C1BOOTLOCK</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU1 CM4 Unique Boot entry lock disabled</Val>
+										<Val value="0x1">CPU1 CM4 Unique Boot entry lock enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>C2BOOTLOCK</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 CM0+ Unique Boot entry lock disabled</Val>
+										<Val value="0x1">CPU2 CM0+ Unique Boot entry lock enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_IPCCBR" size="0x4" address="0x1FFF7868"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IPCCDBA</Name>
+									<Description>IPCC mailbox data buffer base address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<!--<Category>
+						<Name>Security Configuration Option bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ESE</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security disabled</Val>
+										<Val value="0x1">Security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SFR" size="0x4" address="0x1FFF8070"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SFSA</Name>
+									<Description>Secure Flash start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FSD</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">System and Flash secure</Val>
+										<Val value="0x1">System and Flash non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DDS</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 debug access enabled</Val>
+										<Val value="0x1">CPU2 debug access disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SHDPSA</Name>
+									<Description>SHDPSA[6:0] contain the start address of the first 2 kB page of the User Flash Sticky hide protection area. This bit field can only be accessed by software when HDPADIS = 0. When FSD=0 and HDPAD = 0: User Flash Sticky hide protection area enabled.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>HDPAD</Name>
+									<Description>User Flash Sticky hide protection area disabled. This bit can only be accessed by software when HDPADIS = 0</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									
+								</Bit>
+								<Bit>
+									<Name>SPI3SD</Name>
+									<Description>SPI3 security disable. This bit can only be accessed by software when HDPADIS = 0. FSD=1: SPI3 security is disabled</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">FSD=0 and SPI3SD=0: SPI3 security enabled</Val>
+										<Val value="0x1">FSD=0 and SPI3SD=1: SPI3 security disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SRRVR" size="0x4" address="0x1FFF8078"/>
+							<AssignedBits>
+								<Bit>
+									<Name>C2OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SBRV will address SRAM2</Val>
+										<Val value="0x1">SBRV will address Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NBRSD</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2b is secure if FSD=0 and non-secure otherwise</Val>
+										<Val value="0x1">SRAM2b is non-secure if FSD=0 and secure otherwise</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SNBRSA</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BRSD</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2a is secure if FSD=0 and non-secure otherwise</Val>
+										<Val value="0x1">SRAM2b is non-secure if FSD=0 and secure otherwise</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SBRSA</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SBRV</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>-->
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="PCROP1ASR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1AER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BSR" size="0x4" address="0x1FFF7828"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BER" size="0x4" address="0x1FFF7830"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x495  -->
+	<Device>
+		<DeviceID>0x495</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+/M4</CPU>
+		<Name>STM32WB55xx</Name>
+		<Series>STM32WB</Series>
+		<Description>ARM 32-bit Cortex-M0+ and ARM 32-bit Cortex-M4 dual core based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 192 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x30000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x30000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x100000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 128 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 128 Bytes Data MirrorOptionBytes" size="0x80" address="0x1FFF8000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x80" address="0x1FFF8000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x58004020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0 Boot selected based on nBOOT1</Val>
+										<Val value="0x1">nBOOT0=1 Boot from main Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from code area if BOOT0=0 otherwise embedded SRAM</Val>
+										<Val value="0x1">Boot from code area if BOOT0=0 otherwise system Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Stop mode</Val>
+										<Val value="0x1">No reset generated when entering the Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Standby mode</Val>
+										<Val value="0x1">No reset generated when entering the Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRSTSHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDGSW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWGDSTDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSTOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independent watchdog</Val>
+										<Val value="0x1">Software independent watchdog</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_IPCCBR" size="0x4" address="0x5800403C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IPCCDBA</Name>
+									<Description>IPCC mailbox data buffer base address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Security Configuration Option bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x58004020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ESE</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security disabled</Val>
+										<Val value="0x1">Security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SFR" size="0x4" address="0x58004080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SFSA</Name>
+									<Description>Secure Flash start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FSD</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">System and Flash secure</Val>
+										<Val value="0x1">System and Flash non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DDS</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 debug access enabled</Val>
+										<Val value="0x1">CPU2 debug access disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SRRVR" size="0x4" address="0x58004084"/>
+							<AssignedBits>
+								<Bit>
+									<Name>C2OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SBRV will address SRAM2</Val>
+										<Val value="0x1">SBRV will address Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NBRSD</Name>
+									<Description>If FSD=1 : SRAM2b is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2b is secure</Val>
+										<Val value="0x1">SRAM2b is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SNBRSA</Name>
+									<Description>SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BRSD</Name>
+									<Description>If FSD=1 : SRAM2a is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2a is secure</Val>
+										<Val value="0x1">SRAM2a is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SBRSA</Name>
+									<Description>SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SBRV</Name>
+									<Description>Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x12</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="PCROP1ASR" size="0x4" address="0x58004024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1AER" size="0x4" address="0x58004028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BSR" size="0x4" address="0x58004034"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BER" size="0x4" address="0x58004038"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x5800402C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x58004030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x80" address="0x1FFF8000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0 reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1 reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2 reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3 reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4 reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0 Boot selected based on nBOOT1</Val>
+										<Val value="0x1">nBOOT0=1 Boot from main Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if nBoot0=0 otherwise embedded SRAM</Val>
+										<Val value="0x1">Boot from Flash if nBoot0=0 otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Stop mode</Val>
+										<Val value="0x1">No reset generated when entering the Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Standby mode</Val>
+										<Val value="0x1">No reset generated when entering the Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRSTSHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDGSW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWGDSTDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Standby mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSTOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog counter frozen in Stop mode</Val>
+										<Val value="0x1">Independent watchdog counter running in Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDGSW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independent watchdog</Val>
+										<Val value="0x1">Software independent watchdog</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_IPCCBR" size="0x4" address="0x1FFF8068"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IPCCDBA</Name>
+									<Description>IPCC mailbox data buffer base address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xE</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Security Configuration Option bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF8000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ESE</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security disabled</Val>
+										<Val value="0x1">Security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SFR" size="0x4" address="0x1FFF8070"/>
+							<AssignedBits>
+								<Bit>
+									<Name>SFSA</Name>
+									<Description>Secure Flash start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FSD</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">System and Flash secure</Val>
+										<Val value="0x1">System and Flash non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DDS</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">CPU2 debug access enabled</Val>
+										<Val value="0x1">CPU2 debug access disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SRRVR" size="0x4" address="0x1FFF8078"/>
+							<AssignedBits>
+								<Bit>
+									<Name>C2OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SBRV will address SRAM2</Val>
+										<Val value="0x1">SBRV will address Flash</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NBRSD</Name>
+									<Description>If FSD=1 : SRAM2b is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2b is secure</Val>
+										<Val value="0x1">SRAM2b is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SNBRSA</Name>
+									<Description>SNBRSA[4:0] contains the start address of the first 1K page of the secure non-backup SRAM2b area.</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>BRSD</Name>
+									<Description>If FSD=1: SRAM2a is non-secure. If FSD=0 :</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2a is secure</Val>
+										<Val value="0x1">SRAM2a is non-secure</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SBRSA</Name>
+									<Description>SBRSA[4:0] contains the start address of the first 1K page of the secure backup SRAM2a area.</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SBRV</Name>
+									<Description>Contains the word aligned CPU2 boot reset start address offset within the selected. memory area by C2OPT.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x12</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="PCROP1ASR" size="0x4" address="0x1FFF8008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1AER" size="0x4" address="0x1FFF8010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BSR" size="0x4" address="0x1FFF8028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PCROP1BER" size="0x4" address="0x1FFF8030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP. from level 1 to level 0.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF8018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF8020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x413  -->
+	<Device>
+		<DeviceID>0x413</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F405xx/F407xx/F415xx/F417xx</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 112 KB 0x1c000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x20000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x20000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x100000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 8 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 8 Bytes Data MirrorOptionBytes" size="0x8" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x8" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x4" address="0x40023c14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x8" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x419  -->
+	<Device>
+		<DeviceID>0x419</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F42xxx/F43xxx</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x800"/> </flashSize>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0"/> </flashSize>
+				</Configuration>
+				<Configuration	number="0x2">	
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x3">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x4">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x40000000"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x5">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x40000000"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x6"> <!-- dummy config ></!-->
+					<dummy> <ReadRegister address="0x20000000"	mask="0"	value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x2">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+					<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x3">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+					<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x4">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+					<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x4000"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x5">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+					<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x4000"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x6"> <!-- dummy config ></!-->
+					<dummy> <ReadRegister address="0x20000000"	mask="0"	value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 112 KB 0x1c000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x30000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x30000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x200000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration config="0,1,6">
+					<Parameters name=" 2048 Kbytes Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector12" size="0x4000" address="0x08100000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector16" size="0x10000" address="0x08110000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector17" size="0x20000" address="0x08120000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="4,5">
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector8" size="0x20000" address="0x08080000"	occurence="0x4"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3">
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 24 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 24 Bytes Data MirrorOptionBytes" size="0x18" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x8" address="0x1FFEC008"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
+										<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit config="2,3,4,5">
+									<Name>DB1M</Name>
+									<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
+										<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x40023C18"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>nWRP12</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>nWRP12</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
+										<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit config="2,3,4,5">
+									<Name>DB1M</Name>
+									<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
+										<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="WRP0" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+							</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x8" address="0x1FFEC008"/>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFEC008"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>WRP12</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>WRP12</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x423  -->
+	<Device>
+		<DeviceID>0x423</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F401xB/C</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 112 KB 0x1c000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x40000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x433  -->
+	<Device>
+		<DeviceID>0x433</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F401xD/E</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB 0x1c000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x60000"/>
+				<!-- 384KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 384 Kbytes Embedded Flash" size="0x60000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x431  -->
+	<Device>
+		<DeviceID>0x431</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F411xC/E</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 128 KB 0x20000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x80000"/>
+				<!-- 512KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x421  -->
+	<Device>
+		<DeviceID>0x421</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F446xx</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 128 KB 0x20000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x20000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x20000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x80000"/>
+				<!-- 512KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x4" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x441  -->
+	<Device>
+		<DeviceID>0x441</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F412</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 256 KB 0x40000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x40000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x40000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address=" 0x1FFF7A22" default="0x100000"/>
+				<!-- 512KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 1 Mbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x458  -->
+	<Device>
+		<DeviceID>0x458</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F410</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 32 KB 0x8000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x20000"/>
+				<!-- 128K Single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x463  -->
+	<Device>
+		<DeviceID>0x463</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F413/F423</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x80000000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 320 KB 0x50000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x50000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x50000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x180000"/>
+				<!-- 512KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 1.5 Mbytes Embedded Flash" size="0x180000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0xB"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFC000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xF</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x434  -->
+	<Device>
+		<DeviceID>0x434</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F469xx/F467xx</Name>
+		<Series>STM32F4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x800"/> </flashSize>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x800"/> </flashSize>
+				</Configuration>
+				<Configuration	number="0x2">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x3">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x4">
+					<SPRMode reference="0x0"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x40000000"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x5">
+					<SPRMode reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x80000000"	value="0x0"/> </SPRMode>
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF7A22"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40023C14"	mask="0x40000000"	value="0x40000000"/> </DB1M>
+				</Configuration>
+				<Configuration number="0x6">
+					<dummy> <ReadRegister address="0x20000000"	mask="0"	value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x1">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+				</Configuration>
+				<Configuration	number="0x2">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+					<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x3">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+					<DB1M reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x0"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x4">
+					<SPRMode reference="0x0"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x0"/> </SPRMode>
+					<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x4000"/> </DB1M>
+				</Configuration>
+				<Configuration	number="0x5">
+					<SPRMode reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x8000"	value="0x8000"/> </SPRMode>
+					<DB1M reference="0x1"> <ReadRegister address="0x1FFFC008"	mask="0x4000"	value="0x4000"/> </DB1M>
+				</Configuration>
+				<Configuration number="0x6">
+					<dummy> <ReadRegister address="0x20000000"	mask="0"	value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 320 KB 0x50000-->
+				<Configuration>
+					<Parameters name="SRAM" size="0x50000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x50000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x200000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration config="0,1,6">
+					<Parameters name=" 2048 Kbytes Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector12" size="0x4000" address="0x08100000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector16" size="0x10000" address="0x08110000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector17" size="0x20000" address="0x08120000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="4,5">
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector8" size="0x20000" address="0x08080000"	occurence="0x4"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3">
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 20 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 20 Bytes Data MirrorOptionBytes" size="0x14" address="0x1FFEC008"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x4" address="0x1FFEC008"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x10" address="0x1FFFC000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
+										<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit config="2,3,4,5">
+									<Name>DB1M</Name>
+									<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
+										<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x40023C18"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>nWRP12</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>nWRP12</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Selection of protection mode for nWPRi bits.</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP disabled. nWPRi bits used for Write protection on sector i</Val>
+										<Val value="0x1">PCROP enabled. nWPRi bits used for PCROP protection on sector i</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disabled. Boot can be performed either from Flash memory bank 1 or from system memory depending on boot pin state (default)</Val>
+										<Val value="0x1">Dual-bank boot enabled. Boot is always performed from system memory.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit config="2,3,4,5">
+									<Name>DB1M</Name>
+									<Description>Dual-bank on 1 Mbyte Flash memory devices</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 Mbyte single bank Flash memory (contiguous addresses in bank1)</Val>
+										<Val value="0x1">1 Mbyte dual bank Flash memory. The Flash memory is organized as two banks of 512 Kbytes each</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP0" size="0x4" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+							</Field> 
+					</Category> 
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x4" address="0x1FFEC008"/>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x4" address="0x1FFEC008"/>
+							<AssignedBits>
+								<Bit config="0,2,4">
+									<Name>nWRP12</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>	
+								</Bit>
+								<Bit config="1,3,5,6">
+									<Name>nWRP12</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on sector i</Val>
+										<Val value="0x1">PCROP protection active on sector i</Val>
+									</Values>	
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x411 -->
+	<Device>
+		<DeviceID>0x411</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F2xx</Name>
+		<Series>STM32F2</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 128 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x20000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x20000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF7A22" default="0x100000"/>
+				<!-- 1024KB Single Bank -->
+				<Configuration>
+					<Parameters name=" 1024 Kbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0xC" address="0x40023c14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x1" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x1" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x1" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x2" address="0x40023c14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<!--<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0xC" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x1" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x1" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x1" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x2" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>-->
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0xC" address="0x1FFFC000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x1" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x1" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 reset threshold level from 2.70 to 3.60 V</Val>
+										<Val value="0x1">BOR Level 2 reset threshold level from 2.40 to 2.70 V</Val>
+										<Val value="0x2">BOR Level 1 reset threshold level from 2.10 to 2.40 V</Val>
+										<Val value="0x3">BOR  OFF    reset threshold level from 1.80 to 2.10 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x1" address="0x1FFFC000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x2" address="0x1FFFC008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x437 -->
+	<Device>
+		<DeviceID>0x437</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32L15xxE/STM32L162xE</Name>
+		<Series>STM32L1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 80 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x14000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x14000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF800CC" default="0x80000"/>
+				<!-- 512KB dual Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x100" address="0x08000000"	occurence="0x400"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector1024" size="0x100" address="0x08040000"	occurence="0x400"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16KB dual Bank -->
+				<Configuration>
+					<Parameters name=" 16 Kbytes Data EEPROM" size="0x4000" address="0x08080000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x2000" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="EEPROM2" size="0x2000" address="0x08082000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 136 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 136 Bytes Data MirrorOptionBytes" size="0x88" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x88" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x88" address="0x40023C1C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBFB2</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">If boot from Flash then boot from bank 2</Val>
+										<Val value="0x1">If boot from Flash then boot from bank 1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40023C20"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="FLASH_WRPR2" size="0x4" address="0x40023C80"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true"> 
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="FLASH_WRPR3" size="0x4" address="0x40023C84"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="FLASH_WRPR4" size="0x4" address="0x40023C88"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x88" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBFB2</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">If boot from Flash then boot from bank 2</Val>
+										<Val value="0x1">If boot from Flash then boot from bank 1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true"> 
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80014"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF80018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF8001C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP80</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP4" size="0x8" address="0x1FF80080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP96</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP4" size="0x8" address="0x1FF80084"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP112</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x88" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBFB2</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">If boot from Flash then boot from bank 2</Val>
+										<Val value="0x1">If boot from Flash then boot from bank 1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true"> 
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80014"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF80018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF8001C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP80</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP4" size="0x8" address="0x1FF80080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP96</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP4" size="0x8" address="0x1FF80084"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP112</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x436 -->
+	<Device>
+		<DeviceID>0x436</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32L15xxD/STM32L162xD</Name>
+		<Series>STM32L1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 48 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0xC000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0xC000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF800CC" default="0x20000"/>
+				<!-- 384KB dual Bank -->
+				<Configuration>
+					<Parameters name=" 384 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x100" address="0x08000000"	occurence="0x300"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector768" size="0x100" address="0x08030000"	occurence="0x300"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 12KB dual Bank -->
+				<Configuration>
+					<Parameters name=" 12 Kbytes Data EEPROM" size="0x3000" address="0x08080000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x1800" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="EEPROM2" size="0x1800" address="0x08081800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 32 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 32 Bytes Data MirrorOptionBytes" size="0x20" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x20" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral> 
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x88" address="0x40023C1C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBFB2</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">If boot from Flash then boot from bank 2</Val>
+										<Val value="0x1">If boot from Flash then boot from bank 1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40023C20"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="FLASH_WRPR2" size="0x4" address="0x40023C80"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true"> 
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="FLASH_WRPR3" size="0x4" address="0x40023C84"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x20" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBFB2</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">If boot from Flash then boot from bank 2</Val>
+										<Val value="0x1">If boot from Flash then boot from bank 1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true"> 
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80014"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF80018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF8001C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP80</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x20" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBFB2</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">If boot from Flash then boot from bank 2</Val>
+										<Val value="0x1">If boot from Flash then boot from bank 1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true"> 
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80014"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF80018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP64</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP3" size="0x8" address="0x1FF8001C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP80</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x429 -->
+	<Device>
+		<DeviceID>0x429</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32L100x6xxA/STM32L100x8xxA/STM32L100xBxxA/STM32L15xx6xxA/STM32L15xx8xxA/STM32L15xxBxxA</Name>
+		<Series>STM32L1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<SPRMode reference="0x1">
+						<ReadRegister address="0x40023C1C"	mask="0x000000100"	value="0x0"/>
+					</SPRMode>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<SPRMode reference="0x0">
+						<ReadRegister address="0x40023C1C"	mask="0x000000100"	value="0x100"/>
+					</SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<SPRMode reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</SPRMode>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<SPRMode reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x4000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x4000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF8004C" default="0x20000"/>
+				<!-- 128KB single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x100" address="0x08000000"	occurence="0x200"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1KB single Bank -->
+				<Configuration>
+					<Parameters name=" 4096 bytes Data EEPROM" size="0x1000" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x1000" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 24 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 24 Bytes Data MirrorOptionBytes" size="0x18" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x18" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x88" address="0x40023C1C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40023C20"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x88" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="SPRMOD" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector write/read (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x18" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="SPRMOD" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector write/read (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x427 -->
+	<Device>
+		<DeviceID>0x427</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32L100xC/STM32L15xxC/STM32L162xC</Name>
+		<Series>STM32L1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<SPRMode reference="0x1">
+						<ReadRegister address="0x40023C1C"	mask="0x000000100"	value="0x0"/>
+					</SPRMode>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<SPRMode reference="0x0">
+						<ReadRegister address="0x40023C1C"	mask="0x000000100"	value="0x100"/>
+					</SPRMode>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<SPRMode reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</SPRMode>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<SPRMode reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</SPRMode>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 32 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF800CC" default="0x40000"/>
+				<!-- 256KB single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x100" address="0x08000000"	occurence="0x400"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 8KB single Bank -->
+				<Configuration>
+					<Parameters name=" 8 Kbytes Data EEPROM" size="0x2000" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x2000" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 24 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 24 Bytes Data MirrorOptionBytes" size="0x18" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x18" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x88" address="0x40023C1C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40023C20"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRPR2" size="0x4" address="0x40023C80"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x88" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="SPRMOD" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector write/read (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80014"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x18" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="SPRMOD" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>SPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector write/read (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP2" size="0x8" address="0x1FF80014"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP48</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x416 -->
+	<Device>
+		<DeviceID>0x416</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32L100x8/STM32L100xB/STM32L15xx6/STM32L15xx8/STM32L15xxB</Name>
+		<Series>STM32L1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 10-16 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x2800" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x2800" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF8004C" default="0x20000"/>
+				<!-- 128KB single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x100" address="0x08000000"	occurence="0x200"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1KB single Bank -->
+				<Configuration>
+					<Parameters name=" 4096 bytes Data EEPROM" size="0x1000" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x1000" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x88" address="0x40023C1C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40023C20"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x435 -->
+	<Device>
+		<DeviceID>0x435</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L43xxx/STM32L44xxx</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 128 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0xC000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0xC000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 36 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 36 Bytes Data MirrorOptionBytes" size="0x24" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x24" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x464 -->
+	<Device>
+		<DeviceID>0x464</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L41x</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 128 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0xA000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0xA000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 36 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 36 Bytes Data MirrorOptionBytes" size="0x24" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x24" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x462 -->
+	<Device>
+		<DeviceID>0x462</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L45x/L46x</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 128 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x20000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x20000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 36 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 36 Bytes Data MirrorOptionBytes" size="0x24" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x24" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x422 -->
+	<Device>
+		<DeviceID>0x422</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F302xB-xC/STM32F303xB-xC/F358xx</Name>
+		<Series>STM32F3</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 40 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0xA000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0xA000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x40000"/>
+				<!-- 256 KB single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x439 -->
+	<Device>
+		<DeviceID>0x439</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F301x4-x6-x8/STM32F302x4-x6-x8/F318xx</Name>
+		<Series>STM32F3</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB, 12KB accessible -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x4000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x4000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x10000"/>
+				<!-- 64 KB single Bank -->
+				<Configuration>
+					<Parameters name=" 64 Kbytes Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x20"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x461 -->
+	<Device>
+		<DeviceID>0x461</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L496xx/STM32L4A6xx</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 256 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x40000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x50000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x100000"/>
+				<!-- 1MB dual Bank -->
+				<Configuration>
+					<Parameters name=" 1 Mbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector256" size="0x800" address="0x08080000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 64 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 64 Bytes Data MirrorOptionBytes" size="0x40" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x24" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x1C" address="0x1FFFF808"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x40022044"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x40022050"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection  (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x1C" address="0x1FFFF808"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x1FFFF810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x1FFFF818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x1FFFF820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x438 -->
+	<Device>
+		<DeviceID>0x438</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F303x4-x6-x8/F328xx/F334xx</Name>
+		<Series>STM32F3</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB, 12KB accessible -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x3000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x3000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x10000"/>
+				<!-- 64 KB single Bank -->
+				<Configuration>
+					<Parameters name=" 64 Kbytes Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x20"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM_PE</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x432 -->
+	<Device>
+		<DeviceID>0x432</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F37xx</Name>
+		<Series>STM32F3</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 32 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x40000"/>
+				<!-- 256KB single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SDADC12_VDD</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SDADC12_VDD power supply supervisor disabled.</Val>
+										<Val value="0x1">SDADC12_VDD power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x415 -->
+	<Device>
+		<DeviceID>0x415</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L4x1/STM32L475xx/STM32L476xx/STM32L486xx</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x18000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x18000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x100000"/>
+				<!-- 1MB dual Bank -->
+				<Configuration>
+					<Parameters name=" 1 Mbyte Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector256" size="0x800" address="0x08080000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 64 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 64 Bytes Data MirrorOptionBytes" size="0x40" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x24" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x1C" address="0x1FFFF808"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x40022044"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x40022050"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x1C" address="0x1FFFF808"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x1FFFF810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x1FFFF818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x1FFFF820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x20"	offset="0x08080000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x446 -->
+	<Device>
+		<DeviceID>0x446</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32F302xE/F303xE/F398xx</Name>
+		<Series>STM32F3</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 80 KB !!!! Only 64 KB accessible by debug If -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x14000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Main Flash memory is selected as boot area</Val>
+										<Val value="0x1">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from System flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by nBOOT0 option bit</Val>
+										<Val value="0x1">BOOT0 signal is defined by BOOT0 pin value</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x445 -->
+	<Device>
+		<DeviceID>0x445</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0</CPU>
+		<Name>STM32F04x/F070x6</Name>
+		<Series>STM32F0</Series>
+		<Description>ARM 32-bit Cortex-M0 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 6 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x1800" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x1800" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x8000"/>
+				<!-- 32KB single Bank -->
+				<Configuration>
+					<Parameters name=" 32 Kbytes Embedded Flash" size="0x8000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x400" address="0x08000000"	occurence="0x20"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by nBOOT0 option bit</Val>
+										<Val value="0x1">BOOT0 signal is defined by BOOT0 pin value</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x444 -->
+	<Device>
+		<DeviceID>0x444</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0</CPU>
+		<Name>STM32F03x</Name>
+		<Series>STM32F0</Series>
+		<Description>ARM 32-bit Cortex-M0 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 4 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x1000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x1000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x8000"/>
+				<!-- 32KB single Bank -->
+				<Configuration>
+					<Parameters name=" 32 Kbytes Embedded Flash" size="0x8000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x400" address="0x08000000"	occurence="0x20"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x442 -->
+	<Device>
+		<DeviceID>0x442</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0</CPU>
+		<Name>STM32F09x/F030xC</Name>
+		<Series>STM32F0</Series>
+		<Description>ARM 32-bit Cortex-M0 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 32 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x40000"/>
+				<!-- 256KB single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory.</Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by nBOOT0 option bit</Val>
+										<Val value="0x1">BOOT0 signal is defined by BOOT0 pin value</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x451 -->
+	<Device>
+		<DeviceID>0x451</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M7</CPU>
+		<Name>STM32F76x/STM32F77x</Name>
+		<Series>STM32F7</Series>
+		<Description>ARM 32-bit Cortex-M7 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- 2MB Single Bank-->
+					<DualBank reference="0x1">
+						<ReadRegister address="0x40023C14"	mask="0x20000000"	value="0x20000000"/>
+					</DualBank>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- 2MB Dual Bank-->
+					<DualBank reference="0x0">
+						<ReadRegister address="0x40023C14"	mask="0x20000000"	value="0x0"/>
+					</DualBank>
+				</Configuration>
+			</Interface>		
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- 2MB Single Bank-->
+					<DualBank reference="0x1">
+						<ReadRegister address="0x1FFF0008"	mask="0x2000"	value="0x2000"/>
+					</DualBank>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- 2MB Dual Bank-->
+					<DualBank reference="0x0">
+						<ReadRegister address="0x1FFF0008"	mask="0x2000"	value="0x0"/>
+					</DualBank>
+				</Configuration>
+			</Interface>	
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 512 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x80000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM1" size="0x80000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF0F442" default="0x200000"/>
+				<!-- 2MB Single Bank -->
+				<Configuration config="0">
+					<Parameters name=" 2 Mbytes single bank Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x8000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x20000" address="0x08020000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x40000" address="0x08040000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- 2MB Dual Bank -->
+				<Configuration config="1">
+					<Parameters name=" 2 Mbytes dual bank Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector12" size="0x4000" address="0x08100000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector16" size="0x10000" address="0x08110000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector17" size="0x20000" address="0x08120000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- ITCM FLASH -->
+			<Peripheral>
+				<Name>ITCM Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 2MB Single Bank -->
+				<Configuration config="0">
+					<Parameters name=" 2 Mbytes single bank Embedded Flash" size="0x200000" address="0x00200000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x8000" address="0x00200000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x20000" address="0x00220000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x40000" address="0x00240000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- 2MB Dual Bank -->
+				<Configuration config="1">
+					<Parameters name=" 2 Mbytes dual bank Embedded Flash" size="0x200000" address="0x00200000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x00200000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x00210000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x00220000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector12" size="0x4000" address="0x00300000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector16" size="0x10000" address="0x00310000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector17" size="0x20000" address="0x00320000"	occurence="0x7"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FF0F000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FF0F000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 44 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 44 Bytes Data MirrorOptionBytes" size="0x2C" address="0x1FFF0000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x2C" address="0x1FFF0000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
+										<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
+										<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
+										<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit reference="DualBank">
+									<Name>nDBANK</Name>
+									<Description/>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Flash in dual bank with 128 bits read access</Val>
+										<Val value="0x1">Flash in single bank with 256 bits read access</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nDBOOT</Name>
+									<Description/>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual Boot enabled</Val>
+										<Val value="0x1">Dual Boot disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x40023C18"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD0</Name>
+									<Description>Define the boot address when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_ADD1</Name>
+									<Description>Define the boot address when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on bank1 sector 2i and 2i+1</Val>
+										<Val value="0x1">Write protection not active on bank1 sector 2i, 2i+1</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nWRP6</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on bank2 sector 2i and 2i+1</Val>
+										<Val value="0x1">Write protection not active on bank2 sector 2i, 2i+1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x2C" address="0x1FFF0000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
+										<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
+										<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
+										<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit reference="DualBank">
+									<Name>nDBANK</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Flash in dual bank with 128 bits read access</Val>
+										<Val value="0x1">Flash in single bank with 256 bits read access</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nDBOOT</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual Boot enabled</Val>
+										<Val value="0x1">Dual Boot disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD0</Name>
+									<Description>Define the boot address when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD1</Name>
+									<Description>Define the boot address when BOOT0=1</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0008"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on bank1 sector 2i and 2i+1</Val>
+										<Val value="0x1">Write protection not active on bank1 sector 2i, 2i+1</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nWRP6</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on bank2 sector 2i and 2i+1</Val>
+										<Val value="0x1">Write protection not active on bank2 sector 2i, 2i+1</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x449 -->
+	<Device>
+		<DeviceID>0x449</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M7</CPU>
+		<Name>STM32F74x/STM32F75x</Name>
+		<Series>STM32F7</Series>
+		<Description>ARM 32-bit Cortex-M7 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- ROM Die -->
+					<RomLess>
+						<ReadRegister address="0x1FF0F442"	mask="0x40"	value="0x00"/>
+					</RomLess>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- RomLess Die -->
+					<RomLess>
+						<ReadRegister address="0x1FF0F442"	mask="0x40"	value="0x40"/>
+					</RomLess>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- ROM Die -->
+					<RomLess>
+						<ReadRegister address="0x0x08000000"	mask="0x00"	value="0x00"/>
+					</RomLess>
+				</Configuration>
+			</Interface>	
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 320 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x50000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM1" size="0x50000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF0F442" default="0x100000"/>
+				<!-- 1MB single Bank -->
+				<Configuration config="0">
+					<Parameters name=" 1 Mbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x8000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x20000" address="0x08020000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x40000" address="0x08040000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1">
+					<Parameters name=" 64 KByte Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x8000" address="0x08000000"	occurence="0x2"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- ITCM Flash-->
+			<Peripheral>
+				<Name>ITCM Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1MB single Bank -->
+				<Configuration config="0">
+					<Parameters name=" 1 Mbytes Embedded Flash" size="0x100000" address="0x00200000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x8000" address="0x00200000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x20000" address="0x00220000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x40000" address="0x00240000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1">
+					<Parameters name=" 64 KByte Embedded Flash" size="0x10000" address="0x00200000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x8000" address="0x00200000"	occurence="0x2"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x200" address="0x1FF0F000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FF0F000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 44 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 44 Bytes Data MirrorOptionBytes" size="0x2C" address="0x1FFF0000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x2C" address="0x1FFF0000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
+										<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
+										<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
+										<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x40023C18"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD0</Name>
+									<Description>Define the boot address when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_ADD1</Name>
+									<Description>Define the boot address when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x2C" address="0x1FFF0000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
+										<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
+										<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
+										<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD0</Name>
+									<Description>Define the boot address when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD1</Name>
+									<Description>Define the boot address when BOOT0=1</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x440 -->
+	<Device>
+		<DeviceID>0x440</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0</CPU>
+		<Name>STM32F05x/F030x8</Name>
+		<Series>STM32F0</Series>
+		<Description>ARM 32-bit Cortex-M0 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 8 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x1FF8" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x1FF8" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x10000"/>
+				<!-- 64KB single Bank -->
+				<Configuration>
+					<Parameters name=" 64 Kbytes Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x400" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from main flash memory. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x448 -->
+	<Device>
+		<DeviceID>0x448</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0</CPU>
+		<Name>STM32F07x</Name>
+		<Series>STM32F0</Series>
+		<Description>ARM 32-bit Cortex-M0 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x4000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x4000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7CC" default="0x20000"/>
+				<!-- 128KB single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>Together with the input pad BOOT0, selects the Boot mode. If BOOT0=0, always boot from main flash memory regardless of nBoot1 value. </Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM when BOOT0=1</Val>
+										<Val value="0x1">Boot from system flash when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDA_MONITOR</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">VDDA power supply supervisor disabled</Val>
+										<Val value="0x1">VDDA power supply supervisor enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">RAM parity check enabled</Val>
+										<Val value="0x1">RAM parity check disabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nWRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x452 -->
+	<Device>
+		<DeviceID>0x452</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M7</CPU>
+		<Name>STM32F72x/STM32F73x</Name>
+		<Series>STM32F7</Series>
+		<Description>ARM 32-bit Cortex-M7 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- ROM Die -->
+					<RomLess>
+						<ReadRegister address="0x1FF07A22"	mask="0x40"	value="0x00"/>
+					</RomLess>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- RomLess Die -->
+					<RomLess>
+						<ReadRegister address="0x1FF07A22"	mask="0x40"	value="0x40"/>
+					</RomLess>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- ROM Die -->
+					<RomLess>
+						<ReadRegister address="0x0x08000000"	mask="0x00"	value="0x00"/>
+					</RomLess>
+				</Configuration>
+			</Interface>	
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 512 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x40000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x40000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF07A22" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration config="0">
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x08010000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x08020000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- 64KB RomLess -->
+				<Configuration  config="1">
+					<Parameters name=" 64 Kbytes Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x4"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- ITCM Bytes -->
+			<Peripheral>
+				<Name>ITCM Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 512KB single Bank -->
+				<Configuration config="0">
+					<Parameters name=" 512 Kbytes ITCM Flash" size="0x80000" address="0x00200000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x00200000"	occurence="0x4"/>
+						</Field>
+						<Field>
+							<Parameters name="sector4" size="0x10000" address="0x00210000"	occurence="0x1"/>
+						</Field>
+						<Field>
+							<Parameters name="sector5" size="0x20000" address="0x00220000"	occurence="0x3"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- 64KB RomLess -->
+				<Configuration  config="1">
+					<Parameters name=" 64 Kbytes ITCM Flash" size="0x10000" address="0x00200000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x00200000"	occurence="0x4"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x1FF07800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x1FF07800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 44 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 44 Bytes Data MirrorOptionBytes" size="0x2C" address="0x1FFF0000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x2C" address="0x1FFF0000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0xC" address="0x40023C14"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
+										<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
+										<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
+										<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR2" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x40023C18"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD0</Name>
+									<Description>Define the boot address when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_ADD1</Name>
+									<Description>Define the boot address when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x40023C14"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Read/Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR2" size="0x4" address="0x40023C1C"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>PCROP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on this sector</Val>
+										<Val value="0x1">PCROP protection active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on this sector</Val>
+										<Val value="0x1">PCROP protection active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x2C" address="0x1FFF0000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 3 (VBOR3), brownout threshold level 3</Val>
+										<Val value="0x1">BOR Level 2 (VBOR2), brownout threshold level 2</Val>
+										<Val value="0x2">BOR Level 1 (VBOR1), brownout threshold level 1</Val>
+										<Val value="0x3">BOR off, POR/PDR reset threshold level is applied</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR" size="0x4" address="0x1FFF0000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR2" size="0x4" address="0x1FFF0028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0010"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD0</Name>
+									<Description>Define the boot address when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0018"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_ADD1</Name>
+									<Description>Define the boot address when BOOT0=1</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR1" size="0x4" address="0x1FFF0008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Read/Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTCR2" size="0x4" address="0x1FFF0020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">PCROP protection not active on this sector</Val>
+										<Val value="0x1">PCROP protection active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x450 -->
+	<Device>
+		<DeviceID>0x450</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M7</CPU>
+		<Name>STM32H7xx</Name>
+		<Series>STM32H7</Series>
+		<Description>ARM 32-bit Cortex-M7 and ARM 32-bit Cortex-M4 dual core based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- Security extension available && multi-core-->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x4"/>
+					</MultiCore>
+					<!--<RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x00"/>
+					</RomLess>-->
+				</Configuration>
+				<Configuration	number="0x1"> <!-- Security extension not available && multi-core -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x4"/>
+					</MultiCore>
+					<!-- <RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x00"/>
+					</RomLess> -->
+				</Configuration>
+				<Configuration	number="0x2"> <!-- Security extension available && single core -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x3"/>
+					</MultiCore>
+					<RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x00"/>
+					</RomLess>
+				</Configuration>
+				<Configuration	number="0x3"> <!-- Security extension not available && single core -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x3"/>
+					</MultiCore>
+					<RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x00"/>
+					</RomLess>
+				</Configuration>
+
+                <!-- ROMLESS Configurations -->
+				<Configuration	number="0x4"> <!-- Security extension available && multi-core-->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x4"/>
+					</MultiCore>
+					 <RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x80"/>
+					</RomLess> 
+				</Configuration>
+				<Configuration	number="0x5"> <!-- Security extension not available && multi-core -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x4"/>
+					</MultiCore>
+					<RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x80"/>
+					</RomLess>
+				</Configuration>
+				<Configuration	number="0x6"> <!-- Security extension available && single core -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x3"/>
+					</MultiCore>
+					<RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x80"/>
+					</RomLess>
+				</Configuration>
+				<Configuration	number="0x7"> <!-- Security extension not available && single core -->
+					<RomLess>
+						<ReadRegister address="0x1FF1E880"	mask="0x80"	value="0x80"/>
+					</RomLess>
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+					</SecurityEx>
+					<MultiCore>
+						<ReadRegister address="0x0"	mask="0x0"	value="0x3"/>
+					</MultiCore>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- Security extension availabe && multicore--> <!-- dummy always true -->
+					<Dummy>
+						<ReadRegister address="0x08000000"	mask="0x0"	value="0x0"/>
+					</Dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 512 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x80000" address="0x24000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x80000" address="0x24000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF1E880" default="0x200000"/>
+				<!-- 2MB Dual Bank -->
+				<Configuration config="0,1,2,3">
+					<Parameters name="2 MBytes Dual Bank Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x20000" address="0x08000000"	occurence="0x8"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector8" size="0x20000" address="0x08100000"	occurence="0x8"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- RomLess 128KB -->
+				<Configuration config="4,5,6,7">
+					<Parameters name="RomLess 128 KB Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x20000" address="0x08000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- ITCM Flash -->
+			<Peripheral>
+				<Name>ITCM Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 2MB Dual Bank -->
+				<Configuration config="0,1,2,3">
+					<Parameters name="2 MBytes Dual Bank Embedded Flash" size="0x200000" address="0x00200000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x20000" address="0x00200000"	occurence="0x8"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector8" size="0x20000" address="0x00300000"	occurence="0x8"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- RomLess 128KB -->
+				<Configuration config="4,5,6,7">
+					<Parameters name="RomLess 128 KB Embedded Flash" size="0x20000" address="0x00200000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x20000" address="0x00200000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x134" address="0x5200201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>RSS</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RSS1</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">No SFI process on going</Val>
+										<Val value="0x1">SFI process started</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RSS1</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">No SFI process on going</Val>
+										<Val value="0x1">SFI process started</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">reset level is set to VBOR0</Val>
+										<Val value="0x1">reset level is set to VBOR1</Val>
+										<Val value="0x2">reset level is set to VBOR2</Val>
+										<Val value="0x3">reset level is set to VBOR3</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits reflects the power level that generates a system reset. Refer to device datasheet for the values of VBORx VDD reset thresholds.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">reset level is set to VBOR0</Val>
+										<Val value="0x1">reset level is set to VBOR1</Val>
+										<Val value="0x2">reset level is set to VBOR2</Val>
+										<Val value="0x3">reset level is set to VBOR3</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG1_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1,4,5">
+									<Name>IWDG2_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP_D1</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY_D1</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
+										<Val value="0x1">Independent watchdog is running in STOP mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_SDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
+										<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
+									</Values>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>SECURITY</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security feature disabled</Val>
+										<Val value="0x1">Security feature enabled</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1">
+									<Name>BCM4</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">CM4 boot disabled</Val>
+										<Val value="0x1">CM4 boot enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BCM7</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">CM7 boot disabled</Val>
+										<Val value="0x1">CM7 boot enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP_D2</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY_D2</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>SWAP_BANK</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">after boot loading, no swap for user sectors</Val>
+										<Val value="0x1">after boot loading, user sectors swapped</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG1_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1,4,5">
+									<Name>IWDG2_SW</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP_D1</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY_D1</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
+										<Val value="0x1">Independent watchdog is running in STOP mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_SDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
+										<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
+									</Values>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>SECURITY</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Security feature disabled</Val>
+										<Val value="0x1">Security feature enabled</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1,4,5">
+									<Name>BCM4</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">CM4 boot disabled</Val>
+										<Val value="0x1">CM4 boot enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BCM7</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">CM7 boot disabled</Val>
+										<Val value="0x1">CM7 boot enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP_D2</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 2 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 2 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY_D2</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 2 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 2 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>SWAP_BANK</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">after boot loading, no swap for user sectors</Val>
+										<Val value="0x1">after boot loading, user sectors swapped</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FBOOT7_CUR" size="0x4" address="0x52002040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_CM7_ADD0</Name>
+									<Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_CM7_ADD1</Name>
+									<Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FBOOT4_CUR" size="0x4" address="0x52002048"/>
+							<AssignedBits>
+								<Bit config="0,1,4,5">
+									<Name>BOOT_CM4_ADD0</Name>
+									<Description>Define the boot address for Cortex-M4 when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit config="0,1,4,5">
+									<Name>BOOT_CM4_ADD1</Name>
+									<Description>Define the boot address for Cortex-M4 when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FBOOT7_PRG" size="0x4" address="0x52002044"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_CM7_ADD0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_CM7_ADD1</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FBOOT4_PRG" size="0x4" address="0x5200204C"/>
+							<AssignedBits>
+								<Bit config="0,1,4,5">
+									<Name>BOOT_CM4_ADD0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit config="0,1,4,5">
+									<Name>BOOT_CM4_ADD1</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FPRAR_CUR_A" size="0x4" address="0x52002028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START1</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END1</Name>
+									<Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_PRG_A" size="0x4" address="0x5200202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START1</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END1</Name>
+									<Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_CUR_B" size="0x4" address="0x52002128"/>
+							<AssignedBits>
+								<Bit config="0,1,2,3">
+									<Name>PROT_AREA_START2</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>PROT_AREA_END2</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>DMEP2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_PRG_B" size="0x4" address="0x5200212C"/>
+							<AssignedBits>
+								<Bit config="0,1,2,3">
+									<Name>PROT_AREA_START2</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>PROT_AREA_END2</Name>
+									<Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit config="0,1,2,3">
+									<Name>DMEP2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Protection</Name>
+						<Field>
+							<Parameters name="FSCAR_CUR_A" size="0x4" address="0x52002030"/>
+							<AssignedBits>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_START1</Name>
+									<Description>Flash Bank 1 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_END1</Name>
+									<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>DMES1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_PRG_A" size="0x4" address="0x52002034"/>
+							<AssignedBits>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_START1</Name>
+									<Description>Flash Bank 1 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>SEC_AREA_END1</Name>
+									<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit	config="0,2,4,6">
+									<Name>DMES1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_CUR_B" size="0x4" address="0x52002130"/>
+							<AssignedBits>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_START2</Name>
+									<Description>Flash Bank 2 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_END2</Name>
+									<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>DMES2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_PRG_B" size="0x4" address="0x52002134"/>
+							<AssignedBits>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_START2</Name>
+									<Description>Flash Bank 2 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>SEC_AREA_END2</Name>
+									<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit	config="0,2">
+									<Name>DMES2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>DTCM RAM Protection</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ST_RAM_SIZE</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">2 KB</Val>
+										<Val value="0x1">4 KB</Val>
+										<Val value="0x2">8 KB</Val>
+										<Val value="0x3">16 KB</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ST_RAM_SIZE</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">2 KB</Val>
+										<Val value="0x1">4 KB</Val>
+										<Val value="0x2">8 KB</Val>
+										<Val value="0x3">16 KB</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FWPSN_CUR_A" size="0x4" address="0x52002038"/>
+							<AssignedBits>
+								<Bit config="0,1,2,3">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="4,5,6,7">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_PRG_A" size="0x4" address="0x5200203C"/>
+							<AssignedBits>
+								<Bit config="0,1,2,3">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit config="4,5,6,7">
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_CUR_B" size="0x4" address="0x52002138"/>
+							<AssignedBits>
+								<Bit config="0,1,2,3">
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_PRG_B" size="0x4" address="0x5200213C"/>
+							<AssignedBits>
+								<Bit config="0,1,2,3">
+									<Name>nWRP8</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	<!-- Device: 0x480 -->
+	<Device>
+		<DeviceID>0x480</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M7</CPU>
+		<Name>STM32H7A/B</Name>
+		<Series>STM32H7</Series>
+		<Description>ARM 32-bit Cortex-M7 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0xA">
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+						<ReadRegister address="0x08fff80c"	mask="0x00000FFF"	value="0x400"/>
+					</SecurityEx>
+				</Configuration>
+				<Configuration	number="0xB">
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+						<ReadRegister address="0x08fff80c"	mask="0x00000FFF"	value="0x400"/>
+					</SecurityEx>
+				</Configuration>
+				<Configuration	number="0x0"> <!-- Security extension available -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x0"/>
+					</SecurityEx>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- Security extension not available -->
+					<SecurityEx>
+						<WriteRegister	address="0x580244F4"	value="0x2"/>
+						<ReadRegister address="0x58000528"	mask="0x1"	value="0x1"/>
+					</SecurityEx>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- dummy always true, security extension is checked using dedicated cmd -->
+					<Dummy>
+						<ReadRegister address="0x08000000"	mask="0x0"	value="0x0"/>
+					</Dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1024 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x100000" address="0x24000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x100000" address="0x24000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages AXI accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x08fff80c" default="0x200000"/>
+				<!-- 2MB Dual Bank -->
+				<Configuration config="0,1">
+					<Parameters name="2 MBytes Dual Bank Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x2000" address="0x08100000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- 1MB Dual Bank -->
+				<Configuration config="10,11">
+					<Parameters name="1 MBytes Dual Bank Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector64" size="0x2000" address="0x08080000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x08FFF000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x20</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x08FFF000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x134" address="0x5200201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">reset level OFF</Val>
+										<Val value="0x1">reset level is set to 2.1 V</Val>
+										<Val value="0x2">reset level is set to 2.4 V</Val>
+										<Val value="0x3">reset level is set to 2.7 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">reset level OFF</Val>
+										<Val value="0x1">reset level is set to 2.1 V</Val>
+										<Val value="0x2">reset level is set to 2.4 V</Val>
+										<Val value="0x3">reset level is set to 2.7 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG1_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDMMC_HSLV</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
+										<Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
+										<Val value="0x1">Independent watchdog is running in STOP mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_SDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
+										<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
+									</Values>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>SECURITY</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Security feature disabled</Val>
+										<Val value="0x1">Security feature enabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SWAP_BANK_OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">after boot loading, no swap for user sectors</Val>
+										<Val value="0x1">after boot loading, user sectors swapped</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG1_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is controlled by hardware</Val>
+										<Val value="0x1">Independent watchdog is controlled by software</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STOP mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STOP mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>NRST_STBY</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">STANDBY mode on Domain 1 is entering with reset</Val>
+										<Val value="0x1">STANDBY mode on Domain 1 is entering without reset</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>VDDMMC_HSLV</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">I/O speed optimization at low-voltage disabled</Val>
+										<Val value="0x1">VDDMMC power rail operating below 2.5 V, I/O speed optimization at low-voltage feature allowed</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STOP mode</Val>
+										<Val value="0x1">Independent watchdog is running in STOP mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>FZ_IWDG_SDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Independent watchdog is freezed in STANDBY mode</Val>
+										<Val value="0x1">Independent watchdog is running in STANDBY mode</Val>
+									</Values>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>SECURITY</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Security feature disabled</Val>
+										<Val value="0x1">Security feature enabled</Val>
+									</Values>
+								</Bit>						
+								<Bit>
+									<Name>SWAP_BANK_OPT</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">after boot loading, no swap for user sectors</Val>
+										<Val value="0x1">after boot loading, user sectors swapped</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Boot address Option Bytes</Name>
+						<Field>
+							<Parameters name="FBOOT7_CUR" size="0x4" address="0x52002040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_CM7_ADD0</Name>
+									<Description>Define the boot address for Cortex-M7 when BOOT0=0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_CM7_ADD1</Name>
+									<Description>Define the boot address for Cortex-M7 when BOOT0=1</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FBOOT7_PRG" size="0x4" address="0x52002044"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_CM7_ADD0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+								<Bit>
+									<Name>BOOT_CM7_ADD1</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x10000"	offset="0x0"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FPRAR_CUR_A" size="0x4" address="0x52002028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START1</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END1</Name>
+									<Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_PRG_A" size="0x4" address="0x5200202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START1</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END1</Name>
+									<Description>Flash Bank 1 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP1 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_CUR_B" size="0x4" address="0x52002128"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START2</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END2</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FPRAR_PRG_B" size="0x4" address="0x5200212C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PROT_AREA_START2</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit>
+									<Name>PROT_AREA_END2</Name>
+									<Description>Flash Bank 2 PCROP End address (excluded). Deactivation of PCROP can be done by enbaling DMEP2 bit and changing RDP from level 1 to level 0 while putting end address greater than start address</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit>
+									<Name>DMEP2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 PCROP zone is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 PCROP zone is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Protection</Name>
+						<Field>
+							<Parameters name="FSCAR_CUR_A" size="0x4" address="0x52002030"/>
+							<AssignedBits>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_START1</Name>
+									<Description>Flash Bank 1 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_END1</Name>
+									<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>DMES1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_PRG_A" size="0x4" address="0x52002034"/>
+							<AssignedBits>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_START1</Name>
+									<Description>Flash Bank 1 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08000000"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_END1</Name>
+									<Description>Flash Bank 1 secure area end address. If this address is equal to SEC_AREA_START1, the whole bank 1 is secure protected.If this address is lower than SEC_AREA_START1, no protection is set on bank 1.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x080000FF"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>DMES1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 1 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 1 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_CUR_B" size="0x4" address="0x52002130"/>
+							<AssignedBits>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_START2</Name>
+									<Description>Flash Bank 2 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_END2</Name>
+									<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>R</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>DMES2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FSCAR_PRG_B" size="0x4" address="0x52002134"/>
+							<AssignedBits>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_START2</Name>
+									<Description>Flash Bank 2 secure area start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x08100000"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>SEC_AREA_END2</Name>
+									<Description>Flash Bank 2 secure area end address. If this address is equal to SEC_AREA_START2, the whole bank 2 is secure protected.If this address is lower than SEC_AREA_START2, no protection is set on bank 2.</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>W</Access>
+									<Equation	multiplier="0x100"	offset="0x081000FF"/>
+								</Bit>
+								<Bit	config="0,10">
+									<Name>DMES2</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Flash Bank 2 secure area is kept when RDP level regression (change from level 1 to 0) occurs</Val>
+										<Val value="0x1">Flash Bank 2 secure area is erased when RDP level regression (change from level 1 to 0) occurs</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>DTCM RAM Protection</Name>
+						<Field>
+							<Parameters name="FOPTSR_CUR" size="0x4" address="0x5200201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ST_RAM_SIZE</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">2 KB</Val>
+										<Val value="0x1">4 KB</Val>
+										<Val value="0x2">8 KB</Val>
+										<Val value="0x3">16 KB</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FOPTSR_PRG" size="0x4" address="0x52002020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ST_RAM_SIZE</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">2 KB</Val>
+										<Val value="0x1">4 KB</Val>
+										<Val value="0x2">8 KB</Val>
+										<Val value="0x3">16 KB</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FWPSN_CUR_A" size="0x4" address="0x52002038"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_PRG_A" size="0x4" address="0x5200203C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_CUR_B" size="0x4" address="0x52002138"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FWPSN_PRG_B" size="0x4" address="0x5200213C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nWRP32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active</Val>
+										<Val value="0x1">Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x417 -->
+	<Device>
+		<DeviceID>0x417</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+</CPU>
+		<Name>STM32L05x/L06x/L010</Name>
+		<Series>STM32L0</Series>
+		<Description>ARM 32-bit Cortex-M0+ based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x2000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x2000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF8007C" default="0x10000"/>
+				<!-- 128KB single Bank -->
+				<Configuration>
+					<Parameters name="64 Kbytes Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x80" address="0x08000000"	occurence="0x200"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1KB single Bank -->
+				<Configuration>
+					<Parameters name=" 2 Kbytes Data EEPROM" size="0x800" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x800" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 20 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 20 Bytes Data MirrorOptionBytes" size="0x14" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x14" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRPOT1</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRPOT1</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRPOT1</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+				<Parameters name="Bank 2" size="0x14" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRPOT1</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>	
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x447 -->
+	<Device>
+		<DeviceID>0x447</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+</CPU>
+		<Name>STM32L07x/L08x/L010</Name>
+		<Series>STM32L0</Series>
+		<Description>ARM 32-bit Cortex-M0+ based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x0"/>
+					</WPRMOD>
+					<ValueLine>
+						<ReadRegister address="0x1FF8007C"	mask="0x0000FFFF"	value="0x0080"/>
+					</ValueLine>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x100"/>
+					</WPRMOD>
+					<ValueLine>
+						<ReadRegister address="0x1FF8007C"	mask="0x0000FFFF"	value="0x0080"/>
+					</ValueLine>
+				</Configuration>
+				<Configuration	number="0x2"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x3"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</WPRMOD>
+					<ValueLine>
+						<ReadRegister address="0x1FF00000"	mask="0xFFFFFFFF"	value="0x20001290"/>
+					</ValueLine>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</WPRMOD>
+					<ValueLine>
+						<ReadRegister address="0x1FF00000"	mask="0xFFFFFFFF"	value="0x20001290"/>
+					</ValueLine>
+				</Configuration>
+				<Configuration	number="0x2"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x3"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 20 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x5000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x5000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF8007C" default="0x30000"/>
+				<!-- 128KB single Bank -->
+				<Configuration config="0,1">
+					<Parameters name="128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x80" address="0x08000000"	occurence="0x400"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3">
+					<Parameters name="192 Kbytes Embedded Flash" size="0x30000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x80" address="0x08000000"	occurence="0x600"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1KB single Bank -->
+				<Configuration>
+					<Parameters name=" 2 Kbytes Data EEPROM" size="0x1800" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0xC00" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="EEPROM2" size="0xC00" address="0x08080C00"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 20 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 20 Bytes Data MirrorOptionBytes" size="0x14" address="0x1FF80000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x14" address="0x1FF80000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Boot from flash bank 1</Val>
+										<Val value="0x1">boot from flash bank 2</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPROT1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRPROT2" size="0x4" address="0x40022080"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x14" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Boot from flash bank 1</Val>
+										<Val value="0x1">boot from flash bank 2</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPROT11" size="0x4" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRPROT12" size="0x4" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRPROT2" size="0x4" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+				<Parameters name="Bank 1" size="0x14" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from flash bank 1</Val>
+										<Val value="0x1">boot from flash bank 2</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPROT11" size="0x4" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRPROT12" size="0x4" address="0x1FF8000C"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRPROT2" size="0x4" address="0x1FF80010"/>
+							<AssignedBits>
+								<Bit config="0,2">
+									<Name>WRPOT32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1,3">
+									<Name>WRPOT32</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>	
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x430 -->
+	<Device>
+		<DeviceID>0x430</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F101/F103 XL-density</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x18000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x18000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x100000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 1 Mbytes Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector256" size="0x800" address="0x08080000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">The device will boot from Flash memory bank 2 when boot pins are set in user Flash position</Val>
+										<Val value="0x1">The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default)</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">The device will boot from Flash memory bank 2 when boot pins are set in user Flash position</Val>
+										<Val value="0x1">The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default)</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">The device will boot from Flash memory bank 2 when boot pins are set in user Flash position</Val>
+										<Val value="0x1">The device will boot from Flash memory bank 1 when boot pins are set in user Flash position (default)</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x410 -->
+	<Device>
+		<DeviceID>0x410</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F101/F102/F103 Medium-density</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x5000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x5000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x20000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x400" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x414 -->
+	<Device>
+		<DeviceID>0x414</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F101/F103 High-density</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x412 -->
+	<Device>
+		<DeviceID>0x412</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F101/F102/F103 Low-density</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x2800" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x2800" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x8000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 32 Kbytes Embedded Flash" size="0x8000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x400" address="0x08000000"	occurence="0x20"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x418 -->
+	<Device>
+		<DeviceID>0x418</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F105/F107 Connectivity Line</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x40000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 256 Kbytes Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x428 -->
+	<Device>
+		<DeviceID>0x428</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F100 High-density Value Line</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x80000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 512 Kbytes Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x420 -->
+	<Device>
+		<DeviceID>0x420</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M3</CPU>
+		<Name>STM32F100 Low/Medium density Value Line</Name>
+		<Series>STM32F1</Series>
+		<Description>ARM 32-bit Cortex-M3 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration>
+					<Parameters name="SRAM" size="0x2000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x2000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFFF7E0" default="0x20000"/>
+				<!-- 512KB single Bank -->
+				<Configuration>
+					<Parameters name=" 128 Kbytes Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x400" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 16 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 16 Bytes Data MirrorOptionBytes" size="0x10" address="0x1FFFF800"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x10" address="0x1FFFF800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>				
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x8" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0">Flash memory is not read-protected.</Val>
+										<Val value="1">Flash memory is read-protected.</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>							
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x10" address="0x1FFFF800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xA5">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USR_RDP" size="0x4" address="0x1FFFF800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware watchdog</Val>
+										<Val value="0x1">Software watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Data</Name>
+						<Field>
+							<Parameters name="USR_DATA" size="0x4" address="0x1FFFF804"/>
+							<AssignedBits>
+								<Bit>
+									<Name>Data0</Name>
+									<Description>User data 0 (8-bit)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Data1</Name>
+									<Description>User data 1 (8-bit)</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP_0_1" size="0x4" address="0x1FFFF808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP0</Name>
+									<!--<Description>One bit of the user option bytes WRPx is used to protect 2 pages of 2 Kbytes in the main memory block. However, bit 7 of WRP3 write protects pages 62 to 511.</Description>-->
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP8</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="WRP_2_3" size="0x4" address="0x1FFFF80C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP16</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WRP24</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection active on this sector</Val>
+										<Val value="0x1">Write protection not active on this sector</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x470  -->
+	<Device>
+		<DeviceID>0x470</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L4Rxxx/STM32L4Sxxx</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">	
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x800"/> </flashSize>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x1">	
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x800"/> </flashSize>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x2">	
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x3">	
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x4">	
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x5">	
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x6">	
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x7">	
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x8">	
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x9">	
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0xA">	
+					<dummy> <ReadRegister address="0x20000000"	mask="0" value="0"/> </dummy>
+				</Configuration>
+			</Interface>	
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">	
+					<DBANK reference="0x0"> <ReadRegister address="0x1FF00000"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x1">	
+					<DBANK reference="0x1"> <ReadRegister address="0x1FF00000"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0xA">	
+					<dummy> <ReadRegister address="0x1FF00000"	mask="0"	value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x30000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x30000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x200000"/>
+				<Configuration config="0,2,3,6,9"> <!-- 2MB Single Bank -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1,4,5,7,8"> <!-- 2MB dual Bank -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector256" size="0x1000" address="0x08100000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2"> <!-- 2MB dual Bank -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector256" size="0x2000" address="0x08100000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 64 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 64 Bytes Data MirrorOptionBytes" size="0x40" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x24" address="0x1FF00000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x1C" address="0x1FF01008"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit config="2,3,4,5,6,7,8,9,10">
+									<Name>DB1M</Name>
+									<Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
+										<Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>This bit can only be written when PCROPA/B is disabled</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory.</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description>SRAM2 parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description>SRAM2 Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x40022044"/>
+					<Category>
+						<Name>PCROP Protection  (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+								<Bit config="0,10"> <!-- 2M whith offset 1M></!-->
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3"> <!-- 1M whith offset 512K></!-->
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9"> <!-- 512K whith offset 256K></!-->
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x16"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x16"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x16"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x8"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x8"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x40022050"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FF00000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FF00000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FF00000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FF00000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit config="10">
+									<Name>DB1M</Name>
+									<Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
+										<Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>This bit can only be written when PCROPA/B is disabled.</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FF00008"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x16"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FF00010"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x16"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FF00018"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FF00020"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x1C" address="0x1FF01008"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x1FF01008"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x16"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08100000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x1FF01010"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x16"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08100000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x1FF01018"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x1FF01020"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+
+	<!-- Device: 0x471  -->
+	<Device>
+		<DeviceID>0x471</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M4</CPU>
+		<Name>STM32L4Pxxx/STM32L4Qxxx</Name>
+		<Series>STM32L4</Series>
+		<Description>ARM 32-bit Cortex-M4 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x800"/> </flashSize>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x1">
+					<flashSize> <!-- 2M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x800"/> </flashSize>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x2">
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x3">
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x4">
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x5">
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x6">
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x7">
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x0"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x0"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x8">
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x1"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x9">
+					<flashSize> <!-- 512K --><ReadRegister address="0x1FFF75E0"	mask="0xFFFF"	value="0x400"/> </flashSize>
+					<DB1M reference="0x1"> <ReadRegister address="0x40022020"	mask="0x200000"	value="0x200000"/> </DB1M>
+					<DBANK reference="0x0"> <ReadRegister address="0x40022020"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0xA">
+					<flashSize> <!-- 1M --><ReadRegister address="0x1FFF0000"	mask="0xFFFFFFFF"	value="0XFFFFFFFF"/> </flashSize>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<DBANK reference="0x0"> <ReadRegister address="0x1FF00000"	mask="0x400000"	value="0x0"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0x1">
+					<DBANK reference="0x1"> <ReadRegister address="0x1FF00000"	mask="0x400000"	value="0x400000"/> </DBANK>
+				</Configuration>
+				<Configuration	number="0xA">
+					<dummy> <ReadRegister address="0x1FF00000"	mask="0"	value="0"/> </dummy>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x30000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x30000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x100000"/>
+				<Configuration config="0,2,3,6,9"> <!-- 2MB Single Bank -->
+					<Parameters name=" 1 Mbyte Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1,4,5,7,8"> <!-- 1MB dual Bank -->
+					<Parameters name=" 1 Mbyte Embedded Flash" size="0x100000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x1000" address="0x08080000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2"> <!-- 2MB dual Bank -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector256" size="0x2000" address="0x08100000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 64 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 64 Bytes Data MirrorOptionBytes" size="0x40" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x24" address="0x1FF00000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x1C" address="0x1FF01008"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x30" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit config="2,3,4,5,6,7,8,9,10">
+									<Name>DB1M</Name>
+									<Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
+										<Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>This bit can only be written when PCROPA/B is disabled</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory.</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
+										<Val value="0x1">Boot from system memory when BOOT0=1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description>SRAM2 parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description>SRAM2 Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,2,3,6,9,10">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1,4,5,7,8">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x24" address="0x40022030"/>
+					<Category>
+						<Name>PCROP Protection  (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+								<Bit config="0,10"> <!-- 2M whith offset 1M></!-->
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3"> <!-- 1M whith offset 512K></!-->
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,9"> <!-- 512K whith offset 256K></!-->
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x16"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x16"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x16"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x8"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x11</BitWidth>
+									<Access>RW</Access>
+									<Equation  multiplier="0x8"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x40022050"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2,3">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,9">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4,5">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="7,8">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x24" address="0x1FF00000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FF00000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FF00000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FF00000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BFB2</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Dual-bank boot disable</Val>
+										<Val value="0x1">Dual-bank boot enable</Val>
+									</Values>
+								</Bit>
+								<Bit config="10">
+									<Name>DB1M</Name>
+									<Description>Dual-Bank on 1 MB Flash or 512 KB Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">1 MB or 512 Kb single Flash: contiguous address in bank1</Val>
+										<Val value="0x1">1 MB or 512 Kb dual-bank Flash with contiguous addresses. When DB1M is set, a hard Fault is generated when the requested address goes over 1 MB or 512 Kb.</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>This bit can only be written when PCROPA/B is disabled.</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
+										<Val value="0x1">BOOT0 = 0, boot from main flash memory</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FF00008"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP1_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	 multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FF00010"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP1_END</Name>
+									<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 1)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FF00018"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FF00020"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x24" address="0x1FF01000"/>
+					<Category>
+						<Name>PCROP Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP2SR" size="0x4" address="0x1FF01008"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_STRT</Name>
+									<Description>Flash Bank 2 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP2ER" size="0x4" address="0x1FF01010"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x10"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>PCROP2_END</Name>
+									<Description>Flash Bank 2 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x10</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection (Bank 2)</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x1FF01018"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2A_END</Name>
+									<Description>The address of last page of the Bank 2 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x1FF01020"/>
+							<AssignedBits>
+								<Bit config="0,10">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_STRT</Name>
+									<Description>The address of first page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+								<Bit config="0,10">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="1">
+									<Name>WRP2B_END</Name>
+									<Description>The address of last page of the Bank 2 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08080000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x472  -->
+	<Device>
+		<DeviceID>0x472</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M33</CPU>
+		<Name>STM32L5xx</Name>
+		<Series>STM32L5</Series>
+		<Description>ARM 32-bit Cortex-M33 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0xA">	<!-- Single Bank non secure -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+					<valueLine> <ReadRegister address="0x0BFA05E0"	mask="0x00000FFF"	value="0x100"/> </valueLine>
+				</Configuration>
+				<Configuration	number="0xB">	<!-- Dual Bank non secure -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+					<valueLine> <ReadRegister address="0x0BFA05E0"	mask="0x00000FFF"	value="0x100"/> </valueLine>
+				</Configuration>
+				<Configuration	number="0xC">	<!-- Single Bank secure -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+					<RDP reference="0x1"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>
+					<valueLine> <ReadRegister address="0x0BFA05E0"	mask="0x00000FFF"	value="0x100"/> </valueLine>
+				</Configuration>
+				<Configuration	number="0xD">	<!-- Dual Bank secure -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+					<RDP reference="0x1"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>
+					<valueLine> <ReadRegister address="0x0BFA05E0"	mask="0x00000FFF"	value="0x100"/> </valueLine>
+				</Configuration>
+				<Configuration	number="0xE">	<!-- Single Bank secure + RDP -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+					<valueLine> <ReadRegister address="0x0BFA05E0"	mask="0x00000FFF"	value="0x100"/> </valueLine>
+					<!-- <RDP reference="0x0"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>					 -->
+				</Configuration>
+				<Configuration	number="0xF">	<!-- Dual Bank secure + RDP -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </TZEN>
+					<valueLine> <ReadRegister address="0x0BFA05E0"	mask="0x00000FFF"	value="0x100"/> </valueLine>
+					<!-- <RDP reference="0x0"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP> -->
+				</Configuration>
+				<Configuration	number="0x0">	<!-- Single Bank non secure -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>  					
+				</Configuration>
+				<Configuration	number="0x1">	<!-- Dual Bank non secure -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>  
+				</Configuration>
+				<Configuration	number="0x2">	<!-- Single Bank secure -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK> 
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN> 
+					<RDP reference="0x1"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>					
+				</Configuration>
+				<Configuration	number="0x3">	<!-- Dual Bank secure -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </TZEN>
+					<RDP reference="0x1"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>
+				</Configuration>
+				<Configuration	number="0x4">	<!-- Single Bank secure + RDP -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK> 
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN> 
+					<!-- <RDP reference="0x0"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>					 -->
+				</Configuration>
+				<Configuration	number="0x5">	<!-- Dual Bank secure + RDP -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+					<!-- <RDP reference="0x0"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP> -->
+				</Configuration>
+			</Interface>	
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x6">	<!-- Single Bank Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x7">	<!-- Dual Bank Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x8">	<!-- Single Bank non Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x9">	<!-- Dual Bank non Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration config="0,1,6,7,8,9,10,11">
+					<Parameters name="SRAM" size="0x40000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x40000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="4,5,14,15">
+					<Parameters name="SRAM" size="0x10000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3,12,13">
+					<Parameters name="SRAM" size="0x10000" address="0x20018000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x10000" address="0x20030000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x0BFA05E0" default="0x80000"/>
+				<Configuration config="0,4,6,8"> <!-- Single Bank -->
+					<Parameters name=" 512 Kbyte Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="10,14"> <!-- Single Bank -->
+					<Parameters name=" 256 Kbyte Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1,5,7,9"> <!-- dual Bank -->
+					<Parameters name=" 512 Kbyte Embedded Flash" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x08040000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="11,15"> <!-- dual Bank -->
+					<Parameters name=" 256 Kbyte Embedded Flash" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector64" size="0x800" address="0x08020000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2"> <!-- Single Bank secure -->
+					<Parameters name=" 512 Kbyte Embedded Flash" size="0x80000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x0c000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="12"> <!-- Single Bank secure -->
+					<Parameters name=" 256 Kbyte Embedded Flash" size="0x40000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x0c000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="3"> <!-- dual Bank secure -->
+					<Parameters name=" 512 Kbyte Embedded Flash" size="0x80000" address="0x0c000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x0c000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x0c040000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="13"> <!-- dual Bank secure -->
+					<Parameters name=" 256 Kbyte Embedded Flash" size="0x40000" address="0x0c000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x0c000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector64" size="0x800" address="0x0c020000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration config="2,4">
+					<Parameters name=" 512 Kbytes Data EEPROM" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="12,14">
+					<Parameters name=" 256 Kbytes Data EEPROM" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="3,5">
+					<Parameters name=" 512 Kbytes Data EEPROM" size="0x80000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x08040000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="15,13">
+					<Parameters name=" 256 Kbytes Data EEPROM" size="0x40000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x08020000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- Dummy Config Just to avoid crash when TZEN=0 -->
+				<Configuration config="1">
+					<Parameters name=" 512 Kbytes Data EEPROM" size="0x80000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x0C000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x0C040000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="11">
+					<Parameters name=" 256 Kbytes Data EEPROM" size="0x40000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x0C000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x800" address="0x0C020000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="0">
+					<Parameters name=" 512 Kbytes Data EEPROM" size="0x80000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x0C000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="10">
+					<Parameters name=" 256 Kbytes Data EEPROM" size="0x40000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x1000" address="0x0C000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x10000" address="0x0BFA0000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x10000" address="0x0BFA0000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<!--Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access-->
+				<!-- 48 Bytes single bank -->
+				<!--Configuration>
+					<Parameters name=" 48 Bytes Data MirrorOptionBytes" size="0x30" address="0x40022040"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="MirrorOptionBytes">
+						<Field>
+							<Parameters name="MirrorOptionBytes" size="0x30" address="0x40022040"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral-->
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Configuration config="4,5,14,15">
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x28" address="0x40022040"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
+											<Val value="0xDC">Level 1, read protection of memories</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SWAP_BANK</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+										<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DB256</Name>
+									<Description>Dual-Bank on 256 Kb Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
+										<Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description>SRAM2 parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description>SRAM2 Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>nBOOT0 option bit</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>PA15_PUPEN</Name>
+									<Description>PA15 pull-up enable</Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+										<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+									</Values>
+								</Bit>	
+								<Bit>
+									<Name>TZEN</Name>
+									<Description>Global TrustZone security enable</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Global TrustZone security disabled</Val>
+										<Val value="0x1">Global TrustZone security enabled</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022054"/>
+								<AssignedBits>
+									<Bit>
+										<Name>HDP1EN</Name>
+										<Description>Hide protection first area enable</Description>
+										<BitOffset>0x1F</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">No HDP area 1</Val>
+											<Val value="0x1">HDP first area is enabled</Val>
+										</Values>
+									</Bit>
+									<Bit config="4,14">
+										<Name>HDP1_PEND</Name>
+										<Description>End page of first hide protection area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	 multiplier="0x4"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>HDP1_PEND</Name>
+										<Description>End page of first hide protection area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	 multiplier="0x2"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/>
+								<AssignedBits>
+									<Bit config="4,14,15,5">
+										<Name>HDP2EN</Name>
+										<Description>Hide protection second area enable</Description>
+										<BitOffset>0x1F</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">No HDP area 2</Val>
+											<Val value="0x1">HDP second area is enabled</Val>
+										</Values>
+									</Bit>
+									<Bit config="4,14">
+										<Name>HDP2_PEND</Name>
+										<Description>End page of second hide protection area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	 multiplier="0x4"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>HDP2_PEND</Name>
+										<Description>End page of second hide protection area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	 multiplier="0x2"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+							<Bit>
+									<Name>NSBOOTADD0</Name>
+									<Description>Non-secure Boot base address 0</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+							<Bit>
+									<Name>NSBOOTADD1</Name>
+									<Description>Non-secure Boot base address 1</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>	
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+							<Bit>
+									<Name>SECBOOTADD0</Name>
+									<Description>Secure boot base address 0</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>	
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+							<Field>
+							<Parameters name="BOOT_LOCK" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from base address memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+						<Name>Secure Area 1</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM1R1" size="0x4" address="0x40022050"/>
+								<AssignedBits>
+									<Bit config="4,14">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="4,14">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+					</Category>
+					<!-- <Category> -->
+							<!-- <Name>PCROP Protection (Bank 1)</Name> -->
+							<!-- <Field> -->
+								<!-- <Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022054"/> -->
+								<!-- <AssignedBits> -->
+									<!-- <Bit config="4"> -->
+										<!-- <Name>PCROP1_PSTRT</Name> -->
+										<!-- <Description>Start page of first PCROP area</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="5"> -->
+										<!-- <Name>PCROP1_STRT</Name> -->
+										<!-- <Description>Flash Bank 1 PCROP start address</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="4"> -->
+										<!-- <Name>HDP1_PEND</Name> -->
+										<!-- <Description>End page of first hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="5"> -->
+										<!-- <Name>HDP1_PEND</Name> -->
+										<!-- <Description>End page of first hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit> -->
+										<!-- <Name>PCROP1EN</Name> -->
+										<!-- <Description>PCROP1 area enable</Description> -->
+										<!-- <BitOffset>0xF</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">PCROP1 area is disabled</Val> -->
+											<!-- <Val value="0x1">PCROP1 area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+									<!-- <Bit> -->
+										<!-- <Name>HDP1EN</Name> -->
+										<!-- <Description>Hide protection first area enable</Description> -->
+										<!-- <BitOffset>0x1F</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">No HDP area 1</Val> -->
+											<!-- <Val value="0x1">HDP first area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+								<!-- </AssignedBits> -->
+							<!-- </Field> -->
+						<!-- </Category> -->
+					<Category>
+							<Name>Write Protection 1</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x40022058"/>
+							<AssignedBits>
+									<Bit config="4,14">
+									<Name>WRP1A_PSTRT</Name>
+									<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="5,15">
+									<Name>WRP1A_PSTRT</Name>
+									<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="4,14">
+									<Name>WRP1A_PEND</Name>
+									<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="5,15">
+									<Name>WRP1A_PEND</Name>
+									<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x4002205C"/>
+							<AssignedBits>
+									<Bit config="4,14">
+									<Name>WRP1B_PSTRT</Name>
+									<Description>Bank 1 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="5,15">
+									<Name>WRP1B_PSTRT</Name>
+									<Description>Bank 1 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="4,14">
+									<Name>WRP1B_PEND</Name>
+									<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="5,15">
+									<Name>WRP1B_PEND</Name>
+									<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+					<Bank interface="JTAG_SWD">
+						<Parameters name="Bank 2" size="0x10" address="0x40022060"/>
+						<Category>
+						<Name>Secure Area 2</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022060"/>
+								<AssignedBits>
+									<Bit config="4,14">
+										<Name>SECWM2_PSTRT</Name>
+										<Description>Start page of second secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>SECWM2_PSTRT</Name>
+										<Description>Start page of second secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="4,14">
+										<Name>SECWM2_PEND</Name>
+										<Description>End page of second secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>SECWM2_PEND</Name>
+										<Description>End page of second secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<!-- <Category> -->
+							<!-- <Name>PCROP Protection (Bank 2)</Name> -->
+							<!-- <Field> -->
+								<!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/> -->
+								<!-- <AssignedBits> -->
+									<!-- <Bit config="4"> -->
+										<!-- <Name>PCROP2_PSTRT</Name> -->
+										<!-- <Description>Start page of first PCROP area</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="5"> -->
+										<!-- <Name>PCROP2_STRT</Name> -->
+										<!-- <Description>Flash Bank 2 PCROP start address</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="4"> -->
+										<!-- <Name>HDP2_PEND</Name> -->
+										<!-- <Description>End page of second hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="5"> -->
+										<!-- <Name>HDP2_PEND</Name> -->
+										<!-- <Description>End page of second hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="4"> -->
+										<!-- <Name>PCROP2EN</Name> -->
+										<!-- <Description>PCROP2 area enable</Description> -->
+										<!-- <BitOffset>0xF</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
+											<!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="4,5"> -->
+										<!-- <Name>HDP2EN</Name> -->
+										<!-- <Description>Hide protection second area enable</Description> -->
+										<!-- <BitOffset>0x1F</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">No HDP area 2</Val> -->
+											<!-- <Val value="0x1">HDP second area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+								<!-- </AssignedBits> -->
+							<!-- </Field> -->
+						<!-- </Category> -->
+						<Category>
+							<Name>Write Protection 2</Name>
+							<Field>
+								<Parameters name="FLASH_WRP2AR" size="0x4" address="0x40022068"/>
+								<AssignedBits>
+									<Bit config="4,14">
+										<Name>WRP2A_PSTRT</Name>
+										<Description>Bank 2 WPR first area "A" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08040000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>WRP2A_PSTRT</Name>
+										<Description>Bank 2 WPR first area "A" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08040000"/>
+									</Bit>
+									<Bit config="4,14">
+										<Name>WRP2A_PEND</Name>
+										<Description>Bank 2 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08040000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>WRP2A_PEND</Name>
+										<Description>Bank 2 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08040000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_WRP2BR" size="0x4" address="0x4002206C"/>
+								<AssignedBits>
+									<Bit config="4,14">
+										<Name>WRP2B_PSTRT</Name>
+										<Description>Bank 2 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08040000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>WRP2B_PSTRT</Name>
+										<Description>Bank 2 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08040000"/>
+									</Bit>
+									<Bit config="4,14">
+										<Name>WRP2B_PEND</Name>
+										<Description>Bank 2 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08040000"/>
+									</Bit>
+									<Bit config="5,15">
+										<Name>WRP2B_PEND</Name>
+										<Description>Bank 2 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08040000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+					</Bank>
+			</Configuration>
+				<Configuration config="0,1,10,11">
+				<Bank interface="JTAG_SWD">
+						<Parameters name="Bank 1" size="0x20" address="0x40022040"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xDC">Level 1, read protection of memories</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SWAP_BANK</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+										<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DB256</Name>
+									<Description>Dual-Bank on 256 Kb Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
+										<Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+										<Val value="0x1">Dual bank mode with 64 bits data</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_PE</Name>
+									<Description>SRAM2 parity check enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description>SRAM2 Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>nBOOT0 option bit</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>PA15_PUPEN</Name>
+									<Description>PA15 pull-up enable</Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+										<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>TZEN</Name>
+									<Description>Global TrustZone security enable</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Global TrustZone security disabled</Val>
+										<Val value="0x1">Global TrustZone security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+							<Bit>
+									<Name>NSBOOTADD0</Name>
+									<Description>Non-secure Boot base address 0</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+							<Bit>
+									<Name>NSBOOTADD1</Name>
+									<Description>Non-secure Boot base address 1</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>	
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+							<Bit>
+									<Name>SECBOOTADD0</Name>
+									<Description>Secure boot base address 0</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>	
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+							<Field>
+							<Parameters name="BOOT_LOCK" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from base address memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+							<Name>Write Protection 1</Name>
+						<Field>
+								<Parameters name="FLASH_WRP1AR" size="0x4" address="0x40022058"/>
+							<AssignedBits>
+									<Bit config="0,10">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="1,11">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="0,10">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="1,11">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_WRP1BR" size="0x4" address="0x4002205C"/>
+								<AssignedBits>
+									<Bit config="0,10">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="1,11">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="0,10">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="1,11">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					</Bank>
+					<Bank interface="JTAG_SWD">
+							<Parameters name="Bank 2" size="0x10" address="0x40022060"/>
+							<!-- <Category> -->
+								<!-- <Name>PCROP Protection (Bank 2)</Name> -->
+								<!-- <Field> -->
+									<!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/> -->
+									<!-- <AssignedBits> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>PCROP2_PSTRT</Name> -->
+											<!-- <Description>Start page of first PCROP area</Description> -->
+											<!-- <BitOffset>0x0</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>PCROP2_STRT</Name> -->
+											<!-- <Description>Flash Bank 2 PCROP start address</Description> -->
+											<!-- <BitOffset>0x0</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="0"> -->
+											<!-- <Name>HDP2_PEND</Name> -->
+											<!-- <Description>End page of second hide protection area</Description> -->
+											<!-- <BitOffset>0x10</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>HDP2_PEND</Name> -->
+											<!-- <Description>End page of second hide protection area</Description> -->
+											<!-- <BitOffset>0x10</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>PCROP2EN</Name> -->
+											<!-- <Description>PCROP2 area enable</Description> -->
+											<!-- <BitOffset>0xF</BitOffset> -->
+											<!-- <BitWidth>0x1</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Values> -->
+												<!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
+												<!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
+											<!-- </Values> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>HDP2EN</Name> -->
+											<!-- <Description>Hide protection second area enable</Description> -->
+											<!-- <BitOffset>0x1F</BitOffset> -->
+											<!-- <BitWidth>0x1</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Values> -->
+												<!-- <Val value="0x0">No HDP area 2</Val> -->
+												<!-- <Val value="0x1">HDP second area is enabled</Val> -->
+											<!-- </Values> -->
+										<!-- </Bit> -->
+									<!-- </AssignedBits> -->
+								<!-- </Field> -->
+							<!-- </Category> -->
+					<Category>
+								<Name>Write Protection 2</Name>
+						<Field>
+									<Parameters name="FLASH_WRP2AR" size="0x4" address="0x40022068"/>
+							<AssignedBits>
+										<Bit config="0,10">
+											<Name>WRP2A_PSTRT</Name>
+											<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+										<Bit config="1,11">
+											<Name>WRP2A_PSTRT</Name>
+											<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+										<Bit config="0,10">
+											<Name>WRP2A_PEND</Name>
+											<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+										<Bit config="1,11">
+											<Name>WRP2A_PEND</Name>
+											<Description>Bank 2 WPR first area "A" end page</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x800"	offset="0x08040000"/>
+										</Bit>
+									</AssignedBits>
+								</Field>
+								<Field>
+									<Parameters name="FLASH_WRP2BR" size="0x4" address="0x4002206C"/>
+									<AssignedBits>
+										<Bit config="0,10">
+											<Name>WRP2B_PSTRT</Name>
+											<Description>Bank 2 WPR first area "B" start page</Description>
+											<BitOffset>0x0</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x1000"	offset="0x08040000"/>
+										</Bit>
+										<Bit config="1,11">
+											<Name>WRP2B_PSTRT</Name>
+											<Description>Bank 2 WPR first area "B" start page</Description>
+											<BitOffset>0x0</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x800"	offset="0x08040000"/>
+										</Bit>
+										<Bit config="0,10">
+											<Name>WRP2B_PEND</Name>
+											<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x1000"	offset="0x08040000"/>
+										</Bit>
+										<Bit config="1,11">
+											<Name>WRP2B_PEND</Name>
+											<Description>Bank 2 WPR first area "B" end page</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x800"	offset="0x08040000"/>
+										</Bit>
+									</AssignedBits>
+								</Field>
+							</Category>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3,12,13">
+					<Bank interface="JTAG_SWD">
+						<Parameters name="Bank 1" size="0x28" address="0x50022040"/>
+						<Category>
+							<Name>Read Out Protection</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x50022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>RDP</Name>
+										<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x8</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0xAA">Level 0, no protection</Val>
+											<Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
+											<Val value="0xDC">Level 1, read protection of memories</Val>
+											<Val value="0xCC">Level 2, chip protection</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>BOR Level</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x50022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>BOR_LEV</Name>
+										<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+										<BitOffset>0x8</BitOffset>
+										<BitWidth>0x3</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+											<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+											<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+											<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+											<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>User Configuration</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x50022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>nRST_STOP</Name>
+										<Description/>
+										<BitOffset>0xC</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Stop mode</Val>
+											<Val value="0x1">No reset generated when entering Stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_STDBY</Name>
+										<Description/>
+										<BitOffset>0xD</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Standby mode</Val>
+											<Val value="0x1">No reset generated when entering Standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_SHDW</Name>
+										<Description/>
+										<BitOffset>0xE</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+											<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware independant watchdog</Val>
+											<Val value="0x1">Software independant watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STOP</Name>
+										<Description/>
+										<BitOffset>0x11</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+											<Val value="0x1">IWDG counter active in stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STDBY</Name>
+										<Description/>
+										<BitOffset>0x12</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+											<Val value="0x1">IWDG counter active in standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>WWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x13</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware window watchdog</Val>
+											<Val value="0x1">Software window watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SWAP_BANK</Name>
+										<Description/>
+										<BitOffset>0x14</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+											<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>DB256</Name>
+										<Description>Dual-Bank on 256 Kb Flash memory devices</Description>
+										<BitOffset>0x15</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
+											<Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
+										</Values>
+								</Bit>
+								<Bit>
+										<Name>DBANK</Name>
+										<Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
+										<BitOffset>0x16</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+											<Val value="0x1">Dual bank mode with 64 bits data</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_PE</Name>
+										<Description>SRAM2 parity check enable</Description>
+										<BitOffset>0x18</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 parity check enable</Val>
+											<Val value="0x1">SRAM2 parity check disable</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_RST</Name>
+										<Description>SRAM2 Erase when system reset</Description>
+										<BitOffset>0x19</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+											<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nSWBOOT0</Name>
+										<Description>Software BOOT0</Description>
+										<BitOffset>0x1A</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+											<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nBOOT0</Name>
+										<Description>nBOOT0 option bit</Description>
+										<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+											<Val value="0x0">nBOOT0 = 0</Val>
+											<Val value="0x1">nBOOT0 = 1</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>PA15_PUPEN</Name>
+										<Description>PA15 pull-up enable</Description>
+										<BitOffset>0x1C</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+											<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+										<Name>TZEN</Name>
+										<Description>Global TrustZone security enable</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+											<Val value="0x0">Global TrustZone security disabled</Val>
+											<Val value="0x1">Global TrustZone security enabled</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x50022054"/>
+									<AssignedBits>
+										<Bit>
+											<Name>HDP1EN</Name>
+											<Description>Hide protection first area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 1</Val>
+												<Val value="0x1">HDP first area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="2,12">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="3,13">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R2" size="0x4" address="0x50022064"/>
+									<AssignedBits>
+										<Bit>
+											<Name>HDP2EN</Name>
+											<Description>Hide protection second area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 2</Val>
+												<Val value="0x1">HDP second area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="2,12">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="3,13">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x50022044"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD0</Name>
+										<Description>Non-secure Boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x50022048"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD1</Name>
+										<Description>Non-secure Boot base address 1</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x5002204C"/>
+								<AssignedBits>
+								<Bit>
+										<Name>SECBOOTADD0</Name>
+										<Description>Secure boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+							<Parameters name="BOOT_LOCK" size="0x4" address="0x5002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from base address memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Area 1</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM1R1" size="0x4" address="0x50022050"/>
+								<AssignedBits>
+									<Bit config="2,12">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="3,13">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="2,12">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="3,13">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<!-- <Category> -->
+							<!-- <Name>PCROP Protection (Bank 1)</Name> -->
+							<!-- <Field> -->
+								<!-- <Parameters name="FLASH_PCROP1SR" size="0x4" address="0x50022054"/> -->
+								<!-- <AssignedBits> -->
+									<!-- <Bit config="2"> -->
+										<!-- <Name>PCROP1_PSTRT</Name> -->
+										<!-- <Description>Start page of first PCROP area</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="3"> -->
+										<!-- <Name>PCROP1_STRT</Name> -->
+										<!-- <Description>Flash Bank 1 PCROP start address</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="2"> -->
+										<!-- <Name>HDP1_PEND</Name> -->
+										<!-- <Description>End page of first hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="3"> -->
+										<!-- <Name>HDP1_PEND</Name> -->
+										<!-- <Description>End page of first hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit> -->
+										<!-- <Name>PCROP1EN</Name> -->
+										<!-- <Description>PCROP1 area enable</Description> -->
+										<!-- <BitOffset>0xF</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">PCROP1 area is disabled</Val> -->
+											<!-- <Val value="0x1">PCROP1 area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+									<!-- <Bit> -->
+										<!-- <Name>HDP1EN</Name> -->
+										<!-- <Description>Hide protection first area enable</Description> -->
+										<!-- <BitOffset>0x1F</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">No HDP area 1</Val> -->
+											<!-- <Val value="0x1">HDP first area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+								<!-- </AssignedBits> -->
+							<!-- </Field> -->
+						<!-- </Category> -->
+						<Category>
+							<Name>Write Protection 1</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x50022058"/>
+							<AssignedBits>
+								<Bit config="2,12">
+									<Name>WRP1A_PSTRT</Name>
+									<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP1A_PSTRT</Name>
+									<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="2,12">
+									<Name>WRP1A_PEND</Name>
+									<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP1A_PEND</Name>
+									<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x5002205C"/>
+							<AssignedBits>
+								<Bit config="2,12">
+									<Name>WRP1B_PSTRT</Name>
+									<Description>Bank 1 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP1B_PSTRT</Name>
+									<Description>Bank 1 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="2,12">
+									<Name>WRP1B_PEND</Name>
+									<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP1B_PEND</Name>
+									<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x50022060"/>
+					<Category>
+					<Name>Secure Area 2</Name>
+						<Field>
+							<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x50022060"/>
+							<AssignedBits>
+								<Bit config="2,12">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="13">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08020000"/>
+								</Bit>
+								<Bit config="2,12">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<!-- <Category> -->
+						<!-- <Name>PCROP Protection (Bank 2)</Name> -->
+						<!-- <Field> -->
+							<!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x50022064"/> -->
+							<!-- <AssignedBits> -->
+								<!-- <Bit config="2"> -->
+									<!-- <Name>PCROP2_PSTRT</Name> -->
+									<!-- <Description>Start page of first PCROP area</Description> -->
+									<!-- <BitOffset>0x0</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="3"> -->
+									<!-- <Name>PCROP2_STRT</Name> -->
+									<!-- <Description>Flash Bank 2 PCROP start address</Description> -->
+									<!-- <BitOffset>0x0</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="2"> -->
+									<!-- <Name>HDP2_PEND</Name> -->
+									<!-- <Description>End page of second hide protection area</Description> -->
+									<!-- <BitOffset>0x10</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="3"> -->
+									<!-- <Name>HDP2_PEND</Name> -->
+									<!-- <Description>End page of second hide protection area</Description> -->
+									<!-- <BitOffset>0x10</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="2,3"> -->
+									<!-- <Name>PCROP2EN</Name> -->
+									<!-- <Description>PCROP2 area enable</Description> -->
+									<!-- <BitOffset>0xF</BitOffset> -->
+									<!-- <BitWidth>0x1</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Values> -->
+										<!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
+										<!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
+									<!-- </Values> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="2,3"> -->
+									<!-- <Name>HDP2EN</Name> -->
+									<!-- <Description>Hide protection second area enable</Description> -->
+									<!-- <BitOffset>0x1F</BitOffset> -->
+									<!-- <BitWidth>0x1</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Values> -->
+										<!-- <Val value="0x0">No HDP area 2</Val> -->
+										<!-- <Val value="0x1">HDP second area is enabled</Val> -->
+									<!-- </Values> -->
+								<!-- </Bit> -->
+							<!-- </AssignedBits> -->
+						<!-- </Field> -->
+					<!-- </Category> -->
+					<Category>
+						<Name>Write Protection 2</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x50022068"/>
+							<AssignedBits>
+								<Bit config="2,12">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="2,12">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x5002206C"/>
+							<AssignedBits>
+								<Bit config="2,12">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="2,12">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="3,13">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Configuration>
+				<Bank interface="Bootloader">
+						<Parameters name="Bank 1" size="0x30" address="0x40022040"/>
+						<Category>
+							<Name>Read Out Protection</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>RDP</Name>
+										<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x8</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0xAA">Level 0, no protection</Val>
+											<Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
+											<Val value="0xDC">Level 1, read protection of memories</Val>
+											<Val value="0xCC">Level 2, chip protection</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>BOR Level</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>BOR_LEV</Name>
+										<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+										<BitOffset>0x8</BitOffset>
+										<BitWidth>0x3</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+											<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+											<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+											<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+											<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>User Configuration</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>nRST_STOP</Name>
+										<Description/>
+										<BitOffset>0xC</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Stop mode</Val>
+											<Val value="0x1">No reset generated when entering Stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_STDBY</Name>
+										<Description/>
+										<BitOffset>0xD</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Standby mode</Val>
+											<Val value="0x1">No reset generated when entering Standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_SHDW</Name>
+										<Description/>
+										<BitOffset>0xE</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+											<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware independant watchdog</Val>
+											<Val value="0x1">Software independant watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STOP</Name>
+										<Description/>
+										<BitOffset>0x11</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+											<Val value="0x1">IWDG counter active in stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STDBY</Name>
+										<Description/>
+										<BitOffset>0x12</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+											<Val value="0x1">IWDG counter active in standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>WWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x13</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware window watchdog</Val>
+											<Val value="0x1">Software window watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SWAP_BANK</Name>
+										<Description/>
+										<BitOffset>0x14</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+											<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>DB256</Name>
+										<Description>Dual-Bank on 256 Kb Flash memory devices</Description>
+										<BitOffset>0x15</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
+											<Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>DBANK</Name>
+										<Description>This bit can only be written when all protection (secure, PCROP, HDP) are disabled</Description>
+										<BitOffset>0x16</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+											<Val value="0x1">Dual bank mode with 64 bits data</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_PE</Name>
+										<Description>SRAM2 parity check enable</Description>
+										<BitOffset>0x18</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 parity check enable</Val>
+											<Val value="0x1">SRAM2 parity check disable</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_RST</Name>
+										<Description>SRAM2 Erase when system reset</Description>
+										<BitOffset>0x19</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+											<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nSWBOOT0</Name>
+										<Description>Software BOOT0</Description>
+										<BitOffset>0x1A</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+											<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nBOOT0</Name>
+										<Description>nBOOT0 option bit</Description>
+										<BitOffset>0x1B</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">nBOOT0 = 0</Val>
+											<Val value="0x1">nBOOT0 = 1</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>PA15_PUPEN</Name>
+										<Description>PA15 pull-up enable</Description>
+										<BitOffset>0x1C</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+											<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>TZEN</Name>
+										<Description>Global TrustZone security enable</Description>
+										<BitOffset>0x1F</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Global TrustZone security disabled</Val>
+											<Val value="0x1">Global TrustZone security enabled</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022054"/>
+									<AssignedBits>
+										<Bit config="6,7,8,9">
+											<Name>HDP1EN</Name>
+											<Description>Hide protection first area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 1</Val>
+												<Val value="0x1">HDP first area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="6,8">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="7,9">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/>
+									<AssignedBits>
+										<Bit config="6,7,8,9">
+											<Name>HDP2EN</Name>
+											<Description>Hide protection second area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 2</Val>
+												<Val value="0x1">HDP second area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="6,8">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="7,9">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x40022044"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD0</Name>
+										<Description>Non-secure Boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x40022048"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD1</Name>
+										<Description>Non-secure Boot base address 1</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x4002204C"/>
+								<AssignedBits>
+								<Bit>
+										<Name>SECBOOTADD0</Name>
+										<Description>Secure boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+						<Name>Secure area 1</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM1R1" size="0x4" address="0x40022050"/>
+								<AssignedBits>
+									<Bit config="6,8">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="6,8">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>Write Protection 1</Name>
+							<Field>
+								<Parameters name="FLASH_WRP1AR" size="0x4" address="0x40022058"/>
+								<AssignedBits>
+									<Bit config="6,8">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="6,8">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_WRP1BR" size="0x4" address="0x4002205C"/>
+								<AssignedBits>
+									<Bit config="6,8">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="6,8">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+					<Category>
+					<Name>Secure area 2</Name>
+						<Field>
+							<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022060"/>
+							<AssignedBits>
+								<Bit config="6,8">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="6,8">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection 2</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x40022068"/>
+							<AssignedBits>
+								<Bit config="6,8">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="6,8">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x4002206C"/>
+							<AssignedBits>
+								<Bit config="6,8">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="6,8">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	<Device>
+		<DeviceID>0x482</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M33</CPU>
+		<Name>STM32U5xx</Name>
+		<Series>STM32U5</Series>
+		<Description>ARM 32-bit Cortex-M33 based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0">	<!-- Single Bank non secure -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x00200000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x1">	<!-- Dual Bank non secure -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x00200000"	value="0x00200000"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x2">	<!-- Single Bank secure + RDP=0xAA -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x00200000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+					<RDP reference="0x1"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>
+				</Configuration>
+				<Configuration	number="0x3">	<!-- Dual Bank secure + RDP=0xAA -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x00200000"	value="0x00200000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+					<RDP reference="0x1"> <ReadRegister address="0x40022040"	mask="0x000000FF"	value="0x000000AA"/> </RDP>
+				</Configuration>
+				<Configuration	number="0x4">	<!-- Single Bank secure -->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x00200000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x5">	<!-- Dual Bank secure -->
+					<DBANK reference="0x1"> <ReadRegister address="0x40022040"	mask="0x00200000"	value="0x00200000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x6">	<!-- Single Bank Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x7">	<!-- Dual Bank Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x1"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x80000000"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x8">	<!-- Single Bank non Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x0"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+				</Configuration>
+				<Configuration	number="0x9">	<!-- Dual Bank non Secure-->
+					<DBANK reference="0x0"> <ReadRegister address="0x40022040"	mask="0x400000"	value="0x400000"/> </DBANK>
+					<TZEN reference="0x0"> <ReadRegister address="0x40022040"	mask="0x80000000"	value="0x0"/> </TZEN>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration config="0,1,6,7,8,9">
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3,4,5">
+					<Parameters name="SRAM" size="0x8000" address="0x30000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x30000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x0BFA0764" default="0x200000"/>
+				<Configuration config="0"> <!-- Single Bank -->
+					<Parameters name=" 2048 Kbyte Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="1"> <!-- dual Bank -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x2000" address="0x08100000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,4"> <!-- Single Bank secure -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x0c000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="3,5"> <!-- dual Bank secure -->
+					<Parameters name=" 2 Mbyte Embedded Flash" size="0x200000" address="0x0c000000"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x10</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x0c000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x2000" address="0x0c100000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<Configuration config="2">
+					<Parameters name=" 2 Mbyte Data EEPROM" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x4000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<Configuration config="3">
+					<Parameters name=" 2 Mbyte Data EEPROM" size="0x200000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x2000" address="0x08100000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+				<!-- Dummy Config Just to avoid crash when TZEN=0 -->
+				<Configuration config="1">
+					<Parameters name=" 2 Mbyte Data EEPROM" size="0x200000" address="0x0C000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x2000" address="0x0C000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="sector128" size="0x2000" address="0x0C100000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 512 Bytes single bank -->
+				<Configuration>
+					<Parameters name=" 512 Bytes Data OTP" size="0x200" address="0x0BFA0000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x200" address="0x0BFA0000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Configuration config="0,1,4,5">
+				<Bank interface="JTAG_SWD">
+						<Parameters name="Bank 1" size="0x20" address="0x40022040"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
+										<Val value="0xDC">Level 1, read protection of memories</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x3</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+										<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+										<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+										<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+										<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xC</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM134_RST</Name>
+									<Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SWAP_BANK</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+										<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>DBANK</Name>
+									<Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Single bank Flash with contiguous address in bank 1</Val>
+										<Val value="0x1">Dual-bank Flash with contiguous addresses</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BKPRAM_ECC</Name>
+									<Description>SRAM2 parity check enable</Description>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Backup RAM ECC check enabled</Val>
+										<Val value="0x1">Backup RAM ECC check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM3_ECC</Name>
+									<Description>SRAM3 ECC detection and correction enable</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM3 ECC check enabled</Val>
+										<Val value="0x1">SRAM3 ECC check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_ECC</Name>
+									<Description>SRAM2 ECC detection and correction enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 ECC check enabled</Val>
+										<Val value="0x1">SRAM2 ECC check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_RST</Name>
+									<Description>SRAM2 Erase when system reset</Description>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nSWBOOT0</Name>
+									<Description>Software BOOT0</Description>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+										<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>nBOOT0 option bit</Description>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0 = 0</Val>
+										<Val value="0x1">nBOOT0 = 1</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>PA15_PUPEN</Name>
+									<Description>PA15 pull-up enable</Description>
+									<BitOffset>0x1C</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+										<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IO_VDD_HSLV</Name>
+									<Description>High-speed IO at low VDD voltage configuration bit</Description>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
+										<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IO_VDDIO2_HSLV</Name>
+									<Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
+										<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>TZEN</Name>
+									<Description>Global TrustZone security enable</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Global TrustZone security disabled</Val>
+										<Val value="0x1">Global TrustZone security enabled</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x40022044"/>
+							<AssignedBits>
+							<Bit>
+									<Name>NSBOOTADD0</Name>
+									<Description>Non-secure Boot base address 0</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x40022048"/>
+							<AssignedBits>
+							<Bit>
+									<Name>NSBOOTADD1</Name>
+									<Description>Non-secure Boot base address 1</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+								<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+							<Bit>
+									<Name>SECBOOTADD0</Name>
+									<Description>Secure boot base address 0</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x19</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x80"	offset="0x0000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+							<Field>
+							<Parameters name="BOOT_LOCK" size="0x4" address="0x4002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from base address memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Area 1</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM1R1" size="0x4" address="0x40022050"/>
+								<AssignedBits>
+									<Bit config="4">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x4000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x2000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="4">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x4000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="5">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x2000"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+					<Category>
+							<Name>Write Protection 1</Name>
+						<Field>
+								<Parameters name="FLASH_WRP1AR" size="0x4" address="0x40022058"/>
+							<AssignedBits>
+									<Bit config="0,4">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="1,5">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="0,4">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="1,5">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x2000"	offset="0x08000000"/>
+									</Bit>
+									<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 1 WPR first area A unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP1A start and end pages locked</Val>
+										<Val value="0x1">WRP1A start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_WRP1BR" size="0x4" address="0x4002205C"/>
+								<AssignedBits>
+									<Bit config="0,4">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x4000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="1,5">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x2000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="0,4">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x4000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="1,5">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 1 WPR first area B unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP1B start and end pages locked</Val>
+										<Val value="0x1">WRP1B start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					</Bank>
+					<Bank interface="JTAG_SWD">
+							<Parameters name="Bank 2" size="0x10" address="0x40022060"/>
+					<Category>
+					<Name>Secure Area 2</Name>
+						<Field>
+							<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022060"/>
+							<AssignedBits>
+								<Bit config="4">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="5">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="4">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="5">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+							<!-- <Category> -->
+								<!-- <Name>PCROP Protection (Bank 2)</Name> -->
+								<!-- <Field> -->
+									<!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/> -->
+									<!-- <AssignedBits> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>PCROP2_PSTRT</Name> -->
+											<!-- <Description>Start page of first PCROP area</Description> -->
+											<!-- <BitOffset>0x0</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>PCROP2_STRT</Name> -->
+											<!-- <Description>Flash Bank 2 PCROP start address</Description> -->
+											<!-- <BitOffset>0x0</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="0"> -->
+											<!-- <Name>HDP2_PEND</Name> -->
+											<!-- <Description>End page of second hide protection area</Description> -->
+											<!-- <BitOffset>0x10</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>HDP2_PEND</Name> -->
+											<!-- <Description>End page of second hide protection area</Description> -->
+											<!-- <BitOffset>0x10</BitOffset> -->
+											<!-- <BitWidth>0x7</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>PCROP2EN</Name> -->
+											<!-- <Description>PCROP2 area enable</Description> -->
+											<!-- <BitOffset>0xF</BitOffset> -->
+											<!-- <BitWidth>0x1</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Values> -->
+												<!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
+												<!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
+											<!-- </Values> -->
+										<!-- </Bit> -->
+										<!-- <Bit config="1"> -->
+											<!-- <Name>HDP2EN</Name> -->
+											<!-- <Description>Hide protection second area enable</Description> -->
+											<!-- <BitOffset>0x1F</BitOffset> -->
+											<!-- <BitWidth>0x1</BitWidth> -->
+											<!-- <Access>RW</Access> -->
+											<!-- <Values> -->
+												<!-- <Val value="0x0">No HDP area 2</Val> -->
+												<!-- <Val value="0x1">HDP second area is enabled</Val> -->
+											<!-- </Values> -->
+										<!-- </Bit> -->
+									<!-- </AssignedBits> -->
+								<!-- </Field> -->
+							<!-- </Category> -->
+							<Category>
+								<Name>Write Protection 2</Name>
+							<Field>
+									<Parameters name="FLASH_WRP2AR" size="0x4" address="0x40022068"/>
+									<AssignedBits>
+										<Bit config="0,4">
+											<Name>WRP2A_PSTRT</Name>
+											<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+									<Bit config="1,5">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+									<Bit config="0,4">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+										<Bit config="1,5">
+											<Name>WRP2A_PEND</Name>
+											<Description>Bank 2 WPR first area "A" end page</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x2000"	offset="0x08100000"/>
+										</Bit>
+								<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 2 WPR first area A unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP2A start and end pages locked</Val>
+										<Val value="0x1">WRP2A start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+									</AssignedBits>
+								</Field>
+								<Field>
+									<Parameters name="FLASH_WRP2BR" size="0x4" address="0x4002206C"/>
+									<AssignedBits>
+										<Bit config="0,4">
+											<Name>WRP2B_PSTRT</Name>
+											<Description>Bank 2 WPR first area "B" start page</Description>
+											<BitOffset>0x0</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x4000"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="1,5">
+											<Name>WRP2B_PSTRT</Name>
+											<Description>Bank 2 WPR first area "B" start page</Description>
+											<BitOffset>0x0</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x2000"	offset="0x08100000"/>
+										</Bit>
+										<Bit config="0,4">
+											<Name>WRP2B_PEND</Name>
+											<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+											<Equation	multiplier="0x4000"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="1,5">
+											<Name>WRP2B_PEND</Name>
+											<Description>Bank 2 WPR first area "B" end page</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	multiplier="0x2000"	offset="0x08100000"/>
+										</Bit>
+									<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 2 WPR first area B unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP2B start and end pages locked</Val>
+										<Val value="0x1">WRP2B start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+									</AssignedBits>
+								</Field>
+							</Category>
+					</Bank>
+				</Configuration>
+				<Configuration config="2,3">
+					<Bank interface="JTAG_SWD">
+						<Parameters name="Bank 1" size="0x28" address="0x50022040"/>
+						<Category>
+							<Name>Read Out Protection</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x50022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>RDP</Name>
+										<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x8</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0xAA">Level 0, no protection</Val>
+											<Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
+											<Val value="0xDC">Level 1, read protection of memories</Val>
+											<Val value="0xCC">Level 2, chip protection</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>BOR Level</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x50022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>BOR_LEV</Name>
+										<Description>These bits contain the VDD supply level threshold that activates/releases the reset.</Description>
+										<BitOffset>0x8</BitOffset>
+										<BitWidth>0x3</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+											<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+											<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+											<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+											<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>User Configuration</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x50022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>nRST_STOP</Name>
+										<Description/>
+										<BitOffset>0xC</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Stop mode</Val>
+											<Val value="0x1">No reset generated when entering Stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_STDBY</Name>
+										<Description/>
+										<BitOffset>0xD</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Standby mode</Val>
+											<Val value="0x1">No reset generated when entering Standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_SHDW</Name>
+										<Description/>
+										<BitOffset>0xE</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+											<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM134_RST</Name>
+										<Description>SRAM1, SRAM3 and SRAM4 erase upon system reset</Description>
+										<BitOffset>0xF</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM1, SRAM3 and SRAM4 erased when a system reset occurs</Val>
+										<Val value="0x1">SRAM1, SRAM3 and SRAM4 not erased when a system reset occurs</Val>
+									</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware independant watchdog</Val>
+											<Val value="0x1">Software independant watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STOP</Name>
+										<Description/>
+										<BitOffset>0x11</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+											<Val value="0x1">IWDG counter active in stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STDBY</Name>
+										<Description/>
+										<BitOffset>0x12</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+											<Val value="0x1">IWDG counter active in standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>WWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x13</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware window watchdog</Val>
+											<Val value="0x1">Software window watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SWAP_BANK</Name>
+										<Description/>
+										<BitOffset>0x14</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+											<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>DBANK</Name>
+										<Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
+										<BitOffset>0x15</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+											<Val value="0x1">Dual bank mode with 64 bits data</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_PE</Name>
+										<Description>SRAM2 parity check enable</Description>
+										<BitOffset>0x18</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 parity check enable</Val>
+											<Val value="0x1">SRAM2 parity check disable</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_RST</Name>
+										<Description>SRAM2 Erase when system reset</Description>
+										<BitOffset>0x19</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+											<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nSWBOOT0</Name>
+										<Description>Software BOOT0</Description>
+										<BitOffset>0x1A</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+											<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nBOOT0</Name>
+										<Description>nBOOT0 option bit</Description>
+										<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+											<Val value="0x0">nBOOT0 = 0</Val>
+											<Val value="0x1">nBOOT0 = 1</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>PA15_PUPEN</Name>
+										<Description>PA15 pull-up enable</Description>
+										<BitOffset>0x1C</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+											<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+										<Name>BKPRAM_ECC</Name>
+										<Description>SRAM2 parity check enable</Description>
+										<BitOffset>0x16</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+										<Val value="0x0">Backup RAM ECC check enabled</Val>
+										<Val value="0x1">Backup RAM ECC check disabled</Val>
+										</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM3_ECC</Name>
+									<Description>SRAM3 ECC detection and correction enable</Description>
+									<BitOffset>0x17</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM3 ECC check enabled</Val>
+										<Val value="0x1">SRAM3 ECC check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SRAM2_ECC</Name>
+									<Description>SRAM2 ECC detection and correction enable</Description>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 ECC check enabled</Val>
+										<Val value="0x1">SRAM2 ECC check disabled</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IO_VDD_HSLV</Name>
+									<Description>High-speed IO at low VDD voltage configuration bit</Description>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">High-speed IO at low VDD voltage feature disabled (VDD can exceed 2.5 V)</Val>
+										<Val value="0x1">High-speed IO at low VDD voltage feature enabled (VDD remains below 2.5 V)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IO_VDDIO2_HSLV</Name>
+									<Description>High-speed IO at low VDDIO2 voltage configuration bit</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">High-speed IO at low VDDIO2 voltage feature disabled (VDDIO2 can exceed 2.5 V)</Val>
+										<Val value="0x1">High-speed IO at low VDDIO2 voltage feature enabled (VDDIO2 remains below 2.5 V)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>TZEN</Name>
+									<Description>Global TrustZone security enable</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+											<Val value="0x0">Global TrustZone security disabled</Val>
+											<Val value="0x1">Global TrustZone security enabled</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x50022054"/>
+									<AssignedBits>
+										<Bit>
+											<Name>HDP1EN</Name>
+											<Description>Hide protection first area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 1</Val>
+												<Val value="0x1">HDP first area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="2">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="3">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R2" size="0x4" address="0x50022064"/>
+									<AssignedBits>
+										<Bit>
+											<Name>HDP2EN</Name>
+											<Description>Hide protection second area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 2</Val>
+												<Val value="0x1">HDP second area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="2">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="3">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x50022044"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD0</Name>
+										<Description>Non-secure Boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x50022048"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD1</Name>
+										<Description>Non-secure Boot base address 1</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x5002204C"/>
+								<AssignedBits>
+								<Bit>
+										<Name>SECBOOTADD0</Name>
+										<Description>Secure boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+							<Parameters name="BOOT_LOCK" size="0x4" address="0x5002204C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description> The boot is always forced to base address value programmed in SECBOOTADD0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from base address memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Secure Area 1</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM1R1" size="0x4" address="0x50022050"/>
+								<AssignedBits>
+									<Bit config="2">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x4000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="3">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x2000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="2">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x4000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="3">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x2000"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<!-- <Category> -->
+							<!-- <Name>PCROP Protection (Bank 1)</Name> -->
+							<!-- <Field> -->
+								<!-- <Parameters name="FLASH_PCROP1SR" size="0x4" address="0x50022054"/> -->
+								<!-- <AssignedBits> -->
+									<!-- <Bit config="2"> -->
+										<!-- <Name>PCROP1_PSTRT</Name> -->
+										<!-- <Description>Start page of first PCROP area</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="3"> -->
+										<!-- <Name>PCROP1_STRT</Name> -->
+										<!-- <Description>Flash Bank 1 PCROP start address</Description> -->
+										<!-- <BitOffset>0x0</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="2"> -->
+										<!-- <Name>HDP1_PEND</Name> -->
+										<!-- <Description>End page of first hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit config="3"> -->
+										<!-- <Name>HDP1_PEND</Name> -->
+										<!-- <Description>End page of first hide protection area</Description> -->
+										<!-- <BitOffset>0x10</BitOffset> -->
+										<!-- <BitWidth>0x7</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+									<!-- </Bit> -->
+									<!-- <Bit> -->
+										<!-- <Name>PCROP1EN</Name> -->
+										<!-- <Description>PCROP1 area enable</Description> -->
+										<!-- <BitOffset>0xF</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">PCROP1 area is disabled</Val> -->
+											<!-- <Val value="0x1">PCROP1 area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+									<!-- <Bit> -->
+										<!-- <Name>HDP1EN</Name> -->
+										<!-- <Description>Hide protection first area enable</Description> -->
+										<!-- <BitOffset>0x1F</BitOffset> -->
+										<!-- <BitWidth>0x1</BitWidth> -->
+										<!-- <Access>RW</Access> -->
+										<!-- <Values> -->
+											<!-- <Val value="0x0">No HDP area 1</Val> -->
+											<!-- <Val value="0x1">HDP first area is enabled</Val> -->
+										<!-- </Values> -->
+									<!-- </Bit> -->
+								<!-- </AssignedBits> -->
+							<!-- </Field> -->
+						<!-- </Category> -->
+						<Category>
+							<Name>Write Protection 1</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x50022058"/>
+							<AssignedBits>
+								<Bit config="2">
+									<Name>WRP1A_PSTRT</Name>
+									<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP1A_PSTRT</Name>
+									<Description>Bank 1 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="2">
+									<Name>WRP1A_PEND</Name>
+									<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP1A_PEND</Name>
+									<Description>Bank 1 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 1 WPR first area A unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP1A start and end pages locked</Val>
+										<Val value="0x1">WRP1A start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x5002205C"/>
+							<AssignedBits>
+								<Bit config="2">
+									<Name>WRP1B_PSTRT</Name>
+									<Description>Bank 1 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP1B_PSTRT</Name>
+									<Description>Bank 1 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="2">
+									<Name>WRP1B_PEND</Name>
+									<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP1B_PEND</Name>
+									<Description>Bank 1 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 1 WPR first area B unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP1B start and end pages locked</Val>
+										<Val value="0x1">WRP1B start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x4" address="0x50022060"/>
+					<Category>
+					<Name>Secure Area 2</Name>
+						<Field>
+							<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x50022060"/>
+							<AssignedBits>
+								<Bit config="2">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<!-- <Category> -->
+						<!-- <Name>PCROP Protection (Bank 2)</Name> -->
+						<!-- <Field> -->
+							<!-- <Parameters name="FLASH_SECWM2R2" size="0x4" address="0x50022064"/> -->
+							<!-- <AssignedBits> -->
+								<!-- <Bit config="2"> -->
+									<!-- <Name>PCROP2_PSTRT</Name> -->
+									<!-- <Description>Start page of first PCROP area</Description> -->
+									<!-- <BitOffset>0x0</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="3"> -->
+									<!-- <Name>PCROP2_STRT</Name> -->
+									<!-- <Description>Flash Bank 2 PCROP start address</Description> -->
+									<!-- <BitOffset>0x0</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="2"> -->
+									<!-- <Name>HDP2_PEND</Name> -->
+									<!-- <Description>End page of second hide protection area</Description> -->
+									<!-- <BitOffset>0x10</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x4"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="3"> -->
+									<!-- <Name>HDP2_PEND</Name> -->
+									<!-- <Description>End page of second hide protection area</Description> -->
+									<!-- <BitOffset>0x10</BitOffset> -->
+									<!-- <BitWidth>0x7</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Equation	 multiplier="0x2"	offset="0x08000000"/> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="2,3"> -->
+									<!-- <Name>PCROP2EN</Name> -->
+									<!-- <Description>PCROP2 area enable</Description> -->
+									<!-- <BitOffset>0xF</BitOffset> -->
+									<!-- <BitWidth>0x1</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Values> -->
+										<!-- <Val value="0x0">PCROP2 area is disabled</Val> -->
+										<!-- <Val value="0x1">PCROP2 area is enabled</Val> -->
+									<!-- </Values> -->
+								<!-- </Bit> -->
+								<!-- <Bit config="2,3"> -->
+									<!-- <Name>HDP2EN</Name> -->
+									<!-- <Description>Hide protection second area enable</Description> -->
+									<!-- <BitOffset>0x1F</BitOffset> -->
+									<!-- <BitWidth>0x1</BitWidth> -->
+									<!-- <Access>RW</Access> -->
+									<!-- <Values> -->
+										<!-- <Val value="0x0">No HDP area 2</Val> -->
+										<!-- <Val value="0x1">HDP second area is enabled</Val> -->
+									<!-- </Values> -->
+								<!-- </Bit> -->
+							<!-- </AssignedBits> -->
+						<!-- </Field> -->
+					<!-- </Category> -->
+					<Category>
+						<Name>Write Protection 2</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x50022068"/>
+							<AssignedBits>
+								<Bit config="2">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 2 WPR first area A unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP2A start and end pages locked</Val>
+										<Val value="0x1">WRP2A start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x5002206C"/>
+							<AssignedBits>
+								<Bit config="2">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="2">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x4000"	offset="0x08100000"/>
+								</Bit>
+								<Bit config="3">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x2000"	offset="0x08100000"/>
+								</Bit>
+								<Bit>
+									<Name>UNLOCK</Name>
+									<Description>Bank 2 WPR first area B unlock</Description>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRP2B start and end pages locked</Val>
+										<Val value="0x1">WRP2B start and end pages unlocked</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Configuration>
+				<Bank interface="Bootloader">
+						<Parameters name="Bank 1" size="0x30" address="0x40022040"/>
+						<Category>
+							<Name>Read Out Protection</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>RDP</Name>
+										<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x8</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0xAA">Level 0, no protection</Val>
+											<Val value="0x55">Level 0.5, read protection not active, only non-secure debug access is possible. Only available when TrustZone is active (TZEN=1)</Val>
+											<Val value="0xDC">Level 1, read protection of memories</Val>
+											<Val value="0xCC">Level 2, chip protection</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>BOR Level</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>BOR_LEV</Name>
+										<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+										<BitOffset>0x8</BitOffset>
+										<BitWidth>0x3</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
+											<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
+											<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
+											<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
+											<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>User Configuration</Name>
+							<Field>
+								<Parameters name="FLASH_OPTR" size="0x4" address="0x40022040"/>
+								<AssignedBits>
+									<Bit>
+										<Name>nRST_STOP</Name>
+										<Description/>
+										<BitOffset>0xC</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Stop mode</Val>
+											<Val value="0x1">No reset generated when entering Stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_STDBY</Name>
+										<Description/>
+										<BitOffset>0xD</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering Standby mode</Val>
+											<Val value="0x1">No reset generated when entering Standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nRST_SHDW</Name>
+										<Description/>
+										<BitOffset>0xE</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+											<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware independant watchdog</Val>
+											<Val value="0x1">Software independant watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STOP</Name>
+										<Description/>
+										<BitOffset>0x11</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+											<Val value="0x1">IWDG counter active in stop mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>IWDG_STDBY</Name>
+										<Description/>
+										<BitOffset>0x12</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+											<Val value="0x1">IWDG counter active in standby mode</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>WWDG_SW</Name>
+										<Description/>
+										<BitOffset>0x13</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Hardware window watchdog</Val>
+											<Val value="0x1">Software window watchdog</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SWAP_BANK</Name>
+										<Description/>
+										<BitOffset>0x14</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Bank 1 and bank 2 address are not swapped</Val>
+											<Val value="0x1">Bank 1 and bank 2 address are swapped</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>DB256</Name>
+										<Description>Dual-Bank on 256 Kb Flash memory devices</Description>
+										<BitOffset>0x15</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">256Kb single Flash: contiguous address in bank1</Val>
+											<Val value="0x1">256Kb dual-bank Flash with contiguous addresses</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>DBANK</Name>
+										<Description>Dual-bank on 1-Mbyte and 512-Kbyte Flash memory devices</Description>
+										<BitOffset>0x16</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Single bank mode with 128 bits data read width</Val>
+											<Val value="0x1">Dual bank mode with 64 bits data</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_PE</Name>
+										<Description>SRAM2 parity check enable</Description>
+										<BitOffset>0x18</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 parity check enable</Val>
+											<Val value="0x1">SRAM2 parity check disable</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>SRAM2_RST</Name>
+										<Description>SRAM2 Erase when system reset</Description>
+										<BitOffset>0x19</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
+											<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nSWBOOT0</Name>
+										<Description>Software BOOT0</Description>
+										<BitOffset>0x1A</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
+											<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>nBOOT0</Name>
+										<Description>nBOOT0 option bit</Description>
+										<BitOffset>0x1B</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">nBOOT0 = 0</Val>
+											<Val value="0x1">nBOOT0 = 1</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>PA15_PUPEN</Name>
+										<Description>PA15 pull-up enable</Description>
+										<BitOffset>0x1C</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">USB power delivery dead-battery enabled/ TDI pull-up deactivated</Val>
+											<Val value="0x1">USB power delivery dead-battery disabled/ TDI pull-up activated</Val>
+										</Values>
+									</Bit>
+									<Bit>
+										<Name>TZEN</Name>
+										<Description>Global TrustZone security enable</Description>
+										<BitOffset>0x1F</BitOffset>
+										<BitWidth>0x1</BitWidth>
+										<Access>RW</Access>
+										<Values>
+											<Val value="0x0">Global TrustZone security disabled</Val>
+											<Val value="0x1">Global TrustZone security enabled</Val>
+										</Values>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022054"/>
+									<AssignedBits>
+										<Bit config="6,7,8,9">
+											<Name>HDP1EN</Name>
+											<Description>Hide protection first area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 1</Val>
+												<Val value="0x1">HDP first area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="6,8">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="7,9">
+											<Name>HDP1_PEND</Name>
+											<Description>End page of first hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+									<Parameters name="FLASH_SECWM2R2" size="0x4" address="0x40022064"/>
+									<AssignedBits>
+										<Bit config="6,7,8,9">
+											<Name>HDP2EN</Name>
+											<Description>Hide protection second area enable</Description>
+											<BitOffset>0x1F</BitOffset>
+											<BitWidth>0x1</BitWidth>
+											<Access>RW</Access>
+											<Values>
+												<Val value="0x0">No HDP area 2</Val>
+												<Val value="0x1">HDP second area is enabled</Val>
+											</Values>
+										</Bit>
+										<Bit config="6,8">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x4"	offset="0x08000000"/>
+										</Bit>
+										<Bit config="7,9">
+											<Name>HDP2_PEND</Name>
+											<Description>End page of second hide protection area</Description>
+											<BitOffset>0x10</BitOffset>
+											<BitWidth>0x7</BitWidth>
+											<Access>RW</Access>
+											<Equation	 multiplier="0x2"	offset="0x08000000"/>
+										</Bit>
+									</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD0" size="0x4" address="0x40022044"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD0</Name>
+										<Description>Non-secure Boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_NSBOOTADD1" size="0x4" address="0x40022048"/>
+								<AssignedBits>
+								<Bit>
+										<Name>NSBOOTADD1</Name>
+										<Description>Non-secure Boot base address 1</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_SECBOOTADD0" size="0x4" address="0x4002204C"/>
+								<AssignedBits>
+								<Bit>
+										<Name>SECBOOTADD0</Name>
+										<Description>Secure boot base address 0</Description>
+										<BitOffset>0x7</BitOffset>
+										<BitWidth>0x19</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x80"	offset="0x0000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+						<Name>Secure area 1</Name>
+							<Field>
+								<Parameters name="FLASH_SECWM1R1" size="0x4" address="0x40022050"/>
+								<AssignedBits>
+									<Bit config="6,8">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>SECWM1_PSTRT</Name>
+										<Description>Start page of first secure area</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="6,8">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>SECWM1_PEND</Name>
+										<Description>End page of first secure area</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+						<Category>
+							<Name>Write Protection 1</Name>
+							<Field>
+								<Parameters name="FLASH_WRP1AR" size="0x4" address="0x40022058"/>
+								<AssignedBits>
+									<Bit config="6,8">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1A_PSTRT</Name>
+										<Description>Bank 1 WPR first area "A" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="6,8">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1A_PEND</Name>
+										<Description>Bank 1 WPR first area "A" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+							<Field>
+								<Parameters name="FLASH_WRP1BR" size="0x4" address="0x4002205C"/>
+								<AssignedBits>
+									<Bit config="6,8">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1B_PSTRT</Name>
+										<Description>Bank 1 WPR first area "B" start page</Description>
+										<BitOffset>0x0</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="6,8">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x1000"	offset="0x08000000"/>
+									</Bit>
+									<Bit config="7,9">
+										<Name>WRP1B_PEND</Name>
+										<Description>Bank 1 WPR first area "B" end page</Description>
+										<BitOffset>0x10</BitOffset>
+										<BitWidth>0x7</BitWidth>
+										<Access>RW</Access>
+										<Equation	multiplier="0x800"	offset="0x08000000"/>
+									</Bit>
+								</AssignedBits>
+							</Field>
+						</Category>
+					<Category>
+					<Name>Secure area 2</Name>
+						<Field>
+							<Parameters name="FLASH_SECWM2R1" size="0x4" address="0x40022060"/>
+							<AssignedBits>
+								<Bit config="6,8">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>SECWM2_PSTRT</Name>
+									<Description>Start page of second secure area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="6,8">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>SECWM2_PEND</Name>
+									<Description>End page of second secure area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection 2</Name>
+						<Field>
+							<Parameters name="FLASH_WRP2AR" size="0x4" address="0x40022068"/>
+							<AssignedBits>
+								<Bit config="6,8">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2A_PSTRT</Name>
+									<Description>Bank 2 WPR first area "A" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="6,8">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2A_PEND</Name>
+									<Description>Bank 2 WPR first area "A" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP2BR" size="0x4" address="0x4002206C"/>
+							<AssignedBits>
+								<Bit config="6,8">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2B_PSTRT</Name>
+									<Description>Bank 2 WPR first area "B" start page</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+								<Bit config="6,8">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x1000"	offset="0x08000000"/>
+								</Bit>
+								<Bit config="7,9">
+									<Name>WRP2B_PEND</Name>
+									<Description>Bank 2 WPR first area "B" end page</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08040000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+
+	<!-- Device: 0x425 -->
+	<Device>
+		<DeviceID>0x425</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+</CPU>
+		<Name>STM32L03x/L04x/L010</Name>
+		<Series>STM32L0</Series>
+		<Description>ARM 32-bit Cortex-M0+ based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x2000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x2000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF8007C" default="0x8000"/>
+				<!-- 128KB single Bank -->
+				<Configuration>
+					<Parameters name="32 Kbytes Embedded Flash" size="0x8000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x80" address="0x08000000"	occurence="0x100"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1KB single Bank -->
+				<Configuration>
+					<Parameters name=" 1 Kbytes Data EEPROM" size="0x400" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x400" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x14" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+				<Parameters name="Bank 2" size="0x14" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>						
+					</Category>	
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	<!-- Device: 0x457 -->
+	<Device>
+		<DeviceID>0x457</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+</CPU>
+		<Name>STM32L01x/L02x</Name>
+		<Series>STM32L0</Series>
+		<Description>ARM 32-bit Cortex-M0+ based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x4002201C"	mask="0x000000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0"> <!-- WRPx control the write protection of user sector-->
+					<WPRMOD reference="0x1">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x0"/>
+					</WPRMOD>
+				</Configuration>
+				<Configuration	number="0x1"> <!-- WRPx control the read/write protection PcROP-->
+					<WPRMOD reference="0x0">
+						<ReadRegister address="0x1FF80000"	mask="0x00000100"	value="0x100"/>
+					</WPRMOD>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 16 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x800" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x800" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FF8007C" default="0x4000"/>
+				<!-- 128KB single Bank -->
+				<Configuration>
+					<Parameters name="16 Kbytes Embedded Flash" size="0x4000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x80" address="0x08000000"	occurence="0x80"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Data EEPROM -->
+			<Peripheral>
+				<Name>Data EEPROM</Name>
+				<Type>Storage</Type>
+				<Description>The Data EEPROM memory block. It contains user data.</Description>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 1KB single Bank -->
+				<Configuration>
+					<Parameters name=" 1 Kbytes Data EEPROM" size="0x200" address="0x08080000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="EEPROM1" size="0x200" address="0x08080000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x68" address="0x4002201C"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters nname="FLASH_OBR" size="0x4" address="0x4002201C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (default mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode</Description>
+									<BitOffset>0x1E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Main Flash memory is selected as boot area</Val>
+										<Val value="0x1">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x10" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (default mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode</Description>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Main Flash memory is selected as boot area</Val>
+										<Val value="0x1">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>W</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="WRP1" size="0x8" address="0x1FF80008"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>W</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field> 
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+				<Parameters name="Bank 2" size="0x10" address="0x1FF80000"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="RDP" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OBR" size="0x4" address="0x1FF80000"/>
+							<AssignedBits>
+								<Bit reference="SPRMode">
+									<Name>WPRMOD</Name>
+									<Description>Sector protection mode selection option byte.</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">WRPx bit defines sector write protection</Val>
+										<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
+										<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
+										<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
+										<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
+										<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
+										<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
+										<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="USER" size="0x4" address="0x1FF80004"/>
+							<AssignedBits>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x0D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (default mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description>When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used toselect the device boot mode</Description>
+									<BitOffset>0x0E</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Main Flash memory is selected as boot area</Val>
+										<Val value="0x1">nBOOT1=1 SysMem/nBOOT1=0 SRAM as boot area</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x0F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRPR1" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit config="0">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">Write protection not active</Val>
+										<Val value="0x1">Write protection active</Val>
+									</Values>
+								</Bit>
+								<Bit config="1">
+									<Name>WRPOT0</Name>
+									<Description/>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+									<Values	ByBit="true">
+										<Val value="0x0">read/Write protection active</Val>
+										<Val value="0x1">read/Write protection not active</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>						
+					</Category>	
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	<!-- Device: 0x466 -->
+	<Device>
+		<DeviceID>0x466</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+</CPU>
+		<Name>STM32G03x/STM32G04x</Name>
+		<Series>STM32G0</Series>
+		<Description>ARM 32-bit Cortex-M0+ based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x2000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x2000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x10000"/>
+				<!-- Single Bank -->
+				<Configuration>
+					<Parameters name=" 64 KB Embedded Flash" size="0x10000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x20"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Mirror Option Bytes -->
+			<Peripheral>
+				<Name>MirrorOptionBytes</Name>
+				<Type>Storage</Type>
+				<Description>Mirror Option Bytes contains the extra area.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 56 Bytes Dual bank -->
+				<Configuration>
+					<Parameters name=" 56 Bytes Data MirrorOptionBytes" size="0x38" address="0x1FFF7800"/>
+					<Description/>
+					<Organization>Dual</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="Bank1" size="0x34" address="0x1FFF7800"	occurence="0x1"/>
+						</Field>
+					</Bank>
+					<Bank name="Bank 2">
+						<Field>
+							<Parameters name="Bank2" size="0x4" address="0x1FFF7870"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x20" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_EN</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
+										<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORF_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
+										<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
+										<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
+										<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0xB</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
+										<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
+										<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
+										<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_HDW</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY_CHECK</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>				
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1BSR" size="0x4" address="0x40022034"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1BER" size="0x4" address="0x40022038"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x10" address="0x40022080"/>
+					<Category>
+						<Name>FLASH security</Name>
+						<Field>
+							<Parameters name="FLASH_SECR" size="0x4" address="0x40022080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>used to force boot from user area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from Main Flash memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SEC_SIZE</Name>
+									<Description>Securable memory area size</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x34" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_EN</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
+										<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORF_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
+										<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
+										<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
+										<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0xB</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
+										<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
+										<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
+										<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY_CHECK</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>				
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x4" address="0x1FFF7870"/>
+					<Category>
+						<Name>FLASH security</Name>
+						<Field>
+							<Parameters name="FLASH_SECR" size="0x4" address="0x1FFF7870"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>used to force boot from user area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from Main Flash memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SEC_SIZE</Name>
+									<Description>Securable memory area size</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	<!-- Device: 0x460 -->
+	<Device>
+		<DeviceID>0x460</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MCU</Type>
+		<CPU>Cortex-M0+</CPU>
+		<Name>STM32G07x/STM32G08x</Name>
+		<Series>STM32G0</Series>
+		<Description>ARM 32-bit Cortex-M0+ based device</Description>
+		<Configurations>
+			<!-- JTAG_SWD Interface -->
+			<Interface name="JTAG_SWD"/>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader"/>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<!-- Embedded SRAM -->
+			<Peripheral>
+				<Name>Embedded SRAM</Name>
+				<Type>Storage</Type>
+				<Description/>
+				<ErasedValue>0x00</ErasedValue>
+				<Access>RWE</Access>
+				<!-- 96 KB -->
+				<Configuration>
+					<Parameters name="SRAM" size="0x8000" address="0x20000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="SRAM" size="0x8000" address="0x20000000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Embedded Flash -->
+			<Peripheral>
+				<Name>Embedded Flash</Name>
+				<Type>Storage</Type>
+				<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RWE</Access>
+				<FlashSize address="0x1FFF75E0" default="0x20000"/>
+				<!-- Single Bank -->
+				<Configuration>
+					<Parameters name=" 128 KB Embedded Flash" size="0x20000" address="0x08000000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x8</Allignement>
+					<Bank name="Bank 1">
+						<Field>
+							<Parameters name="sector0" size="0x800" address="0x08000000"	occurence="0x40"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- OTP -->
+			<Peripheral>
+				<Name>OTP</Name>
+				<Type>Storage</Type>
+				<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
+				<ErasedValue>0xFF</ErasedValue>
+				<Access>RW</Access>
+				<!-- 1 KBytes single bank -->
+				<Configuration>
+					<Parameters name=" 1 KBytes Data OTP" size="0x400" address="0x1FFF7000"/>
+					<Description/>
+					<Organization>Single</Organization>
+					<Allignement>0x4</Allignement>
+					<Bank name="OTP">
+						<Field>
+							<Parameters name="OTP" size="0x400" address="0x1FFF7000"	occurence="0x1"/>
+						</Field>
+					</Bank>
+				</Configuration>
+			</Peripheral>
+			<!-- Option Bytes -->
+			<Peripheral>
+				<Name>Option Bytes</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 1" size="0x20" address="0x40022020"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_EN</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
+										<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORF_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
+										<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
+										<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
+										<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0xB</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
+										<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
+										<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
+										<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x40022020"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY_CHECK</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>				
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x40022024"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x40022028"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1BSR" size="0x4" address="0x40022034"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1BER" size="0x4" address="0x40022038"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1B_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x4002202C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x40022030"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="JTAG_SWD">
+					<Parameters name="Bank 2" size="0x4" address="0x40022080"/>
+					<Category>
+						<Name>FLASH security</Name>
+						<Field>
+							<Parameters name="FLASH_SECR" size="0x4" address="0x40022080"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>used to force boot from user area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from Main Flash memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SEC_SIZE</Name>
+									<Description>Securable memory area size</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 1" size="0x34" address="0x1FFF7800"/>
+					<Category>
+						<Name>Read Out Protection</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>RDP</Name>
+									<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0xAA">Level 0, no protection</Val>
+										<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
+										<Val value="0xCC">Level 2, chip protection</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>BOR Level</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOR_EN</Name>
+									<Description/>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Configurable brown out reset disabled, power-on reset defined by POR/PDR levels</Val>
+										<Val value="0x1">Configurable brown out reset enabled, values of BORR_LEV and BORF_LEV taken into account</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORF_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR falling level 1 with threshold around 2.0 V</Val>
+										<Val value="0x1">BOR falling level 2 with threshold around 2.2 V</Val>
+										<Val value="0x2">BOR falling level 3 with threshold around 2.5 V</Val>
+										<Val value="0x3">BOR falling level 4 with threshold around 2.8 V</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>BORR_LEV</Name>
+									<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
+									<BitOffset>0xB</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOR rising level 1 with threshold around 2.1 V</Val>
+										<Val value="0x1">BOR rising level 2 with threshold around 2.3 V</Val>
+										<Val value="0x2">BOR rising level 3 with threshold around 2.6 V</Val>
+										<Val value="0x3">BOR rising level 4 with threshold around 2.9 V</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>User Configuration</Name>
+						<Field>
+							<Parameters name="FLASH_OPTR" size="0x4" address="0x1FFF7800"/>
+							<AssignedBits>
+								<Bit>
+									<Name>nRST_STOP</Name>
+									<Description/>
+									<BitOffset>0xD</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Stop mode</Val>
+										<Val value="0x1">No reset generated when entering Stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_STDBY</Name>
+									<Description/>
+									<BitOffset>0xE</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering Standby mode</Val>
+										<Val value="0x1">No reset generated when entering Standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nRST_SHDW</Name>
+									<Description/>
+									<BitOffset>0xF</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
+										<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware independant watchdog</Val>
+										<Val value="0x1">Software independant watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STOP</Name>
+									<Description/>
+									<BitOffset>0x11</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in stop mode</Val>
+										<Val value="0x1">IWDG counter active in stop mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IWDG_STDBY</Name>
+									<Description/>
+									<BitOffset>0x12</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Freeze IWDG counter in standby mode</Val>
+										<Val value="0x1">IWDG counter active in standby mode</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>WWDG_SW</Name>
+									<Description/>
+									<BitOffset>0x13</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Hardware window watchdog</Val>
+										<Val value="0x1">Software window watchdog</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>RAM_PARITY_CHECK</Name>
+									<Description/>
+									<BitOffset>0x16</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">SRAM2 parity check enable</Val>
+										<Val value="0x1">SRAM2 parity check disable</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT_SEL</Name>
+									<Description/>
+									<BitOffset>0x18</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">BOOT0 signal is defined by BOOT0 pin value (legacy mode)</Val>
+										<Val value="0x1">BOOT0 signal is defined by nBOOT0 option bit</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT1</Name>
+									<Description/>
+									<BitOffset>0x19</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
+										<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>nBOOT0</Name>
+									<Description/>
+									<BitOffset>0x1A</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">nBOOT0=0</Val>
+										<Val value="0x1">nBOOT0=1</Val>
+									</Values>
+								</Bit>				
+								<Bit>
+									<Name>NRST_MODE</Name>
+									<Description/>
+									<BitOffset>0x1B</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Reserved</Val>
+										<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
+										<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
+										<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>IRHEN</Name>
+									<Description>Internal reset holder enable bit</Description>
+									<BitOffset>0x1D</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
+										<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
+									</Values>
+								</Bit>	
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>PCROP Protection</Name>
+						<Field>
+							<Parameters name="FLASH_PCROP1SR" size="0x4" address="0x1FFF7808"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_STRT</Name>
+									<Description>Flash Bank 1 PCROP start address</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_PCROP1ER" size="0x4" address="0x1FFF7810"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PCROP1A_END</Name>
+									<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x9</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x8"	offset="0x08000008"/>
+								</Bit>
+								<Bit>
+									<Name>PCROP_RDP</Name>
+									<Description/>
+									<BitOffset>0x1F</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
+										<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
+									</Values>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+					<Category>
+						<Name>Write Protection</Name>
+						<Field>
+							<Parameters name="FLASH_WRP1AR" size="0x4" address="0x1FFF7818"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1A_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1A_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP first area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="FLASH_WRP1BR" size="0x4" address="0x1FFF7820"/>
+							<AssignedBits>
+								<Bit>
+									<Name>WRP1B_STRT</Name>
+									<Description>The address of the first page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+								<Bit>
+									<Name>WRP1B_END</Name>
+									<Description>The address of the last page of the Bank 1 WRP second area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x6</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+				<Bank interface="Bootloader">
+					<Parameters name="Bank 2" size="0x4" address="0x1FFF7870"/>
+					<Category>
+						<Name>FLASH security</Name>
+						<Field>
+							<Parameters name="FLASH_SECR" size="0x4" address="0x1FFF7870"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BOOT_LOCK</Name>
+									<Description>used to force boot from user area</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+									<Values>
+										<Val value="0x0">Boot based on the pad/option bit configuration</Val>
+										<Val value="0x1">Boot forced from Main Flash memory</Val>
+									</Values>
+								</Bit>
+								<Bit>
+									<Name>SEC_SIZE</Name>
+									<Description>Securable memory area size</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+									<Equation	multiplier="0x800"	offset="0x08000000"/>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+
+	<!-- Device: 0x500 -->
+	<Device>
+		<DeviceID>0x500</DeviceID>
+		<Vendor>STMicroelectronics</Vendor>
+		<Type>MPU</Type>
+		<CPU>Cortex-A7</CPU>
+		<Name>STM32MPxxx</Name>
+		<Series>STM32MP</Series>
+		<Description>ARM 32-bit Cortex-A7 and ARM 32-bit Cortex-M4  dualprocessor based device, CPU clock up to 600MHz</Description>
+		<!-- Gonfigurations' List -->
+		<Configurations>
+			<!-- Bootloader Interface -->
+			<Interface name="Bootloader">
+				<Configuration	number="0x0">
+					<MultiCore>  <!--  Nothing here just the make sure that the XML file is compliant to the Schema file -->
+						<ReadRegister address="0x0"	mask="0x0"	value="0x4"/>
+					</MultiCore>
+				</Configuration>
+			</Interface>
+		</Configurations>
+		<!-- Peripherals -->
+		<Peripherals>
+			<Peripheral>
+				<Name>OTP Memory</Name>
+				<Type>Configuration</Type>
+				<Description/>
+				<Access>RW</Access>
+				<Bank>
+					<Parameters name="Bank 1" size="0x400" address="0x0"/>
+					<Category>
+						<Name>OTP</Name>
+						<Field>
+							<Parameters name="Struct_version" size="0x4" address="0x0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>none</Name>
+									<Description>none</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_CONFIG" size="0x4" address="0x4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>TR</Name>
+									<Description>set SAFMEM Ring current level, default value = 0b00</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>PRGWIDTH</Name>
+									<Description>SAFMEM Programming Pulse Width, default value = 0b0001</Description>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FRC</Name>
+									<Description>SAFMEM CLOCK frequency range selection, default value = 0b11</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>PWRUP</Name>
+									<Description>SAFMEM Power up control</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_Status" size="0x4" address="0xC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BIST2LOCK</Name>
+									<Description>0: BIST2 is not locked, 1: BIST2 is locked.</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>BIST1LOCK</Name>
+									<Description>0: BIST1 is not locked, 1: BIST1 is locked.</Description>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>PWRON</Name>
+									<Description>0: SAFMEM is in Power Off, 1: SAFMEM is in Power On.</Description>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>PROGFAIL</Name>
+									<Description>0: SAFMEM last programming was successful, 1: SAFMEM last programming failed.</Description>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>BUSY</Name>
+									<Description>0: SAFMEM is Idle, 1: SAFMEM operation is on going.</Description>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>INVALID</Name>
+									<Description>0: OTP mode is not OTP-INVALID, 1: OTP mode is OTP-INVALID.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>FULLDBG</Name>
+									<Description>0: OTP mode is OTP-OPEN1, 1: OTP mode is OTP-OPEN2.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>SECURE</Name>
+									<Description>0: OTP mode is not OTP-SECURED, 1: OTP mode is OTP-SECURED.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_LOCK" size="0x4" address="0x10"/>
+							<AssignedBits>
+								<Bit>
+									<Name>GPLOCK</Name>
+									<Description>0: SAFMEM Programming is allowed, 1: SAFMEM Programming is disabled until next sytem reste.</Description>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>FENREG</Name>
+									<Description>0: BSEC_FENABLE register is not Locked, 1: BSEC_FENABLE register is Locked until the next System-Reset.</Description>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>DENREG</Name>
+									<Description>0: BSEC_DENABLE register is not Locked, 1: BSEC_DENABLE register is Locked until the next System-Reset.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>OTP</Name>
+									<Description>0: upper OTP region access is not locked, 1: upper OTP region access is Locked until the next System-Reset, when locked, the upper region OTP can not be R out from SAFMEM.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_DENABLE" size="0x4" address="0x14"/>
+							<AssignedBits>
+								<Bit>
+									<Name>DBGSWENABLE</Name>
+									<Description>Control Self Hosted Debug enable with signal dbgswenable. 0: memory-mapped accesses to all ETM registers are disabled and return Error, 1: no effect on external debugger accesses.</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>CFGSDISABLE</Name>
+									<Description>Write access to secure GIC registers disable with signal: cfgsdisable. 0: no effect, all GIC registers can be accessed, 1: Disable write access to some Secure GIC registers.</Description>
+									<BitOffset>0x9</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>CP15SDISABLE</Name>
+									<Description>Write access to some secure Cortex-A7 CP15 registers is disabled for CPUx. 0: All CP15 registers can be accessed, 1: Disable write access to some Secure CP15 registers into Cortex-A7 corresponding CPU.</Description>
+									<BitOffset>0x7</BitOffset>
+									<BitWidth>0x2</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SPNIDEN</Name>
+									<Description>Secure Privilege Non Invasive Debug enable with signal spiden. 0: Secure Privilege Non Invasive Debug Disabled, 1: Secure Privilege Non Invasive Debug Enabled.</Description>
+									<BitOffset>0x6</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>SPIDEN</Name>
+									<Description>Secure Privilege Invasive Debug enable with signal spniden. 0: Secure Privilege Invasive Debug Disabled, 1: Secure Privilege Invasive Debug Enabled.</Description>
+									<BitOffset>0x5</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>HDPEN</Name>
+									<Description>Hardware Debug Port enable with signal hdpen. 0: Hardware Debug Port Disabled, 1: Hardware Debug Port Enabled.</Description>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>DEVICEEN</Name>
+									<Description>Controls the access to Debug component via external debug port by signal deviceen. 0: Disabled, 1: Enabled.</Description>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>NIDEN</Name>
+									<Description>Non Invasive Debug enable with signal niden. 0: Non Invasive Debug Disabled, 1: Non Invasive Debug Enabled.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>DBGEN</Name>
+									<Description>Debug enable with signal dbgen. 0: Disabled, 1: Enabled.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>DFTEN</Name>
+									<Description>DFT enable with signal dften. 0: DFT Disabled, 1: DFT Enabled.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_FENABLE" size="0x4" address="0x18"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CAN_disable</Name>
+									<Description>0: CAN interface is enabled, 1: CAN interface is disabled.</Description>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>GPU_disable</Name>
+									<Description>0: GPU enabled, 1: GPU disabled.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Dual_A7_disable</Name>
+									<Description>0: Cortex A7 Dual CPU, 1: Cortex A7 Single CPU.</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>Crypto_disable</Name>
+									<Description>0: All crypto HW accelerators are enabled(default), 1: All crypto HW accelerators are disabled for export license control.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="Write_R_Conf" size="0x4" address="0x1C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>W_R conf</Name>
+									<Description>This Bit determins weither the OTP file will be written in BSEC or programmed in SAFMEM</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_DISTURBED0" size="0x4" address="0x20"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_DISTURBED0</Name>
+									<Description>If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_DISTURBED1" size="0x4" address="0x24"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_DISTURBED1</Name>
+									<Description>If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_DISTURBED2" size="0x4" address="0x28"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_DISTURBED2</Name>
+									<Description>If the Bit is set to 1 that means that the last Ring of the corresponding word has been disturbed; abnormal Ring conditions in decoding circuitry and Ring voltages have been detected</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_ERROR0" size="0x4" address="0x38"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_ERROR0</Name>
+									<Description>If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_ERROR1" size="0x4" address="0x3C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_ERROR1</Name>
+									<Description>If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_ERROR2" size="0x4" address="0x40"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_ERROR2</Name>
+									<Description>If the Bit is set to 1 that means that the last R operation of the word concerned has revealed a redundancy or ECC check error.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_WRLOCK0" size="0x4" address="0x50"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_WRLOCK0</Name>
+									<Description>If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_WRLOCK1" size="0x4" address="0x54"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_WRLOCK1</Name>
+									<Description>If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_WRLOCK2" size="0x4" address="0x58"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_WRLOCK2</Name>
+									<Description>If the Bit is set to 1 that means that the correspanding OTP word is under programming permenant lock.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SPLOCK0" size="0x4" address="0x68"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SPLOCK0</Name>
+									<Description>If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SPLOCK1" size="0x4" address="0x6C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SPLOCK1</Name>
+									<Description>If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SPLOCK2" size="0x4" address="0x70"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SPLOCK2</Name>
+									<Description>If the Bit is set to 1 that means that the correspanding OTP word is under programming sticky lock until next system-reset</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SWLOCK0" size="0x4" address="0x80"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SWLOCK0</Name>
+									<Description>If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SWLOCK1" size="0x4" address="0x84"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SWLOCK1</Name>
+									<Description>If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SWLOCK2" size="0x4" address="0x8C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SWLOCK2</Name>
+									<Description>If the Bit is set to 1 that means that any attempt to write to the correspanding OTP shadow register will be prevented until next system-reset</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SRLOCK0" size="0x4" address="0x98"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SRLOCK0</Name>
+									<Description>If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SRLOCK1" size="0x4" address="0x9C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SRLOCK1</Name>
+									<Description>If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_OTP_SRLOCK2" size="0x4" address="0xA0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>BSEC_OTP_SRLOCK2</Name>
+									<Description>If the Bit is set to 1 that means that any attempt to reload to the correspanding OTP shadow register will be prevented until next system-reset. Instead a R command, shall clear the shadow register</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG0" size="0x4" address="0xB0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG0</Name>
+									<Description>These bits determins the OTP mode encoding</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x7</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG1" size="0x4" address="0xB4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>fdis3</Name>
+									<Description>Disable CAN</Description>
+									<BitOffset>0x3</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>fdis2</Name>
+									<Description>Disable GPU</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>fdis1</Name>
+									<Description>Disable CPU1</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>fdis0</Name>
+									<Description>Disable Crypto (license export)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG2" size="0x4" address="0xB8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>rma_force</Name>
+									<Description>RMA force Bit</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>rma_relock</Name>
+									<Description>RMA relock Bit</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG3" size="0x4" address="0xBC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG3</Name>
+									<Description>These bits determins the BOOT source definition</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG4" size="0x4" address="0xC0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG4</Name>
+									<Description>These bits determins the BOOT monotonic counter</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG5" size="0x4" address="0xC4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG5</Name>
+									<Description>These bits determins the BOOT AFmux configuration</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG6" size="0x4" address="0xC8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG6</Name>
+									<Description>These bits determins the BOOT AFmux configuration</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG7" size="0x4" address="0xCC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG7</Name>
+									<Description>These bits determins the BOOT AFmux configuration</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG8" size="0x4" address="0xD0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG8</Name>
+									<Description>BOOT/Device configuration.</Description>
+									<BitOffset>0x2</BitOffset>
+									<BitWidth>0x1E</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>rma_relock</Name>
+									<Description>RMA relock Bit</Description>
+									<BitOffset>0x1</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>rma_lock</Name>
+									<Description>RMA lock Bit</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x1</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG9" size="0x4" address="0xD4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG9</Name>
+									<Description>These bits determin the device configuration.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG10" size="0x4" address="0xD8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG10</Name>
+									<Description>These bits determin the device configuration.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG11" size="0x4" address="0xDC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG11</Name>
+									<Description>These bits determin the device configuration.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="CFG12" size="0x4" address="0xE0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>CFG12</Name>
+									<Description>These bits determin the device configuration.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="ID0" size="0x4" address="0xE4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ID0</Name>
+									<Description>Lot ID on 42bit (11LSB's)</Description>
+									<BitOffset>0x15</BitOffset>
+									<BitWidth>0xB</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>ID0</Name>
+									<Description>Wafer ID</Description>
+									<BitOffset>0x10</BitOffset>
+									<BitWidth>0x5</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>ID0</Name>
+									<Description>Wafer Y coordinates</Description>
+									<BitOffset>0x8</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>ID0</Name>
+									<Description>Wafer X coordinates</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x8</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="ID1" size="0x4" address="0xE8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ID1</Name>
+									<Description>Lot ID on 42bit (31MSB's)</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="ID2" size="0x4" address="0xEC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ID2</Name>
+									<Description>Test program flow T[12],F[12],Q[12]</Description>
+									<BitOffset>0x14</BitOffset>
+									<BitWidth>0xC</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>ID2</Name>
+									<Description>FT program revision</Description>
+									<BitOffset>0xA</BitOffset>
+									<BitWidth>0xA</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+								<Bit>
+									<Name>ID2</Name>
+									<Description>EWS program revision</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0xA</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW0" size="0x4" address="0xF0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW0</Name>
+									<Description>Analog TRIM</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW1" size="0x4" address="0xF4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW1</Name>
+									<Description>Analog TRIM</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW2" size="0x4" address="0xF8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW2</Name>
+									<Description>Analog TRIM and hardware options</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW3" size="0x4" address="0xFC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW3</Name>
+									<Description>Analog TRIM</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW4" size="0x4" address="0x100"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW4</Name>
+									<Description>not used yet</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW5" size="0x4" address="0x104"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW5</Name>
+									<Description>memory repair bits</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW6" size="0x4" address="0x108"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW6</Name>
+									<Description>memory repair bits</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="HW7" size="0x4" address="0x10C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>HW7</Name>
+									<Description>reserved</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH0" size="0x4" address="0x110"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH0</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH1" size="0x4" address="0x114"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH1</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH2" size="0x4" address="0x118"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH2</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH3" size="0x4" address="0x11C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH3</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH4" size="0x4" address="0x120"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH4</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH5" size="0x4" address="0x124"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH5</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH6" size="0x4" address="0x128"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH6</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="PKH7" size="0x4" address="0x12C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>PKH7</Name>
+									<Description>Public Key Hash</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK0" size="0x4" address="0x130"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK0</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK1" size="0x4" address="0x134"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK1</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK2" size="0x4" address="0x138"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK2</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK3" size="0x4" address="0x13C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK3</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK4" size="0x4" address="0x140"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK4</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK5" size="0x4" address="0x144"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK5</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK6" size="0x4" address="0x148"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK6</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK7" size="0x4" address="0x14C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK7</Name>
+									<Description>ST ECDSA Private Key for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK8" size="0x4" address="0x150"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK8</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK9" size="0x4" address="0x154"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK9</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK10" size="0x4" address="0x158"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK10</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK11" size="0x4" address="0x15C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK11</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK12" size="0x4" address="0x160"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK12</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK13" size="0x4" address="0x164"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK13</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK14" size="0x4" address="0x168"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK14</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK15" size="0x4" address="0x16C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK15</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK16" size="0x4" address="0x170"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK16</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK17" size="0x4" address="0x174"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK17</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK18" size="0x4" address="0x178"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK18</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK19" size="0x4" address="0x17C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK19</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK20" size="0x4" address="0x180"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK20</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK21" size="0x4" address="0x184"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK21</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK22" size="0x4" address="0x188"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK22</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK23" size="0x4" address="0x18C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK23</Name>
+									<Description>ST Public ECDSA Chip Certificate for SSP</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK24" size="0x4" address="0x190"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK24</Name>
+									<Description>RMA lock and relock passwords</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK25" size="0x4" address="0x194"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK25</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK26" size="0x4" address="0x198"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK26</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK27" size="0x4" address="0x19C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK27</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK28" size="0x4" address="0x1A0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK28</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK29" size="0x4" address="0x1A4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK29</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK30" size="0x4" address="0x1A8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK30</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK31" size="0x4" address="0x1AC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK31</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK32" size="0x4" address="0x1B0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK32</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK33" size="0x4" address="0x1B4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK33</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK34" size="0x4" address="0x1B8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK34</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK35" size="0x4" address="0x1BC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK35</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK36" size="0x4" address="0x1C0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK36</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK37" size="0x4" address="0x1C4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK37</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK38" size="0x4" address="0x1C8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK38</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK39" size="0x4" address="0x1CC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK39</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK40" size="0x4" address="0x1D0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK40</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK41" size="0x4" address="0x1D4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK41</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK42" size="0x4" address="0x1D8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK42</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK43" size="0x4" address="0x1DC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK43</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK44" size="0x4" address="0x1E0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK44</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK45" size="0x4" address="0x1E4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK45</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK46" size="0x4" address="0x1E8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK46</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK47" size="0x4" address="0x1EC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK47</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK48" size="0x4" address="0x1F0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK48</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK49" size="0x4" address="0x1F4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK49</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK50" size="0x4" address="0x1F8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK50</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK51" size="0x4" address="0x1FC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK51</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK52" size="0x4" address="0x200"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK52</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK53" size="0x4" address="0x204"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK53</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK54" size="0x4" address="0x208"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK54</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK55" size="0x4" address="0x20C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK55</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK56" size="0x4" address="0x210"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK56</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK57" size="0x4" address="0x214"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK57</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK58" size="0x4" address="0x218"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK58</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK59" size="0x4" address="0x21C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK59</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK60" size="0x4" address="0x220"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK60</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK61" size="0x4" address="0x224"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK61</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK62" size="0x4" address="0x228"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK62</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="XK63" size="0x4" address="0x22C"/>
+							<AssignedBits>
+								<Bit>
+									<Name>XK63</Name>
+									<Description>OEM OTP secret word</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>RW</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_HWCFGR" size="0x4" address="0x3F0"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ECC_USE</Name>
+									<Description>SAFMEM use ECC for Upper OTP bits. 0x0: No, 0x1: Yes, others: reserved.</Description>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>SAFMEM_SIZE</Name>
+									<Description>SAFMEM size. 0x2: 2KBits, 0x4: 4KBits, 0x8: 8KBits, others: reserved.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_VER" size="0x4" address="0x3F4"/>
+							<AssignedBits>
+								<Bit>
+									<Name>MAJREV</Name>
+									<Description>IP Version major revision information.</Description>
+									<BitOffset>0x4</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+								</Bit>
+								<Bit>
+									<Name>MINREV</Name>
+									<Description>IP Version minor revision information.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x4</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_ID" size="0x4" address="0x3F8"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ID</Name>
+									<Description>IP Identification.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+						<Field>
+							<Parameters name="BSEC_SID" size="0x04" address="0x3FC"/>
+							<AssignedBits>
+								<Bit>
+									<Name>ID</Name>
+									<Description>IP Magic Identification.</Description>
+									<BitOffset>0x0</BitOffset>
+									<BitWidth>0x20</BitWidth>
+									<Access>R</Access>
+								</Bit>
+							</AssignedBits>
+						</Field>
+					</Category>
+				</Bank>
+			</Peripheral>
+		</Peripherals>
+	</Device>
+	
+	
+</Root>
+	

tools/Drivers/DFU_Driver/DriverNotSigned/license/libusb0/installer_license.txt

@@ -0,0 +1,851 @@
+Copyright (c) 2002-2004 Stephan Meyer, <ste_meyer@web.de>
+Copyright (c) 2000-2004 Johannes Erdfelt, <johannes@erdfelt.com>
+Copyright (c) 2000-2004 Thomas Sailer, <sailer@ife.ee.ethz.ch>
+Copyright (c) 2010 Travis Robinson, <libusbdotnet@gmail.com>
+
+This software is distributed under the following licenses:
+Driver:      GNU General Public License (GPL)
+Library, Test Files, Installer:    GNU Lesser General Public License (LGPL)
+
+***********************************************************************
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
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+
+  A patent license is "discriminatory" if it does not include within
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+or that patent license was granted, prior to 28 March 2007.
+
+  Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+  12. No Surrender of Others' Freedom.
+
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+
+  13. Use with the GNU Affero General Public License.
+
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+  If the Program specifies that a proxy can decide which future
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+
+  17. Interpretation of Sections 15 and 16.
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+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
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+
+Also add information on how to contact you by electronic and paper mail.
+
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+
+The hypothetical commands `show w' and `show c' should show the appropriate
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+might be different; for a GUI interface, you would use an "about box".
+
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+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
+
+                   GNU LESSER GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+  This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
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+
+  0. Additional Definitions.
+
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+General Public License, and the "GNU GPL" refers to version 3 of the GNU
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+
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+differ in detail to address new problems or concerns.
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+permanent authorization for you to choose that version for the
+Library.
+

tools/Drivers/DFU_Driver/STM32Bootloader.bat

@@ -0,0 +1,20 @@
+::echo off
+
+@echo off
+setlocal
+for /f "tokens=4-5 delims=. " %%i in ('ver') do set VERSION=%%i.%%j
+
+if "%version%" == "6.1" (
+if exist "%windir%\sysnative\pnputil.exe" (
+    start "STM32 USB DFU DRIVER" %windir%\sysnative\pnputil.exe -i -a  %0\..\DriverNotSigned\DFU_in_HS_Mode.inf
+) else (
+    start "STM32 USB DFU DRIVER" pnputil -i -a  %0\..\DriverNotSigned\DFU_in_HS_Mode.inf
+)
+) else (
+if exist "%windir%\sysnative\pnputil.exe" (
+    start "STM32 USB DFU DRIVER" %windir%\sysnative\pnputil.exe -i -a  %0\..\Driver\STM32Bootloader.inf
+) else (
+    start "STM32 USB DFU DRIVER" pnputil -i -a  %0\..\Driver\STM32Bootloader.inf
+)
+)
+endlocal

tools/Drivers/FirmwareUpgrade/StlinkRulesFilesForLinux/49-stlinkv2-1.rules

@@ -0,0 +1,15 @@
+# stm32 nucleo boards, with onboard st/linkv2-1
+# ie, STM32F0, STM32F4.
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv2-1_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv2-1_%n"
+
+# If you share your linux system with other users, or just don't like the
+# idea of write permission for everybody, you can replace MODE:="0666" with
+# OWNER:="yourusername" to create the device owned by you, or with
+# GROUP:="somegroupname" and mange access using standard unix groups.

tools/Drivers/FirmwareUpgrade/StlinkRulesFilesForLinux/49-stlinkv2.rules

@@ -0,0 +1,11 @@
+# stm32 discovery boards, with onboard st/linkv2
+# ie, STM32L, STM32F4.
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv2_%n"
+
+# If you share your linux system with other users, or just don't like the
+# idea of write permission for everybody, you can replace MODE:="0666" with
+# OWNER:="yourusername" to create the device owned by you, or with
+# GROUP:="somegroupname" and mange access using standard unix groups.

tools/Drivers/FirmwareUpgrade/StlinkRulesFilesForLinux/49-stlinkv3.rules

@@ -0,0 +1,22 @@
+# stlink-v3 boards (standalone and embedded) in usbloader mode and standard (debug) mode
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3loader_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3_%n"
+
+# If you share your linux system with other users, or just don't like the
+# idea of write permission for everybody, you can replace MODE:="0666" with
+# OWNER:="yourusername" to create the device owned by you, or with
+# GROUP:="somegroupname" and mange access using standard unix groups.

tools/Drivers/FirmwareUpgrade/StlinkRulesFilesForLinux/Readme.txt

@@ -0,0 +1,4 @@
+File to copy in /etc/udev/rules.d/ on Ubuntu ("sudo cp *.* /etc/udev/rules.d").
+
+Note that no file is provided for ST-Link/V1 (idProduct=3744) as long as the interfacing
+with this device has not been ported on Linux.

tools/Drivers/rules/49-stlinkv1.rules

@@ -0,0 +1,6 @@
+# stm32 discovery boards, with onboard st/linkv1
+# ie, STM32VL.
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", \
+    MODE="660", GROUP="plugdev", TAG+="uaccess", \
+    SYMLINK+="stlinkv1_%n"

tools/Drivers/rules/49-stlinkv2-1.rules

@@ -0,0 +1,15 @@
+# stm32 nucleo boards, with onboard st/linkv2-1
+# ie, STM32F0, STM32F4.
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv2-1_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv2-1_%n"
+
+# If you share your linux system with other users, or just don't like the
+# idea of write permission for everybody, you can replace MODE:="0666" with
+# OWNER:="yourusername" to create the device owned by you, or with
+# GROUP:="somegroupname" and mange access using standard unix groups.

tools/Drivers/rules/49-stlinkv2.rules

@@ -0,0 +1,11 @@
+# stm32 discovery boards, with onboard st/linkv2
+# ie, STM32L, STM32F4.
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv2_%n"
+
+# If you share your linux system with other users, or just don't like the
+# idea of write permission for everybody, you can replace MODE:="0666" with
+# OWNER:="yourusername" to create the device owned by you, or with
+# GROUP:="somegroupname" and mange access using standard unix groups.

tools/Drivers/rules/49-stlinkv3.rules

@@ -0,0 +1,22 @@
+# stlink-v3 boards (standalone and embedded) in usbloader mode and standard (debug) mode
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3loader_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3_%n"
+
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", \
+    MODE:="0666", \
+    SYMLINK+="stlinkv3_%n"
+
+# If you share your linux system with other users, or just don't like the
+# idea of write permission for everybody, you can replace MODE:="0666" with
+# OWNER:="yourusername" to create the device owned by you, or with
+# GROUP:="somegroupname" and mange access using standard unix groups.

tools/Drivers/rules/50-usb-conf.rules

@@ -0,0 +1 @@
+SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="df11", GROUP="users", MODE="0666"

tools/Drivers/rules/Readme.txt

@@ -0,0 +1,4 @@
+Files to copy in /etc/udev/rules.d/ on Ubuntu ("sudo cp *.* /etc/udev/rules.d").
+
+Note that no file is provided for ST-Link/V1 (idProduct=3744) as long as the interfacing
+with this device has not been ported on Linux.

tools/Drivers/rules/version.txt

@@ -0,0 +1 @@
+1.0.0

tools/Drivers/stsw-link009_v3/readme.txt

@@ -0,0 +1,7 @@
+Digitally signed USB driver for ST-Link/V2, ST-Link/V2-1 a	nd STLINK-V3 on Windows7, Windows8 and Windows10, 32 and 64 bits.
+
+To install the driver, run stlink_winusb_install.bat in administrator mode, before connecting any ST-Link to the PC.
+
+In case of issue, it's also possible to run (as administrator):
+ - dpinst_x86.exe on 32 bits machines
+ - dpinst_amd64.exe on 64 bits machines

tools/Drivers/stsw-link009_v3/stlink_VCP.inf

@@ -0,0 +1,72 @@
+
+;
+; Installs the Virtual COM port interface of ST-Link based composite devices.
+;
+
+[Version]
+Signature = "$Windows NT$"
+Class     = Ports
+ClassGUID = {4D36E978-E325-11CE-BFC1-08002BE10318}
+Provider  = %ManufacturerName%
+CatalogFile.NTx86  = STLinkVCP_x86.cat
+CatalogFile.NTAMD64 = STLinkVCP_x64.cat
+DriverVer=06/08/2017,2.01
+
+; ========== Manufacturer/Models sections ===========
+
+[Manufacturer]
+%ManufacturerName% = Standard,NTx86,NTamd64
+
+; List of devices supporting the Virtual COM port (with the corresponding interface ID)
+[Standard.NTx86]
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374A&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374B&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374E&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374F&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_3752&MI_01
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_3753&MI_01
+%DeviceNameVCP2% =USB_InstallVCP, USB\VID_0483&PID_3753&MI_04
+
+[Standard.NTamd64]
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374A&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374B&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374E&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_374F&MI_02
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_3752&MI_01
+%DeviceNameVCP% =USB_InstallVCP, USB\VID_0483&PID_3753&MI_01
+%DeviceNameVCP2% =USB_InstallVCP, USB\VID_0483&PID_3753&MI_04
+
+; =================== Installation ===================
+
+[USB_InstallVCP]
+Include   = mdmcpq.inf
+CopyFiles = FakeModemCopyFileSection
+AddReg    = USB_InstallVCP.AddReg
+
+[USB_InstallVCP.AddReg]
+HKR,,DevLoader,,*ntkern
+HKR,,NTMPDriver,,usbser.sys
+HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
+
+[USB_InstallVCP.Services]
+AddService=usbser, 0x00000002, DriverService
+
+[DriverService]
+DisplayName=%DeviceNameVCP%
+ServiceType=1
+StartType=3
+ErrorControl=1
+ServiceBinary=%12%\usbser.sys
+
+; [DestinationDirs]
+; If your INF needs to copy files, you must not use the DefaultDestDir directive here.  
+; You must explicitly reference all file-list-section names in this section.
+
+; =================== Strings ===================
+
+[Strings]
+ManufacturerName="STMicroelectronics"
+;ClassName="Universal Serial Bus devices"
+DeviceNameVCP="STMicroelectronics STLink Virtual COM Port"
+DeviceNameVCP2="STMicroelectronics STLink Virtual COM Port 2"
+REG_MULTI_SZ = 0x00010000

tools/Drivers/stsw-link009_v3/stlink_bridge_winusb.inf

@@ -0,0 +1,108 @@
+;
+; Installation INF for the STMicroelectronics STLINK (bridge interface) for Windows XP SP2 or later.
+;
+
+[Version]
+Signature = "$Windows NT$"
+Class     = STLinkWinUSB
+ClassGUID = {88BAE032-5A81-49f0-BC3D-A4FF138216D6}
+Provider  = %ManufacturerName%
+CatalogFile.NTx86  = STLinkBridgeWinUSB_x86.cat
+CatalogFile.NTAMD64 = STLinkBridgeWinUSB_x64.cat
+DriverVer=06/08/2017,1.00
+
+; ========== Manufacturer/Models sections ===========
+
+[Manufacturer]
+%ManufacturerName% = Standard,NTx86,NTamd64
+
+[Standard.NTx86]
+%DeviceName% =USB_Install, USB\VID_0483&PID_374F&MI_04
+%DeviceName% =USB_Install, USB\VID_0483&PID_3753&MI_03
+
+[Standard.NTamd64]
+%DeviceName% =USB_Install, USB\VID_0483&PID_374F&MI_04
+%DeviceName% =USB_Install, USB\VID_0483&PID_3753&MI_03
+
+; ========== Class definition ===========
+
+[ClassInstall32]
+AddReg = ClassInstall_AddReg
+
+[ClassInstall_AddReg]
+HKR,,,,%ClassName%
+HKR,,NoInstallClass,,1
+HKR,,IconPath,%REG_MULTI_SZ%,"%systemroot%\system32\setupapi.dll,-20"
+HKR,,LowerLogoVersion,,5.2
+
+; =================== Installation ===================
+
+[USB_Install]
+Include=winusb.inf
+Needs=WINUSB.NT
+
+[USB_Install.Services]
+Include=winusb.inf
+Addservice = WinUSB, 0x00000002, WinUSB_ServiceInstall
+
+[WinUSB_ServiceInstall]
+DisplayName    = %WinUSB_SvcDesc%
+ServiceType    = 1                  ; SERVICE_KERNEL_DRIVER
+StartType      = 3                  ; SERVICE_DEMAND_START
+ErrorControl   = 1                  ; SERVICE_ERROR_NORMAL
+ServiceBinary  = %12%\WinUSB.sys
+
+[USB_Install.Wdf]
+KmdfService=WINUSB, WinUsb_Install
+
+[WinUsb_Install]
+KmdfLibraryVersion=1.9
+;KmdfLibraryVersion=1.11
+
+[USB_Install.HW]
+AddReg=Dev_AddReg
+
+[Dev_AddReg]
+HKR,,DeviceInterfaceGUIDs,0x10000,%STBridge_GUID%
+
+[USB_Install.CoInstallers]
+AddReg=CoInstallers_AddReg
+CopyFiles=CoInstallers_CopyFiles
+
+[CoInstallers_CopyFiles]
+WinUSBCoInstaller2.dll
+WdfCoInstaller01009.dll
+
+[CoInstallers_AddReg]
+HKR,,CoInstallers32,0x00010000,"WdfCoInstaller01009.dll,WdfCoInstaller","WinUSBCoInstaller2.dll"
+
+[DestinationDirs]
+CoInstallers_CopyFiles=11
+
+; ================= Source Media Section =====================
+
+[SourceDisksNames]
+1 = %DISK_NAME%,,,\x86
+2 = %DISK_NAME%,,,\amd64
+
+[SourceDisksFiles.x86]
+WinUSBCoInstaller2.dll=1
+WdfCoInstaller01009.dll=1
+
+[SourceDisksFiles.amd64]
+WinUSBCoInstaller2.dll=2
+WdfCoInstaller01009.dll=2
+
+;------------------------------------------------------------;
+
+[Strings]
+ManufacturerName="STMicroelectronics"
+ClassName="Universal Serial Bus devices"
+DeviceName="STMicroelectronics STLink Bridge"
+WinUSB_SvcDesc="WinUSB Driver for STLink Bridge"
+REG_MULTI_SZ = 0x00010000
+DISK_NAME="WinUSB coinstallers sources on disk"
+
+
+;------------Replace GUID below with custom GUID-------------;
+STBridge_GUID="{29184208-E12E-417f-89B0-D90B17BD96C6}"

tools/Drivers/stsw-link009_v3/stlink_dbg_winusb.inf

@@ -0,0 +1,146 @@
+;
+; Installation INF for the STMicroelectronics STLINK (debug and usb loader interfaces) for Windows XP SP2 or later.
+;
+
+[Version]
+Signature = "$Windows NT$"
+Class     = STLinkWinUSB
+ClassGUID = {88BAE032-5A81-49f0-BC3D-A4FF138216D6}
+Provider  = %ManufacturerName%
+CatalogFile.NTx86  = STLinkDbgWinUSB_x86.cat
+CatalogFile.NTAMD64 = STLinkDbgWinUSB_x64.cat
+DriverVer=06/08/2017,2.01
+
+; ========== Manufacturer/Models sections ===========
+
+[Manufacturer]
+%ManufacturerName% = Standard,NTx86,NTamd64
+
+[Standard.NTx86]
+%DeviceName% =USB_Install, USB\VID_0483&PID_3748
+%DeviceName% =USB_Install, USB\VID_0483&PID_374A&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_374B&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_374E&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_374F&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_3752&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_3753&MI_00
+%DeviceNameRW% =USB_InstallRW, USB\VID_0483&PID_374A&MI_01
+%DeviceNameUsbLoader% =USB_Install, USB\VID_0483&PID_374D
+
+[Standard.NTamd64]
+%DeviceName% =USB_Install, USB\VID_0483&PID_3748
+%DeviceName% =USB_Install, USB\VID_0483&PID_374A&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_374B&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_374E&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_374F&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_3752&MI_00
+%DeviceName% =USB_Install, USB\VID_0483&PID_3753&MI_00
+%DeviceNameRW% =USB_InstallRW, USB\VID_0483&PID_374A&MI_01
+%DeviceNameUsbLoader% =USB_Install, USB\VID_0483&PID_374D
+
+; ========== Class definition ===========
+
+[ClassInstall32]
+AddReg = ClassInstall_AddReg
+
+[ClassInstall_AddReg]
+HKR,,,,%ClassName%
+HKR,,NoInstallClass,,1
+HKR,,IconPath,%REG_MULTI_SZ%,"%systemroot%\system32\setupapi.dll,-20"
+HKR,,LowerLogoVersion,,5.2
+
+; =================== Installation ===================
+
+[USB_Install]
+Include = winusb.inf
+Needs   = WINUSB.NT
+
+[USB_InstallRW]
+Include = winusb.inf
+Needs   = WINUSB.NT
+
+[USB_Install.Services]
+Include =winusb.inf
+Addservice = WinUSB, 0x00000002, WinUSB_ServiceInstall
+
+[USB_InstallRW.Services]
+Include =winusb.inf
+Addservice = WinUSB, 0x00000002, WinUSB_ServiceInstall
+
+[WinUSB_ServiceInstall]
+DisplayName    = %WinUSB_SvcDesc%
+ServiceType    = 1                  ; SERVICE_KERNEL_DRIVER
+StartType      = 3                  ; SERVICE_DEMAND_START
+ErrorControl   = 1                  ; SERVICE_ERROR_NORMAL
+ServiceBinary  = %12%\WinUSB.sys
+
+[USB_Install.Wdf]
+KmdfService=WINUSB, WinUsb_Install
+
+[USB_InstallRW.Wdf]
+KmdfService=WINUSB, WinUsb_Install
+
+[WinUsb_Install]
+KmdfLibraryVersion=1.9
+
+[USB_Install.HW]
+AddReg=Dev_AddReg
+
+[USB_InstallRW.HW]
+AddReg=Dev_AddRegRW
+
+[Dev_AddReg]
+HKR,,DeviceInterfaceGUIDs,0x10000,%STLink_GUID%
+
+[Dev_AddRegRW]
+HKR,,DeviceInterfaceGUIDs,0x10000,%STLink_GUID_RW%
+
+[USB_Install.CoInstallers]
+AddReg=CoInstallers_AddReg
+CopyFiles=CoInstallers_CopyFiles
+
+[USB_InstallRW.CoInstallers]
+AddReg=CoInstallers_AddReg
+CopyFiles=CoInstallers_CopyFiles
+
+[CoInstallers_CopyFiles]
+WinUSBCoInstaller2.dll
+WdfCoInstaller01009.dll
+
+[CoInstallers_AddReg]
+HKR,,CoInstallers32,0x00010000,"WdfCoInstaller01009.dll,WdfCoInstaller","WinUSBCoInstaller2.dll"
+
+[DestinationDirs]
+; If your INF needs to copy files, you must not use the DefaultDestDir directive here.  
+; You must explicitly reference all file-list-section names in this section.
+CoInstallers_CopyFiles=11
+
+; ================= Source Media Section =====================
+
+[SourceDisksNames]
+1 = %DISK_NAME%,,,\x86
+2 = %DISK_NAME%,,,\amd64
+
+[SourceDisksFiles.x86]
+WinUSBCoInstaller2.dll=1
+WdfCoInstaller01009.dll=1
+
+[SourceDisksFiles.amd64]
+WinUSBCoInstaller2.dll=2
+WdfCoInstaller01009.dll=2
+
+; =================== Strings ===================
+
+[Strings]
+ManufacturerName="STMicroelectronics"
+ClassName="Universal Serial Bus devices"
+DeviceName="STMicroelectronics STLink dongle"
+DeviceNameRW="STMicroelectronics STLink dongle RW"
+DeviceNameUsbLoader="STMicroelectronics STLink USB Loader"
+WinUSB_SvcDesc="WinUSB Driver for STLink"
+REG_MULTI_SZ = 0x00010000
+DISK_NAME="WinUSB coinstallers sources on disk"
+
+;------------Replace GUID below with custom GUID-------------;
+STLink_GUID="{DBCE1CD9-A320-4b51-A365-A0C3F3C5FB29}"
+STLink_GUID_RW="{8326506F-7260-4854-9C03-26E416F04494}"

tools/Drivers/stsw-link009_v3/stlink_winusb_install.bat

@@ -0,0 +1,12 @@
+@echo off
+REM If enough rights, check the machine architecture
+if /I "%PROCESSOR_ARCHITECTURE%"=="AMD64" goto AMD64
+REM If here, we are running a 32-bit version of cmd; but still may be on a 64-bit machine
+if /I "%PROCESSOR_ARCHITEW6432%"=="AMD64" goto AMD64
+start "" "%~dp0/dpinst_x86.exe"
+goto END
+
+:AMD64
+start "" "%~dp0/dpinst_amd64.exe"
+
+:END