sim3x.cfg 1.2 KB

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  1. #
  2. # Silicon Laboratories SiM3x Cortex-M3
  3. #
  4. # SiM3x devices support both JTAG and SWD transports.
  5. source [find target/swj-dp.tcl]
  6. if { [info exists CHIPNAME] } {
  7. set _CHIPNAME $CHIPNAME
  8. } else {
  9. set _CHIPNAME SiM3x
  10. }
  11. if { [info exists CPUTAPID] } {
  12. set _CPUTAPID $CPUTAPID
  13. } else {
  14. set _CPUTAPID 0x4ba00477
  15. }
  16. if { [info exists CPURAMSIZE] } {
  17. set _CPURAMSIZE $CPURAMSIZE
  18. } else {
  19. # Minimum size of RAM in the Silicon Labs product matrix (8KB)
  20. set _CPURAMSIZE 0x2000
  21. }
  22. if { [info exists CPUROMSIZE] } {
  23. set _CPUROMSIZE $CPUROMSIZE
  24. } else {
  25. # Minimum size of FLASH in the Silicon Labs product matrix (32KB)
  26. set _CPUROMSIZE 0x8000
  27. }
  28. if { [info exists WORKAREASIZE] } {
  29. set _WORKAREASIZE $WORKAREASIZE
  30. } else {
  31. set _WORKAREASIZE $_CPURAMSIZE
  32. }
  33. swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
  34. dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  35. set _TARGETNAME $_CHIPNAME.cpu
  36. target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
  37. $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
  38. set _FLASHNAME $_CHIPNAME.flash
  39. flash bank $_FLASHNAME sim3x 0 $_CPUROMSIZE 0 0 $_TARGETNAME
  40. adapter speed 1000
  41. adapter srst delay 100
  42. if {[using_jtag]} {
  43. jtag_ntrst_delay 100
  44. }