bootloader: Can boot to IDF scheduler start on internal-use FPGA

On ESP32 & ESP32-S2. Patch doesn't include changes to make the app run fully.

components/bootloader_support/src/bootloader_common_loader.c

@@ -67,6 +67,8 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
         ESP_LOGE(TAG, "mismatch chip ID, expected %d, found %d", chip_id, img_hdr->chip_id);
         err = ESP_FAIL;
     }
+
+#ifndef CONFIG_IDF_ENV_FPGA
     uint8_t revision = bootloader_common_get_chip_revision();
     if (revision < img_hdr->min_chip_rev) {
         /* To fix this error, please update mininum supported chip revision from configuration,
@@ -78,6 +80,8 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
         ESP_LOGI(TAG, "chip revision: %d, min. %s chip revision: %d", revision, type == ESP_IMAGE_BOOTLOADER ? "bootloader" : "application", img_hdr->min_chip_rev);
 #endif
     }
+#endif // CONFIG_IDF_ENV_FPGA
+
     return err;
 }
 

components/bootloader_support/src/bootloader_random.c

@@ -46,4 +46,26 @@
     }
 }
 
+#ifndef CONFIG_IDF_ENV_FPGA
+
+#else // CONFIG_IDF_ENV_FPGA
+#include "esp_log.h"
+
+static void s_non_functional(const char *func)
+{
+    ESP_EARLY_LOGW("rand", "%s non-functional for FPGA builds", func);
+}
+
+void bootloader_random_enable()
+{
+    s_non_functional(__func__);
+}
+
+void bootloader_random_disable()
+{
+    s_non_functional(__func__);
+}
+
+#endif // CONFIG_IDF_ENV_FPGA
+
 #endif // BOOTLOADER_BUILD

components/esp_hw_support/port/esp32/rtc_clk_init.c

@@ -140,6 +140,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
 
 static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
 {
+#ifndef CONFIG_IDF_ENV_FPGA
     /* Enable 8M/256 clock if needed */
     const bool clk_8m_enabled = rtc_clk_8m_enabled();
     const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
@@ -172,4 +173,8 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
     }
     /* Restore 8M and 8md256 clocks to original state */
     rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
+
+#else // CONFIG_IDF_ENV_FPGA
+    return RTC_XTAL_FREQ_40M;
+#endif // CONFIG_IDF_ENV_FPGA
 }