refactor(mcpwm): add RCC related LL functions

components/driver/deprecated/mcpwm_legacy.c

@@ -46,6 +46,18 @@ _Static_assert(MCPWM_UNIT_MAX == SOC_MCPWM_GROUPS, "MCPWM unit number not equal
 #define MCPWM_INTR_FLAG  0
 #endif
 
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define MCPWM_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define MCPWM_CLOCK_SRC_ATOMIC()
+#endif
+
+#if !SOC_RCC_IS_INDEPENDENT
+#define MCPWM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define MCPWM_RCC_ATOMIC()
+#endif
+
 // Note: we can't modify the default MCPWM group resolution once it's determined
 // otherwise we may break user's existing code which configures the dead-time based on this resolution, see `mcpwm_deadtime_enable`
 #if CONFIG_IDF_TARGET_ESP32H2
@@ -93,6 +105,7 @@ typedef struct {
     int timer_resolution_hz[SOC_MCPWM_TIMERS_PER_GROUP];
     intr_handle_t mcpwm_intr_handle;  // handler for ISR register, one per MCPWM group
     cap_isr_func_t cap_isr_func[SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER]; // handler for ISR callback, one for each cap ch
+    int module_ref_count;
 } mcpwm_context_t;
 
 static mcpwm_context_t context[SOC_MCPWM_GROUPS] = {
@@ -132,6 +145,31 @@ static inline void mcpwm_mutex_unlock(mcpwm_unit_t mcpwm_num)
     _lock_release(&context[mcpwm_num].mutex_lock);
 }
 
+static void mcpwm_module_enable(mcpwm_unit_t mcpwm_num)
+{
+    mcpwm_critical_enter(mcpwm_num);
+    if (context[mcpwm_num].module_ref_count == 0) {
+        MCPWM_RCC_ATOMIC() {
+            mcpwm_ll_enable_bus_clock(mcpwm_num, true);
+            mcpwm_ll_reset_register(mcpwm_num);
+        }
+    }
+    context[mcpwm_num].module_ref_count++;
+    mcpwm_critical_exit(mcpwm_num);
+}
+
+static void mcpwm_module_disable(mcpwm_unit_t mcpwm_num)
+{
+    mcpwm_critical_enter(mcpwm_num);
+    context[mcpwm_num].module_ref_count--;
+    if (context[mcpwm_num].module_ref_count == 0) {
+        MCPWM_RCC_ATOMIC() {
+            mcpwm_ll_enable_bus_clock(mcpwm_num, false);
+        }
+    }
+    mcpwm_critical_exit(mcpwm_num);
+}
+
 esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num)
 {
     if (gpio_num < 0) { // ignore on minus gpio number
@@ -231,9 +269,9 @@ esp_err_t mcpwm_group_set_resolution(mcpwm_unit_t mcpwm_num, uint32_t resolution
     ESP_RETURN_ON_FALSE(pre_scale_temp >= 1, ESP_ERR_INVALID_ARG, TAG, "invalid resolution");
     context[mcpwm_num].group_resolution_hz = clk_src_hz / pre_scale_temp;
 
-    mcpwm_critical_enter(mcpwm_num);
-    mcpwm_ll_group_set_clock_prescale(hal->dev, pre_scale_temp);
-    mcpwm_critical_exit(mcpwm_num);
+    MCPWM_CLOCK_SRC_ATOMIC() {
+        mcpwm_ll_group_set_clock_prescale(hal->dev, pre_scale_temp);
+    }
     return ESP_OK;
 }
 
@@ -408,7 +446,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
     const int op = timer_num;
     MCPWM_TIMER_ID_CHECK(mcpwm_num, op);
     mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
-    periph_module_enable(mcpwm_periph_signals.groups[mcpwm_num].module);
+    mcpwm_module_enable(mcpwm_num);
     mcpwm_hal_init_config_t config = {
         .group_id = mcpwm_num
     };
@@ -421,10 +459,13 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw
     uint32_t group_pre_scale = clk_src_hz / group_resolution;
     uint32_t timer_pre_scale = group_resolution / timer_resolution;
 
+    MCPWM_CLOCK_SRC_ATOMIC() {
+        mcpwm_ll_group_enable_clock(hal->dev, true);
+        mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
+        mcpwm_ll_group_set_clock_prescale(hal->dev, group_pre_scale);
+    }
+
     mcpwm_critical_enter(mcpwm_num);
-    mcpwm_ll_group_enable_clock(hal->dev, true);
-    mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
-    mcpwm_ll_group_set_clock_prescale(hal->dev, group_pre_scale);
     mcpwm_ll_timer_set_clock_prescale(hal->dev, timer_num, timer_pre_scale);
     mcpwm_ll_timer_set_count_mode(hal->dev, timer_num, mcpwm_conf->counter_mode);
     mcpwm_ll_timer_update_period_at_once(hal->dev, timer_num);
@@ -804,7 +845,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
     mcpwm_hal_context_t *hal = &context[mcpwm_num].hal;
 
     // enable MCPWM module incase user don't use `mcpwm_init` at all. always increase reference count
-    periph_module_enable(mcpwm_periph_signals.groups[mcpwm_num].module);
+    mcpwm_module_enable(mcpwm_num);
 
     mcpwm_hal_init_config_t init_config = {
         .group_id = mcpwm_num
@@ -816,10 +857,13 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha
     uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num);
     uint32_t group_pre_scale = clk_src_hz / group_resolution;
 
+    MCPWM_CLOCK_SRC_ATOMIC() {
+        mcpwm_ll_group_enable_clock(hal->dev, true);
+        mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
+        mcpwm_ll_group_set_clock_prescale(hal->dev, group_pre_scale);
+    }
+
     mcpwm_critical_enter(mcpwm_num);
-    mcpwm_ll_group_enable_clock(hal->dev, true);
-    mcpwm_ll_group_set_clock_source(hal->dev, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT);
-    mcpwm_ll_group_set_clock_prescale(hal->dev, group_pre_scale);
     mcpwm_ll_capture_enable_timer(hal->dev, true);
     mcpwm_ll_capture_enable_channel(hal->dev, cap_channel, true);
     mcpwm_ll_capture_enable_negedge(hal->dev, cap_channel, cap_conf->cap_edge & MCPWM_NEG_EDGE);
@@ -878,7 +922,7 @@ esp_err_t mcpwm_capture_disable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_ch
     mcpwm_mutex_unlock(mcpwm_num);
 
     // always decrease reference count
-    periph_module_disable(mcpwm_periph_signals.groups[mcpwm_num].module);
+    mcpwm_module_disable(mcpwm_num);
     return ret;
 }
 

components/driver/mcpwm/mcpwm_com.c

@@ -20,6 +20,18 @@
 #include "hal/mcpwm_ll.h"
 #include "mcpwm_private.h"
 
+#if SOC_PERIPH_CLK_CTRL_SHARED
+#define MCPWM_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define MCPWM_CLOCK_SRC_ATOMIC()
+#endif
+
+#if !SOC_RCC_IS_INDEPENDENT
+#define MCPWM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define MCPWM_RCC_ATOMIC()
+#endif
+
 static const char *TAG = "mcpwm";
 
 typedef struct {
@@ -46,8 +58,10 @@ mcpwm_group_t *mcpwm_acquire_group_handle(int group_id)
             group->intr_priority = -1;
             group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
             // enable APB to access MCPWM registers
-            periph_module_enable(mcpwm_periph_signals.groups[group_id].module);
-            periph_module_reset(mcpwm_periph_signals.groups[group_id].module);
+            MCPWM_RCC_ATOMIC() {
+                mcpwm_ll_enable_bus_clock(group_id, true);
+                mcpwm_ll_reset_register(group_id);
+            }
             // initialize HAL context
             mcpwm_hal_init_config_t hal_config = {
                 .group_id = group_id
@@ -57,7 +71,11 @@ mcpwm_group_t *mcpwm_acquire_group_handle(int group_id)
             // disable all interrupts and clear pending status
             mcpwm_ll_intr_enable(hal->dev, UINT32_MAX, false);
             mcpwm_ll_intr_clear_status(hal->dev, UINT32_MAX);
-            mcpwm_ll_group_enable_clock(hal->dev, true);
+
+            // enable function clock
+            MCPWM_CLOCK_SRC_ATOMIC() {
+                mcpwm_ll_group_enable_clock(group->hal.dev, true);
+            }
         }
     } else { // group already install
         group = s_platform.groups[group_id];
@@ -84,10 +102,14 @@ void mcpwm_release_group_handle(mcpwm_group_t *group)
     if (s_platform.group_ref_counts[group_id] == 0) {
         do_deinitialize = true;
         s_platform.groups[group_id] = NULL; // deregister from platfrom
-        mcpwm_ll_group_enable_clock(group->hal.dev, false);
+        MCPWM_CLOCK_SRC_ATOMIC() {
+            mcpwm_ll_group_enable_clock(group->hal.dev, false);
+        }
         // hal layer deinitialize
         mcpwm_hal_deinit(&group->hal);
-        periph_module_disable(mcpwm_periph_signals.groups[group_id].module);
+        MCPWM_RCC_ATOMIC() {
+            mcpwm_ll_enable_bus_clock(group_id, false);
+        }
         free(group);
     }
     _lock_release(&s_platform.mutex);
@@ -149,12 +171,14 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_s
         ESP_LOGD(TAG, "install NO_LIGHT_SLEEP lock for MCPWM group(%d)", group->group_id);
 #endif // CONFIG_PM_ENABLE
 
-        mcpwm_ll_group_set_clock_source(group->hal.dev, clk_src);
+        MCPWM_CLOCK_SRC_ATOMIC() {
+            mcpwm_ll_group_set_clock_source(group->hal.dev, clk_src);
+        }
     }
     return ret;
 }
 
-esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolution_hz, uint32_t module_prescale_max, uint32_t* ret_module_prescale)
+esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolution_hz, uint32_t module_prescale_max, uint32_t *ret_module_prescale)
 {
     ESP_RETURN_ON_FALSE(group && expect_module_resolution_hz && module_prescale_max, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
     uint32_t periph_src_clk_hz = 0;
@@ -206,7 +230,9 @@ esp_err_t mcpwm_set_prescale(mcpwm_group_t *group, uint32_t expect_module_resolu
     if (group->prescale == 0) {
         group->prescale = group_prescale;
         group->resolution_hz = group_resolution_hz;
-        mcpwm_ll_group_set_clock_prescale(group->hal.dev, group_prescale);
+        MCPWM_CLOCK_SRC_ATOMIC() {
+            mcpwm_ll_group_set_clock_prescale(group->hal.dev, group_prescale);
+        }
     } else {
         prescale_conflict = (group->prescale != group_prescale);
     }

components/hal/esp32/include/hal/mcpwm_ll.h

@@ -17,6 +17,7 @@
 #include <stdbool.h>
 #include "soc/soc_caps.h"
 #include "soc/mcpwm_struct.h"
+#include "soc/dport_reg.h"
 #include "hal/mcpwm_types.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
@@ -67,6 +68,49 @@ typedef enum {
 
 ////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
 
+/**
+ * @brief Enable the bus clock for MCPWM module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void mcpwm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
+    if (group_id == 0) {
+        reg_val &= ~DPORT_PWM0_CLK_EN;
+        reg_val |= enable << 17;
+    } else {
+        reg_val &= ~DPORT_PWM1_CLK_EN;
+        reg_val |= enable << 20;
+    }
+    DPORT_WRITE_PERI_REG(DPORT_PERIP_CLK_EN_REG, reg_val);
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the MCPWM module
+ *
+ * @param group_id Group ID
+ */
+static inline void mcpwm_ll_reset_register(int group_id)
+{
+    if (group_id == 0) {
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_PWM0_RST);
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
+    } else {
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, DPORT_PWM1_RST);
+        DPORT_WRITE_PERI_REG(DPORT_PERIP_RST_EN_REG, 0);
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief Set the clock source for MCPWM
  *

components/hal/esp32c6/include/hal/mcpwm_ll.h

@@ -76,6 +76,30 @@ typedef enum {
 
 ////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
 
+/**
+ * @brief Enable the bus clock for MCPWM module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void mcpwm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    PCR.pwm_conf.pwm_clk_en = enable;
+}
+
+/**
+ * @brief Reset the MCPWM module
+ *
+ * @param group_id Group ID
+ */
+static inline void mcpwm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.pwm_conf.pwm_rst_en = 1;
+    PCR.pwm_conf.pwm_rst_en = 0;
+}
+
 /**
  * @brief Set the clock source for MCPWM
  *

components/hal/esp32h2/include/hal/mcpwm_ll.h

@@ -74,6 +74,30 @@ typedef enum {
 
 ////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
 
+/**
+ * @brief Enable the bus clock for MCPWM module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void mcpwm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    PCR.pwm_conf.pwm_clk_en = enable;
+}
+
+/**
+ * @brief Reset the MCPWM module
+ *
+ * @param group_id Group ID
+ */
+static inline void mcpwm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.pwm_conf.pwm_rst_en = 1;
+    PCR.pwm_conf.pwm_rst_en = 0;
+}
+
 /**
  * @brief Set the clock source for MCPWM
  *

components/hal/esp32p4/include/hal/clk_gate_ll.h

@@ -72,10 +72,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return HP_SYS_CLKRST_REG_I3C_MST_CLK_EN;
     case PERIPH_CAM_MODULE:
         return HP_SYS_CLKRST_REG_CAM_CLK_EN;
-    case PERIPH_MCPWM0_MODULE:
-        return HP_SYS_CLKRST_REG_MCPWM0_APB_CLK_EN;
-    case PERIPH_MCPWM1_MODULE:
-        return HP_SYS_CLKRST_REG_MCPWM1_APB_CLK_EN;
     case PERIPH_SYSTIMER_MODULE:
         return HP_SYS_CLKRST_REG_SYSTIMER_CLK_EN;
     case PERIPH_LEDC_MODULE:
@@ -104,8 +100,6 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN;
     case PERIPH_ISP_MODULE:
         return HP_SYS_CLKRST_REG_ISP_CLK_EN;
-    case PERIPH_PCNT_MODULE:
-        return HP_SYS_CLKRST_REG_PCNT_APB_CLK_EN;
     default:
         return 0;
     }
@@ -155,10 +149,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return HP_SYS_CLKRST_REG_RST_EN_I2C1;
     case PERIPH_RMT_MODULE:
         return HP_SYS_CLKRST_REG_RST_EN_RMT;
-    case PERIPH_MCPWM0_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_PWM0;
-    case PERIPH_MCPWM1_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_PWM1;
     case PERIPH_TWAI0_MODULE:
         return HP_SYS_CLKRST_REG_RST_EN_CAN0;
     case PERIPH_TWAI1_MODULE:
@@ -167,8 +157,6 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return HP_SYS_CLKRST_REG_RST_EN_CAN2;
     case PERIPH_LEDC_MODULE:
         return HP_SYS_CLKRST_REG_RST_EN_LEDC;
-    case PERIPH_PCNT_MODULE:
-        return HP_SYS_CLKRST_REG_RST_EN_PCNT;
     case PERIPH_PARLIO_MODULE:
         return HP_SYS_CLKRST_REG_RST_EN_PARLIO | HP_SYS_CLKRST_REG_RST_EN_PARLIO_RX | HP_SYS_CLKRST_REG_RST_EN_PARLIO_TX;
     case PERIPH_I2S0_MODULE:
@@ -263,10 +251,6 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
     case PERIPH_I3C_MODULE:
     case PERIPH_CAM_MODULE:
         return HP_SYS_CLKRST_PERI_CLK_CTRL119_REG;
-    case PERIPH_MCPWM0_MODULE:
-    case PERIPH_MCPWM1_MODULE:
-    case PERIPH_PCNT_MODULE:
-        return HP_SYS_CLKRST_SOC_CLK_CTRL2_REG;
     case PERIPH_SYSTIMER_MODULE:
     case PERIPH_LEDC_MODULE:
     case PERIPH_RMT_MODULE:
@@ -316,13 +300,10 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
     case PERIPH_I2C1_MODULE:
         return HP_SYS_CLKRST_HP_RST_EN1_REG;
     case PERIPH_RMT_MODULE:
-    case PERIPH_MCPWM0_MODULE:
-    case PERIPH_MCPWM1_MODULE:
     case PERIPH_TWAI0_MODULE:
     case PERIPH_TWAI1_MODULE:
     case PERIPH_TWAI2_MODULE:
     case PERIPH_LEDC_MODULE:
-    case PERIPH_PCNT_MODULE:
     case PERIPH_PARLIO_MODULE:
     case PERIPH_I2S0_MODULE:
         return HP_SYS_CLKRST_HP_RST_EN1_REG;

components/hal/esp32p4/include/hal/mcpwm_ll.h

@@ -93,6 +93,45 @@ typedef enum {
 
 ////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
 
+/**
+ * @brief Enable the bus clock for MCPWM module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void mcpwm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    if (group_id == 0) {
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_mcpwm0_apb_clk_en = enable;
+    } else {
+        HP_SYS_CLKRST.soc_clk_ctrl2.reg_mcpwm1_apb_clk_en = enable;
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the MCPWM module
+ *
+ * @param group_id Group ID
+ */
+static inline void mcpwm_ll_reset_register(int group_id)
+{
+    if (group_id == 0) {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_pwm0 = 1;
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_pwm0 = 0;
+    } else {
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_pwm1 = 1;
+        HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_pwm1 = 0;
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief Set the clock source for MCPWM
  *
@@ -123,6 +162,10 @@ static inline void mcpwm_ll_group_set_clock_source(mcpwm_dev_t *mcpwm, soc_modul
     }
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_group_set_clock_source(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_group_set_clock_source(__VA_ARGS__)
+
 /**
  * @brief Enable MCPWM module clock
  *
@@ -138,6 +181,10 @@ static inline void mcpwm_ll_group_enable_clock(mcpwm_dev_t *mcpwm, bool en)
     }
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_group_enable_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_group_enable_clock(__VA_ARGS__)
+
 /**
  * @brief Set the MCPWM group clock prescale
  *
@@ -155,6 +202,10 @@ static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int pre
     }
 }
 
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_group_set_clock_prescale(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_group_set_clock_prescale(__VA_ARGS__)
+
 /**
  * @brief Enable update MCPWM active registers from shadow registers
  *

components/hal/esp32s3/include/hal/mcpwm_ll.h

@@ -20,6 +20,7 @@
 #include "hal/mcpwm_types.h"
 #include "hal/misc.h"
 #include "hal/assert.h"
+#include "soc/system_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -67,6 +68,45 @@ typedef enum {
 
 ////////////////////////////////////////MCPWM Group Specific////////////////////////////////////////////////////////////
 
+/**
+ * @brief Enable the bus clock for MCPWM module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void mcpwm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    if (group_id == 0) {
+        SYSTEM.perip_clk_en0.pwm0_clk_en = enable;
+    } else {
+        SYSTEM.perip_clk_en0.pwm1_clk_en = enable;
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the MCPWM module
+ *
+ * @param group_id Group ID
+ */
+static inline void mcpwm_ll_reset_register(int group_id)
+{
+    if (group_id == 0) {
+        SYSTEM.perip_rst_en0.pwm0_rst = 1;
+        SYSTEM.perip_rst_en0.pwm0_rst = 0;
+    } else {
+        SYSTEM.perip_rst_en0.pwm1_rst = 1;
+        SYSTEM.perip_rst_en0.pwm1_rst = 0;
+    }
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define mcpwm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; mcpwm_ll_reset_register(__VA_ARGS__)
+
 /**
  * @brief Set the clock source for MCPWM
  *

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1043,6 +1043,10 @@ config SOC_CLK_RC32K_SUPPORTED
     bool
     default y
 
+config SOC_PERIPH_CLK_CTRL_SHARED
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -502,6 +502,8 @@
 #define SOC_CLK_OSC_SLOW_SUPPORTED                (1)     /*!< Support to connect an external oscillator, not a crystal */
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */
 
+#define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC                (1)
 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL                (1)