esp32: move brownout and cache err int setup

components/esp32/CMakeLists.txt

@@ -12,7 +12,6 @@ if(BOOTLOADER_BUILD)
 else()
     # Regular app build
     set(srcs
-        "cache_err_int.c"
         "cache_sram_mmu.c"
         "clk.c"
         "crosscore_int.c"

components/esp32/Kconfig

@@ -487,18 +487,6 @@ menu "ESP32-specific"
         default 6 if ESP32_BROWNOUT_DET_LVL_SEL_6
         default 7 if ESP32_BROWNOUT_DET_LVL_SEL_7
 
-
-        #Reduce PHY TX power when brownout reset
-    config ESP32_REDUCE_PHY_TX_POWER
-        bool "Reduce PHY TX power when brownout reset"
-        depends on ESP32_BROWNOUT_DET
-        default y
-        help
-            When brownout reset occurs, reduce PHY TX power to keep the code running
-
-            # Note about the use of "FRC1" name: currently FRC1 timer is not used for
-            # high resolution timekeeping anymore. Instead the esp_timer API is used.
-            # FRC1 name in the option name is kept for compatibility.
     choice ESP32_TIME_SYSCALL
         prompt "Timers used for gettimeofday function"
         default ESP32_TIME_SYSCALL_USE_RTC_FRC1

components/esp32/include/esp32/brownout.h

@@ -1,31 +0,0 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_BROWNOUT_H
-#define __ESP_BROWNOUT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void esp_brownout_init(void);
-
-void esp_brownout_disable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

components/esp32/include/esp32/cache_err_int.h

@@ -1,33 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-/**
- * @brief initialize cache invalid access interrupt
- *
- * This function enables cache invalid access interrupt source and connects it
- * to interrupt input number ETS_MEMACCESS_ERR_INUM (see soc/soc.h). It is called
- * from the startup code.
- */
-void esp_cache_err_int_init(void);
-
-
-/**
- * @brief get the CPU which caused cache invalid access interrupt
- * @return
- *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
- *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
- *  - (-1) otherwise
- */
-int esp_cache_err_get_cpuid(void);

components/esp32/sdkconfig.rename

@@ -31,7 +31,5 @@ CONFIG_BROWNOUT_DET_LVL_SEL_5                           CONFIG_ESP32_BROWNOUT_DE
 CONFIG_BROWNOUT_DET_LVL_SEL_6                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_6
 CONFIG_BROWNOUT_DET_LVL_SEL_7                           CONFIG_ESP32_BROWNOUT_DET_LVL_SEL_7
 CONFIG_BROWNOUT_DET_LVL                                 CONFIG_ESP32_BROWNOUT_DET_LVL
-CONFIG_REDUCE_PHY_TX_POWER                              CONFIG_ESP32_REDUCE_PHY_TX_POWER
-
 # SPI RAM config
 CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST           CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP

components/esp32/system_api_esp32.c

@@ -33,8 +33,6 @@
 #include "freertos/xtensa_api.h"
 #include "soc/soc_memory_layout.h"
 
-#include "esp32/cache_err_int.h"
-
 /* "inner" restart function for after RTOS, interrupts & anything else on this
  * core are already stopped. Stalls other core, resets hardware,
  * triggers restart.

components/esp32c3/CMakeLists.txt

@@ -11,8 +11,7 @@ if(BOOTLOADER_BUILD)
 else()
     # Regular app build
 
-    set(srcs "cache_err_int.c"
-             "clk.c"
+    set(srcs "clk.c"
              "crosscore_int.c"
              "dport_access.c"
              "esp_hmac.c"

components/esp32c3/include/esp32c3/brownout.h

@@ -1,31 +0,0 @@
-// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_BROWNOUT_H
-#define __ESP_BROWNOUT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void esp_brownout_init(void);
-
-void esp_brownout_disable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

components/esp32c3/include/esp32c3/cache_err_int.h

@@ -1,33 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-/**
- * @brief initialize cache invalid access interrupt
- *
- * This function enables cache invalid access interrupt source and connects it
- * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
- * from the startup code.
- */
-void esp_cache_err_int_init(void);
-
-
-/**
- * @brief get the CPU which caused cache invalid access interrupt
- * @return
- *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
- *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
- *  - (-1) otherwise
- */
-int esp_cache_err_get_cpuid(void);

components/esp32c3/system_api_esp32c3.c

@@ -20,7 +20,6 @@
 #include "esp_efuse.h"
 #include "esp_log.h"
 #include "esp32c3/rom/cache.h"
-#include "esp32c3/cache_err_int.h"
 #include "riscv/riscv_interrupts.h"
 #include "riscv/interrupt.h"
 #include "esp_rom_uart.h"

components/esp32s2/CMakeLists.txt

@@ -11,8 +11,7 @@ if(BOOTLOADER_BUILD)
 else()
     # Regular app build
 
-    set(srcs "cache_err_int.c"
-             "memprot.c"
+    set(srcs "memprot.c"
              "clk.c"
              "crosscore_int.c"
              "dport_access.c"

components/esp32s3/CMakeLists.txt

@@ -12,12 +12,10 @@ if(BOOTLOADER_BUILD)
 else()
     # Regular app build
 
-    set(srcs "cache_err_int.c"
-             "clk.c"
+    set(srcs "clk.c"
              "crosscore_int.c"
              "dport_access.c"
              "esp_crypto_lock.c"
-
              "memprot.c"
              "spiram.c"
              "spiram_psram.c"

components/esp32s3/include/esp32s3/brownout.h

@@ -1,31 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-#ifndef __ESP_BROWNOUT_H
-#define __ESP_BROWNOUT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void esp_brownout_init(void);
-
-void esp_brownout_disable(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

components/esp32s3/include/esp32s3/cache_err_int.h

@@ -1,33 +0,0 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-/**
- * @brief initialize cache invalid access interrupt
- *
- * This function enables cache invalid access interrupt source and connects it
- * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
- * from the startup code.
- */
-void esp_cache_err_int_init(void);
-
-
-/**
- * @brief get the CPU which caused cache invalid access interrupt
- * @return
- *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
- *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
- *  - (-1) otherwise
- */
-int esp_cache_err_get_cpuid(void);

components/esp_system/port/CMakeLists.txt

@@ -1,4 +1,4 @@
-target_include_directories(${COMPONENT_LIB} PRIVATE include .)
+target_include_directories(${COMPONENT_LIB} PRIVATE include . PUBLIC soc)
 
 set(srcs "cpu_start.c" "panic_handler.c" "brownout.c")
 add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" ${srcs})

components/esp_system/port/arch/riscv/panic_arch.c

@@ -18,15 +18,12 @@
 #include "esp_private/panic_internal.h"
 #include "esp_private/panic_reason.h"
 #include "riscv/rvruntime-frames.h"
+#include "cache_err_int.h"
 
-#if CONFIG_IDF_TARGET_ESP32C3
-#include "esp32c3/cache_err_int.h"
-#endif
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #include "esp32c3/memprot.h"
 #endif
 
-
 #define DIM(array) (sizeof(array)/sizeof(*array))
 
 /**

components/esp_system/port/arch/xtensa/panic_arch.c

@@ -21,21 +21,19 @@
 #include "esp_private/panic_reason.h"
 #include "soc/soc.h"
 
+#include "cache_err_int.h"
+
 #include "sdkconfig.h"
 
-#if CONFIG_IDF_TARGET_ESP32
-#include "esp32/cache_err_int.h"
-#else
+#if !CONFIG_IDF_TARGET_ESP32
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
 #include "soc/rtc_cntl_reg.h"
 #if CONFIG_IDF_TARGET_ESP32S2
-#include "esp32s2/cache_err_int.h"
 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #include "esp32s2/memprot.h"
 #endif
 #elif CONFIG_IDF_TARGET_ESP32S3
-#include "esp32s3/cache_err_int.h"
 #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
 #include "esp32s3/memprot.h"
 #endif

components/esp_system/port/cpu_start.c

@@ -23,6 +23,7 @@
 #include "esp_system.h"
 
 #include "esp_efuse.h"
+#include "cache_err_int.h"
 #include "esp_clk_internal.h"
 
 #include "esp_rom_efuse.h"
@@ -33,14 +34,11 @@
 #if CONFIG_IDF_TARGET_ESP32
 #include "soc/dport_reg.h"
 #include "esp32/rtc.h"
-#include "esp32/cache_err_int.h"
 #include "esp32/rom/cache.h"
 #include "esp32/rom/rtc.h"
 #include "esp32/spiram.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/rtc.h"
-#include "esp32s2/brownout.h"
-#include "esp32s2/cache_err_int.h"
 #include "esp32s2/rom/cache.h"
 #include "esp32s2/rom/rtc.h"
 #include "esp32s2/spiram.h"
@@ -48,8 +46,6 @@
 #include "esp32s2/memprot.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/rtc.h"
-#include "esp32s3/brownout.h"
-#include "esp32s3/cache_err_int.h"
 #include "esp32s3/rom/cache.h"
 #include "esp32s3/rom/rtc.h"
 #include "esp32s3/spiram.h"
@@ -60,7 +56,6 @@
 #include "soc/system_reg.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/rtc.h"
-#include "esp32c3/cache_err_int.h"
 #include "esp32s3/rom/cache.h"
 #include "esp32c3/rom/rtc.h"
 #include "soc/cache_memory.h"

components/esp32s2/include/esp32s2/cache_err_int.h → components/esp_system/port/include/cache_err_int.h

@@ -12,6 +12,8 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+#pragma once
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -20,14 +22,17 @@ extern "C" {
  * @brief initialize cache invalid access interrupt
  *
  * This function enables cache invalid access interrupt source and connects it
- * to interrupt input number ETS_MEMACCESS_ERR_INUM (see soc/soc.h). It is called
- * from the startup code.
+ * to interrupt input number. It is called from the startup code.
+ *
+ * On ESP32, the interrupt input number is ETS_MEMACCESS_ERR_INUM. On other targets
+ * it is ETS_CACHEERR_INUM. See soc/soc.h for more information.
  */
 void esp_cache_err_int_init(void);
 
 
 /**
- * @brief get the CPU which caused cache invalid access interrupt
+ * @brief get the CPU which caused cache invalid access interrupt. Helper function in
+ * panic handling.
  * @return
  *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
  *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt

components/esp_system/port/panic_handler.c

@@ -25,21 +25,19 @@
 #include "hal/soc_hal.h"
 #include "hal/cpu_hal.h"
 
+#include "cache_err_int.h"
+
 #include "sdkconfig.h"
 #include "esp_rom_sys.h"
 
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/dport_access.h"
-#include "esp32/cache_err_int.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/memprot.h"
-#include "esp32s2/cache_err_int.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/memprot.h"
-#include "esp32s3/cache_err_int.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/memprot.h"
-#include "esp32c3/cache_err_int.h"
 #endif
 
 #include "esp_private/panic_internal.h"

components/esp_system/port/soc/esp32/CMakeLists.txt

@@ -1,6 +1,7 @@
 set(srcs "dport_panic_highint_hdl.S"
          "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../arch/xtensa/panic_arch.c"
          "../../arch/xtensa/panic_handler_asm.S"
          "../../arch/xtensa/expression_with_stack.c"

components/esp_system/port/soc/esp32/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/port/soc/esp32c3/CMakeLists.txt

@@ -1,5 +1,6 @@
 set(srcs "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../async_memcpy_impl_gdma.c"
          "apb_backup_dma.c"
          "../../arch/riscv/expression_with_stack.c"

components/esp_system/port/soc/esp32c3/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/port/soc/esp32s2/CMakeLists.txt

@@ -2,6 +2,7 @@ set(srcs "async_memcpy_impl_cp_dma.c"
          "dport_panic_highint_hdl.S"
          "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../arch/xtensa/panic_arch.c"
          "../../arch/xtensa/panic_handler_asm.S"
          "../../arch/xtensa/expression_with_stack.c"

components/esp_system/port/soc/esp32s2/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/port/soc/esp32s3/CMakeLists.txt

@@ -1,6 +1,7 @@
 set(srcs "dport_panic_highint_hdl.S"
          "clk.c"
          "reset_reason.c"
+         "cache_err_int.c"
          "../../async_memcpy_impl_gdma.c"
          "../../arch/xtensa/panic_arch.c"
          "../../arch/xtensa/panic_handler_asm.S"

components/esp_system/port/soc/esp32s3/cache_err_int.h

@@ -0,0 +1,2 @@
+#pragma once
+#include "cache_err_int.h"

components/esp_system/sleep_modes.c

@@ -48,6 +48,7 @@
 
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
+#include "brownout.h"
 
 #ifdef CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/cache.h"
@@ -58,7 +59,6 @@
 #include "esp32s2/clk.h"
 #include "esp32s2/rom/cache.h"
 #include "esp32s2/rom/rtc.h"
-#include "esp32s2/brownout.h"
 #include "soc/extmem_reg.h"
 #include "driver/gpio.h"
 #elif CONFIG_IDF_TARGET_ESP32S3

components/esp_system/startup.c

@@ -60,24 +60,22 @@
 #include "esp_private/usb_console.h"
 #include "esp_vfs_cdcacm.h"
 
+#include "brownout.h"
+
 #include "esp_rom_sys.h"
 
 // [refactor-todo] make this file completely target-independent
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/clk.h"
 #include "esp32/spiram.h"
-#include "esp32/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
 #include "esp32s2/clk.h"
 #include "esp32s2/spiram.h"
-#include "esp32s2/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
 #include "esp32s3/clk.h"
 #include "esp32s3/spiram.h"
-#include "esp32s3/brownout.h"
 #elif CONFIG_IDF_TARGET_ESP32C3
 #include "esp32c3/clk.h"
-#include "esp32c3/brownout.h"
 #endif
 /***********************************************/
 

components/esp_wifi/Kconfig

@@ -488,4 +488,12 @@ menu "PHY"
             by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
             2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).
 
+            #Reduce PHY TX power when brownout reset
+    config ESP32_REDUCE_PHY_TX_POWER
+        bool "Reduce PHY TX power when brownout reset"
+        depends on ESP32_BROWNOUT_DET
+        default y
+        help
+            When brownout reset occurs, reduce PHY TX power to keep the code running.
+
 endmenu  # PHY

components/esp_wifi/sdkconfig.rename

@@ -3,3 +3,4 @@
 
 CONFIG_SW_COEXIST_ENABLE                CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE
 CONFIG_MAC_BB_PD                        CONFIG_ESP32_PHY_MAC_BB_PD
+CONFIG_REDUCE_PHY_TX_POWER              CONFIG_ESP32_REDUCE_PHY_TX_POWER