esp32c3: format and clean up interrupt and os port code

components/esp_common/src/int_wdt.c

@@ -1,9 +1,9 @@
-// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -12,14 +12,14 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "sdkconfig.h"
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <stdbool.h>
+#include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
-#include <esp_types.h>
+#include "esp_types.h"
 #include "esp_err.h"
 #include "esp_intr_alloc.h"
 #include "esp_attr.h"
@@ -29,6 +29,7 @@
 #include "driver/periph_ctrl.h"
 #include "esp_int_wdt.h"
 #include "esp_private/system_internal.h"
+#include "hal/cpu_hal.h"
 #include "hal/timer_types.h"
 #include "hal/wdt_hal.h"
 #include "hal/interrupt_controller_hal.h"
@@ -45,7 +46,7 @@ static wdt_hal_context_t iwdt_context;
 
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
 /*
- * This parameter is indicates the response time of Interrupt watchdog to
+ * This parameter is used to indicate the response time of Interrupt watchdog to
  * identify the live lock.
  */
 #define IWDT_LIVELOCK_TIMEOUT_MS    (20)
@@ -58,8 +59,9 @@ extern uint32_t _l4_intr_livelock_counter, _l4_intr_livelock_max;
 //Not static; the ISR assembly checks this.
 bool int_wdt_app_cpu_ticked = false;
 
-static void IRAM_ATTR tick_hook(void) {
-    if (xPortGetCoreID()!=0) {
+static void IRAM_ATTR tick_hook(void)
+{
+    if (cpu_hal_get_core_id() != 0) {
         int_wdt_app_cpu_ticked = true;
     } else {
         //Only feed wdt if app cpu also ticked.
@@ -70,11 +72,11 @@ static void IRAM_ATTR tick_hook(void) {
 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
             _l4_intr_livelock_counter = 0;
             wdt_hal_config_stage(&iwdt_context, WDT_STAGE0,
-                    CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US/(_l4_intr_livelock_max+1), WDT_STAGE_ACTION_INT);                            //Set timeout before interrupt
+                                 CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US / (_l4_intr_livelock_max + 1), WDT_STAGE_ACTION_INT);                    //Set timeout before interrupt
 #else
-            wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);              //Set timeout before interrupt
+            wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);          //Set timeout before interrupt
 #endif
-            wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);   //Set timeout before reset
+            wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
             wdt_hal_feed(&iwdt_context);
             wdt_hal_write_protect_enable(&iwdt_context);
             int_wdt_app_cpu_ticked = false;
@@ -82,32 +84,31 @@ static void IRAM_ATTR tick_hook(void) {
     }
 }
 #else
-static void IRAM_ATTR tick_hook(void) {
+static void IRAM_ATTR tick_hook(void)
+{
 #if !CONFIG_FREERTOS_UNICORE
-    if (xPortGetCoreID()!=0) {
+    if (cpu_hal_get_core_id() != 0) {
         return;
     }
 #endif
     //Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
     wdt_hal_write_protect_disable(&iwdt_context);
     //Reconfigure stage timeouts
-    wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);              //Set timeout before interrupt
-    wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2*CONFIG_ESP_INT_WDT_TIMEOUT_MS*1000/IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);   //Set timeout before reset
+    wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);          //Set timeout before interrupt
+    wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
     wdt_hal_feed(&iwdt_context);
     wdt_hal_write_protect_enable(&iwdt_context);
 }
 #endif
 
 
-void esp_int_wdt_init(void) {
+void esp_int_wdt_init(void)
+{
     periph_module_enable(PERIPH_TIMG1_MODULE);
     //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
     //it to their actual value.
     wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
     wdt_hal_write_protect_disable(&iwdt_context);
-    //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
-    //it to their actual value.
-
     //1st stage timeout: interrupt
     wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
     //2nd stage timeout: reset system
@@ -119,17 +120,14 @@ void esp_int_wdt_init(void) {
 
 void esp_int_wdt_cpu_init(void)
 {
-    assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS<<1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!");
-    esp_register_freertos_tick_hook_for_cpu(tick_hook, xPortGetCoreID());
+    assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!");
+    esp_register_freertos_tick_hook_for_cpu(tick_hook, cpu_hal_get_core_id());
     ESP_INTR_DISABLE(WDT_INT_NUM);
-    intr_matrix_set(xPortGetCoreID(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
+    intr_matrix_set(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
 
-    /* Set the type and priority to cache error interrupts, if supported. */
-#if SOC_INTERRUPT_TYPE_CAN_SET
+    /* Set the type and priority to watch dog interrupts */
+#if SOC_CPU_HAS_FLEXIBLE_INTC
     interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
-#endif
-
-#if SOC_INTERRUPT_LEVEL_CAN_SET
     interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
 #endif
 
@@ -140,15 +138,15 @@ void esp_int_wdt_cpu_init(void)
      */
     _l4_intr_livelock_counter = 0;
     if (soc_has_cache_lock_bug()) {
-        assert((portTICK_PERIOD_MS<<1) <= IWDT_LIVELOCK_TIMEOUT_MS);
-        assert(CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (IWDT_LIVELOCK_TIMEOUT_MS*3));
-        _l4_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS/IWDT_LIVELOCK_TIMEOUT_MS - 1;
+        assert((portTICK_PERIOD_MS << 1) <= IWDT_LIVELOCK_TIMEOUT_MS);
+        assert(CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (IWDT_LIVELOCK_TIMEOUT_MS * 3));
+        _l4_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS / IWDT_LIVELOCK_TIMEOUT_MS - 1;
     }
 #endif
 
-    //We do not register a handler for the interrupt because it is interrupt level 4 which
-    //is not servicable from C. Instead, xtensa_vectors.S has a call to the panic handler for
-    //this interrupt.
+    // We do not register a handler for the watchdog interrupt because:
+    // 1. Interrupt level 4 on Xtensa architecture is not servicable from C
+    // 2. Instead, we set the entry of watchdog interrupt to the panic handler, see riscv/vector.S and xtensa_vectors.S
     ESP_INTR_ENABLE(WDT_INT_NUM);
 }
 

components/esp_system/include/esp_intr_alloc.h

@@ -1,4 +1,4 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -12,8 +12,7 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#ifndef __ESP_INTR_ALLOC_H__
-#define __ESP_INTR_ALLOC_H__
+#pragma once
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -37,24 +36,24 @@ extern "C" {
  */
 
 //Keep the LEVELx values as they are here; they match up with (1<<level)
-#define ESP_INTR_FLAG_LEVEL1		(1<<1)	///< Accept a Level 1 interrupt vector (lowest priority)
-#define ESP_INTR_FLAG_LEVEL2		(1<<2)	///< Accept a Level 2 interrupt vector
-#define ESP_INTR_FLAG_LEVEL3		(1<<3)	///< Accept a Level 3 interrupt vector
-#define ESP_INTR_FLAG_LEVEL4		(1<<4)	///< Accept a Level 4 interrupt vector
-#define ESP_INTR_FLAG_LEVEL5		(1<<5)	///< Accept a Level 5 interrupt vector
-#define ESP_INTR_FLAG_LEVEL6		(1<<6)	///< Accept a Level 6 interrupt vector
-#define ESP_INTR_FLAG_NMI			(1<<7)	///< Accept a Level 7 interrupt vector (highest priority)
-#define ESP_INTR_FLAG_SHARED		(1<<8)	///< Interrupt can be shared between ISRs
-#define ESP_INTR_FLAG_EDGE			(1<<9)	///< Edge-triggered interrupt
-#define ESP_INTR_FLAG_IRAM			(1<<10)	///< ISR can be called if cache is disabled
-#define ESP_INTR_FLAG_INTRDISABLED	(1<<11)	///< Return with this interrupt disabled
-
-#define ESP_INTR_FLAG_LOWMED	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
-#define ESP_INTR_FLAG_HIGH		(ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
-
-#define ESP_INTR_FLAG_LEVELMASK	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
-								 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
-								 ESP_INTR_FLAG_NMI) ///< Mask for all level flags
+#define ESP_INTR_FLAG_LEVEL1        (1<<1)  ///< Accept a Level 1 interrupt vector (lowest priority)
+#define ESP_INTR_FLAG_LEVEL2        (1<<2)  ///< Accept a Level 2 interrupt vector
+#define ESP_INTR_FLAG_LEVEL3        (1<<3)  ///< Accept a Level 3 interrupt vector
+#define ESP_INTR_FLAG_LEVEL4        (1<<4)  ///< Accept a Level 4 interrupt vector
+#define ESP_INTR_FLAG_LEVEL5        (1<<5)  ///< Accept a Level 5 interrupt vector
+#define ESP_INTR_FLAG_LEVEL6        (1<<6)  ///< Accept a Level 6 interrupt vector
+#define ESP_INTR_FLAG_NMI           (1<<7)  ///< Accept a Level 7 interrupt vector (highest priority)
+#define ESP_INTR_FLAG_SHARED        (1<<8)  ///< Interrupt can be shared between ISRs
+#define ESP_INTR_FLAG_EDGE          (1<<9)  ///< Edge-triggered interrupt
+#define ESP_INTR_FLAG_IRAM          (1<<10) ///< ISR can be called if cache is disabled
+#define ESP_INTR_FLAG_INTRDISABLED  (1<<11) ///< Return with this interrupt disabled
+
+#define ESP_INTR_FLAG_LOWMED    (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
+#define ESP_INTR_FLAG_HIGH      (ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
+
+#define ESP_INTR_FLAG_LEVELMASK (ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
+                                 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
+                                 ESP_INTR_FLAG_NMI) ///< Mask for all level flags
 
 
 /** @addtogroup Intr_Alloc_Pseudo_Src
@@ -67,18 +66,18 @@ extern "C" {
  * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
  * pass these pseudo-sources to the functions.
  */
-#define ETS_INTERNAL_TIMER0_INTR_SOURCE		-1 ///< Platform timer 0 interrupt source
-#define ETS_INTERNAL_TIMER1_INTR_SOURCE		-2 ///< Platform timer 1 interrupt source
-#define ETS_INTERNAL_TIMER2_INTR_SOURCE		-3 ///< Platform timer 2 interrupt source
-#define ETS_INTERNAL_SW0_INTR_SOURCE		-4 ///< Software int source 1
-#define ETS_INTERNAL_SW1_INTR_SOURCE		-5 ///< Software int source 2
-#define ETS_INTERNAL_PROFILING_INTR_SOURCE	-6 ///< Int source for profiling
+#define ETS_INTERNAL_TIMER0_INTR_SOURCE     -1 ///< Platform timer 0 interrupt source
+#define ETS_INTERNAL_TIMER1_INTR_SOURCE     -2 ///< Platform timer 1 interrupt source
+#define ETS_INTERNAL_TIMER2_INTR_SOURCE     -3 ///< Platform timer 2 interrupt source
+#define ETS_INTERNAL_SW0_INTR_SOURCE        -4 ///< Software int source 1
+#define ETS_INTERNAL_SW1_INTR_SOURCE        -5 ///< Software int source 2
+#define ETS_INTERNAL_PROFILING_INTR_SOURCE  -6 ///< Int source for profiling
 
 /**@}*/
 
 /** Provides SystemView with positive IRQ IDs, otherwise scheduler events are not shown properly
  */
-#define ETS_INTERNAL_INTR_SOURCE_OFF		(-ETS_INTERNAL_PROFILING_INTR_SOURCE)
+#define ETS_INTERNAL_INTR_SOURCE_OFF        (-ETS_INTERNAL_PROFILING_INTR_SOURCE)
 
 /** Enable interrupt by interrupt number */
 #define ESP_INTR_ENABLE(inum)  esp_intr_enable_source(inum)
@@ -93,7 +92,7 @@ typedef void (*intr_handler_t)(void *arg);
 typedef struct intr_handle_data_t intr_handle_data_t;
 
 /** Handle to an interrupt handler */
-typedef intr_handle_data_t* intr_handle_t ;
+typedef intr_handle_data_t *intr_handle_t ;
 
 /**
  * @brief Mark an interrupt as a shared interrupt
@@ -306,11 +305,18 @@ void esp_intr_enable_source(int inum);
  */
 void esp_intr_disable_source(int inum);
 
+/**
+ * @brief Get the lowest interrupt level from the flags
+ * @param flags The same flags that pass to `esp_intr_alloc_intrstatus` API
+ */
+static inline int esp_intr_flags_to_level(int flags)
+{
+    return __builtin_ffs((flags & ESP_INTR_FLAG_LEVELMASK) >> 1) + 1;
+}
+
 /**@}*/
 
 
 #ifdef __cplusplus
 }
 #endif
-
-#endif

components/esp_system/intr_alloc.c

@@ -1,9 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
 //
 // Unless required by applicable law or agreed to in writing, software
@@ -12,7 +12,6 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
-#include "sdkconfig.h"
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -21,6 +20,7 @@
 #include <esp_types.h>
 #include <limits.h>
 #include <assert.h>
+#include "sdkconfig.h"
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
 #include "esp_err.h"
@@ -48,7 +48,8 @@ Define this to debug the choices made when allocating the interrupt. This leads
 output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
 being triggered, that is why it is separate from the normal LOG* scheme.
 */
-//#define DEBUG_INT_ALLOC_DECISIONS
+// #define DEBUG_INT_ALLOC_DECISIONS
+
 #ifdef DEBUG_INT_ALLOC_DECISIONS
 # define ALCHLOG(...) ESP_EARLY_LOGD(TAG, __VA_ARGS__)
 #else
@@ -240,13 +241,14 @@ static bool is_vect_desc_usable(vector_desc_t *vd, int flags, int cpu, int force
 
 #ifndef SOC_CPU_HAS_FLEXIBLE_INTC
     //Check if the interrupt level is acceptable
-   if (!(flags&(1<<interrupt_controller_hal_get_level(x)))) {
+    if (!(flags&(1<<interrupt_controller_hal_get_level(x)))) {
         ALCHLOG("....Unusable: incompatible level");
         return false;
     }
     //check if edge/level type matches what we want
     if (((flags&ESP_INTR_FLAG_EDGE) && (interrupt_controller_hal_get_type(x)==INTTP_LEVEL)) ||
-        (((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {        ALCHLOG("....Unusable: incompatible trigger type");
+        (((!(flags&ESP_INTR_FLAG_EDGE)) && (interrupt_controller_hal_get_type(x)==INTTP_EDGE)))) {
+        ALCHLOG("....Unusable: incompatible trigger type");
         return false;
     }
 #endif
@@ -557,7 +559,7 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
 
         if (flags & ESP_INTR_FLAG_EDGE) {
             interrupt_controller_hal_edge_int_acknowledge(intr);
-        }      
+        }
 
         vd->source=source;
     }
@@ -587,14 +589,13 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre
 
 #ifdef SOC_CPU_HAS_FLEXIBLE_INTC
     //Extract the level from the interrupt passed flags
-    int level = (__builtin_ffs((flags >> 1) & ESP_INTR_FLAG_LEVELMASK)) + 1;
-
-    interrupt_controller_hal_set_int_level(intr,level);
+    int level = esp_intr_flags_to_level(flags);
+    interrupt_controller_hal_set_int_level(intr, level);
 
     if (flags & ESP_INTR_FLAG_EDGE) {
-        interrupt_controller_hal_set_int_type(intr,INTTP_EDGE);
+        interrupt_controller_hal_set_int_type(intr, INTTP_EDGE);
     } else {
-        interrupt_controller_hal_set_int_type(intr,INTTP_LEVEL);
+        interrupt_controller_hal_set_int_type(intr, INTTP_LEVEL);
     }
 #endif
 

components/freertos/port/riscv/port.c

@@ -102,7 +102,7 @@
  *       to ensure interrupts don't inadvertently become unmasked before the scheduler starts.
  *       As it is stored as part of the task context it will automatically be set to 0 when the first task is started.
  */
-static UBaseType_t uxCriticalNesting = 0;          
+static UBaseType_t uxCriticalNesting = 0;
 static UBaseType_t uxSavedInterruptState = 0;
 BaseType_t uxSchedulerRunning = 0;
 UBaseType_t uxInterruptNesting = 0;
@@ -124,7 +124,6 @@ void vPortEnterCritical(void)
     uxCriticalNesting++;
 
     if (uxCriticalNesting == 1) {
-        //portDISABLE_INTERRUPTS();
         uxSavedInterruptState = state;
     }
 }
@@ -135,7 +134,6 @@ void vPortExitCritical(void)
         uxCriticalNesting--;
         if (uxCriticalNesting == 0) {
             portEXIT_CRITICAL_NESTED(uxSavedInterruptState);
-            //portENABLE_INTERRUPTS();
         }
     }
 }
@@ -169,8 +167,7 @@ void prvTaskExitError(void)
     defined, then stop here so application writers can catch the error. */
     configASSERT(uxCriticalNesting == ~0UL);
     portDISABLE_INTERRUPTS();
-    for (;;)
-        ;
+    abort();
 }
 
 /* Clear current interrupt mask and set given mask */
@@ -227,16 +224,16 @@ IRAM_ATTR void vPortSysTickHandler(void *arg)
 }
 
 BaseType_t xPortStartScheduler(void)
-{    
+{
     uxInterruptNesting = 0;
     uxCriticalNesting = 0;
-    uxSchedulerRunning = 0; 
+    uxSchedulerRunning = 0;
 
     vPortSetupTimer();
 
     esprv_intc_int_set_threshold(1); /* set global INTC masking level */
     riscv_global_interrupts_enable();
-    
+
     vPortYield();
 
     /*Should not get here*/
@@ -251,7 +248,7 @@ void vPortEndScheduler(void)
 
 void vPortYieldOtherCore(BaseType_t coreid)
 {
-    esp_crosscore_int_send_yield(coreid);        
+    esp_crosscore_int_send_yield(coreid);
 }
 
 void vPortYieldFromISR( void )
@@ -266,7 +263,7 @@ void vPortYield(void)
         vPortYieldFromISR();
     } else {
 
-        esp_crosscore_int_send_yield(0);        
+        esp_crosscore_int_send_yield(0);
         /* There are 3-4 instructions of latency between triggering the software
            interrupt and the CPU interrupt happening. Make sure it happened before
            we return, otherwise vTaskDelay() may return and execute 1-2
@@ -277,7 +274,7 @@ void vPortYield(void)
            for an instant yield, and if that happens then the WFI would be
            waiting for the next interrupt to occur...)
         */
-        while(uxSchedulerRunning && uxCriticalNesting == 0 && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0) { }
+        while (uxSchedulerRunning && uxCriticalNesting == 0 && REG_READ(SYSTEM_CPU_INTR_FROM_CPU_0_REG) != 0) {}
     }
 
 }
@@ -295,7 +292,7 @@ BaseType_t xPortInIsrContext(void)
 BaseType_t IRAM_ATTR xPortInterruptedFromISRContext(void)
 {
     /* For single core, this can be the same as xPortInIsrContext() because reading it is atomic */
-	return uxInterruptNesting;
+    return uxInterruptNesting;
 }
 
 

components/freertos/port/riscv/portasm.S

@@ -36,7 +36,7 @@ rtos_int_enter:
     mv t2, a0
 
     /* scheduler not enabled, jump directly to ISR handler */
-    lw t0, uxSchedulerRunning 
+    lw t0, uxSchedulerRunning
     beq t0,zero, rtos_enter_end
 
     /* increments the ISR nesting count */
@@ -44,7 +44,7 @@ rtos_int_enter:
 	lw t4, 0x0(t3)
 	addi t5,t4,1
 	sw  t5, 0x0(t3)
-    
+
     /* If reached here from another low-prio ISR, skip stack pushing to TCB */
 	bne t4,zero, rtos_enter_end
 
@@ -66,8 +66,8 @@ rtos_enter_end:
     .type rtos_int_exit, @function
 rtos_int_exit:
     /* may skip RTOS aware interrupt since scheduler was not started */
-    lw t0, uxSchedulerRunning 
-    beq t0,zero, rtos_exit_end 
+    lw t0, uxSchedulerRunning
+    beq t0,zero, rtos_exit_end
 
     /* update nesting interrupts counter */
     la t2, uxInterruptNesting
@@ -81,7 +81,7 @@ rtos_int_exit:
 isr_skip_decrement:
 
     /* may still have interrupts pending, skip section below and exit */
-    bne t3,zero,rtos_exit_end 
+    bne t3,zero,rtos_exit_end
 
     /* Schedule the next task if a yield is pending */
     la t0, xPortSwitchFlag

components/hal/esp32/include/hal/interrupt_controller_ll.h

@@ -62,7 +62,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
  * @param handler handler invoked when an interrupt occurs
  * @param arg optional argument to pass to the handler
  */
-static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
+static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
 {
     xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
 }
@@ -74,7 +74,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
  *
  * @return argument used by handler of passed interrupt number
  */
-static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
+static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
 {
     return xt_get_interrupt_handler_arg(intr);
 }
@@ -102,10 +102,10 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
 
 /**
  * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
- * 
+ *
  * @param intr interrupt number ranged from 0 to 31
  */
-static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
+static inline void intr_cntrl_ll_edge_int_acknowledge(int intr)
 {
     xthal_set_intclear(1 << intr);
 }

components/hal/esp32c3/include/hal/interrupt_controller_ll.h

@@ -68,7 +68,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
  * @param handler handler invoked when an interrupt occurs
  * @param arg optional argument to pass to the handler
  */
-static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
+static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
 {
     intr_handler_set(intr, (void *)handler, arg);
 }
@@ -80,7 +80,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
  *
  * @return argument used by handler of passed interrupt number
  */
-static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
+static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
 {
     return intr_handler_get_arg(intr);
 }
@@ -120,9 +120,9 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
  *
  * @param intr interrupt number ranged from 0 to 31
  */
-static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)
+static inline void intr_cntrl_ll_edge_int_acknowledge(int intr)
 {
-     REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
+    REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr);
 }
 
 /**

components/hal/esp32s2/include/hal/interrupt_controller_ll.h

@@ -62,7 +62,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
  * @param handler handler invoked when an interrupt occurs
  * @param arg optional argument to pass to the handler
  */
-static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
+static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
 {
     xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
 }
@@ -74,7 +74,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
  *
  * @return argument used by handler of passed interrupt number
  */
-static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
+static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
 {
     return xt_get_interrupt_handler_arg(intr);
 }
@@ -102,7 +102,7 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
 
 /**
  * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
- * 
+ *
  * @param intr interrupt number ranged from 0 to 31
  */
 static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)

components/hal/esp32s3/include/hal/interrupt_controller_ll.h

@@ -62,7 +62,7 @@ static inline bool intr_cntrl_ll_has_handler(uint8_t intr, uint8_t cpu)
  * @param handler handler invoked when an interrupt occurs
  * @param arg optional argument to pass to the handler
  */
-static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void * arg)
+static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler_t handler, void *arg)
 {
     xt_set_interrupt_handler(intr, (xt_handler)handler, arg);
 }
@@ -74,7 +74,7 @@ static inline void intr_cntrl_ll_set_int_handler(uint8_t intr, interrupt_handler
  *
  * @return argument used by handler of passed interrupt number
  */
-static inline void * intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
+static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
 {
     return xt_get_interrupt_handler_arg(intr);
 }
@@ -102,7 +102,7 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
 
 /**
  * @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
- * 
+ *
  * @param intr interrupt number ranged from 0 to 31
  */
 static inline void intr_cntrl_ll_edge_int_acknowledge (int intr)

components/riscv/expression_with_stack_riscv_asm.S

@@ -23,7 +23,7 @@ esp_shared_stack_invoke_function:
 
     /* Set shared stack as new stack pointer */
     mv sp, a1
-    
+
     /* store the ra and previous stack pointer in a safe place */
     addi sp,sp,-4
     sw  t0, 0(sp)
@@ -33,11 +33,11 @@ esp_shared_stack_invoke_function:
     jalr a0, 0
 
     /* gets the ra and stack pointer saved previously */
-    lw  t0, 0(sp)    
+    lw  t0, 0(sp)
     lw  t1, 4(sp)
     addi sp, sp, 4
-    
+
     /* restore both ra and real stack pointer of current task */
-    mv ra, t1    
+    mv ra, t1
     mv sp, t0
     ret

components/riscv/vectors.S

@@ -215,7 +215,7 @@ _interrupt_handler:
 	/* entry */
 	save_regs
 	save_mepc
-	
+
 	/* Before doing anythig preserve the stack pointer */
 	/* It will be saved in current TCB, if needed */
 	mv a0, sp

components/soc/esp32c3/include/soc/soc_caps.h

@@ -43,7 +43,6 @@
 #include "rmt_caps.h"
 #include "spi_caps.h"
 #include "uart_caps.h"
-#include "int_caps.h"
 
 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
 #define SOC_TOUCH_SENSOR_NUM            (0)    /*! No touch sensors on ESP32-C3 */