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@@ -1,5 +1,5 @@
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/*
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- * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
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+ * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -17,11 +17,11 @@
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#include "soc/gpio_struct.h"
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#include "esp_attr.h"
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#ifdef CONFIG_IDF_TARGET_ESP32S3
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-#include "esp32s3/rom/gpio.h"
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+#include "esp_rom/include/esp32s3/rom/gpio.h"
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#endif
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#endif
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-static const char* TAG = "coexist";
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+//static const char* TAG = "coexist";
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const char *esp_coex_version_get(void)
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{
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@@ -246,6 +246,41 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
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switch (wire_type)
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{
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+#ifndef SOC_EXTERNAL_COEX_ADVANCE
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+ case EXTERN_COEX_WIRE_4:
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+ {
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+ /*Input gpio pin setup --> GPIO_BT_PRIORITY_IDX:GPIO_BT_ACTIVE_IDX*/
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+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin0], PIN_FUNC_GPIO);
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+ gpio_set_direction(gpio_pin.in_pin0, GPIO_MODE_INPUT);
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+
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+ esp_rom_gpio_connect_in_signal(gpio_pin.in_pin0, GPIO_BT_ACTIVE_IDX, false);
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+
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+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.in_pin1], PIN_FUNC_GPIO);
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+ gpio_set_direction(gpio_pin.in_pin1, GPIO_MODE_INPUT);
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+
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+ esp_rom_gpio_connect_in_signal(gpio_pin.in_pin1, GPIO_BT_PRIORITY_IDX, false);
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+
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+ /*Output gpio pin setup --> GPIO_WLAN_ACTIVE_IDX: 1 BT, 0 WiFi*/
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+ gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_pin.out_pin0], PIN_FUNC_GPIO);
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+ gpio_set_direction(gpio_pin.out_pin0, GPIO_MODE_OUTPUT);
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+ REG_WRITE(GPIO_ENABLE_W1TC_REG, BIT(gpio_pin.out_pin0));
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+
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+ esp_rom_gpio_connect_out_signal(gpio_pin.out_pin0, GPIO_WLAN_ACTIVE_IDX, false, false);
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+
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+
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+ REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC1_BYPASS, 2);
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+ REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin0), GPIO_PIN1_SYNC2_BYPASS, 2);
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+ REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC1_BYPASS, 2);
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+ REG_SET_FIELD(GPIO_PIN_REG(gpio_pin.in_pin1), GPIO_PIN1_SYNC2_BYPASS, 2);
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+
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+ esp_extern_coex_register_txline(gpio_pin.out_pin1);
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+ int ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
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+ if (ESP_OK != ret) {
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+ return ESP_FAIL;
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+ }
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+ break;
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+ }
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+#endif
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case EXTERN_COEX_WIRE_3:
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{
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#if SOC_EXTERNAL_COEX_ADVANCE
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@@ -424,7 +459,7 @@ esp_err_t esp_extern_coex_register_txline(uint32_t pin)
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ESP_LOGI(TAG, "external coex select output io %d as txline", esp_extern_coex_outpin);
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- gpio_matrix_out(esp_extern_coex_outpin, BB_DIAG9_IDX, false, false);
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+ esp_rom_gpio_matrix_out(esp_extern_coex_outpin, BB_DIAG9_IDX, false, false);
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return ESP_OK;
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}
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