esp_system.c 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /*
  2. * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "esp_system.h"
  7. #include "esp_private/system_internal.h"
  8. #include "esp_heap_caps.h"
  9. #include "freertos/FreeRTOS.h"
  10. #include "freertos/task.h"
  11. #include "soc/cpu.h"
  12. #include "soc/rtc.h"
  13. #include "soc/rtc_cntl_reg.h"
  14. #include "esp_private/panic_internal.h"
  15. #include "esp_rom_uart.h"
  16. #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
  17. #if CONFIG_IDF_TARGET_ESP32S2
  18. #include "esp32s2/memprot.h"
  19. #else
  20. #include "esp_memprot.h"
  21. #endif
  22. #endif
  23. #define SHUTDOWN_HANDLERS_NO 5
  24. static shutdown_handler_t shutdown_handlers[SHUTDOWN_HANDLERS_NO];
  25. void IRAM_ATTR esp_restart_noos_dig(void)
  26. {
  27. // make sure all the panic handler output is sent from UART FIFO
  28. if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
  29. esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
  30. }
  31. // switch to XTAL (otherwise we will keep running from the PLL)
  32. rtc_clk_cpu_freq_set_xtal();
  33. #if CONFIG_IDF_TARGET_ESP32
  34. esp_cpu_unstall(PRO_CPU_NUM);
  35. #endif
  36. // reset the digital part
  37. SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST);
  38. while (true) {
  39. ;
  40. }
  41. }
  42. esp_err_t esp_register_shutdown_handler(shutdown_handler_t handler)
  43. {
  44. for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
  45. if (shutdown_handlers[i] == handler) {
  46. return ESP_ERR_INVALID_STATE;
  47. } else if (shutdown_handlers[i] == NULL) {
  48. shutdown_handlers[i] = handler;
  49. return ESP_OK;
  50. }
  51. }
  52. return ESP_ERR_NO_MEM;
  53. }
  54. esp_err_t esp_unregister_shutdown_handler(shutdown_handler_t handler)
  55. {
  56. for (int i = 0; i < SHUTDOWN_HANDLERS_NO; i++) {
  57. if (shutdown_handlers[i] == handler) {
  58. shutdown_handlers[i] = NULL;
  59. return ESP_OK;
  60. }
  61. }
  62. return ESP_ERR_INVALID_STATE;
  63. }
  64. void IRAM_ATTR esp_restart(void)
  65. {
  66. for (int i = SHUTDOWN_HANDLERS_NO - 1; i >= 0; i--) {
  67. if (shutdown_handlers[i]) {
  68. shutdown_handlers[i]();
  69. }
  70. }
  71. // Disable scheduler on this core.
  72. vTaskSuspendAll();
  73. bool digital_reset_needed = false;
  74. #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
  75. #if CONFIG_IDF_TARGET_ESP32S2
  76. if (esp_memprot_is_intr_ena_any() || esp_memprot_is_locked_any()) {
  77. digital_reset_needed = true;
  78. }
  79. #else
  80. bool is_on = false;
  81. if (esp_mprot_is_intr_ena_any(&is_on) != ESP_OK || is_on) {
  82. digital_reset_needed = true;
  83. } else if (esp_mprot_is_conf_locked_any(&is_on) != ESP_OK || is_on) {
  84. digital_reset_needed = true;
  85. }
  86. #endif
  87. #endif
  88. if (digital_reset_needed) {
  89. esp_restart_noos_dig();
  90. }
  91. esp_restart_noos();
  92. }
  93. uint32_t esp_get_free_heap_size( void )
  94. {
  95. return heap_caps_get_free_size( MALLOC_CAP_DEFAULT );
  96. }
  97. uint32_t esp_get_free_internal_heap_size( void )
  98. {
  99. return heap_caps_get_free_size( MALLOC_CAP_8BIT | MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL );
  100. }
  101. uint32_t esp_get_minimum_free_heap_size( void )
  102. {
  103. return heap_caps_get_minimum_free_size( MALLOC_CAP_DEFAULT );
  104. }
  105. const char *esp_get_idf_version(void)
  106. {
  107. return IDF_VER;
  108. }
  109. void __attribute__((noreturn)) esp_system_abort(const char *details)
  110. {
  111. panic_abort(details);
  112. }