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@@ -476,86 +476,6 @@ void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_nu
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free((void *)buf);
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}
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-void spi_send_data_standard_dma_irq(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
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- spi_chip_select_t chip_select,
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- const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len,
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- plic_irq_callback_t callback, void *ctx, uint32_t priority)
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-{
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- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
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-
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- volatile spi_t *spi_handle = spi[spi_num];
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- spi_set_tmod(spi_num, SPI_TMOD_TRANS);
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-
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- uint8_t dfs_offset;
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- switch(spi_num)
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- {
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- case 0:
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- case 1:
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- dfs_offset = 16;
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- break;
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- case 2:
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- configASSERT(!"Spi Bus 2 Not Support!");
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- break;
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- case 3:
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- default:
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- dfs_offset = 0;
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- break;
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- }
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- uint32_t data_bit_length = (spi_handle->ctrlr0 >> dfs_offset) & 0x1F;
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- spi_transfer_width_t frame_width = spi_get_frame_size(data_bit_length);
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-
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- uint32_t *buf;
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- size_t v_send_len;
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- int i;
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- switch(frame_width)
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- {
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- case SPI_TRANS_INT:
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- buf = malloc(cmd_len + tx_len);
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- for(i = 0; i < cmd_len / 4; i++)
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- buf[i] = ((uint32_t *)cmd_buff)[i];
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- for(i = 0; i < tx_len / 4; i++)
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- buf[cmd_len / 4 + i] = ((uint32_t *)tx_buff)[i];
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- v_send_len = (cmd_len + tx_len) / 4;
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- break;
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- case SPI_TRANS_SHORT:
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- buf = malloc((cmd_len + tx_len) / 2 * sizeof(uint32_t));
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- for(i = 0; i < cmd_len / 2; i++)
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- buf[i] = ((uint16_t *)cmd_buff)[i];
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- for(i = 0; i < tx_len / 2; i++)
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- buf[cmd_len / 2 + i] = ((uint16_t *)tx_buff)[i];
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- v_send_len = (cmd_len + tx_len) / 2;
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- break;
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- default:
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- buf = malloc((cmd_len + tx_len) * sizeof(uint32_t));
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- for(i = 0; i < cmd_len; i++)
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- buf[i] = cmd_buff[i];
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- for(i = 0; i < tx_len; i++)
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- buf[cmd_len + i] = tx_buff[i];
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- v_send_len = cmd_len + tx_len;
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- break;
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- }
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-
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- spi_handle->dmacr = 0x2; /*enable dma transmit*/
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- spi_handle->ssienr = 0x01;
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-
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- spi_dma_context[spi_num] = (spi_dma_context_t){
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- .dmac_channel = channel_num,
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- .spi_num = spi_num,
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- .malloc_buffer = buf,
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- .buffer = (uint8_t *)tx_buff,
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- .buf_len = tx_len,
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- .int_mode = SPI_TMOD_TRANS,
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- .spi_int_instance.callback = callback,
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- .spi_int_instance.ctx = ctx,
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- };
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-
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- dmac_irq_register(channel_num, spi_dma_callback, &spi_dma_context[spi_num], priority);
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- sysctl_dma_select((sysctl_dma_channel_t) channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
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- dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_send_len);
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- spi_handle->ser = 1U << chip_select;
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-}
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-
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void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
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spi_chip_select_t chip_select,
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const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width)
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@@ -925,84 +845,6 @@ void spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num,
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free(write_cmd);
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}
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-void spi_receive_data_standard_dma_irq(dmac_channel_number_t dma_send_channel_num,
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- dmac_channel_number_t dma_receive_channel_num,
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- spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff,
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- size_t cmd_len, uint8_t *rx_buff, size_t rx_len,
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- plic_irq_callback_t callback, void *ctx, uint32_t priority)
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-{
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- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
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- volatile spi_t *spi_handle = spi[spi_num];
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- spi_transfer_width_t frame_width = spi_get_frame_length(spi_num);
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-
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- size_t i;
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- uint32_t *write_cmd;
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- size_t v_recv_len;
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- size_t v_cmd_len;
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- switch(frame_width)
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- {
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- case SPI_TRANS_INT:
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- write_cmd = malloc(cmd_len + rx_len);
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- for(i = 0; i < cmd_len / 4; i++)
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- write_cmd[i] = ((uint32_t *)cmd_buff)[i];
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- v_recv_len = rx_len / 4;
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- v_cmd_len = cmd_len / 4;
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- break;
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- case SPI_TRANS_SHORT:
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- write_cmd = malloc((cmd_len + rx_len) /2 * sizeof(uint32_t));
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- for(i = 0; i < cmd_len / 2; i++)
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- write_cmd[i] = ((uint16_t *)cmd_buff)[i];
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- v_recv_len = rx_len / 2;
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- v_cmd_len = cmd_len / 2;
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- break;
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- default:
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- write_cmd = malloc((cmd_len + rx_len) * sizeof(uint32_t));
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- for(i = 0; i < cmd_len; i++)
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- write_cmd[i] = cmd_buff[i];
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- v_recv_len = rx_len;
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- v_cmd_len = cmd_len;
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- break;
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- }
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-
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- spi_dma_context[spi_num] = (spi_dma_context_t){
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- .dmac_channel = dma_receive_channel_num,
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- .spi_num = spi_num,
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- .malloc_buffer = write_cmd,
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- .buffer = (uint8_t *)rx_buff,
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- .buf_len = v_recv_len,
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- .int_mode = SPI_TMOD_RECV,
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- .spi_int_instance.callback = callback,
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- .spi_int_instance.ctx = ctx,
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- };
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-
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- if(cmd_len == 0)
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- spi_set_tmod(spi_num, SPI_TMOD_RECV);
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- else
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- spi_set_tmod(spi_num, SPI_TMOD_EEROM);
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-
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- spi_handle->ctrlr1 = (uint32_t)(v_recv_len - 1);
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- spi_handle->dmacr = 0x3;
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- spi_handle->ssienr = 0x01;
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-
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- if(cmd_len)
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- {
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- sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
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- dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_cmd_len);
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- }
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- else
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- {
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- spi[spi_num]->dr[0] = 0xffffffff;
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- }
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-
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- dmac_irq_register(dma_receive_channel_num, spi_dma_callback, &spi_dma_context[spi_num], priority);
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- sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2);
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- dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), (void *)write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
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- DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_recv_len);
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-
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- spi_handle->ser = 1U << chip_select;
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-}
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-
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void spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff,
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size_t cmd_len, uint8_t *rx_buff, size_t rx_len)
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{
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@@ -1161,121 +1003,6 @@ void spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num,
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free(write_cmd);
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}
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-void spi_receive_data_multiple_dma_irq(dmac_channel_number_t dma_send_channel_num,
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- dmac_channel_number_t dma_receive_channel_num,
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- spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff,
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- size_t cmd_len, uint8_t *rx_buff, size_t rx_len,
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- plic_irq_callback_t callback, void *ctx, uint32_t priority)
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-{
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- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
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-
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- volatile spi_t *spi_handle = spi[spi_num];
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-
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- uint8_t dfs_offset;
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- switch(spi_num)
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- {
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- case 0:
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- case 1:
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- dfs_offset = 16;
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- break;
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- case 2:
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- configASSERT(!"Spi Bus 2 Not Support!");
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- break;
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- case 3:
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- default:
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- dfs_offset = 0;
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- break;
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- }
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- uint32_t data_bit_length = (spi_handle->ctrlr0 >> dfs_offset) & 0x1F;
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- spi_transfer_width_t frame_width = spi_get_frame_size(data_bit_length);
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-
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- size_t i;
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-
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- uint32_t *write_cmd = NULL;
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- size_t v_recv_len;
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- switch(frame_width)
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- {
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- case SPI_TRANS_INT:
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- v_recv_len = rx_len / 4;
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- break;
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- case SPI_TRANS_SHORT:
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- write_cmd = malloc(cmd_len + rx_len /2 * sizeof(uint32_t));
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- for(i = 0; i < cmd_len; i++)
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- write_cmd[i] = cmd_buff[i];
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- v_recv_len = rx_len / 2;
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- break;
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- default:
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- write_cmd = malloc(cmd_len + rx_len * sizeof(uint32_t));
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- for(i = 0; i < cmd_len; i++)
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- write_cmd[i] = cmd_buff[i];
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- v_recv_len = rx_len;
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- break;
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- }
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-
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- spi_dma_context[spi_num] = (spi_dma_context_t){
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- .dmac_channel = dma_receive_channel_num,
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- .spi_num = spi_num,
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- .malloc_buffer = write_cmd,
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- .buffer = (uint8_t *)rx_buff,
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- .buf_len = v_recv_len,
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- .int_mode = SPI_TMOD_RECV,
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- .spi_int_instance.callback = callback,
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- .spi_int_instance.ctx = ctx,
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- };
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- if(frame_width == SPI_TRANS_INT)
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- {
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- spi_dma_context[spi_num].malloc_buffer = NULL;
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- }
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-
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- if(cmd_len == 0)
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- spi_set_tmod(spi_num, SPI_TMOD_RECV);
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- else
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- spi_set_tmod(spi_num, SPI_TMOD_EEROM);
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-
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- spi_handle->ctrlr1 = (uint32_t)(v_recv_len - 1);
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- spi_handle->dmacr = 0x3;
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- spi_handle->ssienr = 0x01;
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-
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- if(frame_width == SPI_TRANS_INT)
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- {
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- if(cmd_len)
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- {
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- sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
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- dmac_set_single_mode(dma_send_channel_num, cmd_buff, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len);
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- }
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- else
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- {
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- spi[spi_num]->dr[0] = 0xffffffff;
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- }
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-
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- dmac_irq_register(dma_receive_channel_num, spi_dma_callback, &spi_dma_context[spi_num], priority);
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- sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2);
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- dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), (void *)rx_buff, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
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- DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_recv_len);
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- }
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- else
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- {
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- if(cmd_len)
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- {
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- sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
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- dmac_set_single_mode(dma_send_channel_num, write_cmd, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
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- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, cmd_len);
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- }
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- else
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- {
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- spi[spi_num]->dr[0] = 0xffffffff;
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- }
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-
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- dmac_irq_register(dma_receive_channel_num, spi_dma_callback, &spi_dma_context[spi_num], priority);
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- sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2);
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- dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), (void *)write_cmd, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
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- DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, v_recv_len);
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- }
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- spi_handle->ser = 1U << chip_select;
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-
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-}
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-
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void spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff,
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size_t cmd_len, const uint8_t *tx_buff, size_t tx_len)
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{
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@@ -1361,86 +1088,6 @@ void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_nu
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free((void *)buf);
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}
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-void spi_send_data_multiple_dma_irq(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
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- spi_chip_select_t chip_select,
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- const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len,
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- plic_irq_callback_t callback, void *ctx, uint32_t priority)
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-{
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- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
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- volatile spi_t *spi_handle = spi[spi_num];
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-
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- spi_set_tmod(spi_num, SPI_TMOD_TRANS);
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-
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- uint8_t dfs_offset;
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- switch(spi_num)
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- {
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- case 0:
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- case 1:
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- dfs_offset = 16;
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- break;
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- case 2:
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- configASSERT(!"Spi Bus 2 Not Support!");
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- break;
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- case 3:
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- default:
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- dfs_offset = 0;
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- break;
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- }
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- uint32_t data_bit_length = (spi_handle->ctrlr0 >> dfs_offset) & 0x1F;
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- spi_transfer_width_t frame_width = spi_get_frame_size(data_bit_length);
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-
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- uint32_t *buf;
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- size_t v_send_len;
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- int i;
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- switch(frame_width)
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- {
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- case SPI_TRANS_INT:
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- buf = malloc(cmd_len * sizeof(uint32_t) + tx_len);
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- for(i = 0; i < cmd_len; i++)
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- buf[i] = cmd_buff[i];
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- for(i = 0; i < tx_len / 4; i++)
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- buf[cmd_len + i] = ((uint32_t *)tx_buff)[i];
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- v_send_len = cmd_len + tx_len / 4;
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- break;
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- case SPI_TRANS_SHORT:
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- buf = malloc(cmd_len * sizeof(uint32_t) + tx_len / 2 * sizeof(uint32_t));
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- for(i = 0; i < cmd_len; i++)
|
|
|
- buf[i] = cmd_buff[i];
|
|
|
- for(i = 0; i < tx_len / 2; i++)
|
|
|
- buf[cmd_len + i] = ((uint16_t *)tx_buff)[i];
|
|
|
- v_send_len = cmd_len + tx_len / 2;
|
|
|
- break;
|
|
|
- default:
|
|
|
- buf = malloc((cmd_len + tx_len) * sizeof(uint32_t));
|
|
|
- for(i = 0; i < cmd_len; i++)
|
|
|
- buf[i] = cmd_buff[i];
|
|
|
- for(i = 0; i < tx_len; i++)
|
|
|
- buf[cmd_len + i] = tx_buff[i];
|
|
|
- v_send_len = cmd_len + tx_len;
|
|
|
- break;
|
|
|
- }
|
|
|
-
|
|
|
- spi_handle->dmacr = 0x2; /*enable dma transmit*/
|
|
|
- spi_handle->ssienr = 0x01;
|
|
|
-
|
|
|
- spi_dma_context[spi_num] = (spi_dma_context_t){
|
|
|
- .dmac_channel = channel_num,
|
|
|
- .spi_num = spi_num,
|
|
|
- .malloc_buffer = buf,
|
|
|
- .buffer = (uint8_t *)tx_buff,
|
|
|
- .buf_len = tx_len,
|
|
|
- .int_mode = SPI_TMOD_TRANS,
|
|
|
- .spi_int_instance.callback = callback,
|
|
|
- .spi_int_instance.ctx = ctx,
|
|
|
- };
|
|
|
-
|
|
|
- dmac_irq_register(channel_num, spi_dma_callback, &spi_dma_context[spi_num], priority);
|
|
|
- sysctl_dma_select((sysctl_dma_channel_t) channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
|
|
|
- dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
|
|
|
- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, v_send_len);
|
|
|
- spi_handle->ser = 1U << chip_select;
|
|
|
-}
|
|
|
-
|
|
|
void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select,
|
|
|
const uint32_t *tx_buff, size_t tx_len)
|
|
|
{
|
|
|
@@ -1787,123 +1434,6 @@ void spi_slave_config(uint8_t int_pin, uint8_t ready_pin, dmac_channel_number_t
|
|
|
plic_irq_register(IRQN_SPI_SLAVE_INTERRUPT, spi_slave_irq, NULL);
|
|
|
}
|
|
|
|
|
|
-void spi_send_data_normal_dma_irq(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
|
|
|
- spi_chip_select_t chip_select,
|
|
|
- const void *tx_buff, size_t tx_len,
|
|
|
- plic_irq_callback_t callback, void *ctx, uint32_t priority)
|
|
|
-{
|
|
|
- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
|
|
|
- spi_set_tmod(spi_num, SPI_TMOD_TRANS);
|
|
|
- volatile spi_t *spi_handle = spi[spi_num];
|
|
|
- uint32_t *buf;
|
|
|
- int i;
|
|
|
- spi_transfer_width_t frame_width = spi_get_frame_length(spi_num);
|
|
|
- switch(frame_width)
|
|
|
- {
|
|
|
- case SPI_TRANS_SHORT:
|
|
|
- buf = malloc((tx_len) * sizeof(uint32_t));
|
|
|
- for(i = 0; i < tx_len; i++)
|
|
|
- buf[i] = ((uint16_t *)tx_buff)[i];
|
|
|
- break;
|
|
|
- case SPI_TRANS_INT:
|
|
|
- buf = (uint32_t *)tx_buff;
|
|
|
- break;
|
|
|
- case SPI_TRANS_CHAR:
|
|
|
- default:
|
|
|
- buf = malloc((tx_len) * sizeof(uint32_t));
|
|
|
- for(i = 0; i < tx_len; i++)
|
|
|
- buf[i] = ((uint8_t *)tx_buff)[i];
|
|
|
- break;
|
|
|
- }
|
|
|
- spi_handle->dmacr = 0x2; /*enable dma transmit*/
|
|
|
- spi_handle->ssienr = 0x01;
|
|
|
-
|
|
|
- spi_dma_context[spi_num] = (spi_dma_context_t){
|
|
|
- .dmac_channel = channel_num,
|
|
|
- .spi_num = spi_num,
|
|
|
- .malloc_buffer = buf,
|
|
|
- .buffer = (uint8_t *)tx_buff,
|
|
|
- .buf_len = tx_len,
|
|
|
- .int_mode = SPI_TMOD_TRANS,
|
|
|
- .spi_int_instance.callback = callback,
|
|
|
- .spi_int_instance.ctx = ctx,
|
|
|
- };
|
|
|
- if(frame_width == SPI_TRANS_INT)
|
|
|
- {
|
|
|
- spi_dma_context[spi_num].malloc_buffer = NULL;
|
|
|
- }
|
|
|
-
|
|
|
- dmac_irq_register(channel_num, spi_dma_callback, &spi_dma_context[spi_num], priority);
|
|
|
- sysctl_dma_select((sysctl_dma_channel_t) channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
|
|
|
- dmac_set_single_mode(channel_num, buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
|
|
|
- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len);
|
|
|
- spi_handle->ser = 1U << chip_select;
|
|
|
-
|
|
|
-}
|
|
|
-
|
|
|
-void spi_send_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select,
|
|
|
- const uint32_t *tx_buf, size_t tx_len,
|
|
|
- plic_interrupt_t *callback)
|
|
|
-{
|
|
|
- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
|
|
|
- volatile spi_t *spi_handle = spi[spi_num];
|
|
|
-
|
|
|
- spi_set_tmod(spi_num, SPI_TMOD_TRANS);
|
|
|
-
|
|
|
- spi_handle->dmacr = 0x2; /*enable dma transmit*/
|
|
|
- spi_handle->ssienr = 0x01;
|
|
|
-
|
|
|
- if(callback)
|
|
|
- dmac_irq_register(channel_num, callback->callback, callback->ctx, callback->priority);
|
|
|
- sysctl_dma_select((sysctl_dma_channel_t) channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
|
|
|
- dmac_set_single_mode(channel_num, tx_buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
|
|
|
- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len);
|
|
|
- spi_handle->ser = 1U << chip_select;
|
|
|
- if(!callback)
|
|
|
- dmac_wait_idle(channel_num);
|
|
|
-}
|
|
|
-
|
|
|
-void spi_receive_dma(dmac_channel_number_t dma_send_channel_num, dmac_channel_number_t dma_receive_channel_num,
|
|
|
- spi_device_num_t spi_num, spi_chip_select_t chip_select,
|
|
|
- const uint32_t *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len,
|
|
|
- plic_interrupt_t *callback)
|
|
|
-{
|
|
|
- configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
|
|
|
- if(tx_len)
|
|
|
- configASSERT(tx_buf);
|
|
|
- volatile spi_t *spi_handle = spi[spi_num];
|
|
|
-
|
|
|
- if(tx_len == 0)
|
|
|
- spi_set_tmod(spi_num, SPI_TMOD_RECV);
|
|
|
- else
|
|
|
- spi_set_tmod(spi_num, SPI_TMOD_EEROM);
|
|
|
-
|
|
|
- if(rx_len > 65536)
|
|
|
- rx_len = 65536;
|
|
|
- spi_handle->ctrlr1 = (uint32_t)(rx_len - 1);
|
|
|
- spi_handle->dmacr = 0x3;
|
|
|
- spi_handle->ssienr = 0x01;
|
|
|
-
|
|
|
- if(tx_len)
|
|
|
- {
|
|
|
- sysctl_dma_select(dma_send_channel_num, SYSCTL_DMA_SELECT_SSI0_TX_REQ + spi_num * 2);
|
|
|
- dmac_set_single_mode(dma_send_channel_num, tx_buf, (void *)(&spi_handle->dr[0]), DMAC_ADDR_INCREMENT, DMAC_ADDR_NOCHANGE,
|
|
|
- DMAC_MSIZE_4, DMAC_TRANS_WIDTH_32, tx_len);
|
|
|
- }
|
|
|
- else
|
|
|
- {
|
|
|
- spi[spi_num]->dr[0] = 0xffffffff;
|
|
|
- }
|
|
|
- if(callback)
|
|
|
- dmac_irq_register(dma_receive_channel_num, callback->callback, callback->ctx, callback->priority);
|
|
|
- sysctl_dma_select(dma_receive_channel_num, SYSCTL_DMA_SELECT_SSI0_RX_REQ + spi_num * 2);
|
|
|
- dmac_set_single_mode(dma_receive_channel_num, (void *)(&spi_handle->dr[0]), (void *)rx_buf, DMAC_ADDR_NOCHANGE, DMAC_ADDR_INCREMENT,
|
|
|
- DMAC_MSIZE_1, DMAC_TRANS_WIDTH_32, rx_len);
|
|
|
- spi_handle->ser = 1U << chip_select;
|
|
|
- if(!callback)
|
|
|
- dmac_wait_idle(dma_receive_channel_num);
|
|
|
-}
|
|
|
-
|
|
|
void spi_handle_data_dma(spi_device_num_t spi_num, spi_chip_select_t chip_select, spi_data_t data, plic_interrupt_t *cb)
|
|
|
{
|
|
|
configASSERT(spi_num < SPI_DEVICE_MAX && spi_num != 2);
|