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@@ -27,7 +27,7 @@
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#include <common/tusb_common.h>
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#if TUSB_OPT_HOST_ENABLED && \
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- (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
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+ (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX)
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//--------------------------------------------------------------------+
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// INCLUDE
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@@ -84,23 +84,23 @@ enum {
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};
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enum {
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- OHCI_RHPORT_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
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- OHCI_RHPORT_PORT_ENABLE_STATUS_MASK = TU_BIT(1),
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- OHCI_RHPORT_PORT_SUSPEND_STATUS_MASK = TU_BIT(2),
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- OHCI_RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = TU_BIT(3),
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- OHCI_RHPORT_PORT_RESET_STATUS_MASK = TU_BIT(4), ///< write '1' to reset port
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-
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- OHCI_RHPORT_PORT_POWER_STATUS_MASK = TU_BIT(8),
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- OHCI_RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK = TU_BIT(9),
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-
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- OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK = TU_BIT(16),
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- OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK = TU_BIT(17),
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- OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK = TU_BIT(18),
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- OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK = TU_BIT(19),
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- OHCI_RHPORT_PORT_RESET_CHANGE_MASK = TU_BIT(20),
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-
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- OHCI_RHPORT_ALL_CHANGE_MASK = OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK | OHCI_RHPORT_PORT_ENABLE_CHANGE_MASK |
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- OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK | OHCI_RHPORT_OVER_CURRENT_CHANGE_MASK | OHCI_RHPORT_PORT_RESET_CHANGE_MASK
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+ RHPORT_CURRENT_CONNECT_STATUS_MASK = TU_BIT(0),
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+ RHPORT_PORT_ENABLE_STATUS_MASK = TU_BIT(1),
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+ RHPORT_PORT_SUSPEND_STATUS_MASK = TU_BIT(2),
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+ RHPORT_PORT_OVER_CURRENT_INDICATOR_MASK = TU_BIT(3),
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+ RHPORT_PORT_RESET_STATUS_MASK = TU_BIT(4), ///< write '1' to reset port
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+
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+ RHPORT_PORT_POWER_STATUS_MASK = TU_BIT(8),
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+ RHPORT_LOW_SPEED_DEVICE_ATTACHED_MASK = TU_BIT(9),
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+
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+ RHPORT_CONNECT_STATUS_CHANGE_MASK = TU_BIT(16),
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+ RHPORT_PORT_ENABLE_CHANGE_MASK = TU_BIT(17),
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+ RHPORT_PORT_SUSPEND_CHANGE_MASK = TU_BIT(18),
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+ RHPORT_OVER_CURRENT_CHANGE_MASK = TU_BIT(19),
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+ RHPORT_PORT_RESET_CHANGE_MASK = TU_BIT(20),
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+
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+ RHPORT_ALL_CHANGE_MASK = RHPORT_CONNECT_STATUS_CHANGE_MASK | RHPORT_PORT_ENABLE_CHANGE_MASK |
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+ RHPORT_PORT_SUSPEND_CHANGE_MASK | RHPORT_OVER_CURRENT_CHANGE_MASK | RHPORT_PORT_RESET_CHANGE_MASK
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};
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enum {
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@@ -123,6 +123,23 @@ enum {
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OHCI_INT_ON_COMPLETE_YES = 0,
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OHCI_INT_ON_COMPLETE_NO = TU_BIN8(111)
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};
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+
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+enum {
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+ GTD_DT_TOGGLE_CARRY = 0,
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+ GTD_DT_DATA0 = TU_BIT(1) | 0,
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+ GTD_DT_DATA1 = TU_BIT(1) | 1,
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+};
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+
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+enum {
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+ PID_SETUP = 0,
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+ PID_OUT,
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+ PID_IN,
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+};
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+
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+enum {
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+ PID_FROM_TD = 0,
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+};
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+
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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@@ -185,10 +202,10 @@ bool hcd_init(uint8_t rhport)
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return true;
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}
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-uint32_t hcd_uframe_number(uint8_t rhport)
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+uint32_t hcd_frame_number(uint8_t rhport)
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{
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(void) rhport;
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- return (ohci_data.frame_number_hi << 16 | OHCI_REG->frame_number) << 3;
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+ return (ohci_data.frame_number_hi << 16) | OHCI_REG->frame_number;
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}
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@@ -198,7 +215,7 @@ uint32_t hcd_uframe_number(uint8_t rhport)
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void hcd_port_reset(uint8_t hostid)
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{
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(void) hostid;
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- OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
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+ OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
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}
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bool hcd_port_connect_status(uint8_t hostid)
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@@ -244,16 +261,16 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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-// CONTROL PIPE API
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+// List Helper
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//--------------------------------------------------------------------+
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static inline tusb_xfer_type_t ed_get_xfer_type(ohci_ed_t const * const p_ed)
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{
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- return (p_ed->ep_number == 0 ) ? TUSB_XFER_CONTROL :
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- (p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
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- (p_ed->is_interrupt_xfer ) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
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+ return (p_ed->ep_number == 0 ) ? TUSB_XFER_CONTROL :
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+ (p_ed->is_iso ) ? TUSB_XFER_ISOCHRONOUS :
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+ (p_ed->is_interrupt_xfer) ? TUSB_XFER_INTERRUPT : TUSB_XFER_BULK;
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}
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-static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type, uint8_t interval)
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+static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t ep_size, uint8_t ep_addr, uint8_t xfer_type, uint8_t interval)
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{
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(void) interval;
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@@ -263,18 +280,18 @@ static void ed_init(ohci_ed_t *p_ed, uint8_t dev_addr, uint16_t max_packet_size,
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tu_memclr(p_ed, sizeof(ohci_ed_t));
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}
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- p_ed->dev_addr = dev_addr;
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- p_ed->ep_number = endpoint_addr & 0x0F;
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- p_ed->pid = (xfer_type == TUSB_XFER_CONTROL) ? OHCI_PID_SETUP : ( (endpoint_addr & TUSB_DIR_IN_MASK) ? OHCI_PID_IN : OHCI_PID_OUT );
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+ p_ed->dev_addr = dev_addr;
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+ p_ed->ep_number = ep_addr & 0x0F;
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+ p_ed->pid = (xfer_type == TUSB_XFER_CONTROL) ? PID_FROM_TD : (tu_edpt_dir(ep_addr) ? PID_IN : PID_OUT);
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p_ed->speed = _usbh_devices[dev_addr].speed;
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p_ed->is_iso = (xfer_type == TUSB_XFER_ISOCHRONOUS) ? 1 : 0;
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- p_ed->max_packet_size = max_packet_size;
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+ p_ed->max_packet_size = ep_size;
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p_ed->used = 1;
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p_ed->is_interrupt_xfer = (xfer_type == TUSB_XFER_INTERRUPT ? 1 : 0);
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}
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-static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
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+static void gtd_init(ohci_gtd_t* p_td, uint8_t* data_ptr, uint16_t total_bytes)
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{
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tu_memclr(p_td, sizeof(ohci_gtd_t));
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@@ -286,81 +303,9 @@ static void gtd_init(ohci_gtd_t* p_td, void* data_ptr, uint16_t total_bytes)
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p_td->condition_code = OHCI_CCODE_NOT_ACCESSED;
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p_td->current_buffer_pointer = data_ptr;
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- p_td->buffer_end = total_bytes ? (((uint8_t*) data_ptr) + total_bytes-1) : NULL;
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-}
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-
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-bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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-{
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- (void) rhport;
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-
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- ohci_ed_t* p_ed = &ohci_data.control[dev_addr].ed;
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- ohci_gtd_t *p_setup = &ohci_data.control[dev_addr].gtd;
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-
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- gtd_init(p_setup, (void*) setup_packet, 8);
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- p_setup->index = dev_addr;
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- p_setup->pid = OHCI_PID_SETUP;
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- p_setup->data_toggle = TU_BIN8(10); // DATA0
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- p_setup->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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-
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- //------------- Attach TDs list to Control Endpoint -------------//
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- p_ed->td_head.address = (uint32_t) p_setup;
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-
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- OHCI_REG->command_status_bit.control_list_filled = 1;
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-
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- return true;
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-}
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-
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-// TODO move around
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-static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr);
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-static ohci_gtd_t * gtd_find_free(void);
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-static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd);
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-
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-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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-{
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- (void) rhport;
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-
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- uint8_t const epnum = tu_edpt_number(ep_addr);
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- uint8_t const dir = tu_edpt_dir(ep_addr);
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-
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- // FIXME control only for now
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- if ( epnum == 0 )
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- {
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- ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
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- ohci_gtd_t *p_data = &ohci_data.control[dev_addr].gtd;
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-
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- gtd_init(p_data, buffer, buflen);
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-
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- p_data->index = dev_addr;
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- p_data->pid = dir ? OHCI_PID_IN : OHCI_PID_OUT;
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- p_data->data_toggle = TU_BIN8(11); // DATA1
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- p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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-
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- p_ed->td_head.address = (uint32_t) p_data;
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-
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- OHCI_REG->command_status_bit.control_list_filled = 1;
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- }else
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- {
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- ohci_ed_t * p_ed = ed_from_addr(dev_addr, ep_addr);
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- ohci_gtd_t* p_gtd = gtd_find_free();
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-
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- TU_ASSERT(p_gtd);
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-
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- gtd_init(p_gtd, buffer, buflen);
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- p_gtd->index = p_ed-ohci_data.ed_pool;
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- p_gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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-
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- td_insert_to_ed(p_ed, p_gtd);
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-
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- tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_addr(dev_addr, ep_addr) );
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- if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
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- }
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-
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- return true;
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+ p_td->buffer_end = total_bytes ? (data_ptr + total_bytes-1) : data_ptr;
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}
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-//--------------------------------------------------------------------+
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-// BULK/INT/ISO PIPE API
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-//--------------------------------------------------------------------+
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static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
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{
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if ( tu_edpt_number(ep_addr) == 0 ) return &ohci_data.control[dev_addr].ed;
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@@ -370,7 +315,7 @@ static ohci_ed_t * ed_from_addr(uint8_t dev_addr, uint8_t ep_addr)
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for(uint32_t i=0; i<HCD_MAX_ENDPOINT; i++)
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{
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if ( (ed_pool[i].dev_addr == dev_addr) &&
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- ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == OHCI_PID_IN) )
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+ ep_addr == tu_edpt_addr(ed_pool[i].ep_number, ed_pool[i].pid == PID_IN) )
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{
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return &ed_pool[i];
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}
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@@ -420,9 +365,36 @@ static void ed_list_remove_by_addr(ohci_ed_t * p_head, uint8_t dev_addr)
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}
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}
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+static ohci_gtd_t * gtd_find_free(void)
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+{
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+ for(uint8_t i=0; i < HCD_MAX_XFER; i++)
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+ {
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+ if ( !ohci_data.gtd_pool[i].used ) return &ohci_data.gtd_pool[i];
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+ }
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+
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+ return NULL;
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+}
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+
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+static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
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+{
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+ // tail is always NULL
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+ if ( tu_align16(p_ed->td_head.address) == 0 )
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+ { // TD queue is empty --> head = TD
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+ p_ed->td_head.address |= (uint32_t) p_gtd;
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+ }
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+ else
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+ { // TODO currently only support queue up to 2 TD each endpoint at a time
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+ ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd;
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+ }
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+}
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+
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+//--------------------------------------------------------------------+
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+// Endpoint API
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+//--------------------------------------------------------------------+
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+
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bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
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{
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- (void) rhport;
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+ (void) rhport;
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// TODO iso support
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TU_ASSERT(ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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@@ -454,62 +426,65 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
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return true;
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}
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-static ohci_gtd_t * gtd_find_free(void)
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+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
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{
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- for(uint8_t i=0; i < HCD_MAX_XFER; i++)
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- {
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- if ( !ohci_data.gtd_pool[i].used ) return &ohci_data.gtd_pool[i];
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- }
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+ (void) rhport;
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- return NULL;
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-}
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+ ohci_ed_t* ed = &ohci_data.control[dev_addr].ed;
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+ ohci_gtd_t *qtd = &ohci_data.control[dev_addr].gtd;
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-static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd)
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-{
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- // tail is always NULL
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- if ( tu_align16(p_ed->td_head.address) == 0 )
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- { // TD queue is empty --> head = TD
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- p_ed->td_head.address |= (uint32_t) p_gtd;
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- }
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- else
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- { // TODO currently only support queue up to 2 TD each endpoint at a time
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- ((ohci_gtd_t*) tu_align16(p_ed->td_head.address))->next = (uint32_t) p_gtd;
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- }
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+ gtd_init(qtd, (uint8_t*) setup_packet, 8);
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+ qtd->index = dev_addr;
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+ qtd->pid = PID_SETUP;
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+ qtd->data_toggle = GTD_DT_DATA0;
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+ qtd->delay_interrupt = 0;
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+
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+ //------------- Attach TDs list to Control Endpoint -------------//
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+ ed->td_head.address = (uint32_t) qtd;
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+
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+ OHCI_REG->command_status_bit.control_list_filled = 1;
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+
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+ return true;
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}
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-static bool pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
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+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
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{
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- ohci_ed_t* const p_ed = ed_from_addr(dev_addr, ep_addr);
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+ (void) rhport;
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- // not support ISO yet
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- TU_VERIFY ( !p_ed->is_iso );
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+ uint8_t const epnum = tu_edpt_number(ep_addr);
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+ uint8_t const dir = tu_edpt_dir(ep_addr);
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- ohci_gtd_t * const p_gtd = gtd_find_free();
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- TU_ASSERT(p_gtd); // not enough gtd
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+ if ( epnum == 0 )
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+ {
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+ ohci_ed_t* ed = &ohci_data.control[dev_addr].ed;
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+ ohci_gtd_t* gtd = &ohci_data.control[dev_addr].gtd;
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|
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- gtd_init(p_gtd, buffer, total_bytes);
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- p_gtd->index = p_ed-ohci_data.ed_pool;
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+ gtd_init(gtd, buffer, buflen);
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|
|
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- if ( int_on_complete ) p_gtd->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
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+ gtd->index = dev_addr;
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+ gtd->pid = dir ? PID_IN : PID_OUT;
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+ gtd->data_toggle = GTD_DT_DATA1; // Both Data and Ack stage start with DATA1
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+ gtd->delay_interrupt = 0;
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|
|
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- td_insert_to_ed(p_ed, p_gtd);
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+ ed->td_head.address = (uint32_t) gtd;
|
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|
|
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- return true;
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-}
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+ OHCI_REG->command_status_bit.control_list_filled = 1;
|
|
|
+ }else
|
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|
+ {
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|
+ ohci_ed_t * ed = ed_from_addr(dev_addr, ep_addr);
|
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+ ohci_gtd_t* gtd = gtd_find_free();
|
|
|
|
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-bool hcd_pipe_queue_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes)
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-{
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|
- return pipe_queue_xfer(dev_addr, ep_addr, buffer, total_bytes, false);
|
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-}
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+ TU_ASSERT(gtd);
|
|
|
|
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|
-bool hcd_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t buffer[], uint16_t total_bytes, bool int_on_complete)
|
|
|
-{
|
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|
- (void) int_on_complete;
|
|
|
- TU_ASSERT( pipe_queue_xfer(dev_addr, ep_addr, buffer, total_bytes, true) );
|
|
|
+ gtd_init(gtd, buffer, buflen);
|
|
|
+ gtd->index = ed-ohci_data.ed_pool;
|
|
|
+ gtd->delay_interrupt = 0;
|
|
|
|
|
|
- tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_addr(dev_addr, ep_addr) );
|
|
|
+ td_insert_to_ed(ed, gtd);
|
|
|
|
|
|
- if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
|
|
|
+ tusb_xfer_type_t xfer_type = ed_get_xfer_type( ed_from_addr(dev_addr, ep_addr) );
|
|
|
+ if (TUSB_XFER_BULK == xfer_type) OHCI_REG->command_status_bit.bulk_list_filled = 1;
|
|
|
+ }
|
|
|
|
|
|
return true;
|
|
|
}
|
|
|
@@ -580,7 +555,12 @@ static inline ohci_ed_t* gtd_get_ed(ohci_gtd_t const * const p_qtd)
|
|
|
}
|
|
|
|
|
|
static inline uint32_t gtd_xfer_byte_left(uint32_t buffer_end, uint32_t current_buffer)
|
|
|
-{ // 5.2.9 OHCI sample code
|
|
|
+{
|
|
|
+ // 5.2.9 OHCI sample code
|
|
|
+
|
|
|
+ // CBP is 0 mean all data is transferred
|
|
|
+ if (current_buffer == 0) return 0;
|
|
|
+
|
|
|
return (tu_align4k(buffer_end ^ current_buffer) ? 0x1000 : 0) +
|
|
|
tu_offset4k(buffer_end) - tu_offset4k(current_buffer) + 1;
|
|
|
}
|
|
|
@@ -596,16 +576,16 @@ static void done_queue_isr(uint8_t hostid)
|
|
|
{
|
|
|
// TODO check if td_head is iso td
|
|
|
//------------- Non ISO transfer -------------//
|
|
|
- ohci_gtd_t * const p_qtd = (ohci_gtd_t *) td_head;
|
|
|
- xfer_result_t const event = (p_qtd->condition_code == OHCI_CCODE_NO_ERROR) ? XFER_RESULT_SUCCESS :
|
|
|
- (p_qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
|
|
|
+ ohci_gtd_t * const qtd = (ohci_gtd_t *) td_head;
|
|
|
+ xfer_result_t const event = (qtd->condition_code == OHCI_CCODE_NO_ERROR) ? XFER_RESULT_SUCCESS :
|
|
|
+ (qtd->condition_code == OHCI_CCODE_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_FAILED;
|
|
|
|
|
|
- p_qtd->used = 0; // free TD
|
|
|
- if ( (p_qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
|
|
|
+ qtd->used = 0; // free TD
|
|
|
+ if ( (qtd->delay_interrupt == OHCI_INT_ON_COMPLETE_YES) || (event != XFER_RESULT_SUCCESS) )
|
|
|
{
|
|
|
- ohci_ed_t * const p_ed = gtd_get_ed(p_qtd);
|
|
|
+ ohci_ed_t * const ed = gtd_get_ed(qtd);
|
|
|
|
|
|
- uint32_t const xferred_bytes = p_qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) p_qtd->buffer_end, (uint32_t) p_qtd->current_buffer_pointer);
|
|
|
+ uint32_t const xferred_bytes = qtd->expected_bytes - gtd_xfer_byte_left((uint32_t) qtd->buffer_end, (uint32_t) qtd->current_buffer_pointer);
|
|
|
|
|
|
// NOTE Assuming the current list is BULK and there is no other EDs in the list has queued TDs.
|
|
|
// When there is a error resulting this ED is halted, and this EP still has other queued TD
|
|
|
@@ -616,14 +596,14 @@ static void done_queue_isr(uint8_t hostid)
|
|
|
// the TailP must be set back to NULL for processing remaining TDs
|
|
|
if ((event != XFER_RESULT_SUCCESS))
|
|
|
{
|
|
|
- p_ed->td_tail &= 0x0Ful;
|
|
|
- p_ed->td_tail |= tu_align16(p_ed->td_head.address); // mark halted EP as empty queue
|
|
|
- if ( event == XFER_RESULT_STALLED ) p_ed->is_stalled = 1;
|
|
|
+ ed->td_tail &= 0x0Ful;
|
|
|
+ ed->td_tail |= tu_align16(ed->td_head.address); // mark halted EP as empty queue
|
|
|
+ if ( event == XFER_RESULT_STALLED ) ed->is_stalled = 1;
|
|
|
}
|
|
|
|
|
|
- hcd_event_xfer_complete(p_ed->dev_addr,
|
|
|
- tu_edpt_addr(p_ed->ep_number, p_ed->pid == OHCI_PID_IN),
|
|
|
- xferred_bytes, event, true);
|
|
|
+ uint8_t dir = (ed->ep_number == 0) ? (qtd->pid == PID_IN) : (ed->pid == PID_IN);
|
|
|
+
|
|
|
+ hcd_event_xfer_complete(ed->dev_addr, tu_edpt_addr(ed->ep_number, dir), xferred_bytes, event, true);
|
|
|
}
|
|
|
|
|
|
td_head = (ohci_td_item_t*) td_head->next;
|
|
|
@@ -646,16 +626,16 @@ void hcd_int_handler(uint8_t hostid)
|
|
|
//------------- RootHub status -------------//
|
|
|
if ( int_status & OHCI_INT_RHPORT_STATUS_CHANGE_MASK )
|
|
|
{
|
|
|
- uint32_t const rhport_status = OHCI_REG->rhport_status[0] & OHCI_RHPORT_ALL_CHANGE_MASK;
|
|
|
+ uint32_t const rhport_status = OHCI_REG->rhport_status[0] & RHPORT_ALL_CHANGE_MASK;
|
|
|
|
|
|
// TODO dual port is not yet supported
|
|
|
- if ( rhport_status & OHCI_RHPORT_CONNECT_STATUS_CHANGE_MASK )
|
|
|
+ if ( rhport_status & RHPORT_CONNECT_STATUS_CHANGE_MASK )
|
|
|
{
|
|
|
// TODO check if remote wake-up
|
|
|
if ( OHCI_REG->rhport_status_bit[0].current_connect_status )
|
|
|
{
|
|
|
// TODO reset port immediately, without this controller will got 2-3 (debouncing connection status change)
|
|
|
- OHCI_REG->rhport_status[0] = OHCI_RHPORT_PORT_RESET_STATUS_MASK;
|
|
|
+ OHCI_REG->rhport_status[0] = RHPORT_PORT_RESET_STATUS_MASK;
|
|
|
hcd_event_device_attach(hostid, true);
|
|
|
}else
|
|
|
{
|
|
|
@@ -663,7 +643,7 @@ void hcd_int_handler(uint8_t hostid)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- if ( rhport_status & OHCI_RHPORT_PORT_SUSPEND_CHANGE_MASK)
|
|
|
+ if ( rhport_status & RHPORT_PORT_SUSPEND_CHANGE_MASK)
|
|
|
{
|
|
|
|
|
|
}
|
|
|
@@ -672,7 +652,7 @@ void hcd_int_handler(uint8_t hostid)
|
|
|
}
|
|
|
|
|
|
//------------- Transfer Complete -------------//
|
|
|
- if ( int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK)
|
|
|
+ if (int_status & OHCI_INT_WRITEBACK_DONEHEAD_MASK)
|
|
|
{
|
|
|
done_queue_isr(hostid);
|
|
|
}
|