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@@ -30,13 +30,10 @@
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/**********************************************
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* This driver has been tested with the following MCUs:
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- *
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- *
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- * STM32F070RB
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- *
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+ * - F070, F072, L053
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*
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* It also should work with minimal changes for any ST MCU with an "USB A"/"PCD"/"HCD" peripheral. This
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- * covers:
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+ * covers:
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*
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* F04x, F072, F078, 070x6/B 1024 byte buffer
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* F102, F103 512 byte buffer; no internal D+ pull-up (maybe many more changes?)
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@@ -46,9 +43,13 @@
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* L1 512 byte buffer
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* L4x2, L4x3 1024 byte buffer
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*
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+ * To use this driver, you must:
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+ * - Enable USB clock; Perhaps use __HAL_RCC_USB_CLK_ENABLE();
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+ * - (Optionally configure GPIO HAL to tell it the USB driver is using the USB pins)
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+ * - call tusb_init();
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+ * - periodically call tusb_task();
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+ *
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* Assumptions of the driver:
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- * - dcd_fs_irqHandler() is called by the USB interrupt handler
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- * - USB clock enabled before usb_init() is called; Perhaps use __HAL_RCC_USB_CLK_ENABLE();
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* - You are not using CAN (it must share the packet buffer)
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* - APB clock is >= 10 MHz
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* - On some boards, series resistors are required, but not on others.
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@@ -59,7 +60,6 @@
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* Current driver limitations (i.e., a list of features for you to add):
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* - STALL handled, but not tested.
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* - Does it work? No clue.
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- * - Only tested on F070RB; other models will have an #error during compilation
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* - All EP BTABLE buffers are created as max 64 bytes.
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* - Smaller can be requested, but it has to be an even number.
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* - No isochronous endpoints
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@@ -74,7 +74,7 @@
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* - No DMA
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* - No provision to control the D+ pull-up using GPIO on devices without an internal pull-up.
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* - Minimal error handling
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- * - Perhaps error interrupts sholud be reported to the stack, or cause a device reset?
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+ * - Perhaps error interrupts should be reported to the stack, or cause a device reset?
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* - Assumes a single USB peripheral; I think that no hardware has multiple so this is fine.
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* - Add a callback for enabling/disabling the D+ PU on devices without an internal PU.
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* - F3 models use three separate interrupts. I think we could only use the LP interrupt for
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@@ -103,14 +103,17 @@
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#include "tusb_option.h"
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+#if defined(STM32F102x6) || defined(STM32F102xB) || \
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+ defined(STM32F103x6) || defined(STM32F103xB) || \
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+ defined(STM32F103xE) || defined(STM32F103xG)
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+#define STM32F1_FSDEV
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+#endif
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+
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#if (TUSB_OPT_DEVICE_ENABLED) && ( \
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- ((CFG_TUSB_MCU) == OPT_MCU_STM32F0) || \
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- (((CFG_TUSB_MCU) == OPT_MCU_STM32F1) && ( \
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- defined(stm32f102x6) || defined(stm32f102xb) || \
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- defined(stm32f103x6) || defined(stm32f103xb) || \
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- defined(stm32f103xe) || defined(stm32f103xg) \
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- )) || \
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- ((CFG_TUSB_MCU) == OPT_MCU_STM32F3) \
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+ (CFG_TUSB_MCU == OPT_MCU_STM32F0 ) || \
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+ (CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \
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+ (CFG_TUSB_MCU == OPT_MCU_STM32F3 ) || \
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+ (CFG_TUSB_MCU == OPT_MCU_STM32L0 ) \
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)
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// In order to reduce the dependance on HAL, we undefine this.
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@@ -144,22 +147,12 @@
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* Checks, structs, defines, function definitions, etc.
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*/
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-#if ((MAX_EP_COUNT) > 8)
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-# error Only 8 endpoints supported on the hardware
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-#endif
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-
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-#if (((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))>(PMA_LENGTH))
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-# error BTABLE does not fit in PMA RAM
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-#endif
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+TU_VERIFY_STATIC((MAX_EP_COUNT) <= STFSDEV_EP_COUNT, "Only 8 endpoints supported on the hardware");
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-#if (((DCD_STM32_BTABLE_BASE) % 8) != 0)
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-// per STM32F3 reference manual
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-#error BTABLE must be aligned to 8 bytes
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-#endif
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-
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-// Max size of a USB FS packet is 64...
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-#define MAX_PACKET_SIZE 64
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+TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))<=(PMA_LENGTH),
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+ "BTABLE does not fit in PMA RAM");
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+TU_VERIFY_STATIC(((DCD_STM32_BTABLE_BASE) % 8) == 0, "BTABLE base must be aligned to 8 bytes");
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// One of these for every EP IN & OUT, uses a bit of RAM....
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typedef struct
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@@ -167,24 +160,37 @@ typedef struct
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uint8_t * buffer;
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uint16_t total_len;
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uint16_t queued_len;
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+ uint16_t max_packet_size;
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} xfer_ctl_t;
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-static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
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-#define XFER_CTL_BASE(_epnum, _dir) &xfer_status[_epnum][_dir]
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+static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
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+
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+static inline xfer_ctl_t* xfer_ctl_ptr(uint32_t epnum, uint32_t dir)
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+{
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+ return &xfer_status[epnum][dir];
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+}
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t newDADDR; // Used to set the new device address during the CTR IRQ handler
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+static uint8_t remoteWakeCountdown; // When wake is requested
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// EP Buffers assigned from end of memory location, to minimize their chance of crashing
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// into the stack.
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static uint16_t ep_buf_ptr;
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static void dcd_handle_bus_reset(void);
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-static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
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-static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
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+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
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+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
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static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
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static uint16_t dcd_ep_ctr_handler(void);
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+
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+// Using a function due to better type checks
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+// This seems better than having to do type casts everywhere else
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+static inline void reg16_clear_bits(__IO uint16_t *reg, uint16_t mask) {
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+ *reg = (uint16_t)(*reg & ~mask);
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+}
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+
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void dcd_init (uint8_t rhport)
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{
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(void)rhport;
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@@ -204,7 +210,7 @@ void dcd_init (uint8_t rhport)
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{
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asm("NOP");
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}
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- USB->CNTR &= ~(USB_CNTR_PDWN);// Remove powerdown
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+ reg16_clear_bits(&USB->CNTR, USB_CNTR_PDWN);// Remove powerdown
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// Wait startup time, for F042 and F070, this is <= 1 us.
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for(uint32_t i = 0; i<200; i++) // should be a few us
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{
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@@ -214,21 +220,22 @@ void dcd_init (uint8_t rhport)
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USB->BTABLE = DCD_STM32_BTABLE_BASE;
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- USB->ISTR &= ~(USB_ISTR_ALL_EVENTS); // Clear pending interrupts
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+ reg16_clear_bits(&USB->ISTR, USB_ISTR_ALL_EVENTS); // Clear pending interrupts
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- // Clear all EPREG
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- for(uint16_t i=0; i<8; i++)
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+ // Reset endpoints to disabled
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+ for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
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{
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- EPREG(0) = 0u;
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+ // This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
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+ pcd_set_endpoint(USB,i,0u);
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}
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// Initialize the BTABLE for EP0 at this point (though setting up the EP0R is unneeded)
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// This is actually not necessary, but helps debugging to start with a blank RAM area
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- for(uint16_t i=0;i<(DCD_STM32_BTABLE_LENGTH>>1); i++)
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+ for(uint32_t i=0;i<(DCD_STM32_BTABLE_LENGTH>>1); i++)
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{
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pma[PMA_STRIDE*(DCD_STM32_BTABLE_BASE + i)] = 0u;
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}
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- USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
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+ USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
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dcd_handle_bus_reset();
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// And finally enable pull-up, which may trigger the RESET IRQ if the host is connected.
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@@ -245,16 +252,21 @@ void dcd_init (uint8_t rhport)
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void dcd_int_enable (uint8_t rhport)
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{
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(void)rhport;
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-#if defined(STM32F0)
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- NVIC_SetPriority(USB_IRQn, 0);
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+ // Member here forces write to RAM before allowing ISR to execute
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+ __DSB();
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+ __ISB();
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+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
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NVIC_EnableIRQ(USB_IRQn);
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-#elif defined(STM32F3)
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- NVIC_SetPriority(USB_HP_CAN_TX_IRQn, 0);
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- NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0);
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- NVIC_SetPriority(USBWakeUp_IRQn, 0);
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+#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
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NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
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NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
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NVIC_EnableIRQ(USBWakeUp_IRQn);
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+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
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+ NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn);
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+ NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
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+ NVIC_EnableIRQ(USBWakeUp_IRQn);
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+#else
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+ #error Unknown arch in USB driver
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#endif
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}
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@@ -262,15 +274,22 @@ void dcd_int_enable (uint8_t rhport)
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void dcd_int_disable(uint8_t rhport)
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{
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(void)rhport;
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-#if defined(STM32F0)
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+
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+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
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NVIC_DisableIRQ(USB_IRQn);
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-#elif defined(STM32F3)
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+#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
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NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
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NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
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NVIC_DisableIRQ(USBWakeUp_IRQn);
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+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
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+ NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);
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+ NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);
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+ NVIC_DisableIRQ(USBWakeUp_IRQn);
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#else
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-#error Unknown arch in USB driver
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+ #error Unknown arch in USB driver
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#endif
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+
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+ // CMSIS has a membar after disabling interrupts
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}
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// Receive Set Address request, mcu port must also include status IN response
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@@ -297,6 +316,9 @@ void dcd_set_config (uint8_t rhport, uint8_t config_num)
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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+
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+ USB->CNTR |= (uint16_t) USB_CNTR_RESUME;
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+ remoteWakeCountdown = 4u; // required to be 1 to 15 ms, ESOF should trigger every 1ms.
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}
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// I'm getting a weird warning about missing braces here that I don't
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@@ -319,7 +341,9 @@ static const tusb_desc_endpoint_t ep0IN_desc =
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.bEndpointAddress = 0x80
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};
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+#if defined(__GNUC__) && (__GNUC__ >= 7)
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#pragma GCC diagnostic pop
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+#endif
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static void dcd_handle_bus_reset(void)
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{
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@@ -327,23 +351,22 @@ static void dcd_handle_bus_reset(void)
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USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
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// Clear all EPREG (or maybe this is automatic? I'm not sure)
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- for(uint16_t i=0; i<8; i++)
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+ for(uint32_t i=0; i<STFSDEV_EP_COUNT; i++)
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{
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- EPREG(0) = 0u;
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+ pcd_set_endpoint(USB,i,0u);
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}
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ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
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dcd_edpt_open (0, &ep0OUT_desc);
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dcd_edpt_open (0, &ep0IN_desc);
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- newDADDR = 0;
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+ newDADDR = 0u;
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USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
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- PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID); // And start accepting SETUP on EP0
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}
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// FIXME: Defined to return uint16 so that ASSERT can be used, even though a return value is not needed.
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static uint16_t dcd_ep_ctr_handler(void)
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{
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- uint16_t count=0U;
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+ uint32_t count=0U;
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uint8_t EPindex;
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__IO uint16_t wIstr;
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__IO uint16_t wEPVal = 0U;
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@@ -365,9 +388,9 @@ static uint16_t dcd_ep_ctr_handler(void)
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{
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/* DIR = 0 => IN int */
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/* DIR = 0 implies that (EP_CTR_TX = 1) always */
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- PCD_CLEAR_TX_EP_CTR(USB, 0);
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+ pcd_clear_tx_ep_ctr(USB, 0);
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- xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
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+ xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
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if((xfer->total_len == xfer->queued_len))
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{
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@@ -375,13 +398,13 @@ static uint16_t dcd_ep_ctr_handler(void)
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if((newDADDR != 0) && ( xfer->total_len == 0U))
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{
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// Delayed setting of the DADDR after the 0-len DATA packet acking the request is sent.
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- USB->DADDR &= ~USB_DADDR_ADD;
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- USB->DADDR |= newDADDR;
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+ reg16_clear_bits(&USB->DADDR, USB_DADDR_ADD);
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+ USB->DADDR = (uint16_t)(USB->DADDR | newDADDR); // leave the enable bit set
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newDADDR = 0;
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}
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if(xfer->total_len == 0) // Probably a status message?
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{
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- PCD_CLEAR_RX_DTOG(USB,EPindex);
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+ pcd_clear_rx_dtog(USB,EPindex);
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}
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}
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else
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@@ -394,10 +417,10 @@ static uint16_t dcd_ep_ctr_handler(void)
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/* DIR = 1 & CTR_RX => SETUP or OUT int */
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/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
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- xfer_ctl_t *xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
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+ xfer_ctl_t *xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
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//ep = &hpcd->OUT_ep[0];
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- wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
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+ wEPVal = pcd_get_endpoint(USB, EPindex);
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if ((wEPVal & USB_EP_SETUP) != 0U) // SETUP
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{
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@@ -405,69 +428,67 @@ static uint16_t dcd_ep_ctr_handler(void)
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// user memory, to allow for the 32-bit access that memcpy performs.
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uint8_t userMemBuf[8];
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/* Get SETUP Packet*/
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- count = PCD_GET_EP_RX_CNT(USB, EPindex);
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- //TU_ASSERT_ERR(count == 8);
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- dcd_read_packet_memory(userMemBuf, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), 8);
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+ count = pcd_get_ep_rx_cnt(USB, EPindex);
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+ if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
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+ {
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+ // Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
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+ pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
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+ pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
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+ dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
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+ dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
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+ }
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/* SETUP bit kept frozen while CTR_RX = 1*/
|
|
|
- dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
|
|
|
- PCD_CLEAR_RX_EP_CTR(USB, EPindex);
|
|
|
+ pcd_clear_rx_ep_ctr(USB, EPindex);
|
|
|
}
|
|
|
else if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
|
|
|
{
|
|
|
|
|
|
- PCD_CLEAR_RX_EP_CTR(USB, EPindex);
|
|
|
+ pcd_clear_rx_ep_ctr(USB, EPindex);
|
|
|
|
|
|
/* Get Control Data OUT Packet */
|
|
|
- count = PCD_GET_EP_RX_CNT(USB,EPindex);
|
|
|
+ count = pcd_get_ep_rx_cnt(USB,EPindex);
|
|
|
|
|
|
if (count != 0U)
|
|
|
{
|
|
|
- dcd_read_packet_memory(xfer->buffer, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
|
|
|
+ dcd_read_packet_memory(xfer->buffer, *pcd_ep_rx_address_ptr(USB,EPindex), count);
|
|
|
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
|
|
|
}
|
|
|
|
|
|
/* Process Control Data OUT status Packet*/
|
|
|
- if(EPindex == 0 && xfer->total_len == 0)
|
|
|
- {
|
|
|
- PCD_CLEAR_EP_KIND(USB,0); // Good, so allow non-zero length packets now.
|
|
|
- }
|
|
|
dcd_event_xfer_complete(0, EPindex, xfer->total_len, XFER_RESULT_SUCCESS, true);
|
|
|
|
|
|
- PCD_SET_EP_RX_CNT(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
|
|
|
- if(EPindex == 0 && xfer->total_len == 0)
|
|
|
+ pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
|
|
|
+ if(EPindex == 0u && xfer->total_len == 0u)
|
|
|
{
|
|
|
- PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
|
|
|
+ pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
|
|
|
}
|
|
|
-
|
|
|
}
|
|
|
-
|
|
|
}
|
|
|
}
|
|
|
else /* Decode and service non control endpoints interrupt */
|
|
|
{
|
|
|
-
|
|
|
/* process related endpoint register */
|
|
|
- wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
|
|
|
+ wEPVal = pcd_get_endpoint(USB, EPindex);
|
|
|
if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
|
|
|
{
|
|
|
/* clear int flag */
|
|
|
- PCD_CLEAR_RX_EP_CTR(USB, EPindex);
|
|
|
+ pcd_clear_rx_ep_ctr(USB, EPindex);
|
|
|
|
|
|
- xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
|
|
|
+ xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_OUT);
|
|
|
|
|
|
//ep = &hpcd->OUT_ep[EPindex];
|
|
|
|
|
|
- count = PCD_GET_EP_RX_CNT(USB, EPindex);
|
|
|
+ count = pcd_get_ep_rx_cnt(USB, EPindex);
|
|
|
if (count != 0U)
|
|
|
{
|
|
|
dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]),
|
|
|
- *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
|
|
|
+ *pcd_ep_rx_address_ptr(USB,EPindex), count);
|
|
|
}
|
|
|
|
|
|
/*multi-packet on the NON control OUT endpoint */
|
|
|
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
|
|
|
|
|
|
- if ((count < 64) || (xfer->queued_len == xfer->total_len))
|
|
|
+ if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
|
|
|
{
|
|
|
/* RX COMPLETE */
|
|
|
dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true);
|
|
|
@@ -476,14 +497,14 @@ static uint16_t dcd_ep_ctr_handler(void)
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
- uint16_t remaining = (uint16_t)(xfer->total_len - xfer->queued_len);
|
|
|
- if(remaining >=64) {
|
|
|
- PCD_SET_EP_RX_CNT(USB, EPindex,64);
|
|
|
+ uint32_t remaining = (uint32_t)xfer->total_len - (uint32_t)xfer->queued_len;
|
|
|
+ if(remaining >= xfer->max_packet_size) {
|
|
|
+ pcd_set_ep_rx_cnt(USB, EPindex,xfer->max_packet_size);
|
|
|
} else {
|
|
|
- PCD_SET_EP_RX_CNT(USB, EPindex,remaining);
|
|
|
+ pcd_set_ep_rx_cnt(USB, EPindex,remaining);
|
|
|
}
|
|
|
|
|
|
- PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);
|
|
|
+ pcd_set_ep_rx_status(USB, EPindex, USB_EP_RX_VALID);
|
|
|
}
|
|
|
|
|
|
} /* if((wEPVal & EP_CTR_RX) */
|
|
|
@@ -491,9 +512,9 @@ static uint16_t dcd_ep_ctr_handler(void)
|
|
|
if ((wEPVal & USB_EP_CTR_TX) != 0U) // IN
|
|
|
{
|
|
|
/* clear int flag */
|
|
|
- PCD_CLEAR_TX_EP_CTR(USB, EPindex);
|
|
|
+ pcd_clear_tx_ep_ctr(USB, EPindex);
|
|
|
|
|
|
- xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
|
|
|
+ xfer_ctl_t * xfer = xfer_ctl_ptr(EPindex,TUSB_DIR_IN);
|
|
|
|
|
|
if (xfer->queued_len != xfer->total_len) // data remaining in transfer?
|
|
|
{
|
|
|
@@ -507,46 +528,71 @@ static uint16_t dcd_ep_ctr_handler(void)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-void dcd_fs_irqHandler(void) {
|
|
|
+static void dcd_fs_irqHandler(void) {
|
|
|
+
|
|
|
+ uint32_t int_status = USB->ISTR;
|
|
|
+ //const uint32_t handled_ints = USB_ISTR_CTR | USB_ISTR_RESET | USB_ISTR_WKUP
|
|
|
+ // | USB_ISTR_SUSP | USB_ISTR_SOF | USB_ISTR_ESOF;
|
|
|
+ // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_L1REQ )
|
|
|
|
|
|
- uint16_t int_status = USB->ISTR;
|
|
|
- // unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | USB_ISTR_ESOF | USB_ISTR_L1REQ )
|
|
|
+ // The ST driver loops here on the CTR bit, but that loop has been moved into the
|
|
|
+ // dcd_ep_ctr_handler(), so less need to loop here. The other interrupts shouldn't
|
|
|
+ // be triggered repeatedly.
|
|
|
+
|
|
|
+ if(int_status & USB_ISTR_RESET) {
|
|
|
+ // USBRST is start of reset.
|
|
|
+ reg16_clear_bits(&USB->ISTR, USB_ISTR_RESET);
|
|
|
+ dcd_handle_bus_reset();
|
|
|
+ dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
|
|
+ return; // Don't do the rest of the things here; perhaps they've been cleared?
|
|
|
+ }
|
|
|
|
|
|
if (int_status & USB_ISTR_CTR)
|
|
|
{
|
|
|
/* servicing of the endpoint correct transfer interrupt */
|
|
|
/* clear of the CTR flag into the sub */
|
|
|
dcd_ep_ctr_handler();
|
|
|
- USB->ISTR &= ~USB_ISTR_CTR;
|
|
|
- }
|
|
|
- if(int_status & USB_ISTR_RESET) {
|
|
|
- // USBRST is start of reset.
|
|
|
- USB->ISTR &= ~USB_ISTR_RESET;
|
|
|
- dcd_handle_bus_reset();
|
|
|
- dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
|
|
|
+ reg16_clear_bits(&USB->ISTR, USB_ISTR_CTR);
|
|
|
}
|
|
|
+
|
|
|
if (int_status & USB_ISTR_WKUP)
|
|
|
{
|
|
|
-
|
|
|
- USB->CNTR &= ~USB_CNTR_LPMODE;
|
|
|
- USB->CNTR &= ~USB_CNTR_FSUSP;
|
|
|
- USB->ISTR &= ~USB_ISTR_WKUP;
|
|
|
+ reg16_clear_bits(&USB->CNTR, USB_CNTR_LPMODE);
|
|
|
+ reg16_clear_bits(&USB->CNTR, USB_CNTR_FSUSP);
|
|
|
+ reg16_clear_bits(&USB->ISTR, USB_ISTR_WKUP);
|
|
|
+ dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
|
|
|
}
|
|
|
|
|
|
if (int_status & USB_ISTR_SUSP)
|
|
|
{
|
|
|
+ /* Suspend is asserted for both suspend and unplug events. without Vbus monitoring,
|
|
|
+ * these events cannot be differentiated, so we only trigger suspend. */
|
|
|
+
|
|
|
/* Force low-power mode in the macrocell */
|
|
|
USB->CNTR |= USB_CNTR_FSUSP;
|
|
|
USB->CNTR |= USB_CNTR_LPMODE;
|
|
|
|
|
|
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
|
|
|
- USB->ISTR &= ~USB_ISTR_SUSP;
|
|
|
+ reg16_clear_bits(&USB->ISTR, USB_ISTR_SUSP);
|
|
|
+ dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
|
|
|
}
|
|
|
|
|
|
if(int_status & USB_ISTR_SOF) {
|
|
|
- USB->ISTR &= ~USB_ISTR_SOF;
|
|
|
+ reg16_clear_bits(&USB->ISTR, USB_ISTR_SOF);
|
|
|
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
|
|
|
}
|
|
|
+
|
|
|
+ if(int_status & USB_ISTR_ESOF) {
|
|
|
+ if(remoteWakeCountdown == 1u)
|
|
|
+ {
|
|
|
+ USB->CNTR &= (uint16_t)(~USB_CNTR_RESUME);
|
|
|
+ }
|
|
|
+ if(remoteWakeCountdown > 0u)
|
|
|
+ {
|
|
|
+ remoteWakeCountdown--;
|
|
|
+ }
|
|
|
+ reg16_clear_bits(&USB->ISTR, USB_ISTR_ESOF);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
@@ -561,47 +607,57 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
|
|
|
(void)rhport;
|
|
|
uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
|
|
|
uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
|
|
|
-
|
|
|
+ const uint16_t epMaxPktSize = p_endpoint_desc->wMaxPacketSize.size;
|
|
|
// Isochronous not supported (yet), and some other driver assumptions.
|
|
|
+
|
|
|
TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
|
|
|
- TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= MAX_PACKET_SIZE);
|
|
|
TU_ASSERT(epnum < MAX_EP_COUNT);
|
|
|
- TU_ASSERT((p_endpoint_desc->wMaxPacketSize.size %2) == 0);
|
|
|
-
|
|
|
- // __IO uint16_t * const epreg = &(EPREG(epnum));
|
|
|
|
|
|
// Set type
|
|
|
switch(p_endpoint_desc->bmAttributes.xfer) {
|
|
|
case TUSB_XFER_CONTROL:
|
|
|
- PCD_SET_EPTYPE(USB, epnum, USB_EP_CONTROL); break;
|
|
|
- case TUSB_XFER_ISOCHRONOUS:
|
|
|
- PCD_SET_EPTYPE(USB, epnum, USB_EP_ISOCHRONOUS); break;
|
|
|
+ pcd_set_eptype(USB, epnum, USB_EP_CONTROL);
|
|
|
+ break;
|
|
|
+#if (0)
|
|
|
+ case TUSB_XFER_ISOCHRONOUS: // FIXME: Not yet supported
|
|
|
+ pcd_set_eptype(USB, epnum, USB_EP_ISOCHRONOUS); break;
|
|
|
+ break;
|
|
|
+#endif
|
|
|
+
|
|
|
case TUSB_XFER_BULK:
|
|
|
- PCD_SET_EPTYPE(USB, epnum, USB_EP_BULK); break;
|
|
|
+ pcd_set_eptype(USB, epnum, USB_EP_BULK);
|
|
|
+ break;
|
|
|
+
|
|
|
case TUSB_XFER_INTERRUPT:
|
|
|
- PCD_SET_EPTYPE(USB, epnum, USB_EP_INTERRUPT); break;
|
|
|
+ pcd_set_eptype(USB, epnum, USB_EP_INTERRUPT);
|
|
|
+ break;
|
|
|
+
|
|
|
default:
|
|
|
TU_ASSERT(false);
|
|
|
+ return false;
|
|
|
}
|
|
|
|
|
|
- PCD_SET_EP_ADDRESS(USB, epnum, epnum);
|
|
|
- PCD_CLEAR_EP_KIND(USB,0); // Be normal, for now, instead of only accepting zero-byte packets
|
|
|
+ pcd_set_ep_address(USB, epnum, epnum);
|
|
|
+ // Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
|
|
|
+ // or being double-buffered (bulk endpoints)
|
|
|
+ pcd_clear_ep_kind(USB,0);
|
|
|
|
|
|
if(dir == TUSB_DIR_IN)
|
|
|
{
|
|
|
- *PCD_EP_TX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
|
|
|
- PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
|
|
- PCD_CLEAR_TX_DTOG(USB, epnum);
|
|
|
- PCD_SET_EP_TX_STATUS(USB,epnum,USB_EP_TX_NAK);
|
|
|
+ *pcd_ep_tx_address_ptr(USB, epnum) = ep_buf_ptr;
|
|
|
+ pcd_set_ep_tx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
|
|
+ pcd_clear_tx_dtog(USB, epnum);
|
|
|
+ pcd_set_ep_tx_status(USB,epnum,USB_EP_TX_NAK);
|
|
|
}
|
|
|
else
|
|
|
{
|
|
|
- *PCD_EP_RX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
|
|
|
- PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
|
|
- PCD_CLEAR_RX_DTOG(USB, epnum);
|
|
|
- PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_NAK);
|
|
|
+ *pcd_ep_rx_address_ptr(USB, epnum) = ep_buf_ptr;
|
|
|
+ pcd_set_ep_rx_cnt(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
|
|
|
+ pcd_clear_rx_dtog(USB, epnum);
|
|
|
+ pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_NAK);
|
|
|
}
|
|
|
|
|
|
+ xfer_ctl_ptr(epnum, dir)->max_packet_size = epMaxPktSize;
|
|
|
ep_buf_ptr = (uint16_t)(ep_buf_ptr + p_endpoint_desc->wMaxPacketSize.size); // increment buffer pointer
|
|
|
|
|
|
return true;
|
|
|
@@ -613,15 +669,16 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
|
|
|
{
|
|
|
uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
|
|
|
|
|
|
- if(len > 64u) // max packet size for FS transfer
|
|
|
+ if(len > xfer->max_packet_size) // max packet size for FS transfer
|
|
|
{
|
|
|
- len = 64u;
|
|
|
+ len = xfer->max_packet_size;
|
|
|
}
|
|
|
- dcd_write_packet_memory(*PCD_EP_TX_ADDRESS_PTR(USB,ep_ix), &(xfer->buffer[xfer->queued_len]), len);
|
|
|
+ uint16_t oldAddr = *pcd_ep_tx_address_ptr(USB,ep_ix);
|
|
|
+ dcd_write_packet_memory(oldAddr, &(xfer->buffer[xfer->queued_len]), len);
|
|
|
xfer->queued_len = (uint16_t)(xfer->queued_len + len);
|
|
|
|
|
|
- PCD_SET_EP_TX_CNT(USB,ep_ix,len);
|
|
|
- PCD_SET_EP_TX_STATUS(USB, ep_ix, USB_EP_TX_VALID);
|
|
|
+ pcd_set_ep_tx_cnt(USB,ep_ix,len);
|
|
|
+ pcd_set_ep_tx_status(USB, ep_ix, USB_EP_TX_VALID);
|
|
|
}
|
|
|
|
|
|
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
|
|
|
@@ -631,7 +688,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
|
|
uint8_t const epnum = tu_edpt_number(ep_addr);
|
|
|
uint8_t const dir = tu_edpt_dir(ep_addr);
|
|
|
|
|
|
- xfer_ctl_t * xfer = XFER_CTL_BASE(epnum,dir);
|
|
|
+ xfer_ctl_t * xfer = xfer_ctl_ptr(epnum,dir);
|
|
|
|
|
|
xfer->buffer = buffer;
|
|
|
xfer->total_len = total_bytes;
|
|
|
@@ -644,15 +701,14 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
|
|
|
if (epnum == 0 && buffer == NULL)
|
|
|
{
|
|
|
xfer->buffer = (uint8_t*)_setup_packet;
|
|
|
- PCD_SET_EP_KIND(USB,0); // Expect a zero-byte INPUT
|
|
|
}
|
|
|
- if(total_bytes > 64)
|
|
|
+ if(total_bytes > xfer->max_packet_size)
|
|
|
{
|
|
|
- PCD_SET_EP_RX_CNT(USB,epnum,64);
|
|
|
+ pcd_set_ep_rx_cnt(USB,epnum,xfer->max_packet_size);
|
|
|
} else {
|
|
|
- PCD_SET_EP_RX_CNT(USB,epnum,total_bytes);
|
|
|
+ pcd_set_ep_rx_cnt(USB,epnum,total_bytes);
|
|
|
}
|
|
|
- PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_VALID);
|
|
|
+ pcd_set_ep_rx_status(USB, epnum, USB_EP_RX_VALID);
|
|
|
}
|
|
|
else // IN
|
|
|
{
|
|
|
@@ -665,41 +721,35 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
|
|
|
{
|
|
|
(void)rhport;
|
|
|
|
|
|
- if (ep_addr == 0) { // CTRL EP0 (OUT for setup)
|
|
|
- PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
|
|
|
+ if (ep_addr & 0x80)
|
|
|
+ { // IN
|
|
|
+ pcd_set_ep_tx_status(USB, ep_addr & 0x7F, USB_EP_TX_STALL);
|
|
|
}
|
|
|
-
|
|
|
- if (ep_addr & 0x80) { // IN
|
|
|
- ep_addr &= 0x7F;
|
|
|
- PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
|
|
|
- } else { // OUT
|
|
|
- PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_STALL);
|
|
|
+ else
|
|
|
+ { // OUT
|
|
|
+ pcd_set_ep_rx_status(USB, ep_addr, USB_EP_RX_STALL);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
|
|
{
|
|
|
(void)rhport;
|
|
|
- if (ep_addr == 0)
|
|
|
- {
|
|
|
- PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
|
|
|
- }
|
|
|
|
|
|
if (ep_addr & 0x80)
|
|
|
{ // IN
|
|
|
ep_addr &= 0x7F;
|
|
|
|
|
|
- PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
|
|
|
+ pcd_set_ep_tx_status(USB,ep_addr, USB_EP_TX_NAK);
|
|
|
|
|
|
/* Reset to DATA0 if clearing stall condition. */
|
|
|
- PCD_CLEAR_TX_DTOG(USB,ep_addr);
|
|
|
+ pcd_clear_tx_dtog(USB,ep_addr);
|
|
|
}
|
|
|
else
|
|
|
{ // OUT
|
|
|
/* Reset to DATA0 if clearing stall condition. */
|
|
|
- PCD_CLEAR_RX_DTOG(USB,ep_addr);
|
|
|
+ pcd_clear_rx_dtog(USB,ep_addr);
|
|
|
|
|
|
- PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_VALID);
|
|
|
+ pcd_set_ep_rx_status(USB,ep_addr, USB_EP_RX_NAK);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
@@ -714,19 +764,13 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
|
|
|
* @param wNBytes no. of bytes to be copied.
|
|
|
* @retval None
|
|
|
*/
|
|
|
-static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
|
|
|
+static bool dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
|
|
|
{
|
|
|
- uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
|
|
|
+ uint32_t n = ((uint32_t)wNBytes + 1U) >> 1U;
|
|
|
uint32_t i;
|
|
|
uint16_t temp1, temp2;
|
|
|
const uint8_t * srcVal;
|
|
|
|
|
|
-#ifdef DEBUG
|
|
|
- if(((dst%2) != 0) ||
|
|
|
- (dst < DCD_STM32_BTABLE_BASE) ||
|
|
|
- dst >= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH))
|
|
|
- while(1) TU_BREAKPOINT();
|
|
|
-#endif
|
|
|
// The GCC optimizer will combine access to 32-bit sizes if we let it. Force
|
|
|
// it volatile so that it won't do that.
|
|
|
__IO uint16_t *pdwVal;
|
|
|
@@ -743,6 +787,7 @@ static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
|
|
|
pdwVal += PMA_STRIDE;
|
|
|
srcVal++;
|
|
|
}
|
|
|
+ return true;
|
|
|
}
|
|
|
|
|
|
/**
|
|
|
@@ -751,7 +796,7 @@ static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, si
|
|
|
* @param wNBytes no. of bytes to be copied.
|
|
|
* @retval None
|
|
|
*/
|
|
|
-static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
|
|
|
+static bool dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
|
|
|
{
|
|
|
uint32_t n = (uint32_t)wNBytes >> 1U;
|
|
|
uint32_t i;
|
|
|
@@ -760,13 +805,6 @@ static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
|
|
|
__IO const uint16_t *pdwVal;
|
|
|
uint32_t temp;
|
|
|
|
|
|
-#ifdef DEBUG
|
|
|
- if((src%2) != 0 ||
|
|
|
- (src < DCD_STM32_BTABLE_BASE) ||
|
|
|
- src >= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH))
|
|
|
- while(1) TU_BREAKPOINT();
|
|
|
-#endif
|
|
|
-
|
|
|
pdwVal = &pma[PMA_STRIDE*(src>>1)];
|
|
|
uint8_t *dstVal = (uint8_t*)dst;
|
|
|
|
|
|
@@ -784,17 +822,18 @@ static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wN
|
|
|
pdwVal += PMA_STRIDE;
|
|
|
*dstVal++ = ((temp >> 0) & 0xFF);
|
|
|
}
|
|
|
+ return true;
|
|
|
}
|
|
|
|
|
|
|
|
|
// Interrupt handlers
|
|
|
-#if (CFG_TUSB_MCU) == (OPT_MCU_STM32F0)
|
|
|
+#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
|
|
|
void USB_IRQHandler(void)
|
|
|
{
|
|
|
dcd_fs_irqHandler();
|
|
|
}
|
|
|
|
|
|
-#elif (CFG_TUSB_MCU) == (OPT_MCU_STM32F1)
|
|
|
+#elif CFG_TUSB_MCU == OPT_MCU_STM32F1
|
|
|
void USB_HP_IRQHandler(void)
|
|
|
{
|
|
|
dcd_fs_irqHandler();
|
|
|
@@ -826,14 +865,16 @@ void USB_LP_CAN_RX0_IRQHandler(void)
|
|
|
{
|
|
|
dcd_fs_irqHandler();
|
|
|
}
|
|
|
+
|
|
|
// USB wakeup interrupt (Channel 42): Triggered by the wakeup event from the USB
|
|
|
// Suspend mode.
|
|
|
void USBWakeUp_IRQHandler(void)
|
|
|
{
|
|
|
dcd_fs_irqHandler();
|
|
|
}
|
|
|
+
|
|
|
#else
|
|
|
-#error Which IRQ handler do you need?
|
|
|
+ #error Which IRQ handler do you need?
|
|
|
#endif
|
|
|
|
|
|
#endif
|