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@@ -85,25 +85,25 @@ static dcd_data_t* const dcd_data_ptr[2] = { &dcd_data0, &dcd_data1 };
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//--------------------------------------------------------------------+
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// CONTROLLER API
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//--------------------------------------------------------------------+
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-void tusb_dcd_connect(uint8_t port)
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+void tusb_dcd_connect(uint8_t rhport)
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{
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- LPC_USB[port]->USBCMD_D |= BIT_(0);
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+ LPC_USB[rhport]->USBCMD_D |= BIT_(0);
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}
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-void tusb_dcd_set_address(uint8_t port, uint8_t dev_addr)
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+void tusb_dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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- LPC_USB[port]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
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+ LPC_USB[rhport]->DEVICEADDR = (dev_addr << 25) | BIT_(24);
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}
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-void tusb_dcd_set_config(uint8_t port, uint8_t config_num)
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+void tusb_dcd_set_config(uint8_t rhport, uint8_t config_num)
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{
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}
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/// follows LPC43xx User Manual 23.10.3
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-static void bus_reset(uint8_t port)
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+static void bus_reset(uint8_t rhport)
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{
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- LPC_USB0_Type* const lpc_usb = LPC_USB[port];
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+ LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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// The reset value for all endpoint types is the control endpoint. If one endpoint
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//direction is enabled and the paired endpoint of opposite direction is disabled, then the
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@@ -114,7 +114,7 @@ static void bus_reset(uint8_t port)
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(TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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// USB1 only has 3 non-control endpoints
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- if ( port == 0)
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+ if ( rhport == 0)
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{
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lpc_usb->ENDPTCTRL4 = lpc_usb->ENDPTCTRL5 = (TUSB_XFER_BULK << 2) | (TUSB_XFER_BULK << 18);
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}
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@@ -133,7 +133,7 @@ static void bus_reset(uint8_t port)
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// read reset bit in portsc
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//------------- Queue Head & Queue TD -------------//
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- dcd_data_t* p_dcd = dcd_data_ptr[port];
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+ dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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memclr_(p_dcd, sizeof(dcd_data_t));
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@@ -146,10 +146,10 @@ static void bus_reset(uint8_t port)
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}
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-bool tusb_dcd_init(uint8_t port)
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+bool tusb_dcd_init(uint8_t rhport)
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{
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- LPC_USB0_Type* const lpc_usb = LPC_USB[port];
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- dcd_data_t* p_dcd = dcd_data_ptr[port];
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+ LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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+ dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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memclr_(p_dcd, sizeof(dcd_data_t));
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@@ -161,7 +161,7 @@ bool tusb_dcd_init(uint8_t port)
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lpc_usb->USBCMD_D |= BIT_(0); // connect
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// enable interrupt
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- NVIC_EnableIRQ(port ? USB1_IRQn : USB0_IRQn);
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+ NVIC_EnableIRQ(rhport ? USB1_IRQn : USB0_IRQn);
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return true;
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}
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@@ -217,12 +217,12 @@ static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes)
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}
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// retval 0: invalid
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-static inline uint8_t qtd_find_free(uint8_t port)
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+static inline uint8_t qtd_find_free(uint8_t rhport)
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{
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// QTD0 is reserved for control transfer
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for(uint8_t i=1; i<DCD_QTD_MAX; i++)
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{
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- if ( dcd_data_ptr[port]->qtd[i].used == 0) return i;
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+ if ( dcd_data_ptr[rhport]->qtd[i].used == 0) return i;
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}
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return 0;
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@@ -234,10 +234,10 @@ static inline uint8_t qtd_find_free(uint8_t port)
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// control transfer does not need to use qtd find function
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// follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism
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-bool tusb_dcd_control_xfer(uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length)
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+bool tusb_dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16_t length)
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{
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- LPC_USB0_Type* const lpc_usb = LPC_USB[port];
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- dcd_data_t* const p_dcd = dcd_data_ptr[port];
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+ LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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+ dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
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uint8_t const ep_phy = (dir == TUSB_DIR_IN) ? 1 : 0;
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@@ -264,15 +264,15 @@ bool tusb_dcd_control_xfer(uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uin
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//--------------------------------------------------------------------+
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// BULK/INTERRUPT/ISOCHRONOUS PIPE API
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//--------------------------------------------------------------------+
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-static inline volatile uint32_t * get_reg_control_addr(uint8_t port, uint8_t physical_endpoint)
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+static inline volatile uint32_t * get_reg_control_addr(uint8_t rhport, uint8_t physical_endpoint)
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{
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- return &(LPC_USB[port]->ENDPTCTRL0) + edpt_phy2log(physical_endpoint);
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+ return &(LPC_USB[rhport]->ENDPTCTRL0) + edpt_phy2log(physical_endpoint);
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}
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-void tusb_dcd_edpt_stall(uint8_t port, uint8_t ep_addr)
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+void tusb_dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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- volatile uint32_t * reg_control = get_reg_control_addr(port, ep_idx);
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+ volatile uint32_t * reg_control = get_reg_control_addr(rhport, ep_idx);
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if ( ep_addr == 0)
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{
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@@ -284,16 +284,16 @@ void tusb_dcd_edpt_stall(uint8_t port, uint8_t ep_addr)
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}
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}
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-void tusb_dcd_edpt_clear_stall(uint8_t port, uint8_t ep_addr)
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+void tusb_dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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- volatile uint32_t * reg_control = get_reg_control_addr(port, edpt_addr2phy(ep_addr));
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+ volatile uint32_t * reg_control = get_reg_control_addr(rhport, edpt_addr2phy(ep_addr));
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// data toggle also need to be reset
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(*reg_control) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0);
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(*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((ep_addr & TUSB_DIR_IN_MASK) ? 16 : 0));
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}
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-bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc)
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+bool tusb_dcd_edpt_open(uint8_t rhport, tusb_descriptor_endpoint_t const * p_endpoint_desc)
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{
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// TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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// TODO not support ISO yet
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@@ -303,7 +303,7 @@ bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpo
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//------------- Prepare Queue Head -------------//
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uint8_t ep_idx = edpt_addr2phy(p_endpoint_desc->bEndpointAddress);
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- dcd_qhd_t * p_qhd = &dcd_data_ptr[port]->qhd[ep_idx];
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+ dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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memclr_(p_qhd, sizeof(dcd_qhd_t));
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@@ -312,7 +312,7 @@ bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpo
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p_qhd->qtd_overlay.next = QTD_NEXT_INVALID;
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//------------- Endpoint Control Register -------------//
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- volatile uint32_t * reg_control = get_reg_control_addr(port, ep_idx);
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+ volatile uint32_t * reg_control = get_reg_control_addr(rhport, ep_idx);
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// endpoint must not be already enabled
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VERIFY( !( (*reg_control) & (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
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@@ -322,10 +322,10 @@ bool tusb_dcd_edpt_open(uint8_t port, tusb_descriptor_endpoint_t const * p_endpo
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return true;
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}
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-bool tusb_dcd_edpt_busy(uint8_t port, uint8_t ep_addr)
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+bool tusb_dcd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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- dcd_qhd_t const * p_qhd = &dcd_data_ptr[port]->qhd[ep_idx];
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+ dcd_qhd_t const * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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return p_qhd->list_qtd_idx[0] != 0; // qtd list is not empty
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// return !p_qhd->qtd_overlay.halted && p_qhd->qtd_overlay.active;
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@@ -333,12 +333,12 @@ bool tusb_dcd_edpt_busy(uint8_t port, uint8_t ep_addr)
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// add only, controller virtually cannot know
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// TODO remove and merge to tusb_dcd_edpt_xfer
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-static bool pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
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+static bool pipe_add_xfer(uint8_t rhport, uint8_t ed_idx, void * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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- uint8_t qtd_idx = qtd_find_free(port);
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+ uint8_t qtd_idx = qtd_find_free(rhport);
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TU_ASSERT(qtd_idx != 0);
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- dcd_data_t* p_dcd = dcd_data_ptr[port];
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+ dcd_data_t* p_dcd = dcd_data_ptr[rhport];
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dcd_qhd_t * p_qhd = &p_dcd->qhd[ed_idx];
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dcd_qtd_t * p_qtd = &p_dcd->qtd[qtd_idx];
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@@ -361,35 +361,35 @@ static bool pipe_add_xfer(uint8_t port, uint8_t ed_idx, void * buffer, uint16_t
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return true;
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}
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-bool tusb_dcd_edpt_xfer(uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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+bool tusb_dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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uint8_t ep_idx = edpt_addr2phy(ep_addr);
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- VERIFY ( pipe_add_xfer(port, ep_idx, buffer, total_bytes, true) );
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+ VERIFY ( pipe_add_xfer(rhport, ep_idx, buffer, total_bytes, true) );
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- dcd_qhd_t* p_qhd = &dcd_data_ptr[port]->qhd[ ep_idx ];
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- dcd_qtd_t* p_qtd = &dcd_data_ptr[port]->qtd[ p_qhd->list_qtd_idx[0] ];
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+ dcd_qhd_t* p_qhd = &dcd_data_ptr[rhport]->qhd[ ep_idx ];
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+ dcd_qtd_t* p_qtd = &dcd_data_ptr[rhport]->qtd[ p_qhd->list_qtd_idx[0] ];
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p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // attach head QTD to QHD start transferring
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- LPC_USB[port]->ENDPTPRIME = BIT_( edpt_phy2pos(ep_idx) ) ;
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+ LPC_USB[rhport]->ENDPTPRIME = BIT_( edpt_phy2pos(ep_idx) ) ;
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return true;
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}
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//------------- Device Controller Driver's Interrupt Handler -------------//
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-void xfer_complete_isr(uint8_t port, uint32_t reg_complete)
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+void xfer_complete_isr(uint8_t rhport, uint32_t reg_complete)
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{
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for(uint8_t ep_idx = 2; ep_idx < DCD_QHD_MAX; ep_idx++)
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{
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if ( BIT_TEST_(reg_complete, edpt_phy2pos(ep_idx)) )
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{ // 23.10.12.3 Failed QTD also get ENDPTCOMPLETE set
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- dcd_qhd_t * p_qhd = &dcd_data_ptr[port]->qhd[ep_idx];
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+ dcd_qhd_t * p_qhd = &dcd_data_ptr[rhport]->qhd[ep_idx];
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// retire all QTDs in array list, up to 1st still-active QTD
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while( p_qhd->list_qtd_idx[0] != 0 )
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{
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- dcd_qtd_t * p_qtd = &dcd_data_ptr[port]->qtd[ p_qhd->list_qtd_idx[0] ];
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+ dcd_qtd_t * p_qtd = &dcd_data_ptr[rhport]->qtd[ p_qhd->list_qtd_idx[0] ];
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if (p_qtd->active) break; // stop immediately if found still-active QTD and shift array list
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@@ -403,16 +403,16 @@ void xfer_complete_isr(uint8_t port, uint32_t reg_complete)
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bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
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uint8_t ep_addr = edpt_phy2addr(ep_idx);
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- tusb_dcd_xfer_complete(port, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, succeeded); // only number of bytes in the IOC qtd
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+ tusb_dcd_xfer_complete(rhport, ep_addr, p_qtd->expected_bytes - p_qtd->total_bytes, succeeded); // only number of bytes in the IOC qtd
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}
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}
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}
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}
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}
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-void hal_dcd_isr(uint8_t port)
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+void hal_dcd_isr(uint8_t rhport)
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{
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- LPC_USB0_Type* const lpc_usb = LPC_USB[port];
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+ LPC_USB0_Type* const lpc_usb = LPC_USB[rhport];
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uint32_t const int_enable = lpc_usb->USBINTR_D;
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uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
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@@ -422,8 +422,8 @@ void hal_dcd_isr(uint8_t port)
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if (int_status & INT_MASK_RESET)
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{
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- bus_reset(port);
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- tusb_dcd_bus_event(port, USBD_BUS_EVENT_RESET);
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+ bus_reset(rhport);
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+ tusb_dcd_bus_event(rhport, USBD_BUS_EVENT_RESET);
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}
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if (int_status & INT_MASK_SUSPEND)
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@@ -451,7 +451,7 @@ void hal_dcd_isr(uint8_t port)
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uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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- dcd_data_t* const p_dcd = dcd_data_ptr[port];
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+ dcd_data_t* const p_dcd = dcd_data_ptr[rhport];
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//------------- Set up Received -------------//
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if (lpc_usb->ENDPTSETUPSTAT)
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@@ -459,7 +459,7 @@ void hal_dcd_isr(uint8_t port)
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// 23.10.10.2 Operational model for setup transfers
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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- tusb_dcd_setup_received(port, (uint8_t*) &p_dcd->qhd[0].setup_request);
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+ tusb_dcd_setup_received(rhport, (uint8_t*) &p_dcd->qhd[0].setup_request);
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}
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//------------- Control Request Completed -------------//
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else if ( edpt_complete & ( BIT_(0) | BIT_(16)) )
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@@ -476,7 +476,7 @@ void hal_dcd_isr(uint8_t port)
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bool succeeded = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? false : true;
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(void) succeeded;
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- tusb_dcd_control_complete(port);
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+ tusb_dcd_control_complete(rhport);
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}
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}
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}
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@@ -485,13 +485,13 @@ void hal_dcd_isr(uint8_t port)
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//------------- Transfer Complete -------------//
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if ( edpt_complete & ~(BIT_(0) | BIT_(16)) )
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{
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- xfer_complete_isr(port, edpt_complete);
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+ xfer_complete_isr(rhport, edpt_complete);
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}
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}
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if (int_status & INT_MASK_SOF)
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{
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- tusb_dcd_bus_event(port, USBD_BUS_EVENT_SOF);
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+ tusb_dcd_bus_event(rhport, USBD_BUS_EVENT_SOF);
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}
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if (int_status & INT_MASK_NAK) {}
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