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@@ -413,7 +413,7 @@ static inline void insert_qtd_to_qhd(ehci_qhd_t *p_qhd, ehci_qtd_t *p_qtd_new)
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if (p_qhd->p_qtd_list_head == NULL) // empty list
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{
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p_qhd->p_qtd_list_head = p_qhd->p_qtd_list_tail = p_qtd_new;
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- p_qhd->qtd_overlay.next.address = (uint32_t) p_qhd->p_qtd_list_head;
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+ p_qhd->qtd_overlay.next.address = (uint32_t) p_qtd_new;
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}else
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{
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p_qhd->p_qtd_list_tail->next.address = (uint32_t) p_qtd_new;
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@@ -450,7 +450,6 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_std_request_t const *
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init_qtd(p_setup, (uint32_t) p_request, 8);
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p_setup->pid = EHCI_PID_SETUP;
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p_setup->next.address = (uint32_t) p_data;
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- insert_qtd_to_qhd(p_qhd, p_setup);
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//------------- DATA Phase -------------//
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if (p_request->wLength > 0)
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@@ -458,12 +457,10 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_std_request_t const *
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init_qtd(p_data, (uint32_t) data, p_request->wLength);
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p_data->data_toggle = 1;
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p_data->pid = p_request->bmRequestType.direction ? EHCI_PID_IN : EHCI_PID_OUT;
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- insert_qtd_to_qhd(p_qhd, p_data);
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}else
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{
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p_data = p_setup;
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}
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-
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p_data->next.address = (uint32_t) p_status;
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//------------- STATUS Phase -------------//
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@@ -472,7 +469,12 @@ tusb_error_t hcd_pipe_control_xfer(uint8_t dev_addr, tusb_std_request_t const *
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p_status->data_toggle = 1;
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p_status->pid = p_request->bmRequestType.direction ? EHCI_PID_OUT : EHCI_PID_IN; // reverse direction of data phase
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p_status->next.terminate = 1;
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- insert_qtd_to_qhd(p_qhd, p_status);
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+
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+ //------------- Attach TDs list to Control Endpoint -------------//
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+ p_qhd->p_qtd_list_head = p_setup;
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+ p_qhd->p_qtd_list_tail = p_status;
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+
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+ p_qhd->qtd_overlay.next.address = (uint32_t) p_setup;
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return TUSB_ERROR_NONE;
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}
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@@ -576,7 +578,10 @@ static inline ehci_qtd_t* get_control_qtds(uint8_t dev_addr)
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static void init_qhd(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_packet_size, uint8_t endpoint_addr, uint8_t xfer_type)
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{
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- memclr_(p_qhd, sizeof(ehci_qhd_t));
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+ if (dev_addr != 0)
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+ {
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+ memclr_(p_qhd, sizeof(ehci_qhd_t));
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+ }
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p_qhd->device_address = dev_addr;
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p_qhd->inactive_next_xact = 0;
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@@ -595,6 +600,9 @@ static void init_qhd(ehci_qhd_t *p_qhd, uint8_t dev_addr, uint16_t max_packet_si
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p_qhd->interrupt_smask = (TUSB_SPEED_HIGH == usbh_device_info_pool[dev_addr].speed) ? 0xFF : 0x01;
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// Highspeed: ignored by Host Controller, Full/Low: 4.12.2.1 (EHCI) case 1 schedule complete split at 2,3,4 uframe
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p_qhd->non_hs_interrupt_cmask = BIN8(11100);
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+ }else
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+ {
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+ p_qhd->interrupt_smask = p_qhd->non_hs_interrupt_cmask = 0;
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}
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p_qhd->hub_address = usbh_device_info_pool[dev_addr].hub_addr;
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