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@@ -48,22 +48,41 @@
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/*------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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/* MACRO TYPEDEF CONSTANT ENUM
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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*------------------------------------------------------------------*/
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-enum { MAX_PACKET_SIZE = 64 };
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+enum
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+{
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+ // Max allowed by USB specs
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+ MAX_PACKET_SIZE = 64,
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+
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+ // Mask of all END event (IN & OUT) for all endpoints. ENDEPIN0-7, ENDEPOUT0-7, ENDISOIN, ENDISOOUT
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+ EDPT_END_ALL_MASK = 0x1FFBFC
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+};
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/*------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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/* VARIABLE DECLARATION
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/* VARIABLE DECLARATION
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*------------------------------------------------------------------*/
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*------------------------------------------------------------------*/
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-static struct
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+typedef struct
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+{
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+ uint8_t* buffer;
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+ uint16_t total_len;
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+ uint16_t actual_len;
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+
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+ uint8_t mps; // max packet size
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+} nom_xfer_t;
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+
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+/*static*/ struct
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{
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{
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struct
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struct
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{
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{
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uint8_t* buffer;
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uint8_t* buffer;
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- uint16_t xfer_len;
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+ uint16_t len;
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uint8_t dir;
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uint8_t dir;
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}control;
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}control;
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+ // Non control: 7 endpoints IN & OUT (offset 1)
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+ nom_xfer_t xfer[2][7];
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+
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volatile bool dma_running;
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volatile bool dma_running;
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-}_dcd_data;
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+}_dcd;
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/*------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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/* Controller API
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/* Controller API
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@@ -73,30 +92,6 @@ static void hfclk_ready(nrf_drv_clock_evt_type_t event)
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// do nothing
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// do nothing
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}
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}
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-static void enable_usb(void)
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-{
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- /* Prepare for READY event receiving */
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- nrf_usbd_eventcause_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
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-
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- /* Enable the peripheral */
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- nrf_usbd_enable();
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-
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- // Enable HFCLK
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- nrf_drv_clock_handler_item_t clock_handler_item =
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- {
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- .event_handler = hfclk_ready
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- };
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- nrf_drv_clock_hfclk_request(&clock_handler_item);
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-
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- /* Waiting for peripheral to enable, this should take a few us */
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- while ( !(NRF_USBD_EVENTCAUSE_READY_MASK & NRF_USBD->EVENTCAUSE) ) { }
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- nrf_usbd_eventcause_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
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- nrf_usbd_event_clear(NRF_USBD_EVENT_USBEVENT);
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-
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- // Wait until power is ready
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- while (!nrf_power_usbregstatus_outrdy_get()) {}
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-}
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-
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static void power_usb_event_handler(nrf_drv_power_usb_evt_t event)
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static void power_usb_event_handler(nrf_drv_power_usb_evt_t event)
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{
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{
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// 51.4 specs USBD start-up sequene
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// 51.4 specs USBD start-up sequene
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@@ -133,8 +128,8 @@ static void power_usb_event_handler(nrf_drv_power_usb_evt_t event)
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{
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{
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*((volatile uint32_t *) (NRF_USBD_BASE + 0x800)) = 0x7E3;
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*((volatile uint32_t *) (NRF_USBD_BASE + 0x800)) = 0x7E3;
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*((volatile uint32_t *) (NRF_USBD_BASE + 0x804)) = 0x40;
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*((volatile uint32_t *) (NRF_USBD_BASE + 0x804)) = 0x40;
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- __ISB();
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- __DSB();
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+
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+ __ISB(); __DSB();
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}
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}
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nrf_usbd_isosplit_set(NRF_USBD_ISOSPLIT_Half);
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nrf_usbd_isosplit_set(NRF_USBD_ISOSPLIT_Half);
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@@ -192,7 +187,7 @@ void bus_reset(void)
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NRF_USBD->TASKS_STARTISOIN = 0;
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NRF_USBD->TASKS_STARTISOIN = 0;
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NRF_USBD->TASKS_STARTISOOUT = 0;
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NRF_USBD->TASKS_STARTISOOUT = 0;
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- varclr(&_dcd_data);
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+ varclr(&_dcd);
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}
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}
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/*------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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@@ -216,14 +211,20 @@ void tusb_dcd_disconnect (uint8_t port)
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{
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{
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}
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}
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+
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void tusb_dcd_set_address (uint8_t port, uint8_t dev_addr)
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void tusb_dcd_set_address (uint8_t port, uint8_t dev_addr)
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{
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{
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(void) port;
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(void) port;
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- // address is automatically update by hw controller
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+
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+ // Set Address is automatically update by hw controller
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}
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}
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+
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void tusb_dcd_set_config (uint8_t port, uint8_t config_num)
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void tusb_dcd_set_config (uint8_t port, uint8_t config_num)
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{
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{
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+ (void) port;
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+ (void) config_num;
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+ // Nothing to do
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}
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}
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/*------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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@@ -232,9 +233,9 @@ void tusb_dcd_set_config (uint8_t port, uint8_t config_num)
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static void edpt_dma_start(uint8_t epnum, uint8_t dir)
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static void edpt_dma_start(uint8_t epnum, uint8_t dir)
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{
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{
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// Only one dma could be active
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// Only one dma could be active
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- while ( _dcd_data.dma_running ) { }
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+ while ( _dcd.dma_running ) { }
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- _dcd_data.dma_running = true;
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+ _dcd.dma_running = true;
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if ( dir == TUSB_DIR_OUT )
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if ( dir == TUSB_DIR_OUT )
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{
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{
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@@ -243,35 +244,38 @@ static void edpt_dma_start(uint8_t epnum, uint8_t dir)
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{
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{
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NRF_USBD->TASKS_STARTEPIN[epnum] = 1;
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NRF_USBD->TASKS_STARTEPIN[epnum] = 1;
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}
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}
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+
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+ __ISB(); __DSB();
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}
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}
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static void edpt_dma_end(void)
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static void edpt_dma_end(void)
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{
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{
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- _dcd_data.dma_running = false;
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+ _dcd.dma_running = false;
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}
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}
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static void control_xact_start(void)
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static void control_xact_start(void)
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{
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{
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// Each transaction is up to 64 bytes
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// Each transaction is up to 64 bytes
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- uint8_t xact_len = min16_of(_dcd_data.control.xfer_len, MAX_PACKET_SIZE);
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+ uint8_t const xact_len = min16_of(_dcd.control.len, MAX_PACKET_SIZE);
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- if ( _dcd_data.control.dir == TUSB_DIR_OUT )
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+ if ( _dcd.control.dir == TUSB_DIR_OUT )
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{
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{
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// TODO control out
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// TODO control out
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- NRF_USBD->EPOUT[0].PTR = (uint32_t) _dcd_data.control.buffer;
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+ NRF_USBD->EPOUT[0].PTR = (uint32_t) _dcd.control.buffer;
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NRF_USBD->EPOUT[0].MAXCNT = xact_len;
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NRF_USBD->EPOUT[0].MAXCNT = xact_len;
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NRF_USBD->TASKS_EP0RCVOUT = 1;
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NRF_USBD->TASKS_EP0RCVOUT = 1;
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+ __ISB(); __DSB();
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}else
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}else
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{
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{
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- NRF_USBD->EPIN[0].PTR = (uint32_t) _dcd_data.control.buffer;
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+ NRF_USBD->EPIN[0].PTR = (uint32_t) _dcd.control.buffer;
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NRF_USBD->EPIN[0].MAXCNT = xact_len;
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NRF_USBD->EPIN[0].MAXCNT = xact_len;
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edpt_dma_start(0, TUSB_DIR_IN);
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edpt_dma_start(0, TUSB_DIR_IN);
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}
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}
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- _dcd_data.control.buffer += xact_len;
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- _dcd_data.control.xfer_len -= xact_len;
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+ _dcd.control.buffer += xact_len;
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+ _dcd.control.len -= xact_len;
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}
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}
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//static void control_xact_done(void)
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//static void control_xact_done(void)
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@@ -300,15 +304,16 @@ bool tusb_dcd_control_xfer (uint8_t port, tusb_dir_t dir, uint8_t * buffer, uint
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if ( length )
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if ( length )
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{
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{
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// Data Phase
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// Data Phase
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- _dcd_data.control.xfer_len = length;
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- _dcd_data.control.buffer = buffer;
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- _dcd_data.control.dir = (uint8_t) dir;
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+ _dcd.control.len = length;
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+ _dcd.control.buffer = buffer;
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+ _dcd.control.dir = (uint8_t) dir;
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control_xact_start();
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control_xact_start();
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}else
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}else
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{
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{
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// Status Phase
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// Status Phase
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NRF_USBD->TASKS_EP0STATUS = 1;
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NRF_USBD->TASKS_EP0STATUS = 1;
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+ __ISB(); __DSB();
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}
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}
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return true;
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return true;
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@@ -317,40 +322,99 @@ void tusb_dcd_control_stall (uint8_t port)
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{
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{
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(void) port;
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(void) port;
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NRF_USBD->TASKS_EP0STALL = 1;
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NRF_USBD->TASKS_EP0STALL = 1;
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+ __ISB(); __DSB();
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}
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}
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/*------------------------------------------------------------------*/
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/*------------------------------------------------------------------*/
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/*
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/*
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*------------------------------------------------------------------*/
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*------------------------------------------------------------------*/
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-bool tusb_dcd_edpt_open (uint8_t port, tusb_descriptor_endpoint_t const * p_endpoint_desc)
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+static void normal_xact_start(uint8_t epnum, uint8_t dir)
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+{
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+ // Each transaction is up to Max Packet Size
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+ nom_xfer_t* xfer = &_dcd.xfer[dir][epnum-1];
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+
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+ uint8_t const xact_len = min16_of(xfer->total_len - xfer->actual_len, xfer->mps);
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+
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+ if ( dir == TUSB_DIR_OUT )
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+ {
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+ // Overwrite size will allow hw to accept data
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+ NRF_USBD->SIZE.EPOUT[epnum] = 0;
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+ __ISB(); __DSB();
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+ }else
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+ {
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+ NRF_USBD->EPIN[epnum].PTR = (uint32_t) xfer->buffer;
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+ NRF_USBD->EPIN[epnum].MAXCNT = xact_len;
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+
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+ xfer->buffer += xact_len;
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+
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+ edpt_dma_start(epnum, TUSB_DIR_IN);
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+ }
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+}
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+
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+bool tusb_dcd_edpt_open (uint8_t port, tusb_descriptor_endpoint_t const * desc_edpt)
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{
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{
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(void) port;
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(void) port;
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+ uint8_t const epnum = edpt_number(desc_edpt->bEndpointAddress);
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+ uint8_t const dir = edpt_dir(desc_edpt->bEndpointAddress);
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+
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+ _dcd.xfer[dir][epnum-1].mps = desc_edpt->wMaxPacketSize.size;
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+
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+ if ( dir == TUSB_DIR_OUT )
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+ {
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+ NRF_USBD->INTENSET = BIT_(USBD_INTEN_ENDEPOUT0_Pos + epnum);
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+ NRF_USBD->EPOUTEN |= BIT_(epnum);
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+ }else
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+ {
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+ NRF_USBD->INTENSET = BIT_(USBD_INTEN_ENDEPIN0_Pos + epnum);
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+ NRF_USBD->EPINEN |= BIT_(epnum);
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+ }
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+ __ISB(); __DSB();
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+
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return true;
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return true;
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}
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}
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-bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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+bool tusb_dcd_edpt_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes, bool int_on_complete)
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{
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{
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+ (void) port;
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+
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+ uint8_t const epnum = edpt_number(ep_addr);
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+ uint8_t const dir = edpt_dir(ep_addr);
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+
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+ _dcd.xfer[dir][epnum-1].buffer = buffer;
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+ _dcd.xfer[dir][epnum-1].total_len = total_bytes;
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+ _dcd.xfer[dir][epnum-1].actual_len = 0;
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+
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+ normal_xact_start(epnum, dir);
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+
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+// if ( dir == TUSB_DIR_OUT )
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+// {
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+// // TODO
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+// }else
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+// {
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+//
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+// }
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+
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return true;
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return true;
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}
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}
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-bool tusb_dcd_edpt_queue_xfer (uint8_t port, uint8_t edpt_addr, uint8_t * buffer, uint16_t total_bytes)
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+bool tusb_dcd_edpt_queue_xfer (uint8_t port, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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{
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return true;
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return true;
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}
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}
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-void tusb_dcd_edpt_stall (uint8_t port, uint8_t edpt_addr)
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+void tusb_dcd_edpt_stall (uint8_t port, uint8_t ep_addr)
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|
{
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|
{
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}
|
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}
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-void tusb_dcd_edpt_clear_stall (uint8_t port, uint8_t edpt_addr)
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+void tusb_dcd_edpt_clear_stall (uint8_t port, uint8_t ep_addr)
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{
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|
{
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}
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}
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// TODO may remove
|
|
// TODO may remove
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-bool tusb_dcd_edpt_busy (uint8_t port, uint8_t edpt_addr)
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+bool tusb_dcd_edpt_busy (uint8_t port, uint8_t ep_addr)
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{
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|
{
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|
return true;
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return true;
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}
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}
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|
@@ -373,100 +437,10 @@ void USBD_IRQHandler(void)
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// nrf_usbd_event_clear()
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// nrf_usbd_event_clear()
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regclr[i] = 0;
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regclr[i] = 0;
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- __ISB();
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- __DSB();
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- }
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- }
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-#if 0
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- if (nrf_drv_usbd_errata_104())
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- {
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- /* Event correcting */
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- if ((0 == m_dma_pending) && (0 != (active & (USBD_INTEN_SOF_Msk))))
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- {
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- uint8_t usbi, uoi, uii;
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- /* Testing */
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7A9;
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- uii = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
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- if (0 != uii)
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- {
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- uii &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
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- }
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-
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AA;
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- uoi = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
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- if (0 != uoi)
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- {
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- uoi &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
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- }
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AB;
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- usbi = (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
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- if (0 != usbi)
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- {
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- usbi &= (uint8_t)(*((volatile uint32_t *)(NRF_USBD_BASE + 0x804)));
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- }
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- /* Processing */
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AC;
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- uii &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
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- if (0 != uii)
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- {
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- uint8_t rb;
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- m_simulated_dataepstatus |= ((uint32_t)uii) << USBD_EPIN_BITPOS_0;
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7A9;
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = uii;
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- rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
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- NRF_DRV_USBD_LOG_PROTO1_FIX_PRINTF(" uii: 0x%.2x (0x%.2x)", uii, rb);
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- }
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-
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AD;
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- uoi &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
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- if (0 != uoi)
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- {
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- uint8_t rb;
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- m_simulated_dataepstatus |= ((uint32_t)uoi) << USBD_EPOUT_BITPOS_0;
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AA;
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = uoi;
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- rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
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- NRF_DRV_USBD_LOG_PROTO1_FIX_PRINTF(" uoi: 0x%.2u (0x%.2x)", uoi, rb);
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- }
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-
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- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AE;
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- usbi &= (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
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- if (0 != usbi)
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- {
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- uint8_t rb;
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- if (usbi & 0x01)
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- {
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- active |= USBD_INTEN_EP0SETUP_Msk;
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- }
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- if (usbi & 0x10)
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- {
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- active |= USBD_INTEN_USBRESET_Msk;
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|
- }
|
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|
|
|
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x800)) = 0x7AB;
|
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|
|
|
- *((volatile uint32_t *)(NRF_USBD_BASE + 0x804)) = usbi;
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|
|
|
- rb = (uint8_t)*((volatile uint32_t *)(NRF_USBD_BASE + 0x804));
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|
|
|
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- NRF_DRV_USBD_LOG_PROTO1_FIX_PRINTF(" usbi: 0x%.2u (0x%.2x)", usbi, rb);
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|
|
|
|
- }
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|
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|
|
-
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|
|
|
|
- if (0 != (m_simulated_dataepstatus &
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|
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- ~((1U << USBD_EPOUT_BITPOS_0) | (1U << USBD_EPIN_BITPOS_0))))
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|
|
|
|
- {
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|
|
|
|
- active |= enabled & NRF_USBD_INT_DATAEP_MASK;
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|
|
|
|
- }
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|
|
- if (0 != (m_simulated_dataepstatus &
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|
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- ((1U << USBD_EPOUT_BITPOS_0) | (1U << USBD_EPIN_BITPOS_0))))
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|
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|
|
- {
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|
|
|
|
- if (0 != (enabled & NRF_USBD_INT_EP0DATADONE_MASK))
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|
|
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|
- {
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|
|
|
|
- m_simulated_dataepstatus &=
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|
|
|
|
- ~((1U << USBD_EPOUT_BITPOS_0) | (1U << USBD_EPIN_BITPOS_0));
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|
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|
|
- active |= NRF_USBD_INT_EP0DATADONE_MASK;
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|
|
|
- }
|
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|
|
- }
|
|
|
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|
|
+ __ISB(); __DSB();
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
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|
-#endif
|
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|
|
|
|
|
|
|
/*------------- Interrupt Processing -------------*/
|
|
/*------------- Interrupt Processing -------------*/
|
|
|
|
|
|
|
@@ -477,6 +451,12 @@ void USBD_IRQHandler(void)
|
|
|
tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESET);
|
|
tusb_dcd_bus_event(0, USBD_BUS_EVENT_RESET);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
|
|
+ if ( int_status & EDPT_END_ALL_MASK )
|
|
|
|
|
+ {
|
|
|
|
|
+ // DMA complete move data from SRAM -> Endpoint
|
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|
|
|
+ edpt_dma_end();
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
/*------------- Control Transfer -------------*/
|
|
/*------------- Control Transfer -------------*/
|
|
|
if ( int_status & USBD_INTEN_EP0SETUP_Msk )
|
|
if ( int_status & USBD_INTEN_EP0SETUP_Msk )
|
|
|
{
|
|
{
|
|
@@ -485,29 +465,25 @@ void USBD_IRQHandler(void)
|
|
|
NRF_USBD->WINDEXL, NRF_USBD->WINDEXH, NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
|
|
NRF_USBD->WINDEXL, NRF_USBD->WINDEXH, NRF_USBD->WLENGTHL, NRF_USBD->WLENGTHH
|
|
|
};
|
|
};
|
|
|
|
|
|
|
|
- //NRF_USBD->TASKS_EP0STALL = 0; // clear stall upon receive new setup
|
|
|
|
|
tusb_dcd_setup_received(0, setup);
|
|
tusb_dcd_setup_received(0, setup);
|
|
|
}
|
|
}
|
|
|
|
|
|
|
|
- if ( int_status & USBD_INTEN_ENDEPIN0_Msk )
|
|
|
|
|
- {
|
|
|
|
|
- edpt_dma_end();
|
|
|
|
|
- }
|
|
|
|
|
-
|
|
|
|
|
if ( int_status & USBD_INTEN_EP0DATADONE_Msk )
|
|
if ( int_status & USBD_INTEN_EP0DATADONE_Msk )
|
|
|
{
|
|
{
|
|
|
- if ( _dcd_data.control.dir == TUSB_DIR_OUT )
|
|
|
|
|
|
|
+ if ( _dcd.control.dir == TUSB_DIR_OUT )
|
|
|
{
|
|
{
|
|
|
- // out control need to wait for END EPOUT (DMA complete) event
|
|
|
|
|
|
|
+ // OUT data from Host -> Endpoint
|
|
|
|
|
+ // Trigger DMA to move Endpoint -> SRAM
|
|
|
edpt_dma_start(0, TUSB_DIR_OUT);
|
|
edpt_dma_start(0, TUSB_DIR_OUT);
|
|
|
}else
|
|
}else
|
|
|
{
|
|
{
|
|
|
- if ( _dcd_data.control.xfer_len > 0 )
|
|
|
|
|
|
|
+ // IN: data transferred from Endpoint -> Host
|
|
|
|
|
+ if ( _dcd.control.len > 0 )
|
|
|
{
|
|
{
|
|
|
control_xact_start();
|
|
control_xact_start();
|
|
|
}else
|
|
}else
|
|
|
{
|
|
{
|
|
|
- // Data IN xfer complete
|
|
|
|
|
|
|
+ // Control IN complete
|
|
|
tusb_dcd_xfer_complete(0, 0, 0, true);
|
|
tusb_dcd_xfer_complete(0, 0, 0, true);
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
@@ -515,15 +491,84 @@ void USBD_IRQHandler(void)
|
|
|
|
|
|
|
|
if ( int_status & USBD_INTEN_ENDEPOUT0_Msk)
|
|
if ( int_status & USBD_INTEN_ENDEPOUT0_Msk)
|
|
|
{
|
|
{
|
|
|
- edpt_dma_end();
|
|
|
|
|
-
|
|
|
|
|
- if ( _dcd_data.control.xfer_len > 0 )
|
|
|
|
|
|
|
+ // OUT data moved from Endpoint -> SRAM
|
|
|
|
|
+ if ( _dcd.control.len > 0 )
|
|
|
{
|
|
{
|
|
|
control_xact_start();
|
|
control_xact_start();
|
|
|
}else
|
|
}else
|
|
|
{
|
|
{
|
|
|
- // Data OUT xfer complete
|
|
|
|
|
|
|
+ // Control OUT complete
|
|
|
tusb_dcd_xfer_complete(0, 0, 0, true);
|
|
tusb_dcd_xfer_complete(0, 0, 0, true);
|
|
|
}
|
|
}
|
|
|
}
|
|
}
|
|
|
|
|
+
|
|
|
|
|
+ /*------------- Bulk/Interrupt Transfer -------------*/
|
|
|
|
|
+ if ( int_status & USBD_INTEN_EPDATA_Msk)
|
|
|
|
|
+ {
|
|
|
|
|
+ uint32_t data_status = NRF_USBD->EPDATASTATUS;
|
|
|
|
|
+
|
|
|
|
|
+ nrf_usbd_epdatastatus_clear(data_status);
|
|
|
|
|
+
|
|
|
|
|
+ // In: data from Endpoint -> Host
|
|
|
|
|
+ for(uint8_t epnum=1; epnum<8; epnum++)
|
|
|
|
|
+ {
|
|
|
|
|
+ if ( BIT_TEST_(data_status, epnum ) )
|
|
|
|
|
+ {
|
|
|
|
|
+ nom_xfer_t* xfer = &_dcd.xfer[TUSB_DIR_IN][epnum-1];
|
|
|
|
|
+
|
|
|
|
|
+ xfer->actual_len += NRF_USBD->EPIN[epnum].MAXCNT;
|
|
|
|
|
+
|
|
|
|
|
+ if ( xfer->actual_len < xfer->total_len )
|
|
|
|
|
+ {
|
|
|
|
|
+ // more to xfer
|
|
|
|
|
+ normal_xact_start(epnum, TUSB_DIR_IN);
|
|
|
|
|
+ } else
|
|
|
|
|
+ {
|
|
|
|
|
+ // xfer complete
|
|
|
|
|
+ tusb_dcd_xfer_complete(0, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, true);
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ // OUT: data from Host -> Endpoint
|
|
|
|
|
+ for(uint8_t epnum=1; epnum<8; epnum++)
|
|
|
|
|
+ {
|
|
|
|
|
+ if ( BIT_TEST_(data_status, 16+epnum ) )
|
|
|
|
|
+ {
|
|
|
|
|
+ nom_xfer_t* xfer = &_dcd.xfer[TUSB_DIR_OUT][epnum-1];
|
|
|
|
|
+
|
|
|
|
|
+ uint8_t const xact_len = NRF_USBD->SIZE.EPOUT[epnum];
|
|
|
|
|
+
|
|
|
|
|
+ // Trigger DMA move data from Endpoint -> SRAM
|
|
|
|
|
+ NRF_USBD->EPOUT[epnum].PTR = (uint32_t) xfer->buffer;
|
|
|
|
|
+ NRF_USBD->EPOUT[epnum].MAXCNT = xact_len;
|
|
|
|
|
+
|
|
|
|
|
+ edpt_dma_start(epnum, TUSB_DIR_OUT);
|
|
|
|
|
+
|
|
|
|
|
+ xfer->buffer += xact_len;
|
|
|
|
|
+ xfer->actual_len += xact_len;
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
|
|
+ // OUT: data from DMA -> SRAM
|
|
|
|
|
+ for(uint8_t epnum=1; epnum<8; epnum++)
|
|
|
|
|
+ {
|
|
|
|
|
+ if ( BIT_TEST_(int_status, USBD_INTEN_ENDEPOUT0_Pos+epnum) )
|
|
|
|
|
+ {
|
|
|
|
|
+ nom_xfer_t* xfer = &_dcd.xfer[TUSB_DIR_OUT][epnum-1];
|
|
|
|
|
+
|
|
|
|
|
+ // Transfer complete if transaction len < Max Packet Size or total len is transferred
|
|
|
|
|
+ if ( (NRF_USBD->EPOUT[epnum].AMOUNT == xfer->mps) && (xfer->actual_len < xfer->total_len) )
|
|
|
|
|
+ {
|
|
|
|
|
+ // Allow Host -> Endpoint
|
|
|
|
|
+ NRF_USBD->SIZE.EPOUT[epnum] = 0;
|
|
|
|
|
+ __ISB(); __DSB();
|
|
|
|
|
+ }else
|
|
|
|
|
+ {
|
|
|
|
|
+ tusb_dcd_xfer_complete(0, epnum, xfer->actual_len, true);
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+ }
|
|
|
|
|
+
|
|
|
}
|
|
}
|