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@@ -52,23 +52,23 @@ typedef struct TU_ATTR_PACKED
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struct {
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union {
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struct {
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- uint16_t : 2;
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- uint16_t tok_pid : 4;
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- uint16_t data : 1;
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- uint16_t own : 1;
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- uint16_t : 8;
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+ uint16_t : 2;
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+ __IO uint16_t tok_pid : 4;
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+ uint16_t data : 1;
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+ __IO uint16_t own : 1;
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+ uint16_t : 8;
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};
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struct {
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- uint16_t : 2;
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- uint16_t bdt_stall: 1;
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- uint16_t dts : 1;
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- uint16_t ninc : 1;
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- uint16_t keep : 1;
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- uint16_t : 10;
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+ uint16_t : 2;
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+ uint16_t bdt_stall : 1;
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+ uint16_t dts : 1;
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+ uint16_t ninc : 1;
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+ uint16_t keep : 1;
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+ uint16_t : 10;
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};
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};
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- uint16_t bc : 10;
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- uint16_t : 6;
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+ __IO uint16_t bc : 10;
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+ uint16_t : 6;
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};
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};
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uint8_t *addr;
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@@ -120,10 +120,8 @@ static void prepare_next_setup_packet(uint8_t rhport)
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{
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const unsigned out_odd = _dcd.endpoint[0][0].odd;
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const unsigned in_odd = _dcd.endpoint[0][1].odd;
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- if (_dcd.bdt[0][0][out_odd].own) {
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- TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
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- return;
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- }
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+ TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, );
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+
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_dcd.bdt[0][0][out_odd].data = 0;
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_dcd.bdt[0][0][out_odd ^ 1].data = 1;
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_dcd.bdt[0][1][in_odd].data = 1;
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@@ -134,10 +132,16 @@ static void prepare_next_setup_packet(uint8_t rhport)
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static void process_stall(uint8_t rhport)
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{
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- if (KHCI->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) {
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- /* clear stall condition of the control pipe */
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- prepare_next_setup_packet(rhport);
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- KHCI->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
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+ for (int i = 0; i < 16; ++i) {
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+ unsigned const endpt = KHCI->ENDPOINT[i].ENDPT;
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+
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+ if (endpt & USB_ENDPT_EPSTALL_MASK) {
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+ // prepare next setup if endpoint0
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+ if ( i == 0 ) prepare_next_setup_packet(rhport);
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+
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+ // clear stall bit
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+ KHCI->ENDPOINT[i].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
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+ }
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}
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}
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@@ -145,12 +149,17 @@ static void process_tokdne(uint8_t rhport)
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{
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const unsigned s = KHCI->STAT;
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KHCI->ISTAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
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+
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+ uint8_t const epnum = (s >> USB_STAT_ENDP_SHIFT);
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+ uint8_t const dir = (s & USB_STAT_TX_MASK) >> USB_STAT_TX_SHIFT;
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+ unsigned const odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
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+
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buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
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endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3];
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- unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
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/* fetch pid before discarded by the next steps */
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const unsigned pid = bd->tok_pid;
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+
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/* reset values for a next transfer */
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bd->bdt_stall = 0;
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bd->dts = 1;
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@@ -163,9 +172,6 @@ static void process_tokdne(uint8_t rhport)
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KHCI->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
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return;
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}
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- if (s >> 4) {
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- TU_LOG1("TKDNE %x\r\n", s);
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- }
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const unsigned bc = bd->bc;
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const unsigned remaining = ep->remaining - bc;
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@@ -184,9 +190,9 @@ static void process_tokdne(uint8_t rhport)
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}
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const unsigned length = ep->length;
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dcd_event_xfer_complete(rhport,
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- ((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
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+ tu_edpt_addr(epnum, dir),
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length - remaining, XFER_RESULT_SUCCESS, true);
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- if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
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+ if (0 == epnum && 0 == length) {
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/* After completion a ZLP of control transfer,
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* it prepares for the next steup transfer. */
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if (_dcd.addr) {
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@@ -204,7 +210,8 @@ static void process_bus_reset(uint8_t rhport)
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KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
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KHCI->CTL |= USB_CTL_ODDRST_MASK;
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KHCI->ADDR = 0;
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- KHCI->INTEN = (KHCI->INTEN & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
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+ KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK | USB_INTEN_SLEEPEN_MASK |
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+ USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
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KHCI->ENDPOINT[0].ENDPT = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
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for (unsigned i = 1; i < 16; ++i) {
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@@ -229,21 +236,27 @@ static void process_bus_reset(uint8_t rhport)
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dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
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}
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-static void process_bus_inactive(uint8_t rhport)
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+static void process_bus_sleep(uint8_t rhport)
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{
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- (void) rhport;
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+ // Enable resume & disable suspend interrupt
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const unsigned inten = KHCI->INTEN;
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+
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KHCI->INTEN = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
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+ KHCI->USBTRC0 |= USB_USBTRC0_USBRESMEN_MASK;
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KHCI->USBCTRL |= USB_USBCTRL_SUSP_MASK;
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+
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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}
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-static void process_bus_active(uint8_t rhport)
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+static void process_bus_resume(uint8_t rhport)
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{
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- (void) rhport;
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- KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK;
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+ // Enable suspend & disable resume interrupt
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const unsigned inten = KHCI->INTEN;
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+
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+ KHCI->USBCTRL &= ~USB_USBCTRL_SUSP_MASK; // will also clear USB_USBTRC0_USB_RESUME_INT_MASK
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+ KHCI->USBTRC0 &= ~USB_USBTRC0_USBRESMEN_MASK;
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KHCI->INTEN = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
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+
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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@@ -256,12 +269,15 @@ void dcd_init(uint8_t rhport)
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KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
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while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
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+
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tu_memclr(&_dcd, sizeof(_dcd));
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KHCI->USBTRC0 |= TU_BIT(6); /* software must set this bit to 1 */
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KHCI->BDTPAGE1 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
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KHCI->BDTPAGE2 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
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KHCI->BDTPAGE3 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
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+ KHCI->INTEN = USB_INTEN_USBRSTEN_MASK;
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+
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dcd_connect(rhport);
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NVIC_ClearPendingIRQ(USB0_IRQn);
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}
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@@ -269,8 +285,6 @@ void dcd_init(uint8_t rhport)
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void dcd_int_enable(uint8_t rhport)
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{
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(void) rhport;
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- KHCI->INTEN = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
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- USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
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NVIC_EnableIRQ(USB0_IRQn);
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}
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@@ -278,13 +292,11 @@ void dcd_int_disable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(USB0_IRQn);
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- KHCI->INTEN = 0;
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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- (void) rhport;
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- _dcd.addr = dev_addr & 0x7F;
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+ _dcd.addr = dev_addr & 0x7F;
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/* Response with status first before changing device address */
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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}
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@@ -292,9 +304,12 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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- unsigned cnt = SystemCoreClock / 100;
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+
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KHCI->CTL |= USB_CTL_RESUME_MASK;
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+
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+ unsigned cnt = SystemCoreClock / 1000;
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while (cnt--) __NOP();
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+
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KHCI->CTL &= ~USB_CTL_RESUME_MASK;
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}
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@@ -321,12 +336,12 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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(void) rhport;
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const unsigned ep_addr = ep_desc->bEndpointAddress;
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- const unsigned epn = ep_addr & 0xFu;
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- const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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+ const unsigned epn = tu_edpt_number(ep_addr);
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+ const unsigned dir = tu_edpt_dir(ep_addr);
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const unsigned xfer = ep_desc->bmAttributes.xfer;
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endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
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const unsigned odd = ep->odd;
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- buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
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+ buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
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/* No support for control transfer */
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TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
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@@ -347,41 +362,60 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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return true;
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}
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-void dcd_edpt_close_all (uint8_t rhport)
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+void dcd_edpt_close_all(uint8_t rhport)
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{
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(void) rhport;
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- // TODO implement dcd_edpt_close_all()
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+ const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
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+ NVIC_DisableIRQ(USB0_IRQn);
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+ for (unsigned i = 1; i < 16; ++i) {
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+ KHCI->ENDPOINT[i].ENDPT = 0;
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+ }
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+ if (ie) NVIC_EnableIRQ(USB0_IRQn);
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+ buffer_descriptor_t *bd = _dcd.bdt[1][0];
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+ for (unsigned i = 2; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
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+ bd->head = 0;
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+ }
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+ endpoint_state_t *ep = &_dcd.endpoint[1][0];
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+ for (unsigned i = 2; i < sizeof(_dcd.endpoint)/sizeof(*ep); ++i, ++ep) {
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+ /* Clear except the odd */
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+ ep->max_packet_size = 0;
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+ ep->length = 0;
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+ ep->remaining = 0;
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+ }
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}
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void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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- const unsigned epn = ep_addr & 0xFu;
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- const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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+ const unsigned epn = tu_edpt_number(ep_addr);
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+ const unsigned dir = tu_edpt_dir(ep_addr);
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endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
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- buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
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+ buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
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const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
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+ const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
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+ NVIC_DisableIRQ(USB0_IRQn);
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KHCI->ENDPOINT[epn].ENDPT &= ~msk;
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ep->max_packet_size = 0;
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ep->length = 0;
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ep->remaining = 0;
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- bd->head = 0;
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+ bd[0].head = 0;
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+ bd[1].head = 0;
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+ if (ie) NVIC_EnableIRQ(USB0_IRQn);
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
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{
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(void) rhport;
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- NVIC_DisableIRQ(USB0_IRQn);
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- const unsigned epn = ep_addr & 0xFu;
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- const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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+ const unsigned epn = tu_edpt_number(ep_addr);
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+ const unsigned dir = tu_edpt_dir(ep_addr);
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endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
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buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
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+ TU_ASSERT(0 == bd->own);
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+
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+ const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
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+ NVIC_DisableIRQ(USB0_IRQn);
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- if (bd->own) {
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- TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
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- return false; /* The last transfer has not completed */
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- }
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ep->length = total_bytes;
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ep->remaining = total_bytes;
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@@ -394,42 +428,69 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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next->addr = buffer + mps;
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next->own = 1;
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}
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- bd->bc = total_bytes >= mps ? mps: total_bytes;
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- bd->addr = buffer;
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+ bd->bc = total_bytes >= mps ? mps: total_bytes;
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+ bd->addr = buffer;
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__DSB();
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- bd->own = 1; /* the own bit must set after addr */
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- NVIC_EnableIRQ(USB0_IRQn);
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+ bd->own = 1; /* This bit must be set last */
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+
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+ if (ie) NVIC_EnableIRQ(USB0_IRQn);
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return true;
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}
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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- const unsigned epn = ep_addr & 0xFu;
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+ const unsigned epn = tu_edpt_number(ep_addr);
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+
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if (0 == epn) {
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KHCI->ENDPOINT[epn].ENDPT |= USB_ENDPT_EPSTALL_MASK;
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} else {
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- const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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- buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
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- bd[0].bdt_stall = 1;
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- bd[1].bdt_stall = 1;
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+ const unsigned dir = tu_edpt_dir(ep_addr);
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+ const unsigned odd = _dcd.endpoint[epn][dir].odd;
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+ buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][odd];
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+ TU_ASSERT(0 == bd->own,);
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+
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+ const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
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+ NVIC_DisableIRQ(USB0_IRQn);
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+
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+ bd->bdt_stall = 1;
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+ __DSB();
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+ bd->own = 1; /* This bit must be set last */
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+
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+ if (ie) NVIC_EnableIRQ(USB0_IRQn);
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}
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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- const unsigned epn = ep_addr & 0xFu;
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- const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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+ const unsigned epn = tu_edpt_number(ep_addr);
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|
+ TU_VERIFY(epn,);
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|
+ const unsigned dir = tu_edpt_dir(ep_addr);
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|
|
const unsigned odd = _dcd.endpoint[epn][dir].odd;
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|
|
buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
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|
|
+ TU_VERIFY(bd[odd].own,);
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|
|
+
|
|
|
+ const unsigned ie = NVIC_GetEnableIRQ(USB0_IRQn);
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|
|
+ NVIC_DisableIRQ(USB0_IRQn);
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|
|
+
|
|
|
+ bd[odd].own = 0;
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|
|
+ __DSB();
|
|
|
+
|
|
|
+ // clear stall
|
|
|
+ bd[odd].bdt_stall = 0;
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|
|
+
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|
|
+ // Reset data toggle
|
|
|
+ bd[odd ].data = 0;
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|
|
+ bd[odd ^ 1].data = 1;
|
|
|
|
|
|
- bd[odd ^ 1].own = 0;
|
|
|
- bd[odd ^ 1].data = 1;
|
|
|
- bd[odd ^ 1].bdt_stall = 0;
|
|
|
- bd[odd].own = 0;
|
|
|
- bd[odd].data = 0;
|
|
|
- bd[odd].bdt_stall = 0;
|
|
|
+ // We already cleared this in ISR, but just clear it here to be safe
|
|
|
+ const unsigned endpt = KHCI->ENDPOINT[epn].ENDPT;
|
|
|
+ if (endpt & USB_ENDPT_EPSTALL_MASK) {
|
|
|
+ KHCI->ENDPOINT[epn].ENDPT = endpt & ~USB_ENDPT_EPSTALL_MASK;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (ie) NVIC_EnableIRQ(USB0_IRQn);
|
|
|
}
|
|
|
|
|
|
//--------------------------------------------------------------------+
|
|
|
@@ -437,48 +498,59 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
|
|
|
//--------------------------------------------------------------------+
|
|
|
void dcd_int_handler(uint8_t rhport)
|
|
|
{
|
|
|
- (void) rhport;
|
|
|
-
|
|
|
uint32_t is = KHCI->ISTAT;
|
|
|
uint32_t msk = KHCI->INTEN;
|
|
|
+
|
|
|
+ // clear non-enabled interrupts
|
|
|
KHCI->ISTAT = is & ~msk;
|
|
|
is &= msk;
|
|
|
+
|
|
|
if (is & USB_ISTAT_ERROR_MASK) {
|
|
|
/* TODO: */
|
|
|
uint32_t es = KHCI->ERRSTAT;
|
|
|
KHCI->ERRSTAT = es;
|
|
|
KHCI->ISTAT = is; /* discard any pending events */
|
|
|
- return;
|
|
|
}
|
|
|
|
|
|
if (is & USB_ISTAT_USBRST_MASK) {
|
|
|
KHCI->ISTAT = is; /* discard any pending events */
|
|
|
process_bus_reset(rhport);
|
|
|
- return;
|
|
|
}
|
|
|
+
|
|
|
if (is & USB_ISTAT_SLEEP_MASK) {
|
|
|
+ // TU_LOG2("Suspend: "); TU_LOG2_HEX(is);
|
|
|
+
|
|
|
+ // Note Host usually has extra delay after bus reset (without SOF), which could falsely
|
|
|
+ // detected as Sleep event. Though usbd has debouncing logic so we are good
|
|
|
KHCI->ISTAT = USB_ISTAT_SLEEP_MASK;
|
|
|
- process_bus_inactive(rhport);
|
|
|
- return;
|
|
|
+ process_bus_sleep(rhport);
|
|
|
}
|
|
|
+
|
|
|
+#if 0 // ISTAT_RESUME never trigger, probably for host mode ?
|
|
|
if (is & USB_ISTAT_RESUME_MASK) {
|
|
|
+ // TU_LOG2("ISTAT Resume: "); TU_LOG2_HEX(is);
|
|
|
KHCI->ISTAT = USB_ISTAT_RESUME_MASK;
|
|
|
- process_bus_active(rhport);
|
|
|
- return;
|
|
|
+ process_bus_resume(rhport);
|
|
|
}
|
|
|
+#endif
|
|
|
+
|
|
|
+ if (KHCI->USBTRC0 & USB_USBTRC0_USB_RESUME_INT_MASK) {
|
|
|
+ // TU_LOG2("USBTRC0 Resume: "); TU_LOG2_HEX(is); TU_LOG2_HEX(KHCI->USBTRC0);
|
|
|
+ process_bus_resume(rhport);
|
|
|
+ }
|
|
|
+
|
|
|
if (is & USB_ISTAT_SOFTOK_MASK) {
|
|
|
KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK;
|
|
|
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
|
|
- return;
|
|
|
}
|
|
|
+
|
|
|
if (is & USB_ISTAT_STALL_MASK) {
|
|
|
KHCI->ISTAT = USB_ISTAT_STALL_MASK;
|
|
|
process_stall(rhport);
|
|
|
- return;
|
|
|
}
|
|
|
+
|
|
|
if (is & USB_ISTAT_TOKDNE_MASK) {
|
|
|
process_tokdne(rhport);
|
|
|
- return;
|
|
|
}
|
|
|
}
|
|
|
|