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@@ -286,11 +286,13 @@ tusb_error_t dcd_init(void)
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//--------------------------------------------------------------------+
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// PIPE HELPER
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//--------------------------------------------------------------------+
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+#if 0
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static inline uint8_t edpt_pos2phy(uint8_t pos) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t edpt_pos2phy(uint8_t pos)
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{ // 0-5 --> OUT, 16-21 IN
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return (pos < DCD_QHD_MAX/2) ? (2*pos) : (2*(pos-16)+1);
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}
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+#endif
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static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint) ATTR_CONST ATTR_ALWAYS_INLINE;
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static inline uint8_t edpt_phy2pos(uint8_t physical_endpoint)
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@@ -546,29 +548,30 @@ void dcd_isr(uint8_t coreid)
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{
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LPC_USB0_Type* const lpc_usb = LPC_USB[coreid];
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- uint32_t const int_status = lpc_usb->USBSTS_D & lpc_usb->USBINTR_D;
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- lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
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-
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- if (int_status == 0) return; // disabled interrupt sources
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-
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- if (int_status & INT_MASK_RESET)
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- {
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- bus_reset(coreid);
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- usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_RESET);
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- }
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-
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- if (int_status & INT_MASK_SUSPEND)
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- {
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- if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
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- { // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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- if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
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- {
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- usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_SUSPENDED);
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- }
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- }
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- }
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-
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- // TODO disconnection does not generate interrupt !!!!!!
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+ uint32_t const int_enable = lpc_usb->USBINTR_D;
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+ uint32_t const int_status = lpc_usb->USBSTS_D & int_enable;
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+ lpc_usb->USBSTS_D = int_status; // Acknowledge handled interrupt
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+
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+ if (int_status == 0) return;// disabled interrupt sources
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+
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+ if (int_status & INT_MASK_RESET)
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+ {
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+ bus_reset(coreid);
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+ usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_RESET);
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+ }
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+
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+ if (int_status & INT_MASK_SUSPEND)
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+ {
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+ if (lpc_usb->PORTSC1_D & PORTSC_SUSPEND_MASK)
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+ { // Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration.
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+ if ((lpc_usb->DEVICEADDR >> 25) & 0x0f)
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+ {
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+ usbd_dcd_bus_event_isr(0, USBD_BUS_EVENT_SUSPENDED);
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+ }
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+ }
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+ }
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+
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+ // TODO disconnection does not generate interrupt !!!!!!
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// if (int_status & INT_MASK_PORT_CHANGE)
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// {
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// if ( !(lpc_usb->PORTSC1_D & PORTSC_CURRENT_CONNECT_STATUS_MASK) )
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@@ -577,47 +580,47 @@ void dcd_isr(uint8_t coreid)
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// }
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// }
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- if (int_status & INT_MASK_USB)
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- {
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- uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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- lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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-
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- dcd_data_t* const p_dcd = dcd_data_ptr[coreid];
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-
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- //------------- Set up Received -------------//
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- if (lpc_usb->ENDPTSETUPSTAT)
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- { // 23.10.10.2 Operational model for setup transfers
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- tusb_control_request_t control_request = p_dcd->qhd[0].setup_request;
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- lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT; // acknowledge
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-
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- usbd_setup_received_isr(coreid, &control_request);
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- }
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- //------------- Control Request Completed -------------//
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- else if ( edpt_complete & 0x03 )
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- { // only either of Endpoint Control is set with interrupt on complete flag
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- endpoint_handle_t edpt_hdl =
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+ if (int_status & INT_MASK_USB)
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+ {
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+ uint32_t const edpt_complete = lpc_usb->ENDPTCOMPLETE;
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+ lpc_usb->ENDPTCOMPLETE = edpt_complete; // acknowledge
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+
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+ dcd_data_t* const p_dcd = dcd_data_ptr[coreid];
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+
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+ //------------- Set up Received -------------//
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+ if (lpc_usb->ENDPTSETUPSTAT)
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+ { // 23.10.10.2 Operational model for setup transfers
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+ tusb_control_request_t control_request = p_dcd->qhd[0].setup_request;
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+ lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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+
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+ usbd_setup_received_isr(coreid, &control_request);
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+ }
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+ //------------- Control Request Completed -------------//
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+ else if ( edpt_complete & 0x03 )
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+ { // only either of Endpoint Control is set with interrupt on complete flag
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+ endpoint_handle_t edpt_hdl =
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{
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- .coreid = coreid,
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- .index = 0,
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- .class_code = 0
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+ .coreid = coreid,
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+ .index = 0,
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+ .class_code = 0
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};
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- dcd_qtd_t volatile * const p_qtd = &p_dcd->qhd[ (edpt_complete & BIT_(0)) ? 0 : 1 ].qtd_overlay;
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- tusb_event_t event = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? TUSB_EVENT_XFER_ERROR : TUSB_EVENT_XFER_COMPLETE;
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+ dcd_qtd_t volatile * const p_qtd = &p_dcd->qhd[ (edpt_complete & BIT_(0)) ? 0 : 1 ].qtd_overlay;
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+ tusb_event_t event = ( p_qtd->xact_err || p_qtd->halted || p_qtd->buffer_err ) ? TUSB_EVENT_XFER_ERROR : TUSB_EVENT_XFER_COMPLETE;
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- usbd_xfer_isr(edpt_hdl, event, 0); // TODO xferred bytes for control xfer is not needed yet !!!!
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- }
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+ usbd_xfer_isr(edpt_hdl, event, 0); // TODO xferred bytes for control xfer is not needed yet !!!!
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+ }
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- //------------- Transfer Complete -------------//
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- if ( edpt_complete & ~(0x03UL) )
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- {
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- xfer_complete_isr(coreid, edpt_complete);
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- }
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- }
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+ //------------- Transfer Complete -------------//
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+ if ( edpt_complete & ~(0x03UL) )
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+ {
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+ xfer_complete_isr(coreid, edpt_complete);
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+ }
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+ }
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- if (int_status & INT_MASK_SOF) { }
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- if (int_status & INT_MASK_NAK) { }
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- if (int_status & INT_MASK_ERROR) ASSERT(false, VOID_RETURN);
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+ if (int_status & INT_MASK_SOF) {}
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+ if (int_status & INT_MASK_NAK) {}
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+ if (int_status & INT_MASK_ERROR) ASSERT(false, VOID_RETURN);
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}
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//--------------------------------------------------------------------+
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