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@@ -1,25 +1,39 @@
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/**************************************************************************//**
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* @file core_cmInstr.h
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* @brief CMSIS Cortex-M Core Instruction Access Header File
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- * @version V3.01
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- * @date 06. March 2012
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+ * @version V3.20
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+ * @date 05. March 2013
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*
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* @note
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- * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
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- *
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- * @par
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- * ARM Limited (ARM) is supplying this software for use with Cortex-M
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- * processor based microcontrollers. This file can be freely distributed
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- * within development tools that are supporting such ARM based processors.
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- *
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- * @par
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- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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+/* Copyright (c) 2009 - 2013 ARM LIMITED
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+
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+ All rights reserved.
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+ Redistribution and use in source and binary forms, with or without
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+ modification, are permitted provided that the following conditions are met:
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+ - Redistributions of source code must retain the above copyright
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+ notice, this list of conditions and the following disclaimer.
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+ - Redistributions in binary form must reproduce the above copyright
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+ notice, this list of conditions and the following disclaimer in the
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+ documentation and/or other materials provided with the distribution.
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+ - Neither the name of ARM nor the names of its contributors may be used
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+ to endorse or promote products derived from this software without
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+ specific prior written permission.
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+ *
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+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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+ POSSIBILITY OF SUCH DAMAGE.
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+ ---------------------------------------------------------------------------*/
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+
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#ifndef __CORE_CMINSTR_H
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#define __CORE_CMINSTR_H
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@@ -111,12 +125,13 @@
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\param [in] value Value to reverse
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\return Reversed value
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*/
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+#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
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{
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rev16 r0, r0
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bx lr
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}
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-
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+#endif
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/** \brief Reverse byte order in signed short value
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@@ -125,11 +140,13 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
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\param [in] value Value to reverse
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\return Reversed value
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*/
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+#ifndef __NO_EMBEDDED_ASM
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__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
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{
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revsh r0, r0
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bx lr
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}
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+#endif
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/** \brief Rotate Right in unsigned value (32 bit)
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@@ -143,6 +160,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
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#define __ROR __ror
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+/** \brief Breakpoint
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+
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+ This function causes the processor to enter Debug state.
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+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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+
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+ \param [in] value is ignored by the processor.
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+ If required, a debugger can use it to store additional information about the breakpoint.
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+ */
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+#define __BKPT(value) __breakpoint(value)
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+
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+
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#if (__CORTEX_M >= 0x03)
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/** \brief Reverse bit order of value
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@@ -279,6 +307,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
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#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
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/* GNU gcc specific functions */
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+/* Define macros for porting to both thumb1 and thumb2.
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+ * For thumb1, use low register (r0-r7), specified by constrant "l"
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+ * Otherwise, use general registers, specified by constrant "r" */
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+#if defined (__thumb__) && !defined (__thumb2__)
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+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
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+#define __CMSIS_GCC_USE_REG(r) "l" (r)
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+#else
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+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
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+#define __CMSIS_GCC_USE_REG(r) "r" (r)
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+#endif
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+
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/** \brief No Operation
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No Operation does nothing. This instruction can be used for code alignment purposes.
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@@ -364,10 +403,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
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{
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+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
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+ return __builtin_bswap32(value);
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+#else
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uint32_t result;
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- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
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+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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+#endif
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}
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@@ -382,7 +425,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
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{
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uint32_t result;
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- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
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+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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}
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@@ -396,10 +439,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
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{
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+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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+ return (short)__builtin_bswap16(value);
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+#else
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uint32_t result;
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- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
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+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return(result);
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+#endif
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}
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@@ -413,12 +460,21 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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-
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- __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
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- return(op1);
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+ return (op1 >> op2) | (op1 << (32 - op2));
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}
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+/** \brief Breakpoint
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+
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+ This function causes the processor to enter Debug state.
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+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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+
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+ \param [in] value is ignored by the processor.
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+ If required, a debugger can use it to store additional information about the breakpoint.
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+ */
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+#define __BKPT(value) __ASM volatile ("bkpt "#value)
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+
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+
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#if (__CORTEX_M >= 0x03)
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/** \brief Reverse bit order of value
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@@ -446,9 +502,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
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{
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- uint8_t result;
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+ uint32_t result;
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- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
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+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
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+#else
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+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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+ accepted by assembler. So has to use following less efficient pattern.
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+ */
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+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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+#endif
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return(result);
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}
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@@ -462,9 +525,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
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{
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- uint16_t result;
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+ uint32_t result;
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- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
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+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
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+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
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+#else
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+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
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+ accepted by assembler. So has to use following less efficient pattern.
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+ */
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+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
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+#endif
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return(result);
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}
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@@ -480,7 +550,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
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{
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uint32_t result;
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- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
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+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
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return(result);
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}
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@@ -498,7 +568,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
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{
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uint32_t result;
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- __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
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+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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return(result);
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}
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@@ -516,7 +586,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
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{
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uint32_t result;
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- __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
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+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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return(result);
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}
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@@ -534,7 +604,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
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{
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uint32_t result;
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- __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
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+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
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return(result);
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}
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@@ -546,7 +616,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
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{
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- __ASM volatile ("clrex");
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+ __ASM volatile ("clrex" ::: "memory");
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}
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@@ -591,7 +661,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
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*/
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__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
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{
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- uint8_t result;
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+ uint32_t result;
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__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
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return(result);
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hathach