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@@ -232,6 +232,7 @@ void hcd_isr(uint8_t hostid)
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if (int_status & EHCI_INT_MASK_ERROR)
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if (int_status & EHCI_INT_MASK_ERROR)
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{
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{
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// TODO something going wrong
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// TODO something going wrong
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+ ASM_BREAKPOINT;
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}
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}
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//------------- some QTD/SITD/ITD with IOC set is completed -------------//
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//------------- some QTD/SITD/ITD with IOC set is completed -------------//
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@@ -247,10 +248,8 @@ void hcd_isr(uint8_t hostid)
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if (int_status & EHCI_INT_MASK_PORT_CHANGE)
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if (int_status & EHCI_INT_MASK_PORT_CHANGE)
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{
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{
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- printf("%s %d\n", __PRETTY_FUNCTION__, __LINE__);
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if (regs->portsc_bit.connect_status_change)
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if (regs->portsc_bit.connect_status_change)
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{
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{
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- printf("%s %d\n", __PRETTY_FUNCTION__, __LINE__);
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port_connect_status_isr(hostid);
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port_connect_status_isr(hostid);
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}
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}
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@@ -278,11 +277,10 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
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regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status
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regs->usb_sts = EHCI_INT_MASK_ALL; // 2. clear all status
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regs->usb_int_enable =
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regs->usb_int_enable =
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EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE
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EHCI_INT_MASK_ERROR | EHCI_INT_MASK_PORT_CHANGE
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- | EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_ASYNC
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#if EHCI_PERIODIC_LIST
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#if EHCI_PERIODIC_LIST
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| EHCI_INT_MASK_NXP_PERIODIC
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| EHCI_INT_MASK_NXP_PERIODIC
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#endif
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#endif
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- ;
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+ | EHCI_INT_MASK_ASYNC_ADVANCE | EHCI_INT_MASK_NXP_ASYNC;
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//------------- Asynchronous List -------------//
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//------------- Asynchronous List -------------//
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ehci_qhd_t * const async_head = get_async_head(hostid);
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ehci_qhd_t * const async_head = get_async_head(hostid);
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@@ -292,6 +290,7 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
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async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
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async_head->next.type = EHCI_QUEUE_ELEMENT_QHD;
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async_head->head_list_flag = 1;
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async_head->head_list_flag = 1;
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async_head->qtd_overlay.halted = 1; // inactive most of time
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async_head->qtd_overlay.halted = 1; // inactive most of time
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+ async_head->qtd_overlay.next.terminate = 1; // TODO removed if verified
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regs->async_list_base = (uint32_t) async_head;
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regs->async_list_base = (uint32_t) async_head;
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@@ -321,7 +320,7 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
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//------------- USB CMD Register -------------//
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//------------- USB CMD Register -------------//
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- regs->usb_cmd = BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
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+ regs->usb_cmd |= BIT_(EHCI_USBCMD_POS_RUN_STOP) | BIT_(EHCI_USBCMD_POS_ASYNC_ENABLE)
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#if EHCI_PERIODIC_LIST
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#if EHCI_PERIODIC_LIST
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| BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE)
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| BIT_(EHCI_USBCMD_POS_PERIOD_ENABLE)
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#endif
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#endif
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@@ -330,6 +329,8 @@ tusb_error_t hcd_controller_init(uint8_t hostid)
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//------------- ConfigFlag Register (skip) -------------//
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//------------- ConfigFlag Register (skip) -------------//
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+ regs->portsc_bit.port_power = 1; // enable port power
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+
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return TUSB_ERROR_NONE;
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return TUSB_ERROR_NONE;
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}
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}
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