clean up ehci, support only 1 controller

src/host/ehci/ehci.c

@@ -209,8 +209,8 @@ static bool ehci_init(uint8_t hostid)
 
   for(uint32_t i=0; i<4; i++)
   {
-    ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ][i].interrupt_smask    = 1; // queue head in period list must have smask non-zero
-    ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ][i].qtd_overlay.halted = 1; // dummy node, always inactive
+    ehci_data.period_head_arr[i].interrupt_smask    = 1; // queue head in period list must have smask non-zero
+    ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
   }
 
   ehci_link_t * const framelist  = get_period_frame_list(hostid);
@@ -873,27 +873,16 @@ static inline ehci_link_t* get_period_frame_list(uint8_t hostid)
 }
 #endif
 
-static inline uint8_t hostid_to_data_idx(uint8_t hostid)
-{
-  #if (CONTROLLER_HOST_NUMBER == 1) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
-    (void) hostid;
-    return 0;
-  #else
-    return hostid;
-  #endif
-}
-
 //------------- queue head helper -------------//
 static inline ehci_qhd_t* get_async_head(uint8_t hostid)
 {
-  return &ehci_data.async_head[ hostid_to_data_idx(hostid) ];
+  return &ehci_data.async_head;
 }
 
 #if EHCI_PERIODIC_LIST // TODO refractor/group this together
 static inline ehci_link_t* get_period_head(uint8_t hostid, uint8_t interval_ms)
 {
-  return (ehci_link_t*) (&ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ]
-                                                    [ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ] );
+  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ];
 }
 #endif
 

src/host/ehci/ehci.h

@@ -450,12 +450,12 @@ typedef volatile struct {
 //--------------------------------------------------------------------+
 typedef struct {
   //------------- Static Async/Period List Head, Each for one controller -------------//
-  ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
+  ehci_qhd_t async_head; /// head qhd of async list, also is used as control endpoint for address 0
 
 #if EHCI_PERIODIC_LIST
   // for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
   // [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
-  ehci_qhd_t period_head_arr[CONTROLLER_HOST_NUMBER][4];
+  ehci_qhd_t period_head_arr[4];
 #endif
 
   //------------- Data for Address 0 (use async head as its queue head) -------------//

src/host/hcd.h

@@ -113,8 +113,6 @@ static inline bool pipehandle_is_equal(pipe_handle_t x, pipe_handle_t y)
 // USBH-HCD API
 //--------------------------------------------------------------------+
 bool hcd_init(void);
-void hal_hcd_isr(uint8_t hostid);
-
 void hcd_int_enable (uint8_t rhport);
 void hcd_int_disable(uint8_t rhport);
 
@@ -128,9 +126,8 @@ void hcd_event_handler(hcd_event_t const* event, bool in_isr);
 //--------------------------------------------------------------------+
 bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const* ep_desc);
 bool hcd_edpt_close(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr);
-bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
-
 bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
 
 //--------------------------------------------------------------------+
 // PIPE API

src/portable/nxp/lpc18_43/hal_lpc18_43.c

@@ -42,7 +42,8 @@
 
 #include "chip.h"
 
-void hal_dcd_isr(uint8_t rhport);
+extern void hal_dcd_isr(uint8_t rhport);
+extern void hal_hcd_isr(uint8_t hostid);
 
 #if CFG_TUSB_RHPORT0_MODE
 void USB0_IRQHandler(void)