seperate control xfer to 3 tds for ohci

- ohci only work with 1st transfer with specific timing. TODO fix it
later

src/host/ohci/ohci.c

@@ -328,7 +328,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     p_data->index       = dev_addr;
     p_data->pid         = dir ? OHCI_PID_IN : OHCI_PID_OUT;
     p_data->data_toggle = BIN8(11); // DATA1
-
     p_data->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
 
     p_ed->td_head.address = (uint32_t) p_data;
@@ -336,7 +335,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *
     OHCI_REG->command_status_bit.control_list_filled = 1;
   }
 
-  return false;
+  return true;
 }
 
 tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
@@ -356,48 +355,48 @@ tusb_error_t  hcd_pipe_control_open(uint8_t dev_addr, uint8_t max_packet_size)
   return TUSB_ERROR_NONE;
 }
 
-bool  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
-{
-  ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
-
-  ohci_gtd_t *p_setup      = &ohci_data.control[dev_addr].gtd[0];
-  ohci_gtd_t *p_data       = p_setup + 1;
-  ohci_gtd_t *p_status     = p_setup + 2;
-
-  //------------- SETUP Phase -------------//
-  gtd_init(p_setup, (void*) p_request, 8);
-  p_setup->index       = dev_addr;
-  p_setup->pid         = OHCI_PID_SETUP;
-  p_setup->data_toggle = BIN8(10); // DATA0
-  p_setup->next_td     = (uint32_t) p_data;
-
-  //------------- DATA Phase -------------//
-  if (p_request->wLength > 0)
-  {
-    gtd_init(p_data, data, p_request->wLength);
-    p_data->index       = dev_addr;
-    p_data->pid         = p_request->bmRequestType_bit.direction ? OHCI_PID_IN : OHCI_PID_OUT;
-    p_data->data_toggle = BIN8(11); // DATA1
-  }else
-  {
-    p_data = p_setup;
-  }
-  p_data->next_td = (uint32_t) p_status;
-
-  //------------- STATUS Phase -------------//
-  gtd_init(p_status, NULL, 0); // zero-length data
-  p_status->index           = dev_addr;
-  p_status->pid             = p_request->bmRequestType_bit.direction ? OHCI_PID_OUT : OHCI_PID_IN; // reverse direction of data phase
-  p_status->data_toggle     = BIN8(11); // DATA1
-  p_status->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
-
-  //------------- Attach TDs list to Control Endpoint -------------//
-  p_ed->td_head.address = (uint32_t) p_setup;
-
-  OHCI_REG->command_status_bit.control_list_filled = 1;
-
-  return true;
-}
+//bool  hcd_pipe_control_xfer(uint8_t dev_addr, tusb_control_request_t const * p_request, uint8_t data[])
+//{
+//  ohci_ed_t* const p_ed = &ohci_data.control[dev_addr].ed;
+//
+//  ohci_gtd_t *p_setup      = &ohci_data.control[dev_addr].gtd[0];
+//  ohci_gtd_t *p_data       = p_setup + 1;
+//  ohci_gtd_t *p_status     = p_setup + 2;
+//
+//  //------------- SETUP Phase -------------//
+//  gtd_init(p_setup, (void*) p_request, 8);
+//  p_setup->index       = dev_addr;
+//  p_setup->pid         = OHCI_PID_SETUP;
+//  p_setup->data_toggle = BIN8(10); // DATA0
+//  p_setup->next_td     = (uint32_t) p_data;
+//
+//  //------------- DATA Phase -------------//
+//  if (p_request->wLength > 0)
+//  {
+//    gtd_init(p_data, data, p_request->wLength);
+//    p_data->index       = dev_addr;
+//    p_data->pid         = p_request->bmRequestType_bit.direction ? OHCI_PID_IN : OHCI_PID_OUT;
+//    p_data->data_toggle = BIN8(11); // DATA1
+//  }else
+//  {
+//    p_data = p_setup;
+//  }
+//  p_data->next_td = (uint32_t) p_status;
+//
+//  //------------- STATUS Phase -------------//
+//  gtd_init(p_status, NULL, 0); // zero-length data
+//  p_status->index           = dev_addr;
+//  p_status->pid             = p_request->bmRequestType_bit.direction ? OHCI_PID_OUT : OHCI_PID_IN; // reverse direction of data phase
+//  p_status->data_toggle     = BIN8(11); // DATA1
+//  p_status->delay_interrupt = OHCI_INT_ON_COMPLETE_YES;
+//
+//  //------------- Attach TDs list to Control Endpoint -------------//
+//  p_ed->td_head.address = (uint32_t) p_setup;
+//
+//  OHCI_REG->command_status_bit.control_list_filled = 1;
+//
+//  return true;
+//}
 
 tusb_error_t  hcd_pipe_control_close(uint8_t dev_addr)
 {

src/host/usbh.c

@@ -200,10 +200,6 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8
   dev->control.request = *request;
   dev->control.pipe_status = 0;
 
-#if 0
-  TU_ASSERT(hcd_pipe_control_xfer(dev_addr, &dev->control.request, data));
-  TU_ASSERT(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
-#else
   // Setup Stage
   hcd_setup_send(rhport, dev_addr, (uint8_t*) &dev->control.request);
   TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
@@ -218,7 +214,6 @@ bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8
   // Status : data toggle is always 1
   hcd_edpt_xfer(rhport, dev_addr, edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
   TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL));
-#endif
 
   osal_mutex_unlock(dev->control.mutex_hdl);
 
@@ -395,8 +390,14 @@ void usbh_hcd_rhport_unplugged_isr(uint8_t hostid)
 bool enum_task(hcd_event_t* event)
 {
   enum {
+#if 1
+    // FIXME ohci LPC1769 xpresso + debugging to have 1st control xfer to work, some kind of timing or ohci driver issue !!!
+    POWER_STABLE_DELAY = 100,
+    RESET_DELAY        = 500
+#else
     POWER_STABLE_DELAY = 500,
-    RESET_DELAY        = 200 // USB specs say only 50ms but many devices require much longer
+    RESET_DELAY        = 200, // USB specs say only 50ms but many devices require much longer
+#endif
   };
 
   // for OSAL_NONE local variable won't retain value after blocking service sem_wait/queue_recv