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@@ -242,33 +242,24 @@ bool tusb_dcd_control_xfer(uint8_t port, tusb_dir_t dir, uint8_t * p_buffer, uin
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LPC_USB0_Type* const lpc_usb = LPC_USB[port];
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dcd_data_t* const p_dcd = dcd_data_ptr[port];
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- // determine Endpoint where Data & Status phase occurred (IN or OUT)
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- uint8_t const ep_data = (dir == TUSB_DIR_IN) ? 1 : 0;
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- uint8_t const ep_status = 1 - ep_data;
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+ uint8_t const ep_phy = (dir == TUSB_DIR_IN) ? 1 : 0;
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- while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {} // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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-// while(p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active) {}; // wait until previous device request is completed TODO add timeout
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+ dcd_qhd_t* qhd = &p_dcd->qhd[ep_phy];
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- VERIFY( !(p_dcd->qhd[0].qtd_overlay.active || p_dcd->qhd[1].qtd_overlay.active) );
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+ // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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+ while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {}
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- //------------- Data Phase -------------//
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- if (length > 0)
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- {
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- dcd_qtd_t* p_qtd_data = &p_dcd->qtd[0];
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- qtd_init(p_qtd_data, p_buffer, length);
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- p_dcd->qhd[ep_data].qtd_overlay.next = (uint32_t) p_qtd_data;
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+ VERIFY( !qhd->qtd_overlay.active );
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- lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_data));
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- }
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+ dcd_qtd_t* qtd = &p_dcd->qtd[0];
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+ qtd_init(qtd, p_buffer, length);
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- //------------- Status Phase -------------//
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- dcd_qtd_t* p_qtd_status = &p_dcd->qtd[1];
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- qtd_init(p_qtd_status, NULL, 0); // zero length xfer
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- p_qtd_status->int_on_complete = int_on_complete ? 1 : 0;
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+ // skip xfer complete for Status
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+ qtd->int_on_complete = (length > 0 ? 1 : 0);
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- p_dcd->qhd[ep_status].qtd_overlay.next = (uint32_t) p_qtd_status;
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+ qhd->qtd_overlay.next = (uint32_t) qtd;
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- lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_status));
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+ lpc_usb->ENDPTPRIME = BIT_(edpt_phy2pos(ep_phy));
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return true;
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}
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@@ -465,13 +456,14 @@ void hal_dcd_isr(uint8_t port)
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//------------- Set up Received -------------//
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if (lpc_usb->ENDPTSETUPSTAT)
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- { // 23.10.10.2 Operational model for setup transfers
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+ {
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+ // 23.10.10.2 Operational model for setup transfers
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lpc_usb->ENDPTSETUPSTAT = lpc_usb->ENDPTSETUPSTAT;// acknowledge
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tusb_dcd_setup_received(port, (uint8_t*) &p_dcd->qhd[0].setup_request);
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}
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//------------- Control Request Completed -------------//
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- else if ( edpt_complete & 0x03 )
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+ else if ( edpt_complete & ( BIT_(0) | BIT_(16)) )
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{
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for(uint8_t ep_idx = 0; ep_idx < 2; ep_idx++)
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{
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@@ -490,7 +482,7 @@ void hal_dcd_isr(uint8_t port)
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}
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//------------- Transfer Complete -------------//
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- if ( edpt_complete & ~(0x03UL) )
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+ if ( edpt_complete & ~(BIT_(0) | BIT_(16)) )
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{
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xfer_complete_isr(port, edpt_complete);
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}
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