ehci_controller_fake.c 6.4 KB

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  1. /*
  2. * The MIT License (MIT)
  3. *
  4. * Copyright (c) 2018, hathach (tinyusb.org)
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a copy
  7. * of this software and associated documentation files (the "Software"), to deal
  8. * in the Software without restriction, including without limitation the rights
  9. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10. * copies of the Software, and to permit persons to whom the Software is
  11. * furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19. * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22. * THE SOFTWARE.
  23. *
  24. * This file is part of the TinyUSB stack.
  25. */
  26. //--------------------------------------------------------------------+
  27. // INCLUDE
  28. //--------------------------------------------------------------------+
  29. #include "unity.h"
  30. #include "common/common.h"
  31. #include "hal.h"
  32. #include "usbh_hcd.h"
  33. #include "ehci.h"
  34. #include "ehci_controller_fake.h"
  35. //--------------------------------------------------------------------+
  36. // MACRO CONSTANT TYPEDEF
  37. //--------------------------------------------------------------------+
  38. LPC_USB0_Type lpc_usb0;
  39. LPC_USB1_Type lpc_usb1;
  40. extern usbh_device_t _usbh_devices[CFG_TUSB_HOST_DEVICE_MAX+1];
  41. //--------------------------------------------------------------------+
  42. // IMPLEMENTATION
  43. //--------------------------------------------------------------------+
  44. void ehci_controller_init(void)
  45. {
  46. tu_memclr(&lpc_usb0, sizeof(LPC_USB0_Type));
  47. tu_memclr(&lpc_usb1, sizeof(LPC_USB1_Type));
  48. }
  49. void ehci_controller_control_xfer_proceed(uint8_t dev_addr, uint8_t p_data[])
  50. {
  51. ehci_registers_t* const regs = get_operational_register( _usbh_devices[dev_addr].rhport );
  52. ehci_qhd_t * p_qhd = get_control_qhd(dev_addr);
  53. ehci_qtd_t * p_qtd_setup = get_control_qtds(dev_addr);
  54. ehci_qtd_t * p_qtd_data = p_qtd_setup + 1;
  55. ehci_qtd_t * p_qtd_status = p_qtd_setup + 2;
  56. tusb_control_request_t const *p_request = (tusb_control_request_t *) p_qtd_setup->buffer[0];
  57. if (p_request->wLength > 0 && p_request->bmRequestType_bit.direction == TUSB_DIR_DEV_TO_HOST)
  58. {
  59. memcpy(p_qtd_data, p_data, p_request->wLength);
  60. }
  61. //------------- retire all QTDs -------------//
  62. p_qtd_setup->active = p_qtd_data->active = p_qtd_status->active = 0;
  63. p_qhd->qtd_overlay = *p_qtd_status;
  64. regs->usb_sts = EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC;
  65. hcd_isr( _usbh_devices[dev_addr].rhport );
  66. }
  67. void complete_qtd_in_qhd(ehci_qhd_t *p_qhd)
  68. {
  69. if ( !p_qhd->qtd_overlay.halted )
  70. {
  71. while(!p_qhd->qtd_overlay.next.terminate)
  72. {
  73. ehci_qtd_t* p_qtd = (ehci_qtd_t*) tu_align32(p_qhd->qtd_overlay.next.address);
  74. p_qtd->active = 0;
  75. p_qtd->total_bytes = 0;
  76. p_qhd->qtd_overlay = *p_qtd;
  77. }
  78. }
  79. }
  80. bool complete_all_qtd_in_async(ehci_qhd_t *head)
  81. {
  82. ehci_qhd_t *p_qhd = head;
  83. do
  84. {
  85. complete_qtd_in_qhd(p_qhd);
  86. p_qhd = (ehci_qhd_t*) tu_align32(p_qhd->next.address);
  87. }while(p_qhd != head); // stop if loop around
  88. return true;
  89. }
  90. bool complete_all_qtd_in_period(ehci_link_t *head)
  91. {
  92. while(!head->terminate)
  93. {
  94. uint32_t queue_type = head->type;
  95. head = (ehci_link_t*) tu_align32(head->address);
  96. if ( queue_type == EHCI_QUEUE_ELEMENT_QHD)
  97. {
  98. complete_qtd_in_qhd( (ehci_qhd_t*) head );
  99. }
  100. }
  101. return true;
  102. }
  103. void ehci_controller_run(uint8_t hostid)
  104. {
  105. //------------- Async List -------------//
  106. ehci_registers_t* const regs = get_operational_register(hostid);
  107. complete_all_qtd_in_async((ehci_qhd_t*) regs->async_list_base);
  108. //------------- Period List -------------//
  109. for(uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
  110. {
  111. complete_all_qtd_in_period( get_period_head(hostid, i) );
  112. }
  113. regs->usb_sts = EHCI_INT_MASK_NXP_ASYNC | EHCI_INT_MASK_NXP_PERIODIC;
  114. hcd_isr(hostid);
  115. }
  116. void complete_1st_qtd_with_error(ehci_qhd_t* p_qhd, bool halted, bool xact_err)
  117. {
  118. if ( !p_qhd->qtd_overlay.halted )
  119. {
  120. if(!p_qhd->qtd_overlay.next.terminate) // TODO add active check
  121. {
  122. ehci_qtd_t* p_qtd = (ehci_qtd_t*) tu_align32(p_qhd->qtd_overlay.next.address);
  123. p_qtd->active = 0;
  124. p_qtd->halted = halted ? 1 : 0;
  125. p_qtd->xact_err = xact_err ? 1 : 0;
  126. p_qhd->qtd_overlay = *p_qtd;
  127. }
  128. }
  129. }
  130. void complete_list_with_error(uint8_t hostid, bool halted, bool xact_err)
  131. {
  132. //------------- Async List -------------//
  133. ehci_registers_t* const regs = get_operational_register(hostid);
  134. ehci_qhd_t *p_qhd = (ehci_qhd_t*) regs->async_list_base;
  135. do
  136. {
  137. complete_1st_qtd_with_error(p_qhd, halted, xact_err);
  138. p_qhd = (ehci_qhd_t*) tu_align32(p_qhd->next.address);
  139. }while(p_qhd != get_async_head(hostid)); // stop if loop around
  140. //------------- Period List -------------//
  141. for(uint8_t i=1; i <= EHCI_FRAMELIST_SIZE; i *= 2)
  142. {
  143. ehci_link_t *head = get_period_head(hostid, i);
  144. while(!head->terminate)
  145. {
  146. uint32_t queue_type = head->type;
  147. head = (ehci_link_t*) tu_align32(head->address);
  148. if ( queue_type == EHCI_QUEUE_ELEMENT_QHD)
  149. {
  150. complete_1st_qtd_with_error((ehci_qhd_t*) head, halted, xact_err);
  151. }
  152. }
  153. }
  154. regs->usb_sts = EHCI_INT_MASK_ERROR;
  155. hcd_isr(hostid);
  156. }
  157. void ehci_controller_run_stall(uint8_t hostid)
  158. {
  159. complete_list_with_error(hostid, true, false);
  160. }
  161. void ehci_controller_run_error(uint8_t hostid)
  162. {
  163. complete_list_with_error(hostid, true, true);
  164. }
  165. void ehci_controller_device_plug(uint8_t hostid, tusb_speed_t speed)
  166. {
  167. ehci_registers_t* const regs = get_operational_register(hostid);
  168. regs->usb_sts_bit.port_change_detect = 1;
  169. regs->portsc_bit.connect_status_change = 1;
  170. regs->portsc_bit.current_connect_status = 1;
  171. regs->portsc_bit.nxp_port_speed = speed;
  172. hcd_isr(hostid);
  173. }
  174. void ehci_controller_device_unplug(uint8_t hostid)
  175. {
  176. ehci_registers_t* const regs = get_operational_register(hostid);
  177. regs->usb_sts_bit.port_change_detect = 1;
  178. regs->portsc_bit.connect_status_change = 1;
  179. regs->portsc_bit.current_connect_status = 0;
  180. hcd_isr(hostid);
  181. }