bsp/nxp：Separate nxp_lpc library (#10265)

bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.c

@@ -1,784 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.c
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
-  clrex
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t  __get_BASEPRI(void)
-{
-  mrs r0, basepri
-  bx lr
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
-  msr basepri, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t  __get_FAULTMASK(void)
-{
-  mrs r0, faultmask
-  bx lr
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
-  msr faultmask, r0
-  bx lr
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  __ASM("rev16 r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-  __ASM("bx lr"); 
-}
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-  __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, psp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, msp\n\t" 
-                  "MOV r0, %0 \n\t"
-                  "BX  lr     \n\t"  : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n\t"
-                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
-  uint32_t result=0;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
-  uint32_t result=0;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result=0;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
-    uint8_t result=0;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
-    uint16_t result=0;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
-    uint32_t result=0;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
-   uint32_t result=0;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CM3/CoreSupport/core_cm3.h

@@ -1,1818 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V1.30
- * @date     30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- *   - Error 10: \n
- *     register uint32_t __regBasePri         __asm("basepri"); \n
- *     Error 10: Expecting ';'
- * .
- *   - Error 530: \n
- *     return(__regBasePri); \n
- *     Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * . 
- *   - Error 550: \n
- *     __regBasePri = (basePri & 0x1ff); \n
- *     Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- *   - Error 754: \n
- *     uint32_t RESERVED0[24]; \n
- *     Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
- * .
- *   - Error 750: \n
- *     #define __CM3_CORE_H__ \n
- *     Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- *   - Error 528: \n
- *     static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- *     Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- *   - Error 751: \n
- *     } InterruptType_Type; \n
- *     Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note:  To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10  */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-    - CMSIS version number
-    - Cortex-M core registers and bitfields
-    - Cortex-M core peripheral base address
-  @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x30)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-#include <stdint.h>                           /* Include standard types */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
-  #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
-  #define     __I     volatile                /*!< defines 'read only' permissions      */
-#else
-  #define     __I     volatile const          /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
-  memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
-  @{
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                      /*!< Offset: 0x000  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];                                   
-  __IO uint32_t ICER[8];                      /*!< Offset: 0x080  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];                                    
-  __IO uint32_t ISPR[8];                      /*!< Offset: 0x100  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];                                   
-  __IO uint32_t ICPR[8];                      /*!< Offset: 0x180  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];                                   
-  __IO uint32_t IABR[8];                      /*!< Offset: 0x200  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];                                   
-  __IO uint8_t  IP[240];                      /*!< Offset: 0x300  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];                                  
-  __O  uint32_t STIR;                         /*!< Offset: 0xE00  Software Trigger Interrupt Register     */
-}  NVIC_Type;                                               
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
-  memory mapped structure for System Control Block (SCB)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                        /*!< Offset: 0x00  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                         /*!< Offset: 0x04  Interrupt Control State Register                      */
-  __IO uint32_t VTOR;                         /*!< Offset: 0x08  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                        /*!< Offset: 0x0C  Application Interrupt / Reset Control Register        */
-  __IO uint32_t SCR;                          /*!< Offset: 0x10  System Control Register                               */
-  __IO uint32_t CCR;                          /*!< Offset: 0x14  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                      /*!< Offset: 0x18  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                        /*!< Offset: 0x24  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                         /*!< Offset: 0x28  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                         /*!< Offset: 0x2C  Hard Fault Status Register                            */
-  __IO uint32_t DFSR;                         /*!< Offset: 0x30  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                        /*!< Offset: 0x34  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                         /*!< Offset: 0x38  Bus Fault Address Register                            */
-  __IO uint32_t AFSR;                         /*!< Offset: 0x3C  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                       /*!< Offset: 0x40  Processor Feature Register                            */
-  __I  uint32_t DFR;                          /*!< Offset: 0x48  Debug Feature Register                                */
-  __I  uint32_t ADR;                          /*!< Offset: 0x4C  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                      /*!< Offset: 0x50  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                      /*!< Offset: 0x60  ISA Feature Register                                  */
-} SCB_Type;                                                
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFul << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFul << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFul << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1ul << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1ul << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1ul << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1ul << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1ul << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1ul << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1ul << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFul << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1ul << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (0x1FFul << SCB_VTOR_TBLBASE_Pos)              /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1ul << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7ul << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1ul << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1ul << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1ul << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1ul << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1ul << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1ul << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1ul << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1ul << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1ul << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1ul << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1ul << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1ul << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1ul << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1ul << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1ul << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1ul << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1ul << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1ul << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1ul << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-                                     
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1ul << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1ul << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1ul << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1ul << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1ul << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1ul << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1ul << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1ul << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1ul << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1ul << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1ul << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
-  memory mapped structure for SysTick
-  @{
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                         /*!< Offset: 0x00  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                         /*!< Offset: 0x04  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                          /*!< Offset: 0x08  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                        /*!< Offset: 0x0C  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1ul << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1ul << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1ul << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1ul << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1ul << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1ul << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
-  memory mapped structure for Instrumentation Trace Macrocell (ITM)
-  @{
- */
-typedef struct
-{
-  __O  union  
-  {
-    __O  uint8_t    u8;                       /*!< Offset:       ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                      /*!< Offset:       ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                      /*!< Offset:       ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                               /*!< Offset: 0x00  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];                                 
-  __IO uint32_t TER;                          /*!< Offset:       ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];                                  
-  __IO uint32_t TPR;                          /*!< Offset:       ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];                                  
-  __IO uint32_t TCR;                          /*!< Offset:       ITM Trace Control Register                */
-       uint32_t RESERVED3[29];                                  
-  __IO uint32_t IWR;                          /*!< Offset:       ITM Integration Write Register            */
-  __IO uint32_t IRR;                          /*!< Offset:       ITM Integration Read Register             */
-  __IO uint32_t IMCR;                         /*!< Offset:       ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];                                  
-  __IO uint32_t LAR;                          /*!< Offset:       ITM Lock Access Register                  */
-  __IO uint32_t LSR;                          /*!< Offset:       ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];                                   
-  __I  uint32_t PID4;                         /*!< Offset:       ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                         /*!< Offset:       ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                         /*!< Offset:       ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                         /*!< Offset:       ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                         /*!< Offset:       ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                         /*!< Offset:       ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                         /*!< Offset:       ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                         /*!< Offset:       ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                         /*!< Offset:       ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                         /*!< Offset:       ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                         /*!< Offset:       ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                         /*!< Offset:       ITM Component  Identification Register #3 */
-} ITM_Type;                                                
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFul << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1ul << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7Ful << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3ul << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1ul << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1ul << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1ul << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1ul << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1ul << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1ul << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1ul << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1ul << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1ul << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1ul << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1ul << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
-  memory mapped structure for Interrupt Type
-  @{
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                         /*!< Offset: 0x04  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                        /*!< Offset: 0x08  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos  0                                             /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos     2                                             /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk    (1ul << InterruptType_ACTLR_DISFOLD_Pos)       /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos  1                                             /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)    /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos  0                                             /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)    /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
-  memory mapped structure for Memory Protection Unit (MPU)
-  @{
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                         /*!< Offset: 0x00  MPU Type Register                              */
-  __IO uint32_t CTRL;                         /*!< Offset: 0x04  MPU Control Register                           */
-  __IO uint32_t RNR;                          /*!< Offset: 0x08  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                         /*!< Offset: 0x0C  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                         /*!< Offset: 0x10  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                      /*!< Offset: 0x14  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                      /*!< Offset: 0x18  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                      /*!< Offset: 0x1C  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                      /*!< Offset: 0x20  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                      /*!< Offset: 0x24  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                      /*!< Offset: 0x28  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;                                                
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFul << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFul << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1ul << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1ul << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1ul << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1ul << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFul << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFul << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1ul << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFul << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1ul << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7ul << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7ul << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1ul << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1ul << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1ul << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFul << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1Ful << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1Ful << MPU_RASR_ENA_Pos)                  /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
-  memory mapped structure for Core Debug Register
-  @{
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                        /*!< Offset: 0x00  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                        /*!< Offset: 0x04  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                        /*!< Offset: 0x08  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                        /*!< Offset: 0x0C  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1ul << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1ul << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1ul << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1ul << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1ul << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1ul << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1ul << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1ul << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1ul << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000)                              /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000)                              /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0)                              /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010)                      /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100)                      /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00)                      /*!< System Control Block Base Address */
-
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90)                      /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq                __enable_fiq
-#define __disable_fault_irq               __disable_fiq
-
-#define __NOP                             __nop
-#define __WFI                             __wfi
-#define __WFE                             __wfe
-#define __SEV                             __sev
-#define __ISB()                           __isb(0)
-#define __DSB()                           __dsb(0)
-#define __DMB()                           __dmb(0)
-#define __REV                             __rev
-#define __RBIT                            __rbit
-#define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
-#define __STREXB(value, ptr)              __strex(value, ptr)
-#define __STREXH(value, ptr)              __strex(value, ptr)
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param   value  value to reverse
- * @return         reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param   priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else  /* (__ARMCC_VERSION >= 400000)  */
-
-/**
- * @brief  Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX                           __clrex
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief  Return the Control Register value
- * 
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION  */ 
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
-#define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq()         { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM ("cpsid f"); }
-
-#define __NOP                                     __no_operation            /*!< no operation intrinsic in IAR Compiler */ 
-static __INLINE  void __WFI()                     { __ASM ("wfi"); }
-static __INLINE  void __WFE()                     { __ASM ("wfe"); }
-static __INLINE  void __SEV()                     { __ASM ("sev"); }
-static __INLINE  void __CLREX()                   { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void)                                     */
-/* intrinsic void __DSB(void)                                     */
-/* intrinsic void __DMB(void)                                     */
-/* intrinsic void __set_PRIMASK();                                */
-/* intrinsic void __get_PRIMASK();                                */
-/* intrinsic void __set_FAULTMASK();                              */
-/* intrinsic void __get_FAULTMASK();                              */
-/* intrinsic uint32_t __REV(uint32_t value);                      */
-/* intrinsic uint32_t __REVSH(uint32_t value);                    */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *);              */
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq()               { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq()              { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq()         { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq()        { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
-static __INLINE void __WFI()                      { __ASM volatile ("wfi"); }
-static __INLINE void __WFE()                      { __ASM volatile ("wfe"); }
-static __INLINE void __SEV()                      { __ASM volatile ("sev"); }
-static __INLINE void __ISB()                      { __ASM volatile ("isb"); }
-static __INLINE void __DSB()                      { __ASM volatile ("dsb"); }
-static __INLINE void __DMB()                      { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX()                    { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief  Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief  Set the Process Stack Pointer
- *
- * @param  topOfProcStack  Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP 
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief  Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief  Set the Main Stack Pointer
- *
- * @param  topOfMainStack  Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP 
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief  Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief  Set the Base Priority value
- *
- * @param  basePri  BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief  Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t  __get_PRIMASK(void);
-
-/**
- * @brief  Set the Priority Mask value
- *
- * @param  priMask  PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief  Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief  Set the Fault Mask value
- *
- * @param  faultMask  faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief  Return the Control Register value
-* 
-*  @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief  Set the Control Register value
- *
- * @param  control  Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief  Reverse byte order in integer value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief  Reverse byte order in unsigned short value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief  Reverse byte order in signed short value with sign extension to integer
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief  Reverse bit order of value
- *
- * @param  value  value to reverse
- * @return        reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief  LDR Exclusive (8 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief  LDR Exclusive (16 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief  LDR Exclusive (32 bit)
- *
- * @param  *addr  address pointer
- * @return        value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief  STR Exclusive (8 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief  STR Exclusive (16 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief  STR Exclusive (32 bit)
- *
- * @param  value  value to store
- * @param  *addr  address pointer
- * @return        successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
-  Core  Function Interface containing:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Reset Functions
-*/
-/*@{*/
-
-/* ##########################   NVIC functions  #################################### */
-
-/**
- * @brief  Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param  PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field 
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-  
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-/**
- * @brief  Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field 
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-/**
- * @brief  Enable Interrupt in NVIC Interrupt Controller
- *
- * @param  IRQn   The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief  Disable the interrupt line for external interrupt specified
- * 
- * @param  IRQn   The positive number of the external interrupt to disable
- * 
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief  Read the interrupt pending bit for a device specific interrupt source
- * 
- * @param  IRQn    The number of the device specifc interrupt
- * @return         1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending, 
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief  Set the pending bit for an external interrupt
- * 
- * @param  IRQn    The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief  Clear the pending bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt. 
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief  Read the active bit for an external interrupt
- *
- * @param  IRQn    The number of the interrupt for read active bit
- * @return         1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active, 
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief  Set the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for set priority
- * @param  priority  The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-/**
- * @brief  Read the priority for an interrupt
- *
- * @param  IRQn      The number of the interrupt for get priority
- * @return           The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt 
- * number can be positive to specify an external (device specific) 
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M3 system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/**
- * @brief  Encode the priority for an interrupt
- *
- * @param  PriorityGroup    The used priority group
- * @param  PreemptPriority  The preemptive priority value (starting from 0)
- * @param  SubPriority      The sub priority value (starting from 0)
- * @return                  The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
- 
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/**
- * @brief  Decode the priority of an interrupt
- *
- * @param  Priority           The priority for the interrupt
- * @param  PriorityGroup      The used priority group
- * @param  pPreemptPriority   The preemptive priority value (starting from 0)
- * @param  pSubPriority       The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to 
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-  
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-
-/* ##################################    SysTick function  ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief  Initialize and start the SysTick counter and its interrupt.
- *
- * @param   ticks   number of ticks between two interrupts
- * @return  1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate 
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{ 
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-                                                               
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
-                   SysTick_CTRL_TICKINT_Msk   | 
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ##################################    Reset function  ############################################ */
-
-/**
- * @brief  Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */              
-  while(1);                                                    /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
-  Core Debug Interface containing:
-  - Core Debug Receive / Transmit Functions
-  - Core Debug Defines
-  - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer;                    /*!< variable to receive characters                             */
-#define             ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief  Outputs a character via the ITM channel 0
- *
- * @param  ch   character to output
- * @return      character to output
- *
- * The function outputs a character via the ITM channel 0. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1ul << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }  
-  return (ch);
-}
-
-
-/**
- * @brief  Inputs a character via variable ITM_RxBuffer
- *
- * @return      received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer. 
- * The function returns when no debugger is connected that has booked the output.  
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. 
- */
-static __INLINE int ITM_ReceiveChar (void) {
-  int ch = -1;                               /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-  
-  return (ch); 
-}
-
-
-/**
- * @brief  Check if a character via variable ITM_RxBuffer is available
- *
- * @return      1 = character available, 0 = no character available
- *
- * The function checks  variable ITM_RxBuffer whether a character is available or not. 
- * The function returns '1' if a character is available and '0' if no character is available. 
- */
-static __INLINE int ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */

bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/LPC17xx.h

@@ -1,1028 +0,0 @@
-/**************************************************************************//**
- * @file     LPC17xx.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for 
- *           NXP LPC17xx Device Series
- * @version  V1.07
- * @date     19. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC17xx_H__
-#define __LPC17xx_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC17xx Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-#include "system_LPC17xx.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
-  __IO uint32_t PLL0CFG;
-  __I  uint32_t PLL0STAT;
-  __O  uint32_t PLL0FEED;
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;
-  __IO uint32_t PLL1CFG;
-  __I  uint32_t PLL1STAT;
-  __O  uint32_t PLL1FEED;
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;
-  __IO uint32_t PCONP;
-       uint32_t RESERVED3[15];
-  __IO uint32_t CCLKCFG;
-  __IO uint32_t USBCLKCFG;
-  __IO uint32_t CLKSRCSEL;
-       uint32_t RESERVED4[12];
-  __IO uint32_t EXTINT;                 /* External Interrupts                */
-       uint32_t RESERVED5;
-  __IO uint32_t EXTMODE;
-  __IO uint32_t EXTPOLAR;
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                   /* Reset                              */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
-  __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
-  __IO uint32_t PCLKSEL0;
-  __IO uint32_t PCLKSEL1;
-       uint32_t RESERVED8[4];
-  __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
-  __IO uint32_t DMAREQSEL;
-  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t PINSEL0;
-  __IO uint32_t PINSEL1;
-  __IO uint32_t PINSEL2;
-  __IO uint32_t PINSEL3;
-  __IO uint32_t PINSEL4;
-  __IO uint32_t PINSEL5;
-  __IO uint32_t PINSEL6;
-  __IO uint32_t PINSEL7;
-  __IO uint32_t PINSEL8;
-  __IO uint32_t PINSEL9;
-  __IO uint32_t PINSEL10;
-       uint32_t RESERVED0[5];
-  __IO uint32_t PINMODE0;
-  __IO uint32_t PINMODE1;
-  __IO uint32_t PINMODE2;
-  __IO uint32_t PINMODE3;
-  __IO uint32_t PINMODE4;
-  __IO uint32_t PINMODE5;
-  __IO uint32_t PINMODE6;
-  __IO uint32_t PINMODE7;
-  __IO uint32_t PINMODE8;
-  __IO uint32_t PINMODE9;
-  __IO uint32_t PINMODE_OD0;
-  __IO uint32_t PINMODE_OD1;
-  __IO uint32_t PINMODE_OD2;
-  __IO uint32_t PINMODE_OD3;
-  __IO uint32_t PINMODE_OD4;
-  __IO uint32_t I2CPADCFG;
-} LPC_PINCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  union {
-    __IO uint32_t FIODIR;
-    struct {
-      __IO uint16_t FIODIRL;
-      __IO uint16_t FIODIRH;
-    };
-    struct {
-      __IO uint8_t  FIODIR0;
-      __IO uint8_t  FIODIR1;
-      __IO uint8_t  FIODIR2;
-      __IO uint8_t  FIODIR3;
-    };
-  };
-  uint32_t RESERVED0[3];
-  union {
-    __IO uint32_t FIOMASK;
-    struct {
-      __IO uint16_t FIOMASKL;
-      __IO uint16_t FIOMASKH;
-    };
-    struct {
-      __IO uint8_t  FIOMASK0;
-      __IO uint8_t  FIOMASK1;
-      __IO uint8_t  FIOMASK2;
-      __IO uint8_t  FIOMASK3;
-    };
-  };
-  union {
-    __IO uint32_t FIOPIN;
-    struct {
-      __IO uint16_t FIOPINL;
-      __IO uint16_t FIOPINH;
-    };
-    struct {
-      __IO uint8_t  FIOPIN0;
-      __IO uint8_t  FIOPIN1;
-      __IO uint8_t  FIOPIN2;
-      __IO uint8_t  FIOPIN3;
-    };
-  };
-  union {
-    __IO uint32_t FIOSET;
-    struct {
-      __IO uint16_t FIOSETL;
-      __IO uint16_t FIOSETH;
-    };
-    struct {
-      __IO uint8_t  FIOSET0;
-      __IO uint8_t  FIOSET1;
-      __IO uint8_t  FIOSET2;
-      __IO uint8_t  FIOSET3;
-    };
-  };
-  union {
-    __O  uint32_t FIOCLR;
-    struct {
-      __O  uint16_t FIOCLRL;
-      __O  uint16_t FIOCLRH;
-    };
-    struct {
-      __O  uint8_t  FIOCLR0;
-      __O  uint8_t  FIOCLR1;
-      __O  uint8_t  FIOCLR2;
-      __O  uint8_t  FIOCLR3;
-    };
-  };
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;
-  __IO uint32_t TCR;
-  __IO uint32_t TC;
-  __IO uint32_t PR;
-  __IO uint32_t PC;
-  __IO uint32_t MCR;
-  __IO uint32_t MR0;
-  __IO uint32_t MR1;
-  __IO uint32_t MR2;
-  __IO uint32_t MR3;
-  __IO uint32_t CCR;
-  __I  uint32_t CR0;
-  __I  uint32_t CR1;
-  __I  uint32_t CR2;
-  __I  uint32_t CR3;
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;
-  __IO uint32_t MR5;
-  __IO uint32_t MR6;
-  __IO uint32_t PCR;
-  __IO uint32_t LER;
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART0_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART1_TypeDef;
-
-/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t SPCR;
-  __I  uint32_t SPSR;
-  __IO uint32_t SPDR;
-  __IO uint32_t SPCCR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t SPINT;
-} LPC_SPI_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;
-  __IO uint32_t CR1;
-  __IO uint32_t DR;
-  __I  uint32_t SR;
-  __IO uint32_t CPSR;
-  __IO uint32_t IMSC;
-  __IO uint32_t RIS;
-  __IO uint32_t MIS;
-  __IO uint32_t ICR;
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2CONSET;
-  __I  uint32_t I2STAT;
-  __IO uint32_t I2DAT;
-  __IO uint32_t I2ADR0;
-  __IO uint32_t I2SCLH;
-  __IO uint32_t I2SCLL;
-  __O  uint32_t I2CONCLR;
-  __IO uint32_t MMCTRL;
-  __IO uint32_t I2ADR1;
-  __IO uint32_t I2ADR2;
-  __IO uint32_t I2ADR3;
-  __I  uint32_t I2DATA_BUFFER;
-  __IO uint32_t I2MASK0;
-  __IO uint32_t I2MASK1;
-  __IO uint32_t I2MASK2;
-  __IO uint32_t I2MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t I2SDAO;
-  __IO uint32_t I2SDAI;
-  __O  uint32_t I2STXFIFO;
-  __I  uint32_t I2SRXFIFO;
-  __I  uint32_t I2SSTATE;
-  __IO uint32_t I2SDMA1;
-  __IO uint32_t I2SDMA2;
-  __IO uint32_t I2SIRQ;
-  __IO uint32_t I2STXRATE;
-  __IO uint32_t I2SRXRATE;
-  __IO uint32_t I2STXBITRATE;
-  __IO uint32_t I2SRXBITRATE;
-  __IO uint32_t I2STXMODE;
-  __IO uint32_t I2SRXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t RICOMPVAL;
-  __IO uint32_t RIMASK;
-  __IO uint8_t  RICTRL;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t RICOUNTER;
-} LPC_RIT_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  WDMOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t WDTC;
-  __O  uint8_t  WDFEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t WDTV;
-  __IO uint32_t WDCLKSEL;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t ADCR;
-  __IO uint32_t ADGDR;
-       uint32_t RESERVED0;
-  __IO uint32_t ADINTEN;
-  __I  uint32_t ADDR0;
-  __I  uint32_t ADDR1;
-  __I  uint32_t ADDR2;
-  __I  uint32_t ADDR3;
-  __I  uint32_t ADDR4;
-  __I  uint32_t ADDR5;
-  __I  uint32_t ADDR6;
-  __I  uint32_t ADDR7;
-  __I  uint32_t ADSTAT;
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t DACR;
-  __IO uint32_t DACCTRL;
-  __IO uint16_t DACCNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t MCCON;
-  __O  uint32_t MCCON_SET;
-  __O  uint32_t MCCON_CLR;
-  __I  uint32_t MCCAPCON;
-  __O  uint32_t MCCAPCON_SET;
-  __O  uint32_t MCCAPCON_CLR;
-  __IO uint32_t MCTIM0;
-  __IO uint32_t MCTIM1;
-  __IO uint32_t MCTIM2;
-  __IO uint32_t MCPER0;
-  __IO uint32_t MCPER1;
-  __IO uint32_t MCPER2;
-  __IO uint32_t MCPW0;
-  __IO uint32_t MCPW1;
-  __IO uint32_t MCPW2;
-  __IO uint32_t MCDEADTIME;
-  __IO uint32_t MCCCP;
-  __IO uint32_t MCCR0;
-  __IO uint32_t MCCR1;
-  __IO uint32_t MCCR2;
-  __I  uint32_t MCINTEN;
-  __O  uint32_t MCINTEN_SET;
-  __O  uint32_t MCINTEN_CLR;
-  __I  uint32_t MCCNTCON;
-  __O  uint32_t MCCNTCON_SET;
-  __O  uint32_t MCCNTCON_CLR;
-  __I  uint32_t MCINTFLAG;
-  __O  uint32_t MCINTFLAG_SET;
-  __O  uint32_t MCINTFLAG_CLR;
-  __O  uint32_t MCCAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t QEICON;
-  __I  uint32_t QEISTAT;
-  __IO uint32_t QEICONF;
-  __I  uint32_t QEIPOS;
-  __IO uint32_t QEIMAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP;
-  __IO uint32_t QEILOAD;
-  __I  uint32_t QEITIME;
-  __I  uint32_t QEIVEL;
-  __I  uint32_t QEICAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTER;
-       uint32_t RESERVED0[998];
-  __O  uint32_t QEIIEC;
-  __O  uint32_t QEIIES;
-  __I  uint32_t QEIINTSTAT;
-  __I  uint32_t QEIIE;
-  __O  uint32_t QEICLR;
-  __O  uint32_t QEISET;
-} LPC_QEI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-  __IO uint32_t AFMR;
-  __IO uint32_t SFF_sa;
-  __IO uint32_t SFF_GRP_sa;
-  __IO uint32_t EFF_sa;
-  __IO uint32_t EFF_GRP_sa;
-  __IO uint32_t ENDofTable;
-  __I  uint32_t LUTerrAd;
-  __I  uint32_t LUTerr;
-  __IO uint32_t FCANIE;
-  __IO uint32_t FCANIC0;
-  __IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t CANTxSR;
-  __I  uint32_t CANRxSR;
-  __I  uint32_t CANMSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-  __IO uint32_t MOD;
-  __O  uint32_t CMR;
-  __IO uint32_t GSR;
-  __I  uint32_t ICR;
-  __IO uint32_t IER;
-  __IO uint32_t BTR;
-  __IO uint32_t EWL;
-  __I  uint32_t SR;
-  __IO uint32_t RFS;
-  __IO uint32_t RID;
-  __IO uint32_t RDA;
-  __IO uint32_t RDB;
-  __IO uint32_t TFI1;
-  __IO uint32_t TID1;
-  __IO uint32_t TDA1;
-  __IO uint32_t TDB1;
-  __IO uint32_t TFI2;
-  __IO uint32_t TID2;
-  __IO uint32_t TDA2;
-  __IO uint32_t TDB2;
-  __IO uint32_t TFI3;
-  __IO uint32_t TID3;
-  __IO uint32_t TDA3;
-  __IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t DMACIntStat;
-  __I  uint32_t DMACIntTCStat;
-  __O  uint32_t DMACIntTCClear;
-  __I  uint32_t DMACIntErrStat;
-  __O  uint32_t DMACIntErrClr;
-  __I  uint32_t DMACRawIntTCStat;
-  __I  uint32_t DMACRawIntErrStat;
-  __I  uint32_t DMACEnbldChns;
-  __IO uint32_t DMACSoftBReq;
-  __IO uint32_t DMACSoftSReq;
-  __IO uint32_t DMACSoftLBReq;
-  __IO uint32_t DMACSoftLSReq;
-  __IO uint32_t DMACConfig;
-  __IO uint32_t DMACSync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t DMACCSrcAddr;
-  __IO uint32_t DMACCDestAddr;
-  __IO uint32_t DMACCLLI;
-  __IO uint32_t DMACCControl;
-  __IO uint32_t DMACCConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t HcRevision;             /* USB Host Registers                 */
-  __IO uint32_t HcControl;
-  __IO uint32_t HcCommandStatus;
-  __IO uint32_t HcInterruptStatus;
-  __IO uint32_t HcInterruptEnable;
-  __IO uint32_t HcInterruptDisable;
-  __IO uint32_t HcHCCA;
-  __I  uint32_t HcPeriodCurrentED;
-  __IO uint32_t HcControlHeadED;
-  __IO uint32_t HcControlCurrentED;
-  __IO uint32_t HcBulkHeadED;
-  __IO uint32_t HcBulkCurrentED;
-  __I  uint32_t HcDoneHead;
-  __IO uint32_t HcFmInterval;
-  __I  uint32_t HcFmRemaining;
-  __I  uint32_t HcFmNumber;
-  __IO uint32_t HcPeriodicStart;
-  __IO uint32_t HcLSTreshold;
-  __IO uint32_t HcRhDescriptorA;
-  __IO uint32_t HcRhDescriptorB;
-  __IO uint32_t HcRhStatus;
-  __IO uint32_t HcRhPortStatus1;
-  __IO uint32_t HcRhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t OTGIntEn;
-  __O  uint32_t OTGIntSet;
-  __O  uint32_t OTGIntClr;
-  __IO uint32_t OTGStCtrl;
-  __IO uint32_t OTGTmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t USBDevIntEn;
-  __O  uint32_t USBDevIntClr;
-  __O  uint32_t USBDevIntSet;
-
-  __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t USBCmdData;
-
-  __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t USBTxData;
-  __I  uint32_t USBRxPLen;
-  __O  uint32_t USBTxPLen;
-  __IO uint32_t USBCtrl;
-  __O  uint32_t USBDevIntPri;
-
-  __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t USBEpIntEn;
-  __O  uint32_t USBEpIntClr;
-  __O  uint32_t USBEpIntSet;
-  __O  uint32_t USBEpIntPri;
-
-  __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t USBEpInd;
-  __IO uint32_t USBMaxPSize;
-
-  __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t USBDMARClr;
-  __O  uint32_t USBDMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t USBUDCAH;
-  __I  uint32_t USBEpDMASt;
-  __O  uint32_t USBEpDMAEn;
-  __O  uint32_t USBEpDMADis;
-  __I  uint32_t USBDMAIntSt;
-  __IO uint32_t USBDMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t USBEoTIntSt;
-  __O  uint32_t USBEoTIntClr;
-  __O  uint32_t USBEoTIntSet;
-  __I  uint32_t USBNDDRIntSt;
-  __O  uint32_t USBNDDRIntClr;
-  __O  uint32_t USBNDDRIntSet;
-  __I  uint32_t USBSysErrIntSt;
-  __O  uint32_t USBSysErrIntClr;
-  __O  uint32_t USBSysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_WO;
-  __I  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[823];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __IO uint32_t RxFilterWoLStatus;
-  __IO uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_GPIO_BASE         (0x2009C000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHB_BASE          (0x50000000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-
-/* GPIOs                                                                      */
-#define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
-#define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
-#define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
-#define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
-#define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
-#define LPC_UART0             ((LPC_UART0_TypeDef     *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-
-#endif  // __LPC17xx_H__

bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s

@@ -1,277 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC17xx.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
-; *           for the NXP LPC17xx Device Series 
-; * @version: V1.02
-; * @date:    27. July 2009
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2009 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000200
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-                DCD     TIMER0_IRQHandler         ; 17: Timer0
-                DCD     TIMER1_IRQHandler         ; 18: Timer1
-                DCD     TIMER2_IRQHandler         ; 19: Timer2
-                DCD     TIMER3_IRQHandler         ; 20: Timer3
-                DCD     UART0_IRQHandler          ; 21: UART0
-                DCD     UART1_IRQHandler          ; 22: UART1
-                DCD     UART2_IRQHandler          ; 23: UART2
-                DCD     UART3_IRQHandler          ; 24: UART3
-                DCD     PWM1_IRQHandler           ; 25: PWM1
-                DCD     I2C0_IRQHandler           ; 26: I2C0
-                DCD     I2C1_IRQHandler           ; 27: I2C1
-                DCD     I2C2_IRQHandler           ; 28: I2C2
-                DCD     SPI_IRQHandler            ; 29: SPI
-                DCD     SSP0_IRQHandler           ; 30: SSP0
-                DCD     SSP1_IRQHandler           ; 31: SSP1
-                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-                DCD     RTC_IRQHandler            ; 33: Real Time Clock
-                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-                DCD     ADC_IRQHandler            ; 38: A/D Converter
-                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-                DCD     USB_IRQHandler            ; 40: USB
-                DCD     CAN_IRQHandler            ; 41: CAN
-                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-                DCD     I2S_IRQHandler            ; 43: I2S
-                DCD     ENET_IRQHandler           ; 44: Ethernet
-                DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
-                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)                
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  TIMER0_IRQHandler         [WEAK]
-                EXPORT  TIMER1_IRQHandler         [WEAK]
-                EXPORT  TIMER2_IRQHandler         [WEAK]
-                EXPORT  TIMER3_IRQHandler         [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  PWM1_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  I2C2_IRQHandler           [WEAK]
-                EXPORT  SPI_IRQHandler            [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  PLL0_IRQHandler           [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  EINT2_IRQHandler          [WEAK]
-                EXPORT  EINT3_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  DMA_IRQHandler            [WEAK]
-                EXPORT  I2S_IRQHandler            [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  RIT_IRQHandler            [WEAK]
-                EXPORT  MCPWM_IRQHandler          [WEAK]
-                EXPORT  QEI_IRQHandler            [WEAK]
-                EXPORT  PLL1_IRQHandler           [WEAK]
-
-WDT_IRQHandler           
-TIMER0_IRQHandler         
-TIMER1_IRQHandler         
-TIMER2_IRQHandler         
-TIMER3_IRQHandler         
-UART0_IRQHandler          
-UART1_IRQHandler          
-UART2_IRQHandler          
-UART3_IRQHandler          
-PWM1_IRQHandler           
-I2C0_IRQHandler           
-I2C1_IRQHandler           
-I2C2_IRQHandler           
-SPI_IRQHandler            
-SSP0_IRQHandler           
-SSP1_IRQHandler           
-PLL0_IRQHandler           
-RTC_IRQHandler            
-EINT0_IRQHandler          
-EINT1_IRQHandler          
-EINT2_IRQHandler          
-EINT3_IRQHandler          
-ADC_IRQHandler            
-BOD_IRQHandler            
-USB_IRQHandler            
-CAN_IRQHandler            
-DMA_IRQHandler          
-I2S_IRQHandler            
-ENET_IRQHandler       
-RIT_IRQHandler          
-MCPWM_IRQHandler             
-QEI_IRQHandler            
-PLL1_IRQHandler           
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-                ELSE
-                
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END

bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s

@@ -1,228 +0,0 @@
-/**
- * startup_LPC17xx.s
- */
-
-	.syntax unified
-	.cpu cortex-m3
-	.fpu softvfp
-	.thumb
-
-	.word  _sidata
-	.word  _sdata
-	.word  _edata
-	.word  _sbss
-	.word  _ebss
-
-/* Vector Table */
-
-    .section ".interrupt_vector"
-    .globl  __interrupt_vector
-    .type   __interrupt_vector, %object
-
-__interrupt_vector:
-    .long   _estack                     /* Top of Stack                 */
-    .long   Reset_Handler               /* Reset Handler                */
-    .long   NMI_Handler                 /* NMI Handler                  */
-    .long   HardFault_Handler           /* Hard Fault Handler           */
-    .long   MemManage_Handler           /* MPU Fault Handler            */
-    .long   BusFault_Handler            /* Bus Fault Handler            */
-    .long   UsageFault_Handler          /* Usage Fault Handler          */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   SVC_Handler                 /* SVCall Handler               */
-    .long   DebugMon_Handler            /* Debug Monitor Handler        */
-    .long   0                           /* Reserved                     */
-    .long   PendSV_Handler              /* PendSV Handler               */
-    .long   SysTick_Handler             /* SysTick Handler              */
-
-    /* External Interrupts */
-    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
-    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
-    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
-    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
-    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
-    .long   UART0_IRQHandler            /* 21: UART0                        */
-    .long   UART1_IRQHandler            /* 22: UART1                        */
-    .long   UART2_IRQHandler            /* 23: UART2                        */
-    .long   UART3_IRQHandler            /* 24: UART3                        */
-    .long   PWM1_IRQHandler             /* 25: PWM1                         */
-    .long   I2C0_IRQHandler             /* 26: I2C0                         */
-    .long   I2C1_IRQHandler             /* 27: I2C1                         */
-    .long   I2C2_IRQHandler             /* 28: I2C2                         */
-    .long   SPI_IRQHandler              /* 29: SPI                          */
-    .long   SSP0_IRQHandler             /* 30: SSP0                         */
-    .long   SSP1_IRQHandler             /* 31: SSP1                         */
-    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
-    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
-    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
-    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
-    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
-    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
-    .long   ADC_IRQHandler              /* 38: A/D Converter                */
-    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
-    .long   USB_IRQHandler              /* 40: USB                          */
-    .long   CAN_IRQHandler              /* 41: CAN                          */
-    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
-    .long   I2S_IRQHandler              /* 43: I2S                          */
-    .long   ENET_IRQHandler             /* 44: Ethernet                     */
-    .long   RIT_IRQHandler              /* 45: Repetitive Interrupt Timer   */
-    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
-    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
-    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
-
-    .size   __interrupt_vector, . - __interrupt_vector
-
-/* Reset Handler */
-    .section  .text.Reset_Handler
-	.weak  Reset_Handler
-	.type  Reset_Handler, %function
-Reset_Handler:
-    .fnstart
-
-/* Copy the data segment initializers from flash to SRAM */
-	movs	r1, #0
-  	b	LoopCopyDataInit
-
-CopyDataInit:
-	ldr	r3, =_sidata
-	ldr	r3, [r3, r1]
-	str	r3, [r0, r1]
-	add	r1, r1, #4
-
-LoopCopyDataInit:
-	ldr	r0, =_sdata
-	ldr	r3, =_edata
-	add	r2, r0, r1
-	cmp	r2, r3
-	bcc	CopyDataInit
-	ldr	r2, =_sbss
-	b	LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-	movs	r3, #0
-	str	r3, [r2], #4
-
-LoopFillZerobss:
-	ldr	r3, = _ebss
-	cmp	r2, r3
-	bcc	FillZerobss
-/* Call the clock system intitialization function.*/
-  	bl  SystemInit
-/* Call the application's entry point.*/
-	bl	main
-	bx	lr
-
-    .pool
-    .cantunwind
-    .fnend
-    .size   Reset_Handler,.-Reset_Handler
-
-    .section ".text"
-
-/* Exception Handlers */
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   MemManage_Handler
-    .type   MemManage_Handler, %function
-MemManage_Handler:
-    B       .
-    .size   MemManage_Handler, . - MemManage_Handler
-
-    .weak   BusFault_Handler
-    .type   BusFault_Handler, %function
-BusFault_Handler:
-    B       .
-    .size   BusFault_Handler, . - BusFault_Handler
-
-    .weak   UsageFault_Handler
-    .type   UsageFault_Handler, %function
-UsageFault_Handler:
-    B       .
-    .size   UsageFault_Handler, . - UsageFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   DebugMon_Handler
-    .type   DebugMon_Handler, %function
-DebugMon_Handler:
-    B       .
-    .size   DebugMon_Handler, . - DebugMon_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-
-/* IRQ Handlers */
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ     WDT_IRQHandler
-    IRQ     TIMER0_IRQHandler
-    IRQ     TIMER1_IRQHandler
-    IRQ     TIMER2_IRQHandler
-    IRQ     TIMER3_IRQHandler
-    IRQ     UART0_IRQHandler
-    IRQ     UART1_IRQHandler
-    IRQ     UART2_IRQHandler
-    IRQ     UART3_IRQHandler
-    IRQ     PWM1_IRQHandler
-    IRQ     I2C0_IRQHandler
-    IRQ     I2C1_IRQHandler
-    IRQ     I2C2_IRQHandler
-    IRQ     SPI_IRQHandler
-    IRQ     SSP0_IRQHandler
-    IRQ     SSP1_IRQHandler
-    IRQ     PLL0_IRQHandler
-    IRQ     RTC_IRQHandler
-    IRQ     EINT0_IRQHandler
-    IRQ     EINT1_IRQHandler
-    IRQ     EINT2_IRQHandler
-    IRQ     EINT3_IRQHandler
-    IRQ     ADC_IRQHandler
-    IRQ     BOD_IRQHandler
-    IRQ     USB_IRQHandler
-    IRQ     CAN_IRQHandler
-    IRQ     DMA_IRQHandler
-    IRQ     I2S_IRQHandler
-    IRQ     ENET_IRQHandler
-    IRQ     RIT_IRQHandler
-    IRQ     MCPWM_IRQHandler
-    IRQ     QEI_IRQHandler
-    IRQ     PLL1_IRQHandler
-
-    .end

bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s

@@ -1,341 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC17xx.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File 
-; *           for the NXP LPC17xx Device Series 
-; * @version: V1.02
-; * @date:    31. July 2009
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (C) 2009 ARM Limited. All rights reserved.
-; *
-; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; ******************************************************************************/
-
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-	
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-        DCD     TIMER0_IRQHandler         ; 17: Timer0
-        DCD     TIMER1_IRQHandler         ; 18: Timer1
-        DCD     TIMER2_IRQHandler         ; 19: Timer2
-        DCD     TIMER3_IRQHandler         ; 20: Timer3
-        DCD     UART0_IRQHandler          ; 21: UART0
-        DCD     UART1_IRQHandler          ; 22: UART1
-        DCD     UART2_IRQHandler          ; 23: UART2
-        DCD     UART3_IRQHandler          ; 24: UART3
-        DCD     PWM1_IRQHandler           ; 25: PWM1
-        DCD     I2C0_IRQHandler           ; 26: I2C0
-        DCD     I2C1_IRQHandler           ; 27: I2C1
-        DCD     I2C2_IRQHandler           ; 28: I2C2
-        DCD     SPI_IRQHandler            ; 29: SPI
-        DCD     SSP0_IRQHandler           ; 30: SSP0
-        DCD     SSP1_IRQHandler           ; 31: SSP1
-        DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-        DCD     RTC_IRQHandler            ; 33: Real Time Clock
-        DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-        DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-        DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-        DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-        DCD     ADC_IRQHandler            ; 38: A/D Converter
-        DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-        DCD     USB_IRQHandler            ; 40: USB
-        DCD     CAN_IRQHandler            ; 41: CAN
-        DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-        DCD     I2S_IRQHandler            ; 43: I2S
-        DCD     ENET_IRQHandler           ; 44: Ethernet
-        DCD     RIT_IRQHandler            ; 45: Repetitive Interrupt Timer
-        DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-        DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-        DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size 	EQU 	__Vectors_End - __Vectors
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK TIMER0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER0_IRQHandler
-        B TIMER0_IRQHandler
-
-        PUBWEAK TIMER1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER1_IRQHandler
-        B TIMER1_IRQHandler
-
-        PUBWEAK TIMER2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER2_IRQHandler
-        B TIMER2_IRQHandler
-
-        PUBWEAK TIMER3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER3_IRQHandler
-        B TIMER3_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK PWM1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PWM1_IRQHandler
-        B PWM1_IRQHandler
-
-        PUBWEAK I2C0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C0_IRQHandler
-        B I2C0_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-        PUBWEAK SPI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPI_IRQHandler
-        B SPI_IRQHandler
-
-        PUBWEAK SSP0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP0_IRQHandler
-        B SSP0_IRQHandler
-
-        PUBWEAK SSP1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP1_IRQHandler
-        B SSP1_IRQHandler
-
-        PUBWEAK PLL0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL0_IRQHandler
-        B PLL0_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK EINT0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT0_IRQHandler
-        B EINT0_IRQHandler
-
-        PUBWEAK EINT1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT1_IRQHandler
-        B EINT1_IRQHandler
-
-        PUBWEAK EINT2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT2_IRQHandler
-        B EINT2_IRQHandler
-
-        PUBWEAK EINT3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT3_IRQHandler
-        B EINT3_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK BOD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-BOD_IRQHandler
-        B BOD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK DMA_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA_IRQHandler
-        B DMA_IRQHandler
-
-        PUBWEAK I2S_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2S_IRQHandler
-        B I2S_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK RIT_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RIT_IRQHandler
-        B RIT_IRQHandler
-
-        PUBWEAK MCPWM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-MCPWM_IRQHandler
-        B MCPWM_IRQHandler
-
-        PUBWEAK QEI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-QEI_IRQHandler
-        B QEI_IRQHandler
-
-        PUBWEAK PLL1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL1_IRQHandler
-        B PLL1_IRQHandler
-
-        END

bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c

@@ -1,539 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC17xx.c
- * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Source File
- *           for the NXP LPC17xx Device Series
- * @version  V1.03
- * @date     07. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-#include "LPC17xx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Controls and Status Register (SCS)
-//     <o1.4>    OSCRANGE: Main Oscillator Range Select
-//                     <0=>  1 MHz to 20 MHz
-//                     <1=> 15 MHz to 24 MHz
-//     <e1.5>       OSCEN: Main Oscillator Enable
-//     </e>
-//   </h>
-//
-//   <h> Clock Source Select Register (CLKSRCSEL)
-//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
-//                     <0=> Internal RC oscillator
-//                     <1=> Main oscillator
-//                     <2=> RTC oscillator
-//   </h>
-//
-//   <e3> PLL0 Configuration (Main PLL)
-//     <h> PLL0 Configuration Register (PLL0CFG)
-//                     <i> F_cco0 = (2 * M * F_in) / N
-//                     <i> F_in must be in the range of 32 kHz to 50 MHz
-//                     <i> F_cco0 must be in the range of 275 MHz to 550 MHz
-//       <o4.0..14>  MSEL: PLL Multiplier Selection
-//                     <6-32768><#-1>
-//                     <i> M Value
-//       <o4.16..23> NSEL: PLL Divider Selection
-//                     <1-256><#-1>
-//                     <i> N Value
-//     </h>
-//   </e>
-//
-//   <e5> PLL1 Configuration (USB PLL)
-//     <h> PLL1 Configuration Register (PLL1CFG)
-//                     <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
-//                     <i> F_cco1 = F_osc * M * 2 * P
-//                     <i> F_cco1 must be in the range of 156 MHz to 320 MHz
-//       <o6.0..4>   MSEL: PLL Multiplier Selection
-//                     <1-32><#-1>
-//                     <i> M Value (for USB maximum value is 4)
-//       <o6.5..6>   PSEL: PLL Divider Selection
-//                     <0=> 1
-//                     <1=> 2
-//                     <2=> 4
-//                     <3=> 8
-//                     <i> P Value
-//     </h>
-//   </e>
-//
-//   <h> CPU Clock Configuration Register (CCLKCFG)
-//     <o7.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL0
-//                     <3-256><#-1>
-//   </h>
-//
-//   <h> USB Clock Configuration Register (USBCLKCFG)
-//     <o8.0..3>   USBSEL: Divide Value for USB Clock from PLL0
-//                     <0-15>
-//                     <i> Divide is USBSEL + 1
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
-//     <o9.0..1>    PCLK_WDT: Peripheral Clock Selection for WDT
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.2..3>    PCLK_TIMER0: Peripheral Clock Selection for TIMER0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.4..5>    PCLK_TIMER1: Peripheral Clock Selection for TIMER1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.12..13>  PCLK_PWM1: Peripheral Clock Selection for PWM1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.14..15>  PCLK_I2C0: Peripheral Clock Selection for I2C0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.16..17>  PCLK_SPI: Peripheral Clock Selection for SPI
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.20..21>  PCLK_SSP1: Peripheral Clock Selection for SSP1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.22..23>  PCLK_DAC: Peripheral Clock Selection for DAC
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.24..25>  PCLK_ADC: Peripheral Clock Selection for ADC
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o9.26..27>  PCLK_CAN1: Peripheral Clock Selection for CAN1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//     <o9.28..29>  PCLK_CAN2: Peripheral Clock Selection for CAN2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//     <o9.30..31>  PCLK_ACF: Peripheral Clock Selection for ACF
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 6
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
-//     <o10.0..1>   PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.2..3>   PCLK_GPIO: Peripheral Clock Selection for GPIOs
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.4..5>   PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.6..7>   PCLK_I2C1: Peripheral Clock Selection for I2C1
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//     <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
-//                     <0=> Pclk = Cclk / 4
-//                     <1=> Pclk = Cclk
-//                     <2=> Pclk = Cclk / 2
-//                     <3=> Pclk = Hclk / 8
-//   </h>
-//
-//   <h> Power Control for Peripherals Register (PCONP)
-//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
-//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
-//     <o11.3>      PCUART0: UART 0 power/clock enable
-//     <o11.4>      PCUART1: UART 1 power/clock enable
-//     <o11.6>      PCPWM1: PWM 1 power/clock enable
-//     <o11.7>      PCI2C0: I2C interface 0 power/clock enable
-//     <o11.8>      PCSPI: SPI interface power/clock enable
-//     <o11.9>      PCRTC: RTC power/clock enable
-//     <o11.10>     PCSSP1: SSP interface 1 power/clock enable
-//     <o11.12>     PCAD: A/D converter power/clock enable
-//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
-//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
-//     <o11.15>     PCGPIO: GPIOs power/clock enable
-//     <o11.16>     PCRIT: Repetitive interrupt timer power/clock enable
-//     <o11.17>     PCMC: Motor control PWM power/clock enable
-//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
-//     <o11.19>     PCI2C1: I2C interface 1 power/clock enable
-//     <o11.21>     PCSSP0: SSP interface 0 power/clock enable
-//     <o11.22>     PCTIM2: Timer 2 power/clock enable
-//     <o11.23>     PCTIM3: Timer 3 power/clock enable
-//     <o11.24>     PCUART2: UART 2 power/clock enable
-//     <o11.25>     PCUART3: UART 3 power/clock enable
-//     <o11.26>     PCI2C2: I2C interface 2 power/clock enable
-//     <o11.27>     PCI2S: I2S interface power/clock enable
-//     <o11.29>     PCGPDMA: GP DMA function power/clock enable
-//     <o11.30>     PCENET: Ethernet block power/clock enable
-//     <o11.31>     PCUSB: USB interface power/clock enable
-//   </h>
-//
-//   <h> Clock Output Configuration Register (CLKOUTCFG)
-//     <o12.0..3>   CLKOUTSEL: Selects clock source for CLKOUT
-//                     <0=> CPU clock
-//                     <1=> Main oscillator
-//                     <2=> Internal RC oscillator
-//                     <3=> USB clock
-//                     <4=> RTC oscillator
-//     <o12.4..7>   CLKOUTDIV: Selects clock divider for CLKOUT
-//                     <1-16><#-1>
-//     <o12.8>      CLKOUT_EN: CLKOUT enable control
-//   </h>
-//
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000020
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x00050063
-#define PLL1_SETUP            1
-#define PLL1CFG_Val           0x00000023
-#define CCLKCFG_Val           0x00000003
-#define USBCLKCFG_Val         0x00000000
-#define PCLKSEL0_Val          0x00000000
-#define PCLKSEL1_Val          0x00000000
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000000
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-// <e> Flash Accelerator Configuration
-//   <o1.0..1>   FETCHCFG: Fetch Configuration
-//               <0=> Instruction fetches from flash are not buffered
-//               <1=> One buffer is used for all instruction fetch buffering
-//               <2=> All buffers may be used for instruction fetch buffering
-//               <3=> Reserved (do not use this setting)
-//   <o1.2..3>   DATACFG: Data Configuration
-//               <0=> Data accesses from flash are not buffered
-//               <1=> One buffer is used for all data access buffering
-//               <2=> All buffers may be used for data access buffering
-//               <3=> Reserved (do not use this setting)
-//   <o1.4>      ACCEL: Acceleration Enable
-//   <o1.5>      PREFEN: Prefetch Enable
-//   <o1.6>      PREFOVR: Prefetch Override
-//   <o1.12..15> FLASHTIM: Flash Access Time
-//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
-//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
-//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
-//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
-//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
-//               <5=> 6 CPU clocks (for any CPU clock)
-// </e>
-*/
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x0000303A
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x00000030))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x00FF7FFF))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
-   #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
-#endif
-
-#if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
-   #error "USBCLKCFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL0_Val),   0x000C0C00))
-   #error "PCLKSEL0: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL1_Val),   0x03000300))
-   #error "PCLKSEL1: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val),      0x10100821))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
-   #error "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-    
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32000UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     ( 4000000UL)        /* Internal RC oscillator frequency   */
-
-
-/* F_cco0 = (2 * M * F_in) / N  */
-#define __M               (((PLL0CFG_Val      ) & 0x7FFF) + 1)
-#define __N               (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
-#define __FCCO(__F_IN)    ((2 * __M * __F_IN) / __N) 
-#define __CCLK_DIV        (((CCLKCFG_Val      ) & 0x00FF) + 1)
-
-/* Determine core clock frequency according to settings */
- #if (PLL0_SETUP)
-    #if   ((CLKSRCSEL_Val & 0x03) == 1)
-        #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
-    #elif ((CLKSRCSEL_Val & 0x03) == 2)
-        #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
-    #else 
-        #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
-    #endif
- #else
-    #if   ((CLKSRCSEL_Val & 0x03) == 1)
-        #define __CORE_CLK (OSC_CLK         / __CCLK_DIV)
-    #elif ((CLKSRCSEL_Val & 0x03) == 2)
-        #define __CORE_CLK (RTC_CLK         / __CCLK_DIV)
-    #else
-        #define __CORE_CLK (IRC_OSC         / __CCLK_DIV)
-    #endif
- #endif
-
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                                /* Int. RC oscillator => PLL0    */
-      case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = (IRC_OSC * 
-                          ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = (OSC_CLK * 
-                          ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-      case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = (RTC_CLK * 
-                          ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1)))  /
-                          (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)    /
-                          ((LPC_SC->CCLKCFG & 0xFF)+ 1));
-        break;
-    }
-  } else {
-    switch (LPC_SC->CLKSRCSEL & 0x03) {
-      case 0:                                /* Int. RC oscillator => PLL0    */
-      case 3:                                /* Reserved, default to Int. RC  */
-        SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 1:                                /* Main oscillator => PLL0       */
-        SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-      case 2:                                /* RTC oscillator => PLL0        */
-        SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
-        break;
-    }
-  }
-
-}
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CCLKCFG   = CCLKCFG_Val;      /* Setup Clock Divider                */
-
-#if (PLL0_SETUP)
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for PLL0       */
-
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;      /* configure PLL0                     */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0                    */
-
-  LPC_SC->PLL0CON   = 0x03;             /* PLL0 Enable & Connect              */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-
-  LPC_SC->PLL1CON   = 0x03;             /* PLL1 Enable & Connect              */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
-#else
-  LPC_SC->USBCLKCFG = USBCLKCFG_Val;    /* Setup USB Clock Divider            */
-#endif
-
-  LPC_SC->PCLKSEL0  = PCLKSEL0_Val;     /* Peripheral Clock Selection         */
-  LPC_SC->PCLKSEL1  = PCLKSEL1_Val;
-
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = FLASHCFG_Val;
-#endif
-}

bsp/nxp/lpc/lpc176x/CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.h

@@ -1,64 +0,0 @@
-/**************************************************************************//**
- * @file     system_LPC17xx.h
- * @brief    CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- *           for the NXP LPC17xx Device Series
- * @version  V1.02
- * @date     08. September 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC17xx_H
-#define __SYSTEM_LPC17xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock 
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC17xx_H */

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_common_tables.h

@@ -1,93 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-*
-* $Date:        17. January 2013
-* $Revision:    V1.4.1
-*
-* Project:      CMSIS DSP Library
-* Title:        arm_common_tables.h
-*
-* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const q31_t realCoefAQ31[1024];
-extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoefQ31[6144];
-extern const q15_t twiddleCoefQ15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-#endif /*  ARM_COMMON_TABLES_H */

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/arm_math.h

@@ -1,7306 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-*
-* $Date:        17. January 2013
-* $Revision:    V1.4.1
-*
-* Project:      CMSIS DSP Library
-* Title:        arm_math.h
-*
-* Description:  Public header file for CMSIS DSP Library
-*
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*   - Redistributions of source code must retain the above copyright
-*     notice, this list of conditions and the following disclaimer.
-*   - Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in
-*     the documentation and/or other materials provided with the
-*     distribution.
-*   - Neither the name of ARM LIMITED nor the names of its contributors
-*     may be used to endorse or promote products derived from this
-*     software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
- * -------------------------------------------------------------------- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * <b>Introduction</b>
-   *
-   * This user manual describes the CMSIS DSP software library,
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of functions each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values.
-   *
-   * <b>Using the Library</b>
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
-   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
-   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
-   *
-   * <b>Examples</b>
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * <b>Toolchain Support</b>
-   *
-   * The library has been developed and tested with MDK-ARM version 4.60.
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * <b>Building the Library</b>
-   *
-   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
-   * - arm_cortexM0b_math.uvproj
-   * - arm_cortexM0l_math.uvproj
-   * - arm_cortexM3b_math.uvproj
-   * - arm_cortexM3l_math.uvproj
-   * - arm_cortexM4b_math.uvproj
-   * - arm_cortexM4l_math.uvproj
-   * - arm_cortexM4bf_math.uvproj
-   * - arm_cortexM4lf_math.uvproj
-   *
-   *
-   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
-   *
-   * <b>Pre-processor Macros</b>
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * - UNALIGNED_SUPPORT_DISABLE:
-   *
-   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
-   *
-   * - ARM_MATH_BIG_ENDIAN:
-   *
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * - ARM_MATH_MATRIX_CHECK:
-   *
-   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
-   *
-   * - ARM_MATH_ROUNDING:
-   *
-   * Define macro ARM_MATH_ROUNDING for rounding on support functions
-   *
-   * - ARM_MATH_CMx:
-   *
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
-   *
-   * - __FPU_PRESENT:
-   *
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
-   *
-   * <b>Copyright Notice</b>
-   *
-   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
-
-#if defined (ARM_MATH_CM4)
-#include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-#include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-#include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
-#define ARM_MATH_CM0_FAMILY
-#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
-#endif
-
-#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef	__cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
-#ifndef PI
-#define PI					3.14159265358979f
-#endif
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define TABLE_SIZE			256
-#define TABLE_SPACING_Q31	0x800000
-#define TABLE_SPACING_Q15	0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
-
-  /**
-   * @brief Macro for Unaligned Support
-   */
-#ifndef UNALIGNED_SUPPORT_DISABLE
-    #define ALIGN4
-#else
-  #if defined  (__GNUC__)
-    #define ALIGN4 __attribute__((aligned(4)))
-  #else
-    #define ALIGN4 __align(4)
-  #endif
-#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-  {
-    ARM_MATH_SUCCESS = 0,                /**< No error */
-    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
-    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
-    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
-    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
-    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
-  } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#if defined __CC_ARM
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED __attribute__((unused))
-#elif defined __ICCARM__
-#define CMSIS_UNUSED
-#define __SIMD32_TYPE int32_t __packed
-#elif defined __GNUC__
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#else
-#error Unknown compiler
-#endif
-
-#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
-
-#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
-
-#define __SIMD64(addr)  (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
-                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
-
-#endif
-
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  static __INLINE q31_t clip_q63_to_q31(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  static __INLINE q15_t clip_q63_to_q15(
-  q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  static __INLINE q7_t clip_q31_to_q7(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  static __INLINE q15_t clip_q31_to_q15(
-  q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  static __INLINE q63_t mult32x64(
-  q63_t x,
-  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-
-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
-#define __CLZ __clz
-#endif
-
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
-
-  static __INLINE uint32_t __CLZ(
-  q31_t data);
-
-
-  static __INLINE uint32_t __CLZ(
-  q31_t data)
-  {
-    uint32_t count = 0;
-    uint32_t mask = 0x80000000;
-
-    while((data & mask) == 0)
-    {
-      count += 1u;
-      mask = mask >> 1u;
-    }
-
-    return (count);
-
-  }
-
-#endif
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
-   */
-
-  static __INLINE uint32_t arm_recip_q31(
-  q31_t in,
-  q31_t * dst,
-  q31_t * pRecipTable)
-  {
-
-    uint32_t out, tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 1;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 1;
-    }
-
-    /* Convert input sample to 1.31 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t) (in >> 24u);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-    {
-      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
-      tempVal = 0x7FFFFFFF - tempVal;
-      /*      1.31 with exp 1 */
-      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
-      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-
-  }
-
-  /**
-   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
-   */
-  static __INLINE uint32_t arm_recip_q15(
-  q15_t in,
-  q15_t * dst,
-  q15_t * pRecipTable)
-  {
-
-    uint32_t out = 0, tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if(in > 0)
-    {
-      signBits = __CLZ(in) - 17;
-    }
-    else
-    {
-      signBits = __CLZ(-in) - 17;
-    }
-
-    /* Convert input sample to 1.15 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = in >> 8;
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0; i < 2; i++)
-    {
-      tempVal = (q15_t) (((q31_t) in * out) >> 15);
-      tempVal = 0x7FFF - tempVal;
-      /*      1.15 with exp 1 */
-      out = (q15_t) (((q31_t) out * tempVal) >> 14);
-    }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0_FAMILY)
-
-  static __INLINE q31_t __SSAT(
-  q31_t x,
-  uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-    {
-      posMax = posMax * 2;
-    }
-
-    if(x > 0)
-    {
-      posMax = (posMax - 1);
-
-      if(x > posMax)
-      {
-        x = posMax;
-      }
-    }
-    else
-    {
-      negMin = -posMax;
-
-      if(x < negMin)
-      {
-        x = negMin;
-      }
-    }
-    return (x);
-
-
-  }
-
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q7_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((q31_t) (r + s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
-    sum =
-      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB8(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s, t, u;
-
-    r = (q7_t) x;
-    s = (q7_t) y;
-
-    r = __SSAT((r - s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
-    sum =
-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
-                                                                0x000000FF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r + s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHADD16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (s >> 1));
-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r - s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSUB16(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t diff;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (s >> 1));
-    s = (((x >> 17) - (y >> 17)) << 16);
-
-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return diff;
-  }
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHASX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (y >> 17));
-    s = (((x >> 17) + (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum =
-      ((sum +
-        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSAX(
-  q31_t x,
-  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (y >> 17));
-    s = (((x >> 17) - (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSDX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((short) x * (short) (y >> 16)) -
-                     ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUADX(
-  q31_t x,
-  q31_t y)
-  {
-
-    return ((q31_t) (((short) x * (short) (y >> 16)) +
-                     ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x + y);
-  }
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB(
-  q31_t x,
-  q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x - y);
-  }
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLAD(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLADX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLSDX(
-  q31_t x,
-  q31_t y,
-  q31_t sum)
-  {
-
-    return (sum - ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALD(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALDX(
-  q31_t x,
-  q31_t y,
-  q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) y)) +
-      ((short) x * (short) (y >> 16));
-  }
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUAD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSD(
-  q31_t x,
-  q31_t y)
-  {
-
-    return (-((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-
-  /*
-   * @brief C custom defined SXTB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SXTB16(
-  q31_t x)
-  {
-
-    return ((((x << 24) >> 24) & 0x0000FFFF) |
-            (((x << 8) >> 8) & 0xFFFF0000));
-  }
-
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in] *S points to an instance of the Q7 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q7(
-  const arm_fir_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] *S points to an instance of the Q7 FIR structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed.
-   * @return none
-   */
-  void arm_fir_init_q7(
-  arm_fir_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in] *S points to an instance of the Q15 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q15(
-  const arm_fir_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-
-  arm_status arm_fir_init_q15(
-  arm_fir_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in] *S points to an instance of the Q31 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q31(
-  const arm_fir_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
-   */
-  void arm_fir_init_q31(
-  arm_fir_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in] *S points to an instance of the floating-point FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_f32(
-  const arm_fir_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
-   */
-  void arm_fir_init_f32(
-  arm_fir_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q15;
-
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-
-
-  } arm_biquad_casd_df1_inst_f32;
-
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q15(
-  arm_biquad_casd_df1_inst_q15 * S,
-  uint8_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q15(
-  const arm_biquad_casd_df1_inst_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q31(
-  const arm_biquad_casd_df1_inst_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages      number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q31(
-  arm_biquad_casd_df1_inst_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_f32(
-  const arm_biquad_casd_df1_inst_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_f32(
-  arm_biquad_casd_df1_inst_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q31;
-
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA  points to the first input matrix structure
-   * @param[in]       *pSrcB  points to the second input matrix structure
-   * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst,
-  q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_f32(
-  const arm_matrix_instance_f32 * pSrcA,
-  const arm_matrix_instance_f32 * pSrcB,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q15(
-  const arm_matrix_instance_q15 * pSrcA,
-  const arm_matrix_instance_q15 * pSrcB,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q31(
-  const arm_matrix_instance_q31 * pSrcA,
-  const arm_matrix_instance_q31 * pSrcB,
-  arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[in]  scale scale factor
-   * @param[out] *pDst points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_f32(
-  const arm_matrix_instance_f32 * pSrc,
-  float32_t scale,
-  arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q15(
-  const arm_matrix_instance_q15 * pSrc,
-  q15_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q31(
-  const arm_matrix_instance_q31 * pSrc,
-  q31_t scaleFract,
-  int32_t shift,
-  arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q31(
-  arm_matrix_instance_q31 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q31_t * pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q15(
-  arm_matrix_instance_q15 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  q15_t * pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_f32(
-  arm_matrix_instance_f32 * S,
-  uint16_t nRows,
-  uint16_t nColumns,
-  float32_t * pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0_FAMILY
-    q15_t A1;
-    q15_t A2;
-#else
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
-    q15_t state[3];       /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;               /**< The proportional gain. */
-    float32_t Ki;               /**< The integral gain. */
-    float32_t Kd;               /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] *S      points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_f32(
-  arm_pid_instance_f32 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_f32(
-  arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q31(
-  arm_pid_instance_q31 * S,
-  int32_t resetStateFlag);
-
-
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @return none
-   */
-
-  void arm_pid_reset_q31(
-  arm_pid_instance_q31 * S);
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q15(
-  arm_pid_instance_q15 * S,
-  int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the q15 PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_q15(
-  arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;           /**< nValues */
-    float32_t x1;               /**< x1 */
-    float32_t xSpacing;         /**< xSpacing */
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    float32_t *pData;   /**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q31_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q15_t *pData;       /**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;   /**< number of rows in the data table. */
-    uint16_t numCols;   /**< number of columns in the data table. */
-    q7_t *pData;                /**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q15;
-
-  arm_status arm_cfft_radix2_init_q15(
-  arm_cfft_radix2_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  void arm_cfft_radix2_q15(
-  const arm_cfft_radix2_instance_q15 * S,
-  q15_t * pSrc);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-  arm_status arm_cfft_radix4_init_q15(
-  arm_cfft_radix4_instance_q15 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  void arm_cfft_radix4_q15(
-  const arm_cfft_radix4_instance_q15 * S,
-  q15_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix2_instance_q31;
-
-  arm_status arm_cfft_radix2_init_q31(
-  arm_cfft_radix2_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  void arm_cfft_radix2_q31(
-  const arm_cfft_radix2_instance_q31 * S,
-  q31_t * pSrc);
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                 /**< length of the FFT. */
-    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
-    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-
-  void arm_cfft_radix4_q31(
-  const arm_cfft_radix4_instance_q31 * S,
-  q31_t * pSrc);
-
-  arm_status arm_cfft_radix4_init_q31(
-  arm_cfft_radix4_instance_q31 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix2_init_f32(
-  arm_cfft_radix2_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix2_f32(
-  const arm_cfft_radix2_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
-    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
-    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
-  arm_status arm_cfft_radix4_init_f32(
-  arm_cfft_radix4_instance_f32 * S,
-  uint16_t fftLen,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-/* Deprecated */
-  void arm_cfft_radix4_f32(
-  const arm_cfft_radix4_instance_f32 * S,
-  float32_t * pSrc);
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t fftLen;                   /**< length of the FFT. */
-    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
-    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
-    uint16_t bitRevLength;             /**< bit reversal table length. */
-  } arm_cfft_instance_f32;
-
-  void arm_cfft_f32(
-  const arm_cfft_instance_f32 * S,
-  float32_t * p1,
-  uint8_t ifftFlag,
-  uint8_t bitReverseFlag);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
-    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  arm_status arm_rfft_init_q15(
-  arm_rfft_instance_q15 * S,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q15(
-  const arm_rfft_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst);
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
-    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  arm_status arm_rfft_init_q31(
-  arm_rfft_instance_q31 * S,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_q31(
-  const arm_rfft_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  arm_status arm_rfft_init_f32(
-  arm_rfft_instance_f32 * S,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint32_t fftLenReal,
-  uint32_t ifftFlagR,
-  uint32_t bitReverseFlag);
-
-  void arm_rfft_f32(
-  const arm_rfft_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-typedef struct
-  {
-    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
-    uint16_t fftLenRFFT;                        /**< length of the real sequence */
-	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
-  } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
-	arm_rfft_fast_instance_f32 * S,
-	uint16_t fftLen);
-
-void arm_rfft_fast_f32(
-  arm_rfft_fast_instance_f32 * S,
-  float32_t * p, float32_t * pOut,
-  uint8_t ifftFlag);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    float32_t normalize;                /**< normalizing factor. */
-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;              /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_f32(
-  arm_dct4_instance_f32 * S,
-  arm_rfft_instance_f32 * S_RFFT,
-  arm_cfft_radix4_instance_f32 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  float32_t normalize);
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_f32(
-  const arm_dct4_instance_f32 * S,
-  float32_t * pState,
-  float32_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q31_t normalize;                    /**< normalizing factor. */
-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q31(
-  arm_dct4_instance_q31 * S,
-  arm_rfft_instance_q31 * S_RFFT,
-  arm_cfft_radix4_instance_q31 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q31_t normalize);
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q31(
-  const arm_dct4_instance_q31 * S,
-  q31_t * pState,
-  q31_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q15_t normalize;                    /**< normalizing factor. */
-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q15(
-  arm_dct4_instance_q15 * S,
-  arm_rfft_instance_q15 * S_RFFT,
-  arm_cfft_radix4_instance_q15 * S_CFFT,
-  uint16_t N,
-  uint16_t Nby2,
-  q15_t normalize);
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q15(
-  const arm_dct4_instance_q15 * S,
-  q15_t * pState,
-  q15_t * pInlineBuffer);
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scale scale factor to be applied
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_f32(
-  float32_t * pSrc,
-  float32_t scale,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q7(
-  q7_t * pSrc,
-  q7_t scaleFract,
-  int8_t shift,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q15(
-  q15_t * pSrc,
-  q15_t scaleFract,
-  int8_t shift,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q31(
-  q31_t * pSrc,
-  q31_t scaleFract,
-  int8_t shift,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t blockSize,
-  float32_t * result);
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q7(
-  q7_t * pSrcA,
-  q7_t * pSrcB,
-  uint32_t blockSize,
-  q31_t * result);
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t blockSize,
-  q63_t * result);
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q7(
-  q7_t * pSrc,
-  int8_t shiftBits,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q15(
-  q15_t * pSrc,
-  int8_t shiftBits,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q31(
-  q31_t * pSrc,
-  int8_t shiftBits,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_f32(
-  float32_t * pSrc,
-  float32_t offset,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q7(
-  q7_t * pSrc,
-  q7_t offset,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q15(
-  q15_t * pSrc,
-  q15_t offset,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q31(
-  q31_t * pSrc,
-  q31_t offset,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Copies the elements of a floating-point vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q7 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q7(
-  q7_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q15 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q31 vector.
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-  /**
-   * @brief  Fills a constant value into a floating-point vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_f32(
-  float32_t value,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q7(
-  q7_t value,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q15(
-  q15_t value,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector.
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q31(
-  q31_t value,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
- * @return none.
- */
-
-  void arm_conv_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-  /**
-   * @brief Convolution of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-
-  void arm_conv_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
- * @return none.
- */
-
-  void arm_conv_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_conv_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-    /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_conv_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-    /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q7 sequences
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-/**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  uint32_t firstIndex,
-  uint32_t numPoints);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                      /**< decimation factor. */
-    uint16_t numTaps;               /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                          /**< decimation factor. */
-    uint16_t numTaps;                   /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_f32;
-
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_f32(
-  const arm_fir_decimate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_f32(
-  arm_fir_decimate_instance_f32 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q15(
-  const arm_fir_decimate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q15(
-  arm_fir_decimate_instance_q15 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q31(
-  const arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q31(
-  arm_fir_decimate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q31(
-  arm_fir_decimate_instance_q31 * S,
-  uint16_t numTaps,
-  uint8_t M,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q15(
-  const arm_fir_interpolate_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q15(
-  arm_fir_interpolate_instance_q15 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q31(
-  const arm_fir_interpolate_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q31(
-  arm_fir_interpolate_instance_q31 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_f32(
-  const arm_fir_interpolate_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_f32(
-  arm_fir_interpolate_instance_f32 * S,
-  uint8_t L,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cas_df1_32x64_q31(
-  const arm_biquad_cas_df1_32x64_ins_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cas_df1_32x64_init_q31(
-  arm_biquad_cas_df1_32x64_ins_q31 * S,
-  uint8_t numStages,
-  q31_t * pCoeffs,
-  q63_t * pState,
-  uint8_t postShift);
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f32(
-  const arm_biquad_cascade_df2T_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f32(
-  arm_biquad_cascade_df2T_instance_f32 * S,
-  uint8_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q15(
-  arm_fir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pCoeffs,
-  q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_lattice_q15(
-  const arm_fir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q31(
-  arm_fir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pCoeffs,
-  q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_q31(
-  const arm_fir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
- * @param[in] *pState points to the state buffer.  The array is of length numStages.
- * @return none.
- */
-
-  void arm_fir_lattice_init_f32(
-  arm_fir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pCoeffs,
-  float32_t * pState);
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_f32(
-  const arm_fir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_f32(
-  const arm_iir_lattice_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_f32(
-  arm_iir_lattice_instance_f32 * S,
-  uint16_t numStages,
-  float32_t * pkCoeffs,
-  float32_t * pvCoeffs,
-  float32_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q31(
-  const arm_iir_lattice_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_q31(
-  arm_iir_lattice_instance_q31 * S,
-  uint16_t numStages,
-  q31_t * pkCoeffs,
-  q31_t * pvCoeffs,
-  q31_t * pState,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q15(
-  const arm_iir_lattice_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-  void arm_iir_lattice_init_q15(
-  arm_iir_lattice_instance_q15 * S,
-  uint16_t numStages,
-  q15_t * pkCoeffs,
-  q15_t * pvCoeffs,
-  q15_t * pState,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_f32(
-  const arm_lms_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_init_f32(
-  arm_lms_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return    none.
-   */
-
-  void arm_lms_init_q15(
-  arm_lms_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_q15(
-  const arm_lms_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-
-  } arm_lms_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_q31(
-  const arm_lms_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_init_q31(
-  arm_lms_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint32_t postShift);
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that control filter coefficient updates. */
-    float32_t energy;    /**< saves previous frame energy. */
-    float32_t x0;        /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_f32(
-  arm_lms_norm_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pRef,
-  float32_t * pOut,
-  float32_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_f32(
-  arm_lms_norm_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  float32_t mu,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q31(
-  arm_lms_norm_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pRef,
-  q31_t * pOut,
-  q31_t * pErr,
-  uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q31(
-  arm_lms_norm_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  q31_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;   /**< bit shift applied to coefficients. */
-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
-    q15_t energy;        /**< saves previous frame energy. */
-    q15_t x0;            /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q15(
-  arm_lms_norm_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pRef,
-  q15_t * pOut,
-  q15_t * pErr,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q15(
-  arm_lms_norm_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  q15_t mu,
-  uint32_t blockSize,
-  uint8_t postShift);
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_f32(
-  float32_t * pSrcA,
-  uint32_t srcALen,
-  float32_t * pSrcB,
-  uint32_t srcBLen,
-  float32_t * pDst);
-
-
-   /**
-   * @brief Correlation of Q15 sequences
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @return none.
-   */
-  void arm_correlate_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
-
-
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @return none.
-   */
-
-  void arm_correlate_fast_opt_q15(
-  q15_t * pSrcA,
-  uint32_t srcALen,
-  q15_t * pSrcB,
-  uint32_t srcBLen,
-  q15_t * pDst,
-  q15_t * pScratch);
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q31(
-  q31_t * pSrcA,
-  uint32_t srcALen,
-  q31_t * pSrcB,
-  uint32_t srcBLen,
-  q31_t * pDst);
-
-
-
- /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
-   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
-   * @return none.
-   */
-
-  void arm_correlate_opt_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst,
-  q15_t * pScratch1,
-  q15_t * pScratch2);
-
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q7(
-  q7_t * pSrcA,
-  uint32_t srcALen,
-  q7_t * pSrcB,
-  uint32_t srcBLen,
-  q7_t * pDst);
-
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_f32(
-  arm_fir_sparse_instance_f32 * S,
-  float32_t * pSrc,
-  float32_t * pDst,
-  float32_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_f32(
-  arm_fir_sparse_instance_f32 * S,
-  uint16_t numTaps,
-  float32_t * pCoeffs,
-  float32_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q31(
-  arm_fir_sparse_instance_q31 * S,
-  q31_t * pSrc,
-  q31_t * pDst,
-  q31_t * pScratchIn,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q31(
-  arm_fir_sparse_instance_q31 * S,
-  uint16_t numTaps,
-  q31_t * pCoeffs,
-  q31_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q15(
-  arm_fir_sparse_instance_q15 * S,
-  q15_t * pSrc,
-  q15_t * pDst,
-  q15_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q15(
-  arm_fir_sparse_instance_q15 * S,
-  uint16_t numTaps,
-  q15_t * pCoeffs,
-  q15_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q7(
-  arm_fir_sparse_instance_q7 * S,
-  q7_t * pSrc,
-  q7_t * pDst,
-  q7_t * pScratchIn,
-  q31_t * pScratchOut,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q7(
-  arm_fir_sparse_instance_q7 * S,
-  uint16_t numTaps,
-  q7_t * pCoeffs,
-  q7_t * pState,
-  int32_t * pTapDelay,
-  uint16_t maxDelay,
-  uint32_t blockSize);
-
-
-  /*
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees
-   * @param[out] *pSinVal points to the processed sine output.
-   * @param[out] *pCosVal points to the processed cos output.
-   * @return none.
-   */
-
-  void arm_sin_cos_f32(
-  float32_t theta,
-  float32_t * pSinVal,
-  float32_t * pCcosVal);
-
-  /*
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees
-   * @param[out] *pSinVal points to the processed sine output.
-   * @param[out] *pCosVal points to the processed cosine output.
-   * @return none.
-   */
-
-  void arm_sin_cos_q31(
-  q31_t theta,
-  q31_t * pSinVal,
-  q31_t * pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   *
-   * \par
-   * \image html PID.gif "Proportional Integral Derivative Controller"
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.
-   * The proportional value determines the reaction to the current error,
-   * the integral value determines the reaction based on the sum of recent errors,
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
-   * A separate instance structure must be defined for each PID Controller.
-   * There are separate instance structure declarations for each of the 3 supported data types.
-   *
-   * \par Reset Functions
-   * There is also an associated reset function for each data type which clears the state array.
-   *
-   * \par Initialization Functions
-   * There is also an associated initialization function for each data type.
-   * The initialization function performs the following operations:
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.
-   *
-   * \par
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
-   *
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the fixed-point versions of the PID Controller functions.
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   */
-
-
-  static __INLINE float32_t arm_pid_f32(
-  arm_pid_instance_f32 * S,
-  float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 64-bit accumulator.
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
-   * Thus, if the accumulator result overflows it wraps around rather than clip.
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
-   */
-
-  static __INLINE q31_t arm_pid_q31(
-  arm_pid_instance_q31 * S,
-  q31_t in)
-  {
-    q63_t acc;
-    q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using a 64-bit internal accumulator.
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-
-  static __INLINE q15_t arm_pid_q15(
-  arm_pid_instance_q15 * S,
-  q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-#ifndef ARM_MATH_CM0_FAMILY
-    __SIMD32_TYPE *vstate;
-
-    /* Implementation of PID controller */
-
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD(S->A0, in);
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    vstate = __SIMD32_CONST(S->state);
-    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
-
-#else
-    /* acc = A0 * x[n]  */
-    acc = ((q31_t) S->A0) * in;
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc += (q31_t) S->A1 * S->state[0];
-    acc += (q31_t) S->A2 * S->state[1];
-
-#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f32(
-  const arm_matrix_instance_f32 * src,
-  arm_matrix_instance_f32 * dst);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   */
-
-  static __INLINE void arm_clarke_f32(
-  float32_t Ia,
-  float32_t Ib,
-  float32_t * pIalpha,
-  float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta =
-      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
-  }
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_clarke_q31(
-  q31_t Ia,
-  q31_t Ib,
-  q31_t * pIalpha,
-  q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out]  *pDst    output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q31(
-  q7_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   */
-
-
-  static __INLINE void arm_inv_clarke_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pIa,
-  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
-  }
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_inv_clarke_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pIa,
-  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out] *pDst     output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q15(
-  q7_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
-   * from the stationary to the moving reference frame and control the spatial relationship between
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-
-  static __INLINE void arm_park_f32(
-  float32_t Ialpha,
-  float32_t Ibeta,
-  float32_t * pId,
-  float32_t * pIq,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
-  }
-
-  /**
-   * @brief  Park transform for Q31 version
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output rotor reference frame d
-   * @param[out]      *pIq   points to output rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_park_q31(
-  q31_t Ialpha,
-  q31_t Ibeta,
-  q31_t * pId,
-  q31_t * pIq,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_float(
-  q7_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output.
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   */
-
-  static __INLINE void arm_inv_park_f32(
-  float32_t Id,
-  float32_t Iq,
-  float32_t * pIalpha,
-  float32_t * pIbeta,
-  float32_t sinVal,
-  float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for	Q31 version
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_inv_park_q31(
-  q31_t Id,
-  q31_t Iq,
-  q31_t * pIalpha,
-  q31_t * pIbeta,
-  q31_t sinVal,
-  q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_float(
-  q31_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   *
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table
-   * if x is below input range and returns last value of table if x is above range.
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
-   * @param[in] x input sample to process
-   * @return y processed output sample.
-   *
-   */
-
-  static __INLINE float32_t arm_linear_interp_f32(
-  arm_linear_interp_instance_f32 * S,
-  float32_t x)
-  {
-
-    float32_t y;
-    float32_t x0, x1;                            /* Nearest input values */
-    float32_t y0, y1;                            /* Nearest output values */
-    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
-    int32_t i;                                   /* Index variable */
-    float32_t *pYData = S->pYData;               /* pointer to output table */
-
-    /* Calculation of index */
-    i = (int32_t) ((x - S->x1) / xSpacing);
-
-    if(i < 0)
-    {
-      /* Iniatilize output for below specified range as least output value of table */
-      y = pYData[0];
-    }
-    else if((uint32_t)i >= S->nValues)
-    {
-      /* Iniatilize output for above specified range as last output value of table */
-      y = pYData[S->nValues - 1];
-    }
-    else
-    {
-      /* Calculation of nearest input values */
-      x0 = S->x1 + i * xSpacing;
-      x1 = S->x1 + (i + 1) * xSpacing;
-
-      /* Read of nearest output values */
-      y0 = pYData[i];
-      y1 = pYData[i + 1];
-
-      /* Calculation of output */
-      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
-    }
-
-    /* returns output value */
-    return (y);
-  }
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q31_t arm_linear_interp_q31(
-  q31_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20);
-
-    if(index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* shift left by 11 to keep fract in 1.31 format */
-      fract = (x & 0x000FFFFF) << 11;
-
-      /* Read two nearest output values from the index in 1.31(q31) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
-      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
-      /* Convert y to 1.31 format */
-      return (y << 1u);
-
-    }
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q15_t arm_linear_interp_q15(
-  q15_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q63_t y;                                     /* output */
-    q15_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                               /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-    if(index >= (int32_t)(nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else if(index < 0)
-    {
-      return (pYData[0]);
-    }
-    else
-    {
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-      y = ((q63_t) y0 * (0xFFFFF - fract));
-
-      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-      y += ((q63_t) y1 * (fract));
-
-      /* convert y to 1.15 format */
-      return (y >> 20);
-    }
-
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-
-
-  static __INLINE q7_t arm_linear_interp_q7(
-  q7_t * pYData,
-  q31_t x,
-  uint32_t nValues)
-  {
-    q31_t y;                                     /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    uint32_t index;                              /* Index to read nearest output values */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    if (x < 0)
-    {
-      return (pYData[0]);
-    }
-    index = (x >> 20) & 0xfff;
-
-
-    if(index >= (nValues - 1))
-    {
-      return (pYData[nValues - 1]);
-    }
-    else
-    {
-
-      /* 20 bits for the fractional part */
-      /* fract is in 12.20 format */
-      fract = (x & 0x000FFFFF);
-
-      /* Read two nearest output values from the index and are in 1.7(q7) format */
-      y0 = pYData[index];
-      y1 = pYData[index + 1u];
-
-      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-      y = ((y0 * (0xFFFFF - fract)));
-
-      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-      y += (y1 * fract);
-
-      /* convert y to 1.7(q7) format */
-      return (y >> 20u);
-
-    }
-
-  }
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  sin(x).
-   */
-
-  float32_t arm_sin_f32(
-  float32_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q31_t arm_sin_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q15_t arm_sin_q15(
-  q15_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  cos(x).
-   */
-
-  float32_t arm_cos_f32(
-  float32_t x);
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q31_t arm_cos_q31(
-  q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q15_t arm_cos_q15(
-  q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate, and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in     input value.
-   * @param[out] *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-
-  static __INLINE arm_status arm_sqrt_f32(
-  float32_t in,
-  float32_t * pOut)
-  {
-    if(in > 0)
-    {
-
-//      #if __FPU_USED
-#if (__FPU_USED == 1) && defined ( __CC_ARM   )
-      *pOut = __sqrtf(in);
-#else
-      *pOut = sqrtf(in);
-#endif
-
-      return (ARM_MATH_SUCCESS);
-    }
-    else
-    {
-      *pOut = 0.0f;
-      return (ARM_MATH_ARGUMENT_ERROR);
-    }
-
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out]  *pOut square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-  q31_t in,
-  q31_t * pOut);
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out]  *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-  q15_t in,
-  q15_t * pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-
-
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const int32_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  static __INLINE void arm_circularRead_f32(
-  int32_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  int32_t * dst,
-  int32_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (int32_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value  */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q15_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q15(
-  q15_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q15_t * dst,
-  q15_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q15_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  uint16_t * writeOffset,
-  int32_t bufferInc,
-  const q7_t * src,
-  int32_t srcInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the input sample to the circular buffer */
-      circBuffer[wOffset] = *src;
-
-      /* Update the input pointer */
-      src += srcInc;
-
-      /* Circularly update wOffset.  Watch out for positive and negative value */
-      wOffset += bufferInc;
-      if(wOffset >= L)
-        wOffset -= L;
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q7(
-  q7_t * circBuffer,
-  int32_t L,
-  int32_t * readOffset,
-  int32_t bufferInc,
-  q7_t * dst,
-  q7_t * dst_base,
-  int32_t dst_length,
-  int32_t dstInc,
-  uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-    {
-      /* copy the sample from the circular buffer to the destination buffer */
-      *dst = circBuffer[rOffset];
-
-      /* Update the input pointer */
-      dst += dstInc;
-
-      if(dst == (q7_t *) dst_end)
-      {
-        dst = dst_base;
-      }
-
-      /* Circularly update rOffset.  Watch out for positive and negative value */
-      rOffset += bufferInc;
-
-      if(rOffset >= L)
-      {
-        rOffset -= L;
-      }
-
-      /* Decrement the loop counter */
-      i--;
-    }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_mean_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q63_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult);
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_f32(
-  float32_t * pSrc,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q31(
-  q31_t * pSrc,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q15(
-  q15_t * pSrc,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  uint32_t numSamples,
-  q31_t * realResult,
-  q31_t * imagResult);
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  uint32_t numSamples,
-  q63_t * realResult,
-  q63_t * imagResult);
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  uint32_t numSamples,
-  float32_t * realResult,
-  float32_t * imagResult);
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q15(
-  q15_t * pSrcCmplx,
-  q15_t * pSrcReal,
-  q15_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q31(
-  q31_t * pSrcCmplx,
-  q31_t * pSrcReal,
-  q31_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_f32(
-  float32_t * pSrcCmplx,
-  float32_t * pSrcReal,
-  float32_t * pCmplxDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *result is output pointer
-   * @param[in]  index is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * result,
-  uint32_t * index);
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-  void arm_min_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q7(
-  q7_t * pSrc,
-  uint32_t blockSize,
-  q7_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q15(
-  q15_t * pSrc,
-  uint32_t blockSize,
-  q15_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q31(
-  q31_t * pSrc,
-  uint32_t blockSize,
-  q31_t * pResult,
-  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_f32(
-  float32_t * pSrc,
-  uint32_t blockSize,
-  float32_t * pResult,
-  uint32_t * pIndex);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q15(
-  q15_t * pSrcA,
-  q15_t * pSrcB,
-  q15_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q31(
-  q31_t * pSrcA,
-  q31_t * pSrcB,
-  q31_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_f32(
-  float32_t * pSrcA,
-  float32_t * pSrcB,
-  float32_t * pDst,
-  uint32_t numSamples);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return none.
-   */
-  void arm_float_to_q31(
-  float32_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return          none
-   */
-  void arm_float_to_q15(
-  float32_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector.
-   * @param[in]       *pSrc points to the floating-point input vector
-   * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector
-   * @return          none
-   */
-  void arm_float_to_q7(
-  float32_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q15(
-  q31_t * pSrc,
-  q15_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q7(
-  q31_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_float(
-  q15_t * pSrc,
-  float32_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q31(
-  q15_t * pSrc,
-  q31_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q7(
-  q15_t * pSrc,
-  q7_t * pDst,
-  uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate.
-  * @param[in] Y interpolation coordinate.
-  * @return out interpolated value.
-  */
-
-
-  static __INLINE float32_t arm_bilinear_interp_f32(
-  const arm_bilinear_interp_instance_f32 * S,
-  float32_t X,
-  float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
-       || yIndex > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q31_t arm_bilinear_interp_q31(
-  arm_bilinear_interp_instance_q31 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20u);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20u);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return (acc << 2u);
-
-  }
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q15_t arm_bilinear_interp_q15(
-  arm_bilinear_interp_instance_q15 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                              /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return (acc >> 36);
-
-  }
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q7_t arm_bilinear_interp_q7(
-  arm_bilinear_interp_instance_q7 * S,
-  q31_t X,
-  q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                              /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-    /* Care taken for table outside boundary */
-    /* Returns zero output when values are outside table boundary */
-    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
-    {
-      return (0);
-    }
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return (acc >> 40);
-
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-#if   defined ( __CC_ARM ) //Keil
-//SMMLAR
-  #define multAcc_32x32_keep32_R(a, x, y) \
-  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMLSR
-  #define multSub_32x32_keep32_R(a, x, y) \
-  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMULR
-  #define mult_32x32_keep32_R(a, x, y) \
-  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-//Enter low optimization region - place directly above function definition
-  #define LOW_OPTIMIZATION_ENTER \
-     _Pragma ("push")         \
-     _Pragma ("O1")
-
-//Exit low optimization region - place directly after end of function definition
-  #define LOW_OPTIMIZATION_EXIT \
-     _Pragma ("pop")
-
-//Enter low optimization region - place directly above function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-//Exit low optimization region - place directly after end of function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ICCARM__) //IAR
- //SMMLA
-  #define multAcc_32x32_keep32_R(a, x, y) \
-  a += (q31_t) (((q63_t) x * y) >> 32)
-
- //SMMLS
-  #define multSub_32x32_keep32_R(a, x, y) \
-  a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
-  #define mult_32x32_keep32_R(a, x, y) \
-  a = (q31_t) (((q63_t) x * y ) >> 32)
-
-//Enter low optimization region - place directly above function definition
-  #define LOW_OPTIMIZATION_ENTER \
-     _Pragma ("optimize=low")
-
-//Exit low optimization region - place directly after end of function definition
-  #define LOW_OPTIMIZATION_EXIT
-
-//Enter low optimization region - place directly above function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
-     _Pragma ("optimize=low")
-
-//Exit low optimization region - place directly after end of function definition
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__GNUC__)
- //SMMLA
-  #define multAcc_32x32_keep32_R(a, x, y) \
-  a += (q31_t) (((q63_t) x * y) >> 32)
-
- //SMMLS
-  #define multSub_32x32_keep32_R(a, x, y) \
-  a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
-  #define mult_32x32_keep32_R(a, x, y) \
-  a = (q31_t) (((q63_t) x * y ) >> 32)
-
-  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
-
-  #define LOW_OPTIMIZATION_EXIT
-
-  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-
-/**
- *
- * End of file.
- */

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0.h

@@ -1,682 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm0plus.h

@@ -1,793 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
-  @{
- */
-
-/*  CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-#if (__VTOR_PRESENT == 1)
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-#else
-       uint32_t RESERVED0;
-#endif
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm3.h

@@ -1,1627 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4.h

@@ -1,1772 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-    \brief      Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cm4_simd.h

@@ -1,673 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmFunc.h

@@ -1,636 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_cmInstr.h

@@ -1,688 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V3.20
- * @date     05. March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2)); 
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-   uint32_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc000.h

@@ -1,813 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup SC000
-  @{
- */
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
-                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
-
-#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC000_REV
-    #define __SC000_REV             0x0000
-    #warning "__SC000_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED0[1];
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-       uint32_t RESERVED1[154];
-  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/* SCB Security Features Register Definitions */
-#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
-#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
-
-#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
-#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of SC000 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/CMSIS/Include/core_sc300.h

@@ -1,1598 +0,0 @@
-/**************************************************************************//**
- * @file     core_sc300.h
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V3.20
- * @date     25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup SC3000
-  @{
- */
-
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
-                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
-
-#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC300_REV
-    #define __SC300_REV               0x0000
-    #warning "__SC300_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-    \brief      Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-       uint32_t RESERVED1[1];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
-  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
-  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
-  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
-  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
-  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
-  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
-  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
-  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
-  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
-  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
-  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
-  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
-       uint32_t RESERVED0[1];
-  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
-  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
-  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
-       uint32_t RESERVED1[1];
-  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
-  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
-  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
-       uint32_t RESERVED2[1];
-  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
-  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
-  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-    \brief      Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/** \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
-  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-       uint32_t RESERVED0[2];
-  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-       uint32_t RESERVED1[55];
-  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-       uint32_t RESERVED2[131];
-  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-       uint32_t RESERVED3[759];
-  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
-  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-       uint32_t RESERVED4[1];
-  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-       uint32_t RESERVED5[39];
-  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-       uint32_t RESERVED7[8];
-  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-    \brief      Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Type definitions for the Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/** \brief  Set Priority Grouping
-
-  The function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  The function reads the priority grouping field from the NVIC Interrupt Controller.
-
-    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    The function reads the active register in NVIC and returns the active bit.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not active.
-    \return             1  Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    The function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value, and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
-    \param [in]     PriorityGroup  Used priority group.
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-    \param [in]       SubPriority  Subpriority value (starting from 0).
-    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    The function decodes an interrupt priority value with a given priority group to
-    preemptive priority value and subpriority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-    \param [in]     PriorityGroup  Used priority group.
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-    \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions ITM Functions
-    \brief   Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief  ITM Send Character
-
-    The function transmits a character via the ITM channel 0, and
-    \li Just returns when no debugger is connected that has booked the output.
-    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
-    \param [in]     ch  Character to transmit.
-
-    \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    The function inputs a character via the external variable \ref ITM_RxBuffer.
-
-    \return             Received character.
-    \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
-    \return          0  No character available.
-    \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc176x/CMSIS/SConscript

@@ -1,26 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-
-src = ['CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c']
-
-# add for startup script
-if rtconfig.PLATFORM in ['gcc']:
-    src += ['CM3/DeviceSupport/NXP/LPC17xx/startup/gcc/startup_LPC17xx.s']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
-    src += ['CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s']
-elif rtconfig.PLATFORM in ['iccarm']:
-    src += ['CM3/DeviceSupport/NXP/LPC17xx/startup/iar/startup_LPC17xx.s']
-
-CPPPATH = [cwd + '/CM3/DeviceSupport/NXP/LPC17xx/',
-    cwd + '/CMSIS/Include']
-
-if GetDepend(['RT_USING_BSP_CMSIS']):
-    CPPPATH += [cwd + '/CM3/CoreSupport']
-    src += ['CM3/CoreSupport/core_cm3.c']
-
-group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/nxp/lpc/lpc176x/Kconfig

@@ -12,4 +12,5 @@ osource "$PKGS_DIR/Kconfig"
 config SOC_LPC176
     bool
     select ARCH_ARM_CORTEX_M3
+    select PKG_USING_NXP_LPC_DRIVER
     default y

bsp/nxp/lpc/lpc176x/SConstruct

@@ -9,6 +9,23 @@ else:
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
 
+def bsp_pkg_check():
+    import subprocess
+
+    check_paths = [
+        os.path.join("packages", "nxp-lpc-series-latest"),
+    ]
+
+    need_update = not all(os.path.exists(p) for p in check_paths)
+
+    if need_update:
+        print("\n==============================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("==============================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
 TARGET = 'rtthread-lpc17xx.' + rtconfig.TARGET_EXT
 
 DefaultEnvironment(tools=[])

bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.c

@@ -1,358 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.c
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version  V2.00
- * @date     13. September 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#include <stdint.h>
-
-
-/* define compiler specific symbols */
-#if defined   ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm           /*!< asm keyword for TASKING Compiler          */
-  #define __INLINE         inline          /*!< inline keyword for TASKING Compiler       */
-
-#endif
-
-
-/* ##########################  Core Instruction Access  ######################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-__ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-__ASM void __CLREX(void)
-{
-  clrex
-}
-#endif /* __ARMCC_VERSION  */
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t  __get_CONTROL(void)
-{
-  mrs r0, control
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_CONTROL(uint32_t control)
-{
-  msr control, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_IPSR(void)
-{
-  mrs r0, ipsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_APSR(void)
-{
-  mrs r0, apsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_xPSR(void)
-{
-  mrs r0, xpsr
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PSP(void)
-{
-  mrs r0, psp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
-  msr psp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_MSP(void)
-{
-  mrs r0, msp
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
-  msr msp, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t  __get_BASEPRI(void)
-{
-  mrs r0, basepri
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
-  msr basepri, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t __get_PRIMASK(void)
-{
-  mrs r0, primask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
-  msr primask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask Register.
-
-    \return               Fault Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM uint32_t  __get_FAULTMASK(void)
-{
-  mrs r0, faultmask
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-/** \brief  Set the Fault Mask
-
-     This function assigns the given value to the Fault Mask Register.
-
-    \param [in]    faultMask  Fault Mask value value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
-  msr faultmask, r0
-  bx lr
-}
-#endif /*  __ARMCC_VERSION  */
-
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* obsolete */
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* obsolete */
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-

bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cm3.h

@@ -1,1242 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.01
- * @date     06. December 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M3
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
- @ingroup CMSIS
-
-  List of Lint messages which will be suppressed and not shown:
-    - not yet checked
-  .
-  Note:  To re-enable a Message, insert a space before 'lint' *
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  @ingroup CMSIS
-  This file defines all structures and symbols for CMSIS core:
-    - CMSIS version number
-    - Cortex-M core
-    - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-
-#if defined ( __CC_ARM   )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined   (  __GNUC__  )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined   (  __TASKING__  )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define     __I     volatile                /*!< defines 'read only' permissions      */
-#else
-  #define     __I     volatile const          /*!< defines 'read only' permissions      */
-#endif
-#define     __O     volatile                  /*!< defines 'write only' permissions     */
-#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  @ingroup CMSIS
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
- @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t RELOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t CURR;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __IO  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
-       uint32_t RESERVED3[29];
-  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
-  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
-  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
-       uint32_t RESERVED4[43];
-  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
-  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
-       uint32_t RESERVED5[6];
-  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
-  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
-  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
-  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
-  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
-  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
-  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
-  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
-  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
-  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
-  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
-  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
-  Type definitions for the Cortex-M Interrupt Type Register
-  @{
- */
-
-/** \brief  Structure type to access the Interrupt Type Register.
- */
-typedef struct
-{
-       uint32_t RESERVED0;
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
-#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
-#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
-
-/*@}*/ /* end of group CMSIS_InterruptType */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
-#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
-#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
-#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
-#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
-  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  @ingroup CMSIS
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/** \brief  Set Priority Grouping
-
-  This function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                       |
-                (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
-    \return                Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    This function reads the active register in NVIC and returns the active bit.
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The returned priority value can be used for NVIC_SetPriority(...) function
-
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    This function decodes an interrupt priority value with the given priority group to
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The priority value can be retrieved with NVIC_GetPriority(...) function
-
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->RELOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->CURR   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief  ITM Send Character
-
-    This function transmits a character via the ITM channel 0.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    This function inputs a character via external variable ITM_RxBuffer.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \return             Received character
-    \return         -1  No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    This function checks external variable ITM_RxBuffer whether a character is available or not.
-    It returns '1' if a character is available and '0' if no character is available.
-
-    \return          0  No character available
-    \return          1  Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
-
-/*lint -restore */

bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmFunc.h

@@ -1,844 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.01
- * @date     06. December 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H__
-#define __CORE_CMFUNC_H__
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-/* ARM armcc specific functions */
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_CONTROL(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_CONTROL(uint32_t control);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_IPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_APSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_xPSR(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PSP(uint32_t topOfProcStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_MSP(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_MSP(uint32_t topOfMainStack);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_PRIMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_PRIMASK(uint32_t priMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_BASEPRI(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_BASEPRI(uint32_t basePri);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-#endif /*  __ARMCC_VERSION  */ 
- 
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          uint32_t __get_FAULTMASK(void);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-#if       (__ARMCC_VERSION <  400000)
-extern          void __set_FAULTMASK(uint32_t faultMask);
-#else  /* (__ARMCC_VERSION >= 400000) */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & 1);
-}
-#endif /*  __ARMCC_VERSION  */ 
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
- #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* IAR iccarm specific functions */
-
-#if defined (__ICCARM__)
-  #include <intrinsics.h>                     /* IAR Intrinsics   */
-#endif
-
-#pragma diag_suppress=Pe940
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __enable_irq                              __enable_interrupt
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-#define __disable_irq                             __disable_interrupt
-
-
-/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
-/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static uint32_t __get_IPSR(void)
-{
-  __ASM("mrs r0, ipsr");
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static uint32_t __get_APSR(void)
-{
-  __ASM("mrs r0, apsr");
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static uint32_t __get_xPSR(void)
-{
-  __ASM("mrs r0, psr");           // assembler does not know "xpsr"
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static uint32_t __get_PSP(void)
-{
-  __ASM("mrs r0, psp");
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM("msr psp, r0");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-static uint32_t __get_MSP(void)
-{
-  __ASM("mrs r0, msp");
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM("msr msp, r0");
-}
- 
-
-/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __enable_fault_irq(void)
-{
-  __ASM ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-static __INLINE void __disable_fault_irq(void)
-{
-  __ASM ("cpsid f");
-}
-
-
-/* intrinsic unsigned long __get_BASEPRI( void );   (see intrinsic.h) */
-/* intrinsic void __set_BASEPRI( unsigned long );   (see intrinsic.h) */
-/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
-/* intrinsic void __set_FAULTMASK(unsigned long);   (see intrinsic.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmrs r0, fpscr"); 
-#else
-  return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM("vmsr fpscr, r0");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1)
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1)
-  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H__ */

bsp/nxp/lpc/lpc178x/CMSIS/CM3/CoreSupport/core_cmInstr.h

@@ -1,775 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.01
- * @date     06. December 2010
- *
- * @note
- * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H__
-#define __CORE_CMINSTR_H__
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
-/* ARM armcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor, 
-    so that all instructions following the ISB are fetched from cache or 
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier. 
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before 
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-extern uint32_t __REV16(uint32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#if (__ARMCC_VERSION < 400677)
-extern int32_t __REVSH(int32_t value);
-#else  /* (__ARMCC_VERSION >= 400677)  */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif /* __ARMCC_VERSION  */ 
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#if (__ARMCC_VERSION < 400000)
-extern void __CLREX(void);
-#else  /* (__ARMCC_VERSION >= 400000)  */
-#define __CLREX                           __clrex
-#endif /* __ARMCC_VERSION  */ 
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz 
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
-/* IAR iccarm specific functions */
-
-#include <intrinsics.h>                     /* IAR Intrinsics   */
-
-#pragma diag_suppress=Pe940
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                           __no_operation
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-static __INLINE  void __WFI(void)
-{
-  __ASM ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-static __INLINE  void __WFE(void)
-{
-  __ASM ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-static __INLINE  void __SEV(void)
-{
-  __ASM ("sev");
-}
-
-
-/* intrinsic     void __ISB(void)            (see intrinsics.h) */
-/* intrinsic     void __DSB(void)            (see intrinsics.h) */
-/* intrinsic     void __DMB(void)            (see intrinsics.h) */
-/* intrinsic uint32_t __REV(uint32_t value)  (see intrinsics.h) */
-/* intrinsic          __SSAT                 (see intrinsics.h) */
-/* intrinsic          __USAT                 (see intrinsics.h) */
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __REV16(uint32_t value)
-{
-  __ASM("rev16 r0, r0");
-}
-
-
-/* intrinsic uint32_t __REVSH(uint32_t value)  (see intrinsics.h */
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static uint32_t __RBIT(uint32_t value)
-{
-  __ASM("rbit r0, r0");
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-static uint8_t __LDREXB(volatile uint8_t *addr)
-{
-  __ASM("ldrexb r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-static uint16_t __LDREXH(volatile uint16_t *addr)
-{
-  __ASM("ldrexh r0, [r0]");
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-/* intrinsic unsigned long __LDREX(unsigned long *)  (see intrinsics.h) */
-static uint32_t __LDREXW(volatile uint32_t *addr)
-{
-  __ASM("ldrex r0, [r0]");
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-  __ASM("strexb r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-  __ASM("strexh r0, r0, [r1]");
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long)  (see intrinsics.h )*/
-static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-  __ASM("strex r0, r0, [r1]");
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-static __INLINE void __CLREX(void)
-{
-  __ASM ("clrex");
-}
-
-/* intrinsic   unsigned char __CLZ( unsigned long )      (see intrinsics.h) */
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#pragma diag_default=Pe940
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor, 
-    so that all instructions following the ISB are fetched from cache or 
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier. 
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before 
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-  
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H__ */

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/LPC177x_8x.h

@@ -1,1443 +0,0 @@
-/**********************************************************************
-* $Id: LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $		LPC177x_8x.h			2011-06-02
-*//**
-* @file		LPC177x_8x.h
-* @brief	Cortex-M3 Core Peripheral Access Layer Header File for
-*			NXP LPC177x_8x Series.
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef __LPC177x_8x_H__
-#define __LPC177x_8x_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC177x_8x Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  Reserved0_IRQn                = 13,       /*!< Reserved                                         */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  MCI_IRQn                      = 29,       /*!< SD/MMC card I/F Interrupt                        */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /*!< USB Activity interrupt                           */
-  CANActivity_IRQn              = 34,       /*!< CAN Activity interrupt                           */
-  UART4_IRQn                    = 35,       /*!< UART4 Interrupt                                  */
-  SSP2_IRQn                     = 36,       /*!< SSP2 Interrupt                                   */
-  LCD_IRQn                      = 37,       /*!< LCD Interrupt                                    */
-  GPIO_IRQn                     = 38,       /*!< GPIO Interrupt                                   */
-  PWM0_IRQn                     = 39,       /*!< PWM0 Interrupt                                   */
-  EEPROM_IRQn                   = 40,       /*!< EEPROM Interrupt                           */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-//#include "system_LPC177x_8x.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;                   /*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                    /*!< Offset: 0x080 (R/W)  PLL0 Control Register */
-  __IO uint32_t PLL0CFG;                    /*!< Offset: 0x084 (R/W)  PLL0 Configuration Register */
-  __I  uint32_t PLL0STAT;                   /*!< Offset: 0x088 (R/ )  PLL0 Status Register */
-  __O  uint32_t PLL0FEED;                   /*!< Offset: 0x08C ( /W)  PLL0 Feed Register */
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;                    /*!< Offset: 0x0A0 (R/W)  PLL1 Control Register */
-  __IO uint32_t PLL1CFG;                    /*!< Offset: 0x0A4 (R/W)  PLL1 Configuration Register */
-  __I  uint32_t PLL1STAT;                   /*!< Offset: 0x0A8 (R/ )  PLL1 Status Register */
-  __O  uint32_t PLL1FEED;                   /*!< Offset: 0x0AC ( /W)  PLL1 Feed Register */
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;                       /*!< Offset: 0x0C0 (R/W)  Power Control Register */
-  __IO uint32_t PCONP;                      /*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
-       uint32_t RESERVED3[14];
-  __IO uint32_t EMCCLKSEL;                  /*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
-  __IO uint32_t CCLKSEL;                    /*!< Offset: 0x104 (R/W)  CPU Clock Selection Register */
-  __IO uint32_t USBCLKSEL;                  /*!< Offset: 0x108 (R/W)  USB Clock Selection Register */
-  __IO uint32_t CLKSRCSEL;                  /*!< Offset: 0x10C (R/W)  Clock Source Select Register */
-  __IO uint32_t	CANSLEEPCLR;                /*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
-  __IO uint32_t	CANWAKEFLAGS;               /*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                     /*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
-       uint32_t RESERVED5[1];
-  __IO uint32_t EXTMODE;                    /*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
-  __IO uint32_t EXTPOLAR;                   /*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                       /*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                        /*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
-  __IO uint32_t IRCTRIM;                    /*!< Offset: 0x1A4 (R/W) Clock Dividers                     */
-  __IO uint32_t PCLKSEL;                    /*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
-       uint32_t RESERVED8[3];
-  __IO uint32_t LCD_CFG;                    /*!< Offset: 0x1B8 (R/W)  LCD Configuration and clocking control Register */
-       uint32_t RESERVED9[1];
-  __IO uint32_t USBIntSt;                   /*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
-  __IO uint32_t DMAREQSEL;                  /*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
-  __IO uint32_t CLKOUTCFG;                  /*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
-  __IO uint32_t RSTCON0;                    /*!< Offset: 0x1CC (R/W)  RESET Control0 Register */
-  __IO uint32_t RSTCON1;                    /*!< Offset: 0x1D0 (R/W)  RESET Control1 Register */
-       uint32_t RESERVED10[2];
-  __IO uint32_t EMCDLYCTL;                  /*!< Offset: 0x1DC (R/W) SDRAM programmable delays          */
-  __IO uint32_t EMCCAL;                     /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t P0_0;				/* 0x000 */
-  __IO uint32_t P0_1;
-  __IO uint32_t P0_2;
-  __IO uint32_t P0_3;
-  __IO uint32_t P0_4;
-  __IO uint32_t P0_5;
-  __IO uint32_t P0_6;
-  __IO uint32_t P0_7;
-
-  __IO uint32_t P0_8;				/* 0x020 */
-  __IO uint32_t P0_9;
-  __IO uint32_t P0_10;
-  __IO uint32_t P0_11;
-  __IO uint32_t P0_12;
-  __IO uint32_t P0_13;
-  __IO uint32_t P0_14;
-  __IO uint32_t P0_15;
-
-  __IO uint32_t P0_16;				/* 0x040 */
-  __IO uint32_t P0_17;
-  __IO uint32_t P0_18;
-  __IO uint32_t P0_19;
-  __IO uint32_t P0_20;
-  __IO uint32_t P0_21;
-  __IO uint32_t P0_22;
-  __IO uint32_t P0_23;
-
-  __IO uint32_t P0_24;				/* 0x060 */
-  __IO uint32_t P0_25;
-  __IO uint32_t P0_26;
-  __IO uint32_t P0_27;
-  __IO uint32_t P0_28;
-  __IO uint32_t P0_29;
-  __IO uint32_t P0_30;
-  __IO uint32_t P0_31;
-
-  __IO uint32_t P1_0;				/* 0x080 */
-  __IO uint32_t P1_1;
-  __IO uint32_t P1_2;
-  __IO uint32_t P1_3;
-  __IO uint32_t P1_4;
-  __IO uint32_t P1_5;
-  __IO uint32_t P1_6;
-  __IO uint32_t P1_7;
-
-  __IO uint32_t P1_8;				/* 0x0A0 */
-  __IO uint32_t P1_9;
-  __IO uint32_t P1_10;
-  __IO uint32_t P1_11;
-  __IO uint32_t P1_12;
-  __IO uint32_t P1_13;
-  __IO uint32_t P1_14;
-  __IO uint32_t P1_15;
-
-  __IO uint32_t P1_16;				/* 0x0C0 */
-  __IO uint32_t P1_17;
-  __IO uint32_t P1_18;
-  __IO uint32_t P1_19;
-  __IO uint32_t P1_20;
-  __IO uint32_t P1_21;
-  __IO uint32_t P1_22;
-  __IO uint32_t P1_23;
-
-  __IO uint32_t P1_24;				/* 0x0E0 */
-  __IO uint32_t P1_25;
-  __IO uint32_t P1_26;
-  __IO uint32_t P1_27;
-  __IO uint32_t P1_28;
-  __IO uint32_t P1_29;
-  __IO uint32_t P1_30;
-  __IO uint32_t P1_31;
-
-  __IO uint32_t P2_0;				/* 0x100 */
-  __IO uint32_t P2_1;
-  __IO uint32_t P2_2;
-  __IO uint32_t P2_3;
-  __IO uint32_t P2_4;
-  __IO uint32_t P2_5;
-  __IO uint32_t P2_6;
-  __IO uint32_t P2_7;
-
-  __IO uint32_t P2_8;				/* 0x120 */
-  __IO uint32_t P2_9;
-  __IO uint32_t P2_10;
-  __IO uint32_t P2_11;
-  __IO uint32_t P2_12;
-  __IO uint32_t P2_13;
-  __IO uint32_t P2_14;
-  __IO uint32_t P2_15;
-
-  __IO uint32_t P2_16;				/* 0x140 */
-  __IO uint32_t P2_17;
-  __IO uint32_t P2_18;
-  __IO uint32_t P2_19;
-  __IO uint32_t P2_20;
-  __IO uint32_t P2_21;
-  __IO uint32_t P2_22;
-  __IO uint32_t P2_23;
-
-  __IO uint32_t P2_24;				/* 0x160 */
-  __IO uint32_t P2_25;
-  __IO uint32_t P2_26;
-  __IO uint32_t P2_27;
-  __IO uint32_t P2_28;
-  __IO uint32_t P2_29;
-  __IO uint32_t P2_30;
-  __IO uint32_t P2_31;
-
-  __IO uint32_t P3_0;				/* 0x180 */
-  __IO uint32_t P3_1;
-  __IO uint32_t P3_2;
-  __IO uint32_t P3_3;
-  __IO uint32_t P3_4;
-  __IO uint32_t P3_5;
-  __IO uint32_t P3_6;
-  __IO uint32_t P3_7;
-
-  __IO uint32_t P3_8;				/* 0x1A0 */
-  __IO uint32_t P3_9;
-  __IO uint32_t P3_10;
-  __IO uint32_t P3_11;
-  __IO uint32_t P3_12;
-  __IO uint32_t P3_13;
-  __IO uint32_t P3_14;
-  __IO uint32_t P3_15;
-
-  __IO uint32_t P3_16;				/* 0x1C0 */
-  __IO uint32_t P3_17;
-  __IO uint32_t P3_18;
-  __IO uint32_t P3_19;
-  __IO uint32_t P3_20;
-  __IO uint32_t P3_21;
-  __IO uint32_t P3_22;
-  __IO uint32_t P3_23;
-
-  __IO uint32_t P3_24;				/* 0x1E0 */
-  __IO uint32_t P3_25;
-  __IO uint32_t P3_26;
-  __IO uint32_t P3_27;
-  __IO uint32_t P3_28;
-  __IO uint32_t P3_29;
-  __IO uint32_t P3_30;
-  __IO uint32_t P3_31;
-
-  __IO uint32_t P4_0;				/* 0x200 */
-  __IO uint32_t P4_1;
-  __IO uint32_t P4_2;
-  __IO uint32_t P4_3;
-  __IO uint32_t P4_4;
-  __IO uint32_t P4_5;
-  __IO uint32_t P4_6;
-  __IO uint32_t P4_7;
-
-  __IO uint32_t P4_8;				/* 0x220 */
-  __IO uint32_t P4_9;
-  __IO uint32_t P4_10;
-  __IO uint32_t P4_11;
-  __IO uint32_t P4_12;
-  __IO uint32_t P4_13;
-  __IO uint32_t P4_14;
-  __IO uint32_t P4_15;
-
-  __IO uint32_t P4_16;				/* 0x240 */
-  __IO uint32_t P4_17;
-  __IO uint32_t P4_18;
-  __IO uint32_t P4_19;
-  __IO uint32_t P4_20;
-  __IO uint32_t P4_21;
-  __IO uint32_t P4_22;
-  __IO uint32_t P4_23;
-
-  __IO uint32_t P4_24;				/* 0x260 */
-  __IO uint32_t P4_25;
-  __IO uint32_t P4_26;
-  __IO uint32_t P4_27;
-  __IO uint32_t P4_28;
-  __IO uint32_t P4_29;
-  __IO uint32_t P4_30;
-  __IO uint32_t P4_31;
-
-  __IO uint32_t P5_0;				/* 0x280 */
-  __IO uint32_t P5_1;
-  __IO uint32_t P5_2;
-  __IO uint32_t P5_3;
-  __IO uint32_t P5_4;				/* 0x290 */
-} LPC_IOCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  __IO uint32_t DIR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t MASK;
-  __IO uint32_t PIN;
-  __IO uint32_t SET;
-  __O  uint32_t CLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-  __I  uint32_t CR2;					/*!< Offset: 0x034 Capture Register 2 (R/ ) */
-  __I  uint32_t CR3;					/*!< Offset: 0x038 Capture Register 3 (R/ ) */
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;					/*!< Offset: 0x040 Match Register 4 (R/W) */
-  __IO uint32_t MR5;					/*!< Offset: 0x044 Match Register 5 (R/W) */
-  __IO uint32_t MR6;					/*!< Offset: 0x048 Match Register 6 (R/W) */
-  __IO uint32_t PCR;					/*!< Offset: 0x04C PWM Control Register (R/W) */
-  __IO uint32_t LER;					/*!< Offset: 0x050 Load Enable Register (R/W) */
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;					/*!< Offset: 0x070 Counter Control Register (R/W) */
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
-/* There are three types of UARTs on the chip:
-(1) UART0,UART2, and UART3 are the standard UART.
-(2) UART1 is the standard with modem capability.
-(3) USART(UART4) is the sync/async UART with smart card capability.
-More details can be found on the Users Manual. */
-
-#if 0
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART_TypeDef;
-#else
-typedef struct
-{
-	union
-	{
-		__I  uint8_t  RBR;
-		__O  uint8_t  THR;
-		__IO uint8_t  DLL;
-		uint32_t RESERVED0;
-	};
-	union
-	{
-		__IO uint8_t  DLM;
-		__IO uint32_t IER;
-	};
-	union
-	{
-		__I  uint32_t IIR;
-		__O  uint8_t  FCR;
-	};
-	__IO uint8_t  LCR;
-	uint8_t  RESERVED1[7];//Reserved
-	__I  uint8_t  LSR;
-	uint8_t  RESERVED2[7];//Reserved
-	__IO uint8_t  SCR;
-	uint8_t  RESERVED3[3];//Reserved
-	__IO uint32_t ACR;
-	__IO uint8_t  ICR;
-	uint8_t  RESERVED4[3];//Reserved
-	__IO uint8_t  FDR;
-	uint8_t  RESERVED5[7];//Reserved
-	__IO uint8_t  TER;
-	uint8_t  RESERVED8[27];//Reserved
-	__IO uint8_t  RS485CTRL;
-	uint8_t  RESERVED9[3];//Reserved
-	__IO uint8_t  ADRMATCH;
-	uint8_t  RESERVED10[3];//Reserved
-	__IO uint8_t  RS485DLY;
-	uint8_t  RESERVED11[3];//Reserved
-	__I  uint8_t  FIFOLVL;
-}LPC_UART_TypeDef;
-#endif
-
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART1_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-  __IO uint32_t  ICR;                   /*!< Offset: 0x024 irDA Control Register (R/W) */
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-  __IO uint32_t  OSR;                   /*!< Offset: 0x02C Over sampling Register (R/W) */
-  __O  uint32_t  POP;                   /*!< Offset: 0x030 NHP Pop Register (W) */
-  __IO uint32_t  MODE;                  /*!< Offset: 0x034 NHP Mode selection Register (W) */
-       uint32_t  RESERVED0[2];
-  __IO uint32_t  HDEN;                  /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
-       uint32_t  RESERVED1;
-  __IO uint32_t  SCI_CTRL;				/*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-  __IO uint32_t  SYNCCTRL;              /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
-  __IO uint32_t  TER;                   /*!< Offset: 0x05C Transmit Enable Register (R/W) */
-       uint32_t  RESERVED2[989];
-  __I  uint32_t  CFG;                   /*!< Offset: 0xFD4 Configuration Register (R) */
-  __O  uint32_t  INTCE;                 /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
-  __O  uint32_t  INTSE;                 /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
-  __I  uint32_t  INTS;                  /*!< Offset: 0xFE0 Interrupt Status Register (R) */
-  __I  uint32_t  INTE;                  /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
-  __O  uint32_t  INTCS;                 /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
-  __O  uint32_t  INTSS;                 /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
-       uint32_t  RESERVED3[3];
-  __I  uint32_t  MID;                   /*!< Offset: 0xFFC Module Identification Register (R) */
-} LPC_UART4_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
-  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t DAO;
-  __IO uint32_t DAI;
-  __O  uint32_t TXFIFO;
-  __I  uint32_t RXFIFO;
-  __I  uint32_t STATE;
-  __IO uint32_t DMA1;
-  __IO uint32_t DMA2;
-  __IO uint32_t IRQ;
-  __IO uint32_t TXRATE;
-  __IO uint32_t RXRATE;
-  __IO uint32_t TXBITRATE;
-  __IO uint32_t RXBITRATE;
-  __IO uint32_t TXMODE;
-  __IO uint32_t RXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-  __IO uint32_t ERSTATUS;
-  __IO uint32_t ERCONTROL;
-  __IO uint32_t ERCOUNTERS;
-       uint32_t RESERVED22;
-  __IO uint32_t ERFIRSTSTAMP0;
-  __IO uint32_t ERFIRSTSTAMP1;
-  __IO uint32_t ERFIRSTSTAMP2;
-       uint32_t RESERVED23;
-  __IO uint32_t ERLASTSTAMP0;
-  __IO uint32_t ERLASTSTAMP1;
-  __IO uint32_t ERLASTSTAMP2;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  MOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t TC;
-  __O  uint8_t  FEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t TV;
-       uint32_t RESERVED2;
-  __IO uint32_t WARNINT;
-  __IO uint32_t WINDOW;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CTRL;
-  __IO uint32_t CNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t CON;
-  __O  uint32_t CON_SET;
-  __O  uint32_t CON_CLR;
-  __I  uint32_t CAPCON;
-  __O  uint32_t CAPCON_SET;
-  __O  uint32_t CAPCON_CLR;
-  __IO uint32_t TC0;
-  __IO uint32_t TC1;
-  __IO uint32_t TC2;
-  __IO uint32_t LIM0;
-  __IO uint32_t LIM1;
-  __IO uint32_t LIM2;
-  __IO uint32_t MAT0;
-  __IO uint32_t MAT1;
-  __IO uint32_t MAT2;
-  __IO uint32_t DT;
-  __IO uint32_t CP;
-  __IO uint32_t CAP0;
-  __IO uint32_t CAP1;
-  __IO uint32_t CAP2;
-  __I  uint32_t INTEN;
-  __O  uint32_t INTEN_SET;
-  __O  uint32_t INTEN_CLR;
-  __I  uint32_t CNTCON;
-  __O  uint32_t CNTCON_SET;
-  __O  uint32_t CNTCON_CLR;
-  __I  uint32_t INTF;
-  __O  uint32_t INTF_SET;
-  __O  uint32_t INTF_CLR;
-  __O  uint32_t CAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t CON;
-  __I  uint32_t STAT;
-  __IO uint32_t CONF;
-  __I  uint32_t POS;
-  __IO uint32_t MAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP0;
-  __IO uint32_t LOAD;
-  __I  uint32_t TIME;
-  __I  uint32_t VEL;
-  __I  uint32_t CAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTERPHA;
-  __IO uint32_t FILTERPHB;
-  __IO uint32_t FILTERINX;
-  __IO uint32_t WINDOW;
-  __IO uint32_t INXCMP1;
-  __IO uint32_t INXCMP2;
-       uint32_t RESERVED0[993];
-  __O  uint32_t IEC;
-  __O  uint32_t IES;
-  __I  uint32_t INTSTAT;
-  __I  uint32_t IE;
-  __O  uint32_t CLR;
-  __O  uint32_t SET;
-} LPC_QEI_TypeDef;
-
-/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLOCK;
-  __IO uint32_t ARGUMENT;
-  __IO uint32_t COMMAND;
-  __I  uint32_t RESP_CMD;
-  __I  uint32_t RESP0;
-  __I  uint32_t RESP1;
-  __I  uint32_t RESP2;
-  __I  uint32_t RESP3;
-  __IO uint32_t DATATMR;
-  __IO uint32_t DATALEN;
-  __IO uint32_t DATACTRL;
-  __I  uint32_t DATACNT;
-  __I  uint32_t STATUS;
-  __O  uint32_t CLEAR;
-  __IO uint32_t MASK0;
-       uint32_t RESERVED0[2];
-  __I  uint32_t FIFOCNT;
-       uint32_t RESERVED1[13];
-  __IO uint32_t FIFO;
-} LPC_MCI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-	///Offset: 0x00000000 - Acceptance Filter Register
-	__IO uint32_t AFMR;
-
-	///Offset: 0x00000004 - Standard Frame Individual Start Address Register
-	__IO uint32_t SFF_sa;
-
-	///Offset: 0x00000008 - Standard Frame Group Start Address Register
-	__IO uint32_t SFF_GRP_sa;
-
-	///Offset: 0x0000000C - Extended Frame Start Address Register
-	__IO uint32_t EFF_sa;
-
-	///Offset: 0x00000010 - Extended Frame Group Start Address Register
-	__IO uint32_t EFF_GRP_sa;
-
-	///Offset: 0x00000014 - End of AF Tables register
-	__IO uint32_t ENDofTable;
-
-	///Offset: 0x00000018 - LUT Error Address register
-	__I  uint32_t LUTerrAd;
-
-	///Offset: 0x0000001C - LUT Error Register
-	__I  uint32_t LUTerr;
-
-	///Offset: 0x00000020 - CAN Central Transmit Status Register
-	__IO uint32_t FCANIE;
-
-	///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
-	__IO uint32_t FCANIC0;
-
-	///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
-	__IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t TxSR;
-  __I  uint32_t RxSR;
-  __I  uint32_t MSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-	///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
-	__IO uint32_t MOD;
-
-	///Offset: 0x00000004 - Command bits that affect the state
-	__O  uint32_t CMR;
-
-	///Offset: 0x00000008 - Global Controller Status and Error Counters
-	__IO uint32_t GSR;
-
-	///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
-	__I  uint32_t ICR;
-
-	///Offset: 0x00000010 - Interrupt Enable Register
-	__IO uint32_t IER;
-
-	///Offset: 0x00000014 - Bus Timing Register
-	__IO uint32_t BTR;
-
-	///Offset: 0x00000018 - Error Warning Limit
-	__IO uint32_t EWL;
-
-	///Offset: 0x0000001C - Status Register
-	__I  uint32_t SR;
-
-	///Offset: 0x00000020 - Receive frame status
-	__IO uint32_t RFS;
-
-	///Offset: 0x00000024 - Received Identifier
-	__IO uint32_t RID;
-
-	///Offset: 0x00000028 - Received data bytes 1-4
-	__IO uint32_t RDA;
-
-	///Offset: 0x0000002C - Received data bytes 5-8
-	__IO uint32_t RDB;
-
-	///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
-	__IO uint32_t TFI1;
-
-	///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
-	__IO uint32_t TID1;
-
-	///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
-	__IO uint32_t TDA1;
-
-	///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
-	__IO uint32_t TDB1;
-
-	///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
-	__IO uint32_t TFI2;
-
-	///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
-	__IO uint32_t TID2;
-
-	///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
-	__IO uint32_t TDA2;
-
-	///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
-	__IO uint32_t TDB2;
-
-	///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
-	__IO uint32_t TFI3;
-
-	///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
-	__IO uint32_t TID3;
-
-	///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
-	__IO uint32_t TDA3;
-
-	///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
-	__IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t IntStat;
-  __I  uint32_t IntTCStat;
-  __O  uint32_t IntTCClear;
-  __I  uint32_t IntErrStat;
-  __O  uint32_t IntErrClr;
-  __I  uint32_t RawIntTCStat;
-  __I  uint32_t RawIntErrStat;
-  __I  uint32_t EnbldChns;
-  __IO uint32_t SoftBReq;
-  __IO uint32_t SoftSReq;
-  __IO uint32_t SoftLBReq;
-  __IO uint32_t SoftLSReq;
-  __IO uint32_t Config;
-  __IO uint32_t Sync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t CSrcAddr;
-  __IO uint32_t CDestAddr;
-  __IO uint32_t CLLI;
-  __IO uint32_t CControl;
-  __IO uint32_t CConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t Revision;             /* USB Host Registers                 */
-  __IO uint32_t Control;
-  __IO uint32_t CommandStatus;
-  __IO uint32_t InterruptStatus;
-  __IO uint32_t InterruptEnable;
-  __IO uint32_t InterruptDisable;
-  __IO uint32_t HCCA;
-  __I  uint32_t PeriodCurrentED;
-  __IO uint32_t ControlHeadED;
-  __IO uint32_t ControlCurrentED;
-  __IO uint32_t BulkHeadED;
-  __IO uint32_t BulkCurrentED;
-  __I  uint32_t DoneHead;
-  __IO uint32_t FmInterval;
-  __I  uint32_t FmRemaining;
-  __I  uint32_t FmNumber;
-  __IO uint32_t PeriodicStart;
-  __IO uint32_t LSTreshold;
-  __IO uint32_t RhDescriptorA;
-  __IO uint32_t RhDescriptorB;
-  __IO uint32_t RhStatus;
-  __IO uint32_t RhPortStatus1;
-  __IO uint32_t RhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t IntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t IntEn;
-  __O  uint32_t IntSet;
-  __O  uint32_t IntClr;
-  __IO uint32_t StCtrl;
-  __IO uint32_t Tmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t DevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t DevIntEn;
-  __O  uint32_t DevIntClr;
-  __O  uint32_t DevIntSet;
-
-  __O  uint32_t CmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t CmdData;
-
-  __I  uint32_t RxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t TxData;
-  __I  uint32_t RxPLen;
-  __O  uint32_t TxPLen;
-  __IO uint32_t Ctrl;
-  __O  uint32_t DevIntPri;
-
-  __I  uint32_t EpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t EpIntEn;
-  __O  uint32_t EpIntClr;
-  __O  uint32_t EpIntSet;
-  __O  uint32_t EpIntPri;
-
-  __IO uint32_t ReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t EpInd;
-  __IO uint32_t MaxPSize;
-
-  __I  uint32_t DMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t DMARClr;
-  __O  uint32_t DMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t UDCAH;
-  __I  uint32_t EpDMASt;
-  __O  uint32_t EpDMAEn;
-  __O  uint32_t EpDMADis;
-  __I  uint32_t DMAIntSt;
-  __IO uint32_t DMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t EoTIntSt;
-  __O  uint32_t EoTIntClr;
-  __O  uint32_t EoTIntSet;
-  __I  uint32_t NDDRIntSt;
-  __O  uint32_t NDDRIntClr;
-  __O  uint32_t NDDRIntSet;
-  __I  uint32_t SysErrIntSt;
-  __O  uint32_t SysErrIntClr;
-  __O  uint32_t SysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  union {
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_TX;
-  };
-  __IO  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[824];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __I  uint32_t RxFilterWoLStatus;
-  __O  uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-/*------------- LCD controller (LCD) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t TIMH;                   /* LCD Registers                      */
-  __IO uint32_t TIMV;
-  __IO uint32_t POL;
-  __IO uint32_t LE;
-  __IO uint32_t UPBASE;
-  __IO uint32_t LPBASE;
-  __IO uint32_t CTRL;
-  __IO uint32_t INTMSK;
-  __I  uint32_t INTRAW;
-  __I  uint32_t INTSTAT;
-  __O  uint32_t INTCLR;
-  __I  uint32_t UPCURR;
-  __I  uint32_t LPCURR;
-       uint32_t RESERVED0[115];
-  __IO uint32_t PAL[128];
-       uint32_t RESERVED1[256];
-  __IO uint32_t CRSR_IMG[256];
-  __IO uint32_t CRSR_CTRL;
-  __IO uint32_t CRSR_CFG;
-  __IO uint32_t CRSR_PAL0;
-  __IO uint32_t CRSR_PAL1;
-  __IO uint32_t CRSR_XY;
-  __IO uint32_t CRSR_CLIP;
-       uint32_t RESERVED2[2];
-  __IO uint32_t CRSR_INTMSK;
-  __O  uint32_t CRSR_INTCLR;
-  __I  uint32_t CRSR_INTRAW;
-  __I  uint32_t CRSR_INTSTAT;
-} LPC_LCD_TypeDef;
-
-/*------------- External Memory Controller (EMC) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t Control;
-  __I  uint32_t Status;
-  __IO uint32_t Config;
-       uint32_t RESERVED0[5];
-  __IO uint32_t DynamicControl;
-  __IO uint32_t DynamicRefresh;
-  __IO uint32_t DynamicReadConfig;
-       uint32_t RESERVED1[1];
-  __IO uint32_t DynamicRP;
-  __IO uint32_t DynamicRAS;
-  __IO uint32_t DynamicSREX;
-  __IO uint32_t DynamicAPR;
-  __IO uint32_t DynamicDAL;
-  __IO uint32_t DynamicWR;
-  __IO uint32_t DynamicRC;
-  __IO uint32_t DynamicRFC;
-  __IO uint32_t DynamicXSR;
-  __IO uint32_t DynamicRRD;
-  __IO uint32_t DynamicMRD;
-       uint32_t RESERVED2[9];
-  __IO uint32_t StaticExtendedWait;
-       uint32_t RESERVED3[31];
-  __IO uint32_t DynamicConfig0;
-  __IO uint32_t DynamicRasCas0;
-       uint32_t RESERVED4[6];
-  __IO uint32_t DynamicConfig1;
-  __IO uint32_t DynamicRasCas1;
-       uint32_t RESERVED5[6];
-  __IO uint32_t DynamicConfig2;
-  __IO uint32_t DynamicRasCas2;
-       uint32_t RESERVED6[6];
-  __IO uint32_t DynamicConfig3;
-  __IO uint32_t DynamicRasCas3;
-       uint32_t RESERVED7[38];
-  __IO uint32_t StaticConfig0;
-  __IO uint32_t StaticWaitWen0;
-  __IO uint32_t StaticWaitOen0;
-  __IO uint32_t StaticWaitRd0;
-  __IO uint32_t StaticWaitPage0;
-  __IO uint32_t StaticWaitWr0;
-  __IO uint32_t StaticWaitTurn0;
-       uint32_t RESERVED8[1];
-  __IO uint32_t StaticConfig1;
-  __IO uint32_t StaticWaitWen1;
-  __IO uint32_t StaticWaitOen1;
-  __IO uint32_t StaticWaitRd1;
-  __IO uint32_t StaticWaitPage1;
-  __IO uint32_t StaticWaitWr1;
-  __IO uint32_t StaticWaitTurn1;
-       uint32_t RESERVED9[1];
-  __IO uint32_t StaticConfig2;
-  __IO uint32_t StaticWaitWen2;
-  __IO uint32_t StaticWaitOen2;
-  __IO uint32_t StaticWaitRd2;
-  __IO uint32_t StaticWaitPage2;
-  __IO uint32_t StaticWaitWr2;
-  __IO uint32_t StaticWaitTurn2;
-       uint32_t RESERVED10[1];
-  __IO uint32_t StaticConfig3;
-  __IO uint32_t StaticWaitWen3;
-  __IO uint32_t StaticWaitOen3;
-  __IO uint32_t StaticWaitRd3;
-  __IO uint32_t StaticWaitPage3;
-  __IO uint32_t StaticWaitWr3;
-  __IO uint32_t StaticWaitTurn3;
-} LPC_EMC_TypeDef;
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t MODE;
-  __IO uint32_t SEED;
-  union {
-  __I  uint32_t SUM;
-  __O  uint32_t WR_DATA_DWORD;
-  __O  uint16_t WR_DATA_WORD;
-       uint16_t RESERVED_WORD;
-  __O  uint8_t WR_DATA_BYTE;
-       uint8_t RESERVED_BYTE[3];
-  };
-} LPC_CRC_TypeDef;
-
-/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t CMD;			/* 0x0080 */
-  __IO uint32_t ADDR;
-  __IO uint32_t WDATA;
-  __IO uint32_t RDATA;
-  __IO uint32_t WSTATE;			/* 0x0090 */
-  __IO uint32_t CLKDIV;
-  __IO uint32_t PWRDWN;			/* 0x0098 */
-       uint32_t RESERVED0[975];
-  __IO uint32_t INT_CLR_ENABLE;	/* 0x0FD8 */
-  __IO uint32_t INT_SET_ENABLE;
-  __IO uint32_t INT_STATUS;		/* 0x0FE0 */
-  __IO uint32_t INT_ENABLE;
-  __IO uint32_t INT_CLR_STATUS;
-  __IO uint32_t INT_SET_STATUS;
-} LPC_EEPROM_TypeDef;
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_PERI_RAM_BASE     (0x20000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHBRAM1_BASE      (0x20004000UL)
-#define LPC_AHB_BASE          (0x20080000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM0_BASE         (LPC_APB0_BASE + 0x14000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_UART4_BASE        (LPC_APB1_BASE + 0x24000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_SSP2_BASE         (LPC_APB1_BASE + 0x2C000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_MCI_BASE          (LPC_APB1_BASE + 0x40000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x00100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x00120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x00140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x00160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x00180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x001A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x001C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x001E0)
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x04000)
-#define LPC_LCD_BASE          (LPC_AHB_BASE  + 0x08000)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-#define LPC_CRC_BASE          (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x18000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x18020)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x18040)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x18060)
-#define LPC_GPIO4_BASE        (LPC_AHB_BASE  + 0x18080)
-#define LPC_GPIO5_BASE        (LPC_AHB_BASE  + 0x180A0)
-#define LPC_EMC_BASE          (LPC_AHB_BASE  + 0x1C000)
-
-#define LPC_EEPROM_BASE       (LPC_FLASH_BASE+ 0x200080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_UART4             ((LPC_UART4_TypeDef     *) LPC_UART4_BASE    )
-#define LPC_PWM0              ((LPC_PWM_TypeDef       *) LPC_PWM0_BASE     )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef     *) LPC_IOCON_BASE    )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_SSP2              ((LPC_SSP_TypeDef       *) LPC_SSP2_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_MCI               ((LPC_MCI_TypeDef       *) LPC_MCI_BASE      )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_LCD               ((LPC_LCD_TypeDef       *) LPC_LCD_BASE      )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_GPIO5             ((LPC_GPIO_TypeDef      *) LPC_GPIO5_BASE    )
-#define LPC_EMC               ((LPC_EMC_TypeDef       *) LPC_EMC_BASE      )
-#define LPC_CRC               ((LPC_CRC_TypeDef       *) LPC_CRC_BASE      )
-#define LPC_EEPROM            ((LPC_EEPROM_TypeDef    *) LPC_EEPROM_BASE   )
-
-#endif  // __LPC177x_8x_H__

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_iram_iar.icf

@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x10000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x00000000;
-define symbol __ICFEDIT_region_RAM_start__ = 0x10000140;
-define symbol __ICFEDIT_region_RAM_end__   = 0x1000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define symbol _AHB_RAM_start__  = 0x20080000;
-define symbol _AHB_RAM_end__    = 0x200BFFFF;
-define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
-place in RAM_region     { readonly };
-place in RAM_region     { readwrite,
-                          block CSTACK, block HEAP };
-place in AHB_RAM_region { section USB_RAM };

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/linker/ldscript_irom_iar.icf

@@ -1,35 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
-define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x1000FFFF;
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__   = 0x200;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define symbol _AHB_RAM_start__  = 0x20080000;
-define symbol _AHB_RAM_end__    = 0x200BFFFF;
-define region AHB_RAM_region = mem:[from _AHB_RAM_start__ to _AHB_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { section .intvec };
-place at address mem:0x2FC { section CRPKEY };
-place in ROM_region     { readonly };
-place in RAM_region     { readwrite,
-                          block CSTACK, block HEAP };
-place in AHB_RAM_region { section USB_RAM };

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s

@@ -1,301 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC177x_8x.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File
-; *           for the NXP LPC177x_8x Device Series 
-; * @version: V1.20
-; * @date:    07. October 2010
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2010 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000200
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-                DCD     TIMER0_IRQHandler         ; 17: Timer0
-                DCD     TIMER1_IRQHandler         ; 18: Timer1
-                DCD     TIMER2_IRQHandler         ; 19: Timer2
-                DCD     TIMER3_IRQHandler         ; 20: Timer3
-                DCD     UART0_IRQHandler          ; 21: UART0
-                DCD     UART1_IRQHandler          ; 22: UART1
-                DCD     UART2_IRQHandler          ; 23: UART2
-                DCD     UART3_IRQHandler          ; 24: UART3
-                DCD     PWM1_IRQHandler           ; 25: PWM1
-                DCD     I2C0_IRQHandler           ; 26: I2C0
-                DCD     I2C1_IRQHandler           ; 27: I2C1
-                DCD     I2C2_IRQHandler           ; 28: I2C2
-                DCD     SPIFI_IRQHandler          ; 29: SPIFI
-                DCD     SSP0_IRQHandler           ; 30: SSP0
-                DCD     SSP1_IRQHandler           ; 31: SSP1
-                DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-                DCD     RTC_IRQHandler            ; 33: Real Time Clock
-                DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-                DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-                DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-                DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-                DCD     ADC_IRQHandler            ; 38: A/D Converter
-                DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-                DCD     USB_IRQHandler            ; 40: USB
-                DCD     CAN_IRQHandler            ; 41: CAN
-                DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-                DCD     I2S_IRQHandler            ; 43: I2S
-                DCD     ENET_IRQHandler           ; 44: Ethernet
-                DCD     MCI_IRQHandler            ; 45: SD/MMC card I/F
-                DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-                DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-                DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-				DCD		USBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup
-				DCD		CANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup
-				DCD		UART4_IRQHandler          ; 51: UART4
-				DCD		SSP2_IRQHandler           ; 52: SSP2
-				DCD		LCD_IRQHandler            ; 53: LCD
-				DCD		GPIO_IRQHandler           ; 54: GPIO
-				DCD		PWM0_IRQHandler           ; 55: PWM0
-				DCD		EEPROM_IRQHandler         ; 56: EEPROM
-
-
-                IF      :LNOT::DEF:NO_CRP
-                AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key         DCD     0xFFFFFFFF
-                ENDIF
-
-
-                AREA    |.text|, CODE, READONLY
-
-
-; Reset Handler
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-				IMPORT  SystemInit
-                IMPORT  __main
-				LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler        [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WDT_IRQHandler            [WEAK]
-                EXPORT  TIMER0_IRQHandler         [WEAK]
-                EXPORT  TIMER1_IRQHandler         [WEAK]
-                EXPORT  TIMER2_IRQHandler         [WEAK]
-                EXPORT  TIMER3_IRQHandler         [WEAK]
-                EXPORT  UART0_IRQHandler          [WEAK]
-                EXPORT  UART1_IRQHandler          [WEAK]
-                EXPORT  UART2_IRQHandler          [WEAK]
-                EXPORT  UART3_IRQHandler          [WEAK]
-                EXPORT  PWM1_IRQHandler           [WEAK]
-                EXPORT  I2C0_IRQHandler           [WEAK]
-                EXPORT  I2C1_IRQHandler           [WEAK]
-                EXPORT  I2C2_IRQHandler           [WEAK]
-                EXPORT  SPIFI_IRQHandler          [WEAK]
-                EXPORT  SSP0_IRQHandler           [WEAK]
-                EXPORT  SSP1_IRQHandler           [WEAK]
-                EXPORT  PLL0_IRQHandler           [WEAK]
-                EXPORT  RTC_IRQHandler            [WEAK]
-                EXPORT  EINT0_IRQHandler          [WEAK]
-                EXPORT  EINT1_IRQHandler          [WEAK]
-                EXPORT  EINT2_IRQHandler          [WEAK]
-                EXPORT  EINT3_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler            [WEAK]
-                EXPORT  BOD_IRQHandler            [WEAK]
-                EXPORT  USB_IRQHandler            [WEAK]
-                EXPORT  CAN_IRQHandler            [WEAK]
-                EXPORT  DMA_IRQHandler            [WEAK]
-                EXPORT  I2S_IRQHandler            [WEAK]
-                EXPORT  ENET_IRQHandler           [WEAK]
-                EXPORT  MCI_IRQHandler            [WEAK]
-                EXPORT  MCPWM_IRQHandler          [WEAK]
-                EXPORT  QEI_IRQHandler            [WEAK]
-                EXPORT  PLL1_IRQHandler           [WEAK]
-				EXPORT  USBActivity_IRQHandler    [WEAK]
-				EXPORT  CANActivity_IRQHandler    [WEAK]
-				EXPORT  UART4_IRQHandler          [WEAK]
-				EXPORT  SSP2_IRQHandler           [WEAK]
-				EXPORT  LCD_IRQHandler            [WEAK]
-				EXPORT  GPIO_IRQHandler           [WEAK]
-				EXPORT  PWM0_IRQHandler           [WEAK]
-				EXPORT  EEPROM_IRQHandler         [WEAK]
-
-WDT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-PWM1_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPIFI_IRQHandler            
-SSP0_IRQHandler
-SSP1_IRQHandler
-PLL0_IRQHandler
-RTC_IRQHandler
-EINT0_IRQHandler
-EINT1_IRQHandler
-EINT2_IRQHandler
-EINT3_IRQHandler
-ADC_IRQHandler
-BOD_IRQHandler
-USB_IRQHandler
-CAN_IRQHandler
-DMA_IRQHandler
-I2S_IRQHandler
-ENET_IRQHandler
-MCI_IRQHandler          
-MCPWM_IRQHandler
-QEI_IRQHandler
-PLL1_IRQHandler
-USBActivity_IRQHandler
-CANActivity_IRQHandler
-UART4_IRQHandler
-SSP2_IRQHandler
-LCD_IRQHandler
-GPIO_IRQHandler
-PWM0_IRQHandler
-EEPROM_IRQHandler
-
-                B       .
-
-                ENDP
-
-
-                ALIGN
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ALIGN
-
-                ENDIF
-
-
-                END

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s

@@ -1,269 +0,0 @@
-/*****************************************************************************/
-/* startup_LPC17xx.s: Startup file for LPC17xx device series                 */
-/*****************************************************************************/
-/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
-/*****************************************************************************/
-
-
-/*
-//*** <<< Use Configuration Wizard in Context Menu >>> ***
-*/
-
-    .syntax unified
-    .cpu cortex-m3
-    .fpu softvfp
-    .thumb
-
-    .word  _sidata
-    .word  _sdata
-    .word  _edata
-    .word  _sbss
-    .word  _ebss
-
-/*
-// <h> Stack Configuration
-//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Stack_Size, 0x00000200
-    .section .stack, "w"
-    .align  3
-    .globl  __cs3_stack_mem
-    .globl  __cs3_stack_size
-__cs3_stack_mem:
-    .if     Stack_Size
-    .space  Stack_Size
-    .endif
-    .size   __cs3_stack_mem,  . - __cs3_stack_mem
-    .set    __cs3_stack_size, . - __cs3_stack_mem
-
-/* Vector Table */
-
-    .section .interrupt_vector
-    .globl  __cs3_interrupt_vector_cortex_m
-    .type   __cs3_interrupt_vector_cortex_m, %object
-
-__cs3_interrupt_vector_cortex_m:
-    .long   _estack                 /* Top of Stack                 */
-    .long   Reset_Handler               /* Reset Handler                */
-    .long   NMI_Handler                 /* NMI Handler                  */
-    .long   HardFault_Handler           /* Hard Fault Handler           */
-    .long   MemManage_Handler           /* MPU Fault Handler            */
-    .long   BusFault_Handler            /* Bus Fault Handler            */
-    .long   UsageFault_Handler          /* Usage Fault Handler          */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   SVC_Handler                 /* SVCall Handler               */
-    .long   DebugMon_Handler            /* Debug Monitor Handler        */
-    .long   0                           /* Reserved                     */
-    .long   PendSV_Handler              /* PendSV Handler               */
-    .long   SysTick_Handler             /* SysTick Handler              */
-
-    /* External Interrupts */
-    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
-    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
-    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
-    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
-    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
-    .long   UART0_IRQHandler            /* 21: UART0                        */
-    .long   UART1_IRQHandler            /* 22: UART1                        */
-    .long   UART2_IRQHandler            /* 23: UART2                        */
-    .long   UART3_IRQHandler            /* 24: UART3                        */
-    .long   PWM1_IRQHandler             /* 25: PWM1                         */
-    .long   I2C0_IRQHandler             /* 26: I2C0                         */
-    .long   I2C1_IRQHandler             /* 27: I2C1                         */
-    .long   I2C2_IRQHandler             /* 28: I2C2                         */
-    .long   SPIFI_IRQHandler            /* 29: SPIFI                        */
-    .long   SSP0_IRQHandler             /* 30: SSP0                         */
-    .long   SSP1_IRQHandler             /* 31: SSP1                         */
-    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
-    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
-    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
-    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
-    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
-    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
-    .long   ADC_IRQHandler              /* 38: A/D Converter                */
-    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
-    .long   USB_IRQHandler              /* 40: USB                          */
-    .long   CAN_IRQHandler              /* 41: CAN                          */
-    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
-    .long   I2S_IRQHandler              /* 43: I2S                          */
-    .long   ENET_IRQHandler             /* 44: Ethernet                     */
-    .long   MCI_IRQHandler              /* 45: SD/MMC Card                  */
-    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
-    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
-    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
-    .long   USBActivity_IRQHandler      /* 49: USB Activity                 */
-    .long   CANActivity_IRQHandler      /* 50: CAN Activity                 */
-    .long   UART4_IRQHandler            /* 51: UART4                        */
-    .long   SSP2_IRQHandler             /* 52: SSP2                         */
-    .long   LCD_IRQHandler              /* 53: LCD                          */
-    .long   GPIO_IRQHandler             /* 54: GPIO                         */
-    .long   PWM0_IRQHandler             /* 55: PWM0                         */
-    .long   EEPROM_IRQHandler           /* 56: EEPROM                       */
-
-    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
-
-
-/* Reset Handler */
-    .section  .text.Reset_Handler
-    .weak  Reset_Handler
-    .type  Reset_Handler, %function
-Reset_Handler:
-    .fnstart
-/* Copy the data segment initializers from flash to SRAM */
-    movs    r1, #0
-    b   LoopCopyDataInit
-
-CopyDataInit:
-    ldr r3, =_sidata
-    ldr r3, [r3, r1]
-    str r3, [r0, r1]
-    add r1, r1, #4
-
-LoopCopyDataInit:
-    ldr r0, =_sdata
-    ldr r3, =_edata
-    add r2, r0, r1
-    cmp r2, r3
-    bcc CopyDataInit
-    ldr r2, =_sbss
-    b   LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-    movs    r3, #0
-    str r3, [r2], #4
-
-LoopFillZerobss:
-    ldr r3, = _ebss
-    cmp r2, r3
-    bcc FillZerobss
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call the application's entry point.*/
-    bl  main
-    bx  lr
-
-    .pool
-    .cantunwind
-    .fnend
-    .size   Reset_Handler,.-Reset_Handler
-
-    .section ".text"
-
-/* Exception Handlers */
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   MemManage_Handler
-    .type   MemManage_Handler, %function
-MemManage_Handler:
-    B       .
-    .size   MemManage_Handler, . - MemManage_Handler
-
-    .weak   BusFault_Handler
-    .type   BusFault_Handler, %function
-BusFault_Handler:
-    B       .
-    .size   BusFault_Handler, . - BusFault_Handler
-
-    .weak   UsageFault_Handler
-    .type   UsageFault_Handler, %function
-UsageFault_Handler:
-    B       .
-    .size   UsageFault_Handler, . - UsageFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   DebugMon_Handler
-    .type   DebugMon_Handler, %function
-DebugMon_Handler:
-    B       .
-    .size   DebugMon_Handler, . - DebugMon_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-
-/* IRQ Handlers */
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ     WDT_IRQHandler
-    IRQ     TIMER0_IRQHandler
-    IRQ     TIMER1_IRQHandler
-    IRQ     TIMER2_IRQHandler
-    IRQ     TIMER3_IRQHandler
-    IRQ     UART0_IRQHandler
-    IRQ     UART1_IRQHandler
-    IRQ     UART2_IRQHandler
-    IRQ     UART3_IRQHandler
-    IRQ     PWM1_IRQHandler
-    IRQ     I2C0_IRQHandler
-    IRQ     I2C1_IRQHandler
-    IRQ     I2C2_IRQHandler
-    IRQ     SPIFI_IRQHandler
-    IRQ     SSP0_IRQHandler
-    IRQ     SSP1_IRQHandler
-    IRQ     PLL0_IRQHandler
-    IRQ     RTC_IRQHandler
-    IRQ     EINT0_IRQHandler
-    IRQ     EINT1_IRQHandler
-    IRQ     EINT2_IRQHandler
-    IRQ     EINT3_IRQHandler
-    IRQ     ADC_IRQHandler
-    IRQ     BOD_IRQHandler
-    IRQ     USB_IRQHandler
-    IRQ     CAN_IRQHandler
-    IRQ     DMA_IRQHandler
-    IRQ     I2S_IRQHandler
-    IRQ     ENET_IRQHandler
-    IRQ     MCI_IRQHandler
-    IRQ     MCPWM_IRQHandler
-    IRQ     QEI_IRQHandler
-    IRQ     PLL1_IRQHandler
-    IRQ     USBActivity_IRQHandler
-    IRQ     CANActivity_IRQHandler
-    IRQ     UART4_IRQHandler
-    IRQ     SSP2_IRQHandler
-    IRQ     LCD_IRQHandler
-    IRQ     GPIO_IRQHandler
-    IRQ     PWM0_IRQHandler
-    IRQ     EEPROM_IRQHandler
-
-    .end

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s

@@ -1,393 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC177x_8x.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File
-; *           for the NXP LPC17xx Device Series
-; * @version: V1.03
-; * @date:    09. February 2010
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (C) 2010 ARM Limited. All rights reserved.
-; *
-; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; ******************************************************************************/
-
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-        DCD     TIMER0_IRQHandler         ; 17: Timer0
-        DCD     TIMER1_IRQHandler         ; 18: Timer1
-        DCD     TIMER2_IRQHandler         ; 19: Timer2
-        DCD     TIMER3_IRQHandler         ; 20: Timer3
-        DCD     UART0_IRQHandler          ; 21: UART0
-        DCD     UART1_IRQHandler          ; 22: UART1
-        DCD     UART2_IRQHandler          ; 23: UART2
-        DCD     UART3_IRQHandler          ; 24: UART3
-        DCD     PWM1_IRQHandler           ; 25: PWM1
-        DCD     I2C0_IRQHandler           ; 26: I2C0
-        DCD     I2C1_IRQHandler           ; 27: I2C1
-        DCD     I2C2_IRQHandler           ; 28: I2C2
-        DCD     SPIFI_IRQHandler          ; 29: SPIFI
-        DCD     SSP0_IRQHandler           ; 30: SSP0
-        DCD     SSP1_IRQHandler           ; 31: SSP1
-        DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-        DCD     RTC_IRQHandler            ; 33: Real Time Clock
-        DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-        DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-        DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-        DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-        DCD     ADC_IRQHandler            ; 38: A/D Converter
-        DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-        DCD     USB_IRQHandler            ; 40: USB
-        DCD     CAN_IRQHandler            ; 41: CAN
-        DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-        DCD     I2S_IRQHandler            ; 43: I2S
-        DCD     ENET_IRQHandler           ; 44: Ethernet
-        DCD		MCI_IRQHandler		  	  ; 45: MCI Card
-        DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-		DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-		DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-	    DCD		USBActivity_IRQHandler	  ; 49: USB Activity Interrupt
-	    DCD		CANActivity_IRQHandler	  ; 50: CAN Activity Interrupt
-		DCD		UART4_IRQHandler          ; 51: UART4
-		DCD		SSP2_IRQHandler		      ; 52: SSP2
-		DCD		LCD_IRQHandler		  	  ; 53: LCD
-		DCD		GPIO_IRQHandler		  	  ; 54: GPIO
-		DCD		PWM0_IRQHandler		  	  ; 55: PWM0
-		DCD		EEPROM_IRQHandler	  	  ; 56: EEPROM
-
-
-
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size 	EQU 	__Vectors_End - __Vectors
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK TIMER0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER0_IRQHandler
-        B TIMER0_IRQHandler
-
-        PUBWEAK TIMER1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER1_IRQHandler
-        B TIMER1_IRQHandler
-
-        PUBWEAK TIMER2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER2_IRQHandler
-        B TIMER2_IRQHandler
-
-        PUBWEAK TIMER3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER3_IRQHandler
-        B TIMER3_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK PWM1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PWM1_IRQHandler
-        B PWM1_IRQHandler
-
-        PUBWEAK I2C0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C0_IRQHandler
-        B I2C0_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-        PUBWEAK SPIFI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SPIFI_IRQHandler
-        B SPIFI_IRQHandler
-
-        PUBWEAK SSP0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP0_IRQHandler
-        B SSP0_IRQHandler
-
-        PUBWEAK SSP1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP1_IRQHandler
-        B SSP1_IRQHandler
-
-        PUBWEAK PLL0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL0_IRQHandler
-        B PLL0_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK EINT0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT0_IRQHandler
-        B EINT0_IRQHandler
-
-        PUBWEAK EINT1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT1_IRQHandler
-        B EINT1_IRQHandler
-
-        PUBWEAK EINT2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT2_IRQHandler
-        B EINT2_IRQHandler
-
-        PUBWEAK EINT3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT3_IRQHandler
-        B EINT3_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK BOD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-BOD_IRQHandler
-        B BOD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK DMA_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA_IRQHandler
-        B DMA_IRQHandler
-
-        PUBWEAK I2S_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2S_IRQHandler
-        B I2S_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK MCI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-MCI_IRQHandler
-        B MCI_IRQHandler
-
-        PUBWEAK MCPWM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-MCPWM_IRQHandler
-        B MCPWM_IRQHandler
-
-        PUBWEAK QEI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-QEI_IRQHandler
-        B QEI_IRQHandler
-
-        PUBWEAK PLL1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL1_IRQHandler
-        B PLL1_IRQHandler
-
-        PUBWEAK USBActivity_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBActivity_IRQHandler
-        B USBActivity_IRQHandler
-
-        PUBWEAK CANActivity_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CANActivity_IRQHandler
-        B CANActivity_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK SSP2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP2_IRQHandler
-        B SSP2_IRQHandler
-
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK GPIO_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-GPIO_IRQHandler
-        B GPIO_IRQHandler
-
-        PUBWEAK PWM0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PWM0_IRQHandler
-        B PWM0_IRQHandler
-
-		PUBWEAK EEPROM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EEPROM_IRQHandler
-        B EEPROM_IRQHandler
-
-        END

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c

@@ -1,466 +0,0 @@
-/**********************************************************************
-* $Id: system_LPC177x_8x.c 7485 2011-06-03 07:57:16Z sgg06786 $		system_LPC177x_8x.c			2011-06-02
-*//**
-* @file		system_LPC177x_8x.c
-* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-*          	for the NXP LPC177x_8x Device Series
-*
-*			ARM Limited (ARM) is supplying this software for use with 
-*			Cortex-M processor based microcontrollers.  This file can be 
-*			freely distributed within development tools that are supporting 
-*			such ARM based processors.
-*
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#include <stdint.h>
-#include "LPC177x_8x.h"
-#include "system_LPC177x_8x.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-//   <h> System Controls and Status Register (SCS)
-//     <o1.0>       EMC_SHIFT: EMC Shift enable
-//                     <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit
-//                     <1=> Static CS addresses start at LSB 0 regardless of memory width
-//     <o1.1>       EMC_RESET: EMC Reset disable
-//                     <0=> EMC will be reset by any chip reset
-//                     <1=> Portions of EMC will only be reset by POR or BOR
-//     <o1.2>       EMC_BURST: EMC Burst disable
-//     <o1.3>       MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection
-//                     <0=> SD_PWR is active low
-//                     <1=> SD_PWR is active high
-//     <o1.4>       OSCRANGE: Main Oscillator Range Select
-//                     <0=>  1 MHz to 20 MHz
-//                     <1=> 15 MHz to 25 MHz
-//     <o1.5>       OSCEN: Main Oscillator enable
-//   </h>
-//
-//   <h> Clock Source Select Register (CLKSRCSEL)
-//     <o2.0>       CLKSRC: sysclk and PLL0 clock source selection
-//                     <0=> Internal RC oscillator
-//                     <1=> Main oscillator
-//   </h>
-//
-//   <e3> PLL0 Configuration (Main PLL)
-//     <h> PLL0 Configuration Register (PLL0CFG)
-//                     <i> PLL out clock = (F_cco / (2 * P))
-//                     <i> F_cco = (F_in * M * 2 * P)
-//                     <i> F_in  must be in the range of 1 MHz to 25 MHz
-//                     <i> F_cco must be in the range of 9.75 MHz to 160 MHz
-//       <o4.0..4>   MSEL: PLL Multiplier Selection
-//                     <i> M Value
-//                     <1-32><#-1>
-//       <o4.5..6> PSEL: PLL Divider Selection
-//                     <i> P Value
-//                     <0=> 1
-//                     <1=> 2
-//                     <2=> 4
-//                     <3=> 8
-//     </h>
-//   </e>
-//
-//   <e5> PLL1 Configuration (Alt PLL)
-//     <h> PLL1 Configuration Register (PLL1CFG)
-//                     <i> PLL out clock = (F_cco / (2 * P))
-//                     <i> F_cco = (F_in * M * 2 * P)
-//                     <i> F_in  must be in the range of 1 MHz to 25 MHz
-//                     <i> F_cco must be in the range of 9.75 MHz to 160 MHz
-//       <o6.0..4>   MSEL: PLL Multiplier Selection
-//                     <i> M Value
-//                     <1-32><#-1>
-//       <o6.5..6> PSEL: PLL Divider Selection
-//                     <i> P Value
-//                     <0=> 1
-//                     <1=> 2
-//                     <2=> 4
-//                     <3=> 8
-//     </h>
-//   </e>
-//
-//   <h> CPU Clock Selection Register (CCLKSEL)
-//     <o7.0..4>    CCLKDIV: CPU clock (CCLK) divider
-//                     <i> 0: The divider is turned off. No clock will be provided to the CPU
-//                     <i> n: The input clock is divided by n to produce the CPU clock
-//                     <0-31>
-//     <o7.8>       CCLKSEL: CPU clock divider input clock selection
-//                     <0=> sysclk clock
-//                     <1=> PLL0 clock
-//   </h>
-//
-//   <h> USB Clock Selection Register (USBCLKSEL)
-//     <o8.0..4>    USBDIV: USB clock (source PLL0) divider selection
-//                     <0=> USB clock off
-//                     <4=> PLL0 / 4 (PLL0 must be 192Mhz)
-//                     <6=> PLL0 / 6 (PLL0 must be 288Mhz)
-//     <o8.8..9>    USBSEL: USB clock divider input clock selection
-//                     <i> When CPU clock is selected, the USB can be accessed
-//                     <i> by software but cannot perform USB functions
-//                     <0=> CPU clock
-//                     <1=> PLL0 clock
-//                     <2=> PLL1 clock
-//   </h>
-//
-//   <h> EMC Clock Selection Register (EMCCLKSEL)
-//     <o9.0>       EMCDIV: EMC clock selection
-//                     <0=> CPU clock
-//                     <1=> CPU clock / 2
-//   </h>
-//
-//   <h> Peripheral Clock Selection Register (PCLKSEL)
-//     <o10.0..4>   PCLKDIV: APB Peripheral clock divider
-//                     <i> 0: The divider is turned off. No clock will be provided to APB peripherals
-//                     <i> n: The input clock is divided by n to produce the APB peripheral clock
-//                     <0-31>
-//   </h>
-//
-//   <h> Power Control for Peripherals Register (PCONP)
-//     <o11.0>      PCLCD: LCD controller power/clock enable
-//     <o11.1>      PCTIM0: Timer/Counter 0 power/clock enable
-//     <o11.2>      PCTIM1: Timer/Counter 1 power/clock enable
-//     <o11.3>      PCUART0: UART 0 power/clock enable
-//     <o11.4>      PCUART1: UART 1 power/clock enable
-//     <o11.5>      PCPWM0: PWM0 power/clock enable
-//     <o11.6>      PCPWM1: PWM1 power/clock enable
-//     <o11.7>      PCI2C0: I2C 0 interface power/clock enable
-//     <o11.8>      PCUART4: UART 4 power/clock enable
-//     <o11.9>      PCRTC: RTC and Event Recorder power/clock enable
-//     <o11.10>     PCSSP1: SSP 1 interface power/clock enable
-//     <o11.11>     PCEMC: External Memory Controller power/clock enable
-//     <o11.12>     PCADC: A/D converter power/clock enable
-//     <o11.13>     PCCAN1: CAN controller 1 power/clock enable
-//     <o11.14>     PCCAN2: CAN controller 2 power/clock enable
-//     <o11.15>     PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable
-//     <o11.17>     PCMCPWM: Motor Control PWM power/clock enable
-//     <o11.18>     PCQEI: Quadrature encoder interface power/clock enable
-//     <o11.19>     PCI2C1: I2C 1 interface power/clock enable
-//     <o11.20>     PCSSP2: SSP 2 interface power/clock enable
-//     <o11.21>     PCSSP0: SSP 0 interface power/clock enable
-//     <o11.22>     PCTIM2: Timer 2 power/clock enable
-//     <o11.23>     PCTIM3: Timer 3 power/clock enable
-//     <o11.24>     PCUART2: UART 2 power/clock enable
-//     <o11.25>     PCUART3: UART 3 power/clock enable
-//     <o11.26>     PCI2C2: I2C 2 interface power/clock enable
-//     <o11.27>     PCI2S: I2S interface power/clock enable
-//     <o11.28>     PCSDC: SD Card interface power/clock enable
-//     <o11.29>     PCGPDMA: GPDMA function power/clock enable
-//     <o11.30>     PCENET: Ethernet block power/clock enable
-//     <o11.31>     PCUSB: USB interface power/clock enable
-//   </h>
-//
-//   <h> Clock Output Configuration Register (CLKOUTCFG)
-//     <o12.0..3>   CLKOUTSEL: Clock Source for CLKOUT Selection
-//                     <0=> CPU clock
-//                     <1=> Main Oscillator
-//                     <2=> Internal RC Oscillator
-//                     <3=> USB clock
-//                     <4=> RTC Oscillator
-//                     <5=> unused
-//                     <6=> Watchdog Oscillator
-//     <o12.4..7>   CLKOUTDIV: Output Clock Divider
-//                     <1-16><#-1>
-//     <o12.8>      CLKOUT_EN: CLKOUT enable
-//   </h>
-//
-// </e>
-*/
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000021
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x00000009
-#define PLL1_SETUP            1
-#define PLL1CFG_Val           0x00000023
-#define CCLKSEL_Val           (0x00000001|(1<<8))
-#define USBCLK_SETUP		  1
-#define USBCLKSEL_Val         (0x00000001|(0x02<<8))
-#define EMCCLKSEL_Val         0x00000001
-#define PCLKSEL_Val           0x00000002
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000100
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-// <e> Flash Accelerator Configuration
-//   <o1.12..15> FLASHTIM: Flash Access Time
-//               <0=> 1 CPU clock (for CPU clock up to 20 MHz)
-//               <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
-//               <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
-//               <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
-//               <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
-//               <5=> 6 CPU clocks (for any CPU clock)
-// </e>
-*/
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x00005000
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x0000003F))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))
-   #error "CCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
-   #error "USBCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
-   #error "EMCCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
-   #error "PCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
-   #warning "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-/* pll_out_clk = F_cco / (2 × P)
-   F_cco = pll_in_clk × M × 2 × P */
-#define __M                   ((PLL0CFG_Val & 0x1F) + 1)
-#define __PLL0_CLK(__F_IN)    (__F_IN * __M)
-#define __CCLK_DIV            (CCLKSEL_Val & 0x1F)
-#define __PCLK_DIV			  (PCLKSEL_Val & 0x1F)
-#define __ECLK_DIV			  ((EMCCLKSEL_Val & 0x01) + 1)
-
-/* Determine core clock frequency according to settings */
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-
-  #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
-   #error "Main Oscillator is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
-   #error "Main PLL is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
-		#define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
-        #define __EMC_CLK  (IRC_OSC/  __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
-        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
-        #define __EMC_CLK  (OSC_CLK/  __ECLK_DIV)
-    #endif
-  #else                                 /* cclk = pll_clk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
-        #define __EMC_CLK  (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
-		#define __EMC_CLK  (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
-    #endif
-  #endif
-
-#else
-        #define __CORE_CLK (IRC_OSC)
-        #define __PER_CLK  (IRC_OSC)
-        #define __EMC_CLK  (IRC_OSC)
-#endif
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */
-uint32_t EMCClock		 = __EMC_CLK; /*!< EMC Clock Frequency 				  */
-uint32_t USBClock 		 = (48000000UL);		  /*!< USB Clock Frequency - this value will
-									be updated after call SystemCoreClockUpdate, should be 48MHz*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */
-    if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-          SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-    }
-    else {                                        /* sysclk = osc_clk */
-      if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock        = 0;
-      }
-      else {
-          SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-      }
-    }
-  }
-  else {                                          /* cclk = pll_clk */
-    if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-    }
-    else {
-      if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-          SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-      }
-      else {                                        /* sysclk = osc_clk */
-        if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-        }
-        else {
-          SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-        }
-      }
-    }
-  }
-  /* ---update USBClock------------------*/
-  if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
-  {
-	  switch (LPC_SC->USBCLKSEL & 0x1F)
-	  {
-	  case 0:
-		  USBClock = 0; //no clock will be provided to the USB subsystem
-		  break;
-	  case 4:
-	  case 6:
-		  if(LPC_SC->CLKSRCSEL & 0x01)	//pll_clk_in = main_osc
-			  USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
-		  else //pll_clk_in = irc_clk
-			  USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
-		  break;
-	  default:
-		  USBClock = 0;  /* this should never happen! */
-	  }
-  }
-  else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
-  {
-	  if(LPC_SC->CLKSRCSEL & 0x01)	//pll1_clk_in = main_osc
-	  		USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
-	  else //pll1_clk_in = irc_clk
-	  		USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
-  }
-  else
-	  USBClock = 0; /* this should never happen! */
-}
-
-  /* Determine clock frequency according to clock register values             */
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/
-
-#if (PLL0_SETUP)
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-#endif
-
-  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
-  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
-  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
-  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
-#endif
-#ifdef  __RAM_MODE__
-  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
-#else
-  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
-#endif
-}

bsp/nxp/lpc/lpc178x/CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.h

@@ -1,83 +0,0 @@
-/**********************************************************************
-* $Id: system_LPC177x_8x.h 7485 2011-06-03 07:57:16Z sgg06786 $		system_LPC177x_8x.h			2011-06-02
-*//**
-* @file		system_LPC177x_8x.h
-* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-*			for the NXP LPC177x_8x Device Series
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef __SYSTEM_LPC177x_8x_H
-#define __SYSTEM_LPC177x_8x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;      /*!< System Clock Frequency (Core Clock)  	*/
-extern uint32_t PeripheralClock;	    /*!< Peripheral Clock Frequency (Pclk) 	    */
-extern uint32_t EMCClock;			        /*!< EMC Clock                              */
-extern uint32_t USBClock;			        /*!< USB Frequency 						              */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32768UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     (12000000UL)        /* Internal RC oscillator frequency   */
-#define WDT_OSC		  (  500000UL)		/* Internal WDT oscillator frequency  */
-
-
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC177x_8x_H */

bsp/nxp/lpc/lpc178x/CMSIS/SConscript

@@ -1,20 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = GetCurrentDir()
-src = Glob('*.c')
-src = ['CM3/CoreSupport/core_cm3.c', 'CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c']
-CPPPATH = [cwd + '/CM3/CoreSupport', cwd + '/CM3/DeviceSupport/NXP/LPC177x_8x/']
-
-# add for startup script
-if rtconfig.PLATFORM in ['gcc']:
-    src += ['CM3/DeviceSupport/NXP/LPC177x_8x/startup/gcc/startup_LPC177x_8x.s']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
-    src += ['CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s']
-elif rtconfig.PLATFORM in ['iccarm']:
-    src += ['CM3/DeviceSupport/NXP/LPC177x_8x/startup/iar/startup_LPC177x_8x.s']
-
-group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/nxp/lpc/lpc178x/Kconfig

@@ -14,6 +14,7 @@ config SOC_LPC178
     select ARCH_ARM_CORTEX_M3
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
+    select PKG_USING_NXP_LPC_DRIVER
     default y
 
 source "$(BSP_DIR)/drivers/Kconfig"

bsp/nxp/lpc/lpc178x/SConstruct

@@ -10,6 +10,24 @@ else:
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
 
+def bsp_pkg_check():
+    import subprocess
+
+    check_paths = [
+        os.path.join("packages", "nxp-lpc-series-latest"),
+    ]
+
+    need_update = not all(os.path.exists(p) for p in check_paths)
+
+    if need_update:
+        print("\n==============================================================")
+        print("Dependency packages missing, please running 'pkgs --update'...")
+        print("==============================================================")
+        exit(1)
+
+RegisterPreBuildingAction(bsp_pkg_check)
+
+
 TARGET = 'rtthread-%s.%s' % (rtconfig.BOARD_NAME, rtconfig.TARGET_EXT)
 DefaultEnvironment(tools=[])
 if rtconfig.PLATFORM == 'armcc':

bsp/nxp/lpc/lpc408x/Kconfig

@@ -14,6 +14,7 @@ config SOC_LPC4088
     select ARCH_ARM_CORTEX_M4
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
+    select PKG_USING_NXP_LPC_DRIVER
     default y
 
 source "$(BSP_DIR)/drivers/Kconfig"

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_common_tables.h

@@ -1,35 +0,0 @@
-/* ---------------------------------------------------------------------- 
-* Copyright (C) 2010 ARM Limited. All rights reserved. 
-* 
-* $Date:        11. November 2010  
-* $Revision: 	V1.0.2  
-* 
-* Project: 	    CMSIS DSP Library 
-* Title:	    arm_common_tables.h 
-* 
-* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
-* 
-* Target Processor: Cortex-M4/Cortex-M3
-*  
-* Version 1.0.2 2010/11/11 
-*    Documentation updated.  
-* 
-* Version 1.0.1 2010/10/05  
-*    Production release and review comments incorporated. 
-* 
-* Version 1.0.0 2010/09/20  
-*    Production release and review comments incorporated. 
-* -------------------------------------------------------------------- */ 
- 
-#ifndef _ARM_COMMON_TABLES_H 
-#define _ARM_COMMON_TABLES_H 
- 
-#include "arm_math.h" 
- 
-extern uint16_t armBitRevTable[256]; 
-extern q15_t armRecipTableQ15[64]; 
-extern q31_t armRecipTableQ31[64]; 
-extern const q31_t realCoefAQ31[1024];
-extern const q31_t realCoefBQ31[1024];
- 
-#endif /*  ARM_COMMON_TABLES_H */ 

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/arm_math.h

@@ -1,7062 +0,0 @@
-/* ----------------------------------------------------------------------   
- * Copyright (C) 2010 ARM Limited. All rights reserved.   
- *   
- * $Date:        15. July 2011  
- * $Revision: 	V1.0.10  
- *   
- * Project: 	    CMSIS DSP Library   
- * Title:	     arm_math.h
- *   
- * Description:	 Public header file for CMSIS DSP Library
- *   
- * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
- *  
- * Version 1.0.10 2011/7/15 
- *    Big Endian support added and Merged M0 and M3/M4 Source code.  
- *   
- * Version 1.0.3 2010/11/29  
- *    Re-organized the CMSIS folders and updated documentation.   
- *    
- * Version 1.0.2 2010/11/11   
- *    Documentation updated.    
- *   
- * Version 1.0.1 2010/10/05    
- *    Production release and review comments incorporated.   
- *   
- * Version 1.0.0 2010/09/20    
- *    Production release and review comments incorporated.   
- * -------------------------------------------------------------------- */
-
-/**
-   \mainpage CMSIS DSP Software Library
-   *
-   * <b>Introduction</b>
-   *
-   * This user manual describes the CMSIS DSP software library, 
-   * a suite of common signal processing functions for use on Cortex-M processor based devices.
-   *
-   * The library is divided into a number of modules each covering a specific category:
-   * - Basic math functions
-   * - Fast math functions
-   * - Complex math functions
-   * - Filters
-   * - Matrix functions
-   * - Transforms
-   * - Motor control functions
-   * - Statistical functions
-   * - Support functions
-   * - Interpolation functions
-   *
-   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
-   * 32-bit integer and 32-bit floating-point values. 
-   *
-   * <b>Processor Support</b>
-   *
-   * The library is completely written in C and is fully CMSIS compliant. 
-   * High performance is achieved through maximum use of Cortex-M4 intrinsics. 
-   *
-   * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
-   * with the DSP intrinsics being emulated through software. 
-   *
-   *
-   * <b>Toolchain Support</b>
-   *
-   * The library has been developed and tested with MDK-ARM version 4.21. 
-   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
-   *
-   * <b>Using the Library</b>
-   *
-   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
-   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
-   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
-   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
-   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
-   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
-   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
-   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
-   *
-   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
-   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
-   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
-   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
-   * ARM_MATH_CM0 depending on the target processor in the application.
-   *
-   * <b>Examples</b>
-   *
-   * The library ships with a number of examples which demonstrate how to use the library functions.
-   *
-   * <b>Building the Library</b>
-   *
-   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\DSP_Lib\Source\ARM</code> folder.
-   * - arm_cortexM0b_math.uvproj
-   * - arm_cortexM0l_math.uvproj
-   * - arm_cortexM3b_math.uvproj
-   * - arm_cortexM3l_math.uvproj  
-   * - arm_cortexM4b_math.uvproj
-   * - arm_cortexM4l_math.uvproj
-   * - arm_cortexM4bf_math.uvproj
-   * - arm_cortexM4lf_math.uvproj
-   *
-   * Each library project have differant pre-processor macros.
-   *
-   * <b>ARM_MATH_CMx:</b>
-   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
-   * and ARM_MATH_CM0 for building library on cortex-M0 target.
-   *
-   * <b>ARM_MATH_BIG_ENDIAN:</b>
-   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
-   *
-   * <b>ARM_MATH_MATRIX_CHECK:</b>
-   * Define macro for checking on the input and output sizes of matrices
-   *
-   * <b>ARM_MATH_ROUNDING:</b>
-   * Define macro for rounding on support functions
-   *
-   * <b>__FPU_PRESENT:</b>
-   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
-   *
-   *
-   * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
-   *
-   * <b>Copyright Notice</b>
-   *
-   * Copyright (C) 2010 ARM Limited. All rights reserved.
-   */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- * @ingroup DSP_Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * @ingroup DSP_Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * @ingroup DSP_Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- * @ingroup DSP_Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- * @ingroup DSP_Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures.  For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data.  The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order.  That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- *     pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure.  For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices.  For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns.  If the size check fails the functions return:
- * <pre>
- *     ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- *     ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the #define
- * <pre>
- *     ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings.  By default this macro is defined
- * and size checking is enabled.  By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster.  With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- * @ingroup DSP_Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- * @ingroup DSP_Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- * @ingroup DSP_Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- * @ingroup DSP_Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * @ingroup DSP_Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- * @ingroup DSP_Lib
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
-
-#if defined (ARM_MATH_CM4)
-  #include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-  #include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-  #include "core_cm0.h"
-#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
-#endif
-
-#undef  __CMSIS_GENERIC              /* enable NVIC and Systick functions */
-#include "string.h"
-    #include "math.h"
-#ifdef	__cplusplus
-extern "C"
-{
-#endif
-
-
-  /**
-   * @brief Macros required for reciprocal calculation in Normalized LMS
-   */
-
-#define DELTA_Q31 			(0x100)
-#define DELTA_Q15 			0x5
-#define INDEX_MASK 			0x0000003F
-#define PI					3.14159265358979f
-
-  /**
-   * @brief Macros required for SINE and COSINE Fast math approximations
-   */
-
-#define TABLE_SIZE			256
-#define TABLE_SPACING_Q31	0x800000
-#define TABLE_SPACING_Q15	0x80
-
-  /**
-   * @brief Macros required for SINE and COSINE Controller functions
-   */
-  /* 1.31(q31) Fixed value of 2/360 */
-  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING			0xB60B61
-
-
-  /**
-   * @brief Error status returned by some functions in the library.
-   */
-
-  typedef enum
-    {
-      ARM_MATH_SUCCESS = 0,              /**< No error */
-      ARM_MATH_ARGUMENT_ERROR = -1,      /**< One or more arguments are incorrect */
-      ARM_MATH_LENGTH_ERROR = -2,        /**< Length of data buffer is incorrect */
-      ARM_MATH_SIZE_MISMATCH = -3,       /**< Size of matrices is not compatible with the operation. */
-      ARM_MATH_NANINF = -4,              /**< Not-a-number (NaN) or infinity is generated */
-      ARM_MATH_SINGULAR = -5,            /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
-      ARM_MATH_TEST_FAILURE = -6         /**< Test Failed  */
-    } arm_status;
-
-  /**
-   * @brief 8-bit fractional data type in 1.7 format.
-   */
-  typedef int8_t q7_t;
-
-  /**
-   * @brief 16-bit fractional data type in 1.15 format.
-   */
-  typedef int16_t q15_t;
-
-  /**
-   * @brief 32-bit fractional data type in 1.31 format.
-   */
-  typedef int32_t q31_t;
-
-  /**
-   * @brief 64-bit fractional data type in 1.63 format.
-   */
-  typedef int64_t q63_t;
-
-  /**
-   * @brief 32-bit floating-point type definition.
-   */
-  typedef float float32_t;
-
-  /**
-   * @brief 64-bit floating-point type definition.
-   */
-  typedef double float64_t;
-
-  /**
-   * @brief definition to read/write two 16 bit values.
-   */
-#define __SIMD32(addr)  (*(int32_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-  /**
-   * @brief definition to pack two 16 bit values.
-   */
-#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
-                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
-
-#endif
-
-
-   /**
-   * @brief definition to pack four 8 bit values.
-   */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
-#else								
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
-                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
-							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
-							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
-								
-#endif
-
-
-  /**
-   * @brief Clips Q63 to Q31 values.
-   */
-  static __INLINE q31_t clip_q63_to_q31(
-					q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
-  }
-
-  /**
-   * @brief Clips Q63 to Q15 values.
-   */
-  static __INLINE q15_t clip_q63_to_q15(
-					q63_t x)
-  {
-    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
-  }
-
-  /**
-   * @brief Clips Q31 to Q7 values.
-   */
-  static __INLINE q7_t clip_q31_to_q7(
-				      q31_t x)
-  {
-    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
-      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
-  }
-
-  /**
-   * @brief Clips Q31 to Q15 values.
-   */
-  static __INLINE q15_t clip_q31_to_q15(
-					q31_t x)
-  {
-    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
-      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
-  }
-
-  /**
-   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
-   */
-
-  static __INLINE q63_t mult32x64(
-				  q63_t x,
-				  q31_t y)
-  {
-    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
-            (((q63_t) (x >> 32) * y)));
-  }
-
-
-#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
-#define __CLZ __clz
-#endif 
-
-#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
-
-  static __INLINE  uint32_t __CLZ(q31_t data);
-
-
-  static __INLINE uint32_t __CLZ(q31_t data)
-  {
-	  uint32_t count = 0;
-	  uint32_t mask = 0x80000000;
-
-	  while((data & mask) ==  0)
-	  {
-		  count += 1u;
-		  mask = mask >> 1u;
-	  }
-
-	  return(count);
-
-  }
-
-#endif 
-
-  /**
-   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
-   */
-
-  static __INLINE uint32_t arm_recip_q31(
-					 q31_t in,
-					 q31_t * dst,
-					 q31_t * pRecipTable)
-  {
-
-    uint32_t out, tempVal;
-    uint32_t index, i;
-    uint32_t signBits;
-
-    if(in > 0)
-      {
-	signBits = __CLZ(in) - 1;
-      }
-    else
-      {
-	signBits = __CLZ(-in) - 1;
-      }
-
-    /* Convert input sample to 1.31 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = (uint32_t) (in >> 24u);
-    index = (index & INDEX_MASK);
-
-    /* 1.31 with exp 1 */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0u; i < 2u; i++)
-      {
-	tempVal = (q31_t) (((q63_t) in * out) >> 31u);
-	tempVal = 0x7FFFFFFF - tempVal;
-	/*      1.31 with exp 1 */
-	//out = (q31_t) (((q63_t) out * tempVal) >> 30u);
-	out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
-      }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1u);
-
-  }
-
-  /**
-   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
-   */
-  static __INLINE uint32_t arm_recip_q15(
-					 q15_t in,
-					 q15_t * dst,
-					 q15_t * pRecipTable)
-  {
-
-    uint32_t out = 0, tempVal = 0;
-    uint32_t index = 0, i = 0;
-    uint32_t signBits = 0;
-
-    if(in > 0)
-      {
-	signBits = __CLZ(in) - 17;
-      }
-    else
-      {
-	signBits = __CLZ(-in) - 17;
-      }
-
-    /* Convert input sample to 1.15 format */
-    in = in << signBits;
-
-    /* calculation of index for initial approximated Val */
-    index = in >> 8;
-    index = (index & INDEX_MASK);
-
-    /*      1.15 with exp 1  */
-    out = pRecipTable[index];
-
-    /* calculation of reciprocal value */
-    /* running approximation for two iterations */
-    for (i = 0; i < 2; i++)
-      {
-	tempVal = (q15_t) (((q31_t) in * out) >> 15);
-	tempVal = 0x7FFF - tempVal;
-	/*      1.15 with exp 1 */
-	out = (q15_t) (((q31_t) out * tempVal) >> 14);
-      }
-
-    /* write output */
-    *dst = out;
-
-    /* return num of signbits of out = 1/in value */
-    return (signBits + 1);
-
-  }
-
-
-  /*
-   * @brief C custom defined intrinisic function for only M0 processors
-   */
-#if defined(ARM_MATH_CM0)
-
-  static __INLINE q31_t __SSAT(
-			       q31_t x,
-			       uint32_t y)
-  {
-    int32_t posMax, negMin;
-    uint32_t i;
-
-    posMax = 1;
-    for (i = 0; i < (y - 1); i++)
-      {
-	posMax = posMax * 2;
-      }
-
-    if(x > 0)
-      {
-	posMax = (posMax - 1);
-
-	if(x > posMax)
-	  {
-	    x = posMax;
-	  }
-      }
-    else
-      {
-	negMin = -posMax;
-
-	if(x < negMin)
-	  {
-	    x = negMin;
-	  }
-      }
-    return (x);
-
-
-  }
-
-#endif /* end of ARM_MATH_CM0 */
-
-
-
-  /*
-   * @brief C custom defined intrinsic function for M3 and M0 processors
-   */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
-
-  /*
-   * @brief C custom defined QADD8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD8(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q7_t r, s, t, u;
-
-    r = (char) x;
-    s = (char) y;
-
-    r = __SSAT((q31_t) (r + s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
-    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
-    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
-    sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
-      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB8 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB8(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s, t, u;
-
-    r = (char) x;
-    s = (char) y;
-
-    r = __SSAT((r - s), 8);
-    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
-    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
-    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
-    sum =
-      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-
-  /*
-   * @brief C custom defined QADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD16(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r + s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined SHADD16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHADD16(
-				  q31_t x,
-				  q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (s >> 1));
-    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-
-  }
-
-  /*
-   * @brief C custom defined QSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB16(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = __SSAT(r - s, 16);
-    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSUB16 for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSUB16(
-				  q31_t x,
-				  q31_t y)
-  {
-
-    q31_t diff;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (s >> 1));
-    s = (((x >> 17) - (y >> 17)) << 16);
-
-    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return diff;
-  }
-
-  /*
-   * @brief C custom defined QASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QASX(
-			       q31_t x,
-			       q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHASX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHASX(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) - (y >> 17));
-    s = (((x >> 17) + (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-
-  /*
-   * @brief C custom defined QSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSAX(
-			       q31_t x,
-			       q31_t y)
-  {
-
-    q31_t sum = 0;
-
-    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
-      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SHSAX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SHSAX(
-				q31_t x,
-				q31_t y)
-  {
-
-    q31_t sum;
-    q31_t r, s;
-
-    r = (short) x;
-    s = (short) y;
-
-    r = ((r >> 1) + (y >> 17));
-    s = (((x >> 17) - (s >> 1)) << 16);
-
-    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
-    return sum;
-  }
-
-  /*
-   * @brief C custom defined SMUSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSDX(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    return ((q31_t)(((short) x * (short) (y >> 16)) -
-		    ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined SMUADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUADX(
-				 q31_t x,
-				 q31_t y)
-  {
-
-    return ((q31_t)(((short) x * (short) (y >> 16)) +
-		    ((short) (x >> 16) * (short) y)));
-  }
-
-  /*
-   * @brief C custom defined QADD for M3 and M0 processors
-   */
-  static __INLINE q31_t __QADD(
-			       q31_t x,
-			       q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x + y);
-  }
-
-  /*
-   * @brief C custom defined QSUB for M3 and M0 processors
-   */
-  static __INLINE q31_t __QSUB(
-			       q31_t x,
-			       q31_t y)
-  {
-    return clip_q63_to_q31((q63_t) x - y);
-  }
-
-  /*
-   * @brief C custom defined SMLAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLAD(
-				q31_t x,
-				q31_t y,
-				q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLADX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLADX(
-				 q31_t x,
-				 q31_t y,
-				 q31_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLSDX for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMLSDX(
-				 q31_t x,
-				 q31_t y,
-				 q31_t sum)
-  {
-
-    return (sum - ((short) (x >> 16) * (short) (y)) +
-            ((short) x * (short) (y >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMLALD for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALD(
-				 q31_t x,
-				 q31_t y,
-				 q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
-            ((short) x * (short) y));
-  }
-
-  /*
-   * @brief C custom defined SMLALDX for M3 and M0 processors
-   */
-  static __INLINE q63_t __SMLALDX(
-				  q31_t x,
-				  q31_t y,
-				  q63_t sum)
-  {
-
-    return (sum + ((short) (x >> 16) * (short) y)) +
-      ((short) x * (short) (y >> 16));
-  }
-
-  /*
-   * @brief C custom defined SMUAD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUAD(
-				q31_t x,
-				q31_t y)
-  {
-
-    return (((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-  /*
-   * @brief C custom defined SMUSD for M3 and M0 processors
-   */
-  static __INLINE q31_t __SMUSD(
-				q31_t x,
-				q31_t y)
-  {
-
-    return (-((x >> 16) * (y >> 16)) +
-            (((x << 16) >> 16) * ((y << 16) >> 16)));
-  }
-
-
-
-
-#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
-
-
-  /**
-   * @brief Instance structure for the Q7 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
-    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q7;
-
-  /**
-   * @brief Instance structure for the Q15 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-  } arm_fir_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
-    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-  } arm_fir_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q7 FIR filter.
-   * @param[in] *S points to an instance of the Q7 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q7(
-		  const arm_fir_instance_q7 * S,
-		   q7_t * pSrc,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q7 FIR filter.
-   * @param[in,out] *S points to an instance of the Q7 FIR structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed.
-   * @return none
-   */
-  void arm_fir_init_q7(
-		       arm_fir_instance_q7 * S,
-		       uint16_t numTaps,
-		       q7_t * pCoeffs,
-		       q7_t * pState,
-		       uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR filter.
-   * @param[in] *S points to an instance of the Q15 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q15(
-		   const arm_fir_instance_q15 * S,
-		    q15_t * pSrc,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q15(
-			const arm_fir_instance_q15 * S,
-			 q15_t * pSrc,
-			q15_t * pDst,
-			uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 FIR filter.
-   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
-   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of samples that are processed at a time.
-   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
-   * <code>numTaps</code> is not a supported value.
-   */
-   
-       arm_status arm_fir_init_q15(
-			      arm_fir_instance_q15 * S,
-			      uint16_t numTaps,
-			      q15_t * pCoeffs,
-			      q15_t * pState,
-			      uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR filter.
-   * @param[in] *S points to an instance of the Q31 FIR filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_q31(
-		   const arm_fir_instance_q31 * S,
-		    q31_t * pSrc,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_fast_q31(
-			const arm_fir_instance_q31 * S,
-			 q31_t * pSrc,
-			q31_t * pDst,
-			uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR filter.
-   * @param[in,out] *S points to an instance of the Q31 FIR structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return 		none.
-   */
-  void arm_fir_init_q31(
-			arm_fir_instance_q31 * S,
-			uint16_t numTaps,
-			q31_t * pCoeffs,
-			q31_t * pState,
-			uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the floating-point FIR filter.
-   * @param[in] *S points to an instance of the floating-point FIR structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_f32(
-		   const arm_fir_instance_f32 * S,
-		    float32_t * pSrc,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR filter.
-   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
-   * @param[in] 	numTaps  Number of filter coefficients in the filter.
-   * @param[in] 	*pCoeffs points to the filter coefficients.
-   * @param[in] 	*pState points to the state buffer.
-   * @param[in] 	blockSize number of samples that are processed at a time.
-   * @return    	none.
-   */
-  void arm_fir_init_f32(
-			arm_fir_instance_f32 * S,
-			uint16_t numTaps,
-			float32_t * pCoeffs,
-			float32_t * pState,
-			uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q15;
-
-
-  /**
-   * @brief Instance structure for the Q31 Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_casd_df1_inst_q31;
-
-  /**
-   * @brief Instance structure for the floating-point Biquad cascade filter.
-   */
-  typedef struct
-  {
-    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
-    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
-
-
-  } arm_biquad_casd_df1_inst_f32;
-
-
-
-  /**
-   * @brief Processing function for the Q15 Biquad cascade filter.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q15(
-				  const arm_biquad_casd_df1_inst_q15 * S,
-				   q15_t * pSrc,
-				  q15_t * pDst,
-				  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q15 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q15(
-				       arm_biquad_casd_df1_inst_q15 * S,
-				       uint8_t numStages,
-				       q15_t * pCoeffs,
-				       q15_t * pState,
-				       int8_t postShift);
-
-
-  /**
-   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q15(
-				       const arm_biquad_casd_df1_inst_q15 * S,
-				        q15_t * pSrc,
-				       q15_t * pDst,
-				       uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 Biquad cascade filter
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_q31(
-				  const arm_biquad_casd_df1_inst_q31 * S,
-				   q31_t * pSrc,
-				  q31_t * pDst,
-				  uint32_t blockSize);
-
-  /**
-   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
-   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_fast_q31(
-				       const arm_biquad_casd_df1_inst_q31 * S,
-				        q31_t * pSrc,
-				       q31_t * pDst,
-				       uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
-   * @param[in]     numStages      number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_q31(
-				       arm_biquad_casd_df1_inst_q31 * S,
-				       uint8_t numStages,
-				       q31_t * pCoeffs,
-				       q31_t * pState,
-				       int8_t postShift);
-
-  /**
-   * @brief Processing function for the floating-point Biquad cascade filter.
-   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]  *pSrc      points to the block of input data.
-   * @param[out] *pDst      points to the block of output data.
-   * @param[in]  blockSize  number of samples to process.
-   * @return     none.
-   */
-
-  void arm_biquad_cascade_df1_f32(
-				  const arm_biquad_casd_df1_inst_f32 * S,
-				   float32_t * pSrc,
-				  float32_t * pDst,
-				  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df1_init_f32(
-				       arm_biquad_casd_df1_inst_f32 * S,
-				       uint8_t numStages,
-				       float32_t * pCoeffs,
-				       float32_t * pState);
-
-
-  /**
-   * @brief Instance structure for the floating-point matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    float32_t *pData;     /**< points to the data of the matrix. */
-  } arm_matrix_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q15 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q15_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 matrix structure.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;     /**< number of rows of the matrix.     */
-    uint16_t numCols;     /**< number of columns of the matrix.  */
-    q31_t *pData;         /**< points to the data of the matrix. */
-
-  } arm_matrix_instance_q31;
-
-
-
-  /**
-   * @brief Floating-point matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_f32(
-			     const arm_matrix_instance_f32 * pSrcA,
-			     const arm_matrix_instance_f32 * pSrcB,
-			     arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q15(
-			     const arm_matrix_instance_q15 * pSrcA,
-			     const arm_matrix_instance_q15 * pSrcB,
-			     arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix addition.
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_add_q31(
-			     const arm_matrix_instance_q31 * pSrcA,
-			     const arm_matrix_instance_q31 * pSrcB,
-			     arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_f32(
-			       const arm_matrix_instance_f32 * pSrc,
-			       arm_matrix_instance_f32 * pDst);
-
-
-  /**
-   * @brief Q15 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q15(
-			       const arm_matrix_instance_q15 * pSrc,
-			       arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix transpose.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[out] *pDst points to the output matrix
-   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
-   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_trans_q31(
-			       const arm_matrix_instance_q31 * pSrc,
-			       arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_f32(
-			      const arm_matrix_instance_f32 * pSrcA,
-			      const arm_matrix_instance_f32 * pSrcB,
-			      arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q15(
-			      const arm_matrix_instance_q15 * pSrcA,
-			      const arm_matrix_instance_q15 * pSrcB,
-			      arm_matrix_instance_q15 * pDst,
-			      q15_t * pState);
-
-  /**
-   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA  points to the first input matrix structure
-   * @param[in]       *pSrcB  points to the second input matrix structure
-   * @param[out]      *pDst   points to output matrix structure
-   * @param[in]		  *pState points to the array for storing intermediate results  
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q15(
-				   const arm_matrix_instance_q15 * pSrcA,
-				   const arm_matrix_instance_q15 * pSrcB,
-				   arm_matrix_instance_q15 * pDst,
-				   q15_t * pState);
-
-  /**
-   * @brief Q31 matrix multiplication
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_q31(
-			      const arm_matrix_instance_q31 * pSrcA,
-			      const arm_matrix_instance_q31 * pSrcB,
-			      arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_mult_fast_q31(
-				   const arm_matrix_instance_q31 * pSrcA,
-				   const arm_matrix_instance_q31 * pSrcB,
-				   arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief Floating-point matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_f32(
-			     const arm_matrix_instance_f32 * pSrcA,
-			     const arm_matrix_instance_f32 * pSrcB,
-			     arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q15(
-			     const arm_matrix_instance_q15 * pSrcA,
-			     const arm_matrix_instance_q15 * pSrcB,
-			     arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix subtraction
-   * @param[in]       *pSrcA points to the first input matrix structure
-   * @param[in]       *pSrcB points to the second input matrix structure
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_sub_q31(
-			     const arm_matrix_instance_q31 * pSrcA,
-			     const arm_matrix_instance_q31 * pSrcB,
-			     arm_matrix_instance_q31 * pDst);
-
-  /**
-   * @brief Floating-point matrix scaling.
-   * @param[in]  *pSrc points to the input matrix
-   * @param[in]  scale scale factor
-   * @param[out] *pDst points to the output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_f32(
-			       const arm_matrix_instance_f32 * pSrc,
-			       float32_t scale,
-			       arm_matrix_instance_f32 * pDst);
-
-  /**
-   * @brief Q15 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q15(
-			       const arm_matrix_instance_q15 * pSrc,
-			       q15_t scaleFract,
-			       int32_t shift,
-			       arm_matrix_instance_q15 * pDst);
-
-  /**
-   * @brief Q31 matrix scaling.
-   * @param[in]       *pSrc points to input matrix
-   * @param[in]       scaleFract fractional portion of the scale factor
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to output matrix structure
-   * @return     The function returns either
-   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
-   */
-
-  arm_status arm_mat_scale_q31(
-			       const arm_matrix_instance_q31 * pSrc,
-			       q31_t scaleFract,
-			       int32_t shift,
-			       arm_matrix_instance_q31 * pDst);
-
-
-  /**
-   * @brief  Q31 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q31(
-			arm_matrix_instance_q31 * S,
-			uint16_t nRows,
-			uint16_t nColumns,
-			q31_t   *pData);
-
-  /**
-   * @brief  Q15 matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_q15(
-			arm_matrix_instance_q15 * S,
-			uint16_t nRows,
-			uint16_t nColumns,
-			q15_t    *pData);
-
-  /**
-   * @brief  Floating-point matrix initialization.
-   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
-   * @param[in]     nRows          number of rows in the matrix.
-   * @param[in]     nColumns       number of columns in the matrix.
-   * @param[in]     *pData	       points to the matrix data array.
-   * @return        none
-   */
-
-  void arm_mat_init_f32(
-			arm_matrix_instance_f32 * S,
-			uint16_t nRows,
-			uint16_t nColumns,
-			float32_t   *pData);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 PID Control.
-   */
-  typedef struct
-  {
-    q15_t A0; 	 /**< The derived gain, A0 = Kp + Ki + Kd . */
-	#ifdef ARM_MATH_CM0  
-	q15_t A1;
-	q15_t A2; 
-	#else 	      
-    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-	#endif 
-    q15_t state[3];       /**< The state array of length 3. */
-    q15_t Kp;           /**< The proportional gain. */
-    q15_t Ki;           /**< The integral gain. */
-    q15_t Kd;           /**< The derivative gain. */
-  } arm_pid_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 PID Control.
-   */
-  typedef struct
-  {
-    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
-    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
-    q31_t A2;            /**< The derived gain, A2 = Kd . */
-    q31_t state[3];      /**< The state array of length 3. */
-    q31_t Kp;            /**< The proportional gain. */
-    q31_t Ki;            /**< The integral gain. */
-    q31_t Kd;            /**< The derivative gain. */
-
-  } arm_pid_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point PID Control.
-   */
-  typedef struct
-  {
-    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
-    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
-    float32_t A2;          /**< The derived gain, A2 = Kd . */
-    float32_t state[3];    /**< The state array of length 3. */
-    float32_t Kp;               /**< The proportional gain. */
-    float32_t Ki;               /**< The integral gain. */
-    float32_t Kd;               /**< The derivative gain. */
-  } arm_pid_instance_f32;
-
-
-
-  /**
-   * @brief  Initialization function for the floating-point PID Control.
-   * @param[in,out] *S      points to an instance of the PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_f32(
-			arm_pid_instance_f32 * S,
-			int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_f32(
-			 arm_pid_instance_f32 * S);
-
-
-  /**
-   * @brief  Initialization function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q31(
-			arm_pid_instance_q31 * S,
-			int32_t resetStateFlag);
-
- 
-  /**
-   * @brief  Reset function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @return none
-   */
-
-  void arm_pid_reset_q31(
-			 arm_pid_instance_q31 * S);
-
-  /**
-   * @brief  Initialization function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID structure.
-   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
-   * @return none.
-   */
-  void arm_pid_init_q15(
-			arm_pid_instance_q15 * S,
-			int32_t resetStateFlag);
-
-  /**
-   * @brief  Reset function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the q15 PID Control structure
-   * @return none
-   */
-  void arm_pid_reset_q15(
-			 arm_pid_instance_q15 * S);
-
-
-  /**
-   * @brief Instance structure for the floating-point Linear Interpolate function.
-   */
-  typedef struct
-  {
-    uint32_t nValues;
-    float32_t x1;
-    float32_t xSpacing;
-    float32_t *pYData;          /**< pointer to the table of Y values */
-  } arm_linear_interp_instance_f32;
-
-  /**
-   * @brief Instance structure for the floating-point bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    float32_t *pData;	/**< points to the data table. */
-  } arm_bilinear_interp_instance_f32;
-
-   /**
-   * @brief Instance structure for the Q31 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    q31_t *pData;	/**< points to the data table. */
-  } arm_bilinear_interp_instance_q31;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows;	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    q15_t *pData;	/**< points to the data table. */
-  } arm_bilinear_interp_instance_q15;
-
-   /**
-   * @brief Instance structure for the Q15 bilinear interpolation function.
-   */
-
-  typedef struct
-  {
-    uint16_t numRows; 	/**< number of rows in the data table. */
-    uint16_t numCols;	/**< number of columns in the data table. */
-    q7_t *pData;		/**< points to the data table. */
-  } arm_bilinear_interp_instance_q7;
-
-
-  /**
-   * @brief Q7 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q7(
-		    q7_t * pSrcA,
-		    q7_t * pSrcB,
-		   q7_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst  points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q15(
-		     q15_t * pSrcA,
-		     q15_t * pSrcB,
-		    q15_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_q31(
-		     q31_t * pSrcA,
-		     q31_t * pSrcB,
-		    q31_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector multiplication.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_mult_f32(
-		     float32_t * pSrcA,
-		     float32_t * pSrcB,
-		    float32_t * pDst,
-		    uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q15 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t  fftLen;                /**< length of the FFT. */
-    uint8_t   ifftFlag;              /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t   bitReverseFlag;        /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q15_t     *pTwiddle;             /**< points to the twiddle factor table. */
-    uint16_t  *pBitRevTable;         /**< points to the bit reversal table. */
-    uint16_t  twidCoefModifier;      /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t  bitRevFactor;          /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t    fftLen;              /**< length of the FFT. */
-    uint8_t     ifftFlag;            /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t     bitReverseFlag;      /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    q31_t       *pTwiddle;           /**< points to the twiddle factor table. */
-    uint16_t    *pBitRevTable;       /**< points to the bit reversal table. */
-    uint16_t    twidCoefModifier;    /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t    bitRevFactor;        /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-  } arm_cfft_radix4_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point CFFT/CIFFT function.
-   */
-
-  typedef struct
-  {
-    uint16_t     fftLen;               /**< length of the FFT. */
-    uint8_t      ifftFlag;             /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
-    uint8_t      bitReverseFlag;       /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
-    float32_t    *pTwiddle;            /**< points to the twiddle factor table. */
-    uint16_t     *pBitRevTable;        /**< points to the bit reversal table. */
-    uint16_t     twidCoefModifier;     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    uint16_t     bitRevFactor;         /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
-	float32_t    onebyfftLen;          /**< value of 1/fftLen. */
-  } arm_cfft_radix4_instance_f32;
-
-  /**
-   * @brief Processing function for the Q15 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_q15(
-			   const arm_cfft_radix4_instance_q15 * S,
-			   q15_t * pSrc);
-
-  /**
-   * @brief Initialization function for the Q15 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-
-  arm_status arm_cfft_radix4_init_q15(
-				      arm_cfft_radix4_instance_q15 * S,
-				      uint16_t fftLen,
-				      uint8_t ifftFlag,
-				      uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Q31 CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_q31(
-			   const arm_cfft_radix4_instance_q31 * S,
-			   q31_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the Q31 CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-  
-  arm_status arm_cfft_radix4_init_q31(
-				      arm_cfft_radix4_instance_q31 * S,
-				      uint16_t fftLen,
-				      uint8_t ifftFlag,
-				      uint8_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the floating-point CFFT/CIFFT.
-   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
-   * @return none.
-   */
-
-  void arm_cfft_radix4_f32(
-			   const arm_cfft_radix4_instance_f32 * S,
-			   float32_t * pSrc);
-
-  /**
-   * @brief  Initialization function for the floating-point CFFT/CIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLen         length of the FFT.
-   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
-   */
-  
-  arm_status arm_cfft_radix4_init_f32(
-				      arm_cfft_radix4_instance_f32 * S,
-				      uint16_t fftLen,
-				      uint8_t ifftFlag,
-				      uint8_t bitReverseFlag);
-
-
-
-  /*----------------------------------------------------------------------
-   *		Internal functions prototypes FFT function
-   ----------------------------------------------------------------------*/
-
-  /**
-   * @brief  Core function for the floating-point CFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_f32(
-				float32_t * pSrc,
-				uint16_t fftLen,
-				float32_t * pCoef,
-				uint16_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the floating-point CIFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @param[in]      onebyfftLen      value of 1/fftLen.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_inverse_f32(
-					float32_t * pSrc,
-					uint16_t fftLen,
-					float32_t * pCoef,
-					uint16_t twidCoefModifier,
-					float32_t onebyfftLen);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
-   * @param[in]      fftSize      length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
-   * @param[in]      *pBitRevTab  points to the bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_f32(
-			   float32_t *pSrc,
-			   uint16_t fftSize,
-			   uint16_t bitRevFactor,
-			   uint16_t *pBitRevTab);
-
-  /**
-   * @brief  Core function for the Q31 CFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_q31(
-				q31_t *pSrc,
-				uint32_t fftLen,
-				q31_t *pCoef,
-				uint32_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the Q31 CIFFT butterfly process.
-   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef           points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-  
-  void arm_radix4_butterfly_inverse_q31(
-					q31_t * pSrc,
-					uint32_t fftLen,
-					q31_t * pCoef,
-					uint32_t twidCoefModifier);
-  
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
-   * @param[in]      fftLen       length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-   * @param[in]      *pBitRevTab  points to bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_q31(
-			   q31_t * pSrc,
-			   uint32_t fftLen,
-			   uint16_t bitRevFactor,
-			   uint16_t *pBitRevTab);
-
-  /**
-   * @brief  Core function for the Q15 CFFT butterfly process.
-   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_q15(
-				q15_t *pSrc16,
-				uint32_t fftLen,
-				q15_t *pCoef16,
-				uint32_t twidCoefModifier);
-
-  /**
-   * @brief  Core function for the Q15 CIFFT butterfly process.
-   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen           length of the FFT.
-   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
-   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
-   * @return none.
-   */
-
-  void arm_radix4_butterfly_inverse_q15(
-					q15_t *pSrc16,
-					uint32_t fftLen,
-					q15_t *pCoef16,
-					uint32_t twidCoefModifier);
-
-  /**
-   * @brief  In-place bit reversal function.
-   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
-   * @param[in]      fftLen       length of the FFT.
-   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
-   * @param[in]      *pBitRevTab  points to bit reversal table.
-   * @return none.
-   */
-
-  void arm_bitreversal_q15(
-			   q15_t * pSrc,
-			   uint32_t fftLen,
-			   uint16_t bitRevFactor,
-			   uint16_t *pBitRevTab);
-
-  /**
-   * @brief Instance structure for the Q15 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                      /**< length of the real FFT. */
-    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
-    uint8_t  ifftFlagR;                       /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-	uint8_t  bitReverseFlagR;                 /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */  
-    q15_t    *pTwiddleAReal;                  /**< points to the real twiddle factor table. */
-    q15_t    *pTwiddleBReal;                  /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q15 *pCfft;	  /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t fftLenReal;                        /**< length of the real FFT. */
-    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
-    uint8_t  ifftFlagR;                         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-	uint8_t  bitReverseFlagR;                   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    q31_t    *pTwiddleAReal;                    /**< points to the real twiddle factor table. */
-    q31_t    *pTwiddleBReal;                    /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point RFFT/RIFFT function.
-   */
-
-  typedef struct
-  {
-    uint32_t  fftLenReal;                       /**< length of the real FFT. */
-    uint16_t  fftLenBy2;                        /**< length of the complex FFT. */
-    uint8_t   ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
-    uint8_t   bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
-	uint32_t  twidCoefRModifier;                /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
-    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
-    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
-    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
-  } arm_rfft_instance_f32;
-
-  /**
-   * @brief Processing function for the Q15 RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_q15(
-		    const arm_rfft_instance_q15 * S,
-		    q15_t * pSrc,
-		    q15_t * pDst);
-
-  /**
-   * @brief  Initialization function for the Q15 RFFT/RIFFT.
-   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
-   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
-   * @param[in]      fftLenReal     length of the FFT.
-   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_q15(
-			       arm_rfft_instance_q15 * S,
-			       arm_cfft_radix4_instance_q15 * S_CFFT,
-			       uint32_t fftLenReal,
-			       uint32_t ifftFlagR,
-			       uint32_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the Q31 RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_q31(
-		    const arm_rfft_instance_q31 * S,
-		    q31_t * pSrc,
-		    q31_t * pDst);
-
-  /**
-   * @brief  Initialization function for the Q31 RFFT/RIFFT.
-   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
-   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
-   * @param[in]      fftLenReal     length of the FFT.
-   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_q31(
-			       arm_rfft_instance_q31 * S,
-			       arm_cfft_radix4_instance_q31 * S_CFFT,
-			       uint32_t fftLenReal,
-			       uint32_t ifftFlagR,
-			       uint32_t bitReverseFlag);
-
-  /**
-   * @brief  Initialization function for the floating-point RFFT/RIFFT.
-   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
-   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
-   * @param[in]     fftLenReal     length of the FFT.
-   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
-   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
-   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
-   */
-
-  arm_status arm_rfft_init_f32(
-			       arm_rfft_instance_f32 * S,
-			       arm_cfft_radix4_instance_f32 * S_CFFT,
-			       uint32_t fftLenReal,
-			       uint32_t ifftFlagR,
-			       uint32_t bitReverseFlag);
-
-  /**
-   * @brief Processing function for the floating-point RFFT/RIFFT.
-   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
-   * @param[in]  *pSrc points to the input buffer.
-   * @param[out] *pDst points to the output buffer.
-   * @return none.
-   */
-
-  void arm_rfft_f32(
-		    const arm_rfft_instance_f32 * S,
-		    float32_t * pSrc,
-		    float32_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    float32_t normalize;                /**< normalizing factor. */
-    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
-    float32_t *pCosFactor;              /**< points to the cosFactor table. */
-    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_f32;
-
-  /**
-   * @brief  Initialization function for the floating-point DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_f32(
-			       arm_dct4_instance_f32 * S,
-			       arm_rfft_instance_f32 * S_RFFT,
-			       arm_cfft_radix4_instance_f32 * S_CFFT,
-			       uint16_t N,
-			       uint16_t Nby2,
-			       float32_t normalize);
-
-  /**
-   * @brief Processing function for the floating-point DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_f32(
-		    const arm_dct4_instance_f32 * S,
-		    float32_t * pState,
-		    float32_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q31_t normalize;                    /**< normalizing factor. */
-    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q31;
-
-  /**
-   * @brief  Initialization function for the Q31 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
-   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q31(
-			       arm_dct4_instance_q31 * S,
-			       arm_rfft_instance_q31 * S_RFFT,
-			       arm_cfft_radix4_instance_q31 * S_CFFT,
-			       uint16_t N,
-			       uint16_t Nby2,
-			       q31_t normalize);
-
-  /**
-   * @brief Processing function for the Q31 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q31(
-		    const arm_dct4_instance_q31 * S,
-		    q31_t * pState,
-		    q31_t * pInlineBuffer);
-
-  /**
-   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
-   */
-
-  typedef struct
-  {
-    uint16_t N;                         /**< length of the DCT4. */
-    uint16_t Nby2;                      /**< half of the length of the DCT4. */
-    q15_t normalize;                    /**< normalizing factor. */
-    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
-    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
-    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
-    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
-  } arm_dct4_instance_q15;
-
-  /**
-   * @brief  Initialization function for the Q15 DCT4/IDCT4.
-   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
-   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
-   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
-   * @param[in]     N          length of the DCT4.
-   * @param[in]     Nby2       half of the length of the DCT4.
-   * @param[in]     normalize  normalizing factor.
-   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
-   */
-
-  arm_status arm_dct4_init_q15(
-			       arm_dct4_instance_q15 * S,
-			       arm_rfft_instance_q15 * S_RFFT,
-			       arm_cfft_radix4_instance_q15 * S_CFFT,
-			       uint16_t N,
-			       uint16_t Nby2,
-			       q15_t normalize);
-
-  /**
-   * @brief Processing function for the Q15 DCT4/IDCT4.
-   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
-   * @param[in]       *pState        points to state buffer.
-   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
-   * @return none.
-   */
-
-  void arm_dct4_q15(
-		    const arm_dct4_instance_q15 * S,
-		    q15_t * pState,
-		    q15_t * pInlineBuffer);
-
-  /**
-   * @brief Floating-point vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_f32(
-		   float32_t * pSrcA,
-		   float32_t * pSrcB,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q7(
-		  q7_t * pSrcA,
-		  q7_t * pSrcB,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q15(
-		    q15_t * pSrcA,
-		    q15_t * pSrcB,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector addition.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_add_q31(
-		    q31_t * pSrcA,
-		    q31_t * pSrcB,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_f32(
-		    float32_t * pSrcA,
-		    float32_t * pSrcB,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q7(
-		   q7_t * pSrcA,
-		   q7_t * pSrcB,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q15(
-		    q15_t * pSrcA,
-		    q15_t * pSrcB,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector subtraction.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_sub_q31(
-		    q31_t * pSrcA,
-		    q31_t * pSrcB,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a floating-point vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scale scale factor to be applied
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_f32(
-		      float32_t * pSrc,
-		     float32_t scale,
-		     float32_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q7 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q7(
-		     q7_t * pSrc,
-		    q7_t scaleFract,
-		    int8_t shift,
-		    q7_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q15 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q15(
-		      q15_t * pSrc,
-		     q15_t scaleFract,
-		     int8_t shift,
-		     q15_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief Multiplies a Q31 vector by a scalar.
-   * @param[in]       *pSrc points to the input vector
-   * @param[in]       scaleFract fractional portion of the scale value
-   * @param[in]       shift number of bits to shift the result by
-   * @param[out]      *pDst points to the output vector
-   * @param[in]       blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_scale_q31(
-		      q31_t * pSrc,
-		     q31_t scaleFract,
-		     int8_t shift,
-		     q31_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief Q7 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q7(
-		   q7_t * pSrc,
-		  q7_t * pDst,
-		  uint32_t blockSize);
-
-  /**
-   * @brief Floating-point vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_f32(
-		    float32_t * pSrc,
-		   float32_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q15 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q15(
-		    q15_t * pSrc,
-		   q15_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Q31 vector absolute value.
-   * @param[in]       *pSrc points to the input buffer
-   * @param[out]      *pDst points to the output buffer
-   * @param[in]       blockSize number of samples in each vector
-   * @return none.
-   */
-
-  void arm_abs_q31(
-		    q31_t * pSrc,
-		   q31_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Dot product of floating-point vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_f32(
-			 float32_t * pSrcA,
-			 float32_t * pSrcB,
-			uint32_t blockSize,
-			float32_t * result);
-
-  /**
-   * @brief Dot product of Q7 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q7(
-		        q7_t * pSrcA,
-		        q7_t * pSrcB,
-		       uint32_t blockSize,
-		       q31_t * result);
-
-  /**
-   * @brief Dot product of Q15 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q15(
-			 q15_t * pSrcA,
-			 q15_t * pSrcB,
-			uint32_t blockSize,
-			q63_t * result);
-
-  /**
-   * @brief Dot product of Q31 vectors.
-   * @param[in]       *pSrcA points to the first input vector
-   * @param[in]       *pSrcB points to the second input vector
-   * @param[in]       blockSize number of samples in each vector
-   * @param[out]      *result output result returned here
-   * @return none.
-   */
-
-  void arm_dot_prod_q31(
-			 q31_t * pSrcA,
-			 q31_t * pSrcB,
-			uint32_t blockSize,
-			q63_t * result);
-
-  /**
-   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q7(
-		     q7_t * pSrc,
-		    int8_t shiftBits,
-		    q7_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q15(
-		      q15_t * pSrc,
-		     int8_t shiftBits,
-		     q15_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_shift_q31(
-		      q31_t * pSrc,
-		     int8_t shiftBits,
-		     q31_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_f32(
-		       float32_t * pSrc,
-		      float32_t offset,
-		      float32_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q7(
-		      q7_t * pSrc,
-		     q7_t offset,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q15(
-		       q15_t * pSrc,
-		      q15_t offset,
-		      q15_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Adds a constant offset to a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[in]  offset is the offset to be added
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_offset_q31(
-		       q31_t * pSrc,
-		      q31_t offset,
-		      q31_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a floating-point vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_f32(
-		       float32_t * pSrc,
-		      float32_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q7 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q7(
-		      q7_t * pSrc,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q15 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q15(
-		       q15_t * pSrc,
-		      q15_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Negates the elements of a Q31 vector.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  blockSize number of samples in the vector
-   * @return none.
-   */
-
-  void arm_negate_q31(
-		       q31_t * pSrc,
-		      q31_t * pDst,
-		      uint32_t blockSize);
-  /**
-   * @brief  Copies the elements of a floating-point vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_f32(
-		     float32_t * pSrc,
-		    float32_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q7 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q7(
-		    q7_t * pSrc,
-		   q7_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q15 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q15(
-		     q15_t * pSrc,
-		    q15_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Copies the elements of a Q31 vector. 
-   * @param[in]  *pSrc input pointer
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_copy_q31(
-		     q31_t * pSrc,
-		    q31_t * pDst,
-		    uint32_t blockSize);
-  /**
-   * @brief  Fills a constant value into a floating-point vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_f32(
-		     float32_t value,
-		    float32_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q7 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q7(
-		    q7_t value,
-		   q7_t * pDst,
-		   uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q15 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q15(
-		     q15_t value,
-		    q15_t * pDst,
-		    uint32_t blockSize);
-
-  /**
-   * @brief  Fills a constant value into a Q31 vector. 
-   * @param[in]  value input value to be filled
-   * @param[out]  *pDst output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_fill_q31(
-		     q31_t value,
-		    q31_t * pDst,
-		    uint32_t blockSize);
-
-/**  
- * @brief Convolution of floating-point sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
- */ 
-
-  void arm_conv_f32(
-		     float32_t * pSrcA,
-		    uint32_t srcALen,
-		     float32_t * pSrcB,
-		    uint32_t srcBLen,
-		    float32_t * pDst);
-
-/**  
- * @brief Convolution of Q15 sequences.  
- * @param[in] *pSrcA points to the first input sequence.  
- * @param[in] srcALen length of the first input sequence.  
- * @param[in] *pSrcB points to the second input sequence.  
- * @param[in] srcBLen length of the second input sequence.  
- * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
- * @return none.  
- */
-
-  void arm_conv_q15(
-		     q15_t * pSrcA,
-		    uint32_t srcALen,
-		     q15_t * pSrcB,
-		    uint32_t srcBLen,
-		    q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q31(
-		     q31_t * pSrcA,
-		    uint32_t srcALen,
-		     q31_t * pSrcB,
-		    uint32_t srcBLen,
-		    q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_fast_q31(
-			  q31_t * pSrcA,
-			 uint32_t srcALen,
-			  q31_t * pSrcB,
-			 uint32_t srcBLen,
-			 q31_t * pDst);
-
-  /**
-   * @brief Convolution of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
-   * @return none.
-   */
-
-  void arm_conv_q7(
-		    q7_t * pSrcA,
-		   uint32_t srcALen,
-		    q7_t * pSrcB,
-		   uint32_t srcBLen,
-		   q7_t * pDst);
-
-  /**
-   * @brief Partial convolution of floating-point sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_f32(
-				   float32_t * pSrcA,
-				  uint32_t srcALen,
-				   float32_t * pSrcB,
-				  uint32_t srcBLen,
-				  float32_t * pDst,
-				  uint32_t firstIndex,
-				  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q15(
-				   q15_t * pSrcA,
-				  uint32_t srcALen,
-				   q15_t * pSrcB,
-				  uint32_t srcBLen,
-				  q15_t * pDst,
-				  uint32_t firstIndex,
-				  uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q15(
-				        q15_t * pSrcA,
-				       uint32_t srcALen,
-				        q15_t * pSrcB,
-				       uint32_t srcBLen,
-				       q15_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q31 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q31(
-				   q31_t * pSrcA,
-				  uint32_t srcALen,
-				   q31_t * pSrcB,
-				  uint32_t srcBLen,
-				  q31_t * pDst,
-				  uint32_t firstIndex,
-				  uint32_t numPoints);
-
-
-  /**
-   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_fast_q31(
-				        q31_t * pSrcA,
-				       uint32_t srcALen,
-				        q31_t * pSrcB,
-				       uint32_t srcBLen,
-				       q31_t * pDst,
-				       uint32_t firstIndex,
-				       uint32_t numPoints);
-
-  /**
-   * @brief Partial convolution of Q7 sequences.
-   * @param[in]       *pSrcA points to the first input sequence.
-   * @param[in]       srcALen length of the first input sequence.
-   * @param[in]       *pSrcB points to the second input sequence.
-   * @param[in]       srcBLen length of the second input sequence.
-   * @param[out]      *pDst points to the block of output data
-   * @param[in]       firstIndex is the first output sample to start with.
-   * @param[in]       numPoints is the number of output points to be computed.
-   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
-   */
-
-  arm_status arm_conv_partial_q7(
-				  q7_t * pSrcA,
-				 uint32_t srcALen,
-				  q7_t * pSrcB,
-				 uint32_t srcBLen,
-				 q7_t * pDst,
-				 uint32_t firstIndex,
-				 uint32_t numPoints);
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                      /**< decimation factor. */
-    uint16_t numTaps;               /**< number of coefficients in the filter. */
-    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-  } arm_fir_decimate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                  /**< decimation factor. */
-    uint16_t numTaps;           /**< number of coefficients in the filter. */
-    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
-    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR decimator.
-   */
-
-  typedef struct
-  {
-    uint8_t M;                          /**< decimation factor. */
-    uint16_t numTaps;                   /**< number of coefficients in the filter. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
-  } arm_fir_decimate_instance_f32;
-
-
-
-  /**
-   * @brief Processing function for the floating-point FIR decimator.
-   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_f32(
-			    const arm_fir_decimate_instance_f32 * S,
-			     float32_t * pSrc,
-			    float32_t * pDst,
-			    uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point FIR decimator.
-   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_f32(
-				       arm_fir_decimate_instance_f32 * S,
-				       uint16_t numTaps,
-				       uint8_t M,
-				       float32_t * pCoeffs,
-				       float32_t * pState,
-				       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q15(
-			    const arm_fir_decimate_instance_q15 * S,
-			     q15_t * pSrc,
-			    q15_t * pDst,
-			    uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q15(
-				 const arm_fir_decimate_instance_q15 * S,
-				  q15_t * pSrc,
-				 q15_t * pDst,
-				 uint32_t blockSize);
-
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q15(
-				       arm_fir_decimate_instance_q15 * S,
-				       uint16_t numTaps,
-				       uint8_t M,
-				       q15_t * pCoeffs,
-				       q15_t * pState,
-				       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_q31(
-			    const arm_fir_decimate_instance_q31 * S,
-			     q31_t * pSrc,
-			    q31_t * pDst,
-			    uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
-   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none
-   */
-
-  void arm_fir_decimate_fast_q31(
-				 arm_fir_decimate_instance_q31 * S,
-				  q31_t * pSrc,
-				 q31_t * pDst,
-				 uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q31 FIR decimator.
-   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
-   * @param[in] numTaps  number of coefficients in the filter.
-   * @param[in] M  decimation factor.
-   * @param[in] *pCoeffs points to the filter coefficients.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * <code>blockSize</code> is not a multiple of <code>M</code>.
-   */
-
-  arm_status arm_fir_decimate_init_q31(
-				       arm_fir_decimate_instance_q31 * S,
-				       uint16_t numTaps,
-				       uint8_t M,
-				       q31_t * pCoeffs,
-				       q31_t * pState,
-				       uint32_t blockSize);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                      /**< upsample factor. */
-    uint16_t phaseLength;           /**< length of each polyphase filter component. */
-    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
-    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
-  } arm_fir_interpolate_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR interpolator.
-   */
-
-  typedef struct
-  {
-    uint8_t L;                     /**< upsample factor. */
-    uint16_t phaseLength;          /**< length of each polyphase filter component. */
-    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
-    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
-  } arm_fir_interpolate_instance_f32;
-
-
-  /**
-   * @brief Processing function for the Q15 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q15(
-			       const arm_fir_interpolate_instance_q15 * S,
-			        q15_t * pSrc,
-			       q15_t * pDst,
-			       uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q15(
-					  arm_fir_interpolate_instance_q15 * S,
-					  uint8_t L,
-					  uint16_t numTaps,
-					  q15_t * pCoeffs,
-					  q15_t * pState,
-					  uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 FIR interpolator.
-   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_q31(
-			       const arm_fir_interpolate_instance_q31 * S,
-			        q31_t * pSrc,
-			       q31_t * pDst,
-			       uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 FIR interpolator.
-   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_q31(
-					  arm_fir_interpolate_instance_q31 * S,
-					  uint8_t L,
-					  uint16_t numTaps,
-					  q31_t * pCoeffs,
-					  q31_t * pState,
-					  uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the floating-point FIR interpolator.
-   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in] *pSrc     points to the block of input data.
-   * @param[out] *pDst    points to the block of output data.
-   * @param[in] blockSize number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_interpolate_f32(
-			       const arm_fir_interpolate_instance_f32 * S,
-			        float32_t * pSrc,
-			       float32_t * pDst,
-			       uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point FIR interpolator.
-   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
-   * @param[in]     L         upsample factor.
-   * @param[in]     numTaps   number of filter coefficients in the filter.
-   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
-   * @param[in]     *pState   points to the state buffer.
-   * @param[in]     blockSize number of input samples to process per call.
-   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
-   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
-   */
-
-  arm_status arm_fir_interpolate_init_f32(
-					  arm_fir_interpolate_instance_f32 * S,
-					  uint8_t L,
-					  uint16_t numTaps,
-					  float32_t * pCoeffs,
-					  float32_t * pState,
-					  uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
-    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
-    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
-
-  } arm_biquad_cas_df1_32x64_ins_q31;
-
-
-  /**
-   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cas_df1_32x64_q31(
-				    const arm_biquad_cas_df1_32x64_ins_q31 * S,
-				     q31_t * pSrc,
-				    q31_t * pDst,
-				    uint32_t blockSize);
-
-
-  /**
-   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
-   * @return        none
-   */
-
-  void arm_biquad_cas_df1_32x64_init_q31(
-					 arm_biquad_cas_df1_32x64_ins_q31 * S,
-					 uint8_t numStages,
-					 q31_t * pCoeffs,
-					 q63_t * pState,
-					 uint8_t postShift);
-
-
-
-  /**
-   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
-   */
-
-  typedef struct
-  {
-    uint8_t   numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
-    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
-    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
-  } arm_biquad_cascade_df2T_instance_f32;
-
-
-  /**
-   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in]  *S        points to an instance of the filter data structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_biquad_cascade_df2T_f32(
-				   const arm_biquad_cascade_df2T_instance_f32 * S,
-				    float32_t * pSrc,
-				   float32_t * pDst,
-				   uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
-   * @param[in,out] *S           points to an instance of the filter data structure.
-   * @param[in]     numStages    number of 2nd order stages in the filter.
-   * @param[in]     *pCoeffs     points to the filter coefficients.
-   * @param[in]     *pState      points to the state buffer.
-   * @return        none
-   */
-
-  void arm_biquad_cascade_df2T_init_f32(
-					arm_biquad_cascade_df2T_instance_f32 * S,
-					uint8_t numStages,
-					float32_t * pCoeffs,
-					float32_t * pState);
-
-
-
-  /**
-   * @brief Instance structure for the Q15 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                          /**< number of filter stages. */
-    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
-    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point FIR lattice filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numStages;                  /**< number of filter stages. */
-    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
-    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
-  } arm_fir_lattice_instance_f32;
-
-  /**
-   * @brief Initialization function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
-   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q15(
-				arm_fir_lattice_instance_q15 * S,
-				uint16_t numStages,
-				q15_t * pCoeffs,
-				q15_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q15 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-  void arm_fir_lattice_q15(
-			   const arm_fir_lattice_instance_q15 * S,
-			    q15_t * pSrc,
-			   q15_t * pDst,
-			   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the Q31 FIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
-   * @param[in] numStages  number of filter stages.
-   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
-   * @param[in] *pState points to the state buffer.   The array is of length numStages.
-   * @return none.
-   */
-
-  void arm_fir_lattice_init_q31(
-				arm_fir_lattice_instance_q31 * S,
-				uint16_t numStages,
-				q31_t * pCoeffs,
-				q31_t * pState);
-
-
-  /**
-   * @brief Processing function for the Q31 FIR lattice filter.
-   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_q31(
-			   const arm_fir_lattice_instance_q31 * S,
-			    q31_t * pSrc,
-			   q31_t * pDst,
-			   uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages  number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
- * @param[in] *pState points to the state buffer.  The array is of length numStages.
- * @return none.
- */
-
-  void arm_fir_lattice_init_f32(
-				arm_fir_lattice_instance_f32 * S,
-				uint16_t numStages,
-				float32_t * pCoeffs,
-				float32_t * pState);
-
-  /**
-   * @brief Processing function for the floating-point FIR lattice filter.
-   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
-   * @param[in]  *pSrc     points to the block of input data.
-   * @param[out] *pDst     points to the block of output data
-   * @param[in]  blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_fir_lattice_f32(
-			   const arm_fir_lattice_instance_f32 * S,
-			    float32_t * pSrc,
-			   float32_t * pDst,
-			   uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q31 IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
-    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
-    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_q31;
-
-  /**
-   * @brief Instance structure for the floating-point IIR lattice filter.
-   */
-  typedef struct
-  {
-    uint16_t numStages;                         /**< number of stages in the filter. */
-    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
-    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
-    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
-  } arm_iir_lattice_instance_f32;
-
-  /**
-   * @brief Processing function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_f32(
-			   const arm_iir_lattice_instance_f32 * S,
-			    float32_t * pSrc,
-			   float32_t * pDst,
-			   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for the floating-point IIR lattice filter.
-   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_f32(
-				arm_iir_lattice_instance_f32 * S,
-				uint16_t numStages,
-				float32_t *pkCoeffs,
-				float32_t *pvCoeffs,
-				float32_t *pState,
-				uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q31(
-			   const arm_iir_lattice_instance_q31 * S,
-			    q31_t * pSrc,
-			   q31_t * pDst,
-			   uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for the Q31 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
-   * @param[in] numStages number of stages in the filter.
-   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
-   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
-   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_init_q31(
-				arm_iir_lattice_instance_q31 * S,
-				uint16_t numStages,
-				q31_t *pkCoeffs,
-				q31_t *pvCoeffs,
-				q31_t *pState,
-				uint32_t blockSize);
-
-
-  /**
-   * @brief Processing function for the Q15 IIR lattice filter.
-   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[out] *pDst points to the block of output data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_iir_lattice_q15(
-			   const arm_iir_lattice_instance_q15 * S,
-			    q15_t * pSrc,
-			   q15_t * pDst,
-			   uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages  number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
- * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
-  void arm_iir_lattice_init_q15(
-				arm_iir_lattice_instance_q15 * S,
-				uint16_t numStages,
-				q15_t *pkCoeffs,
-				q15_t *pvCoeffs,
-				q15_t *pState,
-				uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the floating-point LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that controls filter coefficient updates. */
-  } arm_lms_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point LMS filter.
-   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_f32(
-		   const arm_lms_instance_f32 * S,
-		    float32_t * pSrc,
-		    float32_t * pRef,
-		   float32_t * pOut,
-		   float32_t * pErr,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_init_f32(
-			arm_lms_instance_f32 * S,
-			uint16_t numTaps,
-			float32_t * pCoeffs,
-			float32_t * pState,
-			float32_t mu,
-			uint32_t blockSize);
-
-  /**
-   * @brief Instance structure for the Q15 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-  } arm_lms_instance_q15;
-
-
-  /**
-   * @brief Initialization function for the Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to the coefficient buffer.
-   * @param[in] *pState points to the state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return    none.
-   */
-
-  void arm_lms_init_q15(
-			arm_lms_instance_q15 * S,
-			uint16_t numTaps,
-			q15_t * pCoeffs,
-			q15_t * pState,
-			q15_t mu,
-			uint32_t blockSize,
-			uint32_t postShift);
-
-  /**
-   * @brief Processing function for Q15 LMS filter.
-   * @param[in] *S points to an instance of the Q15 LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_q15(
-		   const arm_lms_instance_q15 * S,
-		    q15_t * pSrc,
-		    q15_t * pRef,
-		   q15_t * pOut,
-		   q15_t * pErr,
-		   uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< number of coefficients in the filter. */
-    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;            /**< step size that controls filter coefficient updates. */
-    uint32_t postShift;  /**< bit shift applied to coefficients. */
-
-  } arm_lms_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 LMS filter.
-   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
-   * @param[in]  *pSrc points to the block of input data.
-   * @param[in]  *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in]  blockSize number of samples to process.
-   * @return     none.
-   */
-
-  void arm_lms_q31(
-		   const arm_lms_instance_q31 * S,
-		    q31_t * pSrc,
-		    q31_t * pRef,
-		   q31_t * pOut,
-		   q31_t * pErr,
-		   uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 LMS filter.
-   * @param[in] *S points to an instance of the Q31 LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_init_q31(
-			arm_lms_instance_q31 * S,
-			uint16_t numTaps,
-			q31_t *pCoeffs,
-			q31_t *pState,
-			q31_t mu,
-			uint32_t blockSize,
-			uint32_t postShift);
-
-  /**
-   * @brief Instance structure for the floating-point normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t  numTaps;    /**< number of coefficients in the filter. */
-    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
-    float32_t mu;        /**< step size that control filter coefficient updates. */
-    float32_t energy;    /**< saves previous frame energy. */
-    float32_t x0;        /**< saves previous input sample. */
-  } arm_lms_norm_instance_f32;
-
-  /**
-   * @brief Processing function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_f32(
-			arm_lms_norm_instance_f32 * S,
-			 float32_t * pSrc,
-			 float32_t * pRef,
-			float32_t * pOut,
-			float32_t * pErr,
-			uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for floating-point normalized LMS filter.
-   * @param[in] *S points to an instance of the floating-point LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_f32(
-			     arm_lms_norm_instance_f32 * S,
-			     uint16_t numTaps,
-			     float32_t * pCoeffs,
-			     float32_t * pState,
-			     float32_t mu,
-			     uint32_t blockSize);
-
-
-  /**
-   * @brief Instance structure for the Q31 normalized LMS filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;     /**< number of coefficients in the filter. */
-    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q31_t mu;             /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;    /**< bit shift applied to coefficients. */
-    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
-    q31_t energy;         /**< saves previous frame energy. */
-    q31_t x0;             /**< saves previous input sample. */
-  } arm_lms_norm_instance_q31;
-
-  /**
-   * @brief Processing function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q31(
-			arm_lms_norm_instance_q31 * S,
-			 q31_t * pSrc,
-			 q31_t * pRef,
-			q31_t * pOut,
-			q31_t * pErr,
-			uint32_t blockSize);
-
-  /**
-   * @brief Initialization function for Q31 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q31(
-			     arm_lms_norm_instance_q31 * S,
-			     uint16_t numTaps,
-			     q31_t * pCoeffs,
-			     q31_t * pState,
-			     q31_t mu,
-			     uint32_t blockSize,
-			     uint8_t postShift);
-
-  /**
-   * @brief Instance structure for the Q15 normalized LMS filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;    /**< Number of coefficients in the filter. */
-    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
-    q15_t mu;            /**< step size that controls filter coefficient updates. */
-    uint8_t postShift;   /**< bit shift applied to coefficients. */
-    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
-    q15_t energy;        /**< saves previous frame energy. */
-    q15_t x0;            /**< saves previous input sample. */
-  } arm_lms_norm_instance_q15;
-
-  /**
-   * @brief Processing function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] *pSrc points to the block of input data.
-   * @param[in] *pRef points to the block of reference data.
-   * @param[out] *pOut points to the block of output data.
-   * @param[out] *pErr points to the block of error data.
-   * @param[in] blockSize number of samples to process.
-   * @return none.
-   */
-
-  void arm_lms_norm_q15(
-			arm_lms_norm_instance_q15 * S,
-			 q15_t * pSrc,
-			 q15_t * pRef,
-			q15_t * pOut,
-			q15_t * pErr,
-			uint32_t blockSize);
-
-
-  /**
-   * @brief Initialization function for Q15 normalized LMS filter.
-   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
-   * @param[in] numTaps  number of filter coefficients.
-   * @param[in] *pCoeffs points to coefficient buffer.
-   * @param[in] *pState points to state buffer.
-   * @param[in] mu step size that controls filter coefficient updates.
-   * @param[in] blockSize number of samples to process.
-   * @param[in] postShift bit shift applied to coefficients.
-   * @return none.
-   */
-
-  void arm_lms_norm_init_q15(
-			     arm_lms_norm_instance_q15 * S,
-			     uint16_t numTaps,
-			     q15_t * pCoeffs,
-			     q15_t * pState,
-			     q15_t mu,
-			     uint32_t blockSize,
-			     uint8_t postShift);
-
-  /**
-   * @brief Correlation of floating-point sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_f32(
-			  float32_t * pSrcA,
-			 uint32_t srcALen,
-			  float32_t * pSrcB,
-			 uint32_t srcBLen,
-			 float32_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q15(
-			  q15_t * pSrcA,
-			 uint32_t srcALen,
-			  q15_t * pSrcB,
-			 uint32_t srcBLen,
-			 q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q15(
-			       q15_t * pSrcA,
-			      uint32_t srcALen,
-			       q15_t * pSrcB,
-			      uint32_t srcBLen,
-			      q15_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q31(
-			  q31_t * pSrcA,
-			 uint32_t srcALen,
-			  q31_t * pSrcB,
-			 uint32_t srcBLen,
-			 q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_fast_q31(
-			       q31_t * pSrcA,
-			      uint32_t srcALen,
-			       q31_t * pSrcB,
-			      uint32_t srcBLen,
-			      q31_t * pDst);
-
-  /**
-   * @brief Correlation of Q7 sequences.
-   * @param[in] *pSrcA points to the first input sequence.
-   * @param[in] srcALen length of the first input sequence.
-   * @param[in] *pSrcB points to the second input sequence.
-   * @param[in] srcBLen length of the second input sequence.
-   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
-   * @return none.
-   */
-
-  void arm_correlate_q7(
-			 q7_t * pSrcA,
-			uint32_t srcALen,
-			 q7_t * pSrcB,
-			uint32_t srcBLen,
-			q7_t * pDst);
-
-  /**
-   * @brief Instance structure for the floating-point sparse FIR filter.
-   */
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_f32;
-
-  /**
-   * @brief Instance structure for the Q31 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q31;
-
-  /**
-   * @brief Instance structure for the Q15 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q15;
-
-  /**
-   * @brief Instance structure for the Q7 sparse FIR filter.
-   */
-
-  typedef struct
-  {
-    uint16_t numTaps;             /**< number of coefficients in the filter. */
-    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
-    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
-    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
-    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
-    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
-  } arm_fir_sparse_instance_q7;
-
-  /**
-   * @brief Processing function for the floating-point sparse FIR filter.
-   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_f32(
-			  arm_fir_sparse_instance_f32 * S,
-			   float32_t * pSrc,
-			  float32_t * pDst,
-			  float32_t * pScratchIn,
-			  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the floating-point sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_f32(
-			       arm_fir_sparse_instance_f32 * S,
-			       uint16_t numTaps,
-			       float32_t * pCoeffs,
-			       float32_t * pState,
-			       int32_t * pTapDelay,
-			       uint16_t maxDelay,
-			       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q31 sparse FIR filter.
-   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
-   * @param[in]  *pSrc       points to the block of input data.
-   * @param[out] *pDst       points to the block of output data
-   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize   number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q31(
-			  arm_fir_sparse_instance_q31 * S,
-			   q31_t * pSrc,
-			  q31_t * pDst,
-			  q31_t * pScratchIn,
-			  uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q31 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q31(
-			       arm_fir_sparse_instance_q31 * S,
-			       uint16_t numTaps,
-			       q31_t * pCoeffs,
-			       q31_t * pState,
-			       int32_t * pTapDelay,
-			       uint16_t maxDelay,
-			       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q15 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q15(
-			  arm_fir_sparse_instance_q15 * S,
-			   q15_t * pSrc,
-			  q15_t * pDst,
-			  q15_t * pScratchIn,
-			  q31_t * pScratchOut,
-			  uint32_t blockSize);
-
-
-  /**
-   * @brief  Initialization function for the Q15 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q15(
-			       arm_fir_sparse_instance_q15 * S,
-			       uint16_t numTaps,
-			       q15_t * pCoeffs,
-			       q15_t * pState,
-			       int32_t * pTapDelay,
-			       uint16_t maxDelay,
-			       uint32_t blockSize);
-
-  /**
-   * @brief Processing function for the Q7 sparse FIR filter.
-   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
-   * @param[in]  *pSrc        points to the block of input data.
-   * @param[out] *pDst        points to the block of output data
-   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
-   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
-   * @param[in]  blockSize    number of input samples to process per call.
-   * @return none.
-   */
-
-  void arm_fir_sparse_q7(
-			 arm_fir_sparse_instance_q7 * S,
-			  q7_t * pSrc,
-			 q7_t * pDst,
-			 q7_t * pScratchIn,
-			 q31_t * pScratchOut,
-			 uint32_t blockSize);
-
-  /**
-   * @brief  Initialization function for the Q7 sparse FIR filter.
-   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
-   * @param[in]     numTaps    number of nonzero coefficients in the filter.
-   * @param[in]     *pCoeffs   points to the array of filter coefficients.
-   * @param[in]     *pState    points to the state buffer.
-   * @param[in]     *pTapDelay points to the array of offset times.
-   * @param[in]     maxDelay   maximum offset time supported.
-   * @param[in]     blockSize  number of samples that will be processed per block.
-   * @return none
-   */
-
-  void arm_fir_sparse_init_q7(
-			      arm_fir_sparse_instance_q7 * S,
-			      uint16_t numTaps,
-			      q7_t * pCoeffs,
-			      q7_t * pState,
-			      int32_t *pTapDelay,
-			      uint16_t maxDelay,
-			      uint32_t blockSize);
-
-
-  /*
-   * @brief  Floating-point sin_cos function.
-   * @param[in]  theta    input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cos output. 
-   * @return none.
-   */
-
-  void arm_sin_cos_f32(
-		       float32_t theta,
-		       float32_t *pSinVal,
-		       float32_t *pCcosVal);
-
-  /*
-   * @brief  Q31 sin_cos function.
-   * @param[in]  theta    scaled input value in degrees 
-   * @param[out] *pSinVal points to the processed sine output. 
-   * @param[out] *pCosVal points to the processed cosine output. 
-   * @return none.
-   */
-
-  void arm_sin_cos_q31(
-		       q31_t theta,
-		       q31_t *pSinVal,
-		       q31_t *pCosVal);
-
-
-  /**
-   * @brief  Floating-point complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_f32(
-			   float32_t * pSrc,
-			  float32_t * pDst,
-			  uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q31(
-			   q31_t * pSrc,
-			  q31_t * pDst,
-			  uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex conjugate.
-   * @param[in]  *pSrc points to the input vector
-   * @param[out]  *pDst points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_conj_q15(
-			   q15_t * pSrc,
-			  q15_t * pDst,
-			  uint32_t numSamples);
-
-
-
-  /**
-   * @brief  Floating-point complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_f32(
-				  float32_t * pSrc,
-				 float32_t * pDst,
-				 uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q31(
-				  q31_t * pSrc,
-				 q31_t * pDst,
-				 uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude squared
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_squared_q15(
-				  q15_t * pSrc,
-				 q15_t * pDst,
-				 uint32_t numSamples);
-
-
- /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup PID PID Motor Control
-   *
-   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
-   * loop mechanism widely used in industrial control systems.
-   * A PID controller is the most commonly used type of feedback controller.
-   *
-   * This set of functions implements (PID) controllers
-   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
-   * of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
-   * is the input sample value. The functions return the output value.
-   *
-   * \par Algorithm:
-   * <pre>
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  </pre>
-   *
-   * \par
-   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
-   * 
-   * \par 
-   * \image html PID.gif "Proportional Integral Derivative Controller" 
-   *
-   * \par
-   * The PID controller calculates an "error" value as the difference between
-   * the measured output and the reference input.
-   * The controller attempts to minimize the error by adjusting the process control inputs.  
-   * The proportional value determines the reaction to the current error, 
-   * the integral value determines the reaction based on the sum of recent errors, 
-   * and the derivative value determines the reaction based on the rate at which the error has been changing.
-   *
-   * \par Instance Structure 
-   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
-   * A separate instance structure must be defined for each PID Controller. 
-   * There are separate instance structure declarations for each of the 3 supported data types. 
-   * 
-   * \par Reset Functions 
-   * There is also an associated reset function for each data type which clears the state array. 
-   *
-   * \par Initialization Functions 
-   * There is also an associated initialization function for each data type. 
-   * The initialization function performs the following operations: 
-   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
-   * - Zeros out the values in the state buffer.   
-   * 
-   * \par 
-   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
-   *
-   * \par Fixed-Point Behavior 
-   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
-   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
-   * Refer to the function specific documentation below for usage guidelines. 
-   */
-
-  /**
-   * @addtogroup PID
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point PID Control.
-   * @param[in,out] *S is an instance of the floating-point PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   */
-
-
-  static __INLINE float32_t arm_pid_f32(
-					arm_pid_instance_f32 * S,
-					float32_t in)
-  {
-    float32_t out;
-
-    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
-    out = (S->A0 * in) +
-      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q31 PID Control.
-   * @param[in,out] *S points to an instance of the Q31 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b> 
-   * \par 
-   * The function is implemented using an internal 64-bit accumulator. 
-   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
-   * Thus, if the accumulator result overflows it wraps around rather than clip. 
-   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
-   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
-   */
-
-  static __INLINE q31_t arm_pid_q31(
-				    arm_pid_instance_q31 * S,
-				    q31_t in)
-  {
-    q63_t acc;
-	q31_t out;
-
-    /* acc = A0 * x[n]  */
-    acc = (q63_t) S->A0 * in;
-
-    /* acc += A1 * x[n-1] */
-    acc += (q63_t) S->A1 * S->state[0];
-
-    /* acc += A2 * x[n-2]  */
-    acc += (q63_t) S->A2 * S->state[1];
-
-    /* convert output to 1.31 format to add y[n-1] */
-    out = (q31_t) (acc >> 31u);
-
-    /* out += y[n-1] */
-    out += S->state[2];
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-
-  /**
-   * @brief  Process function for the Q15 PID Control.
-   * @param[in,out] *S points to an instance of the Q15 PID Control structure
-   * @param[in] in input sample to process
-   * @return out processed output sample.
-   *
-   * <b>Scaling and Overflow Behavior:</b> 
-   * \par 
-   * The function is implemented using a 64-bit internal accumulator. 
-   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
-   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
-   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
-   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
-   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
-   */
-
-  static __INLINE q15_t arm_pid_q15(
-				    arm_pid_instance_q15 * S,
-				    q15_t in)
-  {
-    q63_t acc;
-    q15_t out;
-
-    /* Implementation of PID controller */
-
-	#ifdef ARM_MATH_CM0
-
- 	/* acc = A0 * x[n]  */
-	acc = ((q31_t) S->A0 )* in ;
-
-    #else
-				
-    /* acc = A0 * x[n]  */
-    acc = (q31_t) __SMUAD(S->A0, in);
-	
-	#endif
-
-	#ifdef ARM_MATH_CM0
-						   
-	/* acc += A1 * x[n-1] + A2 * x[n-2]  */
-	acc += (q31_t) S->A1  *  S->state[0] ;
-	acc += (q31_t) S->A2  *  S->state[1] ;
-
-	#else
-
-    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
-    acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
-
-	#endif
-
-    /* acc += y[n-1] */
-    acc += (q31_t) S->state[2] << 15;
-
-    /* saturate the output */
-    out = (q15_t) (__SSAT((acc >> 15), 16));
-
-    /* Update state */
-    S->state[1] = S->state[0];
-    S->state[0] = in;
-    S->state[2] = out;
-
-    /* return to application */
-    return (out);
-
-  }
-  
-  /**
-   * @} end of PID group
-   */
-
-
-  /**
-   * @brief Floating-point matrix inverse.
-   * @param[in]  *src points to the instance of the input floating-point matrix structure.
-   * @param[out] *dst points to the instance of the output floating-point matrix structure.
-   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
-   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
-   */
-
-  arm_status arm_mat_inverse_f32(
-				 const arm_matrix_instance_f32 * src,
-				 arm_matrix_instance_f32 * dst);
-
-  
- 
-  /**
-   * @ingroup groupController
-   */
-
-
-  /**
-   * @defgroup clarke Vector Clarke Transform
-   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
-   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
-   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
-   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
-   * \image html clarke.gif Stator current space vector and its components in (a,b).
-   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
-   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeFormula.gif
-   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
-   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup clarke
-   * @{
-   */
-
-  /**
-   *
-   * @brief  Floating-point Clarke transform
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   */
-
-  static __INLINE void arm_clarke_f32(
-				      float32_t Ia,
-				      float32_t Ib,
-				      float32_t * pIalpha,
-				      float32_t * pIbeta)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
-    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
-  }
-
-  /**
-   * @brief  Clarke transform for Q31 version
-   * @param[in]       Ia       input three-phase coordinate <code>a</code>
-   * @param[in]       Ib       input three-phase coordinate <code>b</code>
-   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_clarke_q31(
-				      q31_t Ia,
-				      q31_t Ib,
-				      q31_t * pIalpha,
-				      q31_t * pIbeta)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
-    *pIalpha = Ia;
-
-    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
-    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
-    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
-    /* pIbeta is calculated by adding the intermediate products */
-    *pIbeta = __QADD(product1, product2);
-  }
-
-  /**
-   * @} end of clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q31 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out]  *pDst    output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q31(
-		     q7_t * pSrc,
-		     q31_t * pDst,
-		     uint32_t blockSize);
-
-
- 
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_clarke Vector Inverse Clarke Transform
-   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
-   * 
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html clarkeInvFormula.gif
-   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
-   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Clarke transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_clarke
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Clarke transform
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   */
-
-
-  static __INLINE void arm_inv_clarke_f32(
-					  float32_t Ialpha,
-					  float32_t Ibeta,
-					  float32_t * pIa,
-					  float32_t * pIb)
-  {
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
-    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
-  }
-
-  /**
-   * @brief  Inverse Clarke transform for Q31 version 
-   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
-   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
-   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
-   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the subtraction, hence there is no risk of overflow.
-   */
-
-  static __INLINE void arm_inv_clarke_q31(
-					  q31_t Ialpha,
-					  q31_t Ibeta,
-					  q31_t * pIa,
-					  q31_t * pIb)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-
-    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
-    *pIa = Ialpha;
-
-    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
-    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
-    /* pIb is calculated by subtracting the products */
-    *pIb = __QSUB(product2, product1);
-
-  }
-
-  /**
-   * @} end of inv_clarke group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to Q15 vector.
-   * @param[in]  *pSrc     input pointer
-   * @param[out] *pDst     output pointer
-   * @param[in]  blockSize number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_q15(
-		      q7_t * pSrc,
-		     q15_t * pDst,
-		     uint32_t blockSize);
-
-  
-
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup park Vector Park Transform
-   *
-   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
-   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents 
-   * from the stationary to the moving reference frame and control the spatial relationship between 
-   * the stator vector current and rotor flux vector.
-   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
-   * current vector and the relationship from the two reference frames:
-   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkFormula.gif
-   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,  
-   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup park
-   * @{
-   */
-
-  /**
-   * @brief Floating-point Park transform
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output	rotor reference frame d
-   * @param[out]      *pIq   points to output	rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * The function implements the forward Park transform.
-   *
-   */
-
-  static __INLINE void arm_park_f32(
-				    float32_t Ialpha,
-				    float32_t Ibeta,
-				    float32_t * pId,
-				    float32_t * pIq,
-				    float32_t sinVal,
-				    float32_t cosVal)
-  {
-    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
-    *pId = Ialpha * cosVal + Ibeta * sinVal;
-
-    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
-    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
-  }
-
-  /**
-   * @brief  Park transform for Q31 version 
-   * @param[in]       Ialpha input two-phase vector coordinate alpha
-   * @param[in]       Ibeta  input two-phase vector coordinate beta
-   * @param[out]      *pId   points to output rotor reference frame d
-   * @param[out]      *pIq   points to output rotor reference frame q
-   * @param[in]       sinVal sine value of rotation angle theta
-   * @param[in]       cosVal cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_park_q31(
-				    q31_t Ialpha,
-				    q31_t Ibeta,
-				    q31_t * pId,
-				    q31_t * pIq,
-				    q31_t sinVal,
-				    q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Ialpha * cosVal) */
-    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * sinVal) */
-    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Ialpha * sinVal) */
-    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Ibeta * cosVal) */
-    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
-    /* Calculate pId by adding the two intermediate products 1 and 2 */
-    *pId = __QADD(product1, product2);
-
-    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
-    *pIq = __QSUB(product4, product3);
-  }
-
-  /**
-   * @} end of park group
-   */
-
-  /**
-   * @brief  Converts the elements of the Q7 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q7_to_float(
-		        q7_t * pSrc,
-		       float32_t * pDst,
-		       uint32_t blockSize);
-
- 
-  /**
-   * @ingroup groupController
-   */
-
-  /**
-   * @defgroup inv_park Vector Inverse Park transform
-   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
-   *
-   * The function operates on a single sample of data and each call to the function returns the processed output. 
-   * The library provides separate functions for Q31 and floating-point data types.
-   * \par Algorithm
-   * \image html parkInvFormula.gif
-   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,  
-   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the 
-   * cosine and sine values of theta (rotor flux position).
-   * \par Fixed-Point Behavior
-   * Care must be taken when using the Q31 version of the Park transform.
-   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
-   * Refer to the function specific documentation below for usage guidelines.
-   */
-
-  /**
-   * @addtogroup inv_park
-   * @{
-   */
-
-   /**
-   * @brief  Floating-point Inverse Park transform
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   */
-
-  static __INLINE void arm_inv_park_f32(
-					float32_t Id,
-					float32_t Iq,
-					float32_t * pIalpha,
-					float32_t * pIbeta,
-					float32_t sinVal,
-					float32_t cosVal)
-  {
-    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
-    *pIalpha = Id * cosVal - Iq * sinVal;
-
-    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
-    *pIbeta = Id * sinVal + Iq * cosVal;
-
-  }
-
-
-  /**
-   * @brief  Inverse Park transform for	Q31 version 
-   * @param[in]       Id        input coordinate of rotor reference frame d
-   * @param[in]       Iq        input coordinate of rotor reference frame q
-   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
-   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
-   * @param[in]       sinVal    sine value of rotation angle theta
-   * @param[in]       cosVal    cosine value of rotation angle theta
-   * @return none.
-   *
-   * <b>Scaling and Overflow Behavior:</b>
-   * \par
-   * The function is implemented using an internal 32-bit accumulator.
-   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
-   * There is saturation on the addition, hence there is no risk of overflow.
-   */
-
-
-  static __INLINE void arm_inv_park_q31(
-					q31_t Id,
-					q31_t Iq,
-					q31_t * pIalpha,
-					q31_t * pIbeta,
-					q31_t sinVal,
-					q31_t cosVal)
-  {
-    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
-    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
-
-    /* Intermediate product is calculated by (Id * cosVal) */
-    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * sinVal) */
-    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
-    /* Intermediate product is calculated by (Id * sinVal) */
-    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
-    /* Intermediate product is calculated by (Iq * cosVal) */
-    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
-    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
-    *pIalpha = __QSUB(product1, product2);
-
-    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
-    *pIbeta = __QADD(product4, product3);
-
-  }
-
-  /**
-   * @} end of Inverse park group
-   */
-
-   
-  /**
-   * @brief  Converts the elements of the Q31 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_float(
-			 q31_t * pSrc,
-			float32_t * pDst,
-			uint32_t blockSize);
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup LinearInterpolate Linear Interpolation
-   *
-   * Linear interpolation is a method of curve fitting using linear polynomials.
-   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
-   *
-   * \par 
-   * \image html LinearInterp.gif "Linear interpolation"
-   *
-   * \par
-   * A  Linear Interpolate function calculates an output value(y), for the input(x)
-   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
-   *
-   * \par Algorithm:
-   * <pre>
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * </pre>
-   *
-   * \par
-   * This set of functions implements Linear interpolation process
-   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
-   * sample of data and each call to the function returns a single processed value.
-   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
-   * <code>x</code> is the input sample value. The functions returns the output value.
-   * 
-   * \par
-   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
-   * if x is below input range and returns last value of table if x is above range.  
-   */
-
-  /**
-   * @addtogroup LinearInterpolate
-   * @{
-   */
-
-  /**
-   * @brief  Process function for the floating-point Linear Interpolation Function.
-   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
-   * @param[in] x input sample to process
-   * @return y processed output sample.
-   *
-   */
-
-  static __INLINE float32_t arm_linear_interp_f32(
-						  arm_linear_interp_instance_f32 * S,
-						  float32_t x)
-  {
-
-	  float32_t y;
-	  float32_t x0, x1;						/* Nearest input values */
-	  float32_t y0, y1;	  					/* Nearest output values */
-	  float32_t xSpacing = S->xSpacing;		/* spacing between input values */
-	  int32_t i;  							/* Index variable */
-	  float32_t *pYData = S->pYData;	    /* pointer to output table */
-
-	  /* Calculation of index */
-	  i =   (x - S->x1) / xSpacing;
-
-	  if(i < 0)
-	  {
-	     /* Iniatilize output for below specified range as least output value of table */
-		 y = pYData[0];
-	  }
-	  else if(i >= S->nValues)
-	  {
-	  	  /* Iniatilize output for above specified range as last output value of table */
-	  	  y = pYData[S->nValues-1];	
-	  }
-	  else
-	  {	 
-	  	  /* Calculation of nearest input values */
-		  x0 = S->x1 + i * xSpacing;
-		  x1 = S->x1 + (i +1) * xSpacing;
-		 
-		 /* Read of nearest output values */
-		  y0 = pYData[i];
-		  y1 = pYData[i + 1];
-		
-		  /* Calculation of output */
-		  y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));	
-		
-	  }
-
-      /* returns output value */
-	  return (y);
-  }
-
-   /**
-   *
-   * @brief  Process function for the Q31 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   *
-   */
-
-
-  static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
-					      q31_t x, uint32_t nValues)
-  {
-    q31_t y;                                   /* output */
-    q31_t y0, y1;                                /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                              /* Index to read nearest output values */
-    
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20);
-
-	if(index >= (nValues - 1))
-	{
-		return(pYData[nValues - 1]);
-	}
-	else if(index < 0)
-	{
-		return(pYData[0]);
-	}
-	else
-	{
-
-	    /* 20 bits for the fractional part */
-	    /* shift left by 11 to keep fract in 1.31 format */
-	    fract = (x & 0x000FFFFF) << 11;
-	
-	    /* Read two nearest output values from the index in 1.31(q31) format */
-	    y0 = pYData[index];
-	    y1 = pYData[index + 1u];
-	
-	    /* Calculation of y0 * (1-fract) and y is in 2.30 format */
-	    y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-	
-	    /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
-	    y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-	
-	    /* Convert y to 1.31 format */
-	    return (y << 1u);
-
-	}
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q15 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12. 
-   *
-   */
-
-
-  static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
-  {
-    q63_t y;                                   /* output */
-    q15_t y0, y1;                              /* Nearest output values */
-    q31_t fract;                               /* fractional part */
-    int32_t index;                            /* Index to read nearest output values */ 
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u); 
-
-	if(index >= (nValues - 1))
-	{
-		return(pYData[nValues - 1]);
-	}
-	else if(index < 0)
-	{
-		return(pYData[0]);
-	}
-	else
-	{	
-	    /* 20 bits for the fractional part */
-	    /* fract is in 12.20 format */
-	    fract = (x & 0x000FFFFF);
-	
-	    /* Read two nearest output values from the index */
-	    y0 = pYData[index];
-	    y1 = pYData[index + 1u];
-	
-	    /* Calculation of y0 * (1-fract) and y is in 13.35 format */
-	    y = ((q63_t) y0 * (0xFFFFF - fract));
-	
-	    /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
-	    y += ((q63_t) y1 * (fract));
-	
-	    /* convert y to 1.15 format */
-	    return (y >> 20);
-	}
-
-
-  }
-
-  /**
-   *
-   * @brief  Process function for the Q7 Linear Interpolation Function.
-   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
-   * @param[in] x input sample to process
-   * @param[in] nValues number of table values
-   * @return y processed output sample.
-   *
-   * \par
-   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
-   * This function can support maximum of table size 2^12.
-   */
-
-
-  static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x,  uint32_t nValues)
-  {
-    q31_t y;                                   /* output */
-    q7_t y0, y1;                                 /* Nearest output values */
-    q31_t fract;                                 /* fractional part */
-    int32_t index;                              /* Index to read nearest output values */
-    
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    index = ((x & 0xFFF00000) >> 20u);
-
-
-    if(index >= (nValues - 1))
-	{
-		return(pYData[nValues - 1]);
-	}
-	else if(index < 0)
-	{
-		return(pYData[0]);
-	}
-	else
-	{
-
-	    /* 20 bits for the fractional part */
-	    /* fract is in 12.20 format */
-	    fract = (x & 0x000FFFFF);
-	
-	    /* Read two nearest output values from the index and are in 1.7(q7) format */
-	    y0 = pYData[index];
-	    y1 = pYData[index + 1u];
-	
-	    /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
-	    y = ((y0 * (0xFFFFF - fract)));
-	
-	    /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
-	    y += (y1 * fract);
-	
-	    /* convert y to 1.7(q7) format */
-	    return (y >> 20u);
-
-	}
-
-  }
-  /**
-   * @} end of LinearInterpolate group
-   */
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  sin(x).
-   */
-
-  float32_t arm_sin_f32(
-			 float32_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q31_t arm_sin_q31(
-		     q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  sin(x).
-   */
-
-  q15_t arm_sin_q15(
-		     q15_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
-   * @param[in] x input value in radians.
-   * @return  cos(x).
-   */
-
-  float32_t arm_cos_f32(
-			 float32_t x);
-
-  /**
-   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q31_t arm_cos_q31(
-		     q31_t x);
-
-  /**
-   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
-   * @param[in] x Scaled input value in radians.
-   * @return  cos(x).
-   */
-
-  q15_t arm_cos_q15(
-		     q15_t x);
-
-
-  /**
-   * @ingroup groupFastMath
-   */
-
-
-  /**
-   * @defgroup SQRT Square Root
-   *
-   * Computes the square root of a number.
-   * There are separate functions for Q15, Q31, and floating-point data types.  
-   * The square root function is computed using the Newton-Raphson algorithm.
-   * This is an iterative algorithm of the form:
-   * <pre>
-   *      x1 = x0 - f(x0)/f'(x0)
-   * </pre>
-   * where <code>x1</code> is the current estimate,
-   * <code>x0</code> is the previous estimate and
-   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
-   * For the square root function, the algorithm reduces to:
-   * <pre>
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * </pre>
-   */
-
-
-  /**
-   * @addtogroup SQRT
-   * @{
-   */
-
-  /**
-   * @brief  Floating-point square root function.
-   * @param[in]  in     input value.
-   * @param[out] *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-
-  static __INLINE arm_status  arm_sqrt_f32(
-					  float32_t in, float32_t *pOut)
-  {
-  	if(in > 0)
-	{
-
-//	#if __FPU_USED
-    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
-		*pOut = __sqrtf(in);
-	#else	  
-		*pOut = sqrtf(in);
-	#endif
-
-		return (ARM_MATH_SUCCESS);
-	}
-  	else
-	{
-		*pOut = 0.0f;
-		return (ARM_MATH_ARGUMENT_ERROR);
-	}
-
-  }
-
-
-  /**
-   * @brief Q31 square root function.
-   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
-   * @param[out]  *pOut square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q31(
-		      q31_t in, q31_t *pOut);
-
-  /**
-   * @brief  Q15 square root function.
-   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
-   * @param[out]  *pOut  square root of input value.
-   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
-   * <code>in</code> is negative value and returns zero output for negative values.
-   */
-  arm_status arm_sqrt_q15(
-		      q15_t in, q15_t *pOut);
-
-  /**
-   * @} end of SQRT group
-   */
-
-
-
-
-
-
-  /**
-   * @brief floating-point Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_f32(
-					     int32_t * circBuffer,
-					     int32_t L,
-					     uint16_t * writeOffset,
-					     int32_t bufferInc,
-					     const int32_t * src,
-					     int32_t srcInc,
-					     uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the input sample to the circular buffer */
-	circBuffer[wOffset] = *src;
-
-	/* Update the input pointer */
-	src += srcInc;
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	wOffset += bufferInc;
-	if(wOffset >= L)
-	  wOffset -= L;
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief floating-point Circular Read function.
-   */
-  static __INLINE void arm_circularRead_f32(
-					    int32_t * circBuffer,
-					    int32_t L,
-					    int32_t * readOffset,
-					    int32_t bufferInc,
-					    int32_t * dst,
-					    int32_t * dst_base,
-					    int32_t dst_length,
-					    int32_t dstInc,
-					    uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the sample from the circular buffer to the destination buffer */
-	*dst = circBuffer[rOffset];
-
-	/* Update the input pointer */
-	dst += dstInc;
-
-	if(dst == (int32_t *) dst_end)
-	  {
-	    dst = dst_base;
-	  }
-
-	/* Circularly update rOffset.  Watch out for positive and negative value  */
-	rOffset += bufferInc;
-
-	if(rOffset >= L)
-	  {
-	    rOffset -= L;
-	  }
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-  /**
-   * @brief Q15 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q15(
-					     q15_t * circBuffer,
-					     int32_t L,
-					     uint16_t * writeOffset,
-					     int32_t bufferInc,
-					     const q15_t * src,
-					     int32_t srcInc,
-					     uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the input sample to the circular buffer */
-	circBuffer[wOffset] = *src;
-
-	/* Update the input pointer */
-	src += srcInc;
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	wOffset += bufferInc;
-	if(wOffset >= L)
-	  wOffset -= L;
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q15 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q15(
-					    q15_t * circBuffer,
-					    int32_t L,
-					    int32_t * readOffset,
-					    int32_t bufferInc,
-					    q15_t * dst,
-					    q15_t * dst_base,
-					    int32_t dst_length,
-					    int32_t dstInc,
-					    uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the sample from the circular buffer to the destination buffer */
-	*dst = circBuffer[rOffset];
-
-	/* Update the input pointer */
-	dst += dstInc;
-
-	if(dst == (q15_t *) dst_end)
-	  {
-	    dst = dst_base;
-	  }
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	rOffset += bufferInc;
-
-	if(rOffset >= L)
-	  {
-	    rOffset -= L;
-	  }
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief Q7 Circular write function.
-   */
-
-  static __INLINE void arm_circularWrite_q7(
-					    q7_t * circBuffer,
-					    int32_t L,
-					    uint16_t * writeOffset,
-					    int32_t bufferInc,
-					    const q7_t * src,
-					    int32_t srcInc,
-					    uint32_t blockSize)
-  {
-    uint32_t i = 0u;
-    int32_t wOffset;
-
-    /* Copy the value of Index pointer that points
-     * to the current location where the input samples to be copied */
-    wOffset = *writeOffset;
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the input sample to the circular buffer */
-	circBuffer[wOffset] = *src;
-
-	/* Update the input pointer */
-	src += srcInc;
-
-	/* Circularly update wOffset.  Watch out for positive and negative value */
-	wOffset += bufferInc;
-	if(wOffset >= L)
-	  wOffset -= L;
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *writeOffset = wOffset;
-  }
-
-
-
-  /**
-   * @brief Q7 Circular Read function.
-   */
-  static __INLINE void arm_circularRead_q7(
-					   q7_t * circBuffer,
-					   int32_t L,
-					   int32_t * readOffset,
-					   int32_t bufferInc,
-					   q7_t * dst,
-					   q7_t * dst_base,
-					   int32_t dst_length,
-					   int32_t dstInc,
-					   uint32_t blockSize)
-  {
-    uint32_t i = 0;
-    int32_t rOffset, dst_end;
-
-    /* Copy the value of Index pointer that points
-     * to the current location from where the input samples to be read */
-    rOffset = *readOffset;
-
-    dst_end = (int32_t) (dst_base + dst_length);
-
-    /* Loop over the blockSize */
-    i = blockSize;
-
-    while(i > 0u)
-      {
-	/* copy the sample from the circular buffer to the destination buffer */
-	*dst = circBuffer[rOffset];
-
-	/* Update the input pointer */
-	dst += dstInc;
-
-	if(dst == (q7_t *) dst_end)
-	  {
-	    dst = dst_base;
-	  }
-
-	/* Circularly update rOffset.  Watch out for positive and negative value */
-	rOffset += bufferInc;
-
-	if(rOffset >= L)
-	  {
-	    rOffset -= L;
-	  }
-
-	/* Decrement the loop counter */
-	i--;
-      }
-
-    /* Update the index pointer */
-    *readOffset = rOffset;
-  }
-
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q31(
-		      q31_t * pSrc,
-		     uint32_t blockSize,
-		     q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_f32(
-		      float32_t * pSrc,
-		     uint32_t blockSize,
-		     float32_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q15(
-		      q15_t * pSrc,
-		     uint32_t blockSize,
-		     q63_t * pResult);
-
-  /**
-   * @brief  Sum of the squares of the elements of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_power_q7(
-		     q7_t * pSrc,
-		    uint32_t blockSize,
-		    q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_mean_q7(
-		    q7_t * pSrc,
-		   uint32_t blockSize,
-		   q7_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q15(
-		     q15_t * pSrc,
-		    uint32_t blockSize,
-		    q15_t * pResult);
-
-  /**
-   * @brief  Mean value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_q31(
-		     q31_t * pSrc,
-		    uint32_t blockSize,
-		    q31_t * pResult);
-
-  /**
-   * @brief  Mean value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-  void arm_mean_f32(
-		     float32_t * pSrc,
-		    uint32_t blockSize,
-		    float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q63_t * pResult);
-
-  /**
-   * @brief  Variance of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_var_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult);
-
-  /**
-   * @brief  Root Mean Square of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_rms_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult);
-
-  /**
-   * @brief  Standard deviation of the elements of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output value.
-   * @return none.
-   */
-
-  void arm_std_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult);
-
-  /**
-   * @brief  Floating-point complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_f32(
-			  float32_t * pSrc,
-			 float32_t * pDst,
-			 uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q31(
-			  q31_t * pSrc,
-			 q31_t * pDst,
-			 uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex magnitude
-   * @param[in]  *pSrc points to the complex input vector
-   * @param[out]  *pDst points to the real output vector
-   * @param[in]  numSamples number of complex samples in the input vector
-   * @return none.
-   */
-
-  void arm_cmplx_mag_q15(
-			  q15_t * pSrc,
-			 q15_t * pDst,
-			 uint32_t numSamples);
-
-  /**
-   * @brief  Q15 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q15(
-			       q15_t * pSrcA,
-			       q15_t * pSrcB,
-			      uint32_t numSamples,
-			      q31_t * realResult,
-			      q31_t * imagResult);
-
-  /**
-   * @brief  Q31 complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_q31(
-			       q31_t * pSrcA,
-			       q31_t * pSrcB,
-			      uint32_t numSamples,
-			      q63_t * realResult,
-			      q63_t * imagResult);
-
-  /**
-   * @brief  Floating-point complex dot product
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @param[out]  *realResult real part of the result returned here
-   * @param[out]  *imagResult imaginary part of the result returned here
-   * @return none.
-   */
-
-  void arm_cmplx_dot_prod_f32(
-			       float32_t * pSrcA,
-			       float32_t * pSrcB,
-			      uint32_t numSamples,
-			      float32_t * realResult,
-			      float32_t * imagResult);
-
-  /**
-   * @brief  Q15 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q15(
-			        q15_t * pSrcCmplx,
-			        q15_t * pSrcReal,
-			       q15_t * pCmplxDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_q31(
-			        q31_t * pSrcCmplx,
-			        q31_t * pSrcReal,
-			       q31_t * pCmplxDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-real multiplication
-   * @param[in]  *pSrcCmplx points to the complex input vector
-   * @param[in]  *pSrcReal points to the real input vector
-   * @param[out]  *pCmplxDst points to the complex output vector
-   * @param[in]  numSamples number of samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_real_f32(
-			        float32_t * pSrcCmplx,
-			        float32_t * pSrcReal,
-			       float32_t * pCmplxDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Minimum value of a Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *result is output pointer
-   * @param[in]  index is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q7(
-		   q7_t * pSrc,
-		  uint32_t blockSize,
-		  q7_t * result,
-		  uint32_t * index);
-
-  /**
-   * @brief  Minimum value of a Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult,
-		   uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-  void arm_min_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult,
-		   uint32_t * pIndex);
-
-  /**
-   * @brief  Minimum value of a floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @param[out]  *pResult is output pointer
-   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
-   * @return none.
-   */
-
-  void arm_min_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult,
-		   uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q7(
-		   q7_t * pSrc,
-		  uint32_t blockSize,
-		  q7_t * pResult,
-		  uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q15(
-		    q15_t * pSrc,
-		   uint32_t blockSize,
-		   q15_t * pResult,
-		   uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_q31(
-		    q31_t * pSrc,
-		   uint32_t blockSize,
-		   q31_t * pResult,
-		   uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in]       *pSrc points to the input buffer
- * @param[in]       blockSize length of the input vector
- * @param[out]      *pResult maximum value returned here
- * @param[out]      *pIndex index of maximum value returned here
- * @return none.
- */
-
-  void arm_max_f32(
-		    float32_t * pSrc,
-		   uint32_t blockSize,
-		   float32_t * pResult,
-		   uint32_t * pIndex);
-
-  /**
-   * @brief  Q15 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q15(
-			        q15_t * pSrcA,
-			        q15_t * pSrcB,
-			       q15_t * pDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Q31 complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_q31(
-			        q31_t * pSrcA,
-			        q31_t * pSrcB,
-			       q31_t * pDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief  Floating-point complex-by-complex multiplication
-   * @param[in]  *pSrcA points to the first input vector
-   * @param[in]  *pSrcB points to the second input vector
-   * @param[out]  *pDst  points to the output vector
-   * @param[in]  numSamples number of complex samples in each vector
-   * @return none.
-   */
-
-  void arm_cmplx_mult_cmplx_f32(
-			        float32_t * pSrcA,
-			        float32_t * pSrcB,
-			       float32_t * pDst,
-			       uint32_t numSamples);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q31 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q31 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return none. 
-   */
-  void arm_float_to_q31(
-			       float32_t * pSrc,
-			      q31_t * pDst,
-			      uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q15 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q15 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return          none
-   */
-  void arm_float_to_q15(
-			       float32_t * pSrc,
-			      q15_t * pDst,
-			      uint32_t blockSize);
-
-  /**
-   * @brief Converts the elements of the floating-point vector to Q7 vector. 
-   * @param[in]       *pSrc points to the floating-point input vector 
-   * @param[out]      *pDst points to the Q7 output vector
-   * @param[in]       blockSize length of the input vector 
-   * @return          none
-   */
-  void arm_float_to_q7(
-			      float32_t * pSrc,
-			     q7_t * pDst,
-			     uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q15 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q15(
-		       q31_t * pSrc,
-		      q15_t * pDst,
-		      uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q31 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q31_to_q7(
-		      q31_t * pSrc,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to floating-point vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_float(
-			 q15_t * pSrc,
-			float32_t * pDst,
-			uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q31 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q31(
-		       q15_t * pSrc,
-		      q31_t * pDst,
-		      uint32_t blockSize);
-
-
-  /**
-   * @brief  Converts the elements of the Q15 vector to Q7 vector.
-   * @param[in]  *pSrc is input pointer
-   * @param[out]  *pDst is output pointer
-   * @param[in]  blockSize is the number of samples to process
-   * @return none.
-   */
-  void arm_q15_to_q7(
-		      q15_t * pSrc,
-		     q7_t * pDst,
-		     uint32_t blockSize);
-
-
-  /**
-   * @ingroup groupInterpolation
-   */
-
-  /**
-   * @defgroup BilinearInterpolate Bilinear Interpolation
-   *
-   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
-   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
-   * determines values between the grid points.
-   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
-   * Bilinear interpolation is often used in image processing to rescale images.
-   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
-   *
-   * <b>Algorithm</b>
-   * \par
-   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
-   * For floating-point, the instance structure is defined as:
-   * <pre>
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * </pre>
-   *
-   * \par
-   * where <code>numRows</code> specifies the number of rows in the table;
-   * <code>numCols</code> specifies the number of columns in the table;
-   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
-   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
-   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
-   *
-   * \par
-   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
-   * <pre>
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * </pre>
-   * \par
-   * The interpolated output point is computed as:
-   * <pre>
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * </pre>
-   * Note that the coordinates (x, y) contain integer and fractional components.  
-   * The integer components specify which portion of the table to use while the
-   * fractional components control the interpolation processor.
-   *
-   * \par
-   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
-   */
-
-  /**
-   * @addtogroup BilinearInterpolate
-   * @{
-   */
-
-  /**
-  *
-  * @brief  Floating-point bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate.
-  * @param[in] Y interpolation coordinate.
-  * @return out interpolated value.
-  */
-
-  
-  static __INLINE float32_t arm_bilinear_interp_f32(
-						    const arm_bilinear_interp_instance_f32 * S,
-						    float32_t X,
-						    float32_t Y)
-  {
-    float32_t out;
-    float32_t f00, f01, f10, f11;
-    float32_t *pData = S->pData;
-    int32_t xIndex, yIndex, index;
-    float32_t xdiff, ydiff;
-    float32_t b1, b2, b3, b4;
-
-    xIndex = (int32_t) X;
-    yIndex = (int32_t) Y;
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0  || yIndex > ( S->numCols-1))
-	{
-		return(0);
-	}
-	
-    /* Calculation of index for two nearest points in X-direction */
-    index = (xIndex - 1) + (yIndex-1) *  S->numCols ;
-
-
-    /* Read two nearest points in X-direction */
-    f00 = pData[index];
-    f01 = pData[index + 1];
-
-    /* Calculation of index for two nearest points in Y-direction */
-    index = (xIndex-1) + (yIndex) * S->numCols;
-
-
-    /* Read two nearest points in Y-direction */
-    f10 = pData[index];
-    f11 = pData[index + 1];
-
-    /* Calculation of intermediate values */
-    b1 = f00;
-    b2 = f01 - f00;
-    b3 = f10 - f00;
-    b4 = f00 - f01 - f10 + f11;
-
-    /* Calculation of fractional part in X */
-    xdiff = X - xIndex;
-
-    /* Calculation of fractional part in Y */
-    ydiff = Y - yIndex;
-
-    /* Calculation of bi-linear interpolated output */
-     out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
-   /* return to application */
-    return (out);
-
-  }
-
-  /**
-  *
-  * @brief  Q31 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q31_t arm_bilinear_interp_q31(
-						arm_bilinear_interp_instance_q31 * S,
-						q31_t X,
-						q31_t Y)
-  {
-    q31_t out;                                   /* Temporary output */
-    q31_t acc = 0;                               /* output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q31_t x1, x2, y1, y2;                        /* Nearest output values */
-    int32_t rI, cI;                             /* Row and column indices */
-    q31_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20u);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20u);
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
-	{
-		return(0);
-	}
-
-    /* 20 bits for the fractional part */
-    /* shift left xfract by 11 to keep 1.31 format */
-    xfract = (X & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-    /* 20 bits for the fractional part */
-    /* shift left yfract by 11 to keep 1.31 format */
-    yfract = (Y & 0x000FFFFF) << 11u;
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
-    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
-    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
-    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
-    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
-    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
-    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
-    /* Convert acc to 1.31(q31) format */
-    return (acc << 2u);
-
-  }
-
-  /**
-  * @brief  Q15 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q15_t arm_bilinear_interp_q15(
-						arm_bilinear_interp_instance_q15 * S,
-						q31_t X,
-						q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q15_t x1, x2, y1, y2;                        /* Nearest output values */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    int32_t rI, cI;                             /* Row and column indices */
-    q15_t *pYData = S->pData;                    /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
-	{
-		return(0);
-	}
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
-    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
-    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
-    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
-    acc = ((q63_t) out * (0xFFFFF - yfract));
-
-    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
-    acc += ((q63_t) out * (xfract));
-
-    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
-    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
-    acc += ((q63_t) out * (yfract));
-
-    /* acc is in 13.51 format and down shift acc by 36 times */
-    /* Convert out to 1.15 format */
-    return (acc >> 36);
-
-  }
-
-  /**
-  * @brief  Q7 bilinear interpolation.
-  * @param[in,out] *S points to an instance of the interpolation structure.
-  * @param[in] X interpolation coordinate in 12.20 format.
-  * @param[in] Y interpolation coordinate in 12.20 format.
-  * @return out interpolated value.
-  */
-
-  static __INLINE q7_t arm_bilinear_interp_q7(
-					      arm_bilinear_interp_instance_q7 * S,
-					      q31_t X,
-					      q31_t Y)
-  {
-    q63_t acc = 0;                               /* output */
-    q31_t out;                                   /* Temporary output */
-    q31_t xfract, yfract;                        /* X, Y fractional parts */
-    q7_t x1, x2, y1, y2;                         /* Nearest output values */
-    int32_t rI, cI;                             /* Row and column indices */
-    q7_t *pYData = S->pData;                     /* pointer to output table values */
-    uint32_t nCols = S->numCols;                 /* num of rows */
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    rI = ((X & 0xFFF00000) >> 20);
-
-    /* Input is in 12.20 format */
-    /* 12 bits for the table index */
-    /* Index value calculation */
-    cI = ((Y & 0xFFF00000) >> 20);
-
-	/* Care taken for table outside boundary */
-	/* Returns zero output when values are outside table boundary */
-	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
-	{
-		return(0);
-	}
-
-    /* 20 bits for the fractional part */
-    /* xfract should be in 12.20 format */
-    xfract = (X & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    x1 = pYData[(rI) + nCols * (cI)];
-    x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
-    /* 20 bits for the fractional part */
-    /* yfract should be in 12.20 format */
-    yfract = (Y & 0x000FFFFF);
-
-    /* Read two nearest output values from the index */
-    y1 = pYData[(rI) + nCols * (cI + 1)];
-    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
-    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
-    out = ((x1 * (0xFFFFF - xfract)));
-    acc = (((q63_t) out * (0xFFFFF - yfract)));
-
-    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
-    out = ((x2 * (0xFFFFF - yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y1 * (0xFFFFF - xfract)));
-    acc += (((q63_t) out * (yfract)));
-
-    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
-    out = ((y2 * (yfract)));
-    acc += (((q63_t) out * (xfract)));
-
-    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
-    return (acc >> 40);
-
-  }
-
-  /**
-   * @} end of BilinearInterpolate group
-   */
-
-
-
-
-
-
-#ifdef	__cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-
-/**
- *
- * End of file.
- */

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm0.h

@@ -1,665 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M0
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-
-  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
-  CMSIS violates following MISRA-C2004 Rules:
-  
-   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'. 
-
-   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-   
-   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code. 
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-    /* add preprocessor checks */
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
-  and not via processor. Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm3.h

@@ -1,1240 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M3
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-
-  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
-  * @ingroup CMSIS_Core
-  CMSIS violates following MISRA-C2004 Rules:
-  
-   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'. 
-
-   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-   
-   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code. 
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  * @ingroup CMSIS_Core
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-    /* add preprocessor checks */
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
-#include "core_cmFunc.h"                 /*!< Core Function Access                            */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  * @ingroup CMSIS_Core
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
-  Type definitions for the Cortex-M System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
-#else
-       uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  * @ingroup CMSIS_Core
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/** \brief  Set Priority Grouping
-
-  This function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
-    \return                Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    This function reads the active register in NVIC and returns the active bit.
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The returned priority value can be used for NVIC_SetPriority(...) function
-
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    This function decodes an interrupt priority value with the given priority group to
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The priority value can be retrieved with NVIC_GetPriority(...) function
-
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief  ITM Send Character
-
-    This function transmits a character via the ITM channel 0.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    This function inputs a character via external variable ITM_RxBuffer.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \return             Received character
-    \return         -1  No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    This function checks external variable ITM_RxBuffer whether a character is available or not.
-    It returns '1' if a character is available and '0' if no character is available.
-
-    \return          0  No character available
-    \return          1  Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4.h

@@ -1,1378 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers.  This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-
-/** \mainpage CMSIS Cortex-M4
-
-  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
-  It consists of:
-
-     - Cortex-M Core Register Definitions
-     - Cortex-M functions
-     - Cortex-M instructions
-     - Cortex-M SIMD instructions
-
-  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
-  access to the Cortex-M Core
- */
-
-/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
-  CMSIS violates following MISRA-C2004 Rules:
-  
-   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'. 
-
-   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-   
-   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code. 
-
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
-  This file defines all structures and symbols for CMSIS core:
-   - CMSIS version number
-   - Cortex-M core
-   - Cortex-M core Revision Number
-  @{
- */
-
-/*  CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
-
-#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-
-#elif defined ( __ICCARM__ )
-  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
-  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-
-#endif
-
-/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if (__FPU_PRESENT == 1)
-      #define __FPU_USED       1
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0
-    #endif
-  #else
-    #define __FPU_USED         0
-  #endif
-
-#elif defined ( __TASKING__ )
-    /* add preprocessor checks to define __FPU_USED */
-    #define __FPU_USED         0
-#endif
-
-#include <stdint.h>                      /*!< standard types definitions                      */
-#include <core_cmInstr.h>                /*!< Core Instruction Access                         */
-#include <core_cmFunc.h>                 /*!< Core Function Access                            */
-#include <core_cm4_simd.h>               /*!< Compiler specific SIMD Intrinsics               */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          4
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< defines 'write only' permissions                */
-#define     __IO    volatile             /*!< defines 'read / write' permissions              */
-
-/*@} end of group CMSIS_core_definitions */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
- ******************************************************************************/
-/** \defgroup CMSIS_core_register CMSIS Core Register
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
-*/
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CORE CMSIS Core
-  Type definitions for the Cortex-M Core Registers
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_NVIC CMSIS NVIC
-  Type definitions for the Cortex-M NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[24];
-  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
-       uint32_t RSERVED1[24];
-  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
-       uint32_t RESERVED2[24];
-  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
-       uint32_t RESERVED3[24];
-  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
-       uint32_t RESERVED4[56];
-  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-       uint32_t RESERVED5[644];
-  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB CMSIS SCB
-  Type definitions for the Cortex-M System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
-  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
-  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
-  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
-  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
-  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
-  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
-  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
-  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
-  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
-  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
-       uint32_t RESERVED0[5];
-  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
-  Type definitions for the Cortex-M System Control and ID Register not in the SCB
-  @{
- */
-
-/** \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
-  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick CMSIS SysTick
-  Type definitions for the Cortex-M System Timer Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_ITM CMSIS ITM
-  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __O  union
-  {
-    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
-    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
-    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
-  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
-       uint32_t RESERVED0[864];
-  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
-       uint32_t RESERVED1[15];
-  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
-       uint32_t RESERVED2[15];
-  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
-#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_MPU CMSIS MPU
-  Type definitions for the Cortex-M Memory Protection Unit (MPU)
-  @{
- */
-
-/** \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
-  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
-  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
-  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
-  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
-  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
-  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
-  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
-  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_FPU CMSIS FPU
-  Type definitions for the Cortex-M Floating Point Unit (FPU)
-  @{
- */
-
-/** \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-       uint32_t RESERVED0[1];
-  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
-  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
-  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
-  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
-  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug CMSIS Core Debug
-  Type definitions for the Cortex-M Core Debug Registers
-  @{
- */
-
-/** \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
-  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
-  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
-  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup  CMSIS_core_register
-  @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
-
-#if (__MPU_PRESENT == 1)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
-#endif
-
-#if (__FPU_PRESENT == 1)
-  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
-  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
-  @{
- */
-
-/** \brief  Set Priority Grouping
-
-  This function sets the priority grouping field using the required unlock sequence.
-  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-  Only values from 0..7 are used.
-  In case of a conflict between priority grouping and available
-  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-
-    \param [in]      PriorityGroup  Priority grouping field
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
-  reg_value  =  (reg_value                                 |
-                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/** \brief  Get Priority Grouping
-
-  This function gets the priority grouping from NVIC Interrupt Controller.
-  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
-
-    \return                Priority grouping field
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
-  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
-}
-
-
-/** \brief  Enable External Interrupt
-
-    This function enables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to enable
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
-  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief  Disable External Interrupt
-
-    This function disables a device specific interrupt in the NVIC interrupt controller.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    This function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for get pending
-    \return             0  Interrupt status is not pending
-    \return             1  Interrupt status is pending
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    This function sets the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for set pending
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    This function clears the pending bit for the specified interrupt.
-    The interrupt number cannot be a negative value.
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Get Active Interrupt
-
-    This function reads the active register in NVIC and returns the active bit.
-    \param [in]      IRQn  Number of the interrupt for get active
-    \return             0  Interrupt status is not active
-    \return             1  Interrupt status is active
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
-  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    This function sets the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    Note: The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Number of the interrupt for set priority
-    \param [in]  priority  Priority to set
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
-  else {
-    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    This function reads the priority for the specified interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-    The returned priority value is automatically aligned to the implemented
-    priority bits of the microcontroller.
-
-    \param [in]   IRQn  Number of the interrupt for get priority
-    \return             Interrupt Priority
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
-  else {
-    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  Encode Priority
-
-    This function encodes the priority for an interrupt with the given priority group,
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The returned priority value can be used for NVIC_SetPriority(...) function
-
-    \param [in]     PriorityGroup  Used priority group
-    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
-    \param [in]       SubPriority  Sub priority value (starting from 0)
-    \return                        Encoded priority for the interrupt
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  return (
-           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
-           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
-         );
-}
-
-
-/** \brief  Decode Priority
-
-    This function decodes an interrupt priority value with the given priority group to
-    preemptive priority value and sub priority value.
-    In case of a conflict between priority grouping and available
-    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
-    The priority value can be retrieved with NVIC_GetPriority(...) function
-
-    \param [in]         Priority   Priority value
-    \param [in]     PriorityGroup  Used priority group
-    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
-    \param [out]     pSubPriority  Sub priority value (starting from 0)
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
-  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
-  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
-}
-
-
-/** \brief  System Reset
-
-    This function initiate a system reset request to reset the MCU.
- */
-static __INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    This function initialises the system tick timer and its interrupt and start the system tick timer.
-    Counter is in free running mode to generate periodical interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
-
-  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
-#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/** \brief  ITM Send Character
-
-    This function transmits a character via the ITM channel 0.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \param [in]     ch  Character to transmit
-    \return             Character to transmit
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
-      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
-      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0].u32 == 0);
-    ITM->PORT[0].u8 = (uint8_t) ch;
-  }
-  return (ch);
-}
-
-
-/** \brief  ITM Receive Character
-
-    This function inputs a character via external variable ITM_RxBuffer.
-    It just returns when no debugger is connected that has booked the output.
-    It is blocking when a debugger is connected, but the previous character send is not transmitted.
-
-    \return             Received character
-    \return         -1  No character received
- */
-static __INLINE int32_t ITM_ReceiveChar (void) {
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/** \brief  ITM Check Character
-
-    This function checks external variable ITM_RxBuffer whether a character is available or not.
-    It returns '1' if a character is available and '0' if no character is available.
-
-    \return          0  No character available
-    \return          1  Character available
- */
-static __INLINE int32_t ITM_CheckChar (void) {
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
-    return (0);                                 /* no character available */
-  } else {
-    return (1);                                 /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cm4_simd.h

@@ -1,701 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm4_simd.h
- * @brief    CMSIS Cortex-M4 SIMD Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
-/* intrinsic __SADD8      see intrinsics.h */
-/* intrinsic __QADD8      see intrinsics.h */
-/* intrinsic __SHADD8     see intrinsics.h */
-/* intrinsic __UADD8      see intrinsics.h */
-/* intrinsic __UQADD8     see intrinsics.h */
-/* intrinsic __UHADD8     see intrinsics.h */
-/* intrinsic __SSUB8      see intrinsics.h */
-/* intrinsic __QSUB8      see intrinsics.h */
-/* intrinsic __SHSUB8     see intrinsics.h */
-/* intrinsic __USUB8      see intrinsics.h */
-/* intrinsic __UQSUB8     see intrinsics.h */
-/* intrinsic __UHSUB8     see intrinsics.h */
-/* intrinsic __SADD16     see intrinsics.h */
-/* intrinsic __QADD16     see intrinsics.h */
-/* intrinsic __SHADD16    see intrinsics.h */
-/* intrinsic __UADD16     see intrinsics.h */
-/* intrinsic __UQADD16    see intrinsics.h */
-/* intrinsic __UHADD16    see intrinsics.h */
-/* intrinsic __SSUB16     see intrinsics.h */
-/* intrinsic __QSUB16     see intrinsics.h */
-/* intrinsic __SHSUB16    see intrinsics.h */
-/* intrinsic __USUB16     see intrinsics.h */
-/* intrinsic __UQSUB16    see intrinsics.h */
-/* intrinsic __UHSUB16    see intrinsics.h */
-/* intrinsic __SASX       see intrinsics.h */
-/* intrinsic __QASX       see intrinsics.h */
-/* intrinsic __SHASX      see intrinsics.h */
-/* intrinsic __UASX       see intrinsics.h */
-/* intrinsic __UQASX      see intrinsics.h */
-/* intrinsic __UHASX      see intrinsics.h */
-/* intrinsic __SSAX       see intrinsics.h */
-/* intrinsic __QSAX       see intrinsics.h */
-/* intrinsic __SHSAX      see intrinsics.h */
-/* intrinsic __USAX       see intrinsics.h */
-/* intrinsic __UQSAX      see intrinsics.h */
-/* intrinsic __UHSAX      see intrinsics.h */
-/* intrinsic __USAD8      see intrinsics.h */
-/* intrinsic __USADA8     see intrinsics.h */
-/* intrinsic __SSAT16     see intrinsics.h */
-/* intrinsic __USAT16     see intrinsics.h */
-/* intrinsic __UXTB16     see intrinsics.h */
-/* intrinsic __SXTB16     see intrinsics.h */
-/* intrinsic __UXTAB16    see intrinsics.h */
-/* intrinsic __SXTAB16    see intrinsics.h */
-/* intrinsic __SMUAD      see intrinsics.h */
-/* intrinsic __SMUADX     see intrinsics.h */
-/* intrinsic __SMLAD      see intrinsics.h */
-/* intrinsic __SMLADX     see intrinsics.h */
-/* intrinsic __SMLALD     see intrinsics.h */
-/* intrinsic __SMLALDX    see intrinsics.h */
-/* intrinsic __SMUSD      see intrinsics.h */
-/* intrinsic __SMUSDX     see intrinsics.h */
-/* intrinsic __SMLSD      see intrinsics.h */
-/* intrinsic __SMLSDX     see intrinsics.h */
-/* intrinsic __SMLSLD     see intrinsics.h */
-/* intrinsic __SMLSLDX    see intrinsics.h */
-/* intrinsic __SEL        see intrinsics.h */
-/* intrinsic __QADD       see intrinsics.h */
-/* intrinsic __QSUB       see intrinsics.h */
-/* intrinsic __PKHBT      see intrinsics.h */
-/* intrinsic __PKHTB      see intrinsics.h */
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-  
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-  
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
-  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
-  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-  
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else	\
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmFunc.h

@@ -1,609 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V2.10
- * @date     26. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface   
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-static __INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-static __INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-static __INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-static __INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
- 
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/** \brief  Get ISPR Register
-
-    This function returns the content of the ISPR Register.
-
-    \return               ISPR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
- 
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
- 
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-  
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */

bsp/nxp/lpc/lpc408x/Libraries/CMSIS/Include/core_cmInstr.h

@@ -1,586 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V2.10
- * @date     19. July 2011
- *
- * @note
- * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M 
- * processor based microcontrollers.  This file can be freely distributed 
- * within development tools that are supporting such ARM based processors. 
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  * @ingroup CMSIS_Core
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor, 
-    so that all instructions following the ISB are fetched from cache or 
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier. 
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before 
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static __INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-static __INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz 
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor, 
-    so that all instructions following the ISB are fetched from cache or 
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier. 
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before 
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
-{
-  uint32_t result;
-  
-  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function performs a exclusive LDR command for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint8_t result;
-  
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function performs a exclusive LDR command for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint16_t result;
-  
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function performs a exclusive LDR command for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-  
-   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function performs a exclusive STR command for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function performs a exclusive STR command for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function performs a exclusive STR command for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-  
-   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint8_t result;
-  
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-  return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC177x_8x.h

@@ -1,1442 +0,0 @@
-/**********************************************************************
-* $Id$		LPC177x_8x.h			2011-06-02
-*//**
-* @file		LPC177x_8x.h
-* @brief	Cortex-M3 Core Peripheral Access Layer Header File for
-*			NXP LPC177x_8x Series.
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __LPC177x_8x_H__
-#define __LPC177x_8x_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC177x_8x Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  Reserved0_IRQn                = 13,       /*!< Reserved                                         */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  MCI_IRQn                      = 29,       /*!< SD/MMC card I/F Interrupt                        */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /*!< USB Activity interrupt                           */
-  CANActivity_IRQn              = 34,       /*!< CAN Activity interrupt                           */
-  UART4_IRQn                    = 35,       /*!< UART4 Interrupt                                  */
-  SSP2_IRQn                     = 36,       /*!< SSP2 Interrupt                                   */
-  LCD_IRQn                      = 37,       /*!< LCD Interrupt                                    */
-  GPIO_IRQn                     = 38,       /*!< GPIO Interrupt                                   */
-  PWM0_IRQn                     = 39,       /*!< PWM0 Interrupt                                   */
-  EEPROM_IRQn                   = 40,       /*!< EEPROM Interrupt                           */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-//#include "system_LPC177x_8x.h"                 /* System Header                                      */
-
-
-/******************************************************************************/
-/*                Device Specific Peripheral registers structures             */
-/******************************************************************************/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;                   /*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                    /*!< Offset: 0x080 (R/W)  PLL0 Control Register */
-  __IO uint32_t PLL0CFG;                    /*!< Offset: 0x084 (R/W)  PLL0 Configuration Register */
-  __I  uint32_t PLL0STAT;                   /*!< Offset: 0x088 (R/ )  PLL0 Status Register */
-  __O  uint32_t PLL0FEED;                   /*!< Offset: 0x08C ( /W)  PLL0 Feed Register */
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;                    /*!< Offset: 0x0A0 (R/W)  PLL1 Control Register */
-  __IO uint32_t PLL1CFG;                    /*!< Offset: 0x0A4 (R/W)  PLL1 Configuration Register */
-  __I  uint32_t PLL1STAT;                   /*!< Offset: 0x0A8 (R/ )  PLL1 Status Register */
-  __O  uint32_t PLL1FEED;                   /*!< Offset: 0x0AC ( /W)  PLL1 Feed Register */
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;                       /*!< Offset: 0x0C0 (R/W)  Power Control Register */
-  __IO uint32_t PCONP;                      /*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
-       uint32_t RESERVED3[14];
-  __IO uint32_t EMCCLKSEL;                  /*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
-  __IO uint32_t CCLKSEL;                    /*!< Offset: 0x104 (R/W)  CPU Clock Selection Register */
-  __IO uint32_t USBCLKSEL;                  /*!< Offset: 0x108 (R/W)  USB Clock Selection Register */
-  __IO uint32_t CLKSRCSEL;                  /*!< Offset: 0x10C (R/W)  Clock Source Select Register */
-  __IO uint32_t	CANSLEEPCLR;                /*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
-  __IO uint32_t	CANWAKEFLAGS;               /*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                     /*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
-       uint32_t RESERVED5[1];
-  __IO uint32_t EXTMODE;                    /*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
-  __IO uint32_t EXTPOLAR;                   /*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                       /*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                        /*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
-  __IO uint32_t IRCTRIM;                    /*!< Offset: 0x1A4 (R/W) Clock Dividers                     */
-  __IO uint32_t PCLKSEL;                    /*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
-       uint32_t RESERVED8;					
-  __IO uint32_t PBOOST;						/*!< Offset: 0x1B0 (R/W)  Power Boost control register */	   
-       uint32_t RESERVED9;					
-  __IO uint32_t LCD_CFG;                    /*!< Offset: 0x1B8 (R/W)  LCD Configuration and clocking control Register */
-       uint32_t RESERVED10[1];
-  __IO uint32_t USBIntSt;                   /*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
-  __IO uint32_t DMAREQSEL;                  /*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
-  __IO uint32_t CLKOUTCFG;                  /*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
-  __IO uint32_t RSTCON0;                    /*!< Offset: 0x1CC (R/W)  RESET Control0 Register */
-  __IO uint32_t RSTCON1;                    /*!< Offset: 0x1D0 (R/W)  RESET Control1 Register */
-       uint32_t RESERVED11[2];
-  __IO uint32_t EMCDLYCTL;                  /*!< Offset: 0x1DC (R/W) SDRAM programmable delays          */
-  __IO uint32_t EMCCAL;                     /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
- } LPC_SC_TypeDef;
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t P0_0;				/* 0x000 */
-  __IO uint32_t P0_1;
-  __IO uint32_t P0_2;
-  __IO uint32_t P0_3;
-  __IO uint32_t P0_4;
-  __IO uint32_t P0_5;
-  __IO uint32_t P0_6;
-  __IO uint32_t P0_7;
-
-  __IO uint32_t P0_8;				/* 0x020 */
-  __IO uint32_t P0_9;
-  __IO uint32_t P0_10;
-  __IO uint32_t P0_11;
-  __IO uint32_t P0_12;
-  __IO uint32_t P0_13;
-  __IO uint32_t P0_14;
-  __IO uint32_t P0_15;
-
-  __IO uint32_t P0_16;				/* 0x040 */
-  __IO uint32_t P0_17;
-  __IO uint32_t P0_18;
-  __IO uint32_t P0_19;
-  __IO uint32_t P0_20;
-  __IO uint32_t P0_21;
-  __IO uint32_t P0_22;
-  __IO uint32_t P0_23;
-
-  __IO uint32_t P0_24;				/* 0x060 */
-  __IO uint32_t P0_25;
-  __IO uint32_t P0_26;
-  __IO uint32_t P0_27;
-  __IO uint32_t P0_28;
-  __IO uint32_t P0_29;
-  __IO uint32_t P0_30;
-  __IO uint32_t P0_31;
-
-  __IO uint32_t P1_0;				/* 0x080 */
-  __IO uint32_t P1_1;
-  __IO uint32_t P1_2;
-  __IO uint32_t P1_3;
-  __IO uint32_t P1_4;
-  __IO uint32_t P1_5;
-  __IO uint32_t P1_6;
-  __IO uint32_t P1_7;
-
-  __IO uint32_t P1_8;				/* 0x0A0 */
-  __IO uint32_t P1_9;
-  __IO uint32_t P1_10;
-  __IO uint32_t P1_11;
-  __IO uint32_t P1_12;
-  __IO uint32_t P1_13;
-  __IO uint32_t P1_14;
-  __IO uint32_t P1_15;
-
-  __IO uint32_t P1_16;				/* 0x0C0 */
-  __IO uint32_t P1_17;
-  __IO uint32_t P1_18;
-  __IO uint32_t P1_19;
-  __IO uint32_t P1_20;
-  __IO uint32_t P1_21;
-  __IO uint32_t P1_22;
-  __IO uint32_t P1_23;
-
-  __IO uint32_t P1_24;				/* 0x0E0 */
-  __IO uint32_t P1_25;
-  __IO uint32_t P1_26;
-  __IO uint32_t P1_27;
-  __IO uint32_t P1_28;
-  __IO uint32_t P1_29;
-  __IO uint32_t P1_30;
-  __IO uint32_t P1_31;
-
-  __IO uint32_t P2_0;				/* 0x100 */
-  __IO uint32_t P2_1;
-  __IO uint32_t P2_2;
-  __IO uint32_t P2_3;
-  __IO uint32_t P2_4;
-  __IO uint32_t P2_5;
-  __IO uint32_t P2_6;
-  __IO uint32_t P2_7;
-
-  __IO uint32_t P2_8;				/* 0x120 */
-  __IO uint32_t P2_9;
-  __IO uint32_t P2_10;
-  __IO uint32_t P2_11;
-  __IO uint32_t P2_12;
-  __IO uint32_t P2_13;
-  __IO uint32_t P2_14;
-  __IO uint32_t P2_15;
-
-  __IO uint32_t P2_16;				/* 0x140 */
-  __IO uint32_t P2_17;
-  __IO uint32_t P2_18;
-  __IO uint32_t P2_19;
-  __IO uint32_t P2_20;
-  __IO uint32_t P2_21;
-  __IO uint32_t P2_22;
-  __IO uint32_t P2_23;
-
-  __IO uint32_t P2_24;				/* 0x160 */
-  __IO uint32_t P2_25;
-  __IO uint32_t P2_26;
-  __IO uint32_t P2_27;
-  __IO uint32_t P2_28;
-  __IO uint32_t P2_29;
-  __IO uint32_t P2_30;
-  __IO uint32_t P2_31;
-
-  __IO uint32_t P3_0;				/* 0x180 */
-  __IO uint32_t P3_1;
-  __IO uint32_t P3_2;
-  __IO uint32_t P3_3;
-  __IO uint32_t P3_4;
-  __IO uint32_t P3_5;
-  __IO uint32_t P3_6;
-  __IO uint32_t P3_7;
-
-  __IO uint32_t P3_8;				/* 0x1A0 */
-  __IO uint32_t P3_9;
-  __IO uint32_t P3_10;
-  __IO uint32_t P3_11;
-  __IO uint32_t P3_12;
-  __IO uint32_t P3_13;
-  __IO uint32_t P3_14;
-  __IO uint32_t P3_15;
-
-  __IO uint32_t P3_16;				/* 0x1C0 */
-  __IO uint32_t P3_17;
-  __IO uint32_t P3_18;
-  __IO uint32_t P3_19;
-  __IO uint32_t P3_20;
-  __IO uint32_t P3_21;
-  __IO uint32_t P3_22;
-  __IO uint32_t P3_23;
-
-  __IO uint32_t P3_24;				/* 0x1E0 */
-  __IO uint32_t P3_25;
-  __IO uint32_t P3_26;
-  __IO uint32_t P3_27;
-  __IO uint32_t P3_28;
-  __IO uint32_t P3_29;
-  __IO uint32_t P3_30;
-  __IO uint32_t P3_31;
-
-  __IO uint32_t P4_0;				/* 0x200 */
-  __IO uint32_t P4_1;
-  __IO uint32_t P4_2;
-  __IO uint32_t P4_3;
-  __IO uint32_t P4_4;
-  __IO uint32_t P4_5;
-  __IO uint32_t P4_6;
-  __IO uint32_t P4_7;
-
-  __IO uint32_t P4_8;				/* 0x220 */
-  __IO uint32_t P4_9;
-  __IO uint32_t P4_10;
-  __IO uint32_t P4_11;
-  __IO uint32_t P4_12;
-  __IO uint32_t P4_13;
-  __IO uint32_t P4_14;
-  __IO uint32_t P4_15;
-
-  __IO uint32_t P4_16;				/* 0x240 */
-  __IO uint32_t P4_17;
-  __IO uint32_t P4_18;
-  __IO uint32_t P4_19;
-  __IO uint32_t P4_20;
-  __IO uint32_t P4_21;
-  __IO uint32_t P4_22;
-  __IO uint32_t P4_23;
-
-  __IO uint32_t P4_24;				/* 0x260 */
-  __IO uint32_t P4_25;
-  __IO uint32_t P4_26;
-  __IO uint32_t P4_27;
-  __IO uint32_t P4_28;
-  __IO uint32_t P4_29;
-  __IO uint32_t P4_30;
-  __IO uint32_t P4_31;
-
-  __IO uint32_t P5_0;				/* 0x280 */
-  __IO uint32_t P5_1;
-  __IO uint32_t P5_2;
-  __IO uint32_t P5_3;
-  __IO uint32_t P5_4;				/* 0x290 */
-} LPC_IOCON_TypeDef;
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  __IO uint32_t DIR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t MASK;
-  __IO uint32_t PIN;
-  __IO uint32_t SET;
-  __O  uint32_t CLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
-} LPC_TIM_TypeDef;
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-  __I  uint32_t CR2;					/*!< Offset: 0x034 Capture Register 2 (R/ ) */
-  __I  uint32_t CR3;					/*!< Offset: 0x038 Capture Register 3 (R/ ) */
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;					/*!< Offset: 0x040 Match Register 4 (R/W) */
-  __IO uint32_t MR5;					/*!< Offset: 0x044 Match Register 5 (R/W) */
-  __IO uint32_t MR6;					/*!< Offset: 0x048 Match Register 6 (R/W) */
-  __IO uint32_t PCR;					/*!< Offset: 0x04C PWM Control Register (R/W) */
-  __IO uint32_t LER;					/*!< Offset: 0x050 Load Enable Register (R/W) */
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;					/*!< Offset: 0x070 Counter Control Register (R/W) */
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
-/* There are three types of UARTs on the chip:
-(1) UART0,UART2, and UART3 are the standard UART.
-(2) UART1 is the standard with modem capability.
-(3) USART(UART4) is the sync/async UART with smart card capability.
-More details can be found on the Users Manual. */
-
-#if 0
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART_TypeDef;
-#else
-typedef struct
-{
-	union
-	{
-		__I  uint8_t  RBR;
-		__O  uint8_t  THR;
-		__IO uint8_t  DLL;
-		uint32_t RESERVED0;
-	};
-	union
-	{
-		__IO uint8_t  DLM;
-		__IO uint32_t IER;
-	};
-	union
-	{
-		__I  uint32_t IIR;
-		__O  uint8_t  FCR;
-	};
-	__IO uint8_t  LCR;
-	uint8_t  RESERVED1[7];//Reserved
-	__I  uint8_t  LSR;
-	uint8_t  RESERVED2[7];//Reserved
-	__IO uint8_t  SCR;
-	uint8_t  RESERVED3[3];//Reserved
-	__IO uint32_t ACR;
-	uint8_t  RESERVED4[4];//Reserved
-	__IO uint8_t  FDR;
-	uint8_t  RESERVED5[7];//Reserved
-	__IO uint8_t  TER;
-	uint8_t  RESERVED8[27];//Reserved
-	__IO uint8_t  RS485CTRL;
-	uint8_t  RESERVED9[3];//Reserved
-	__IO uint8_t  ADRMATCH;
-	uint8_t  RESERVED10[3];//Reserved
-	__IO uint8_t  RS485DLY;
-	uint8_t  RESERVED11[3];//Reserved
-}LPC_UART_TypeDef;
-#endif
-
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-} LPC_UART1_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-  __IO uint32_t  ICR;                   /*!< Offset: 0x024 irDA Control Register (R/W) */
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-  __IO uint32_t  OSR;                   /*!< Offset: 0x02C Over sampling Register (R/W) */
-       uint32_t  RESERVED0[6];               
-  __IO uint32_t  SCI_CTRL;				/*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-  __IO uint32_t  SYNCCTRL;              /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
-  __IO uint32_t  TER;                   /*!< Offset: 0x05C Transmit Enable Register (R/W) */
-} LPC_UART4_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
-  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t DAO;
-  __IO uint32_t DAI;
-  __O  uint32_t TXFIFO;
-  __I  uint32_t RXFIFO;
-  __I  uint32_t STATE;
-  __IO uint32_t DMA1;
-  __IO uint32_t DMA2;
-  __IO uint32_t IRQ;
-  __IO uint32_t TXRATE;
-  __IO uint32_t RXRATE;
-  __IO uint32_t TXBITRATE;
-  __IO uint32_t RXBITRATE;
-  __IO uint32_t TXMODE;
-  __IO uint32_t RXMODE;
-} LPC_I2S_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-  __IO uint32_t ERSTATUS;
-  __IO uint32_t ERCONTROL;
-  __IO uint32_t ERCOUNTERS;
-       uint32_t RESERVED22;
-  __IO uint32_t ERFIRSTSTAMP0;
-  __IO uint32_t ERFIRSTSTAMP1;
-  __IO uint32_t ERFIRSTSTAMP2;
-       uint32_t RESERVED23;
-  __IO uint32_t ERLASTSTAMP0;
-  __IO uint32_t ERLASTSTAMP1;
-  __IO uint32_t ERLASTSTAMP2;
-} LPC_RTC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  MOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t TC;
-  __O  uint8_t  FEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t TV;
-       uint32_t RESERVED2;
-  __IO uint32_t WARNINT;
-  __IO uint32_t WINDOW;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CTRL;
-  __IO uint32_t CNTVAL;
-} LPC_DAC_TypeDef;
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t CON;
-  __O  uint32_t CON_SET;
-  __O  uint32_t CON_CLR;
-  __I  uint32_t CAPCON;
-  __O  uint32_t CAPCON_SET;
-  __O  uint32_t CAPCON_CLR;
-  __IO uint32_t TC0;
-  __IO uint32_t TC1;
-  __IO uint32_t TC2;
-  __IO uint32_t LIM0;
-  __IO uint32_t LIM1;
-  __IO uint32_t LIM2;
-  __IO uint32_t MAT0;
-  __IO uint32_t MAT1;
-  __IO uint32_t MAT2;
-  __IO uint32_t DT;
-  __IO uint32_t CP;
-  __IO uint32_t CAP0;
-  __IO uint32_t CAP1;
-  __IO uint32_t CAP2;
-  __I  uint32_t INTEN;
-  __O  uint32_t INTEN_SET;
-  __O  uint32_t INTEN_CLR;
-  __I  uint32_t CNTCON;
-  __O  uint32_t CNTCON_SET;
-  __O  uint32_t CNTCON_CLR;
-  __I  uint32_t INTF;
-  __O  uint32_t INTF_SET;
-  __O  uint32_t INTF_CLR;
-  __O  uint32_t CAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t CON;
-  __I  uint32_t STAT;
-  __IO uint32_t CONF;
-  __I  uint32_t POS;
-  __IO uint32_t MAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP0;
-  __IO uint32_t LOAD;
-  __I  uint32_t TIME;
-  __I  uint32_t VEL;
-  __I  uint32_t CAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTERPHA;
-  __IO uint32_t FILTERPHB;
-  __IO uint32_t FILTERINX;
-  __IO uint32_t WINDOW;
-  __IO uint32_t INXCMP1;
-  __IO uint32_t INXCMP2;
-       uint32_t RESERVED0[993];
-  __O  uint32_t IEC;
-  __O  uint32_t IES;
-  __I  uint32_t INTSTAT;
-  __I  uint32_t IE;
-  __O  uint32_t CLR;
-  __O  uint32_t SET;
-} LPC_QEI_TypeDef;
-
-/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLOCK;
-  __IO uint32_t ARGUMENT;
-  __IO uint32_t COMMAND;
-  __I  uint32_t RESP_CMD;
-  __I  uint32_t RESP0;
-  __I  uint32_t RESP1;
-  __I  uint32_t RESP2;
-  __I  uint32_t RESP3;
-  __IO uint32_t DATATMR;
-  __IO uint32_t DATALEN;
-  __IO uint32_t DATACTRL;
-  __I  uint32_t DATACNT;
-  __I  uint32_t STATUS;
-  __O  uint32_t CLEAR;
-  __IO uint32_t MASK0;
-       uint32_t RESERVED0[2];
-  __I  uint32_t FIFOCNT;
-       uint32_t RESERVED1[13];
-  __IO uint32_t FIFO[16];
-} LPC_MCI_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-	///Offset: 0x00000000 - Acceptance Filter Register
-	__IO uint32_t AFMR;
-
-	///Offset: 0x00000004 - Standard Frame Individual Start Address Register
-	__IO uint32_t SFF_sa;
-
-	///Offset: 0x00000008 - Standard Frame Group Start Address Register
-	__IO uint32_t SFF_GRP_sa;
-
-	///Offset: 0x0000000C - Extended Frame Start Address Register
-	__IO uint32_t EFF_sa;
-
-	///Offset: 0x00000010 - Extended Frame Group Start Address Register
-	__IO uint32_t EFF_GRP_sa;
-
-	///Offset: 0x00000014 - End of AF Tables register
-	__IO uint32_t ENDofTable;
-
-	///Offset: 0x00000018 - LUT Error Address register
-	__I  uint32_t LUTerrAd;
-
-	///Offset: 0x0000001C - LUT Error Register
-	__I  uint32_t LUTerr;
-
-	///Offset: 0x00000020 - CAN Central Transmit Status Register
-	__IO uint32_t FCANIE;
-
-	///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
-	__IO uint32_t FCANIC0;
-
-	///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
-	__IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t TxSR;
-  __I  uint32_t RxSR;
-  __I  uint32_t MSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-	///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
-	__IO uint32_t MOD;
-
-	///Offset: 0x00000004 - Command bits that affect the state
-	__O  uint32_t CMR;
-
-	///Offset: 0x00000008 - Global Controller Status and Error Counters
-	__IO uint32_t GSR;
-
-	///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
-	__I  uint32_t ICR;
-
-	///Offset: 0x00000010 - Interrupt Enable Register
-	__IO uint32_t IER;
-
-	///Offset: 0x00000014 - Bus Timing Register
-	__IO uint32_t BTR;
-
-	///Offset: 0x00000018 - Error Warning Limit
-	__IO uint32_t EWL;
-
-	///Offset: 0x0000001C - Status Register
-	__I  uint32_t SR;
-
-	///Offset: 0x00000020 - Receive frame status
-	__IO uint32_t RFS;
-
-	///Offset: 0x00000024 - Received Identifier
-	__IO uint32_t RID;
-
-	///Offset: 0x00000028 - Received data bytes 1-4
-	__IO uint32_t RDA;
-
-	///Offset: 0x0000002C - Received data bytes 5-8
-	__IO uint32_t RDB;
-
-	///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
-	__IO uint32_t TFI1;
-
-	///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
-	__IO uint32_t TID1;
-
-	///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
-	__IO uint32_t TDA1;
-
-	///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
-	__IO uint32_t TDB1;
-
-	///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
-	__IO uint32_t TFI2;
-
-	///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
-	__IO uint32_t TID2;
-
-	///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
-	__IO uint32_t TDA2;
-
-	///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
-	__IO uint32_t TDB2;
-
-	///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
-	__IO uint32_t TFI3;
-
-	///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
-	__IO uint32_t TID3;
-
-	///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
-	__IO uint32_t TDA3;
-
-	///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
-	__IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t IntStat;
-  __I  uint32_t IntTCStat;
-  __O  uint32_t IntTCClear;
-  __I  uint32_t IntErrStat;
-  __O  uint32_t IntErrClr;
-  __I  uint32_t RawIntTCStat;
-  __I  uint32_t RawIntErrStat;
-  __I  uint32_t EnbldChns;
-  __IO uint32_t SoftBReq;
-  __IO uint32_t SoftSReq;
-  __IO uint32_t SoftLBReq;
-  __IO uint32_t SoftLSReq;
-  __IO uint32_t Config;
-  __IO uint32_t Sync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t CSrcAddr;
-  __IO uint32_t CDestAddr;
-  __IO uint32_t CLLI;
-  __IO uint32_t CControl;
-  __IO uint32_t CConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t Revision;             /* USB Host Registers                 */
-  __IO uint32_t Control;
-  __IO uint32_t CommandStatus;
-  __IO uint32_t InterruptStatus;
-  __IO uint32_t InterruptEnable;
-  __IO uint32_t InterruptDisable;
-  __IO uint32_t HCCA;
-  __I  uint32_t PeriodCurrentED;
-  __IO uint32_t ControlHeadED;
-  __IO uint32_t ControlCurrentED;
-  __IO uint32_t BulkHeadED;
-  __IO uint32_t BulkCurrentED;
-  __I  uint32_t DoneHead;
-  __IO uint32_t FmInterval;
-  __I  uint32_t FmRemaining;
-  __I  uint32_t FmNumber;
-  __IO uint32_t PeriodicStart;
-  __IO uint32_t LSTreshold;
-  __IO uint32_t RhDescriptorA;
-  __IO uint32_t RhDescriptorB;
-  __IO uint32_t RhStatus;
-  __IO uint32_t RhPortStatus1;
-  __IO uint32_t RhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t IntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t IntEn;
-  __O  uint32_t IntSet;
-  __O  uint32_t IntClr;
-  __IO uint32_t StCtrl;
-  __IO uint32_t Tmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t DevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t DevIntEn;
-  __O  uint32_t DevIntClr;
-  __O  uint32_t DevIntSet;
-
-  __O  uint32_t CmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t CmdData;
-
-  __I  uint32_t RxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t TxData;
-  __I  uint32_t RxPLen;
-  __O  uint32_t TxPLen;
-  __IO uint32_t Ctrl;
-  __O  uint32_t DevIntPri;
-
-  __I  uint32_t EpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t EpIntEn;
-  __O  uint32_t EpIntClr;
-  __O  uint32_t EpIntSet;
-  __O  uint32_t EpIntPri;
-
-  __IO uint32_t ReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t EpInd;
-  __IO uint32_t MaxPSize;
-
-  __I  uint32_t DMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t DMARClr;
-  __O  uint32_t DMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t UDCAH;
-  __I  uint32_t EpDMASt;
-  __O  uint32_t EpDMAEn;
-  __O  uint32_t EpDMADis;
-  __I  uint32_t DMAIntSt;
-  __IO uint32_t DMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t EoTIntSt;
-  __O  uint32_t EoTIntClr;
-  __O  uint32_t EoTIntSet;
-  __I  uint32_t NDDRIntSt;
-  __O  uint32_t NDDRIntClr;
-  __O  uint32_t NDDRIntSet;
-  __I  uint32_t SysErrIntSt;
-  __O  uint32_t SysErrIntClr;
-  __O  uint32_t SysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  union {
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_TX;
-  };
-  __IO  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[824];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __I  uint32_t RxFilterWoLStatus;
-  __O  uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-/*------------- LCD controller (LCD) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t TIMH;                   /* LCD Registers                      */
-  __IO uint32_t TIMV;
-  __IO uint32_t POL;
-  __IO uint32_t LE;
-  __IO uint32_t UPBASE;
-  __IO uint32_t LPBASE;
-  __IO uint32_t CTRL;
-  __IO uint32_t INTMSK;
-  __I  uint32_t INTRAW;
-  __I  uint32_t INTSTAT;
-  __O  uint32_t INTCLR;
-  __I  uint32_t UPCURR;
-  __I  uint32_t LPCURR;
-       uint32_t RESERVED0[115];
-  __IO uint32_t PAL[128];
-       uint32_t RESERVED1[256];
-  __IO uint32_t CRSR_IMG[256];
-  __IO uint32_t CRSR_CTRL;
-  __IO uint32_t CRSR_CFG;
-  __IO uint32_t CRSR_PAL0;
-  __IO uint32_t CRSR_PAL1;
-  __IO uint32_t CRSR_XY;
-  __IO uint32_t CRSR_CLIP;
-       uint32_t RESERVED2[2];
-  __IO uint32_t CRSR_INTMSK;
-  __O  uint32_t CRSR_INTCLR;
-  __I  uint32_t CRSR_INTRAW;
-  __I  uint32_t CRSR_INTSTAT;
-} LPC_LCD_TypeDef;
-
-/*------------- External Memory Controller (EMC) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t Control;
-  __I  uint32_t Status;
-  __IO uint32_t Config;
-       uint32_t RESERVED0[5];
-  __IO uint32_t DynamicControl;
-  __IO uint32_t DynamicRefresh;
-  __IO uint32_t DynamicReadConfig;
-       uint32_t RESERVED1[1];
-  __IO uint32_t DynamicRP;
-  __IO uint32_t DynamicRAS;
-  __IO uint32_t DynamicSREX;
-  __IO uint32_t DynamicAPR;
-  __IO uint32_t DynamicDAL;
-  __IO uint32_t DynamicWR;
-  __IO uint32_t DynamicRC;
-  __IO uint32_t DynamicRFC;
-  __IO uint32_t DynamicXSR;
-  __IO uint32_t DynamicRRD;
-  __IO uint32_t DynamicMRD;
-       uint32_t RESERVED2[9];
-  __IO uint32_t StaticExtendedWait;
-       uint32_t RESERVED3[31];
-  __IO uint32_t DynamicConfig0;
-  __IO uint32_t DynamicRasCas0;
-       uint32_t RESERVED4[6];
-  __IO uint32_t DynamicConfig1;
-  __IO uint32_t DynamicRasCas1;
-       uint32_t RESERVED5[6];
-  __IO uint32_t DynamicConfig2;
-  __IO uint32_t DynamicRasCas2;
-       uint32_t RESERVED6[6];
-  __IO uint32_t DynamicConfig3;
-  __IO uint32_t DynamicRasCas3;
-       uint32_t RESERVED7[38];
-  __IO uint32_t StaticConfig0;
-  __IO uint32_t StaticWaitWen0;
-  __IO uint32_t StaticWaitOen0;
-  __IO uint32_t StaticWaitRd0;
-  __IO uint32_t StaticWaitPage0;
-  __IO uint32_t StaticWaitWr0;
-  __IO uint32_t StaticWaitTurn0;
-       uint32_t RESERVED8[1];
-  __IO uint32_t StaticConfig1;
-  __IO uint32_t StaticWaitWen1;
-  __IO uint32_t StaticWaitOen1;
-  __IO uint32_t StaticWaitRd1;
-  __IO uint32_t StaticWaitPage1;
-  __IO uint32_t StaticWaitWr1;
-  __IO uint32_t StaticWaitTurn1;
-       uint32_t RESERVED9[1];
-  __IO uint32_t StaticConfig2;
-  __IO uint32_t StaticWaitWen2;
-  __IO uint32_t StaticWaitOen2;
-  __IO uint32_t StaticWaitRd2;
-  __IO uint32_t StaticWaitPage2;
-  __IO uint32_t StaticWaitWr2;
-  __IO uint32_t StaticWaitTurn2;
-       uint32_t RESERVED10[1];
-  __IO uint32_t StaticConfig3;
-  __IO uint32_t StaticWaitWen3;
-  __IO uint32_t StaticWaitOen3;
-  __IO uint32_t StaticWaitRd3;
-  __IO uint32_t StaticWaitPage3;
-  __IO uint32_t StaticWaitWr3;
-  __IO uint32_t StaticWaitTurn3;
-} LPC_EMC_TypeDef;
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t MODE;
-  __IO uint32_t SEED;
-  union {
-  __I  uint32_t SUM;
-  struct {
-  __O  uint32_t DATA;
-  } WR_DATA_DWORD;
-  
-  struct {
-  __O  uint16_t DATA;
-       uint16_t RESERVED;
-  }WR_DATA_WORD;
-  
-  struct {
-  __O  uint8_t  DATA;
-       uint8_t  RESERVED[3];
-  	}WR_DATA_BYTE;
-  };
-} LPC_CRC_TypeDef;
-
-/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t CMD;			/* 0x0080 */
-  __IO uint32_t ADDR;
-  __IO uint32_t WDATA;
-  __IO uint32_t RDATA;
-  __IO uint32_t WSTATE;			/* 0x0090 */
-  __IO uint32_t CLKDIV;
-  __IO uint32_t PWRDWN;			/* 0x0098 */
-       uint32_t RESERVED0[975];
-  __IO uint32_t INT_CLR_ENABLE;	/* 0x0FD8 */
-  __IO uint32_t INT_SET_ENABLE;
-  __IO uint32_t INT_STATUS;		/* 0x0FE0 */
-  __IO uint32_t INT_ENABLE;
-  __IO uint32_t INT_CLR_STATUS;
-  __IO uint32_t INT_SET_STATUS;
-} LPC_EEPROM_TypeDef;
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_PERI_RAM_BASE     (0x20000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHBRAM1_BASE      (0x20004000UL)
-#define LPC_AHB_BASE          (0x20080000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM0_BASE         (LPC_APB0_BASE + 0x14000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_UART4_BASE        (LPC_APB1_BASE + 0x24000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_SSP2_BASE         (LPC_APB1_BASE + 0x2C000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_MCI_BASE          (LPC_APB1_BASE + 0x40000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x00100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x00120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x00140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x00160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x00180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x001A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x001C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x001E0)
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x04000)
-#define LPC_LCD_BASE          (LPC_AHB_BASE  + 0x08000)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-#define LPC_CRC_BASE          (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x18000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x18020)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x18040)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x18060)
-#define LPC_GPIO4_BASE        (LPC_AHB_BASE  + 0x18080)
-#define LPC_GPIO5_BASE        (LPC_AHB_BASE  + 0x180A0)
-#define LPC_EMC_BASE          (LPC_AHB_BASE  + 0x1C000)
-
-#define LPC_EEPROM_BASE       (LPC_FLASH_BASE+ 0x200080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_UART4             ((LPC_UART4_TypeDef     *) LPC_UART4_BASE    )
-#define LPC_PWM0              ((LPC_PWM_TypeDef       *) LPC_PWM0_BASE     )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef     *) LPC_IOCON_BASE    )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_SSP2              ((LPC_SSP_TypeDef       *) LPC_SSP2_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_MCI               ((LPC_MCI_TypeDef       *) LPC_MCI_BASE      )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_LCD               ((LPC_LCD_TypeDef       *) LPC_LCD_BASE      )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_GPIO5             ((LPC_GPIO_TypeDef      *) LPC_GPIO5_BASE    )
-#define LPC_EMC               ((LPC_EMC_TypeDef       *) LPC_EMC_BASE      )
-#define LPC_CRC               ((LPC_CRC_TypeDef       *) LPC_CRC_BASE      )
-#define LPC_EEPROM            ((LPC_EEPROM_TypeDef    *) LPC_EEPROM_BASE   )
-
-#endif  // __LPC177x_8x_H__

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/LPC407x_8x_177x_8x.h

@@ -1,1514 +0,0 @@
-/****************************************************************************************************//**
-* $Id$		LPC407x_8x_177x_8x.h			2012-04-25
-*//**
- * @file     LPC407x_8x_177x_8x.h
- *
- * @brief    CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
- *           NXP LPC407x_8x_177x_8x.
- * @version  V0.7
- * @date     20. June 2012
- * @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2012, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __LPC407x_8x_177x_8x_H__
-#define __LPC407x_8x_177x_8x_H__
-
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum IRQn
-{
-/******  Cortex-M4 Processor Exceptions Numbers ***************************************************/
-  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
-  NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
-  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
-  MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
-  BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
-  UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
-  SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
-  DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
-  PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
-  SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
-
-/******  LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
-  WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
-  TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
-  TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
-  TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
-  TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
-  UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
-  UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
-  UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
-  UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
-  PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
-  I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
-  I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
-  I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
-  Reserved0_IRQn                = 13,       /*!< Reserved                                         */
-  SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
-  SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
-  PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
-  RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
-  EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
-  EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
-  EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
-  EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
-  ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
-  BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
-  USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
-  CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
-  DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
-  I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
-  ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
-  MCI_IRQn                      = 29,       /*!< SD/MMC card I/F Interrupt                        */
-  MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
-  QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
-  PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
-  USBActivity_IRQn              = 33,       /*!< USB Activity interrupt                           */
-  CANActivity_IRQn              = 34,       /*!< CAN Activity interrupt                           */
-  UART4_IRQn                    = 35,       /*!< UART4 Interrupt                                  */
-  SSP2_IRQn                     = 36,       /*!< SSP2 Interrupt                                   */
-  LCD_IRQn                      = 37,       /*!< LCD Interrupt                                    */
-  GPIO_IRQn                     = 38,       /*!< GPIO Interrupt                                   */
-  PWM0_IRQn                     =  39,              /*!<  39  PWM0                                                             */
-  EEPROM_IRQn                   =  40,              /*!<  40  EEPROM                                                           */
-  CMP0_IRQn                     =  41,              /*!<  41  CMP0                                                             */
-  CMP1_IRQn                     =  42               /*!<  42  CMP1                                                             */
-} IRQn_Type;
-
-/* ================================================================================ */
-/* ================      Processor and Core Peripheral Section     ================ */
-/* ================================================================================ */
-#ifdef CORE_M4
-/* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
-#define __CM4_REV                 0x0000            /*!< Cortex-M4 Core Revision                                               */
-#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
-#define __NVIC_PRIO_BITS               5            /*!< Number of Bits used for Priority Levels                               */
-#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
-#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
-
-
-#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
-#else
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-
-#include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
-
-#endif
-
-#include "system_LPC407x_8x_177x_8x.h"                      /*!< LPC408x_7x System                                                     */
-
-
-
-
-/* ================================================================================ */
-/* ================       Device Specific Peripheral Section       ================ */
-/* ================================================================================ */
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#elif defined ( __ICCARM__ )
-#pragma language=save
-#pragma language=extended
-#endif
-
-/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
-typedef struct                          /* Common Registers                   */
-{
-  __I  uint32_t IntStat;
-  __I  uint32_t IntTCStat;
-  __O  uint32_t IntTCClear;
-  __I  uint32_t IntErrStat;
-  __O  uint32_t IntErrClr;
-  __I  uint32_t RawIntTCStat;
-  __I  uint32_t RawIntErrStat;
-  __I  uint32_t EnbldChns;
-  __IO uint32_t SoftBReq;
-  __IO uint32_t SoftSReq;
-  __IO uint32_t SoftLBReq;
-  __IO uint32_t SoftLSReq;
-  __IO uint32_t Config;
-  __IO uint32_t Sync;
-} LPC_GPDMA_TypeDef;
-
-typedef struct                          /* Channel Registers                  */
-{
-  __IO uint32_t CSrcAddr;
-  __IO uint32_t CDestAddr;
-  __IO uint32_t CLLI;
-  __IO uint32_t CControl;
-  __IO uint32_t CConfig;
-} LPC_GPDMACH_TypeDef;
-
-/*------------- System Control (SC) ------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t FLASHCFG;                   /*!< Offset: 0x000 (R/W)  Flash Accelerator Configuration Register */
-       uint32_t RESERVED0[31];
-  __IO uint32_t PLL0CON;                    /*!< Offset: 0x080 (R/W)  PLL0 Control Register */
-  __IO uint32_t PLL0CFG;                    /*!< Offset: 0x084 (R/W)  PLL0 Configuration Register */
-  __I  uint32_t PLL0STAT;                   /*!< Offset: 0x088 (R/ )  PLL0 Status Register */
-  __O  uint32_t PLL0FEED;                   /*!< Offset: 0x08C ( /W)  PLL0 Feed Register */
-       uint32_t RESERVED1[4];
-  __IO uint32_t PLL1CON;                    /*!< Offset: 0x0A0 (R/W)  PLL1 Control Register */
-  __IO uint32_t PLL1CFG;                    /*!< Offset: 0x0A4 (R/W)  PLL1 Configuration Register */
-  __I  uint32_t PLL1STAT;                   /*!< Offset: 0x0A8 (R/ )  PLL1 Status Register */
-  __O  uint32_t PLL1FEED;                   /*!< Offset: 0x0AC ( /W)  PLL1 Feed Register */
-       uint32_t RESERVED2[4];
-  __IO uint32_t PCON;                       /*!< Offset: 0x0C0 (R/W)  Power Control Register */
-  __IO uint32_t PCONP;                      /*!< Offset: 0x0C4 (R/W)  Power Control for Peripherals Register */
-  __IO uint32_t PCONP1;                      /*!< Offset: 0x0C8 (R/W)  Power Control for Peripherals Register */
-       uint32_t RESERVED3[13];
-  __IO uint32_t EMCCLKSEL;                  /*!< Offset: 0x100 (R/W)  External Memory Controller Clock Selection Register */
-  __IO uint32_t CCLKSEL;                    /*!< Offset: 0x104 (R/W)  CPU Clock Selection Register */
-  __IO uint32_t USBCLKSEL;                  /*!< Offset: 0x108 (R/W)  USB Clock Selection Register */
-  __IO uint32_t CLKSRCSEL;                  /*!< Offset: 0x10C (R/W)  Clock Source Select Register */
-  __IO uint32_t	CANSLEEPCLR;                /*!< Offset: 0x110 (R/W)  CAN Sleep Clear Register */
-  __IO uint32_t	CANWAKEFLAGS;               /*!< Offset: 0x114 (R/W)  CAN Wake-up Flags Register */
-       uint32_t RESERVED4[10];
-  __IO uint32_t EXTINT;                     /*!< Offset: 0x140 (R/W)  External Interrupt Flag Register */
-       uint32_t RESERVED5[1];
-  __IO uint32_t EXTMODE;                    /*!< Offset: 0x148 (R/W)  External Interrupt Mode Register */
-  __IO uint32_t EXTPOLAR;                   /*!< Offset: 0x14C (R/W)  External Interrupt Polarity Register */
-       uint32_t RESERVED6[12];
-  __IO uint32_t RSID;                       /*!< Offset: 0x180 (R/W)  Reset Source Identification Register */
-       uint32_t RESERVED7[7];
-  __IO uint32_t SCS;                        /*!< Offset: 0x1A0 (R/W)  System Controls and Status Register */
-  __IO uint32_t IRCTRIM;                    /*!< Offset: 0x1A4 (R/W) Clock Dividers                     */
-  __IO uint32_t PCLKSEL;                    /*!< Offset: 0x1A8 (R/W)  Peripheral Clock Selection Register */
-       uint32_t RESERVED8;					
-  __IO uint32_t PBOOST;						/*!< Offset: 0x1B0 (R/W)  Power Boost control register */	   
-  __IO uint32_t SPIFICLKSEL;					
-  __IO uint32_t LCD_CFG;                    /*!< Offset: 0x1B8 (R/W)  LCD Configuration and clocking control Register */
-       uint32_t RESERVED10[1];
-  __IO uint32_t USBIntSt;                   /*!< Offset: 0x1C0 (R/W)  USB Interrupt Status Register */
-  __IO uint32_t DMAREQSEL;                  /*!< Offset: 0x1C4 (R/W)  DMA Request Select Register */
-  __IO uint32_t CLKOUTCFG;                  /*!< Offset: 0x1C8 (R/W)  Clock Output Configuration Register */
-  __IO uint32_t RSTCON0;                    /*!< Offset: 0x1CC (R/W)  RESET Control0 Register */
-  __IO uint32_t RSTCON1;                    /*!< Offset: 0x1D0 (R/W)  RESET Control1 Register */
-       uint32_t RESERVED11[2];
-  __IO uint32_t EMCDLYCTL;                  /*!< Offset: 0x1DC (R/W) SDRAM programmable delays          */
-  __IO uint32_t EMCCAL;                     /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
- } LPC_SC_TypeDef;
-/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
-typedef struct
-{
-  __IO uint32_t MAC1;                   /* MAC Registers                      */
-  __IO uint32_t MAC2;
-  __IO uint32_t IPGT;
-  __IO uint32_t IPGR;
-  __IO uint32_t CLRT;
-  __IO uint32_t MAXF;
-  __IO uint32_t SUPP;
-  __IO uint32_t TEST;
-  __IO uint32_t MCFG;
-  __IO uint32_t MCMD;
-  __IO uint32_t MADR;
-  __O  uint32_t MWTD;
-  __I  uint32_t MRDD;
-  __I  uint32_t MIND;
-       uint32_t RESERVED0[2];
-  __IO uint32_t SA0;
-  __IO uint32_t SA1;
-  __IO uint32_t SA2;
-       uint32_t RESERVED1[45];
-  __IO uint32_t Command;                /* Control Registers                  */
-  __I  uint32_t Status;
-  __IO uint32_t RxDescriptor;
-  __IO uint32_t RxStatus;
-  __IO uint32_t RxDescriptorNumber;
-  __I  uint32_t RxProduceIndex;
-  __IO uint32_t RxConsumeIndex;
-  __IO uint32_t TxDescriptor;
-  __IO uint32_t TxStatus;
-  __IO uint32_t TxDescriptorNumber;
-  __IO uint32_t TxProduceIndex;
-  __I  uint32_t TxConsumeIndex;
-       uint32_t RESERVED2[10];
-  __I  uint32_t TSV0;
-  __I  uint32_t TSV1;
-  __I  uint32_t RSV;
-       uint32_t RESERVED3[3];
-  __IO uint32_t FlowControlCounter;
-  __I  uint32_t FlowControlStatus;
-       uint32_t RESERVED4[34];
-  __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
-  __I  uint32_t RxFilterWoLStatus;
-  __O  uint32_t RxFilterWoLClear;
-       uint32_t RESERVED5;
-  __IO uint32_t HashFilterL;
-  __IO uint32_t HashFilterH;
-       uint32_t RESERVED6[882];
-  __I  uint32_t IntStatus;              /* Module Control Registers           */
-  __IO uint32_t IntEnable;
-  __O  uint32_t IntClear;
-  __O  uint32_t IntSet;
-       uint32_t RESERVED7;
-  __IO uint32_t PowerDown;
-       uint32_t RESERVED8;
-  __IO uint32_t Module_ID;
-} LPC_EMAC_TypeDef;
-
-/*------------- LCD controller (LCD) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t TIMH;                   /* LCD Registers                      */
-  __IO uint32_t TIMV;
-  __IO uint32_t POL;
-  __IO uint32_t LE;
-  __IO uint32_t UPBASE;
-  __IO uint32_t LPBASE;
-  __IO uint32_t CTRL;
-  __IO uint32_t INTMSK;
-  __I  uint32_t INTRAW;
-  __I  uint32_t INTSTAT;
-  __O  uint32_t INTCLR;
-  __I  uint32_t UPCURR;
-  __I  uint32_t LPCURR;
-       uint32_t RESERVED0[115];
-  __IO uint32_t PAL[128];
-       uint32_t RESERVED1[256];
-  __IO uint32_t CRSR_IMG[256];
-  __IO uint32_t CRSR_CTRL;
-  __IO uint32_t CRSR_CFG;
-  __IO uint32_t CRSR_PAL0;
-  __IO uint32_t CRSR_PAL1;
-  __IO uint32_t CRSR_XY;
-  __IO uint32_t CRSR_CLIP;
-       uint32_t RESERVED2[2];
-  __IO uint32_t CRSR_INTMSK;
-  __O  uint32_t CRSR_INTCLR;
-  __I  uint32_t CRSR_INTRAW;
-  __I  uint32_t CRSR_INTSTAT;
-} LPC_LCD_TypeDef;
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
-  __I  uint32_t Revision;             /* USB Host Registers                 */
-  __IO uint32_t Control;
-  __IO uint32_t CommandStatus;
-  __IO uint32_t InterruptStatus;
-  __IO uint32_t InterruptEnable;
-  __IO uint32_t InterruptDisable;
-  __IO uint32_t HCCA;
-  __I  uint32_t PeriodCurrentED;
-  __IO uint32_t ControlHeadED;
-  __IO uint32_t ControlCurrentED;
-  __IO uint32_t BulkHeadED;
-  __IO uint32_t BulkCurrentED;
-  __I  uint32_t DoneHead;
-  __IO uint32_t FmInterval;
-  __I  uint32_t FmRemaining;
-  __I  uint32_t FmNumber;
-  __IO uint32_t PeriodicStart;
-  __IO uint32_t LSTreshold;
-  __IO uint32_t RhDescriptorA;
-  __IO uint32_t RhDescriptorB;
-  __IO uint32_t RhStatus;
-  __IO uint32_t RhPortStatus1;
-  __IO uint32_t RhPortStatus2;
-       uint32_t RESERVED0[40];
-  __I  uint32_t Module_ID;
-
-  __I  uint32_t IntSt;               /* USB On-The-Go Registers            */
-  __IO uint32_t IntEn;
-  __O  uint32_t IntSet;
-  __O  uint32_t IntClr;
-  __IO uint32_t StCtrl;
-  __IO uint32_t Tmr;
-       uint32_t RESERVED1[58];
-
-  __I  uint32_t DevIntSt;            /* USB Device Interrupt Registers     */
-  __IO uint32_t DevIntEn;
-  __O  uint32_t DevIntClr;
-  __O  uint32_t DevIntSet;
-
-  __O  uint32_t CmdCode;             /* USB Device SIE Command Registers   */
-  __I  uint32_t CmdData;
-
-  __I  uint32_t RxData;              /* USB Device Transfer Registers      */
-  __O  uint32_t TxData;
-  __I  uint32_t RxPLen;
-  __O  uint32_t TxPLen;
-  __IO uint32_t Ctrl;
-  __O  uint32_t DevIntPri;
-
-  __I  uint32_t EpIntSt;             /* USB Device Endpoint Interrupt Regs */
-  __IO uint32_t EpIntEn;
-  __O  uint32_t EpIntClr;
-  __O  uint32_t EpIntSet;
-  __O  uint32_t EpIntPri;
-
-  __IO uint32_t ReEp;                /* USB Device Endpoint Realization Reg*/
-  __O  uint32_t EpInd;
-  __IO uint32_t MaxPSize;
-
-  __I  uint32_t DMARSt;              /* USB Device DMA Registers           */
-  __O  uint32_t DMARClr;
-  __O  uint32_t DMARSet;
-       uint32_t RESERVED2[9];
-  __IO uint32_t UDCAH;
-  __I  uint32_t EpDMASt;
-  __O  uint32_t EpDMAEn;
-  __O  uint32_t EpDMADis;
-  __I  uint32_t DMAIntSt;
-  __IO uint32_t DMAIntEn;
-       uint32_t RESERVED3[2];
-  __I  uint32_t EoTIntSt;
-  __O  uint32_t EoTIntClr;
-  __O  uint32_t EoTIntSet;
-  __I  uint32_t NDDRIntSt;
-  __O  uint32_t NDDRIntClr;
-  __O  uint32_t NDDRIntSet;
-  __I  uint32_t SysErrIntSt;
-  __O  uint32_t SysErrIntClr;
-  __O  uint32_t SysErrIntSet;
-       uint32_t RESERVED4[15];
-
-  union {
-  __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
-  __O  uint32_t I2C_TX;
-  };
-  __IO  uint32_t I2C_STS;
-  __IO uint32_t I2C_CTL;
-  __IO uint32_t I2C_CLKHI;
-  __O  uint32_t I2C_CLKLO;
-       uint32_t RESERVED5[824];
-
-  union {
-  __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
-  __IO uint32_t OTGClkCtrl;
-  };
-  union {
-  __I  uint32_t USBClkSt;
-  __I  uint32_t OTGClkSt;
-  };
-} LPC_USB_TypeDef;
-
-/*------------- CRC Engine (CRC) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t MODE;
-  __IO uint32_t SEED;
-  union {
-  __I  uint32_t SUM;
-  struct {
-  __O  uint32_t DATA;
-  } WR_DATA_DWORD;
-  
-  struct {
-  __O  uint16_t DATA;
-       uint16_t RESERVED;
-  }WR_DATA_WORD;
-  
-  struct {
-  __O  uint8_t  DATA;
-       uint8_t  RESERVED[3];
-  	}WR_DATA_BYTE;
-  };
-} LPC_CRC_TypeDef;
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
-  __IO uint32_t DIR;
-       uint32_t RESERVED0[3];
-  __IO uint32_t MASK;
-  __IO uint32_t PIN;
-  __IO uint32_t SET;
-  __O  uint32_t CLR;
-} LPC_GPIO_TypeDef;
-
-typedef struct
-{
-  __I  uint32_t IntStatus;
-  __I  uint32_t IO0IntStatR;
-  __I  uint32_t IO0IntStatF;
-  __O  uint32_t IO0IntClr;
-  __IO uint32_t IO0IntEnR;
-  __IO uint32_t IO0IntEnF;
-       uint32_t RESERVED0[3];
-  __I  uint32_t IO2IntStatR;
-  __I  uint32_t IO2IntStatF;
-  __O  uint32_t IO2IntClr;
-  __IO uint32_t IO2IntEnR;
-  __IO uint32_t IO2IntEnF;
-} LPC_GPIOINT_TypeDef;
-
-/*------------- External Memory Controller (EMC) -----------------------------*/
-typedef struct
-{
-  __IO uint32_t Control;
-  __I  uint32_t Status;
-  __IO uint32_t Config;
-       uint32_t RESERVED0[5];
-  __IO uint32_t DynamicControl;
-  __IO uint32_t DynamicRefresh;
-  __IO uint32_t DynamicReadConfig;
-       uint32_t RESERVED1[1];
-  __IO uint32_t DynamicRP;
-  __IO uint32_t DynamicRAS;
-  __IO uint32_t DynamicSREX;
-  __IO uint32_t DynamicAPR;
-  __IO uint32_t DynamicDAL;
-  __IO uint32_t DynamicWR;
-  __IO uint32_t DynamicRC;
-  __IO uint32_t DynamicRFC;
-  __IO uint32_t DynamicXSR;
-  __IO uint32_t DynamicRRD;
-  __IO uint32_t DynamicMRD;
-       uint32_t RESERVED2[9];
-  __IO uint32_t StaticExtendedWait;
-       uint32_t RESERVED3[31];
-  __IO uint32_t DynamicConfig0;
-  __IO uint32_t DynamicRasCas0;
-       uint32_t RESERVED4[6];
-  __IO uint32_t DynamicConfig1;
-  __IO uint32_t DynamicRasCas1;
-       uint32_t RESERVED5[6];
-  __IO uint32_t DynamicConfig2;
-  __IO uint32_t DynamicRasCas2;
-       uint32_t RESERVED6[6];
-  __IO uint32_t DynamicConfig3;
-  __IO uint32_t DynamicRasCas3;
-       uint32_t RESERVED7[38];
-  __IO uint32_t StaticConfig0;
-  __IO uint32_t StaticWaitWen0;
-  __IO uint32_t StaticWaitOen0;
-  __IO uint32_t StaticWaitRd0;
-  __IO uint32_t StaticWaitPage0;
-  __IO uint32_t StaticWaitWr0;
-  __IO uint32_t StaticWaitTurn0;
-       uint32_t RESERVED8[1];
-  __IO uint32_t StaticConfig1;
-  __IO uint32_t StaticWaitWen1;
-  __IO uint32_t StaticWaitOen1;
-  __IO uint32_t StaticWaitRd1;
-  __IO uint32_t StaticWaitPage1;
-  __IO uint32_t StaticWaitWr1;
-  __IO uint32_t StaticWaitTurn1;
-       uint32_t RESERVED9[1];
-  __IO uint32_t StaticConfig2;
-  __IO uint32_t StaticWaitWen2;
-  __IO uint32_t StaticWaitOen2;
-  __IO uint32_t StaticWaitRd2;
-  __IO uint32_t StaticWaitPage2;
-  __IO uint32_t StaticWaitWr2;
-  __IO uint32_t StaticWaitTurn2;
-       uint32_t RESERVED10[1];
-  __IO uint32_t StaticConfig3;
-  __IO uint32_t StaticWaitWen3;
-  __IO uint32_t StaticWaitOen3;
-  __IO uint32_t StaticWaitRd3;
-  __IO uint32_t StaticWaitPage3;
-  __IO uint32_t StaticWaitWr3;
-  __IO uint32_t StaticWaitTurn3;
-} LPC_EMC_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  MOD;
-       uint8_t  RESERVED0[3];
-  __IO uint32_t TC;
-  __O  uint8_t  FEED;
-       uint8_t  RESERVED1[3];
-  __I  uint32_t TV;
-       uint32_t RESERVED2;
-  __IO uint32_t WARNINT;
-  __IO uint32_t WINDOW;
-} LPC_WDT_TypeDef;
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-       uint32_t RESERVED0[2];
-  __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
-       uint32_t RESERVED1[12];
-  __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
-} LPC_TIM_TypeDef;
-
-
-/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
-typedef struct
-{
-  __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
-  __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
-  __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
-  __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
-  __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
-  __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
-  __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
-  __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
-  __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
-  __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
-  __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
-  __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
-  __I  uint32_t CR1;					/*!< Offset: 0x030 Capture Register 1 (R/ ) */
-  __I  uint32_t CR2;					/*!< Offset: 0x034 Capture Register 2 (R/ ) */
-  __I  uint32_t CR3;					/*!< Offset: 0x038 Capture Register 3 (R/ ) */
-       uint32_t RESERVED0;
-  __IO uint32_t MR4;					/*!< Offset: 0x040 Match Register 4 (R/W) */
-  __IO uint32_t MR5;					/*!< Offset: 0x044 Match Register 5 (R/W) */
-  __IO uint32_t MR6;					/*!< Offset: 0x048 Match Register 6 (R/W) */
-  __IO uint32_t PCR;					/*!< Offset: 0x04C PWM Control Register (R/W) */
-  __IO uint32_t LER;					/*!< Offset: 0x050 Load Enable Register (R/W) */
-       uint32_t RESERVED1[7];
-  __IO uint32_t CTCR;					/*!< Offset: 0x070 Counter Control Register (R/W) */
-} LPC_PWM_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
-/* There are three types of UARTs on the chip:
-(1) UART0,UART2, and UART3 are the standard UART.
-(2) UART1 is the standard with modem capability.
-(3) USART(UART4) is the sync/async UART with smart card capability.
-More details can be found on the Users Manual. */
-
-#if 0
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[7];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED2[7];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED3[3];
-  __IO uint32_t ACR;
-  __IO uint8_t  ICR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  FDR;
-       uint8_t  RESERVED5[7];
-  __IO uint8_t  TER;
-       uint8_t  RESERVED6[39];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART_TypeDef;
-#else
-typedef struct
-{
-	union
-	{
-		__I  uint8_t  RBR;
-		__O  uint8_t  THR;
-		__IO uint8_t  DLL;
-		uint32_t RESERVED0;
-	};
-	union
-	{
-		__IO uint8_t  DLM;
-		__IO uint32_t IER;
-	};
-	union
-	{
-		__I  uint32_t IIR;
-		__O  uint8_t  FCR;
-	};
-	__IO uint8_t  LCR;
-	uint8_t  RESERVED1[7];//Reserved
-	__I  uint8_t  LSR;
-	uint8_t  RESERVED2[7];//Reserved
-	__IO uint8_t  SCR;
-	uint8_t  RESERVED3[3];//Reserved
-	__IO uint32_t ACR;
-	__IO uint8_t  ICR;
-	uint8_t  RESERVED4[3];//Reserved
-	__IO uint8_t  FDR;
-	uint8_t  RESERVED5[7];//Reserved
-	__IO uint8_t  TER;
-	uint8_t  RESERVED8[27];//Reserved
-	__IO uint8_t  RS485CTRL;
-	uint8_t  RESERVED9[3];//Reserved
-	__IO uint8_t  ADRMATCH;
-	uint8_t  RESERVED10[3];//Reserved
-	__IO uint8_t  RS485DLY;
-	uint8_t  RESERVED11[3];//Reserved
-	__I  uint8_t  FIFOLVL;
-}LPC_UART_TypeDef;
-#endif
-
-
-typedef struct
-{
-  union {
-  __I  uint8_t  RBR;
-  __O  uint8_t  THR;
-  __IO uint8_t  DLL;
-       uint32_t RESERVED0;
-  };
-  union {
-  __IO uint8_t  DLM;
-  __IO uint32_t IER;
-  };
-  union {
-  __I  uint32_t IIR;
-  __O  uint8_t  FCR;
-  };
-  __IO uint8_t  LCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  MCR;
-       uint8_t  RESERVED2[3];
-  __I  uint8_t  LSR;
-       uint8_t  RESERVED3[3];
-  __I  uint8_t  MSR;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  SCR;
-       uint8_t  RESERVED5[3];
-  __IO uint32_t ACR;
-       uint32_t RESERVED6;
-  __IO uint32_t FDR;
-       uint32_t RESERVED7;
-  __IO uint8_t  TER;
-       uint8_t  RESERVED8[27];
-  __IO uint8_t  RS485CTRL;
-       uint8_t  RESERVED9[3];
-  __IO uint8_t  ADRMATCH;
-       uint8_t  RESERVED10[3];
-  __IO uint8_t  RS485DLY;
-       uint8_t  RESERVED11[3];
-  __I  uint8_t  FIFOLVL;
-} LPC_UART1_TypeDef;
-
-typedef struct
-{
-  union {
-  __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
-  __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
-  __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
-  };
-  union {
-  __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
-  __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
-  };
-  union {
-  __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
-  __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
-  };
-  __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
-  __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
-  __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
-  __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
-  __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
-  __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
-  __IO uint32_t  ICR;                   /*!< Offset: 0x024 irDA Control Register (R/W) */
-  __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
-  __IO uint32_t  OSR;                   /*!< Offset: 0x02C Over sampling Register (R/W) */
-  __O  uint32_t  POP;                   /*!< Offset: 0x030 NHP Pop Register (W) */
-  __IO uint32_t  MODE;                  /*!< Offset: 0x034 NHP Mode selection Register (W) */
-       uint32_t  RESERVED0[2];
-  __IO uint32_t  HDEN;                  /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
-       uint32_t  RESERVED1;
-  __IO uint32_t  SCI_CTRL;				/*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
-  __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
-  __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
-  __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
-  __IO uint32_t  SYNCCTRL;              /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
-  __IO uint32_t  TER;                   /*!< Offset: 0x05C Transmit Enable Register (R/W) */
-       uint32_t  RESERVED2[989];
-  __I  uint32_t  CFG;                   /*!< Offset: 0xFD4 Configuration Register (R) */
-  __O  uint32_t  INTCE;                 /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
-  __O  uint32_t  INTSE;                 /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
-  __I  uint32_t  INTS;                  /*!< Offset: 0xFE0 Interrupt Status Register (R) */
-  __I  uint32_t  INTE;                  /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
-  __O  uint32_t  INTCS;                 /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
-  __O  uint32_t  INTSS;                 /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
-       uint32_t  RESERVED3[3];
-  __I  uint32_t  MID;                   /*!< Offset: 0xFFC Module Identification Register (R) */
-} LPC_UART4_TypeDef;
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
-  __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
-  __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
-  __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
-  __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
-  __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
-  __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
-  __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
-  __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
-  __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
-  __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
-  __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
-  __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
-  __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
-  __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
-  __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
-} LPC_I2C_TypeDef;
-
-/*------------- Real-Time Clock (RTC) ----------------------------------------*/
-typedef struct
-{
-  __IO uint8_t  ILR;
-       uint8_t  RESERVED0[7];
-  __IO uint8_t  CCR;
-       uint8_t  RESERVED1[3];
-  __IO uint8_t  CIIR;
-       uint8_t  RESERVED2[3];
-  __IO uint8_t  AMR;
-       uint8_t  RESERVED3[3];
-  __I  uint32_t CTIME0;
-  __I  uint32_t CTIME1;
-  __I  uint32_t CTIME2;
-  __IO uint8_t  SEC;
-       uint8_t  RESERVED4[3];
-  __IO uint8_t  MIN;
-       uint8_t  RESERVED5[3];
-  __IO uint8_t  HOUR;
-       uint8_t  RESERVED6[3];
-  __IO uint8_t  DOM;
-       uint8_t  RESERVED7[3];
-  __IO uint8_t  DOW;
-       uint8_t  RESERVED8[3];
-  __IO uint16_t DOY;
-       uint16_t RESERVED9;
-  __IO uint8_t  MONTH;
-       uint8_t  RESERVED10[3];
-  __IO uint16_t YEAR;
-       uint16_t RESERVED11;
-  __IO uint32_t CALIBRATION;
-  __IO uint32_t GPREG0;
-  __IO uint32_t GPREG1;
-  __IO uint32_t GPREG2;
-  __IO uint32_t GPREG3;
-  __IO uint32_t GPREG4;
-  __IO uint8_t  RTC_AUXEN;
-       uint8_t  RESERVED12[3];
-  __IO uint8_t  RTC_AUX;
-       uint8_t  RESERVED13[3];
-  __IO uint8_t  ALSEC;
-       uint8_t  RESERVED14[3];
-  __IO uint8_t  ALMIN;
-       uint8_t  RESERVED15[3];
-  __IO uint8_t  ALHOUR;
-       uint8_t  RESERVED16[3];
-  __IO uint8_t  ALDOM;
-       uint8_t  RESERVED17[3];
-  __IO uint8_t  ALDOW;
-       uint8_t  RESERVED18[3];
-  __IO uint16_t ALDOY;
-       uint16_t RESERVED19;
-  __IO uint8_t  ALMON;
-       uint8_t  RESERVED20[3];
-  __IO uint16_t ALYEAR;
-       uint16_t RESERVED21;
-  __IO uint32_t ERSTATUS;
-  __IO uint32_t ERCONTROL;
-  __IO uint32_t ERCOUNTERS;
-       uint32_t RESERVED22;
-  __IO uint32_t ERFIRSTSTAMP0;
-  __IO uint32_t ERFIRSTSTAMP1;
-  __IO uint32_t ERFIRSTSTAMP2;
-       uint32_t RESERVED23;
-  __IO uint32_t ERLASTSTAMP0;
-  __IO uint32_t ERLASTSTAMP1;
-  __IO uint32_t ERLASTSTAMP2;
-} LPC_RTC_TypeDef;
-
-
-
-/*------------- Pin Connect Block (PINCON) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t P0_0;				/* 0x000 */
-  __IO uint32_t P0_1;
-  __IO uint32_t P0_2;
-  __IO uint32_t P0_3;
-  __IO uint32_t P0_4;
-  __IO uint32_t P0_5;
-  __IO uint32_t P0_6;
-  __IO uint32_t P0_7;
-
-  __IO uint32_t P0_8;				/* 0x020 */
-  __IO uint32_t P0_9;
-  __IO uint32_t P0_10;
-  __IO uint32_t P0_11;
-  __IO uint32_t P0_12;
-  __IO uint32_t P0_13;
-  __IO uint32_t P0_14;
-  __IO uint32_t P0_15;
-
-  __IO uint32_t P0_16;				/* 0x040 */
-  __IO uint32_t P0_17;
-  __IO uint32_t P0_18;
-  __IO uint32_t P0_19;
-  __IO uint32_t P0_20;
-  __IO uint32_t P0_21;
-  __IO uint32_t P0_22;
-  __IO uint32_t P0_23;
-
-  __IO uint32_t P0_24;				/* 0x060 */
-  __IO uint32_t P0_25;
-  __IO uint32_t P0_26;
-  __IO uint32_t P0_27;
-  __IO uint32_t P0_28;
-  __IO uint32_t P0_29;
-  __IO uint32_t P0_30;
-  __IO uint32_t P0_31;
-
-  __IO uint32_t P1_0;				/* 0x080 */
-  __IO uint32_t P1_1;
-  __IO uint32_t P1_2;
-  __IO uint32_t P1_3;
-  __IO uint32_t P1_4;
-  __IO uint32_t P1_5;
-  __IO uint32_t P1_6;
-  __IO uint32_t P1_7;
-
-  __IO uint32_t P1_8;				/* 0x0A0 */
-  __IO uint32_t P1_9;
-  __IO uint32_t P1_10;
-  __IO uint32_t P1_11;
-  __IO uint32_t P1_12;
-  __IO uint32_t P1_13;
-  __IO uint32_t P1_14;
-  __IO uint32_t P1_15;
-
-  __IO uint32_t P1_16;				/* 0x0C0 */
-  __IO uint32_t P1_17;
-  __IO uint32_t P1_18;
-  __IO uint32_t P1_19;
-  __IO uint32_t P1_20;
-  __IO uint32_t P1_21;
-  __IO uint32_t P1_22;
-  __IO uint32_t P1_23;
-
-  __IO uint32_t P1_24;				/* 0x0E0 */
-  __IO uint32_t P1_25;
-  __IO uint32_t P1_26;
-  __IO uint32_t P1_27;
-  __IO uint32_t P1_28;
-  __IO uint32_t P1_29;
-  __IO uint32_t P1_30;
-  __IO uint32_t P1_31;
-
-  __IO uint32_t P2_0;				/* 0x100 */
-  __IO uint32_t P2_1;
-  __IO uint32_t P2_2;
-  __IO uint32_t P2_3;
-  __IO uint32_t P2_4;
-  __IO uint32_t P2_5;
-  __IO uint32_t P2_6;
-  __IO uint32_t P2_7;
-
-  __IO uint32_t P2_8;				/* 0x120 */
-  __IO uint32_t P2_9;
-  __IO uint32_t P2_10;
-  __IO uint32_t P2_11;
-  __IO uint32_t P2_12;
-  __IO uint32_t P2_13;
-  __IO uint32_t P2_14;
-  __IO uint32_t P2_15;
-
-  __IO uint32_t P2_16;				/* 0x140 */
-  __IO uint32_t P2_17;
-  __IO uint32_t P2_18;
-  __IO uint32_t P2_19;
-  __IO uint32_t P2_20;
-  __IO uint32_t P2_21;
-  __IO uint32_t P2_22;
-  __IO uint32_t P2_23;
-
-  __IO uint32_t P2_24;				/* 0x160 */
-  __IO uint32_t P2_25;
-  __IO uint32_t P2_26;
-  __IO uint32_t P2_27;
-  __IO uint32_t P2_28;
-  __IO uint32_t P2_29;
-  __IO uint32_t P2_30;
-  __IO uint32_t P2_31;
-
-  __IO uint32_t P3_0;				/* 0x180 */
-  __IO uint32_t P3_1;
-  __IO uint32_t P3_2;
-  __IO uint32_t P3_3;
-  __IO uint32_t P3_4;
-  __IO uint32_t P3_5;
-  __IO uint32_t P3_6;
-  __IO uint32_t P3_7;
-
-  __IO uint32_t P3_8;				/* 0x1A0 */
-  __IO uint32_t P3_9;
-  __IO uint32_t P3_10;
-  __IO uint32_t P3_11;
-  __IO uint32_t P3_12;
-  __IO uint32_t P3_13;
-  __IO uint32_t P3_14;
-  __IO uint32_t P3_15;
-
-  __IO uint32_t P3_16;				/* 0x1C0 */
-  __IO uint32_t P3_17;
-  __IO uint32_t P3_18;
-  __IO uint32_t P3_19;
-  __IO uint32_t P3_20;
-  __IO uint32_t P3_21;
-  __IO uint32_t P3_22;
-  __IO uint32_t P3_23;
-
-  __IO uint32_t P3_24;				/* 0x1E0 */
-  __IO uint32_t P3_25;
-  __IO uint32_t P3_26;
-  __IO uint32_t P3_27;
-  __IO uint32_t P3_28;
-  __IO uint32_t P3_29;
-  __IO uint32_t P3_30;
-  __IO uint32_t P3_31;
-
-  __IO uint32_t P4_0;				/* 0x200 */
-  __IO uint32_t P4_1;
-  __IO uint32_t P4_2;
-  __IO uint32_t P4_3;
-  __IO uint32_t P4_4;
-  __IO uint32_t P4_5;
-  __IO uint32_t P4_6;
-  __IO uint32_t P4_7;
-
-  __IO uint32_t P4_8;				/* 0x220 */
-  __IO uint32_t P4_9;
-  __IO uint32_t P4_10;
-  __IO uint32_t P4_11;
-  __IO uint32_t P4_12;
-  __IO uint32_t P4_13;
-  __IO uint32_t P4_14;
-  __IO uint32_t P4_15;
-
-  __IO uint32_t P4_16;				/* 0x240 */
-  __IO uint32_t P4_17;
-  __IO uint32_t P4_18;
-  __IO uint32_t P4_19;
-  __IO uint32_t P4_20;
-  __IO uint32_t P4_21;
-  __IO uint32_t P4_22;
-  __IO uint32_t P4_23;
-
-  __IO uint32_t P4_24;				/* 0x260 */
-  __IO uint32_t P4_25;
-  __IO uint32_t P4_26;
-  __IO uint32_t P4_27;
-  __IO uint32_t P4_28;
-  __IO uint32_t P4_29;
-  __IO uint32_t P4_30;
-  __IO uint32_t P4_31;
-
-  __IO uint32_t P5_0;				/* 0x280 */
-  __IO uint32_t P5_1;
-  __IO uint32_t P5_2;
-  __IO uint32_t P5_3;
-  __IO uint32_t P5_4;				/* 0x290 */
-} LPC_IOCON_TypeDef;
-
-
-
-
-
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
-  __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
-  __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
-  __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
-  __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
-  __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
-  __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
-  __IO uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
-  __IO uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
-  __IO uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
-  __IO uint32_t DMACR;
-} LPC_SSP_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
-  __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
-       uint32_t RESERVED0;
-  __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
-  __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
-  __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
-  __IO uint32_t ADTRM;
-} LPC_ADC_TypeDef;
-
-/*------------- Controller Area Network (CAN) --------------------------------*/
-typedef struct
-{
-  __IO uint32_t mask[512];              /* ID Masks                           */
-} LPC_CANAF_RAM_TypeDef;
-
-typedef struct                          /* Acceptance Filter Registers        */
-{
-	///Offset: 0x00000000 - Acceptance Filter Register
-	__IO uint32_t AFMR;
-
-	///Offset: 0x00000004 - Standard Frame Individual Start Address Register
-	__IO uint32_t SFF_sa;
-
-	///Offset: 0x00000008 - Standard Frame Group Start Address Register
-	__IO uint32_t SFF_GRP_sa;
-
-	///Offset: 0x0000000C - Extended Frame Start Address Register
-	__IO uint32_t EFF_sa;
-
-	///Offset: 0x00000010 - Extended Frame Group Start Address Register
-	__IO uint32_t EFF_GRP_sa;
-
-	///Offset: 0x00000014 - End of AF Tables register
-	__IO uint32_t ENDofTable;
-
-	///Offset: 0x00000018 - LUT Error Address register
-	__I  uint32_t LUTerrAd;
-
-	///Offset: 0x0000001C - LUT Error Register
-	__I  uint32_t LUTerr;
-
-	///Offset: 0x00000020 - CAN Central Transmit Status Register
-	__IO uint32_t FCANIE;
-
-	///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
-	__IO uint32_t FCANIC0;
-
-	///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
-	__IO uint32_t FCANIC1;
-} LPC_CANAF_TypeDef;
-
-typedef struct                          /* Central Registers                  */
-{
-  __I  uint32_t TxSR;
-  __I  uint32_t RxSR;
-  __I  uint32_t MSR;
-} LPC_CANCR_TypeDef;
-
-typedef struct                          /* Controller Registers               */
-{
-	///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
-	__IO uint32_t MOD;
-
-	///Offset: 0x00000004 - Command bits that affect the state
-	__O  uint32_t CMR;
-
-	///Offset: 0x00000008 - Global Controller Status and Error Counters
-	__IO uint32_t GSR;
-
-	///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
-	__I  uint32_t ICR;
-
-	///Offset: 0x00000010 - Interrupt Enable Register
-	__IO uint32_t IER;
-
-	///Offset: 0x00000014 - Bus Timing Register
-	__IO uint32_t BTR;
-
-	///Offset: 0x00000018 - Error Warning Limit
-	__IO uint32_t EWL;
-
-	///Offset: 0x0000001C - Status Register
-	__I  uint32_t SR;
-
-	///Offset: 0x00000020 - Receive frame status
-	__IO uint32_t RFS;
-
-	///Offset: 0x00000024 - Received Identifier
-	__IO uint32_t RID;
-
-	///Offset: 0x00000028 - Received data bytes 1-4
-	__IO uint32_t RDA;
-
-	///Offset: 0x0000002C - Received data bytes 5-8
-	__IO uint32_t RDB;
-
-	///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
-	__IO uint32_t TFI1;
-
-	///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
-	__IO uint32_t TID1;
-
-	///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
-	__IO uint32_t TDA1;
-
-	///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
-	__IO uint32_t TDB1;
-
-	///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
-	__IO uint32_t TFI2;
-
-	///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
-	__IO uint32_t TID2;
-
-	///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
-	__IO uint32_t TDA2;
-
-	///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
-	__IO uint32_t TDB2;
-
-	///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
-	__IO uint32_t TFI3;
-
-	///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
-	__IO uint32_t TID3;
-
-	///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
-	__IO uint32_t TDA3;
-
-	///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
-	__IO uint32_t TDB3;
-} LPC_CAN_TypeDef;
-
-/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
-typedef struct
-{
-  __IO uint32_t CR;
-  __IO uint32_t CTRL;
-  __IO uint32_t CNTVAL;
-} LPC_DAC_TypeDef;
-
-
-/*------------- Inter IC Sound (I2S) -----------------------------------------*/
-typedef struct
-{
-  __IO uint32_t DAO;
-  __IO uint32_t DAI;
-  __O  uint32_t TXFIFO;
-  __I  uint32_t RXFIFO;
-  __I  uint32_t STATE;
-  __IO uint32_t DMA1;
-  __IO uint32_t DMA2;
-  __IO uint32_t IRQ;
-  __IO uint32_t TXRATE;
-  __IO uint32_t RXRATE;
-  __IO uint32_t TXBITRATE;
-  __IO uint32_t RXBITRATE;
-  __IO uint32_t TXMODE;
-  __IO uint32_t RXMODE;
-} LPC_I2S_TypeDef;
-
-
-
-
-
-
-/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
-typedef struct
-{
-  __I  uint32_t CON;
-  __O  uint32_t CON_SET;
-  __O  uint32_t CON_CLR;
-  __I  uint32_t CAPCON;
-  __O  uint32_t CAPCON_SET;
-  __O  uint32_t CAPCON_CLR;
-  __IO uint32_t TC0;
-  __IO uint32_t TC1;
-  __IO uint32_t TC2;
-  __IO uint32_t LIM0;
-  __IO uint32_t LIM1;
-  __IO uint32_t LIM2;
-  __IO uint32_t MAT0;
-  __IO uint32_t MAT1;
-  __IO uint32_t MAT2;
-  __IO uint32_t DT;
-  __IO uint32_t CP;
-  __IO uint32_t CAP0;
-  __IO uint32_t CAP1;
-  __IO uint32_t CAP2;
-  __I  uint32_t INTEN;
-  __O  uint32_t INTEN_SET;
-  __O  uint32_t INTEN_CLR;
-  __I  uint32_t CNTCON;
-  __O  uint32_t CNTCON_SET;
-  __O  uint32_t CNTCON_CLR;
-  __I  uint32_t INTF;
-  __O  uint32_t INTF_SET;
-  __O  uint32_t INTF_CLR;
-  __O  uint32_t CAP_CLR;
-} LPC_MCPWM_TypeDef;
-
-/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
-typedef struct
-{
-  __O  uint32_t CON;
-  __I  uint32_t STAT;
-  __IO uint32_t CONF;
-  __I  uint32_t POS;
-  __IO uint32_t MAXPOS;
-  __IO uint32_t CMPOS0;
-  __IO uint32_t CMPOS1;
-  __IO uint32_t CMPOS2;
-  __I  uint32_t INXCNT;
-  __IO uint32_t INXCMP0;
-  __IO uint32_t LOAD;
-  __I  uint32_t TIME;
-  __I  uint32_t VEL;
-  __I  uint32_t CAP;
-  __IO uint32_t VELCOMP;
-  __IO uint32_t FILTERPHA;
-  __IO uint32_t FILTERPHB;
-  __IO uint32_t FILTERINX;
-  __IO uint32_t WINDOW;
-  __IO uint32_t INXCMP1;
-  __IO uint32_t INXCMP2;
-       uint32_t RESERVED0[993];
-  __O  uint32_t IEC;
-  __O  uint32_t IES;
-  __I  uint32_t INTSTAT;
-  __I  uint32_t IE;
-  __O  uint32_t CLR;
-  __O  uint32_t SET;
-} LPC_QEI_TypeDef;
-
-/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
-typedef struct
-{
-  __IO uint32_t POWER;
-  __IO uint32_t CLOCK;
-  __IO uint32_t ARGUMENT;
-  __IO uint32_t COMMAND;
-  __I  uint32_t RESP_CMD;
-  __I  uint32_t RESP0;
-  __I  uint32_t RESP1;
-  __I  uint32_t RESP2;
-  __I  uint32_t RESP3;
-  __IO uint32_t DATATMR;
-  __IO uint32_t DATALEN;
-  __IO uint32_t DATACTRL;
-  __I  uint32_t DATACNT;
-  __I  uint32_t STATUS;
-  __O  uint32_t CLEAR;
-  __IO uint32_t MASK0;
-       uint32_t RESERVED0[2];
-  __I  uint32_t FIFOCNT;
-       uint32_t RESERVED1[13];
-  __IO uint32_t FIFO[16];
-} LPC_MCI_TypeDef;
-
-
-
-
-
-
-
-
-
-
-/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
-typedef struct
-{
-  __IO uint32_t CMD;			/* 0x0080 */
-  __IO uint32_t ADDR;
-  __IO uint32_t WDATA;
-  __IO uint32_t RDATA;
-  __IO uint32_t WSTATE;			/* 0x0090 */
-  __IO uint32_t CLKDIV;
-  __IO uint32_t PWRDWN;			/* 0x0098 */
-       uint32_t RESERVED0[975];
-  __IO uint32_t INT_CLR_ENABLE;	/* 0x0FD8 */
-  __IO uint32_t INT_SET_ENABLE;
-  __IO uint32_t INT_STATUS;		/* 0x0FE0 */
-  __IO uint32_t INT_ENABLE;
-  __IO uint32_t INT_CLR_STATUS;
-  __IO uint32_t INT_SET_STATUS;
-} LPC_EEPROM_TypeDef;
-
-
-/*------------- COMPARATOR ----------------------------------------------------*/
-
-typedef struct {                                    /*!< (@ 0x40020000) COMPARATOR Structure                                   */
-  __IO uint32_t  CTRL;                              /*!< (@ 0x40020000) Comparator block control register                      */
-  __IO uint32_t  CTRL0;                             /*!< (@ 0x40020004) Comparator 0 control register                          */
-  __IO uint32_t  CTRL1;                             /*!< (@ 0x40020008) Comparator 1 control register                          */
-} LPC_COMPARATOR_Type;
-
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#elif defined ( __ICCARM__ )
-#pragma language=restore
-#endif
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/* Base addresses                                                             */
-#define LPC_FLASH_BASE        (0x00000000UL)
-#define LPC_RAM_BASE          (0x10000000UL)
-#define LPC_PERI_RAM_BASE     (0x20000000UL)
-#define LPC_APB0_BASE         (0x40000000UL)
-#define LPC_APB1_BASE         (0x40080000UL)
-#define LPC_AHBRAM1_BASE      (0x20004000UL)
-#define LPC_AHB_BASE          (0x20080000UL)
-#define LPC_CM3_BASE          (0xE0000000UL)
-
-/* APB0 peripherals                                                           */
-#define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
-#define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
-#define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
-#define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
-#define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
-#define LPC_PWM0_BASE         (LPC_APB0_BASE + 0x14000)
-#define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
-#define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
-#define LPC_COMPARATOR_BASE   (LPC_APB0_BASE + 0x20000)					
-#define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
-#define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
-#define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x2C000)
-#define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
-#define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
-#define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
-#define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
-#define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
-#define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
-#define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
-#define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
-
-/* APB1 peripherals                                                           */
-#define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
-#define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
-#define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
-#define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
-#define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
-#define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
-#define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
-#define LPC_UART4_BASE        (LPC_APB1_BASE + 0x24000)
-#define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
-#define LPC_SSP2_BASE         (LPC_APB1_BASE + 0x2C000)
-#define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
-#define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
-#define LPC_MCI_BASE          (LPC_APB1_BASE + 0x40000)
-#define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
-
-/* AHB peripherals                                                            */
-#define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x00000)
-#define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x00100)
-#define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x00120)
-#define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x00140)
-#define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x00160)
-#define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x00180)
-#define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x001A0)
-#define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x001C0)
-#define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x001E0)
-#define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x04000)
-#define LPC_LCD_BASE          (LPC_AHB_BASE  + 0x08000)
-#define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
-#define LPC_CRC_BASE          (LPC_AHB_BASE  + 0x10000)
-#define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x18000)
-#define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x18020)
-#define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x18040)
-#define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x18060)
-#define LPC_GPIO4_BASE        (LPC_AHB_BASE  + 0x18080)
-#define LPC_GPIO5_BASE        (LPC_AHB_BASE  + 0x180A0)
-#define LPC_EMC_BASE          (LPC_AHB_BASE  + 0x1C000)
-
-#define LPC_EEPROM_BASE       (LPC_FLASH_BASE+ 0x200080)
-
-
-/******************************************************************************/
-/*                         Peripheral declaration                             */
-/******************************************************************************/
-#define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
-#define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
-#define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
-#define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
-#define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
-#define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
-#define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )
-#define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
-#define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
-#define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
-#define LPC_UART4             ((LPC_UART4_TypeDef     *) LPC_UART4_BASE    )
-#define LPC_PWM0              ((LPC_PWM_TypeDef       *) LPC_PWM0_BASE     )
-#define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
-#define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
-#define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
-#define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
-#define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
-#define LPC_COMPARATOR        ((LPC_COMPARATOR_Type	  *) LPC_COMPARATOR_BASE)
-#define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
-#define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
-#define LPC_IOCON             ((LPC_IOCON_TypeDef     *) LPC_IOCON_BASE    )
-#define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
-#define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
-#define LPC_SSP2              ((LPC_SSP_TypeDef       *) LPC_SSP2_BASE     )
-#define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
-#define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
-#define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
-#define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
-#define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
-#define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
-#define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
-#define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
-#define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
-#define LPC_MCI               ((LPC_MCI_TypeDef       *) LPC_MCI_BASE      )
-#define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
-#define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
-#define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
-#define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
-#define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
-#define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
-#define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
-#define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
-#define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
-#define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
-#define LPC_LCD               ((LPC_LCD_TypeDef       *) LPC_LCD_BASE      )
-#define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
-#define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
-#define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
-#define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
-#define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
-#define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
-#define LPC_GPIO5             ((LPC_GPIO_TypeDef      *) LPC_GPIO5_BASE    )
-#define LPC_EMC               ((LPC_EMC_TypeDef       *) LPC_EMC_BASE      )
-#define LPC_CRC               ((LPC_CRC_TypeDef       *) LPC_CRC_BASE      )
-#define LPC_EEPROM            ((LPC_EEPROM_TypeDef    *) LPC_EEPROM_BASE   )
-
-
-
-#endif  // __LPC407x_8x_177x_8x_H__

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC177x_8x.h

@@ -1,89 +0,0 @@
-/**********************************************************************
-* $Id$		system_LPC177x_8x.h			2011-06-02
-*//**
-* @file		system_LPC177x_8x.h
-* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-*			for the NXP LPC177x_8x Device Series
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __SYSTEM_LPC177x_8x_H
-#define __SYSTEM_LPC177x_8x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;      /*!< System Clock Frequency (Core Clock)  	*/
-extern uint32_t PeripheralClock;	    /*!< Peripheral Clock Frequency (Pclk) 	    */
-extern uint32_t EMCClock;			        /*!< EMC Clock                              */
-extern uint32_t USBClock;			        /*!< USB Frequency 						              */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32768UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     (12000000UL)        /* Internal RC oscillator frequency   */
-#define WDT_OSC		  (  500000UL)		/* Internal WDT oscillator frequency  */
-
-
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC177x_8x_H */

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Include/system_LPC407x_8x_177x_8x.h

@@ -1,89 +0,0 @@
-/**********************************************************************
-* $Id$		system_LPC407x_8x_177x_8x.h			2011-06-02
-*//**
-* @file		system_LPC407x_8x_177x_8x.h
-* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-*			for the NXP LPC Device Series
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __SYSTEM_LPC407x_8x_177x_8x_H
-#define __SYSTEM_LPC407x_8x_177x_8x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock;      /*!< System Clock Frequency (Core Clock)  	*/
-extern uint32_t PeripheralClock;	    /*!< Peripheral Clock Frequency (Pclk) 	    */
-extern uint32_t EMCClock;			        /*!< EMC Clock                              */
-extern uint32_t USBClock;			        /*!< USB Frequency 						              */
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define XTAL        (12000000UL)        /* Oscillator frequency               */
-#define OSC_CLK     (      XTAL)        /* Main oscillator frequency          */
-#define RTC_CLK     (   32768UL)        /* RTC oscillator frequency           */
-#define IRC_OSC     (12000000UL)        /* Internal RC oscillator frequency   */
-#define WDT_OSC		  (  500000UL)		/* Internal WDT oscillator frequency  */
-
-
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC407x_8x_177x_8x_H */

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC177x_8x.s

@@ -1,301 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC177x_8x.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File
-; *           for the NXP LPC177x_8x Device Series 
-; * @version: V1.20
-; * @date:    07. October 2010
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2010 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000200
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors		DCD		__initial_sp              ; Top of Stack
-				DCD		Reset_Handler             ; Reset Handler
-				DCD		NMI_Handler               ; NMI Handler
-				DCD		HardFault_Handler         ; Hard Fault Handler
-				DCD		MemManage_Handler         ; MPU Fault Handler
-				DCD		BusFault_Handler          ; Bus Fault Handler
-				DCD		UsageFault_Handler        ; Usage Fault Handler
-				DCD		0                         ; Reserved
-				DCD		0                         ; Reserved
-				DCD		0                         ; Reserved
-				DCD		0                         ; Reserved
-				DCD		SVC_Handler               ; SVCall Handler
-				DCD		DebugMon_Handler          ; Debug Monitor Handler
-				DCD		0                         ; Reserved
-				DCD		PendSV_Handler            ; PendSV Handler
-				DCD		SysTick_Handler           ; SysTick Handler
-				
-				; External Interrupts
-				DCD		WDT_IRQHandler            ; 16: Watchdog Timer
-				DCD		TIMER0_IRQHandler         ; 17: Timer0
-				DCD		TIMER1_IRQHandler         ; 18: Timer1
-				DCD		TIMER2_IRQHandler         ; 19: Timer2
-				DCD		TIMER3_IRQHandler         ; 20: Timer3
-				DCD		UART0_IRQHandler          ; 21: UART0
-				DCD		UART1_IRQHandler          ; 22: UART1
-				DCD		UART2_IRQHandler          ; 23: UART2
-				DCD		UART3_IRQHandler          ; 24: UART3
-				DCD		PWM1_IRQHandler           ; 25: PWM1
-				DCD		I2C0_IRQHandler           ; 26: I2C0
-				DCD		I2C1_IRQHandler           ; 27: I2C1
-				DCD		I2C2_IRQHandler           ; 28: I2C2
-				DCD		0						  ; 29: reserved, not for SPIFI anymore
-				DCD		SSP0_IRQHandler           ; 30: SSP0
-				DCD		SSP1_IRQHandler           ; 31: SSP1
-				DCD		PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-				DCD		RTC_IRQHandler            ; 33: Real Time Clock
-				DCD		EINT0_IRQHandler          ; 34: External Interrupt 0
-				DCD		EINT1_IRQHandler          ; 35: External Interrupt 1
-				DCD		EINT2_IRQHandler          ; 36: External Interrupt 2
-				DCD		EINT3_IRQHandler          ; 37: External Interrupt 3
-				DCD		ADC_IRQHandler            ; 38: A/D Converter
-				DCD		BOD_IRQHandler            ; 39: Brown-Out Detect
-				DCD		USB_IRQHandler            ; 40: USB
-				DCD		CAN_IRQHandler            ; 41: CAN
-				DCD		DMA_IRQHandler            ; 42: General Purpose DMA
-				DCD		I2S_IRQHandler            ; 43: I2S
-				DCD		ENET_IRQHandler           ; 44: Ethernet
-				DCD		MCI_IRQHandler            ; 45: SD/MMC card I/F
-				DCD		MCPWM_IRQHandler          ; 46: Motor Control PWM
-				DCD		QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-				DCD		PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-				DCD		USBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup
-				DCD		CANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup
-				DCD		UART4_IRQHandler          ; 51: UART4
-				DCD		SSP2_IRQHandler           ; 52: SSP2
-				DCD		LCD_IRQHandler            ; 53: LCD
-				DCD		GPIO_IRQHandler           ; 54: GPIO
-				DCD		PWM0_IRQHandler           ; 55: PWM0
-				DCD		EEPROM_IRQHandler         ; 56: EEPROM
-				
-				
-				IF      :LNOT::DEF:NO_CRP
-				AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key			DCD     0xFFFFFFFF
-				ENDIF
-				
-				
-				AREA    |.text|, CODE, READONLY
-				
-				
-; Reset Handler
-
-Reset_Handler	PROC
-				EXPORT  Reset_Handler             [WEAK]
-				IMPORT  SystemInit
-				IMPORT  __main
-				LDR     R0, =SystemInit
-				BLX     R0
-				LDR     R0, =__main
-				BX      R0
-				ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler		PROC
-				EXPORT  NMI_Handler               [WEAK]
-				B       .
-				ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-				PROC
-				EXPORT  UsageFault_Handler        [WEAK]
-				B       .
-				ENDP
-SVC_Handler		PROC
-				EXPORT  SVC_Handler               [WEAK]
-				B       .
-				ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler	PROC
-				EXPORT  PendSV_Handler            [WEAK]
-				B       .
-				ENDP
-SysTick_Handler	PROC
-				EXPORT  SysTick_Handler           [WEAK]
-				B       .
-				ENDP
-
-Default_Handler PROC
-				
-				EXPORT  WDT_IRQHandler            [WEAK]
-				EXPORT  TIMER0_IRQHandler         [WEAK]
-				EXPORT  TIMER1_IRQHandler         [WEAK]
-				EXPORT  TIMER2_IRQHandler         [WEAK]
-				EXPORT  TIMER3_IRQHandler         [WEAK]
-				EXPORT  UART0_IRQHandler          [WEAK]
-				EXPORT  UART1_IRQHandler          [WEAK]
-				EXPORT  UART2_IRQHandler          [WEAK]
-				EXPORT  UART3_IRQHandler          [WEAK]
-				EXPORT  PWM1_IRQHandler           [WEAK]
-				EXPORT  I2C0_IRQHandler           [WEAK]
-				EXPORT  I2C1_IRQHandler           [WEAK]
-				EXPORT  I2C2_IRQHandler           [WEAK]
-				;EXPORT  SPIFI_IRQHandler          [WEAK]
-				EXPORT  SSP0_IRQHandler           [WEAK]
-				EXPORT  SSP1_IRQHandler           [WEAK]
-				EXPORT  PLL0_IRQHandler           [WEAK]
-				EXPORT  RTC_IRQHandler            [WEAK]
-				EXPORT  EINT0_IRQHandler          [WEAK]
-				EXPORT  EINT1_IRQHandler          [WEAK]
-				EXPORT  EINT2_IRQHandler          [WEAK]
-				EXPORT  EINT3_IRQHandler          [WEAK]
-				EXPORT  ADC_IRQHandler            [WEAK]
-				EXPORT  BOD_IRQHandler            [WEAK]
-				EXPORT  USB_IRQHandler            [WEAK]
-				EXPORT  CAN_IRQHandler            [WEAK]
-				EXPORT  DMA_IRQHandler            [WEAK]
-				EXPORT  I2S_IRQHandler            [WEAK]
-				EXPORT  ENET_IRQHandler           [WEAK]
-				EXPORT  MCI_IRQHandler            [WEAK]
-				EXPORT  MCPWM_IRQHandler          [WEAK]
-				EXPORT  QEI_IRQHandler            [WEAK]
-				EXPORT  PLL1_IRQHandler           [WEAK]
-				EXPORT  USBActivity_IRQHandler    [WEAK]
-				EXPORT  CANActivity_IRQHandler    [WEAK]
-				EXPORT  UART4_IRQHandler          [WEAK]
-				EXPORT  SSP2_IRQHandler           [WEAK]
-				EXPORT  LCD_IRQHandler            [WEAK]
-				EXPORT  GPIO_IRQHandler           [WEAK]
-				EXPORT  PWM0_IRQHandler           [WEAK]
-				EXPORT  EEPROM_IRQHandler         [WEAK]
-
-WDT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-PWM1_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-;SPIFI_IRQHandler	;not used            
-SSP0_IRQHandler
-SSP1_IRQHandler
-PLL0_IRQHandler
-RTC_IRQHandler
-EINT0_IRQHandler
-EINT1_IRQHandler
-EINT2_IRQHandler
-EINT3_IRQHandler
-ADC_IRQHandler
-BOD_IRQHandler
-USB_IRQHandler
-CAN_IRQHandler
-DMA_IRQHandler
-I2S_IRQHandler
-ENET_IRQHandler
-MCI_IRQHandler          
-MCPWM_IRQHandler
-QEI_IRQHandler
-PLL1_IRQHandler
-USBActivity_IRQHandler
-CANActivity_IRQHandler
-UART4_IRQHandler
-SSP2_IRQHandler
-LCD_IRQHandler
-GPIO_IRQHandler
-PWM0_IRQHandler
-EEPROM_IRQHandler
-					
-				B       .
-				
-				ENDP
-				
-				
-				ALIGN
-					
-
-; User Initial Stack & Heap
-				
-				IF      :DEF:__MICROLIB
-				
-				EXPORT  __initial_sp
-				EXPORT  __heap_base
-				EXPORT  __heap_limit
-				
-				ELSE
-				
-				IMPORT  __use_two_region_memory
-				EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-				LDR     R0, =  Heap_Mem
-				LDR     R1, =(Stack_Mem + Stack_Size)
-				LDR     R2, = (Heap_Mem +  Heap_Size)
-				LDR     R3, = Stack_Mem
-				BX      LR
-				
-				ALIGN
-				
-				ENDIF
-				
-				
-				END

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s

@@ -1,302 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC407x_8x.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File
-; *           for the NXP LPC407x_8x Device Series 
-; * @version: V1.20
-; * @date:    16. January 2012
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2012 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M4
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-
-__Vectors		DCD		__initial_sp              ; Top of Stack
-				DCD		Reset_Handler             ; Reset Handler
-				DCD		NMI_Handler               ; NMI Handler
-				DCD		HardFault_Handler         ; Hard Fault Handler
-				DCD		MemManage_Handler         ; MPU Fault Handler
-				DCD		BusFault_Handler          ; Bus Fault Handler
-				DCD		UsageFault_Handler        ; Usage Fault Handler
-			;	DCD		0xEFFFF5D6                ; Reserved- vector sum
-				DCD		0xEFFFF39E                ; Reserved- vector sum
-				DCD		0                         ; Reserved
-				DCD		0                         ; Reserved
-				DCD		0                         ; Reserved
-				DCD		SVC_Handler               ; SVCall Handler
-				DCD		DebugMon_Handler          ; Debug Monitor Handler
-				DCD		0                         ; Reserved
-				DCD		PendSV_Handler            ; PendSV Handler
-				DCD		SysTick_Handler           ; SysTick Handler
-				
-				; External Interrupts
-				DCD		WDT_IRQHandler            ; 16: Watchdog Timer
-				DCD		TIMER0_IRQHandler         ; 17: Timer0
-				DCD		TIMER1_IRQHandler         ; 18: Timer1
-				DCD		TIMER2_IRQHandler         ; 19: Timer2
-				DCD		TIMER3_IRQHandler         ; 20: Timer3
-				DCD		UART0_IRQHandler          ; 21: UART0
-				DCD		UART1_IRQHandler          ; 22: UART1
-				DCD		UART2_IRQHandler          ; 23: UART2
-				DCD		UART3_IRQHandler          ; 24: UART3
-				DCD		PWM1_IRQHandler           ; 25: PWM1
-				DCD		I2C0_IRQHandler           ; 26: I2C0
-				DCD		I2C1_IRQHandler           ; 27: I2C1
-				DCD		I2C2_IRQHandler           ; 28: I2C2
-				DCD		0						  ; 29: reserved, not for SPIFI anymore
-				DCD		SSP0_IRQHandler           ; 30: SSP0
-				DCD		SSP1_IRQHandler           ; 31: SSP1
-				DCD		PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-				DCD		RTC_IRQHandler            ; 33: Real Time Clock
-				DCD		EINT0_IRQHandler          ; 34: External Interrupt 0
-				DCD		EINT1_IRQHandler          ; 35: External Interrupt 1
-				DCD		EINT2_IRQHandler          ; 36: External Interrupt 2
-				DCD		EINT3_IRQHandler          ; 37: External Interrupt 3
-				DCD		ADC_IRQHandler            ; 38: A/D Converter
-				DCD		BOD_IRQHandler            ; 39: Brown-Out Detect
-				DCD		USB_IRQHandler            ; 40: USB
-				DCD		CAN_IRQHandler            ; 41: CAN
-				DCD		DMA_IRQHandler            ; 42: General Purpose DMA
-				DCD		I2S_IRQHandler            ; 43: I2S
-				DCD		ENET_IRQHandler           ; 44: Ethernet
-				DCD		MCI_IRQHandler            ; 45: SD/MMC card I/F
-				DCD		MCPWM_IRQHandler          ; 46: Motor Control PWM
-				DCD		QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-				DCD		PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-				DCD		USBActivity_IRQHandler    ; 49: USB Activity interrupt to wakeup
-				DCD		CANActivity_IRQHandler    ; 50: CAN Activity interrupt to wakeup
-				DCD		UART4_IRQHandler          ; 51: UART4
-				DCD		SSP2_IRQHandler           ; 52: SSP2
-				DCD		LCD_IRQHandler            ; 53: LCD
-				DCD		GPIO_IRQHandler           ; 54: GPIO
-				DCD		PWM0_IRQHandler           ; 55: PWM0
-				DCD		EEPROM_IRQHandler         ; 56: EEPROM
-				
-				
-				IF      :LNOT::DEF:NO_CRP
-				AREA    |.ARM.__at_0x02FC|, CODE, READONLY
-CRP_Key			DCD     0xFFFFFFFF
-				ENDIF
-				
-				
-				AREA    |.text|, CODE, READONLY
-				
-				
-; Reset Handler
-
-Reset_Handler	PROC
-				EXPORT  Reset_Handler             [WEAK]
-				IMPORT  SystemInit
-				IMPORT  __main
-				LDR     R0, =SystemInit
-				BLX     R0
-				LDR     R0, =__main
-				BX      R0
-				ENDP
-
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler		PROC
-				EXPORT  NMI_Handler               [WEAK]
-				B       .
-				ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler         [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler          [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-				PROC
-				EXPORT  UsageFault_Handler        [WEAK]
-				B       .
-				ENDP
-SVC_Handler		PROC
-				EXPORT  SVC_Handler               [WEAK]
-				B       .
-				ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler          [WEAK]
-                B       .
-                ENDP
-PendSV_Handler	PROC
-				EXPORT  PendSV_Handler            [WEAK]
-				B       .
-				ENDP
-SysTick_Handler	PROC
-				EXPORT  SysTick_Handler           [WEAK]
-				B       .
-				ENDP
-
-Default_Handler PROC
-				
-				EXPORT  WDT_IRQHandler            [WEAK]
-				EXPORT  TIMER0_IRQHandler         [WEAK]
-				EXPORT  TIMER1_IRQHandler         [WEAK]
-				EXPORT  TIMER2_IRQHandler         [WEAK]
-				EXPORT  TIMER3_IRQHandler         [WEAK]
-				EXPORT  UART0_IRQHandler          [WEAK]
-				EXPORT  UART1_IRQHandler          [WEAK]
-				EXPORT  UART2_IRQHandler          [WEAK]
-				EXPORT  UART3_IRQHandler          [WEAK]
-				EXPORT  PWM1_IRQHandler           [WEAK]
-				EXPORT  I2C0_IRQHandler           [WEAK]
-				EXPORT  I2C1_IRQHandler           [WEAK]
-				EXPORT  I2C2_IRQHandler           [WEAK]
-				;EXPORT  SPIFI_IRQHandler          [WEAK]
-				EXPORT  SSP0_IRQHandler           [WEAK]
-				EXPORT  SSP1_IRQHandler           [WEAK]
-				EXPORT  PLL0_IRQHandler           [WEAK]
-				EXPORT  RTC_IRQHandler            [WEAK]
-				EXPORT  EINT0_IRQHandler          [WEAK]
-				EXPORT  EINT1_IRQHandler          [WEAK]
-				EXPORT  EINT2_IRQHandler          [WEAK]
-				EXPORT  EINT3_IRQHandler          [WEAK]
-				EXPORT  ADC_IRQHandler            [WEAK]
-				EXPORT  BOD_IRQHandler            [WEAK]
-				EXPORT  USB_IRQHandler            [WEAK]
-				EXPORT  CAN_IRQHandler            [WEAK]
-				EXPORT  DMA_IRQHandler            [WEAK]
-				EXPORT  I2S_IRQHandler            [WEAK]
-				EXPORT  ENET_IRQHandler           [WEAK]
-				EXPORT  MCI_IRQHandler            [WEAK]
-				EXPORT  MCPWM_IRQHandler          [WEAK]
-				EXPORT  QEI_IRQHandler            [WEAK]
-				EXPORT  PLL1_IRQHandler           [WEAK]
-				EXPORT  USBActivity_IRQHandler    [WEAK]
-				EXPORT  CANActivity_IRQHandler    [WEAK]
-				EXPORT  UART4_IRQHandler          [WEAK]
-				EXPORT  SSP2_IRQHandler           [WEAK]
-				EXPORT  LCD_IRQHandler            [WEAK]
-				EXPORT  GPIO_IRQHandler           [WEAK]
-				EXPORT  PWM0_IRQHandler           [WEAK]
-				EXPORT  EEPROM_IRQHandler         [WEAK]
-
-WDT_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-TIMER3_IRQHandler
-UART0_IRQHandler
-UART1_IRQHandler
-UART2_IRQHandler
-UART3_IRQHandler
-PWM1_IRQHandler
-I2C0_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-;SPIFI_IRQHandler	;not used            
-SSP0_IRQHandler
-SSP1_IRQHandler
-PLL0_IRQHandler
-RTC_IRQHandler
-EINT0_IRQHandler
-EINT1_IRQHandler
-EINT2_IRQHandler
-EINT3_IRQHandler
-ADC_IRQHandler
-BOD_IRQHandler
-USB_IRQHandler
-CAN_IRQHandler
-DMA_IRQHandler
-I2S_IRQHandler
-ENET_IRQHandler
-MCI_IRQHandler          
-MCPWM_IRQHandler
-QEI_IRQHandler
-PLL1_IRQHandler
-USBActivity_IRQHandler
-CANActivity_IRQHandler
-UART4_IRQHandler
-SSP2_IRQHandler
-LCD_IRQHandler
-GPIO_IRQHandler
-PWM0_IRQHandler
-EEPROM_IRQHandler
-					
-				B       .
-				
-				ENDP
-				
-				
-				ALIGN
-					
-
-; User Initial Stack & Heap
-				
-				IF      :DEF:__MICROLIB
-				
-				EXPORT  __initial_sp
-				EXPORT  __heap_base
-				EXPORT  __heap_limit
-				
-				ELSE
-				
-				IMPORT  __use_two_region_memory
-				EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-				LDR     R0, =  Heap_Mem
-				LDR     R1, =(Stack_Mem + Stack_Size)
-				LDR     R2, = (Heap_Mem +  Heap_Size)
-				LDR     R3, = Stack_Mem
-				BX      LR
-				
-				ALIGN
-				
-				ENDIF
-				
-				
-				END

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC177x_8x.s

@@ -1,279 +0,0 @@
-/*****************************************************************************/
-/* startup_LPC17xx.s: Startup file for LPC17xx device series                 */
-/*****************************************************************************/
-/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
-/*****************************************************************************/
-
-
-/*
-//*** <<< Use Configuration Wizard in Context Menu >>> ***
-*/
-
-
-/*
-// <h> Stack Configuration
-//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Stack_Size, 0x00000100
-    .section ".stack", "w"
-    .align  3
-    .globl  __cs3_stack_mem
-    .globl  __cs3_stack_size
-__cs3_stack_mem:
-    .if     Stack_Size
-    .space  Stack_Size
-    .endif
-    .size   __cs3_stack_mem,  . - __cs3_stack_mem
-    .set    __cs3_stack_size, . - __cs3_stack_mem
-
-
-/*
-// <h> Heap Configuration
-//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Heap_Size,  0x00001000
-
-    .section ".heap", "w"
-    .align  3
-    .globl  __cs3_heap_start
-    .globl  __cs3_heap_end
-__cs3_heap_start:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-__cs3_heap_end:
-
-
-/* Vector Table */
-
-    .section ".cs3.interrupt_vector"
-    .globl  __cs3_interrupt_vector_cortex_m
-    .type   __cs3_interrupt_vector_cortex_m, %object
-
-__cs3_interrupt_vector_cortex_m:
-    .long   __cs3_stack                 /* Top of Stack                 */
-    .long   __cs3_reset                 /* Reset Handler                */
-    .long   NMI_Handler                 /* NMI Handler                  */
-    .long   HardFault_Handler           /* Hard Fault Handler           */
-    .long   MemManage_Handler           /* MPU Fault Handler            */
-    .long   BusFault_Handler            /* Bus Fault Handler            */
-    .long   UsageFault_Handler          /* Usage Fault Handler          */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   SVC_Handler                 /* SVCall Handler               */
-    .long   DebugMon_Handler            /* Debug Monitor Handler        */
-    .long   0                           /* Reserved                     */
-    .long   PendSV_Handler              /* PendSV Handler               */
-    .long   SysTick_Handler             /* SysTick Handler              */
-
-    /* External Interrupts */
-    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
-    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
-    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
-    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
-    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
-    .long   UART0_IRQHandler            /* 21: UART0                        */
-    .long   UART1_IRQHandler            /* 22: UART1                        */
-    .long   UART2_IRQHandler            /* 23: UART2                        */
-    .long   UART3_IRQHandler            /* 24: UART3                        */
-    .long   PWM1_IRQHandler             /* 25: PWM1                         */
-    .long   I2C0_IRQHandler             /* 26: I2C0                         */
-    .long   I2C1_IRQHandler             /* 27: I2C1                         */
-    .long   I2C2_IRQHandler             /* 28: I2C2                         */
-    .long   0			        /* 29: Reserved, not for SPIFI anymore */
-    .long   SSP0_IRQHandler             /* 30: SSP0                         */
-    .long   SSP1_IRQHandler             /* 31: SSP1                         */
-    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
-    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
-    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
-    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
-    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
-    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
-    .long   ADC_IRQHandler              /* 38: A/D Converter                */
-    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
-    .long   USB_IRQHandler              /* 40: USB                          */
-    .long   CAN_IRQHandler              /* 41: CAN                          */
-    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
-    .long   I2S_IRQHandler              /* 43: I2S                          */
-    .long   ENET_IRQHandler             /* 44: Ethernet                     */
-    .long   MCI_IRQHandler              /* 45: SD/MMC Card					*/
-    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
-    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
-    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
-    .long	USBActivity_IRQHandler		/* 49: USB Activity 				*/
-    .long 	CANActivity_IRQHandler		/* 50: CAN Activity					*/
-    .long	UART4_IRQHandler            /* 51: UART4						*/
-    .long	SSP2_IRQHandler				/* 52: SSP2							*/
-    .long 	LCD_IRQHandler				/* 53: LCD							*/
-    .long	GPIO_IRQHandler				/* 54: GPIO							*/
-    .long 	PWM0_IRQHandler				/* 55: PWM0							*/
-    .long 	EEPROM_IRQHandler			/* 56: EEPROM						*/
-
-    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
-
-
-    .thumb
-
-	.section ".crp"
-	.globl  CRP_Value
-CRP_Value:
-	.long	0xFFFFFFFF
-
-/* Reset Handler */
-
-    .section .cs3.reset,"x",%progbits
-    .thumb_func
-    .globl  __cs3_reset_cortex_m
-    .type   __cs3_reset_cortex_m, %function
-__cs3_reset_cortex_m:
-    .fnstart
-.if (RAM_MODE)
-/* Clear .bss section (Zero init) */
-	MOV     R0, #0
-	LDR     R1, =__bss_start__
-	LDR     R2, =__bss_end__
-	CMP     R1,R2
-	BEQ     BSSIsEmpty
-LoopZI:
-	CMP     R1, R2
-	BHS		BSSIsEmpty
-	STR   	R0, [R1]
-	ADD		R1, #4
-	BLO     LoopZI
-BSSIsEmpty:
-    LDR     R0, =SystemInit
-    BLX     R0
-    LDR     R0,=main
-    BX      R0
-.else
-    LDR     R0, =SystemInit
-    BLX     R0
-	LDR     R0,=_start
-    BX      R0
-.endif
-    .pool
-    .cantunwind
-    .fnend
-    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
-
-    .section ".text"
-
-/* Exception Handlers */
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   MemManage_Handler
-    .type   MemManage_Handler, %function
-MemManage_Handler:
-    B       .
-    .size   MemManage_Handler, . - MemManage_Handler
-
-    .weak   BusFault_Handler
-    .type   BusFault_Handler, %function
-BusFault_Handler:
-    B       .
-    .size   BusFault_Handler, . - BusFault_Handler
-
-    .weak   UsageFault_Handler
-    .type   UsageFault_Handler, %function
-UsageFault_Handler:
-    B       .
-    .size   UsageFault_Handler, . - UsageFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   DebugMon_Handler
-    .type   DebugMon_Handler, %function
-DebugMon_Handler:
-    B       .
-    .size   DebugMon_Handler, . - DebugMon_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-
-/* IRQ Handlers */
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ     WDT_IRQHandler
-    IRQ     TIMER0_IRQHandler
-    IRQ     TIMER1_IRQHandler
-    IRQ     TIMER2_IRQHandler
-    IRQ     TIMER3_IRQHandler
-    IRQ     UART0_IRQHandler
-    IRQ     UART1_IRQHandler
-    IRQ     UART2_IRQHandler
-    IRQ     UART3_IRQHandler
-    IRQ     PWM1_IRQHandler
-    IRQ     I2C0_IRQHandler
-    IRQ     I2C1_IRQHandler
-    IRQ     I2C2_IRQHandler
-/*    IRQ		SPIFI_IRQHandler */
-    IRQ     SSP0_IRQHandler
-    IRQ     SSP1_IRQHandler
-    IRQ     PLL0_IRQHandler
-    IRQ     RTC_IRQHandler
-    IRQ     EINT0_IRQHandler
-    IRQ     EINT1_IRQHandler
-    IRQ     EINT2_IRQHandler
-    IRQ     EINT3_IRQHandler
-    IRQ     ADC_IRQHandler
-    IRQ     BOD_IRQHandler
-    IRQ     USB_IRQHandler
-    IRQ     CAN_IRQHandler
-    IRQ     DMA_IRQHandler
-    IRQ     I2S_IRQHandler
-    IRQ     ENET_IRQHandler
-    IRQ     MCI_IRQHandler
-    IRQ     MCPWM_IRQHandler
-    IRQ     QEI_IRQHandler
-    IRQ     PLL1_IRQHandler
-    IRQ		USBActivity_IRQHandler
-    IRQ		CANActivity_IRQHandler
-	IRQ		UART4_IRQHandler
-	IRQ		SSP2_IRQHandler
-	IRQ		LCD_IRQHandler
-	IRQ		GPIO_IRQHandler
-	IRQ		PWM0_IRQHandler
-	IRQ		EEPROM_IRQHandler
-
-    .end

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s

@@ -1,281 +0,0 @@
-/*****************************************************************************/
-/* startup_LPC17xx.s: Startup file for LPC17xx device series                 */
-/*****************************************************************************/
-/* Version: CodeSourcery Sourcery G++ Lite (with CS3)                        */
-/*****************************************************************************/
-
-
-/*
-//*** <<< Use Configuration Wizard in Context Menu >>> ***
-*/
-
-
-/*
-// <h> Stack Configuration
-//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Stack_Size, 0x00000100
-    .section ".stack", "w"
-    .align  3
-    .globl  __cs3_stack_mem
-    .globl  __cs3_stack_size
-__cs3_stack_mem:
-    .if     Stack_Size
-    .space  Stack_Size
-    .endif
-    .size   __cs3_stack_mem,  . - __cs3_stack_mem
-    .set    __cs3_stack_size, . - __cs3_stack_mem
-
-
-/*
-// <h> Heap Configuration
-//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-// </h>
-*/
-
-    .equ    Heap_Size,  0x00001000
-
-    .section ".heap", "w"
-    .align  3
-    .globl  __cs3_heap_start
-    .globl  __cs3_heap_end
-__cs3_heap_start:
-    .if     Heap_Size
-    .space  Heap_Size
-    .endif
-__cs3_heap_end:
-
-
-/* Vector Table */
-
-    .section ".cs3.interrupt_vector"
-    .globl  __cs3_interrupt_vector_cortex_m
-    .type   __cs3_interrupt_vector_cortex_m, %object
-
-__cs3_interrupt_vector_cortex_m:
-    .long   __cs3_stack                 /* Top of Stack                 */
-    .long   __cs3_reset                 /* Reset Handler                */
-    .long   NMI_Handler                 /* NMI Handler                  */
-    .long   HardFault_Handler           /* Hard Fault Handler           */
-    .long   MemManage_Handler           /* MPU Fault Handler            */
-    .long   BusFault_Handler            /* Bus Fault Handler            */
-    .long   UsageFault_Handler          /* Usage Fault Handler          */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   0                           /* Reserved                     */
-    .long   SVC_Handler                 /* SVCall Handler               */
-    .long   DebugMon_Handler            /* Debug Monitor Handler        */
-    .long   0                           /* Reserved                     */
-    .long   PendSV_Handler              /* PendSV Handler               */
-    .long   SysTick_Handler             /* SysTick Handler              */
-
-    /* External Interrupts */
-    .long   WDT_IRQHandler              /* 16: Watchdog Timer               */
-    .long   TIMER0_IRQHandler           /* 17: Timer0                       */
-    .long   TIMER1_IRQHandler           /* 18: Timer1                       */
-    .long   TIMER2_IRQHandler           /* 19: Timer2                       */
-    .long   TIMER3_IRQHandler           /* 20: Timer3                       */
-    .long   UART0_IRQHandler            /* 21: UART0                        */
-    .long   UART1_IRQHandler            /* 22: UART1                        */
-    .long   UART2_IRQHandler            /* 23: UART2                        */
-    .long   UART3_IRQHandler            /* 24: UART3                        */
-    .long   PWM1_IRQHandler             /* 25: PWM1                         */
-    .long   I2C0_IRQHandler             /* 26: I2C0                         */
-    .long   I2C1_IRQHandler             /* 27: I2C1                         */
-    .long   I2C2_IRQHandler             /* 28: I2C2                         */
-    .long   0			        /* 29: Reserved, not for SPIFI anymore */
-    .long   SSP0_IRQHandler             /* 30: SSP0                         */
-    .long   SSP1_IRQHandler             /* 31: SSP1                         */
-    .long   PLL0_IRQHandler             /* 32: PLL0 Lock (Main PLL)         */
-    .long   RTC_IRQHandler              /* 33: Real Time Clock              */
-    .long   EINT0_IRQHandler            /* 34: External Interrupt 0         */
-    .long   EINT1_IRQHandler            /* 35: External Interrupt 1         */
-    .long   EINT2_IRQHandler            /* 36: External Interrupt 2         */
-    .long   EINT3_IRQHandler            /* 37: External Interrupt 3         */
-    .long   ADC_IRQHandler              /* 38: A/D Converter                */
-    .long   BOD_IRQHandler              /* 39: Brown-Out Detect             */
-    .long   USB_IRQHandler              /* 40: USB                          */
-    .long   CAN_IRQHandler              /* 41: CAN                          */
-    .long   DMA_IRQHandler              /* 42: General Purpose DMA          */
-    .long   I2S_IRQHandler              /* 43: I2S                          */
-    .long   ENET_IRQHandler             /* 44: Ethernet                     */
-    .long   MCI_IRQHandler              /* 45: SD/MMC Card		    */
-    .long   MCPWM_IRQHandler            /* 46: Motor Control PWM            */
-    .long   QEI_IRQHandler              /* 47: Quadrature Encoder Interface */
-    .long   PLL1_IRQHandler             /* 48: PLL1 Lock (USB PLL)          */
-    .long   USBActivity_IRQHandler	/* 49: USB Activity 		    */
-    .long   CANActivity_IRQHandler	/* 50: CAN Activity		    */
-    .long   UART4_IRQHandler            /* 51: UART4			    */
-    .long   SSP2_IRQHandler		/* 52: SSP2			    */
-    .long   LCD_IRQHandler		/* 53: LCD			    */
-    .long   GPIO_IRQHandler		/* 54: GPIO			    */
-    .long   PWM0_IRQHandler		/* 55: PWM0			    */
-    .long   EEPROM_IRQHandler		/* 56: EEPROM			    */
-
-    .size   __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
-
-
-    .thumb
-
-	.section ".crp"
-	.globl  CRP_Value
-CRP_Value:
-	.long	0xFFFFFFFF
-
-/* Reset Handler */
-
-    .section .cs3.reset,"x",%progbits
-    .thumb_func
-    .globl  __cs3_reset_cortex_m
-    .globl  Reset_Handler
-    .type   __cs3_reset_cortex_m, %function
-__cs3_reset_cortex_m:
-Reset_Handler:
-    .fnstart
-.ifdef RAM_MODE
-/* Clear .bss section (Zero init) */
-    MOV     R0, #0
-    LDR     R1, =__bss_start__
-    LDR     R2, =__bss_end__
-    CMP     R1,R2
-    BEQ     BSSIsEmpty
-LoopZI:
-    CMP     R1, R2
-    BHS	    BSSIsEmpty
-    STR     R0, [R1]
-    ADD	    R1, #4
-    BLO     LoopZI
-BSSIsEmpty:
-    LDR     R0, =SystemInit
-    BLX     R0
-    LDR     R0,=main
-    BX      R0
-.else
-    LDR     R0, =SystemInit
-    BLX     R0
-    LDR     R0,=main
-    BX      R0
-.endif
-    .pool
-    .cantunwind
-    .fnend
-    .size   __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
-
-    .section ".text"
-
-/* Exception Handlers */
-
-    .weak   NMI_Handler
-    .type   NMI_Handler, %function
-NMI_Handler:
-    B       .
-    .size   NMI_Handler, . - NMI_Handler
-
-    .weak   HardFault_Handler
-    .type   HardFault_Handler, %function
-HardFault_Handler:
-    B       .
-    .size   HardFault_Handler, . - HardFault_Handler
-
-    .weak   MemManage_Handler
-    .type   MemManage_Handler, %function
-MemManage_Handler:
-    B       .
-    .size   MemManage_Handler, . - MemManage_Handler
-
-    .weak   BusFault_Handler
-    .type   BusFault_Handler, %function
-BusFault_Handler:
-    B       .
-    .size   BusFault_Handler, . - BusFault_Handler
-
-    .weak   UsageFault_Handler
-    .type   UsageFault_Handler, %function
-UsageFault_Handler:
-    B       .
-    .size   UsageFault_Handler, . - UsageFault_Handler
-
-    .weak   SVC_Handler
-    .type   SVC_Handler, %function
-SVC_Handler:
-    B       .
-    .size   SVC_Handler, . - SVC_Handler
-
-    .weak   DebugMon_Handler
-    .type   DebugMon_Handler, %function
-DebugMon_Handler:
-    B       .
-    .size   DebugMon_Handler, . - DebugMon_Handler
-
-    .weak   PendSV_Handler
-    .type   PendSV_Handler, %function
-PendSV_Handler:
-    B       .
-    .size   PendSV_Handler, . - PendSV_Handler
-
-    .weak   SysTick_Handler
-    .type   SysTick_Handler, %function
-SysTick_Handler:
-    B       .
-    .size   SysTick_Handler, . - SysTick_Handler
-
-
-/* IRQ Handlers */
-
-    .globl  Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    B       .
-    .size   Default_Handler, . - Default_Handler
-
-    .macro  IRQ handler
-    .weak   \handler
-    .set    \handler, Default_Handler
-    .endm
-
-    IRQ     WDT_IRQHandler
-    IRQ     TIMER0_IRQHandler
-    IRQ     TIMER1_IRQHandler
-    IRQ     TIMER2_IRQHandler
-    IRQ     TIMER3_IRQHandler
-    IRQ     UART0_IRQHandler
-    IRQ     UART1_IRQHandler
-    IRQ     UART2_IRQHandler
-    IRQ     UART3_IRQHandler
-    IRQ     PWM1_IRQHandler
-    IRQ     I2C0_IRQHandler
-    IRQ     I2C1_IRQHandler
-    IRQ     I2C2_IRQHandler
-/*    IRQ		SPIFI_IRQHandler */
-    IRQ     SSP0_IRQHandler
-    IRQ     SSP1_IRQHandler
-    IRQ     PLL0_IRQHandler
-    IRQ     RTC_IRQHandler
-    IRQ     EINT0_IRQHandler
-    IRQ     EINT1_IRQHandler
-    IRQ     EINT2_IRQHandler
-    IRQ     EINT3_IRQHandler
-    IRQ     ADC_IRQHandler
-    IRQ     BOD_IRQHandler
-    IRQ     USB_IRQHandler
-    IRQ     CAN_IRQHandler
-    IRQ     DMA_IRQHandler
-    IRQ     I2S_IRQHandler
-    IRQ     ENET_IRQHandler
-    IRQ     MCI_IRQHandler
-    IRQ     MCPWM_IRQHandler
-    IRQ     QEI_IRQHandler
-    IRQ     PLL1_IRQHandler
-    IRQ		USBActivity_IRQHandler
-    IRQ		CANActivity_IRQHandler
-	IRQ		UART4_IRQHandler
-	IRQ		SSP2_IRQHandler
-	IRQ		LCD_IRQHandler
-	IRQ		GPIO_IRQHandler
-	IRQ		PWM0_IRQHandler
-	IRQ		EEPROM_IRQHandler
-
-    .end

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC177x_8x.s

@@ -1,396 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC177x_8x.s
-; * @purpose: CMSIS Cortex-M3 Core Device Startup File
-; *           for the NXP LPC17xx Device Series
-; * @version: V1.03
-; * @date:    09. February 2010
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (C) 2010 ARM Limited. All rights reserved.
-; *
-; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; ******************************************************************************/
-
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-		DCD		WDT_IRQHandler            ; 16: Watchdog Timer
-		DCD		TIMER0_IRQHandler         ; 17: Timer0
-		DCD		TIMER1_IRQHandler         ; 18: Timer1
-		DCD		TIMER2_IRQHandler         ; 19: Timer2
-		DCD		TIMER3_IRQHandler         ; 20: Timer3
-		DCD		UART0_IRQHandler          ; 21: UART0
-		DCD		UART1_IRQHandler          ; 22: UART1
-		DCD		UART2_IRQHandler          ; 23: UART2
-		DCD		UART3_IRQHandler          ; 24: UART3
-		DCD		PWM1_IRQHandler           ; 25: PWM1
-		DCD		I2C0_IRQHandler           ; 26: I2C0
-		DCD		I2C1_IRQHandler           ; 27: I2C1
-		DCD		I2C2_IRQHandler           ; 28: I2C2
-		DCD		0		          ; 29: reserved; not for SPIFI anymore
-		DCD		SSP0_IRQHandler           ; 30: SSP0
-		DCD		SSP1_IRQHandler           ; 31: SSP1
-		DCD		PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-		DCD		RTC_IRQHandler            ; 33: Real Time Clock
-		DCD		EINT0_IRQHandler          ; 34: External Interrupt 0
-		DCD		EINT1_IRQHandler          ; 35: External Interrupt 1
-		DCD		EINT2_IRQHandler          ; 36: External Interrupt 2
-		DCD		EINT3_IRQHandler          ; 37: External Interrupt 3
-		DCD		ADC_IRQHandler            ; 38: A/D Converter
-		DCD		BOD_IRQHandler            ; 39: Brown-Out Detect
-		DCD		USB_IRQHandler            ; 40: USB
-		DCD		CAN_IRQHandler            ; 41: CAN
-		DCD		DMA_IRQHandler            ; 42: General Purpose DMA
-		DCD		I2S_IRQHandler            ; 43: I2S
-		DCD		ENET_IRQHandler           ; 44: Ethernet
-		DCD		MCI_IRQHandler		  ; 45: MCI Card
-		DCD		MCPWM_IRQHandler          ; 46: Motor Control PWM
-		DCD		QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-		DCD		PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-		DCD		USBActivity_IRQHandler	  ; 49: USB Activity Interrupt
-		DCD		CANActivity_IRQHandler	  ; 50: CAN Activity Interrupt
-		DCD		UART4_IRQHandler          ; 51: UART4
-		DCD		SSP2_IRQHandler		  ; 52: SSP2
-		DCD		LCD_IRQHandler		  ; 53: LCD
-		DCD		GPIO_IRQHandler		  ; 54: GPIO
-		DCD		PWM0_IRQHandler		  ; 55: PWM0
-		DCD		EEPROM_IRQHandler	  ; 56: EEPROM
-
-
-
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size 	EQU 	__Vectors_End - __Vectors
-
-                PUBLIC   CRP_Value
-		RSEG     CRPKEY : CODE(2)
-CRP_Value       
-                DCD  0xFFFFFFFF
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK TIMER0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER0_IRQHandler
-        B TIMER0_IRQHandler
-
-        PUBWEAK TIMER1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER1_IRQHandler
-        B TIMER1_IRQHandler
-
-        PUBWEAK TIMER2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER2_IRQHandler
-        B TIMER2_IRQHandler
-
-        PUBWEAK TIMER3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-TIMER3_IRQHandler
-        B TIMER3_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK PWM1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PWM1_IRQHandler
-        B PWM1_IRQHandler
-
-        PUBWEAK I2C0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C0_IRQHandler
-        B I2C0_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-        ;PUBWEAK SPIFI_IRQHandler
-        ;SECTION .text:CODE:REORDER(1)
-;SPIFI_IRQHandler
-        ;B SPIFI_IRQHandler
-
-        PUBWEAK SSP0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP0_IRQHandler
-        B SSP0_IRQHandler
-
-        PUBWEAK SSP1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP1_IRQHandler
-        B SSP1_IRQHandler
-
-        PUBWEAK PLL0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL0_IRQHandler
-        B PLL0_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK EINT0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT0_IRQHandler
-        B EINT0_IRQHandler
-
-        PUBWEAK EINT1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT1_IRQHandler
-        B EINT1_IRQHandler
-
-        PUBWEAK EINT2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT2_IRQHandler
-        B EINT2_IRQHandler
-
-        PUBWEAK EINT3_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EINT3_IRQHandler
-        B EINT3_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK BOD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-BOD_IRQHandler
-        B BOD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK DMA_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-DMA_IRQHandler
-        B DMA_IRQHandler
-
-        PUBWEAK I2S_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-I2S_IRQHandler
-        B I2S_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK MCI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-MCI_IRQHandler
-        B MCI_IRQHandler
-
-        PUBWEAK MCPWM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-MCPWM_IRQHandler
-        B MCPWM_IRQHandler
-
-        PUBWEAK QEI_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-QEI_IRQHandler
-        B QEI_IRQHandler
-
-        PUBWEAK PLL1_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PLL1_IRQHandler
-        B PLL1_IRQHandler
-
-        PUBWEAK USBActivity_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-USBActivity_IRQHandler
-        B USBActivity_IRQHandler
-
-        PUBWEAK CANActivity_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-CANActivity_IRQHandler
-        B CANActivity_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK SSP2_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-SSP2_IRQHandler
-        B SSP2_IRQHandler
-
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK GPIO_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-GPIO_IRQHandler
-        B GPIO_IRQHandler
-
-        PUBWEAK PWM0_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-PWM0_IRQHandler
-        B PWM0_IRQHandler
-
-		PUBWEAK EEPROM_IRQHandler
-        SECTION .text:CODE:REORDER(1)
-EEPROM_IRQHandler
-        B EEPROM_IRQHandler
-
-        END

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s

@@ -1,419 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_LPC407x_8x.s
-; * @purpose: CMSIS Cortex-M4 Core Device Startup File
-; *           for the NXP LPC40xx Device Series
-; * @version: V1.00
-; * @date:    September 2012
-; *----------------------------------------------------------------------------
-; *
-; * Copyright (C) 2010 ARM Limited. All rights reserved.
-; *
-; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
-; * processor based microcontrollers.  This file can be freely distributed
-; * within development tools that are supporting such ARM based processors.
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; ******************************************************************************/
-
-
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-        PUBLIC  __vector_table_0x1c
-        PUBLIC  __Vectors
-        PUBLIC  __Vectors_End
-        PUBLIC  __Vectors_Size
-
-        DATA
-
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler
-
-        DCD     NMI_Handler
-        DCD     HardFault_Handler
-        DCD     MemManage_Handler
-        DCD     BusFault_Handler
-        DCD     UsageFault_Handler
-__vector_table_0x1c
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     0
-        DCD     SVC_Handler
-        DCD     DebugMon_Handler
-        DCD     0
-        DCD     PendSV_Handler
-        DCD     SysTick_Handler
-
-        ; External Interrupts
-        DCD     WDT_IRQHandler            ; 16: Watchdog Timer
-        DCD     TIMER0_IRQHandler         ; 17: Timer0
-        DCD     TIMER1_IRQHandler         ; 18: Timer1
-        DCD     TIMER2_IRQHandler         ; 19: Timer2
-        DCD     TIMER3_IRQHandler         ; 20: Timer3
-        DCD     UART0_IRQHandler          ; 21: UART0
-        DCD     UART1_IRQHandler          ; 22: UART1
-        DCD     UART2_IRQHandler          ; 23: UART2
-        DCD     UART3_IRQHandler          ; 24: UART3
-        DCD     PWM1_IRQHandler           ; 25: PWM1
-        DCD     I2C0_IRQHandler           ; 26: I2C0
-        DCD     I2C1_IRQHandler           ; 27: I2C1
-        DCD     I2C2_IRQHandler           ; 28: I2C2
-        DCD     0                         ; 29: Reserved
-        DCD     SSP0_IRQHandler           ; 30: SSP0
-        DCD     SSP1_IRQHandler           ; 31: SSP1
-        DCD     PLL0_IRQHandler           ; 32: PLL0 Lock (Main PLL)
-        DCD     RTC_IRQHandler            ; 33: Real Time Clock
-        DCD     EINT0_IRQHandler          ; 34: External Interrupt 0
-        DCD     EINT1_IRQHandler          ; 35: External Interrupt 1
-        DCD     EINT2_IRQHandler          ; 36: External Interrupt 2
-        DCD     EINT3_IRQHandler          ; 37: External Interrupt 3
-        DCD     ADC_IRQHandler            ; 38: A/D Converter
-        DCD     BOD_IRQHandler            ; 39: Brown-Out Detect
-        DCD     USB_IRQHandler            ; 40: USB
-        DCD     CAN_IRQHandler            ; 41: CAN
-        DCD     DMA_IRQHandler            ; 42: General Purpose DMA
-        DCD     I2S_IRQHandler            ; 43: I2S
-        DCD     ENET_IRQHandler           ; 44: Ethernet
-        DCD		MCI_IRQHandler		  	  ; 45: MCI Card
-        DCD     MCPWM_IRQHandler          ; 46: Motor Control PWM
-        DCD     QEI_IRQHandler            ; 47: Quadrature Encoder Interface
-        DCD     PLL1_IRQHandler           ; 48: PLL1 Lock (USB PLL)
-        DCD		  USBActivity_IRQHandler  ; 49: USB Activity Interrupt
-        DCD		  CANActivity_IRQHandler  ; 50: CAN Activity Interrupt
-        DCD		  UART4_IRQHandler        ; 51: UART4
-        DCD		  SSP2_IRQHandler		  ; 52: SSP2
-        DCD		  LCD_IRQHandler		  ; 53: LCD
-        DCD		  GPIO_IRQHandler		  ; 54: GPIO
-        DCD		  PWM0_IRQHandler		  ; 55: PWM0
-        DCD		  EEPROM_IRQHandler	  	  ; 56: EEPROM
-
-
-__Vectors_End
-
-__Vectors       EQU   __vector_table
-__Vectors_Size 	EQU 	__Vectors_End - __Vectors
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WDT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WDT_IRQHandler
-        B WDT_IRQHandler
-
-        PUBWEAK TIMER0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER0_IRQHandler
-        B TIMER0_IRQHandler
-
-        PUBWEAK TIMER1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER1_IRQHandler
-        B TIMER1_IRQHandler
-
-        PUBWEAK TIMER2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER2_IRQHandler
-        B TIMER2_IRQHandler
-
-        PUBWEAK TIMER3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIMER3_IRQHandler
-        B TIMER3_IRQHandler
-
-        PUBWEAK UART0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART0_IRQHandler
-        B UART0_IRQHandler
-
-        PUBWEAK UART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART1_IRQHandler
-        B UART1_IRQHandler
-
-        PUBWEAK UART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART2_IRQHandler
-        B UART2_IRQHandler
-
-        PUBWEAK UART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART3_IRQHandler
-        B UART3_IRQHandler
-
-        PUBWEAK PWM1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PWM1_IRQHandler
-        B PWM1_IRQHandler
-
-        PUBWEAK I2C0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C0_IRQHandler
-        B I2C0_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-;        PUBWEAK SPIFI_IRQHandler
-;        SECTION .text:CODE:REORDER:NOROOT(1)
-;SPIFI_IRQHandler
-;        B SPIFI_IRQHandler
-
-        PUBWEAK SSP0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SSP0_IRQHandler
-        B SSP0_IRQHandler
-
-        PUBWEAK SSP1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SSP1_IRQHandler
-        B SSP1_IRQHandler
-
-        PUBWEAK PLL0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PLL0_IRQHandler
-        B PLL0_IRQHandler
-
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-
-        PUBWEAK EINT0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EINT0_IRQHandler
-        B EINT0_IRQHandler
-
-        PUBWEAK EINT1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EINT1_IRQHandler
-        B EINT1_IRQHandler
-
-        PUBWEAK EINT2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EINT2_IRQHandler
-        B EINT2_IRQHandler
-
-        PUBWEAK EINT3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EINT3_IRQHandler
-        B EINT3_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK BOD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BOD_IRQHandler
-        B BOD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_IRQHandler
-        B USB_IRQHandler
-
-        PUBWEAK CAN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN_IRQHandler
-        B CAN_IRQHandler
-
-        PUBWEAK DMA_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA_IRQHandler
-        B DMA_IRQHandler
-
-        PUBWEAK I2S_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2S_IRQHandler
-        B I2S_IRQHandler
-
-        PUBWEAK ENET_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ENET_IRQHandler
-        B ENET_IRQHandler
-
-        PUBWEAK MCI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCI_IRQHandler
-        B MCI_IRQHandler
-
-        PUBWEAK MCPWM_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MCPWM_IRQHandler
-        B MCPWM_IRQHandler
-
-        PUBWEAK QEI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-QEI_IRQHandler
-        B QEI_IRQHandler
-
-        PUBWEAK PLL1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PLL1_IRQHandler
-        B PLL1_IRQHandler
-
-        PUBWEAK USBActivity_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USBActivity_IRQHandler
-        B USBActivity_IRQHandler
-
-        PUBWEAK CANActivity_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CANActivity_IRQHandler
-        B CANActivity_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-
-        PUBWEAK SSP2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SSP2_IRQHandler
-        B SSP2_IRQHandler
-
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK GPIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-GPIO_IRQHandler
-        B GPIO_IRQHandler
-
-        PUBWEAK PWM0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PWM0_IRQHandler
-        B PWM0_IRQHandler
-
-		PUBWEAK EEPROM_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EEPROM_IRQHandler
-        B EEPROM_IRQHandler
-
-#ifndef SRAM
-        SECTION .crp:CODE:ROOT(2)
-        DATA
-
-/* Code Read Protection
-CRP1    0x12345678 - Write to RAM command can not access RAM below 0x10000200.
-                   - Read Memory command: disabled.
-                   - Copy RAM to Flash command: cannot write to Sector 0.
-                   - "Go" command: disabled.
-                   - Erase sector(s) command: can erase any individual sector except 
-                   	 sector 0 only, or can erase all sectors at once.
-                   - Compare command: disabled
-CRP2    0x87654321 - Write to RAM command: disabled.
-                   - Copy RAM to Flash: disabled.
-                   - Erase command: only allows erase of all sectors.
-CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
-                     by pulling PIO0_1 LOW is disabled if a valid user code is
-                     present in flash sector 0.
-Caution: If CRP3 is selected, no future factory testing can be
-performed on the device.
-*/
-
-#ifndef CRP
-  #define CRP 0xFFFFFFFF
-#endif
-
-	DCD	CRP
-#endif
-        END

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC177x_8x.c

@@ -1,507 +0,0 @@
-/**********************************************************************
-* $Id$		system_LPC177x_8x.c			2011-06-02
-*//**
-* @file		system_LPC177x_8x.c
-* @brief	CMSIS Cortex-M3 Device Peripheral Access Layer Source File
-*          	for the NXP LPC177x_8x Device Series
-*
-*			ARM Limited (ARM) is supplying this software for use with 
-*			Cortex-M processor based microcontrollers.  This file can be 
-*			freely distributed within development tools that are supporting 
-*			such ARM based processors.
-*
-* @version	1.0
-* @date		02. June. 2011
-* @author	NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#include <stdint.h>
-#include "LPC177x_8x.h"
-#include "system_LPC177x_8x.h"
-
-#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-/*--------------------- Clock Configuration ----------------------------------
-//
-//	<e>	Clock Configuration
-//		<h>	System Controls and Status Register (SCS - address 0x400F C1A0)
-//			<o1.0>	EMC Shift Control Bit
-//					<i>		Controls how addresses are output on the EMC address pins for static memories
-//					<0=>	Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
-//					<1=>	Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
-//
-//			<o1.1>	EMC Reset Disable Bit
-//					<i>		If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
-//					<i>		If 1, EMC is still retained its state through a warm reset
-//					<0=>	Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
-//					<1=>	Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
-//
-//			<o1.2>	EMC Burst Control
-//					<i>		Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
-//					<0=>	Burst enabled (Bit 2 is 0)
-//					<1=>	Bust disbled (Bit 2 is 1)
-//
-//			<o1.3>	MCIPWR Active Level
-//					<i>		Selects the active level for the SD card interface signal SD_PWR
-//					<0=>	SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
-//					<1=>	SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
-//
-//			<o1.4>	Main Oscillator Range Select
-//					<0=>	In Range 1 MHz to 20 MHz (Bit 4 is 0)
-//					<1=>	In Range 15 MHz to 25 MHz (Bit 4 is 1)
-//
-//			<o1.5>	Main Oscillator enable
-//					<i>		0 (zero) means disabled, 1 means enable
-//
-//			<o1.6>	Main Oscillator status (Read-Only)
-//		</h>
-//
-//		<h>	Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
-//			<o2.0>	CLKSRC: Select the clock source for sysclk to PLL0 clock
-//					<0=>	Internal RC oscillator (Bit 0 is 0)
-//					<1=>	Main oscillator (Bit 0 is 1)
-//		</h>
-//
-//		<e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
-//			<i>			F_in  is in the range of 1 MHz to 25 MHz
-//			<i>			F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
-//			<i>			PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
-//
-//			<o4.0..4>   MSEL: PLL Multiplier Value
-//						<i>				M Value
-//						<1-32><#-1>
-//
-//			<o4.5..6>	PSEL: PLL Divider Value
-//						<i>				P Value
-//						<0=> 			1
-//						<1=>			2
-//						<2=>			4
-//						<3=>			8
-//		</e>
-//
-//		<e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
-//			<i>			F_in  is in the range of 1 MHz to 25 MHz
-//			<i>			F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
-//			<i>			PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
-//
-//			<o6.0..4>   MSEL: PLL Multiplier Value
-//						<i>				M Value
-//						<1-32><#-1>
-//
-//			<o6.5..6>	PSEL: PLL Divider Value
-//						<i>		P Value
-//						<0=>	1
-//						<1=>	2
-//						<2=>	4
-//						<3=>	8
-//		</e>
-//
-//		<h>	CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
-//			<o7.0..4>	CCLKDIV: Select the value for divider of CPU clock (CCLK)
-//						<i>		0: The divider is turned off. No clock will be provided to the CPU
-//						<i>		n: The input clock is divided by n to produce the CPU clock
-//						<0-31>
-//
-//			<o7.8>		CCLKSEL: Select the input to the divider of CPU clock
-//						<0=>	sysclk clock is used
-//						<1=>	Main PLL0 clock is used
-//		</h>
-//
-//		<h>	USB Clock Selection Register (USBCLKSEL - 0x400F C108)
-//			<o8.0..4>	USBDIV: USB clock (source PLL0) divider selection
-//						<0=>	Divider is off and no clock provides to USB subsystem
-//						<4=>	Divider value is 4 (The source clock is divided by 4)
-//						<6=>	Divider value is 6 (The source clock is divided by 6)
-//
-//			<o8.8..9>	USBSEL: Select the source for USB clock divider
-//						<i>		When CPU clock is selected, the USB can be accessed
-//						<i>		by software but cannot perform USB functions
-//						<0=>	sysclk clock (the clock input to PLL0)
-//						<1=>	The clock output from PLL0
-//						<2=>	The clock output from PLL1
-//		</h>
-//
-//		<h>	EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
-//			<o9.0>	EMCDIV: Set the divider for EMC clock
-//					<0=> Divider value is 1
-//					<1=> Divider value is 2 (EMC clock is equal a half of input clock)
-//		</h>
-//
-//		<h>	Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
-//			<o10.0..4>	PCLKDIV: APB Peripheral clock divider
-//						<i>	0: The divider is turned off. No clock will be provided to APB peripherals
-//						<i>	n: The input clock is divided by n to produce the APB peripheral clock
-//						<0-31>
-//		</h>
-//
-//		<h>	Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
-//			<o11.0>		PCLCD: LCD controller power/clock enable (bit 0)
-//			<o11.1>		PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
-//			<o11.2>		PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
-//			<o11.3>		PCUART0: UART 0 power/clock enable (bit 3)
-//			<o11.4>		PCUART1: UART 1 power/clock enable (bit 4)
-//			<o11.5>		PCPWM0: PWM0 power/clock enable (bit 5)
-//			<o11.6>		PCPWM1: PWM1 power/clock enable (bit 6)
-//			<o11.7>		PCI2C0: I2C 0 interface power/clock enable (bit 7)
-//			<o11.8>		PCUART4: UART 4 power/clock enable (bit 8)
-//			<o11.9>		PCRTC: RTC and Event Recorder power/clock enable (bit 9)
-//			<o11.10>	PCSSP1: SSP 1 interface power/clock enable (bit 10)
-//			<o11.11>	PCEMC: External Memory Controller power/clock enable (bit 11)
-//			<o11.12>	PCADC: A/D converter power/clock enable (bit 12)
-//			<o11.13>	PCCAN1: CAN controller 1 power/clock enable (bit 13)
-//			<o11.14>	PCCAN2: CAN controller 2 power/clock enable (bit 14)
-//			<o11.15>	PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
-//			<o11.17>	PCMCPWM: Motor Control PWM power/clock enable (bit 17)
-//			<o11.18>	PCQEI: Quadrature encoder interface power/clock enable (bit 18)
-//			<o11.19>	PCI2C1: I2C 1 interface power/clock enable (bit 19)
-//			<o11.20>	PCSSP2: SSP 2 interface power/clock enable (bit 20)
-//			<o11.21>	PCSSP0: SSP 0 interface power/clock enable (bit 21)
-//			<o11.22>	PCTIM2: Timer 2 power/clock enable (bit 22)
-//			<o11.23>	PCTIM3: Timer 3 power/clock enable (bit 23)
-//			<o11.24>	PCUART2: UART 2 power/clock enable (bit 24)
-//			<o11.25>	PCUART3: UART 3 power/clock enable (bit 25)
-//			<o11.26>	PCI2C2: I2C 2 interface power/clock enable (bit 26)
-//			<o11.27>	PCI2S: I2S interface power/clock enable (bit 27)
-//			<o11.28>	PCSDC: SD Card interface power/clock enable (bit 28)
-//			<o11.29>	PCGPDMA: GPDMA function power/clock enable (bit 29)
-//			<o11.30>	PCENET: Ethernet block power/clock enable (bit 30)
-//			<o11.31>	PCUSB: USB interface power/clock enable (bit 31)
-//		</h>
-//
-//		<h>	Clock Output Configuration Register (CLKOUTCFG)
-//			<o12.0..3>	CLKOUTSEL: Clock Source for CLKOUT Selection
-//						<0=>	CPU clock
-//						<1=>	Main Oscillator
-//						<2=>	Internal RC Oscillator
-//						<3=>	USB clock
-//						<4=>	RTC Oscillator
-//						<5=>	unused
-//						<6=>	Watchdog Oscillator
-//
-//			<o12.4..7>	CLKOUTDIV: Output Clock Divider
-//						<1-16><#-1>
-//
-//			<o12.8>		CLKOUT_EN: CLKOUT enable
-//		</h>
-//
-//	</e>
-*/
-
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000021
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x00000009
-#define PLL1_SETUP            1
-#define PLL1CFG_Val           0x00000023
-#define CCLKSEL_Val           0x00000101
-#define USBCLKSEL_Val         0x00000201
-#define EMCCLKSEL_Val         0x00000001
-#define PCLKSEL_Val           0x00000002
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000100
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-//	<e>	Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
-//		<o1.12..15>	FLASHTIM: Flash Access Time
-//					<0=>	1 CPU clock (for CPU clock up to 20 MHz)
-//					<1=>	2 CPU clocks (for CPU clock up to 40 MHz)
-//					<2=>	3 CPU clocks (for CPU clock up to 60 MHz)
-//					<3=>	4 CPU clocks (for CPU clock up to 80 MHz)
-//					<4=>	5 CPU clocks (for CPU clock up to 100 MHz)
-//					<5=>	6 CPU clocks (for any CPU clock)
-//	</e>
-*/
-
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x00005000
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x0000003F))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))
-   #error "CCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
-   #error "USBCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
-   #error "EMCCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
-   #error "PCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
-   #warning "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-/* pll_out_clk = F_cco / (2 × P)
-   F_cco = pll_in_clk × M × 2 × P */
-#define __M                   ((PLL0CFG_Val & 0x1F) + 1)
-#define __PLL0_CLK(__F_IN)    (__F_IN * __M)
-#define __CCLK_DIV            (CCLKSEL_Val & 0x1F)
-#define __PCLK_DIV			  (PCLKSEL_Val & 0x1F)
-#define __ECLK_DIV			  ((EMCCLKSEL_Val & 0x01) + 1)
-
-/* Determine core clock frequency according to settings */
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-
-  #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
-   #error "Main Oscillator is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
-   #error "Main PLL is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
-		#define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
-        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
-    #endif
-  #else                                 /* cclk = pll_clk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
-		#define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
-    #endif
-  #endif
-
-#else
-        #define __CORE_CLK (IRC_OSC)
-        #define __PER_CLK  (IRC_OSC)
-        #define __EMC_CLK  (__CORE_CLK)
-#endif
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */
-uint32_t EMCClock		 = __EMC_CLK; /*!< EMC Clock Frequency 				  */
-uint32_t USBClock 		 = (48000000UL);		  /*!< USB Clock Frequency - this value will
-									be updated after call SystemCoreClockUpdate, should be 48MHz*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */
-    if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-		  SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-    }
-    else {                                        /* sysclk = osc_clk */
-      if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock        = 0;
-      }
-      else {
-          SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));	  	
-          EMCClock        = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-      }
-    }
-  }
-  else {                                          /* cclk = pll_clk */
-    if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-    }
-    else {
-      if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-          uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-          uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
-          uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
-          uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
-          SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
-          PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
-          EMCClock        = SystemCoreClock / emc_div;
-      }
-      else {                                        /* sysclk = osc_clk */
-        if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-        }
-        else {
-          uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-          uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
-          uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
-		  uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
-          SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
-          PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
-          EMCClock        = SystemCoreClock / emc_div;
-        }
-      }
-    }
-  }
-  /* ---update USBClock------------------*/
-  if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
-  {
-	  switch (LPC_SC->USBCLKSEL & 0x1F)
-	  {
-	  case 0:
-		  USBClock = 0; //no clock will be provided to the USB subsystem
-		  break;
-	  case 4:
-	  case 6:
-            {
-                 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-                 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
-		  if(LPC_SC->CLKSRCSEL & 0x01)	//pll_clk_in = main_osc
-			  USBClock = OSC_CLK * mul / usb_div;
-		  else //pll_clk_in = irc_clk
-			  USBClock = IRC_OSC * mul / usb_div;
-            }
-            break;
-	  default:
-		  USBClock = 0;  /* this should never happen! */
-	  }
-  }
-  else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
-  {
-	  if(LPC_SC->CLKSRCSEL & 0x01)	//pll1_clk_in = main_osc
-	  		USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
-	  else //pll1_clk_in = irc_clk
-	  		USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
-  }
-  else
-	  USBClock = 0; /* this should never happen! */
-}
-
-  /* Determine clock frequency according to clock register values             */
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/
-
-#if (PLL0_SETUP)
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-#endif
-
-  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
-  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
-  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
-  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-  LPC_SC->PBOOST 	|= 0x03;			/* Power Boost control				*/
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
-#endif
-#ifdef  __RAM_MODE__
-  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
-#else
-  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
-#endif
-  SystemCoreClockUpdate(); 
-}

bsp/nxp/lpc/lpc408x/Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c

@@ -1,571 +0,0 @@
-/**********************************************************************
-* $Id$		system_LPC407x_8x_177x_8x.c			2012-01-16
-*//**
-* @file		system_LPC407x_8x_177x_8x.c
-* @brief	CMSIS Cortex-M3, M4 Device Peripheral Access Layer Source File
-*          	for the NXP LPC407x_8x_177x_8x Device Series
-*
-*			ARM Limited (ARM) is supplying this software for use with
-*			Cortex-M processor based microcontrollers.  This file can be
-*			freely distributed within development tools that are supporting
-*			such ARM based processors.
-*
-* @version	1.2
-* @date		20. June. 2012
-* @author	NXP MCU SW Application Team
-*
-* Copyright(C) 2012, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#include <stdint.h>
-#include "LPC407x_8x_177x_8x.h"
-#include "system_LPC407x_8x_177x_8x.h"
-
-#define __CLK_DIV(x,y) (((y) == 0) ? 0: (x)/(y))
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-/*--------------------- Clock Configuration ----------------------------------
-//
-//	<e>	Clock Configuration
-//		<h>	System Controls and Status Register (SCS - address 0x400F C1A0)
-//			<o1.0>	EMC Shift Control Bit
-//					<i>		Controls how addresses are output on the EMC address pins for static memories
-//					<0=>	Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit (Bit 0 is 0)
-//					<1=>	Static CS addresses start at LSB 0 regardless of memory width (Bit 0 is 1)
-//
-//			<o1.1>	EMC Reset Disable Bit
-//					<i>		If 0 (zero), all registers and functions of the EMC are initialized upon any reset condition
-//					<i>		If 1, EMC is still retained its state through a warm reset
-//					<0=>	Both EMC resets are asserted when any type of chip reset event occurs (Bit 1 is 0)
-//					<1=>	Portions of EMC will only be reset by POR or BOR event (Bit 1 is 1)
-//
-//			<o1.2>	EMC Burst Control
-//					<i>		Set to 1 to prevent multiple sequential accesses to memory via EMC static memory chip selects
-//					<0=>	Burst enabled (Bit 2 is 0)
-//					<1=>	Bust disbled (Bit 2 is 1)
-//
-//			<o1.3>	MCIPWR Active Level
-//					<i>		Selects the active level for the SD card interface signal SD_PWR
-//					<0=>	SD_PWR is active low (inverted output of the SD Card interface block) (Bit 3 is 0)
-//					<1=>	SD_PWR is active high (follows the output of the SD Card interface block) (Bit 3 is 1)
-//
-//			<o1.4>	Main Oscillator Range Select
-//					<0=>	In Range 1 MHz to 20 MHz (Bit 4 is 0)
-//					<1=>	In Range 15 MHz to 25 MHz (Bit 4 is 1)
-//
-//			<o1.5>	Main Oscillator enable
-//					<i>		0 (zero) means disabled, 1 means enable
-//
-//			<o1.6>	Main Oscillator status (Read-Only)
-//		</h>
-//
-//		<h>	Clock Source Select Register (CLKSRCSEL - address 0x400F C10C)
-//			<o2.0>	CLKSRC: Select the clock source for sysclk to PLL0 clock
-//					<0=>	Internal RC oscillator (Bit 0 is 0)
-//					<1=>	Main oscillator (Bit 0 is 1)
-//		</h>
-//
-//		<e3>PLL0 Configuration (Main PLL PLL0CFG - address 0x400F C084)
-//			<i>			F_in  is in the range of 1 MHz to 25 MHz
-//			<i>			F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
-//			<i>			PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
-//
-//			<o4.0..4>   MSEL: PLL Multiplier Value
-//						<i>				M Value
-//						<1-32><#-1>
-//
-//			<o4.5..6>	PSEL: PLL Divider Value
-//						<i>				P Value
-//						<0=> 			1
-//						<1=>			2
-//						<2=>			4
-//						<3=>			8
-//		</e>
-//
-//		<e5>PLL1 Configuration (Alt PLL PLL1CFG - address 0x400F C0A4)
-//			<i>			F_in  is in the range of 1 MHz to 25 MHz
-//			<i>			F_cco = (F_in * M * 2 * P) is in range of 156 MHz to 320 MHz
-//			<i>			PLL out clock = (F_cco / (2 * P)) is in rane of 9.75 MHz to 160 MHz
-//
-//			<o6.0..4>   MSEL: PLL Multiplier Value
-//						<i>				M Value
-//						<1-32><#-1>
-//
-//			<o6.5..6>	PSEL: PLL Divider Value
-//						<i>		P Value
-//						<0=>	1
-//						<1=>	2
-//						<2=>	4
-//						<3=>	8
-//		</e>
-//
-//		<h>	CPU Clock Selection Register (CCLKSEL - address 0x400F C104)
-//			<o7.0..4>	CCLKDIV: Select the value for divider of CPU clock (CCLK)
-//						<i>		0: The divider is turned off. No clock will be provided to the CPU
-//						<i>		n: The input clock is divided by n to produce the CPU clock
-//						<0-31>
-//
-//			<o7.8>		CCLKSEL: Select the input to the divider of CPU clock
-//						<0=>	sysclk clock is used
-//						<1=>	Main PLL0 clock is used
-//		</h>
-//
-//		<h>	USB Clock Selection Register (USBCLKSEL - 0x400F C108)
-//			<o8.0..4>	USBDIV: USB clock (source PLL0) divider selection
-//						<0=>	Divider is off and no clock provides to USB subsystem
-//						<4=>	Divider value is 4 (The source clock is divided by 4)
-//						<6=>	Divider value is 6 (The source clock is divided by 6)
-//
-//			<o8.8..9>	USBSEL: Select the source for USB clock divider
-//						<i>		When CPU clock is selected, the USB can be accessed
-//						<i>		by software but cannot perform USB functions
-//						<0=>	sysclk clock (the clock input to PLL0)
-//						<1=>	The clock output from PLL0
-//						<2=>	The clock output from PLL1
-//		</h>
-//
-//		<h>	EMC Clock Selection Register (EMCCLKSEL - address 0x400F C100)
-//			<o9.0>	EMCDIV: Set the divider for EMC clock
-//					<0=> Divider value is 1
-//					<1=> Divider value is 2 (EMC clock is equal a half of input clock)
-//		</h>
-//
-//		<h>	Peripheral Clock Selection Register (PCLKSEL - address 0x400F C1A8)
-//			<o10.0..4>	PCLKDIV: APB Peripheral clock divider
-//						<i>	0: The divider is turned off. No clock will be provided to APB peripherals
-//						<i>	n: The input clock is divided by n to produce the APB peripheral clock
-//						<0-31>
-//		</h>
-//
-//		<h>	SPIFI Clock Selection Register (SPIFICLKSEL - address 0x400F C1B4)
-//			<o11.0..4>	SPIFIDIV: Set the divider for SPIFI clock
-//						<i>	0: The divider is turned off. No clock will be provided to the SPIFI
-//						<i>	n: The input clock is divided by n to produce the SPIFI clock
-//						<0-31>
-//
-//			<o11.8..9>	SPIFISEL: Select the input clock for SPIFI clock divider
-//						<0=>	sysclk clock (the clock input to PLL0)
-//						<1=>	The clock output from PLL0
-//						<2=>	The clock output from PLL1
-//		</h>
-//
-//		<h>	Power Control for Peripherals Register (PCONP - address 0x400F C1C8)
-//			<o12.0>		PCLCD: LCD controller power/clock enable (bit 0)
-//			<o12.1>		PCTIM0: Timer/Counter 0 power/clock enable (bit 1)
-//			<o12.2>		PCTIM1: Timer/Counter 1 power/clock enable (bit 2)
-//			<o12.3>		PCUART0: UART 0 power/clock enable (bit 3)
-//			<o12.4>		PCUART1: UART 1 power/clock enable (bit 4)
-//			<o12.5>		PCPWM0: PWM0 power/clock enable (bit 5)
-//			<o12.6>		PCPWM1: PWM1 power/clock enable (bit 6)
-//			<o12.7>		PCI2C0: I2C 0 interface power/clock enable (bit 7)
-//			<o12.8>		PCUART4: UART 4 power/clock enable (bit 8)
-//			<o12.9>		PCRTC: RTC and Event Recorder power/clock enable (bit 9)
-//			<o12.10>	PCSSP1: SSP 1 interface power/clock enable (bit 10)
-//			<o12.11>	PCEMC: External Memory Controller power/clock enable (bit 11)
-//			<o12.12>	PCADC: A/D converter power/clock enable (bit 12)
-//			<o12.13>	PCCAN1: CAN controller 1 power/clock enable (bit 13)
-//			<o12.14>	PCCAN2: CAN controller 2 power/clock enable (bit 14)
-//			<o12.15>	PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable (bit 15)
-//			<o12.17>	PCMCPWM: Motor Control PWM power/clock enable (bit 17)
-//			<o12.18>	PCQEI: Quadrature encoder interface power/clock enable (bit 18)
-//			<o12.19>	PCI2C1: I2C 1 interface power/clock enable (bit 19)
-//			<o12.20>	PCSSP2: SSP 2 interface power/clock enable (bit 20)
-//			<o12.21>	PCSSP0: SSP 0 interface power/clock enable (bit 21)
-//			<o12.22>	PCTIM2: Timer 2 power/clock enable (bit 22)
-//			<o12.23>	PCTIM3: Timer 3 power/clock enable (bit 23)
-//			<o12.24>	PCUART2: UART 2 power/clock enable (bit 24)
-//			<o12.25>	PCUART3: UART 3 power/clock enable (bit 25)
-//			<o12.26>	PCI2C2: I2C 2 interface power/clock enable (bit 26)
-//			<o12.27>	PCI2S: I2S interface power/clock enable (bit 27)
-//			<o12.28>	PCSDC: SD Card interface power/clock enable (bit 28)
-//			<o12.29>	PCGPDMA: GPDMA function power/clock enable (bit 29)
-//			<o12.30>	PCENET: Ethernet block power/clock enable (bit 30)
-//			<o12.31>	PCUSB: USB interface power/clock enable (bit 31)
-//		</h>
-//
-//		<h>	Clock Output Configuration Register (CLKOUTCFG)
-//			<o13.0..3>	CLKOUTSEL: Clock Source for CLKOUT Selection
-//						<0=>	CPU clock
-//						<1=>	Main Oscillator
-//						<2=>	Internal RC Oscillator
-//						<3=>	USB clock
-//						<4=>	RTC Oscillator
-//						<5=>	unused
-//						<6=>	Watchdog Oscillator
-//
-//			<o13.4..7>	CLKOUTDIV: Output Clock Divider
-//						<1-16><#-1>
-//
-//			<o13.8>		CLKOUT_EN: CLKOUT enable
-//		</h>
-//
-//	</e>
-*/
-
-#define CLOCK_SETUP           1
-#define SCS_Val               0x00000020
-#define CLKSRCSEL_Val         0x00000001
-#define PLL0_SETUP            1
-#define PLL0CFG_Val           0x00000009
-#define PLL1_SETUP            1
-#define PLL1CFG_Val           0x00000023
-#define CCLKSEL_Val           0x00000101
-#define USBCLKSEL_Val         0x00000201
-#define EMCCLKSEL_Val         0x00000000
-#define PCLKSEL_Val           0x00000002
-#define SPIFICLKSEL_Val       0x00000002
-#define PCONP_Val             0x042887DE
-#define CLKOUTCFG_Val         0x00000100
-
-#ifdef CORE_M4
-#define	LPC_CPACR	        0xE000ED88
-
-#define SCB_MVFR0           0xE000EF40
-#define SCB_MVFR0_RESET     0x10110021
-
-#define SCB_MVFR1           0xE000EF44
-#define SCB_MVFR1_RESET     0x11000011
-#endif
-
-
-/*--------------------- Flash Accelerator Configuration ----------------------
-//
-//	<e>	Flash Accelerator Configuration register (FLASHCFG - address 0x400F C000)
-//		<o1.12..15>	FLASHTIM: Flash Access Time
-//					<0=>	1 CPU clock (for CPU clock up to 20 MHz)
-//					<1=>	2 CPU clocks (for CPU clock up to 40 MHz)
-//					<2=>	3 CPU clocks (for CPU clock up to 60 MHz)
-//					<3=>	4 CPU clocks (for CPU clock up to 80 MHz)
-//					<4=>	5 CPU clocks (for CPU clock up to 100 MHz)
-//					<5=>	6 CPU clocks (for any CPU clock)
-//	</e>
-*/
-
-#define FLASH_SETUP           1
-#define FLASHCFG_Val          0x00005000
-
-/*----------------------------------------------------------------------------
-  Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask)                     (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SCS_Val),       ~0x0000003F))
-   #error "SCS: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
-   #error "CLKSRCSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((PLL0CFG_Val),   ~0x0000007F))
-   #error "PLL0CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PLL1CFG_Val),   ~0x0000007F))
-   #error "PLL1CFG: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CCLKSEL_Val),   ~0x0000011F))
-   #error "CCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
-   #error "USBCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
-   #error "EMCCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
-   #error "PCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
-   #error "PCONP: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
-   #error "CLKOUTCFG: Invalid values of reserved bits!"
-#endif
-
-/* Flash Accelerator Configuration -------------------------------------------*/
-#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
-   #error "FLASHCFG: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
-  DEFINES
- *----------------------------------------------------------------------------*/
-/* pll_out_clk = F_cco / (2 ?P)
-   F_cco = pll_in_clk ?M ?2 ?P */
-#define __M                   ((PLL0CFG_Val & 0x1F) + 1)
-#define __PLL0_CLK(__F_IN)    (__F_IN * __M)
-#define __CCLK_DIV            (CCLKSEL_Val & 0x1F)
-#define __PCLK_DIV			  (PCLKSEL_Val & 0x1F)
-#define __ECLK_DIV			  ((EMCCLKSEL_Val & 0x01) + 1)
-
-/* Determine core clock frequency according to settings */
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-
-  #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
-   #error "Main Oscillator is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
-   #error "Main PLL is selected as clock source but is not enabled!"
-  #endif
-
-  #if ((CCLKSEL_Val & 0x100) == 0)      /* cclk = sysclk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
-		#define __PER_CLK  (IRC_OSC/  __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
-        #define __PER_CLK  (OSC_CLK/  __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK/  __ECLK_DIV)
-    #endif
-  #else                                 /* cclk = pll_clk */
-    #if ((CLKSRCSEL_Val & 0x01) == 0)   /* sysclk = irc_clk */
-        #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
-        #define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
-    #else                               /* sysclk = osc_clk */
-        #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
-        #define __PER_CLK  (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
-		#define __EMC_CLK  (__CORE_CLK / __ECLK_DIV)
-    #endif
-  #endif
-
-#else
-        #define __CORE_CLK (IRC_OSC)
-        #define __PER_CLK  (IRC_OSC)
-        #define __EMC_CLK  (__CORE_CLK)
-#endif
-
-/*----------------------------------------------------------------------------
-  Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
-uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk)  */
-uint32_t EMCClock		 = __EMC_CLK; /*!< EMC Clock Frequency 				  */
-uint32_t USBClock 		 = (48000000UL);		  /*!< USB Clock Frequency - this value will
-									be updated after call SystemCoreClockUpdate, should be 48MHz*/
-
-
-/*----------------------------------------------------------------------------
-  Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
-{
-  /* Determine clock frequency according to clock register values             */
-  if ((LPC_SC->CCLKSEL &0x100) == 0) {            /* cclk = sysclk    */
-    if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-		  SystemCoreClock = __CLK_DIV(IRC_OSC , (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = __CLK_DIV(IRC_OSC , (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-    }
-    else {                                        /* sysclk = osc_clk */
-      if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock        = 0;
-      }
-      else {
-          SystemCoreClock = __CLK_DIV(OSC_CLK , (LPC_SC->CCLKSEL & 0x1F));
-          PeripheralClock = __CLK_DIV(OSC_CLK , (LPC_SC->PCLKSEL & 0x1F));
-          EMCClock        = (SystemCoreClock / ((LPC_SC->EMCCLKSEL & 0x01)+1));
-      }
-    }
-  }
-  else {                                          /* cclk = pll_clk */
-    if ((LPC_SC->PLL0STAT & 0x100) == 0) {        /* PLL0 not enabled */
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-    }
-    else {
-      if ((LPC_SC->CLKSRCSEL & 0x01) == 0) {    /* sysclk = irc_clk */
-          uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-          uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
-          uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
-          uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
-          SystemCoreClock = __CLK_DIV(IRC_OSC * mul , cpu_div);
-          PeripheralClock = __CLK_DIV(IRC_OSC * mul , per_div);
-          EMCClock        = SystemCoreClock / emc_div;
-      }
-      else {                                        /* sysclk = osc_clk */
-        if ((LPC_SC->SCS & 0x40) == 0) {
-          SystemCoreClock = 0;                      /* this should never happen! */
-          PeripheralClock = 0;
-          EMCClock 		  = 0;
-        }
-        else {
-          uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-          uint8_t cpu_div = (LPC_SC->CCLKSEL & 0x1F);
-          uint8_t per_div = (LPC_SC->PCLKSEL & 0x1F);
-		  uint8_t emc_div = (LPC_SC->EMCCLKSEL & 0x01)+1;
-          SystemCoreClock = __CLK_DIV(OSC_CLK * mul , cpu_div);
-          PeripheralClock = __CLK_DIV(OSC_CLK * mul , per_div);
-          EMCClock        = SystemCoreClock / emc_div;
-        }
-      }
-    }
-  }
-  /* ---update USBClock------------------*/
-  if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
-  {
-	  switch (LPC_SC->USBCLKSEL & 0x1F)
-	  {
-	  case 0:
-		  USBClock = 0; //no clock will be provided to the USB subsystem
-		  break;
-	  case 4:
-	  case 6:
-            {
-                 uint8_t mul = ((LPC_SC->PLL0STAT & 0x1F) + 1);
-                 uint8_t usb_div = (LPC_SC->USBCLKSEL & 0x1F);
-		  if(LPC_SC->CLKSRCSEL & 0x01)	//pll_clk_in = main_osc
-			  USBClock = OSC_CLK * mul / usb_div;
-		  else //pll_clk_in = irc_clk
-			  USBClock = IRC_OSC * mul / usb_div;
-            }
-            break;
-	  default:
-		  USBClock = 0;  /* this should never happen! */
-	  }
-  }
-  else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
-  {
-	  if(LPC_SC->CLKSRCSEL & 0x01)	//pll1_clk_in = main_osc
-	  		USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
-	  else //pll1_clk_in = irc_clk
-	  		USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
-  }
-  else
-	  USBClock = 0; /* this should never happen! */
-}
-
-  /* Determine clock frequency according to clock register values             */
-
-#ifdef CORE_M4
-
-void fpu_init(void)
-{
- // from arm trm manual:
-//                ; CPACR is located at address 0xE000ED88
-//                LDR.W R0, =0xE000ED88
-//                ; Read CPACR
-//                LDR R1, [R0]
-//                ; Set bits 20-23 to enable CP10 and CP11 coprocessors
-//                ORR R1, R1, #(0xF << 20)
-//                ; Write back the modified value to the CPACR
-//                STR R1, [R0]
-
-
-    volatile uint32_t* regCpacr = (uint32_t*) LPC_CPACR;
-    volatile uint32_t* regMvfr0 = (uint32_t*) SCB_MVFR0;
-    volatile uint32_t* regMvfr1 = (uint32_t*) SCB_MVFR1;
-    volatile uint32_t Cpacr;
-    volatile uint32_t Mvfr0;
-    volatile uint32_t Mvfr1;
-    char vfpPresent = 0;
-
-    Mvfr0 = *regMvfr0;
-    Mvfr1 = *regMvfr1;
-
-    vfpPresent = ((SCB_MVFR0_RESET == Mvfr0) && (SCB_MVFR1_RESET == Mvfr1));
-
-    if(vfpPresent)
-    {
-        Cpacr = *regCpacr;
-        Cpacr |= (0xF << 20);
-        *regCpacr = Cpacr;   // enable CP10 and CP11 for full access
-    }
-
-}
-#endif
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-#ifndef __CODE_RED
-#ifdef CORE_M4
-fpu_init();
-#endif
-#endif
-
-#if (CLOCK_SETUP)                       /* Clock Setup                        */
-  LPC_SC->SCS       = SCS_Val;
-  if (SCS_Val & (1 << 5)) {             /* If Main Oscillator is enabled      */
-    while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready    */
-  }
-
-  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val;    /* Select Clock Source for sysclk/PLL0*/
-
-#if (PLL0_SETUP)
-  LPC_SC->PLL0CFG   = PLL0CFG_Val;
-  LPC_SC->PLL0CON   = 0x01;             /* PLL0 Enable                        */
-  LPC_SC->PLL0FEED  = 0xAA;
-  LPC_SC->PLL0FEED  = 0x55;
-  while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0                    */
-#endif
-
-#if (PLL1_SETUP)
-  LPC_SC->PLL1CFG   = PLL1CFG_Val;
-  LPC_SC->PLL1CON   = 0x01;             /* PLL1 Enable                        */
-  LPC_SC->PLL1FEED  = 0xAA;
-  LPC_SC->PLL1FEED  = 0x55;
-  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1                    */
-#endif
-
-  LPC_SC->CCLKSEL   = CCLKSEL_Val;      /* Setup Clock Divider                */
-  LPC_SC->USBCLKSEL = USBCLKSEL_Val;    /* Setup USB Clock Divider            */
-  LPC_SC->EMCCLKSEL = EMCCLKSEL_Val;    /* EMC Clock Selection                */
-  LPC_SC->SPIFICLKSEL  = SPIFICLKSEL_Val;  /* SPIFI Clock Selection              */
-  LPC_SC->PCLKSEL   = PCLKSEL_Val;      /* Peripheral Clock Selection         */
-  LPC_SC->PCONP     = PCONP_Val;        /* Power Control for Peripherals      */
-  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val;    /* Clock Output Configuration         */
-#endif
-
-  LPC_SC->PBOOST 	|= 0x03;			/* Power Boost control				*/
-
-#if (FLASH_SETUP == 1)                  /* Flash Accelerator Setup            */
-  LPC_SC->FLASHCFG  = FLASHCFG_Val|0x03A;
-#endif
-#ifndef __CODE_RED
-#ifdef  __RAM_MODE__
-  SCB->VTOR  = 0x10000000 & 0x3FFFFF80;
-#else
-  SCB->VTOR  = 0x00000000 & 0x3FFFFF80;
-#endif
-#endif
-  SystemCoreClockUpdate();
-}

bsp/nxp/lpc/lpc408x/Libraries/Device/SConscript

@@ -1,23 +0,0 @@
-# RT-Thread building script for component
-
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-src = Split('''
-NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c
-''')
-CPPPATH = [cwd + '/NXP/LPC407x_8x_177x_8x/Include', cwd + '/../CMSIS/Include']
-CPPDEFINES = ['CORE_M4']
-
-# add for startup script
-if rtconfig.PLATFORM in ['gcc']:
-    src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/GCC/startup_LPC407x_8x_177x_8x.s']
-elif rtconfig.PLATFORM in ['armcc', 'armclang']:
-    src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s']
-elif rtconfig.PLATFORM in ['iccarm']:
-    src += ['NXP/LPC407x_8x_177x_8x/Source/Templates/IAR/startup_LPC407x_8x_177x_8x.s']
-
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
-
-Return('group')

bsp/nxp/lpc/lpc408x/Libraries/Drivers/SConscript

@@ -1,39 +0,0 @@
-# RT-Thread building script for component
-
-Import('rtconfig')
-from building import *
-
-cwd = GetCurrentDir()
-src = Split('''
-source/lpc_adc.c
-source/lpc_bod.c
-source/lpc_can.c
-source/lpc_clkpwr.c
-source/lpc_crc.c
-source/lpc_dac.c
-source/lpc_eeprom.c
-source/lpc_emc.c
-source/lpc_exti.c
-source/lpc_gpdma.c
-source/lpc_gpio.c
-source/lpc_i2c.c
-source/lpc_i2s.c
-source/lpc_iap.c
-source/lpc_lcd.c
-source/lpc_mcpwm.c
-source/lpc_nvic.c
-source/lpc_pinsel.c
-source/lpc_pwm.c
-source/lpc_qei.c
-source/lpc_rtc.c
-source/lpc_ssp.c
-source/lpc_systick.c
-source/lpc_timer.c
-source/lpc_uart.c
-source/lpc_wwdt.c
-''')
-CPPPATH = [cwd + '/include']
-
-group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/debug_frmwrk.h

@@ -1,114 +0,0 @@
-/**********************************************************************
-* $Id$      debug_frmwrk.h          2011-06-02
-*//**
-* @file     debug_frmwrk.h
-* @brief    Contains some utilities that used for debugging through UART
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef __DEBUG_FRMWRK_H_
-#define __DEBUG_FRMWRK_H_
-
-#include "lpc_uart.h"
-
-#define USED_UART_DEBUG_PORT    0
-
-#define NUM_SKIPPED_ALLOWED         (10)
-
-#define DBG_GETVAL_IN_DEC           (0)
-#define DBG_GETVAL_IN_HEX           (1)
-//#define DBG_GETVAL_IN_CHARS       (2)
-
-#if (USED_UART_DEBUG_PORT == 0)
-#define DEBUG_UART_PORT             (UART_0)
-#elif (USED_UART_DEBUG_PORT == 1)
-#define DEBUG_UART_PORT             (UART_1)
-#elif (USED_UART_DEBUG_PORT == 2)
-#define DEBUG_UART_PORT             (UART_2)
-#elif (USED_UART_DEBUG_PORT == 3)
-#define DEBUG_UART_PORT             (UART_3)
-#elif (USED_UART_DEBUG_PORT == 4)
-#define DEBUG_UART_PORT             (UART_4)
-#else
- #error "Invalid UART port selection!"
-#endif
-
-#define _DBG(x)                             _db_msg(DEBUG_UART_PORT, x)
-#define _DBG_(x)                            _db_msg_(DEBUG_UART_PORT, x)
-
-#define _DBC(x)                             _db_char(DEBUG_UART_PORT, x)
-
-#define _DBD(x)                             _db_dec(DEBUG_UART_PORT, x)
-#define _DBD16(x)                           _db_dec_16(DEBUG_UART_PORT, x)
-#define _DBD32(x)                           _db_dec_32(DEBUG_UART_PORT, x)
-
-#define _DBH(x)                             _db_hex(DEBUG_UART_PORT, x)
-#define _DBH16(x)                           _db_hex_16(DEBUG_UART_PORT, x)
-#define _DBH32(x)                           _db_hex_32(DEBUG_UART_PORT, x)
-
-#define _DBH_(x)                            _db_hex_(DEBUG_UART_PORT, x)
-#define _DBH16_(x)                          _db_hex_16_(DEBUG_UART_PORT, x)
-#define _DBH32_(x)                          _db_hex_32_(DEBUG_UART_PORT, x)
-
-#define _DG                                 _db_get_char(DEBUG_UART_PORT)
-#define _DG_NONBLOCK(c)                     _db_get_char_nonblocking(DEBUG_UART_PORT,c)
-#define _DGV(option, numCh, val)            _db_get_val(DEBUG_UART_PORT, option, numCh, val)
-
-//void  _printf (const  char *format, ...);
-
-extern void (*_db_msg)(UART_ID_Type UartID, const void *s);
-extern void (*_db_msg_)(UART_ID_Type UartID, const void *s);
-extern void (*_db_char)(UART_ID_Type UartID, uint8_t ch);
-extern void (*_db_dec)(UART_ID_Type UartID, uint8_t decn);
-extern void (*_db_dec_16)(UART_ID_Type UartID, uint16_t decn);
-extern void (*_db_dec_32)(UART_ID_Type UartID, uint32_t decn);
-extern void (*_db_hex)(UART_ID_Type UartID, uint8_t hexn);
-extern void (*_db_hex_16)(UART_ID_Type UartID, uint16_t hexn);
-extern void (*_db_hex_32)(UART_ID_Type UartID, uint32_t hexn);
-extern void (*_db_hex_)(UART_ID_Type UartID, uint8_t hexn);
-extern void (*_db_hex_16_)(UART_ID_Type UartID, uint16_t hexn);
-extern void (*_db_hex_32_)(UART_ID_Type UartID, uint32_t hexn);
-
-extern uint8_t (*_db_get_char)(UART_ID_Type UartID);
-extern Bool (*_db_get_char_nonblocking)(UART_ID_Type UartID, uint8_t* c);
-extern uint8_t (*_db_get_val)(UART_ID_Type UartID, uint8_t option, uint8_t numCh, uint32_t * val);
-
-uint8_t UARTGetValue (UART_ID_Type UartID, uint8_t option,
-                                            uint8_t numCh, uint32_t* val);
-void UARTPutChar (UART_ID_Type UartID, uint8_t ch);
-void UARTPuts(UART_ID_Type UartID, const void *str);
-void UARTPuts_(UART_ID_Type UartID, const void *str);
-void UARTPutDec(UART_ID_Type UartID, uint8_t decnum);
-void UARTPutDec16(UART_ID_Type UartID, uint16_t decnum);
-void UARTPutDec32(UART_ID_Type UartID, uint32_t decnum);
-void UARTPutHex (UART_ID_Type UartID, uint8_t hexnum);
-void UARTPutHex16 (UART_ID_Type UartID, uint16_t hexnum);
-void UARTPutHex32 (UART_ID_Type UartID, uint32_t hexnum);
-uint8_t UARTGetChar (UART_ID_Type UartID);
-Bool UARTGetCharInNonBlock(UART_ID_Type UartID, uint8_t* c);
-void debug_frmwrk_init(void);
-
-#endif /* __DEBUG_FRMWRK_H_ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc177x_8x_libcfg_default.h

@@ -1,156 +0,0 @@
-/**********************************************************************
-* $Id$      lpc17xx_libcfg.h            2010-05-21
-***
-* @file     lpc17xx_libcfg.h
-* @brief    Library configuration file
-* @version  2.0
-* @date     21. May. 2010
-* @author   NXP MCU SW Application Team
-*
-* Copyright(C) 2010, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef _LPC177x_8x_LIBCFG_H_
-#define _LPC177x_8x_LIBCFG_H_
-
-#include "lpc_types.h"
-
-
-/************************** DEBUG MODE DEFINITIONS *********************************/
-/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
-   the "CHECK_PARAM" macro in the FW library code */
-
-#define DEBUG
-
-
-/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
-
-/* Comment the line below to disable the specific peripheral inclusion */
-
-/* DEBUG_FRAMWORK -------------------- */
-#define _DBGFWK
-
-/* Clock & Power -------------------- */
-#define _CLKPWR
-
-/* CRC -------------------- */
-#define _CRC
-
-/* GPIO ------------------------------- */
-#define _GPIO
-
-/* NVIC ------------------------------- */
-#define _NVIC
-
-/* PINSEL ------------------------------- */
-#define _PINSEL
-
-/* EXTI ------------------------------- */
-#define _EXTI
-
-/* EMC ------------------------------- */
-#define _EMC
-
-/* UART ------------------------------- */
-#define _UART
-
-/* SPI ------------------------------- */
-#define _SPI
-
-/* SYSTICK --------------------------- */
-#define _SYSTICK
-
-/* SSP ------------------------------- */
-#define _SSP
-
-
-/* I2C ------------------------------- */
-#define _I2C
-
-/* TIMER ------------------------------- */
-#define _TIM
-
-/* WDT ------------------------------- */
-#define _WDT
-
-
-/* GPDMA ------------------------------- */
-#define _GPDMA
-
-
-/* DAC ------------------------------- */
-#define _DAC
-
-/* ADC ------------------------------- */
-#define _ADC
-
-/* EEPROM ------------------------------- */
-#define _EEPROM
-
-/* PWM ------------------------------- */
-#define _PWM
-
-/* RTC ------------------------------- */
-#define _RTC
-
-/* I2S ------------------------------- */
-#define _I2S
-
-/* USB device ------------------------------- */
-#define _USBDEV
-#ifdef _USBDEV
-#define _USB_DEV_AUDIO
-#define _USB_DEV_MASS_STORAGE
-#define _USB_DEV_HID
-#define _USB_DEV_VIRTUAL_COM
-#endif /*_USBDEV*/
-
-/* USB Host ------------------------------- */
-#define _USBHost
-
-/* QEI ------------------------------- */
-#define _QEI
-
-/* MCPWM ------------------------------- */
-#define _MCPWM
-
-/* CAN--------------------------------*/
-#define _CAN
-
-/* EMAC ------------------------------ */
-#define _EMAC
-
-/* LCD ------------------------------ */
-#define _LCD
-
-/* MCI ------------------------------ */
-#define _MCI
-
-/* IAP------------------------------ */
-#define _IAP
-
-/* BOD------------------------------ */
-#define _BOD
-/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
-
-
-#endif /* _LPC177x_8x_LIBCFG_H_ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_adc.h

@@ -1,303 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_adc.h           2011-06-02
-*//**
-* @file     lpc_adc.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for ADC firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup ADC ADC (Analog-to-Digital Converter)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_ADC_H_
-#define __LPC_ADC_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Private macros ------------------------------------------------------------- */
-/** @defgroup ADC_Private_Macros ADC Private Macros
- * @{
- */
-
-/* -------------------------- BIT DEFINITIONS ----------------------------------- */
-/*********************************************************************//**
- * Macro defines for ADC  control register
- **********************************************************************/
-
-/**  Selects which of the AD0.0:7 pins (channels) is (are) to be sampled and converted */
-#define ADC_CR_CH_SEL(n)    ((1UL << n))
-
-/**  The APB clock (PCLK) is divided by (this value plus one)
-* to produce the clock for the A/D */
-#define ADC_CR_CLKDIV(n)    ((n<<8))
-
-/**  Repeated conversions A/D enable bit */
-#define ADC_CR_BURST        ((1UL<<16))
-
-/**  ADC convert in power down mode; if 0, it's in power down mode; if 1, it's in normal
-* operation mode */
-#define ADC_CR_PDN          ((1UL<<21))
-
-/**  Start mask bits */
-#define ADC_CR_START_MASK   ((7UL<<24))
-
-/**  Select Start Mode controll the AD Converter in case the Burst bit is 0 (zero) */
-#define ADC_CR_START_MODE_SEL(SEL)  ((SEL<<24))
-
-/**  Start conversion now */
-#define ADC_CR_START_NOW    ((1UL<<24))
-
-/**  Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
-#define ADC_CR_START_EINT0  ((2UL<<24))
-
-/** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
-#define ADC_CR_START_CAP01  ((3UL<<24))
-
-/**  Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
-#define ADC_CR_START_MAT01  ((4UL<<24))
-
-/**  Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
-#define ADC_CR_START_MAT03  ((5UL<<24))
-
-/**  Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
-#define ADC_CR_START_MAT10  ((6UL<<24))
-
-/**  Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
-#define ADC_CR_START_MAT11  ((7UL<<24))
-
-/**  Start conversion on a falling edge on the selected CAP/MAT signal */
-#define ADC_CR_EDGE         ((1UL<<27))
-
-/*********************************************************************//**
- * Macro defines for ADC Global Data register
- **********************************************************************/
-
-/** When DONE is 1, this field contains result value of ADC conversion
-* (in 12-bit value) */
-#define ADC_GDR_RESULT(n)       (((n>>4)&0xFFF))
-
-/** These bits contain the channel from which the LS bits were converted */
-#define ADC_GDR_CH(n)           (((n>>24)&0x7))
-
-/** This bits is used to mask for Channel */
-#define ADC_GDR_CH_MASK         ((7UL<<24))
-
-/** This bit is 1 in burst mode if the results of one or
- * more conversions was (were) lost */
-#define ADC_GDR_OVERRUN_FLAG    ((1UL<<30))
-
-/** This bit is set to 1 when an A/D conversion completes */
-#define ADC_GDR_DONE_FLAG       ((1UL<<31))
-
-/*********************************************************************//**
- * Macro defines for ADC Interrupt register
- **********************************************************************/
-
-/** These bits allow control over which A/D channels generate
- * interrupts for conversion completion */
-#define ADC_INTEN_CH(n)         ((1UL<<n))
-
-/** When 1, enables the global DONE flag in ADDR to generate an interrupt */
-#define ADC_INTEN_GLOBAL        ((1UL<<8))
-
-/*********************************************************************//**
- * Macro defines for ADC Data register
- **********************************************************************/
-
-/** When DONE is 1, this field contains result value of ADC conversion */
-#define ADC_DR_RESULT(n)        (((n>>4)&0xFFF))
-
-/** These bits mirror the OVERRRUN status flags that appear in the
- * result register for each A/D channel */
-#define ADC_DR_OVERRUN_FLAG     ((1UL<<30))
-
-/** This bit is set to 1 when an A/D conversion completes. It is cleared
- * when this register is read */
-#define ADC_DR_DONE_FLAG        ((1UL<<31))
-
-/*********************************************************************//**
- * Macro defines for ADC Status register
-**********************************************************************/
-
-/** These bits mirror the DONE status flags that appear in the result
- * register for each A/D channel */
-#define ADC_STAT_CH_DONE_FLAG(n)        ((n&0xFF))
-
-/** These bits mirror the OVERRRUN status flags that appear in the
- * result register for each A/D channel */
-#define ADC_STAT_CH_OVERRUN_FLAG(n)     (((n>>8)&0xFF))
-
-/** This bit is the A/D interrupt flag */
-#define ADC_STAT_INT_FLAG               ((1UL<<16))
-
-/*********************************************************************//**
- * Macro defines for ADC Trim register
-**********************************************************************/
-
-/** Offset trim bits for ADC operation */
-#define ADC_ADCOFFS(n)      (((n&0xF)<<4))
-
-/** Written to boot code*/
-#define ADC_TRIM(n)         (((n&0xF)<<8))
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup ADC_Public_Types ADC Public Types
- * @{
- */
-
-/*********************************************************************//**
- * @brief ADC enumeration
- **********************************************************************/
-
-/** @brief Channel Selection */
-typedef enum
-{
-    ADC_CHANNEL_0  = 0, /*!<  Channel 0 */
-    ADC_CHANNEL_1,      /*!<  Channel 1 */
-    ADC_CHANNEL_2,      /*!<  Channel 2 */
-    ADC_CHANNEL_3,      /*!<  Channel 3 */
-    ADC_CHANNEL_4,      /*!<  Channel 4 */
-    ADC_CHANNEL_5,      /*!<  Channel 5 */
-    ADC_CHANNEL_6,      /*!<  Channel 6 */
-    ADC_CHANNEL_7       /*!<  Channel 7 */
-}ADC_CHANNEL_SELECTION;
-
-/** @brief Type of start option */
-typedef enum
-{
-    ADC_START_CONTINUOUS = 0,   /*!< Continuous mode */
-
-    ADC_START_NOW,              /*!< Start conversion now */
-
-    ADC_START_ON_EINT0,         /*!< Start conversion when the edge selected
-                                 * by bit 27 occurs on P2.10/EINT0 */
-    ADC_START_ON_CAP01,         /*!< Start conversion when the edge selected
-                                 * by bit 27 occurs on P1.27/CAP0.1 */
-    ADC_START_ON_MAT01,         /*!< Start conversion when the edge selected
-                                 * by bit 27 occurs on MAT0.1 */
-    ADC_START_ON_MAT03,         /*!< Start conversion when the edge selected
-                                 * by bit 27 occurs on MAT0.3 */
-    ADC_START_ON_MAT10,         /*!< Start conversion when the edge selected
-                                  * by bit 27 occurs on MAT1.0 */
-    ADC_START_ON_MAT11          /*!< Start conversion when the edge selected
-                                  * by bit 27 occurs on MAT1.1 */
-} ADC_START_OPT;
-
-
-/** @brief Type of edge when start conversion on the selected CAP/MAT signal */
-typedef enum
-{
-    ADC_START_ON_RISING = 0,    /*!< Start conversion on a rising edge
-                                *on the selected CAP/MAT signal */
-    ADC_START_ON_FALLING        /*!< Start conversion on a falling edge
-                                *on the selected CAP/MAT signal */
-} ADC_START_ON_EDGE_OPT;
-
-/** @brief* ADC type interrupt enum */
-typedef enum
-{
-    ADC_ADINTEN0 = 0,       /*!< Interrupt channel 0 */
-    ADC_ADINTEN1,           /*!< Interrupt channel 1 */
-    ADC_ADINTEN2,           /*!< Interrupt channel 2 */
-    ADC_ADINTEN3,           /*!< Interrupt channel 3 */
-    ADC_ADINTEN4,           /*!< Interrupt channel 4 */
-    ADC_ADINTEN5,           /*!< Interrupt channel 5 */
-    ADC_ADINTEN6,           /*!< Interrupt channel 6 */
-    ADC_ADINTEN7,           /*!< Interrupt channel 7 */
-    ADC_ADGINTEN            /*!< Individual channel/global flag done generate an interrupt */
-}ADC_TYPE_INT_OPT;
-
-/** @brief ADC Data  status */
-typedef enum
-{
-    ADC_DATA_BURST = 0,     /*Burst bit*/
-    ADC_DATA_DONE           /*Done bit*/
-}ADC_DATA_STATUS;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup ADC_Public_Functions ADC Public Functions
- * @{
- */
- 
-/* Init/DeInit ADC peripheral ----------------*/
-void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
-void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
-
-/* Enable/Disable ADC functions --------------*/
-void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
-void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
-void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
-void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
-
-/* Configure ADC functions -------------------*/
-void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
-void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
-
-/* Get ADC information functions -------------------*/
-uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
-FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
-uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
-FlagStatus  ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* LPC_ADC_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_bod.h

@@ -1,98 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_bod.h           2011-12-09
-*//**
-* @file     lpc_bod.h
-* @brief    Contain definitions & functions related to BOD.
-* @version  1.0
-* @date     09 December. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup BOD BOD (Brown-Out Detector)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */#ifndef __LPC_BOD_H 
-#define __LPC_BOD_H
-#include "lpc_types.h"
-/** @defgroup BOD_Private_Macros BOD Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/**********************************************************************
-** Power Mode Control register definitions
-**********************************************************************/
-#define BOD_PCON_BODRPM    (0x01 << 2)
-#define BOD_PCON_BOGD      (0x01 << 3)
-#define BOD_PCON_BORD      (0x01 << 4)
-
-/**********************************************************************
-** Reset Source Identification Register definitions
-**********************************************************************/
-#define BOD_RSID_POR              (0x01 << 0)
-#define BOD_RSID_BODR      (0x01 << 3)
-
-/**
- * @}
- */
-
- /** @defgroup BOD_Public_Types BOD Public Types
- * @{
- */
-
-/**
- * @brief The field to configurate BOD
- */
-
-typedef struct 
-{
-    uint8_t Enabled;            /**< Enable BOD Circuit */
-    uint8_t PowerReduced;       /**< if ENABLE, BOD will be turned off in Power-down mode or Deep Sleep mode */
-                                /**< So, BOD can't be used to wake-up from these mode. */
-    uint8_t ResetOnVoltageDown;     /**< if ENABLE, reset the device when the VDD(REG)(3V3) voltage < the BOD reset trip level */
-}BOD_Config_Type;
-
-/**
- * @}
- */
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup BOD_Public_Functions BOD Public Functions
- * @{
- */
-void BOD_Init( BOD_Config_Type* pConfig );
-int32_t BOD_ResetSourceStatus(void);
-void BOD_ResetSourceClr(void);
-/**
- * @}
- */
-#endif /* end __LPC_BOD_H */
-/**
- * @}
- */
-
-/*****************************************************************************
-**                            End Of File
-******************************************************************************/

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_can.h

@@ -1,1014 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_can.h           2011-06-02
-*//**
-* @file     lpc_can.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for CAN firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup CAN CAN (Controller Area Network)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_CAN_H_
-#define __LPC_CAN_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-
-#include "lpc_types.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup CAN_Public_Macros CAN Public Macros
- * @{
- */
-
-/** Controller ID for CAN1 */
-#define CAN1_CTRL               ((uint8_t)(0))
-
-/** Controller ID for CAN2 */
-#define CAN2_CTRL               ((uint8_t)(1))
-
-/** Message(s) Acceptance is enabled */
-#define MSG_ENABLE              ((uint8_t)(0))
-
-/** Message(s) Acceptance is disabled */
-#define MSG_DISABLE             ((uint8_t)(1))
-
-
-/**
- * @}
- */
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup CAN_Private_Macros CAN Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/*********************************************************************//**
- * Macro defines for CAN Mode Register
- **********************************************************************/
-/** CAN Reset mode */
-#define CAN_MOD_RM          ((uint32_t)(1<<0))
-
-/** CAN Listen Only Mode */
-#define CAN_MOD_LOM         ((uint32_t)(1<<1))
-
-/** CAN Self Test mode */
-#define CAN_MOD_STM         ((uint32_t)(1<<2))
-
-/** CAN Transmit Priority mode */
-#define CAN_MOD_TPM         ((uint32_t)(1<<3))
-
-/** CAN Sleep mode */
-#define CAN_MOD_SM          ((uint32_t)(1<<4))
-
-/** CAN Receive Polarity mode */
-#define CAN_MOD_RPM         ((uint32_t)(1<<5))
-
-/** CAN Test mode */
-#define CAN_MOD_TM          ((uint32_t)(1<<7))
-
-/*********************************************************************//**
- * Macro defines for CAN Command Register
- **********************************************************************/
-/** CAN Transmission Request */
-#define CAN_CMR_TR          ((uint32_t)(1))
-
-/** CAN Abort Transmission */
-#define CAN_CMR_AT          ((uint32_t)(1<<1))
-
-/** CAN Release Receive Buffer */
-#define CAN_CMR_RRB         ((uint32_t)(1<<2))
-
-/** CAN Clear Data Overrun */
-#define CAN_CMR_CDO         ((uint32_t)(1<<3))
-
-/** CAN Self Reception Request */
-#define CAN_CMR_SRR         ((uint32_t)(1<<4))
-
-/** CAN Select Tx Buffer 1 */
-#define CAN_CMR_STB1        ((uint32_t)(1<<5))
-
-/** CAN Select Tx Buffer 2 */
-#define CAN_CMR_STB2        ((uint32_t)(1<<6))
-
-/** CAN Select Tx Buffer 3 */
-#define CAN_CMR_STB3        ((uint32_t)(1<<7))
-
-/*********************************************************************//**
- * Macro defines for CAN Global Status Register
- **********************************************************************/
-/** CAN Receive Buffer Status */
-#define CAN_GSR_RBS         ((uint32_t)(1))
-
-/** CAN Data Overrun Status */
-#define CAN_GSR_DOS         ((uint32_t)(1<<1))
-
-/** CAN Transmit Buffer Status */
-#define CAN_GSR_TBS         ((uint32_t)(1<<2))
-
-/** CAN Transmit Complete Status */
-#define CAN_GSR_TCS         ((uint32_t)(1<<3))
-
-/** CAN Receive Status */
-#define CAN_GSR_RS          ((uint32_t)(1<<4))
-
-/** CAN Transmit Status */
-#define CAN_GSR_TS          ((uint32_t)(1<<5))
-
-/** CAN Error Status */
-#define CAN_GSR_ES          ((uint32_t)(1<<6))
-
-/** CAN Bus Status */
-#define CAN_GSR_BS          ((uint32_t)(1<<7))
-
-/** CAN Current value of the Rx Error Counter */
-#define CAN_GSR_RXERR(n)    ((uint32_t)((n&0xFF)<<16))
-
-/** CAN Current value of the Tx Error Counter */
-#define CAN_GSR_TXERR(n)    ((uint32_t)(n&0xFF)<<24))
-
-/*********************************************************************//**
- * Macro defines for CAN Interrupt and Capture Register
- **********************************************************************/
-/** CAN Receive Interrupt */
-#define CAN_ICR_RI          ((uint32_t)(1))
-
-/** CAN Transmit Interrupt 1 */
-#define CAN_ICR_TI1         ((uint32_t)(1<<1))
-
-/** CAN Error Warning Interrupt */
-#define CAN_ICR_EI          ((uint32_t)(1<<2))
-
-/** CAN Data Overrun Interrupt */
-#define CAN_ICR_DOI         ((uint32_t)(1<<3))
-
-/** CAN Wake-Up Interrupt */
-#define CAN_ICR_WUI         ((uint32_t)(1<<4))
-
-/** CAN Error Passive Interrupt */
-#define CAN_ICR_EPI         ((uint32_t)(1<<5))
-
-/** CAN Arbitration Lost Interrupt */
-#define CAN_ICR_ALI         ((uint32_t)(1<<6))
-
-/** CAN Bus Error Interrupt */
-#define CAN_ICR_BEI         ((uint32_t)(1<<7))
-
-/** CAN ID Ready Interrupt */
-#define CAN_ICR_IDI         ((uint32_t)(1<<8))
-
-/** CAN Transmit Interrupt 2 */
-#define CAN_ICR_TI2         ((uint32_t)(1<<9))
-
-/** CAN Transmit Interrupt 3 */
-#define CAN_ICR_TI3         ((uint32_t)(1<<10))
-
-/** CAN Error Code Capture */
-#define CAN_ICR_ERRBIT(n)   ((uint32_t)((n&0x1F)<<16))
-
-/** CAN Error Direction */
-#define CAN_ICR_ERRDIR      ((uint32_t)(1<<21))
-
-/** CAN Error Capture */
-#define CAN_ICR_ERRC(n)     ((uint32_t)((n&0x3)<<22))
-
-/** CAN Arbitration Lost Capture */
-#define CAN_ICR_ALCBIT(n)       ((uint32_t)((n&0xFF)<<24))
-
-/*********************************************************************//**
- * Macro defines for CAN Interrupt Enable Register
- **********************************************************************/
-/** CAN Receive Interrupt Enable */
-#define CAN_IER_RIE         ((uint32_t)(1))
-
-/** CAN Transmit Interrupt Enable for buffer 1 */
-#define CAN_IER_TIE1        ((uint32_t)(1<<1))
-
-/** CAN Error Warning Interrupt Enable */
-#define CAN_IER_EIE         ((uint32_t)(1<<2))
-
-/** CAN Data Overrun Interrupt Enable */
-#define CAN_IER_DOIE        ((uint32_t)(1<<3))
-
-/** CAN Wake-Up Interrupt Enable */
-#define CAN_IER_WUIE        ((uint32_t)(1<<4))
-
-/** CAN Error Passive Interrupt Enable */
-#define CAN_IER_EPIE        ((uint32_t)(1<<5))
-
-/** CAN Arbitration Lost Interrupt Enable */
-#define CAN_IER_ALIE        ((uint32_t)(1<<6))
-
-/** CAN Bus Error Interrupt Enable */
-#define CAN_IER_BEIE        ((uint32_t)(1<<7))
-
-/** CAN ID Ready Interrupt Enable */
-#define CAN_IER_IDIE        ((uint32_t)(1<<8))
-
-/** CAN Transmit Enable Interrupt for Buffer 2 */
-#define CAN_IER_TIE2        ((uint32_t)(1<<9))
-
-/** CAN Transmit Enable Interrupt for Buffer 3 */
-#define CAN_IER_TIE3        ((uint32_t)(1<<10))
-
-/*********************************************************************//**
- * Macro defines for CAN Bus Timing Register
- **********************************************************************/
-/** CAN Baudrate Prescaler */
-#define CAN_BTR_BRP(n)      ((uint32_t)(n&0x3FF))
-
-/** CAN Synchronization Jump Width */
-#define CAN_BTR_SJM(n)      ((uint32_t)((n&0x3)<<14))
-
-/** CAN Time Segment 1 */
-#define CAN_BTR_TESG1(n)    ((uint32_t)(n&0xF)<<16))
-
-/** CAN Time Segment 2 */
-#define CAN_BTR_TESG2(n)    ((uint32_t)(n&0xF)<<20))
-
-/** CAN Sampling */
-#define CAN_BTR_SAM(n)      ((uint32_t)(1<<23))
-
-/*********************************************************************//**
- * Macro defines for CAN Error Warning Limit Register
- **********************************************************************/
-/** CAN Error Warning Limit */
-#define CAN_EWL_EWL(n)      ((uint32_t)(n&0xFF))
-
-/*********************************************************************//**
- * Macro defines for CAN Status Register
- **********************************************************************/
-/** CAN Receive Buffer Status */
-#define CAN_SR_RBS      ((uint32_t)(1))
-
-/** CAN Data Overrun Status */
-#define CAN_SR_DOS      ((uint32_t)(1<<1))
-
-/** CAN Transmit Buffer Status 1 */
-#define CAN_SR_TBS1     ((uint32_t)(1<<2))
-
-/** CAN Transmission Complete Status of Buffer 1 */
-#define CAN_SR_TCS1     ((uint32_t)(1<<3))
-
-/** CAN Receive Status */
-#define CAN_SR_RS       ((uint32_t)(1<<4))
-
-/** CAN Transmit Status 1 */
-#define CAN_SR_TS1      ((uint32_t)(1<<5))
-
-/** CAN Error Status */
-#define CAN_SR_ES       ((uint32_t)(1<<6))
-
-/** CAN Bus Status */
-#define CAN_SR_BS       ((uint32_t)(1<<7))
-
-/** CAN Transmit Buffer Status 2 */
-#define CAN_SR_TBS2     ((uint32_t)(1<<10))
-
-/** CAN Transmission Complete Status of Buffer 2 */
-#define CAN_SR_TCS2     ((uint32_t)(1<<11))
-
-/** CAN Transmit Status 2 */
-#define CAN_SR_TS2      ((uint32_t)(1<<13))
-
-/** CAN Transmit Buffer Status 2 */
-#define CAN_SR_TBS3     ((uint32_t)(1<<18))
-
-/** CAN Transmission Complete Status of Buffer 2 */
-#define CAN_SR_TCS3     ((uint32_t)(1<<19))
-
-/** CAN Transmit Status 2 */
-#define CAN_SR_TS3      ((uint32_t)(1<<21))
-
-/*********************************************************************//**
- * Macro defines for CAN Receive Frame Status Register
- **********************************************************************/
-/** CAN ID Index */
-#define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF))
-
-/** CAN Bypass */
-#define CAN_RFS_BP          ((uint32_t)(1<<10))
-
-/** CAN Data Length Code */
-#define CAN_RFS_DLC(n)      ((uint32_t)((n&0xF)<<16)
-
-/** CAN Remote Transmission Request */
-#define CAN_RFS_RTR         ((uint32_t)(1<<30))
-
-/** CAN control 11 bit or 29 bit Identifier */
-#define CAN_RFS_FF          ((uint32_t)(1<<31))
-
-/*********************************************************************//**
- * Macro defines for CAN Receive Identifier Register
- **********************************************************************/
-/** CAN 11 bit Identifier */
-#define CAN_RID_ID_11(n)        ((uint32_t)(n&0x7FF))
-
-/** CAN 29 bit Identifier */
-#define CAN_RID_ID_29(n)        ((uint32_t)(n&0x1FFFFFFF))
-
-/*********************************************************************//**
- * Macro defines for CAN Receive Data A Register
- **********************************************************************/
-/** CAN Receive Data 1 */
-#define CAN_RDA_DATA1(n)        ((uint32_t)(n&0xFF))
-
-/** CAN Receive Data 2 */
-#define CAN_RDA_DATA2(n)        ((uint32_t)((n&0xFF)<<8))
-
-/** CAN Receive Data 3 */
-#define CAN_RDA_DATA3(n)        ((uint32_t)((n&0xFF)<<16))
-
-/** CAN Receive Data 4 */
-#define CAN_RDA_DATA4(n)        ((uint32_t)((n&0xFF)<<24))
-
-/*********************************************************************//**
- * Macro defines for CAN Receive Data B Register
- **********************************************************************/
-/** CAN Receive Data 5 */
-#define CAN_RDB_DATA5(n)        ((uint32_t)(n&0xFF))
-
-/** CAN Receive Data 6 */
-#define CAN_RDB_DATA6(n)        ((uint32_t)((n&0xFF)<<8))
-
-/** CAN Receive Data 7 */
-#define CAN_RDB_DATA7(n)        ((uint32_t)((n&0xFF)<<16))
-
-/** CAN Receive Data 8 */
-#define CAN_RDB_DATA8(n)        ((uint32_t)((n&0xFF)<<24))
-
-/*********************************************************************//**
- * Macro defines for CAN Transmit Frame Information Register
- **********************************************************************/
-/** CAN Priority */
-#define CAN_TFI_PRIO(n)         ((uint32_t)(n&0xFF))
-
-/** CAN Data Length Code */
-#define CAN_TFI_DLC(n)          ((uint32_t)((n&0xF)<<16))
-
-/** CAN Remote Frame Transmission */
-#define CAN_TFI_RTR             ((uint32_t)(1<<30))
-
-/** CAN control 11-bit or 29-bit Identifier */
-#define CAN_TFI_FF              ((uint32_t)(1<<31))
-
-/*********************************************************************//**
- * Macro defines for CAN Transmit Identifier Register
- **********************************************************************/
-/** CAN 11-bit Identifier */
-#define CAN_TID_ID11(n)         ((uint32_t)(n&0x7FF))
-
-/** CAN 11-bit Identifier */
-#define CAN_TID_ID29(n)         ((uint32_t)(n&0x1FFFFFFF))
-
-/*********************************************************************//**
- * Macro defines for CAN Transmit Data A Register
- **********************************************************************/
-/** CAN Transmit Data 1 */
-#define CAN_TDA_DATA1(n)        ((uint32_t)(n&0xFF))
-
-/** CAN Transmit Data 2 */
-#define CAN_TDA_DATA2(n)        ((uint32_t)((n&0xFF)<<8))
-
-/** CAN Transmit Data 3 */
-#define CAN_TDA_DATA3(n)        ((uint32_t)((n&0xFF)<<16))
-
-/** CAN Transmit Data 4 */
-#define CAN_TDA_DATA4(n)        ((uint32_t)((n&0xFF)<<24))
-
-/*********************************************************************//**
- * Macro defines for CAN Transmit Data B Register
- **********************************************************************/
-/** CAN Transmit Data 5 */
-#define CAN_TDA_DATA5(n)        ((uint32_t)(n&0xFF))
-
-/** CAN Transmit Data 6 */
-#define CAN_TDA_DATA6(n)        ((uint32_t)((n&0xFF)<<8))
-
-/** CAN Transmit Data 7 */
-#define CAN_TDA_DATA7(n)        ((uint32_t)((n&0xFF)<<16))
-
-/** CAN Transmit Data 8 */
-#define CAN_TDA_DATA8(n)        ((uint32_t)((n&0xFF)<<24))
-
-/*********************************************************************//**
- * Macro defines for CAN Sleep Clear Register
- **********************************************************************/
-/** CAN1 Sleep mode */
-#define CAN1SLEEPCLR            ((uint32_t)(1<<1))
-
-/** CAN2 Sleep Mode */
-#define CAN2SLEEPCLR            ((uint32_t)(1<<2))
-
-/*********************************************************************//**
- * Macro defines for CAN Wake up Flags Register
- **********************************************************************/
-/** CAN1 Sleep mode */
-#define CAN_WAKEFLAGES_CAN1WAKE     ((uint32_t)(1<<1))
-
-/** CAN2 Sleep Mode */
-#define CAN_WAKEFLAGES_CAN2WAKE     ((uint32_t)(1<<2))
-
-/*********************************************************************//**
- * Macro defines for Central transmit Status Register
- **********************************************************************/
-/** CAN Transmit 1 */
-#define CAN_TSR_TS1         ((uint32_t)(1))
-
-/** CAN Transmit 2 */
-#define CAN_TSR_TS2         ((uint32_t)(1<<1))
-
-/** CAN Transmit Buffer Status 1 */
-#define CAN_TSR_TBS1            ((uint32_t)(1<<8))
-
-/** CAN Transmit Buffer Status 2 */
-#define CAN_TSR_TBS2            ((uint32_t)(1<<9))
-
-/** CAN Transmission Complete Status 1 */
-#define CAN_TSR_TCS1            ((uint32_t)(1<<16))
-
-/** CAN Transmission Complete Status 2 */
-#define CAN_TSR_TCS2            ((uint32_t)(1<<17))
-
-/*********************************************************************//**
- * Macro defines for Central Receive Status Register
- **********************************************************************/
-/** CAN Receive Status 1 */
-#define CAN_RSR_RS1             ((uint32_t)(1))
-
-/** CAN Receive Status 1 */
-#define CAN_RSR_RS2             ((uint32_t)(1<<1))
-
-/** CAN Receive Buffer Status 1*/
-#define CAN_RSR_RB1             ((uint32_t)(1<<8))
-
-/** CAN Receive Buffer Status 2*/
-#define CAN_RSR_RB2             ((uint32_t)(1<<9))
-
-/** CAN Data Overrun Status 1 */
-#define CAN_RSR_DOS1            ((uint32_t)(1<<16))
-
-/** CAN Data Overrun Status 1 */
-#define CAN_RSR_DOS2            ((uint32_t)(1<<17))
-
-/*********************************************************************//**
- * Macro defines for Central Miscellaneous Status Register
- **********************************************************************/
-/** Same CAN Error Status in CAN1GSR */
-#define CAN_MSR_E1      ((uint32_t)(1))
-
-/** Same CAN Error Status in CAN2GSR */
-#define CAN_MSR_E2      ((uint32_t)(1<<1))
-
-/** Same CAN Bus Status in CAN1GSR */
-#define CAN_MSR_BS1     ((uint32_t)(1<<8))
-
-/** Same CAN Bus Status in CAN2GSR */
-#define CAN_MSR_BS2     ((uint32_t)(1<<9))
-
-/*********************************************************************//**
- * Macro defines for Acceptance Filter Mode Register
- **********************************************************************/
-/** CAN Acceptance Filter Off mode */
-#define CAN_AFMR_AccOff     ((uint32_t)(1))
-
-/** CAN Acceptance File Bypass mode */
-#define CAN_AFMR_AccBP      ((uint32_t)(1<<1))
-
-/** FullCAN Mode Enhancements */
-#define CAN_AFMR_eFCAN      ((uint32_t)(1<<2))
-
-/*********************************************************************//**
- * Macro defines for Standard Frame Individual Start Address Register
- **********************************************************************/
-/** The start address of the table of individual Standard Identifier */
-#define CAN_STT_sa(n)       ((uint32_t)((n&1FF)<<2))
-
-/*********************************************************************//**
- * Macro defines for Standard Frame Group Start Address Register
- **********************************************************************/
-/** The start address of the table of grouped Standard Identifier */
-#define CAN_SFF_GRP_sa(n)       ((uint32_t)((n&3FF)<<2))
-
-/*********************************************************************//**
- * Macro defines for Extended Frame Start Address Register
- **********************************************************************/
-/** The start address of the table of individual Extended Identifier */
-#define CAN_EFF_sa(n)       ((uint32_t)((n&1FF)<<2))
-
-/*********************************************************************//**
- * Macro defines for Extended Frame Group Start Address Register
- **********************************************************************/
-/** The start address of the table of grouped Extended Identifier */
-#define CAN_Eff_GRP_sa(n)       ((uint32_t)((n&3FF)<<2))
-
-/*********************************************************************//**
- * Macro defines for End Of AF Table Register
- **********************************************************************/
-/** The End of Table of AF LookUp Table */
-#define CAN_EndofTable(n)       ((uint32_t)((n&3FF)<<2))
-
-/*********************************************************************//**
- * Macro defines for LUT Error Address Register
- **********************************************************************/
-/** CAN Look-Up Table Error Address */
-#define CAN_LUTerrAd(n)     ((uint32_t)((n&1FF)<<2))
-
-/*********************************************************************//**
- * Macro defines for LUT Error Register
- **********************************************************************/
-/** CAN Look-Up Table Error */
-#define CAN_LUTerr      ((uint32_t)(1))
-
-/*********************************************************************//**
- * Macro defines for Global FullCANInterrupt Enable Register
- **********************************************************************/
-/** Global FullCANInterrupt Enable */
-#define CAN_FCANIE      ((uint32_t)(1))
-
-/*********************************************************************//**
- * Macro defines for FullCAN Interrupt and Capture Register 0
- **********************************************************************/
-/** FullCAN Interrupt and Capture (0-31)*/
-#define CAN_FCANIC0_IntPnd(n)   ((uint32_t)(1<<n))
-
-/*********************************************************************//**
- * Macro defines for FullCAN Interrupt and Capture Register 1
- **********************************************************************/
-/** FullCAN Interrupt and Capture (0-31)*/
-#define CAN_FCANIC1_IntPnd(n)   ((uint32_t)(1<<(n-32)))
-
-
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
-/** Macro to determine if it is valid CAN peripheral or not */
-#define PARAM_CANx(x)           ((((uint32_t*)x)==((uint32_t *)LPC_CAN1)) \
-                                        ||(((uint32_t*)x)==((uint32_t *)LPC_CAN2)))
-
-/*  Macro to determine if it is valid CANAF or not*/
-#define PARAM_CANAFx(x)         (((uint32_t*)x)== ((uint32_t*)LPC_CANAF))
-
-/*  Macro to determine if it is valid CANAF RAM or not*/
-#define PARAM_CANAFRAMx(x)      (((uint32_t*)x)== (uint32_t*)LPC_CANAF_RAM)
-
-/*  Macro to determine if it is valid CANCR or not*/
-#define PARAM_CANCRx(x)         (((uint32_t*)x)==((uint32_t*)LPC_CANCR))
-
-/** Macro to check Data to send valid */
-#define PARAM_I2S_DATA(data)    ((data>=0)&&(data <= 0xFFFFFFFF))
-
-/** Macro to check frequency value */
-#define PRAM_I2S_FREQ(freq)     ((freq>=16000)&&(freq <= 96000))
-
-/** Macro to check Frame Identifier */
-#define PARAM_ID_11(n)          ((n>>11)==0) /*-- 11 bit --*/
-#define PARAM_ID_29(n)          ((n>>29)==0) /*-- 29 bit --*/
-
-/** Macro to check DLC value */
-#define PARAM_DLC(n)            ((n>>4)==0)  /*-- 4 bit --*/
-
-/** Macro to check ID format type */
-#define PARAM_ID_FORMAT(n)      ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT))
-
-/** Macro to check Group identifier */
-#define PARAM_GRP_ID(x, y)      ((x<=y))
-
-/** Macro to check Frame type */
-#define PARAM_FRAME_TYPE(n)     ((n==DATA_FRAME)||(n==REMOTE_FRAME))
-
-/** Macro to check Control/Central Status type parameter */
-#define PARAM_CTRL_STS_TYPE(n)  ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \
-                                            ||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS))
-
-/** Macro to check CR status type */
-#define PARAM_CR_STS_TYPE(n)    ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \
-                                                            ||(n==CANCR_MS))
-
-/** Macro to check AF Mode type parameter */
-#define PARAM_AFMODE_TYPE(n)    ((n==CAN_NORMAL)||(n==CAN_ACC_OFF) \
-                                            ||(n==CAN_ACC_BP)||(n==CAN_EFCAN))
-
-/** Macro to check Operation Mode */
-#define PARAM_MODE_TYPE(n)      ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \
-                                    ||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \
-                                    ||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \
-                                    ||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE))
-
-/** Macro define for struct AF_Section parameter */
-#define PARAM_CTRL(n)   ((n==CAN1_CTRL)|(n==CAN2_CTRL))
-
-/** Macro define for struct AF_Section parameter */
-#define PARAM_MSG_DISABLE(n)    ((n==MSG_ENABLE)|(n==MSG_DISABLE))
-
-/**Macro to check Interrupt Type parameter */
-#define PARAM_INT_EN_TYPE(n)    ((n==CANINT_RIE)||(n==CANINT_TIE1) \
-                                    ||(n==CANINT_EIE)||(n==CANINT_DOIE) \
-                                    ||(n==CANINT_WUIE)||(n==CANINT_EPIE) \
-                                    ||(n==CANINT_ALIE)||(n==CANINT_BEIE) \
-                                    ||(n==CANINT_IDIE)||(n==CANINT_TIE2) \
-                                    ||(n==CANINT_TIE3)||(n==CANINT_FCE))
-
-/** Macro to check AFLUT Entry type */
-#define PARAM_AFLUT_ENTRY_TYPE(n)   ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\
-                                        ||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \
-                                        ||(n==GROUP_EXTEND_ENTRY))
-
-/** Macro to check position */
-#define PARAM_POSITION(n)   ((n>=0)&&(n<512))
-
-/**
- * @}
- */
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup CAN_Public_Types CAN Public Types
- * @{
- */
-
-
-/***********************************************************************
- * CAN device configuration commands (IOCTL commands and arguments)
- **********************************************************************/
-/** CAN peripheral ID 0 */
-#define CAN_1       0
-
-/** CAN peripheral ID 1 */
-#define CAN_2       1
-
-/**
- * @brief CAN peripheral ID no
- */
-typedef enum
-{
-    CAN_ID_1 = CAN_1,
-    CAN_ID_2 = CAN_2
-} en_CAN_unitId;
-
-/**
- * @brief CAN ID format definition
- */
-typedef enum 
-{
-    STD_ID_FORMAT = 0,  /**< Use standard ID format (11 bit ID) */
-    EXT_ID_FORMAT = 1   /**< Use extended ID format (29 bit ID) */
-} CAN_ID_FORMAT_Type;
-
-/**
- * @brief AFLUT Entry type definition
- */
-typedef enum 
-{
-    FULLCAN_ENTRY = 0,
-    EXPLICIT_STANDARD_ENTRY,
-    GROUP_STANDARD_ENTRY,
-    EXPLICIT_EXTEND_ENTRY,
-    GROUP_EXTEND_ENTRY,
-} AFLUT_ENTRY_Type;
-
-/**
- * @brief Symbolic names for type of CAN message
- */
-typedef enum 
-{
-    DATA_FRAME = 0,     /**< Data frame */
-    REMOTE_FRAME = 1    /**< Remote frame */
-} CAN_FRAME_Type;
-
-/**
- * @brief CAN Control status definition
- */
-typedef enum 
-{
-    CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */
-    CANCTRL_INT_CAP,        /**< CAN Interrupt and Capture */
-    CANCTRL_ERR_WRN,        /**< CAN Error Warning Limit */
-    CANCTRL_STS             /**< CAN Control Status */
-} CAN_CTRL_STS_Type;
-
-/**
- * @brief Central CAN status type definition
- */
-typedef enum 
-{
-    CANCR_TX_STS = 0,   /**< Central CAN Tx Status */
-    CANCR_RX_STS,       /**< Central CAN Rx Status */
-    CANCR_MS            /**< Central CAN Miscellaneous Status */
-} CAN_CR_STS_Type;
-
-/**
- * @brief FullCAN Interrupt Capture type definition
- */
-typedef enum
-{
-    FULLCAN_IC0,    /**< FullCAN Interrupt and Capture 0 */
-    FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */
-}FullCAN_IC_Type;
-
-/**
- * @brief CAN interrupt enable type definition
- */
-typedef enum 
-{
-    CANINT_RIE = 0,     /**< CAN Receiver Interrupt Enable */
-    CANINT_TIE1,        /**< CAN Transmit Interrupt Enable */
-    CANINT_EIE,         /**< CAN Error Warning Interrupt Enable */
-    CANINT_DOIE,        /**< CAN Data Overrun Interrupt Enable */
-    CANINT_WUIE,        /**< CAN Wake-Up Interrupt Enable */
-    CANINT_EPIE,        /**< CAN Error Passive Interrupt Enable */
-    CANINT_ALIE,        /**< CAN Arbitration Lost Interrupt Enable */
-    CANINT_BEIE,        /**< CAN Bus Error Inter rupt Enable */
-    CANINT_IDIE,        /**< CAN ID Ready Interrupt Enable */
-    CANINT_TIE2,        /**< CAN Transmit Interrupt Enable for Buffer2 */
-    CANINT_TIE3,        /**< CAN Transmit Interrupt Enable for Buffer3 */
-    CANINT_FCE          /**< FullCAN Interrupt Enable */
-} CAN_INT_EN_Type;
-
-/**
- * @brief Acceptance Filter Mode type definition
- */
-typedef enum 
-{
-    CAN_NORMAL = 0,     /**< Normal Mode */
-    CAN_ACC_OFF,        /**< Acceptance Filter Off Mode */
-    CAN_ACC_BP,             /**< Acceptance Fileter Bypass Mode */
-    CAN_EFCAN           /**< FullCAN Mode Enhancement */
-} CAN_AFMODE_Type;
-
-/**
- * @brief CAN Mode Type definition
- */
-typedef enum 
-{
-    CAN_OPERATING_MODE = 0,     /**< Operating Mode */
-    CAN_RESET_MODE,             /**< Reset Mode */
-    CAN_LISTENONLY_MODE,        /**< Listen Only Mode */
-    CAN_SELFTEST_MODE,          /**< Seft Test Mode */
-    CAN_TXPRIORITY_MODE,        /**< Transmit Priority Mode */
-    CAN_SLEEP_MODE,             /**< Sleep Mode */
-    CAN_RXPOLARITY_MODE,        /**< Receive Polarity Mode */
-    CAN_TEST_MODE               /**< Test Mode */
-} CAN_MODE_Type;
-
-/**
- * @brief Error values that functions can return
- */
-typedef enum 
-{
-    CAN_OK = 1,                 /**< No error */
-    CAN_OBJECTS_FULL_ERROR,     /**< No more rx or tx objects available */
-    CAN_FULL_OBJ_NOT_RCV,       /**< Full CAN object not received */
-    CAN_NO_RECEIVE_DATA,        /**< No have receive data available */
-    CAN_AF_ENTRY_ERROR,         /**< Entry load in AFLUT is unvalid */
-    CAN_CONFLICT_ID_ERROR,      /**< Conflict ID occur */
-    CAN_ENTRY_NOT_EXIT_ERROR    /**< Entry remove outo AFLUT is not exit */
-} CAN_ERROR;
-
-/**
- * @brief Pin Configuration structure
- */
-typedef struct 
-{
-    uint8_t RD;             /**< Serial Inputs, from CAN transceivers, should be:
-                             ** For CAN1:
-                             - CAN_RD1_P0_0: RD pin is on P0.0
-                             - CAN_RD1_P0_21 : RD pin is on P0.21
-                             ** For CAN2:
-                             - CAN_RD2_P0_4: RD pin is on P0.4
-                             - CAN_RD2_P2_7: RD pin is on P2.7
-                             */
-    uint8_t TD;             /**< Serial Outputs, To CAN transceivers, should be:
-                             ** For CAN1:
-                             - CAN_TD1_P0_1: TD pin is on P0.1
-                             - CAN_TD1_P0_22: TD pin is on P0.22
-                             ** For CAN2:
-                             - CAN_TD2_P0_5: TD pin is on P0.5
-                             - CAN_TD2_P2_8: TD pin is on P2.8
-                             */
-} CAN_PinCFG_Type;
-
-/**
- * @brief CAN message object structure
- */
-typedef struct 
-{
-    uint32_t id;            /**< 29 bit identifier, it depend on "format" value
-                                 - if format = STD_ID_FORMAT, id should be 11 bit identifier
-                                 - if format = EXT_ID_FORMAT, id should be 29 bit identifier
-                             */
-    uint8_t dataA[4];       /**< Data field A */
-    uint8_t dataB[4];       /**< Data field B */
-    uint8_t len;            /**< Length of data field in bytes, should be:
-                                 - 0000b-0111b: 0-7 bytes
-                                 - 1xxxb: 8 bytes
-                            */
-    uint8_t format;         /**< Identifier Format, should be:
-                                 - STD_ID_FORMAT: Standard ID - 11 bit format
-                                 - EXT_ID_FORMAT: Extended ID - 29 bit format
-                            */
-    uint8_t type;           /**< Remote Frame transmission, should be:
-                                 - DATA_FRAME: the number of data bytes called out by the DLC
-                                 field are send from the CANxTDA and CANxTDB registers
-                                 - REMOTE_FRAME: Remote Frame is sent
-                            */
-} CAN_MSG_Type;
-
-/**
- * @brief FullCAN Entry structure
- */
-typedef struct 
-{
-    uint8_t controller;     /**< CAN Controller, should be:
-                                 - CAN1_CTRL: CAN1 Controller
-                                 - CAN2_CTRL: CAN2 Controller
-                            */
-    uint8_t disable;        /**< Disable bit, should be:
-                                 - MSG_ENABLE: disable bit = 0
-                                 - MSG_DISABLE: disable bit = 1
-                            */
-    uint16_t id_11;         /**< Standard ID, should be 11-bit value */
-} FullCAN_Entry;
-
-/**
- * @brief Standard ID Frame Format Entry structure
- */
-typedef struct 
-{
-    uint8_t controller;     /**< CAN Controller, should be:
-                                 - CAN1_CTRL: CAN1 Controller
-                                 - CAN2_CTRL: CAN2 Controller
-                            */
-    uint8_t disable;        /**< Disable bit, should be:
-                                 - MSG_ENABLE: disable bit = 0
-                                 - MSG_DISABLE: disable bit = 1
-                            */
-    uint16_t id_11;         /**< Standard ID, should be 11-bit value */
-} SFF_Entry;
-
-/**
- * @brief Group of Standard ID Frame Format Entry structure
- */
-typedef struct 
-{
-    uint8_t controller1;    /**< First CAN Controller, should be:
-                                 - CAN1_CTRL: CAN1 Controller
-                                 - CAN2_CTRL: CAN2 Controller
-                            */
-    uint8_t disable1;       /**< First Disable bit, should be:
-                                 - MSG_ENABLE: disable bit = 0)
-                                 - MSG_DISABLE: disable bit = 1
-                            */
-    uint16_t lowerID;       /**< ID lower bound, should be 11-bit value */
-    uint8_t controller2;    /**< Second CAN Controller, should be:
-                                 - CAN1_CTRL: CAN1 Controller
-                                 - CAN2_CTRL: CAN2 Controller
-                            */
-    uint8_t disable2;       /**< Second Disable bit, should be:
-                                 - MSG_ENABLE: disable bit = 0
-                                 - MSG_DISABLE: disable bit = 1
-                            */
-    uint16_t upperID;       /**< ID upper bound, should be 11-bit value and
-                                 equal or greater than lowerID
-                            */
-} SFF_GPR_Entry;
-
-/**
- * @brief Extended ID Frame Format Entry structure
- */
-typedef struct 
-{
-    uint8_t controller;     /**< CAN Controller, should be:
-                                 - CAN1_CTRL: CAN1 Controller
-                                 - CAN2_CTRL: CAN2 Controller
-                            */
-    uint32_t ID_29;         /**< Extend ID, shoud be 29-bit value */
-} EFF_Entry;
-
-
-/**
- * @brief Group of Extended ID Frame Format Entry structure
- */
-typedef struct 
-{
-    uint8_t controller1;    /**< First CAN Controller, should be:
-                                 - CAN1_CTRL: CAN1 Controller
-                                 - CAN2_CTRL: CAN2 Controller
-                            */
-    uint8_t controller2;    /**< Second Disable bit, should be:
-                                 - MSG_ENABLE: disable bit = 0(default)
-                                 - MSG_DISABLE: disable bit = 1
-                            */
-    uint32_t lowerEID;      /**< Extended ID lower bound, should be 29-bit value */
-    uint32_t upperEID;      /**< Extended ID upper bound, should be 29-bit value */
-} EFF_GPR_Entry;
-
-
-/**
- * @brief Acceptance Filter Section Table structure
- */
-typedef struct 
-{
-    FullCAN_Entry* FullCAN_Sec;     /**< The pointer point to FullCAN_Entry */
-    uint8_t FC_NumEntry;            /**< FullCAN Entry Number */
-    SFF_Entry* SFF_Sec;             /**< The pointer point to SFF_Entry */
-    uint8_t SFF_NumEntry;           /**< Standard ID Entry Number */
-    SFF_GPR_Entry* SFF_GPR_Sec;     /**< The pointer point to SFF_GPR_Entry */
-    uint8_t SFF_GPR_NumEntry;       /**< Group Standard ID Entry Number */
-    EFF_Entry* EFF_Sec;             /**< The pointer point to EFF_Entry */
-    uint8_t EFF_NumEntry;           /**< Extended ID Entry Number */
-    EFF_GPR_Entry* EFF_GPR_Sec;     /**< The pointer point to EFF_GPR_Entry */
-    uint8_t EFF_GPR_NumEntry;       /**< Group Extended ID Entry Number */
-} AF_SectionDef;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup CAN_Public_Functions CAN Public Functions
- * @{
- */
-
-/* Init/DeInit CAN peripheral -----------*/
-void CAN_Init(uint8_t canId, uint32_t baudrate);
-void CAN_DeInit(uint8_t canId);
-
-/* CAN messages functions ---------------*/
-Status CAN_SendMsg(uint8_t canId, CAN_MSG_Type *CAN_Msg);
-Status CAN_ReceiveMsg(uint8_t canId, CAN_MSG_Type *CAN_Msg);
-CAN_ERROR FCAN_ReadObj(CAN_MSG_Type *CAN_Msg);
-
-/* CAN configure functions ---------------*/
-void CAN_ModeConfig(uint8_t canId, CAN_MODE_Type mode,
-                                                FunctionalState NewState);
-void CAN_SetAFMode(CAN_AFMODE_Type AFmode);
-void CAN_SetCommand(uint8_t canId, uint32_t CMRType);
-
-/* AFLUT functions ---------------------- */
-CAN_ERROR CAN_SetupAFLUT(AF_SectionDef* AFSection);
-CAN_ERROR CAN_LoadFullCANEntry(uint8_t canId, uint16_t ID);
-CAN_ERROR CAN_LoadExplicitEntry(uint8_t canId, uint32_t ID,
-                                                    CAN_ID_FORMAT_Type format);
-CAN_ERROR CAN_LoadGroupEntry(uint8_t canId, uint32_t lowerID,
-                                        uint32_t upperID, CAN_ID_FORMAT_Type format);
-CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position);
-
-/* CAN interrupt functions -----------------*/
-void CAN_IRQCmd(uint8_t canId, CAN_INT_EN_Type arg, FunctionalState NewState);
-uint32_t CAN_IntGetStatus(uint8_t canId);
-
-/* CAN get status functions ----------------*/
-IntStatus CAN_FullCANIntGetStatus (void);
-uint32_t CAN_FullCANPendGetStatus (FullCAN_IC_Type type);
-uint32_t CAN_GetCTRLStatus(uint8_t canId, CAN_CTRL_STS_Type arg);
-uint32_t CAN_GetCRStatus(CAN_CR_STS_Type arg);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* LPC_CAN_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_clkpwr.h

@@ -1,248 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_clkpwr.h            2011-06-02
-*//**
-* @file     lpc_clkpwr.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for Clock and Power Control firmware library on 
-*           LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup CLKPWR    CLKPWR (Clock Power)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_CLKPWR_H_
-#define __LPC_CLKPWR_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-#include "system_LPC407x_8x_177x_8x.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
- * @{
- */
-
-/********************************************************************
-* Clock Source Selection Definitions
-**********************************************************************/
-#define CLKPWR_CLKSRCSEL_IRCOSC     ((uint32_t)(0))
-#define CLKPWR_CLKSRCSEL_MAINOSC    ((uint32_t)(1))
-
-/********************************************************************
-* Clock type/domain Definitions (calculated from input and pre-configuration
-* parameter(s)
-**********************************************************************/
-#define CLKPWR_CLKTYPE_CPU          ((uint32_t)(0))
-#define CLKPWR_CLKTYPE_PER          ((uint32_t)(1))
-#define CLKPWR_CLKTYPE_EMC          ((uint32_t)(2))
-#define CLKPWR_CLKTYPE_USB          ((uint32_t)(3))
-
-/********************************************************************
-* Power Control for Peripherals Definitions
-**********************************************************************/
-/** LCD controller power/clock control bit */
-#define CLKPWR_PCONP_PCLCD      ((uint32_t)(1<<0))
-
-/** Timer/Counter 0 power/clock control bit */
-#define CLKPWR_PCONP_PCTIM0     ((uint32_t)(1<<1))
-
-/* Timer/Counter 1 power/clock control bit */
-#define CLKPWR_PCONP_PCTIM1     ((uint32_t)(1<<2))
-
-/** UART0 power/clock control bit */
-#define CLKPWR_PCONP_PCUART0    ((uint32_t)(1<<3))
-
-/** UART1 power/clock control bit */
-#define CLKPWR_PCONP_PCUART1    ((uint32_t)(1<<4))
-
-/** PWM0 power/clock control bit */
-#define CLKPWR_PCONP_PCPWM0     ((uint32_t)(1<<5))
-
-/** PWM1 power/clock control bit */
-#define CLKPWR_PCONP_PCPWM1     ((uint32_t)(1<<6))
-
-/** The I2C0 interface power/clock control bit */
-#define CLKPWR_PCONP_PCI2C0     ((uint32_t)(1<<7))
-
-/** UART4 power/clock control bit */
-#define CLKPWR_PCONP_PCUART4    ((uint32_t)(1<<8))
-
-/** The RTC power/clock control bit */
-#define CLKPWR_PCONP_PCRTC      ((uint32_t)(1<<9))
-
-/** The SSP1 interface power/clock control bit */
-#define CLKPWR_PCONP_PCSSP1     ((uint32_t)(1<<10))
-
-/** External Memory controller power/clock control bit */
-#define CLKPWR_PCONP_PCEMC      ((uint32_t)(1<<11))
-
-/** A/D converter 0 (ADC0) power/clock control bit */
-#define CLKPWR_PCONP_PCADC      ((uint32_t)(1<<12))
-
-/** CAN Controller 1 power/clock control bit */
-#define CLKPWR_PCONP_PCAN1      ((uint32_t)(1<<13))
-
-/** CAN Controller 2 power/clock control bit */
-#define CLKPWR_PCONP_PCAN2  ((uint32_t)(1<<14))
-
-/** GPIO power/clock control bit */
-#define CLKPWR_PCONP_PCGPIO     ((uint32_t)(1<<15))
-
-/** Motor Control PWM */
-#define CLKPWR_PCONP_PCMCPWM    ((uint32_t)(1<<17))
-
-/** Quadrature Encoder Interface power/clock control bit */
-#define CLKPWR_PCONP_PCQEI      ((uint32_t)(1<<18))
-
-/** The I2C1 interface power/clock control bit */
-#define CLKPWR_PCONP_PCI2C1     ((uint32_t)(1<<19))
-
-/** The SSP2 interface power/clock control bit */
-#define CLKPWR_PCONP_PCSSP2     ((uint32_t)(1<<20))
-
-/** The SSP0 interface power/clock control bit */
-#define CLKPWR_PCONP_PCSSP0     ((uint32_t)(1<<21))
-
-/** Timer 2 power/clock control bit */
-#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
-
-/** Timer 3 power/clock control bit */
-#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
-
-/** UART 2 power/clock control bit */
-#define CLKPWR_PCONP_PCUART2    ((uint32_t)(1<<24))
-
-/** UART 3 power/clock control bit */
-#define CLKPWR_PCONP_PCUART3    ((uint32_t)(1<<25))
-
-/** I2C interface 2 power/clock control bit */
-#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
-
-/** I2S interface power/clock control bit*/
-#define CLKPWR_PCONP_PCI2S      ((uint32_t)(1<<27))
-
-/** SD card interface power/clock control bit */
-#define CLKPWR_PCONP_PCSDC      ((uint32_t)(1<<28))
-
-/** GP DMA function power/clock control bit*/
-#define  CLKPWR_PCONP_PCGPDMA   ((uint32_t)(1<<29))
-
-/** Ethernet block power/clock control bit*/
-#define  CLKPWR_PCONP_PCENET    ((uint32_t)(1<<30))
-
-/** USB interface power/clock control bit*/
-#define  CLKPWR_PCONP_PCUSB     ((uint32_t)(1<<31))
-
-/********************************************************************
-* Power Control for Peripherals Definitions
-**********************************************************************/
-#define CLKPWR_RSTCON0_LCD      ((uint32_t)(0))
-#define CLKPWR_RSTCON0_TIM0     ((uint32_t)(1))
-#define CLKPWR_RSTCON0_TIM1     ((uint32_t)(2))
-#define CLKPWR_RSTCON0_UART0    ((uint32_t)(3))
-#define CLKPWR_RSTCON0_UART1    ((uint32_t)(4))
-#define CLKPWR_RSTCON0_PWM0     ((uint32_t)(5))
-#define CLKPWR_RSTCON0_PWM1     ((uint32_t)(6))
-#define CLKPWR_RSTCON0_I2C0     ((uint32_t)(7))
-#define CLKPWR_RSTCON0_UART4    ((uint32_t)(8))
-#define CLKPWR_RSTCON0_RTC      ((uint32_t)(9))
-#define CLKPWR_RSTCON0_SSP1     ((uint32_t)(10))
-#define CLKPWR_RSTCON0_EMC      ((uint32_t)(11))
-#define CLKPWR_RSTCON0_ADC      ((uint32_t)(12))
-#define CLKPWR_RSTCON0_CAN1     ((uint32_t)(13))
-#define CLKPWR_RSTCON0_CAN2     ((uint32_t)(14))
-#define CLKPWR_RSTCON0_GPIO     ((uint32_t)(15))
-#define CLKPWR_RSTCON0_MCPWM    ((uint32_t)(17))
-#define CLKPWR_RSTCON0_QEI      ((uint32_t)(18))
-#define CLKPWR_RSTCON0_I2C1     ((uint32_t)(19))
-#define CLKPWR_RSTCON0_SSP2     ((uint32_t)(20))
-#define CLKPWR_RSTCON0_SSP0     ((uint32_t)(21))
-#define CLKPWR_RSTCON0_TIM2     ((uint32_t)(22))
-#define CLKPWR_RSTCON0_TIM3     ((uint32_t)(23))
-#define CLKPWR_RSTCON0_UART2    ((uint32_t)(24))
-#define CLKPWR_RSTCON0_UART3    ((uint32_t)(25))
-#define CLKPWR_RSTCON0_I2C2     ((uint32_t)(26))
-#define CLKPWR_RSTCON0_I2S      ((uint32_t)(27))
-#define CLKPWR_RSTCON0_SDC      ((uint32_t)(28))
-#define CLKPWR_RSTCON0_GPDMA    ((uint32_t)(29))
-#define CLKPWR_RSTCON0_ENET     ((uint32_t)(30))
-#define CLKPWR_RSTCON0_USB      ((uint32_t)(31))
-
-#define CLKPWR_RSTCON1_IOCON    ((uint32_t)(32))
-#define CLKPWR_RSTCON1_DAC      ((uint32_t)(33))
-#define CLKPWR_RSTCON1_CANACC   ((uint32_t)(34))
-/**
- * @}
- */
- 
-/* External clock variable from system_LPC407x_8x_177x_8x.h */
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)   */
-extern uint32_t PeripheralClock;     /*!< Peripheral Clock Frequency (Pclk)     */
-extern uint32_t EMCClock;        /*!< EMC Clock Frequency                       */
-
-/* External clock variable from lpc_clkpwr.h */
-extern uint32_t USBClock;       /*!< USB Frequency                              */
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
- * @{
- */
-
-void CLKPWR_SetCLKDiv(uint8_t ClkType, uint8_t DivVal);
-uint32_t CLKPWR_GetCLK(uint8_t ClkType);
-void CLKPWR_ConfigPPWR(uint32_t PPType, FunctionalState NewState);
-void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState);
-void CLKPWR_Sleep(void);
-void CLKPWR_DeepSleep(void);
-void CLKPWR_PowerDown(void);
-void CLKPWR_DeepPowerDown(void);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_CLKPWR_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_crc.h

@@ -1,110 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_crc.h           2011-06-02
-*//**
-* @file     lpc_crc.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for CRC firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup CRC   CRC (Cyclic Redundancy Check)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC__CRC_H_
-#define __LPC__CRC_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Private macros ------------------------------------------------------------- */
-/** @defgroup CRC_Private_Macros CRC Private Macros
- * @{
- */
-
-/* -------------------------- BIT DEFINITIONS ----------------------------------- */
-/*********************************************************************//**
- * Macro defines for CRC mode register
- **********************************************************************/
-#define CRC_BIT_RVS_WR          (1<<2)
-#define CRC_CMPL_WR             (1<<3)
-#define CRC_BIT_RVS_SUM         (1<<4)
-#define CRC_CMPL_SUM            (1<<5)
-
-
-/**
- * @}
- */
-/* Private types ------------------------------------------------------------- */
-typedef enum
-{
-    CRC_POLY_CRCCCITT = 0,          /** CRC CCITT polynomial */
-    CRC_POLY_CRC16,                 /** CRC-16 polynomial */
-    CRC_POLY_CRC32                  /** CRC-32 polynomial */
-}CRC_Type;
-
-typedef enum
-{
-    CRC_WR_8BIT = 1,                /** 8-bit write: 1-cycle operation */
-    CRC_WR_16BIT = 2,                   /** 16-bit write: 2-cycle operation */
-    CRC_WR_32BIT = 4,                   /** 32-bit write: 4-cycle operation */
-}CRC_WR_SIZE;
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup CRC_Public_Functions CRC Public Functions
- * @{
- */
-void CRC_Init(CRC_Type CRCType);
-void CRC_Reset(void);
-uint32_t CRC_CalcDataChecksum(uint32_t data, CRC_WR_SIZE SizeType);
-uint32_t CRC_CalcBlockChecksum(void *blockdata, uint32_t blocksize, CRC_WR_SIZE SizeType);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_CRC_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_dac.h

@@ -1,165 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_dac.h           2011-06-02
-*//**
-* @file     lpc_dac.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for DAC firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup DAC DAC (Digital-to-Analog Converter)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_DAC_H_
-#define __LPC_DAC_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup DAC_Private_Macros DAC Private Macros
- * @{
- */
-
-/** After the selected settling time after this field is written with a
-new VALUE, the voltage on the AOUT pin (with respect to VSSA)
-is VALUE/1024 × VREF */
-#define DAC_VALUE(n)        ((uint32_t)((n&0x3FF)<<6))
-
-/** If this bit = 0: The settling time of the DAC is 1 microsecond max,
- * and the maximum current is 700 microAmpere
- * If this bit = 1: The settling time of the DAC is 2.5 microsecond
- * and the maximum current is 350 microAmpere */
-#define DAC_BIAS_EN         ((uint32_t)(1<<16))
-
-/** Value to reload interrupt DMA counter */
-#define DAC_CCNT_VALUE(n)  ((uint32_t)(n&0xffff))
-
-/** DCAR double buffering */
-#define DAC_DBLBUF_ENA      ((uint32_t)(1<<1))
-
-/** DCAR Time out count enable */
-#define DAC_CNT_ENA         ((uint32_t)(1<<2))
-
-/** DCAR DMA access */
-#define DAC_DMA_ENA         ((uint32_t)(1<<3))
-
-/** DCAR DACCTRL mask bit */
-#define DAC_DACCTRL_MASK    ((uint32_t)(0x0F))
-
-/** Macro to determine if it is valid DAC peripheral */
-#define PARAM_DACx(n)       (((uint32_t *)n)==((uint32_t *)LPC_DAC))
-
-/** Macro to check DAC current optional parameter */
-#define PARAM_DAC_CURRENT_OPT(OPTION) ((OPTION == DAC_MAX_CURRENT_700uA)\
-                                            ||(OPTION == DAC_MAX_CURRENT_350uA))
-/**
- * @}
- */
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup DAC_Public_Types DAC Public Types
- * @{
- */
-
-/**
- * @brief Current option in DAC configuration option */
-typedef enum
-{
-    DAC_MAX_CURRENT_700uA = 0,  /*!< The settling time of the DAC is 1 us max,
-                                and the maximum current is 700 uA */
-    DAC_MAX_CURRENT_350uA       /*!< The settling time of the DAC is 2.5 us
-                                and the maximum current is 350 uA */
-} DAC_CURRENT_OPT;
-
-/**
- * @brief Configuration for DAC converter control register */
-typedef struct
-{
-
-    uint8_t DBLBUF_ENA;     /**<
-                            - If 0: Disable DACR double buffering
-
-                            - If 1: when bit CNT_ENA, enable DACR double buffering feature
-                            */
-    uint8_t CNT_ENA;        /*!<
-                            - If 0: Time out counter is disable
-
-                            -1: Time out conter is enable
-                            */
-    uint8_t DMA_ENA;        /*!<
-                            - If 0: DMA access is disable
-
-                            - If 1: DMA burst request
-                            */
-    uint8_t RESERVED;
-
-} DAC_CONVERTER_CFG_Type;
-
-/**
- * @}
- */
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup DAC_Public_Functions DAC Public Functions
- * @{
- */
-
-void    DAC_Init(uint8_t DAC_Id);
-void    DAC_UpdateValue (uint8_t DAC_Id, uint32_t dac_value);
-void    DAC_SetBias (uint8_t DAC_Id,uint32_t bias);
-void    DAC_ConfigDAConverterControl (uint8_t DAC_Id,DAC_CONVERTER_CFG_Type *DAC_ConverterConfigStruct);
-void    DAC_SetDMATimeOut(uint8_t DAC_Id,uint32_t time_out);
-uint8_t DAC_IsIntRequested(uint8_t DAC_Id);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_DAC_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_eeprom.h

@@ -1,152 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_eeprom.h            2011-06-02
-*//**
-* @file     lpc_eeprom.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for EEPROM firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup EEPROM    EEPROM (Electrically Erasable Programmable Read-Only Memory)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_EEPROM_H_
-#define __LPC_EEPROM_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Private macros ------------------------------------------------------------- */
-/** @defgroup EEPROM_Private_Macros EEPROM Private Macros
- * @{
- */
-
-/* -------------------------- BIT DEFINITIONS --------------------------------- */
-/*********************************************************************//**
- * Macro defines for EEPROM command register
- **********************************************************************/
-#define EEPROM_CMD_8_BIT_READ           (0)
-#define EEPROM_CMD_16_BIT_READ          (1)
-#define EEPROM_CMD_32_BIT_READ          (2)
-#define EEPROM_CMD_8_BIT_WRITE          (3)
-#define EEPROM_CMD_16_BIT_WRITE         (4)
-#define EEPROM_CMD_32_BIT_WRITE         (5)
-#define EEPROM_CMD_ERASE_PRG_PAGE       (6)
-
-#define EEPROM_CMD_RDPREFETCH           (1<<3)
-
-#define EEPROM_PAGE_SIZE                64
-#define EEPROM_PAGE_NUM                 63
-
-/*********************************************************************//**
- * Macro defines for EEPROM address register
- **********************************************************************/
-#define EEPROM_PAGE_OFFSET(n)           (n&0x3F)
-#define EEPROM_PAGE_ADRESS(n)           ((n&0x3F)<<6)
-
-/*********************************************************************//**
- * Macro defines for EEPROM write data register
- **********************************************************************/
-#define EEPROM_WDATA_8_BIT(n)           (n&0x000000FF)
-#define EEPROM_WDATA_16_BIT(n)          (n&0x0000FFFF)
-#define EEPROM_WDATA_32_BIT(n)          (n&0xFFFFFFFF)
-
-/*********************************************************************//**
- * Macro defines for EEPROM read data register
- **********************************************************************/
-#define EEPROM_RDATA_8_BIT(n)           (n&0x000000FF)
-#define EEPROM_RDATA_16_BIT(n)          (n&0x0000FFFF)
-#define EEPROM_RDATA_32_BIT(n)          (n&0xFFFFFFFF)
-
-/*********************************************************************//**
- * Macro defines for EEPROM power down register
- **********************************************************************/
-#define EEPROM_PWRDWN                   (1<<0)
-
-#define EEPROM_ENDOF_RW                 (26)
-#define EEPROM_ENDOF_PROG               (28)
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup EEPROM_Public_Types EEPROM Public Types
- * @{
- */
-
-typedef enum
-{
-    MODE_8_BIT = 0,
-    MODE_16_BIT,
-    MODE_32_BIT
-}EEPROM_Mode_Type;
-
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup EEPROM_Public_Functions EEPROM Public Functions
- * @{
- */
-
-void EEPROM_Init(void);
-void EEPROM_Write(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size);
-void EEPROM_Read(uint16_t page_offset, uint16_t page_address, void* data, EEPROM_Mode_Type mode, uint32_t size);
-void EEPROM_Erase(uint16_t address);
-void EEPROM_PowerDown(FunctionalState NewState);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_EEPROM_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emac.h

@@ -1,616 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_emac.h          2011-06-02
-*//**
-* @file     lpc_emac.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for Ethernet MAC firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup EMAC  EMAC (Ethernet Media Access Controller)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_EMAC_H_
-#define __LPC_EMAC_H_
-
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @defgroup EMAC_Private_Macros EMAC Private Macros
- * @{
- */
-
-/* Ethernet MAC register definitions --------------------------------------------------------------------- */
-/* MAC Configuration Register 1 */
-#define EMAC_MAC1_MASK      0xcf1f      /*MAC1 register mask*/
-#define EMAC_MAC1_REC_EN         0x00000001  /**< Receive Enable                    */
-#define EMAC_MAC1_PASS_ALL       0x00000002  /**< Pass All Receive Frames           */
-#define EMAC_MAC1_RX_FLOWC       0x00000004  /**< RX Flow Control                   */
-#define EMAC_MAC1_TX_FLOWC       0x00000008  /**< TX Flow Control                   */
-#define EMAC_MAC1_LOOPB          0x00000010  /**< Loop Back Mode                    */
-#define EMAC_MAC1_RES_TX         0x00000100  /**< Reset TX Logic                    */
-#define EMAC_MAC1_RES_MCS_TX     0x00000200  /**< Reset MAC TX Control Sublayer     */
-#define EMAC_MAC1_RES_RX         0x00000400  /**< Reset RX Logic                    */
-#define EMAC_MAC1_RES_MCS_RX     0x00000800  /**< Reset MAC RX Control Sublayer     */
-#define EMAC_MAC1_SIM_RES        0x00004000  /**< Simulation Reset                  */
-#define EMAC_MAC1_SOFT_RES       0x00008000  /**< Soft Reset MAC                    */
-
-/* MAC Configuration Register 2 */
-#define EMAC_MAC2_MASK      0x73ff      /*MAC2 register mask*/
-#define EMAC_MAC2_FULL_DUP       0x00000001  /**< Full-Duplex Mode                  */
-#define EMAC_MAC2_FRM_LEN_CHK    0x00000002  /**< Frame Length Checking             */
-#define EMAC_MAC2_HUGE_FRM_EN    0x00000004  /**< Huge Frame Enable                 */
-#define EMAC_MAC2_DLY_CRC        0x00000008  /**< Delayed CRC Mode                  */
-#define EMAC_MAC2_CRC_EN         0x00000010  /**< Append CRC to every Frame         */
-#define EMAC_MAC2_PAD_EN         0x00000020  /**< Pad all Short Frames              */
-#define EMAC_MAC2_VLAN_PAD_EN    0x00000040  /**< VLAN Pad Enable                   */
-#define EMAC_MAC2_ADET_PAD_EN    0x00000080  /**< Auto Detect Pad Enable            */
-#define EMAC_MAC2_PPREAM_ENF     0x00000100  /**< Pure Preamble Enforcement         */
-#define EMAC_MAC2_LPREAM_ENF     0x00000200  /**< Long Preamble Enforcement         */
-#define EMAC_MAC2_NO_BACKOFF     0x00001000  /**< No Backoff Algorithm              */
-#define EMAC_MAC2_BACK_PRESSURE  0x00002000  /**< Backoff Presurre / No Backoff     */
-#define EMAC_MAC2_EXCESS_DEF     0x00004000  /**< Excess Defer                      */
-
-/* Back-to-Back Inter-Packet-Gap Register */
-/** Programmable field representing the nibble time offset of the minimum possible period
- * between the end of any transmitted packet to the beginning of the next */
-#define EMAC_IPGT_BBIPG(n)      (n&0x7F)
-
-/** Recommended value for Full Duplex of Programmable field representing the nibble time
- * offset of the minimum possible period between the end of any transmitted packet to the
- * beginning of the next */
-#define EMAC_IPGT_FULL_DUP      (EMAC_IPGT_BBIPG(0x15))
-
-/** Recommended value for Half Duplex of Programmable field representing the nibble time
- * offset of the minimum possible period between the end of any transmitted packet to the
- * beginning of the next */
-#define EMAC_IPGT_HALF_DUP      (EMAC_IPGT_BBIPG(0x12))
-
-/* Non Back-to-Back Inter-Packet-Gap Register */
-/** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
-#define EMAC_IPGR_NBBIPG_P2(n)  (n&0x7F)
-
-/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
-#define EMAC_IPGR_P2_DEF        (EMAC_IPGR_NBBIPG_P2(0x12))
-
-/** Programmable field representing the optional carrierSense window referenced in
- * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
-#define EMAC_IPGR_NBBIPG_P1(n)  ((n&0x7F)<<8)
-
-/** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
-#define EMAC_IPGR_P1_DEF        EMAC_IPGR_NBBIPG_P1(0x0C)
-
-/* Collision Window/Retry Register */
-/** Programmable field specifying the number of retransmission attempts following a collision before
- * aborting the packet due to excessive collisions */
-#define EMAC_CLRT_MAX_RETX(n)   (n&0x0F)
-
-/** Programmable field representing the slot time or collision window during which collisions occur
- * in properly configured networks */
-#define EMAC_CLRT_COLL(n)       ((n&0x3F)<<8)
-
-/** Default value for Collision Window / Retry register */
-#define EMAC_CLRT_DEF           ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
-
-/* Maximum Frame Register */
-/** Represents a maximum receive frame of 1536 octets */
-#define EMAC_MAXF_MAXFRMLEN(n)  (n&0xFFFF)
-#define EMAC_MAXF_MAXFRMLEN_DEF (0x6000)
-
-/* PHY Support Register */
-#define EMAC_SUPP_SPEED         0x00000100      /**< Reduced MII Logic Current Speed   */
-//#define EMAC_SUPP_RES_RMII      0x00000800    /**< Reset Reduced MII Logic           */
-
-/* Test Register */
-#define EMAC_TEST_SHCUT_PQUANTA  0x00000001     /**< Shortcut Pause Quanta             */
-#define EMAC_TEST_TST_PAUSE      0x00000002     /**< Test Pause                        */
-#define EMAC_TEST_TST_BACKP      0x00000004     /**< Test Back Pressure                */
-
-/* MII Management Configuration Register */
-#define EMAC_MCFG_SCAN_INC       0x00000001     /**< Scan Increment PHY Address        */
-#define EMAC_MCFG_SUPP_PREAM     0x00000002     /**< Suppress Preamble                 */
-#define EMAC_MCFG_CLK_SEL(n)     ((n&0x0F)<<2)  /**< Clock Select Field                 */
-#define EMAC_MCFG_RES_MII        0x00008000     /**< Reset MII Management Hardware     */
-#define EMAC_MCFG_MII_MAXCLK     2500000UL      /**< MII Clock max */
-
-/* MII Management Command Register */
-#define EMAC_MCMD_READ           0x00000001     /**< MII Read                          */
-#define EMAC_MCMD_SCAN           0x00000002     /**< MII Scan continuously             */
-
-#define EMAC_MII_WR_TOUT         0x00050000     /**< MII Write timeout count           */
-#define EMAC_MII_RD_TOUT         0x00050000     /**< MII Read timeout count            */
-
-/* MII Management Address Register */
-#define EMAC_MADR_REG_ADR(n)     (n&0x1F)       /**< MII Register Address field         */
-#define EMAC_MADR_PHY_ADR(n)     ((n&0x1F)<<8)  /**< PHY Address Field                  */
-
-/* MII Management Write Data Register */
-#define EMAC_MWTD_DATA(n)       (n&0xFFFF)      /**< Data field for MMI Management Write Data register */
-
-/* MII Management Read Data Register */
-#define EMAC_MRDD_DATA(n)       (n&0xFFFF)      /**< Data field for MMI Management Read Data register */
-
-/* MII Management Indicators Register */
-#define EMAC_MIND_BUSY           0x00000001     /**< MII is Busy                       */
-#define EMAC_MIND_SCAN           0x00000002     /**< MII Scanning in Progress          */
-#define EMAC_MIND_NOT_VAL        0x00000004     /**< MII Read Data not valid           */
-#define EMAC_MIND_MII_LINK_FAIL  0x00000008     /**< MII Link Failed                   */
-
-/* Station Address 0 Register */
-/* Station Address 1 Register */
-/* Station Address 2 Register */
-
-
-/* Control register definitions --------------------------------------------------------------------------- */
-/* Command Register */
-#define EMAC_CR_RX_EN            0x00000001     /**< Enable Receive                    */
-#define EMAC_CR_TX_EN            0x00000002     /**< Enable Transmit                   */
-#define EMAC_CR_REG_RES          0x00000008     /**< Reset Host Registers              */
-#define EMAC_CR_TX_RES           0x00000010     /**< Reset Transmit Datapath           */
-#define EMAC_CR_RX_RES           0x00000020     /**< Reset Receive Datapath            */
-#define EMAC_CR_PASS_RUNT_FRM    0x00000040     /**< Pass Runt Frames                  */
-#define EMAC_CR_PASS_RX_FILT     0x00000080     /**< Pass RX Filter                    */
-#define EMAC_CR_TX_FLOW_CTRL     0x00000100     /**< TX Flow Control                   */
-#define EMAC_CR_RMII             0x00000200     /**< Reduced MII Interface             */
-#define EMAC_CR_FULL_DUP         0x00000400     /**< Full Duplex                       */
-
-/* Status Register */
-#define EMAC_SR_RX_EN            0x00000001     /**< Enable Receive                    */
-#define EMAC_SR_TX_EN            0x00000002     /**< Enable Transmit                   */
-
-/* Receive Descriptor Base Address Register */
-//
-
-/* Receive Status Base Address Register */
-//
-
-/* Receive Number of Descriptors Register */
-//
-
-/* Receive Produce Index Register */
-//
-
-/* Receive Consume Index Register */
-//
-
-/* Transmit Descriptor Base Address Register */
-//
-
-/* Transmit Status Base Address Register */
-//
-
-/* Transmit Number of Descriptors Register */
-//
-
-/* Transmit Produce Index Register */
-//
-
-/* Transmit Consume Index Register */
-//
-
-/* Transmit Status Vector 0 Register */
-#define EMAC_TSV0_CRC_ERR        0x00000001  /**< CRC error                         */
-#define EMAC_TSV0_LEN_CHKERR     0x00000002  /**< Length Check Error                */
-#define EMAC_TSV0_LEN_OUTRNG     0x00000004  /**< Length Out of Range               */
-#define EMAC_TSV0_DONE           0x00000008  /**< Tramsmission Completed            */
-#define EMAC_TSV0_MCAST          0x00000010  /**< Multicast Destination             */
-#define EMAC_TSV0_BCAST          0x00000020  /**< Broadcast Destination             */
-#define EMAC_TSV0_PKT_DEFER      0x00000040  /**< Packet Deferred                   */
-#define EMAC_TSV0_EXC_DEFER      0x00000080  /**< Excessive Packet Deferral         */
-#define EMAC_TSV0_EXC_COLL       0x00000100  /**< Excessive Collision               */
-#define EMAC_TSV0_LATE_COLL      0x00000200  /**< Late Collision Occured            */
-#define EMAC_TSV0_GIANT          0x00000400  /**< Giant Frame                       */
-#define EMAC_TSV0_UNDERRUN       0x00000800  /**< Buffer Underrun                   */
-#define EMAC_TSV0_BYTES          0x0FFFF000  /**< Total Bytes Transferred           */
-#define EMAC_TSV0_CTRL_FRAME     0x10000000  /**< Control Frame                     */
-#define EMAC_TSV0_PAUSE          0x20000000  /**< Pause Frame                       */
-#define EMAC_TSV0_BACK_PRESS     0x40000000  /**< Backpressure Method Applied       */
-#define EMAC_TSV0_VLAN           0x80000000  /**< VLAN Frame                        */
-
-/* Transmit Status Vector 1 Register */
-#define EMAC_TSV1_BYTE_CNT       0x0000FFFF  /**< Transmit Byte Count               */
-#define EMAC_TSV1_COLL_CNT       0x000F0000  /**< Transmit Collision Count          */
-
-/* Receive Status Vector Register */
-#define EMAC_RSV_BYTE_CNT        0x0000FFFF  /**< Receive Byte Count                */
-#define EMAC_RSV_PKT_IGNORED     0x00010000  /**< Packet Previously Ignored         */
-#define EMAC_RSV_RXDV_SEEN       0x00020000  /**< RXDV Event Previously Seen        */
-#define EMAC_RSV_CARR_SEEN       0x00040000  /**< Carrier Event Previously Seen     */
-#define EMAC_RSV_REC_CODEV       0x00080000  /**< Receive Code Violation            */
-#define EMAC_RSV_CRC_ERR         0x00100000  /**< CRC Error                         */
-#define EMAC_RSV_LEN_CHKERR      0x00200000  /**< Length Check Error                */
-#define EMAC_RSV_LEN_OUTRNG      0x00400000  /**< Length Out of Range               */
-#define EMAC_RSV_REC_OK          0x00800000  /**< Frame Received OK                 */
-#define EMAC_RSV_MCAST           0x01000000  /**< Multicast Frame                   */
-#define EMAC_RSV_BCAST           0x02000000  /**< Broadcast Frame                   */
-#define EMAC_RSV_DRIB_NIBB       0x04000000  /**< Dribble Nibble                    */
-#define EMAC_RSV_CTRL_FRAME      0x08000000  /**< Control Frame                     */
-#define EMAC_RSV_PAUSE           0x10000000  /**< Pause Frame                       */
-#define EMAC_RSV_UNSUPP_OPC      0x20000000  /**< Unsupported Opcode                */
-#define EMAC_RSV_VLAN            0x40000000  /**< VLAN Frame                        */
-
-/* Flow Control Counter Register */
-#define EMAC_FCC_MIRR_CNT(n)            (n&0xFFFF)          /**< Mirror Counter                    */
-#define EMAC_FCC_PAUSE_TIM(n)           ((n&0xFFFF)<<16)    /**< Pause Timer                       */
-
-/* Flow Control Status Register */
-#define EMAC_FCS_MIRR_CNT(n)            (n&0xFFFF)          /**< Mirror Counter Current            */
-
-
-/* Receive filter register definitions -------------------------------------------------------- */
-/* Receive Filter Control Register */
-#define EMAC_RFC_UCAST_EN        0x00000001  /**< Accept Unicast Frames Enable      */
-#define EMAC_RFC_BCAST_EN        0x00000002  /**< Accept Broadcast Frames Enable    */
-#define EMAC_RFC_MCAST_EN        0x00000004  /**< Accept Multicast Frames Enable    */
-#define EMAC_RFC_UCAST_HASH_EN   0x00000008  /**< Accept Unicast Hash Filter Frames */
-#define EMAC_RFC_MCAST_HASH_EN   0x00000010  /**< Accept Multicast Hash Filter Fram.*/
-#define EMAC_RFC_PERFECT_EN      0x00000020  /**< Accept Perfect Match Enable       */
-#define EMAC_RFC_MAGP_WOL_EN     0x00001000  /**< Magic Packet Filter WoL Enable    */
-#define EMAC_RFC_PFILT_WOL_EN    0x00002000  /**< Perfect Filter WoL Enable         */
-
-/* Receive Filter WoL Status/Clear Registers */
-#define EMAC_WOL_UCAST           0x00000001  /**< Unicast Frame caused WoL          */
-#define EMAC_WOL_BCAST           0x00000002  /**< Broadcast Frame caused WoL        */
-#define EMAC_WOL_MCAST           0x00000004  /**< Multicast Frame caused WoL        */
-#define EMAC_WOL_UCAST_HASH      0x00000008  /**< Unicast Hash Filter Frame WoL     */
-#define EMAC_WOL_MCAST_HASH      0x00000010  /**< Multicast Hash Filter Frame WoL   */
-#define EMAC_WOL_PERFECT         0x00000020  /**< Perfect Filter WoL                */
-#define EMAC_WOL_RX_FILTER       0x00000080  /**< RX Filter caused WoL              */
-#define EMAC_WOL_MAG_PACKET      0x00000100  /**< Magic Packet Filter caused WoL    */
-#define EMAC_WOL_BITMASK         0x01BF     /**< Receive Filter WoL Status/Clear bitmasl value */
-
-/* Hash Filter Table LSBs Register */
-//
-
-/* Hash Filter Table MSBs Register */
-//
-
-
-/* Module control register definitions ---------------------------------------------------- */
-/* Interrupt Status/Enable/Clear/Set Registers */
-#define EMAC_INT_RX_OVERRUN      0x00000001  /**< Overrun Error in RX Queue         */
-#define EMAC_INT_RX_ERR          0x00000002  /**< Receive Error                     */
-#define EMAC_INT_RX_FIN          0x00000004  /**< RX Finished Process Descriptors   */
-#define EMAC_INT_RX_DONE         0x00000008  /**< Receive Done                      */
-#define EMAC_INT_TX_UNDERRUN     0x00000010  /**< Transmit Underrun                 */
-#define EMAC_INT_TX_ERR          0x00000020  /**< Transmit Error                    */
-#define EMAC_INT_TX_FIN          0x00000040  /**< TX Finished Process Descriptors   */
-#define EMAC_INT_TX_DONE         0x00000080  /**< Transmit Done                     */
-#define EMAC_INT_SOFT_INT        0x00001000  /**< Software Triggered Interrupt      */
-#define EMAC_INT_WAKEUP          0x00002000  /**< Wakeup Event Interrupt            */
-
-/* Power Down Register */
-#define EMAC_PD_POWER_DOWN       0x80000000  /**< Power Down MAC                    */
-
-
-/* Descriptor and status formats ------------------------------------------------------ */
-/* RX and TX descriptor and status definitions. */
-
-/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
-#define EMAC_NUM_RX_FRAG         4           /**< Num.of RX Fragments 4*1536= 6.0kB */
-#define EMAC_NUM_TX_FRAG         3           /**< Num.of TX Fragments 3*1536= 4.6kB */
-#define EMAC_ETH_MAX_FLEN        1536        /**< Max. Ethernet Frame Size          */
-#define EMAC_TX_FRAME_TOUT       0x00100000  /**< Frame Transmit timeout count      */
-
-/* EMAC variables located in 16K Ethernet SRAM */
-#define RX_DESC_BASE        LPC_PERI_RAM_BASE
-#define RX_STAT_BASE        (RX_DESC_BASE + EMAC_NUM_RX_FRAG*8)
-#define TX_DESC_BASE        (RX_STAT_BASE + EMAC_NUM_RX_FRAG*8)
-#define TX_STAT_BASE        (TX_DESC_BASE + EMAC_NUM_TX_FRAG*8)
-#define RX_BUF_BASE         (TX_STAT_BASE + EMAC_NUM_TX_FRAG*4)
-#define TX_BUF_BASE         (RX_BUF_BASE  + EMAC_NUM_RX_FRAG*EMAC_ETH_MAX_FLEN)
-
-/**
- * @brief RX Descriptor structure type definition
- */
-#define RX_DESC_PACKET(i)   (*(uint32_t *)(RX_DESC_BASE   + 8*i))
-#define RX_DESC_CTRL(i)     (*(uint32_t *)(RX_DESC_BASE+4 + 8*i))
-
-/**
- * @brief RX Status structure type definition
- */
-#define RX_STAT_INFO(i)     (*(uint32_t *)(RX_STAT_BASE   + 8*i))
-#define RX_STAT_HASHCRC(i)  (*(uint32_t *)(RX_STAT_BASE+4 + 8*i))
-
-/**
- * @brief TX Descriptor structure type definition
- */
-#define TX_DESC_PACKET(i)   (*(uint32_t *)(TX_DESC_BASE   + 8*i))
-#define TX_DESC_CTRL(i)     (*(uint32_t *)(TX_DESC_BASE+4 + 8*i))
-
-/**
- * @brief TX Status structure type definition
- */
-#define TX_STAT_INFO(i)     (*(uint32_t *)(TX_STAT_BASE   + 4*i))
-
-
-/**
- * @brief TX Data Buffer structure definition
- */
-#define RX_BUF(i)           (RX_BUF_BASE + EMAC_ETH_MAX_FLEN*i)
-#define TX_BUF(i)           (TX_BUF_BASE + EMAC_ETH_MAX_FLEN*i)
-
-/* RX Descriptor Control Word */
-#define EMAC_RCTRL_SIZE(n)       (n&0x7FF)      /**< Buffer size field                  */
-#define EMAC_RCTRL_INT           0x80000000     /**< Generate RxDone Interrupt         */
-
-/* RX Status Hash CRC Word */
-#define EMAC_RHASH_SA            0x000001FF     /**< Hash CRC for Source Address       */
-#define EMAC_RHASH_DA            0x001FF000     /**< Hash CRC for Destination Address  */
-
-/* RX Status Information Word */
-#define EMAC_RINFO_SIZE          0x000007FF  /**< Data size in bytes                */
-#define EMAC_RINFO_CTRL_FRAME    0x00040000  /**< Control Frame                     */
-#define EMAC_RINFO_VLAN          0x00080000  /**< VLAN Frame                        */
-#define EMAC_RINFO_FAIL_FILT     0x00100000  /**< RX Filter Failed                  */
-#define EMAC_RINFO_MCAST         0x00200000  /**< Multicast Frame                   */
-#define EMAC_RINFO_BCAST         0x00400000  /**< Broadcast Frame                   */
-#define EMAC_RINFO_CRC_ERR       0x00800000  /**< CRC Error in Frame                */
-#define EMAC_RINFO_SYM_ERR       0x01000000  /**< Symbol Error from PHY             */
-#define EMAC_RINFO_LEN_ERR       0x02000000  /**< Length Error                      */
-#define EMAC_RINFO_RANGE_ERR     0x04000000  /**< Range Error (exceeded max. size)  */
-#define EMAC_RINFO_ALIGN_ERR     0x08000000  /**< Alignment Error                   */
-#define EMAC_RINFO_OVERRUN       0x10000000  /**< Receive overrun                   */
-#define EMAC_RINFO_NO_DESCR      0x20000000  /**< No new Descriptor available       */
-#define EMAC_RINFO_LAST_FLAG     0x40000000  /**< Last Fragment in Frame            */
-#define EMAC_RINFO_ERR           0x80000000  /**< Error Occured (OR of all errors)  */
-
-/** RX Status Information word mask */
-#define EMAC_RINFO_ERR_MASK     (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR   | EMAC_RINFO_SYM_ERR | \
-                                    EMAC_RINFO_LEN_ERR   | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
-
-/* TX Descriptor Control Word */
-#define EMAC_TCTRL_SIZE          0x000007FF  /**< Size of data buffer in bytes      */
-#define EMAC_TCTRL_OVERRIDE      0x04000000  /**< Override Default MAC Registers    */
-#define EMAC_TCTRL_HUGE          0x08000000  /**< Enable Huge Frame                 */
-#define EMAC_TCTRL_PAD           0x10000000  /**< Pad short Frames to 64 bytes      */
-#define EMAC_TCTRL_CRC           0x20000000  /**< Append a hardware CRC to Frame    */
-#define EMAC_TCTRL_LAST          0x40000000  /**< Last Descriptor for TX Frame      */
-#define EMAC_TCTRL_INT           0x80000000  /**< Generate TxDone Interrupt         */
-
-/* TX Status Information Word */
-#define EMAC_TINFO_COL_CNT       0x01E00000  /**< Collision Count                   */
-#define EMAC_TINFO_DEFER         0x02000000  /**< Packet Deferred (not an error)    */
-#define EMAC_TINFO_EXCESS_DEF    0x04000000  /**< Excessive Deferral                */
-#define EMAC_TINFO_EXCESS_COL    0x08000000  /**< Excessive Collision               */
-#define EMAC_TINFO_LATE_COL      0x10000000  /**< Late Collision Occured            */
-#define EMAC_TINFO_UNDERRUN      0x20000000  /**< Transmit Underrun                 */
-#define EMAC_TINFO_NO_DESCR      0x40000000  /**< No new Descriptor available       */
-#define EMAC_TINFO_ERR           0x80000000  /**< Error Occured (OR of all errors)  */
-
-
-/* DP83848C PHY definition ------------------------------------------------------------ */
-
-/** PHY device reset time out definition */
-#define EMAC_PHY_RESP_TOUT      0x100000UL
-
-/* ENET Device Revision ID */
-#define EMAC_OLD_EMAC_MODULE_ID  0x39022000  /**< Rev. ID for first rev '-'         */
-
-
-/* PHY Basic Mode Control Register (BMCR) bitmap definitions */
-#define EMAC_PHY_BMCR_LOOPBACK              (1<<14)     /**< Loop back */
-//#define EMAC_PHY_BMCR_AN                  (1<<12)     /**< Auto Negotiation */
-
-#define EMAC_PHY_BMCR_ISOLATE               (1<<10)     /**< Isolate */
-#define EMAC_PHY_BMCR_RE_AN                 (1<<9)      /**< Restart auto negotiation */
-
-#define EMAC_PHY_BMSR_NOPREAM               (1<<6)      /**< MF Preamable Supress */
-#define EMAC_PHY_BMSR_AUTO_DONE             (1<<5)      /**< Auto negotiation complete */
-
-
-#define EMAC_PHY_FULLD_100M      (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_DUPLEX)           // Full Duplex 100Mbit
-#define EMAC_PHY_HALFD_100M      (EMAC_PHY_BMCR_SPEED_SEL | (~ EMAC_PHY_BMCR_DUPLEX))       // Half Duplex 100Mbit
-#define EMAC_PHY_FULLD_10M       ((~ EMAC_PHY_BMCR_SPEED_SEL) | EMAC_PHY_BMCR_DUPLEX)       // Full Duplex 10Mbit
-#define EMAC_PHY_HALFD_10M       ((~ EMAC_PHY_BMCR_SPEED_SEL) | (~EMAC_PHY_BMCR_DUPLEX))    // Half Duplex 10MBit
-#define EMAC_PHY_AUTO_NEG        (EMAC_PHY_BMCR_SPEED_SEL | EMAC_PHY_BMCR_AN)               // Select Auto Negotiation
-
-
-
-/* EMAC PHY status type definitions */
-#define EMAC_PHY_STAT_LINK          (0)     /**< Link Status */
-#define EMAC_PHY_STAT_SPEED         (1)     /**< Speed Status */
-#define EMAC_PHY_STAT_DUP           (2)     /**< Duplex Status */
-
-/* EMAC PHY device Speed definitions */
-#define EMAC_MODE_AUTO              (0)     /**< Auto-negotiation mode */
-#define EMAC_MODE_10M_FULL          (1)     /**< 10Mbps FullDuplex mode */
-#define EMAC_MODE_10M_HALF          (2)     /**< 10Mbps HalfDuplex mode */
-#define EMAC_MODE_100M_FULL         (3)     /**< 100Mbps FullDuplex mode */
-#define EMAC_MODE_100M_HALF         (4)     /**< 100Mbps HalfDuplex mode */
-
-/* EMAC User Buffers*/
-#define EMAC_MAX_FRAME_SIZE          (0x600)  /* 1536 */
-#define EMAC_MAX_FRAME_NUM           (2)
-
-/* EMAC Error Codes */
-#define EMAC_ALIGN_ERR              ( 1 << 0)
-#define EMAC_RANGE_ERR              ( 1 << 1)
-#define EMAC_LENGTH_ERR             ( 1 << 2)
-#define EMAC_SYMBOL_ERR             ( 1 << 3)
-#define EMAC_CRC_ERR                ( 1 << 4)
-#define EMAC_RX_NO_DESC_ERR         ( 1 << 5)
-#define EMAC_OVERRUN_ERR            ( 1 << 6)
-#define EMAC_LATE_COLLISION_ERR     ( 1 << 7)
-#define EMAC_EXCESSIVE_COLLISION_ERR ( 1 << 8)
-#define EMAC_EXCESSIVE_DEFER_ERR     ( 1 << 9)
-#define EMAC_UNDERRUN_ERR           ( 1 << 10)
-#define EMAC_TX_NO_DESC_ERR         ( 1 << 11)
-#define EMAC_FILTER_FAILED_ERR      ( 1 << 12)
-
-
-/**
- * @}
- */
-
-
-/**************************** GLOBAL/PUBLIC TYPES ***************************/
-
-/** @defgroup EMAC_Public_Types EMAC Public Types
- * @{
- */
-
-/**
- * @brief TX Data Buffer structure definition
- */
-typedef struct {
-    uint32_t ulDataLen;         /**< Data length */
-    uint32_t *pbDataBuf;        /**< A word-align data pointer to data buffer */
-} EMAC_PACKETBUF_Type;
-
-/**
- * @brief PHY Configuration structure definition
- */
-typedef struct {
-   uint32_t Mode;                       /**< Supported EMAC PHY device speed, should be one of the following:
-                                            - EMAC_MODE_AUTO
-                                            - EMAC_MODE_10M_FULL
-                                            - EMAC_MODE_10M_HALF
-                                            - EMAC_MODE_100M_FULL
-                                            - EMAC_MODE_100M_HALF
-                                            */
-} EMAC_PHY_CFG_Type;
-
-
-/** EMAC Call back function type definition */
-typedef int32_t (PHY_INIT_FUNC)(EMAC_PHY_CFG_Type* pPhyCfg);
-typedef int32_t (PHY_RESET_FUNC)(void);
-typedef void (EMAC_FRAME_RECV_FUNC)(uint16_t* pData, uint32_t size);
-typedef void (EMAC_TRANSMIT_FINISH_FUNC)(void);
-typedef void (EMAC_ERR_RECV_FUNC)(int32_t ulErrCode);
-typedef void (EMAC_WAKEUP_FUNC)(void);
-typedef void (SOFT_INT_FUNC)(void);
-
-/**
- * @brief EMAC configuration structure definition
- */
-typedef struct {
-    EMAC_PHY_CFG_Type PhyCfg;               /* PHY Configuration */
-    uint8_t           bPhyAddr;                    /* 5-bit PHY Address field */    
-    uint8_t     *pbEMAC_Addr;               /**< Pointer to EMAC Station address that contains 6-bytes
-                                            of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
-                                            */
-    uint16_t     nMaxFrameSize;              /* maximum frame length */
-    PHY_INIT_FUNC *pfnPHYInit;               /* point to the funtion which will be called to initialize PHY */
-    PHY_RESET_FUNC *pfnPHYReset;             /* point to the function which will be called to reset PHY */
-    EMAC_FRAME_RECV_FUNC *pfnFrameReceive;     /* point to the function which will be called when a frame is received*/
-    EMAC_TRANSMIT_FINISH_FUNC* pfnTransmitFinish;  /*point to the function which will be called when transmit finished*/
-    EMAC_ERR_RECV_FUNC    *pfnErrorReceive;     /* point to an array of functions which will be called error occur. */
-                                               /* Errors:
-                                                                 EMAC_ALIGN_ERR 
-                                                        EMAC_RANGE_ERR
-                                                        EMAC_LENGTH_ERR
-                                                        EMAC_SYMBOL_ERR 
-                                                        EMAC_CRC_ERR
-                                                        EMAC_RX_NO_DESC_ERR
-                                                        EMAC_OVERRUN_ERR
-                                                        EMAC_LATE_COLLISION_ERR
-                                                        EMAC_EXCESSIVE_COLLISION_ERR
-                                                        EMAC_EXCESSIVE_DEFER_ERR
-                                                        EMAC_UNDERRUN_ERR
-                                                        EMAC_TX_NO_DESC_ERR
-                                                  */
-    EMAC_WAKEUP_FUNC *pfnWakeup;               /* point to the function which will be called when receiving wakeup interrupt */
-    SOFT_INT_FUNC *pfnSoftInt;                /* point to the function which will be called when the interrupt caused by software occurs */                    
-} EMAC_CFG_Type;
-
-/**
- * @brief EMAC Buffer status definition
- */
-typedef enum {
-   EMAC_BUFF_EMPTY,                /* buffer is empty */
-   EMAC_BUFF_PARTIAL_FULL,         /* buffer contains some packets */
-   EMAC_BUFF_FULL,                 /* buffer is full */
-} EMAC_BUFF_STATUS;
-
-/**
- * @brief EMAC Buffer Index definition
- */
-
-typedef enum {
-    EMAC_TX_BUFF,                   /* transmit buffer */
-    EMAC_RX_BUFF,                   /* receive buffer */
-} EMAC_BUFF_IDX;
-
-/**
- * @}
- */
-
-
-/** @defgroup EMAC_Public_Functions EMAC Public Functions
- * @{
- */
-
-/** Init/DeInit */
-int32_t EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
-void EMAC_DeInit(void);
-
-/** Send/Receive data */
-void EMAC_TxEnable( void );
-void EMAC_RxEnable( void );
-void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
-int32_t EMAC_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
-void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
-
-/** PHY Setup */
-void EMAC_Write_PHY (uint8_t PhyReg, uint16_t Value);
-uint16_t EMAC_Read_PHY (uint8_t PhyReg);
-void EMAC_SetFullDuplexMode(uint8_t full_duplex);
-void EMAC_SetPHYSpeed(uint8_t mode_100Mbps);
-
-/** Filter */
-void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
-FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
-void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
-IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
-EMAC_BUFF_STATUS EMAC_GetBufferSts(EMAC_BUFF_IDX idx);
-
-
-/**
- * @}
- */
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_EMAC_DRIVER_H_ */
-
-/**
- * @}
- */
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_emc.h

@@ -1,549 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_emc.h           2011-06-02
-*//**
-* @file     lpc_emc.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for EMC firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup EMC   EMC (External Memory Controller)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_EMC_H_
-#define __LPC_EMC_H_
-
-#include "lpc_types.h"
-#include "LPC407x_8x_177x_8x.h"
-
-
-/** @defgroup EMC_Private_Macros EMC Private Macros
- * @{
- */
-
-/***********************************************************************
- * EMC Control Register (EMCControl)
- **********************************************************************/
-/* Control register mask */
-#define EMC_Control_MASK            ((uint32_t )0x07)
-/* Control register EMC: Enable control. */
-#define EMC_Control_E               ((uint32_t )(1<<0))
-/* Control register EMC: Address mirror control. */
-#define EMC_Control_M               ((uint32_t )(1<<1))
-/* Control register EMC: Low-power mode control. */
-#define EMC_Control_L               ((uint32_t )(1<<2))
-
-/***********************************************************************
- * EMC Status Register (EMCStatus)
- **********************************************************************/
-/* Status register mask */
-#define EMC_Status_MASK             ((uint32_t )0x07)
-/* Status register EMC: Busy. */
-#define EMC_Status_B                ((uint32_t )(1<<0))
-/* Status register EMC: Write buffer status. */
-#define EMC_Status_S                ((uint32_t )(1<<1))
-/* Status register EMC: Self-refresh acknowledge.. */
-#define EMC_Status_SA               ((uint32_t )(1<<2))
-
-/***********************************************************************
- * EMC Configuration register (EMCConfig)
- **********************************************************************/
-/* EMC Configuration register : Little Endian. */
-#define EMC_Config_Little_Endian_Mode       ((uint32_t )(0<<0))
-/* EMC Configuration register : Big Endian. */
-#define EMC_Config_Big_Endian_Mode      ((uint32_t )(1<<0))
-/* EMC Configuration: Endian Mask */
-#define EMC_Config_Endian_Mask           (0x01<<0)
-
-/* EMC Configuration register: CLKOUT ratio 1:1. */
-#define EMC_Config_CCLK_1_1             ((uinr32_t)(0<<8))
-/* EMC Configuration register: CLKOUT ratio 1:1. */
-#define EMC_Config_CCLK_1_2             ((uinr32_t)(1<<8))
-
-/* EMC Configuration register mask */
-#define EMC_Config_MASK             ((uint32_t)(0x101))
-
-
-/***********************************************************************
- * Dynamic Memory Control register (EMCDynamicControl)
- **********************************************************************/
-/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
-#define EMC_DYNAMIC_CTRL_MEMCLK_EN_POS              (0)
-#define EMC_DYNAMIC_CTRL_MEMCLK_EN_BMASK            (1<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
-
-#define EMC_DYNAMIC_CTRL_CE_SAVEPWR                 (0<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
-#define EMC_DYNAMIC_CTRL_CE_ALLCLK_HI               (1<<EMC_DYNAMIC_CTRL_MEMCLK_EN_POS)
-
-/* Dynamic Memory Control register EMC: Dynamic memory clock control */
-#define EMC_DYNAMIC_CTRL_CLKCTRL_POS                (1)
-#define EMC_DYNAMIC_CTRL_CLKCTRL_BMASK              (1<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
-
-#define EMC_DYNAMIC_CTRL_CS_CLKOUT_STOP             (0<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
-#define EMC_DYNAMIC_CTRL_CE_CLKOUT_CONT             (1<<EMC_DYNAMIC_CTRL_CLKCTRL_POS)
-
-/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
-#define EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS            (2)
-#define EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_BMASK          (1<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
-
-#define EMC_DYNAMIC_CTRL_SR_NORMALMODE              (0<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
-#define EMC_DYNAMIC_CTRL_SR_SELFREFRESH             (1<<EMC_DYNAMIC_CTRL_SELFREFRESH_REQ_POS)
-
-/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
-#define EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS         (5)
-#define EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_BMASK       (1<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
-
-#define EMC_DYNAMIC_CTRL_MMC_CLKOUT_ENABLED         (0<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
-#define EMC_DYNAMIC_CTRL_MMC_CLKOUT_DISABLED        (1<<EMC_DYNAMIC_CTRL_MMC_CLKOUTCTRL_POS)
-
-
-/* Dynamic Memory Control register EMC: SDRAM initialization*/
-#define EMC_DYNAMIC_CTRL_SDRAM_INIT_POS             (7)
-#define EMC_DYNAMIC_CTRL_SDRAM_INIT_BMASK           (0x03<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
-
-#define EMC_DYNAMIC_CTRL_SDRAM_NORMAL           (0<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
-#define EMC_DYNAMIC_CTRL_SDRAM_MODE             (1<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
-#define EMC_DYNAMIC_CTRL_SDRAM_PALL             (2<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
-#define EMC_DYNAMIC_CTRL_SDRAM_NOP              (3<<EMC_DYNAMIC_CTRL_SDRAM_INIT_POS)
-
-/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
-#define EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS          (13)
-#define EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_BMASK        (0x01<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
-
-#define EMC_DYNAMIC_CTRL_DP_NORMAL                  (0<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
-#define EMC_DYNAMIC_CTRL_DP_DEEPSLEEP               (1<<EMC_DYNAMIC_CTRL_SDRAM_PWRMODE_POS)
-
-
-/***********************************************************************
- * Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
- **********************************************************************/
-/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
-#define EMC_DynamicRefresh_REFRESH(n)   ((uint32_t ) (n & 0x3ff))
-
-/***********************************************************************
- * Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
- **********************************************************************/
-/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
-#define EMC_DynamicReadConfig_RD(n)     ((uint32_t )(n & 0x03))
-
-/***********************************************************************
- * Dynamic Memory Percentage Command Period register (EMCDynamictRP)
- **********************************************************************/
-/* EMCDynamictRP register EMC: Precharge command period (tRP). */
-#define EMC_DynamictRP_tRP(n)           ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
- **********************************************************************/
-/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
-#define EMC_DynamictRP_tRAS(n)          ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX)
- **********************************************************************/
-/* EMCDynamictSREX register EMC: self-refresh exit time (tSREX)) */
-
-#define EMC_DynamictRP_tSREX(n)         ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
- **********************************************************************/
-/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
-#define EMC_DynamictAPR_tAPR(n)         ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
- **********************************************************************/
-/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
-#define EMC_DynamictDAL_tDAL(n)         ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Dynamic Memory Write Recovery Time register (EMCDynamictWR)
- **********************************************************************/
-/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
-#define EMC_DynamictWR_tWR(n)           (uint32_t )(n & 0x0f)
-
-/***********************************************************************
- * Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
- **********************************************************************/
-/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
-#define EMC_DynamictRC_tRC(n)           (uint32_t )(n & 0x1f)
-
-/***********************************************************************
- * Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
- **********************************************************************/
-/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
-#define EMC_DynamictRFC_tRFC(n)         ((uint32_t )(n & 0x1f))
-
-/***********************************************************************
- * Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
- **********************************************************************/
-/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
-#define EMC_DynamictXSR_tXSR(n)         ((uint32_t )(n & 0x1f))
-
-/***********************************************************************
- * Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
- **********************************************************************/
-/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
-#define EMC_DynamictRRD_tRRD(n)         ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
- **********************************************************************/
-/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
-#define EMC_DynamictMRD_tMRD(n)         ((uint32_t )(n & 0x1f))
-
-/***********************************************************************
- * Static Memory Extended Wait Register (EMCStaticExtendedWait)
- **********************************************************************/
-/* StaticExtendedWait register EMC: External wait time out. */
-#define EMC_StaticExtendedWait_EXTENDEDWAIT(n)          ((uint32_t )(n & 0x3ff))
-
-
-/***********************************************************************
- * Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
- **********************************************************************/
-/* DynamicConfig register EMC: Memory device (MD). */
-#define EMC_DYNAMIC_CFG_MEMDEV_POS              (3)
-#define EMC_DYNAMIC_CFG_MEMDEV_BMASK                (0x03 << EMC_DYNAMIC_CFG_MEMDEV_POS)
-
-#define EMC_DYNAMIC_CFG_MEMDEV_SDRAM                (0 << EMC_DYNAMIC_CFG_MEMDEV_POS)
-#define EMC_DYNAMIC_CFG_MEMDEV_LOWPWR_SDRAM         (1 << EMC_DYNAMIC_CFG_MEMDEV_POS)
-
-/* DynamicConfig register EMC: Address mapping (AM) */
-#define EMC_DYNAMIC_CFG_ADD_MAP_P1_POS                      (7)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK                     (0x3F<<EMC_DYNAMIC_CFG_ADD_MAP_P1_POS)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P2_POS                      (12)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK                     (0x01 << EMC_DYNAMIC_CFG_ADD_MAP_P2_POS)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P3_POS                      (14)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK                     (0x01 << EMC_DYNAMIC_CFG_ADD_MAP_P3_POS)
-
-#define EMC_DYNAMIC_CFG_ADD_MAP_P1(n)                         (  (n<<EMC_DYNAMIC_CFG_ADD_MAP_P1_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P1_MASK)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P2(n)                         (  (n<<EMC_DYNAMIC_CFG_ADD_MAP_P2_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P2_MASK)
-#define EMC_DYNAMIC_CFG_ADD_MAP_P3(n)                         (  (n<<EMC_DYNAMIC_CFG_ADD_MAP_P3_POS)&EMC_DYNAMIC_CFG_ADD_MAP_P3_MASK)
-
-#define EMC_ADD_MAP_ROW_BANK_COL                               (0)
-#define EMC_ADD_MAP_BANK_ROW_COL                               (1)
-
-
-/* DynamicConfig register EMC: Buffer enable */
-#define EMC_DYNAMIC_CFG_BUFFENABLE_POS          (19)
-#define EMC_DYNAMIC_CFG_BUFFENABLE_BMASK        (0x01<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
-
-#define EMC_DYNAMIC_CFG_BUFF_DISABLED           (0<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
-#define EMC_DYNAMIC_CFG_BUFF_ENABLED            (1<<EMC_DYNAMIC_CFG_BUFFENABLE_POS)
-
-
-/* DynamicConfig register EMC: Write protect (P) */
-#define EMC_DYNAMIC_CFG_WRPROTECT_POS           (20)
-#define EMC_DYNAMIC_CFG_WRPROTECT_BMASK         (0x01<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
-
-#define EMC_DYNAMIC_CFG_WR_UNPROTECTED          (0<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
-#define EMC_DYNAMIC_CFG_WR_PROTECTED            (1<<EMC_DYNAMIC_CFG_WRPROTECT_POS)
-
-/***********************************************************************
- * Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
- **********************************************************************/
-/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
-#define EMC_DYNAMIC_RASCAS_RASCFG_POS           (0)
-#define EMC_DYNAMIC_RASCAS_RASCFG_BMASK         (0x03<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
-
-#define EMC_DYNAMIC_RASCAS_RASLATENCY_RESVD     (0<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
-#define EMC_DYNAMIC_RASCAS_RASLATENCY_1CLK      (1<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
-#define EMC_DYNAMIC_RASCAS_RASLATENCY_2CLK      (2<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
-#define EMC_DYNAMIC_RASCAS_RASLATENCY_3CLK      (3<<EMC_DYNAMIC_RASCAS_RASCFG_POS)
-
-
-/* DynamicRASCAS register EMC: CAS latency (CAS)*/
-#define EMC_DYNAMIC_RASCAS_CASCFG_POS           (8)
-#define EMC_DYNAMIC_RASCAS_CASCFG_BMASK         (0x03<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
-
-#define EMC_DYNAMIC_RASCAS_CASLATENCY_RESVD     (0<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
-#define EMC_DYNAMIC_RASCAS_CASLATENCY_1CLK      (1<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
-#define EMC_DYNAMIC_RASCAS_CASLATENCY_2CLK      (2<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
-#define EMC_DYNAMIC_RASCAS_CASLATENCY_3CLK      (3<<EMC_DYNAMIC_RASCAS_CASCFG_POS)
-
-/***********************************************************************
- * Static Memory Configuration registers (EMCStaticConfig0-3)
- **********************************************************************/
-/* StaticConfig register EMC: Memory width (MW). */
-#define EMC_STATIC_CFG_MEMWIDTH_POS     (0)
-#define EMC_STATIC_CFG_MEMWIDTH_BMASK   (0x03<<EMC_STATIC_CFG_MEMWIDTH_POS)
-#define EMC_StaticConfig_MW(n)          ((uint32_t )((n<<EMC_STATIC_CFG_MEMWIDTH_POS) & EMC_STATIC_CFG_MEMWIDTH_BMASK))
-
-/* StaticConfig register EMC: Memory width 8bit . */
-#define EMC_STATIC_CFG_MW_8BITS         (EMC_StaticConfig_MW(0))
-
-/* StaticConfig register EMC: Memory width 16bit . */
-#define EMC_STATIC_CFG_MW_16BITS        (EMC_StaticConfig_MW(1))
-
-/* StaticConfig register EMC: Memory width 32bit . */
-#define EMC_STATIC_CFG_MW_32BITS        (EMC_StaticConfig_MW(2))
-
-/* StaticConfig register EMC: Page mode (PM) */
-#define EMC_STATIC_CFG_PAGEMODE_POS                 (3)
-#define EMC_STATIC_CFG_PAGEMODE_MASK                (1<<EMC_STATIC_CFG_PAGEMODE_POS)
-
-#define EMC_CFG_PM_DISABLE                      (0<<EMC_STATIC_CFG_PAGEMODE_POS)
-#define EMC_CFG_PM_ASYNC_ENABLE                 (1<<EMC_STATIC_CFG_PAGEMODE_POS)
-
-
-/* StaticConfig register EMC: Chip select polarity (PC) */
-#define EMC_STATIC_CFG_CHIPPOLARITY_POS             (6)
-#define EMC_STATIC_CFG_CHIPPOLARITY_MASK            (1<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
-
-#define EMC_CFG_BYTELAND_PC_ACTIVE_LO               (0<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
-#define EMC_CFG_BYTELAND_PC_ACTIVE_HI               (1<<EMC_STATIC_CFG_CHIPPOLARITY_POS)
-
-
-/* StaticConfig register EMC: Byte lane state (PB) */
-#define EMC_STATIC_CFG_BYTELAND_POS                 (7)
-#define EMC_STATIC_CFG_BYTELAND_MASK                (1<<EMC_STATIC_CFG_BYTELAND_POS)
-
-#define EMC_CFG_BYTELAND_READ_BITSHIGH              (0<<EMC_STATIC_CFG_BYTELAND_POS)
-#define EMC_CFG_BYTELAND_READ_BITSLOW               (1<<EMC_STATIC_CFG_BYTELAND_POS)
-
-
-/* StaticConfig register EMC: Extended wait (EW) */
-#define EMC_STATIC_CFG_EXTWAIT_POS              (8)
-#define EMC_STATIC_CFG_EXTWAIT_MASK             (1<<EMC_STATIC_CFG_EXTWAIT_POS)
-
-#define EMC_CFG_EW_DISABLED                 (0<<EMC_STATIC_CFG_EXTWAIT_POS)
-#define EMC_CFG_EW_ENABLED                  (1<<EMC_STATIC_CFG_EXTWAIT_POS)
-
-
-/* StaticConfig register EMC: Buffer enable (B) */
-#define EMC_STATIC_CFG_BUFENABLE_POS                (19)
-#define EMC_STATIC_CFG_BUFENABLE_MASK               (1<<EMC_STATIC_CFG_BUFENABLE_POS)
-
-#define EMC_CFG_BUF_DISABLED                    (0<<EMC_STATIC_CFG_BUFENABLE_POS)
-#define EMC_CFG_BUF_ENABLED                     (1<<EMC_STATIC_CFG_BUFENABLE_POS)
-
-/* StaticConfig register EMC: Write protect (P) */
-#define EMC_STATIC_CFG_WRIEPROTECT_POS              (20)
-#define EMC_STATIC_CFG_WRIEPROTECT_MASK             (1<<EMC_STATIC_CFG_WRIEPROTECT_POS)
-
-#define EMC_CFG_WRITEPROTECT_DISABLED               (0<<EMC_STATIC_CFG_WRIEPROTECT_POS)
-#define EMC_CFG_WRITEPROTECT_ENABLED                (1<<EMC_STATIC_CFG_WRIEPROTECT_POS)
-
-/***********************************************************************
- * Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
- **********************************************************************/
-/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
-#define EMC_StaticWaitWen_WAITWEN(n)    ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
- **********************************************************************/
-/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
-#define EMC_StaticWaitOen_WAITOEN(n)    ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Static Memory Read Delay registers (EMCStaticWaitRd0-3)
- **********************************************************************/
-/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
-read first access wait state (WAITRD) */
-#define EMC_StaticWaitRd_WAITRD(n)      ((uint32_t )(n & 0x1f))
-
-/***********************************************************************
- * Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
- **********************************************************************/
-/* StaticwaitPage register EMC: Asynchronous page mode read after the first
-read wait states (WAITPAGE). */
-#define EMC_StaticwaitPage_WAITPAGE(n)  ((uint32_t )(n & 0x1f))
-
-/***********************************************************************
- * Static Memory Write Delay registers (EMCStaticWaitwr0-3)
- **********************************************************************/
-/* StaticWaitwr register EMC: Write wait states (WAITWR). */
-#define EMC_StaticWaitwr_WAITWR(n)      ((uint32_t )(n & 0x1f))
-
-/***********************************************************************
- * Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
- **********************************************************************/
-/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
-#define EMC_StaticWaitTurn_WAITTURN(n)  ((uint32_t )(n & 0x0f))
-
-/***********************************************************************
- * Delay Control register (EMCDLYCTL)
- **********************************************************************/
-#define EMC_DLYCTL_CMDDLY(n)        ((uint32_t)(n&0x1F))
-#define EMC_DLYCTL_FBCLKDLY(n)      ((uint32_t)((n&0x1F)<<8))
-#define EMC_DLYCTL_CLKOUT0DLY(n)    ((uint32_t)((n&0x1F)<<16))
-#define EMC_DLYCTL_CLKOUT1DLY(n)    ((uint32_t)((n&0x1F)<<24))
-
-/***********************************************************************
- * EMC Calibration register (EMCCAL)
- **********************************************************************/
-#define EMC_CAL_CALVALUE(n)         ((uint32_t)(n&0xFF))
-#define EMC_CAL_START               ((uint32_t)(1<<14))
-#define EMC_CAL_DONE                ((uint32_t)(1<<15))
-
-/***********************************************************************
- * EMC Function Return codes
- **********************************************************************/
- typedef int32_t EMC_FUNC_CODE;
-#define  EMC_FUNC_OK                            (0)
-#define  EMC_FUNC_ERR                           (0x01)
-#define  EMC_FUNC_INVALID_PARAM                 (0x02)
-
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup EMC_Public_Types EMC Public Types
- * @{
- */
-/*EMC dynamic memory registers enum*/
-typedef enum
-{
-  EMC_DYN_MEM_REFRESH_TIMER,
-  EMC_DYN_MEM_READ_CONFIG,
-  EMC_DYN_MEM_TRP,
-  EMC_DYN_MEM_TRAS,
-  EMC_DYN_MEM_TSREX,
-  EMC_DYN_MEM_TAPR,
-  EMC_DYN_MEM_TDAL,
-  EMC_DYN_MEM_TWR,
-  EMC_DYN_MEM_TRC,
-  EMC_DYN_MEM_TRFC,
-  EMC_DYN_MEM_TXSR,
-  EMC_DYN_MEM_TRRD,
-  EMC_DYN_MEM_TMRD
-} EMC_DYN_MEM_PAR;
-
-/*EMC static memory registers enum*/
-typedef enum
-{
-  EMC_STA_MEM_WAITWEN,
-  EMC_STA_MEM_WAITOEN,
-  EMC_STA_MEM_WAITRD,
-  EMC_STA_MEM_WAITPAGE,
-  EMC_STA_MEM_WAITWR,
-  EMC_STA_MEM_WAITTURN,
-} EMC_STA_MEM_PAR;
-
-/* SDRAM Config Struct */
-typedef struct
-{
-    uint8_t  CSn;         // 0/1/2/3
-    uint32_t TotalSize;   // SDRAM TotalSize
-    uint16_t ChipSize;    // chip size(Mb): 16Mb, 64Mb, 128Mb, 256Mb, 512Mb
-    uint8_t   DataWidth;  // 8bit, 16 bit, 32bit
-    uint8_t   AddrBusWidth;  // 16bit, 32bit
-    uint8_t   AddrMap;           // EMC_ADD_MAP_BANK_ROW_COL/ EMC_ADD_MAP_ROW_BANK_COL
-
-    /* timming */
-    uint16_t RefreshTime;  // Dynamic Refresh Time
-    uint8_t  ReadConfig;    // Read Config Strategy
-    uint8_t  PrechargeCmdPeriod;  // Precharge Command Period (tRP)
-    uint8_t SeftRefreshExitTime; // Self-Refresh Exit Time (tSREX)
-    uint8_t DataOut2ActiveTime;            // the last-data-out to active command time (tAPR)
-    uint8_t DataIn2ActiveTime;      //  the data-in to active command time (tDAL, or tAPW)
-    uint8_t WriteRecoveryTime;      // the write recovery time (tWR, tDPL, tRWL, or tRDL)
-    uint8_t Active2ActivePeriod;       // the active to active command period (tRC)
-    uint8_t AutoRefrehPeriod;      // the auto-refresh period and auto-refresh to active command period (tRFC/tRC)
-    uint8_t ExitSelfRefreshTime; // the exit self-refresh to active command time (tXSR)
-    uint8_t ActiveBankLatency;  // the active bank A to active bank B latency (tRRD)
-    uint8_t LoadModeReg2Active;            // the load mode register to active command time (tMRD)
-    uint8_t Active2PreChargeTime;     // Active to precharge command period (tRAS)
-    uint8_t  RASLatency;          // RAS Delay
-    uint8_t  CASLatency;          // CAS Delay
-    
-} EMC_DYN_MEM_Config_Type;
-
-typedef struct
-{
-    uint8_t  CSn;         // 0/1/2/3
-    uint8_t DataWidth;    // 8bit, 16bit, 32bit
-    uint8_t PageMode;   // 1: asynchronous page mode enabled
-    uint8_t ByteLane;   // 1: Read when active bits are low, 0: read when acrive bits are High
-    uint8_t ExtendedWait;  //1: enabled
-    uint8_t AddressMirror; // 1: reset memory map, 0: normal memory map
-
-    uint8_t  WaitWEn;       // Delay from the chip select to the write enable (CCLK cycles) 
-    uint8_t  WaitOEn;       // Delay from the chip select or address change to output enable (CCLK cycles)
-    uint8_t  WaitRd;        // Delay from the chip select to the read access (CCLK cycles)
-    uint8_t  WaitPage;      // Delay for asynchronous page mode sequential accesses (CCLK cycles)
-    uint8_t  WaitWr;        // Delay from the chip select to the write access (CCLK cycles)
-    uint8_t  WaitTurn;      // The number of bus turnaround cycles
-} EMC_STATIC_MEM_Config_Type;
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup EMC_Public_Functions EMC Public Functions
- * @{
- */
- uint32_t EMC_SDRAM_REFRESH(uint32_t time);
- uint32_t EMC_NS2CLK(uint32_t time);
- EMC_FUNC_CODE DynMem_Init(EMC_DYN_MEM_Config_Type* pConfig);
- EMC_FUNC_CODE StaticMem_Init(EMC_STATIC_MEM_Config_Type* pConfig);
- EMC_FUNC_CODE EMC_Init(void);
- EMC_FUNC_CODE EMC_ConfigEndianMode(uint32_t endian_mode);
- EMC_FUNC_CODE EMC_DynCtrlClockEnable(uint32_t clock_enable);
- EMC_FUNC_CODE EMC_DynCtrlClockControl(int32_t clock_control);
- EMC_FUNC_CODE EMC_DynCtrlSelfRefresh(uint32_t self_refresh_mode);
- EMC_FUNC_CODE EMC_DynCtrlMMC(uint32_t MMC_val);
- EMC_FUNC_CODE EMC_DynCtrlSDRAMInit(uint32_t SDRAM_command);
- EMC_FUNC_CODE EMC_DynCtrlPowerDownMode(uint32_t SDRAM_command);
- EMC_FUNC_CODE EMC_SetDynMemoryParameter(EMC_DYN_MEM_PAR par, uint32_t val);
- EMC_FUNC_CODE EMC_StaticExtendedWait(uint32_t Extended_wait_time_out);
- EMC_FUNC_CODE EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev);
- EMC_FUNC_CODE EMC_DynMemConfigAM(uint32_t index , uint8_t addr_bus_width, uint8_t addr_map,uint8_t data_bus_width,uint16_t chip_size);
- EMC_FUNC_CODE EMC_DynMemConfigB(uint32_t index , uint32_t buff_control);
- EMC_FUNC_CODE EMC_DynMemConfigP(uint32_t index , uint32_t permission);
- EMC_FUNC_CODE EMC_DynMemRAS(uint32_t index , uint32_t ras_val);
- EMC_FUNC_CODE EMC_DynMemCAS(uint32_t index , uint32_t cas_val);
- EMC_FUNC_CODE EMC_StaMemConfigMW(uint32_t index , uint32_t mem_width);
- EMC_FUNC_CODE EMC_StaMemConfigPM(uint32_t index , uint32_t page_mode);
- EMC_FUNC_CODE EMC_StaMemConfigPC(uint32_t index , uint32_t pol_val);
- EMC_FUNC_CODE EMC_StaMemConfigPB(uint32_t index , uint32_t pb_val);
- EMC_FUNC_CODE EMC_StaMemConfigEW(uint32_t index , uint32_t ex_wait);
- EMC_FUNC_CODE EMC_StaMemConfigB(uint32_t index , uint32_t buf_val);
- EMC_FUNC_CODE EMC_StaMemConfigpP(uint32_t index , uint32_t per_val);
- EMC_FUNC_CODE EMC_SetStaMemoryParameter(uint32_t index ,EMC_STA_MEM_PAR par, uint32_t val);
-
-/**
- * @}
- */
-
-
-#endif /* __LPC_EMC_H_ */
-
-/**
- * @}
- */
-
-
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_exti.h

@@ -1,158 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_exti.h          2011-06-02
-*//**
-* @file     lpc_exti.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for External Interrupt firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup EXTI  EXTI (External Interrupt)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_EXTI_H_
-#define __LPC_EXTI_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
- * @{
- */
-/*********************************************************************//**
- * Macro defines for EXTI  control register
- **********************************************************************/
-#define EXTI_EINT0_BIT_MARK     0x01
-#define EXTI_EINT1_BIT_MARK     0x02
-#define EXTI_EINT2_BIT_MARK     0x04
-#define EXTI_EINT3_BIT_MARK     0x08
-
-/**
- * @}
- */
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup EXTI_Public_Types EXTI Public Types
- * @{
- */
-
-/**
- * @brief EXTI external interrupt line option
- */
-typedef enum
-{
-    EXTI_EINT0, /*!<  External interrupt 0, P2.10 */
-    EXTI_EINT1, /*!<  External interrupt 0, P2.11 */
-    EXTI_EINT2, /*!<  External interrupt 0, P2.12 */
-    EXTI_EINT3  /*!<  External interrupt 0, P2.13 */
-} EXTI_LINE_ENUM;
-
-/**
- * @brief EXTI mode option
- */
-typedef enum
-{
-    EXTI_MODE_LEVEL_SENSITIVE,  /*!< Level sensitivity is selected */
-    EXTI_MODE_EDGE_SENSITIVE    /*!< Edge sensitivity is selected */
-} EXTI_MODE_ENUM;
-
-/**
- * @brief EXTI polarity option
- */
-typedef enum
-{
-    EXTI_POLARITY_LOW_ACTIVE_OR_FALLING_EDGE,   /*!< Low active or falling edge sensitive
-                                                depending on pin mode */
-    EXTI_POLARITY_HIGH_ACTIVE_OR_RISING_EDGE    /*!< High active or rising edge sensitive
-                                                depending on pin mode */
-} EXTI_POLARITY_ENUM;
-
-/**
- * @brief EXTI Initialize structure
- */
-typedef struct
-{
-    /** Select external interrupt pin (EINT0, EINT1, EINT 2, EINT3) */
-    EXTI_LINE_ENUM EXTI_Line;
-
-    /** Choose between Level-sensitivity or Edge sensitivity */
-    EXTI_MODE_ENUM EXTI_Mode;
-
-    /** If EXTI mode is level-sensitive: this element use to select low or high active level
-    if EXTI mode is polarity-sensitive: this element use to select falling or rising edge */
-    EXTI_POLARITY_ENUM EXTI_polarity;
-
-}EXTI_InitTypeDef;
-
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup EXTI_Public_Functions EXTI Public Functions
- * @{
- */
-
-void EXTI_Init(void);
-void EXTI_DeInit(void);
-
-void EXTI_Config(EXTI_InitTypeDef *EXTICfg);
-void EXTI_SetMode(EXTI_LINE_ENUM EXTILine, EXTI_MODE_ENUM mode);
-void EXTI_SetPolarity(EXTI_LINE_ENUM EXTILine, EXTI_POLARITY_ENUM polarity);
-void EXTI_ClearEXTIFlag(EXTI_LINE_ENUM EXTILine);
-
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_EXTI_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_gpdma.h

@@ -1,418 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_gpdma.h         2011-06-02
-*//**
-* @file     lpc_gpdma.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for GPDMA firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_GPDMA_H_
-#define __LPC_GPDMA_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
- * @{
- */
-
-/** DMA Connection number definitions */
-#define GPDMA_CONN_MCI              ((1UL))         /** SD card */
-#define GPDMA_CONN_SSP0_Tx          ((2UL))         /**< SSP0 Tx */
-#define GPDMA_CONN_SSP0_Rx          ((3UL))         /**< SSP0 Rx */
-#define GPDMA_CONN_SSP1_Tx          ((4UL))         /**< SSP1 Tx */
-#define GPDMA_CONN_SSP1_Rx          ((5UL))         /**< SSP1 Rx */
-#define GPDMA_CONN_SSP2_Tx          ((6UL))         /**< SSP2 Tx */
-#define GPDMA_CONN_SSP2_Rx          ((7UL))         /**< SSP2 Rx */
-#define GPDMA_CONN_ADC              ((8UL))         /**< ADC */
-#define GPDMA_CONN_DAC              ((9UL))         /**< DAC */
-#define GPDMA_CONN_UART0_Tx         ((10UL))        /**< UART0 Tx */
-#define GPDMA_CONN_UART0_Rx         ((11UL))        /**< UART0 Rx */
-#define GPDMA_CONN_UART1_Tx         ((12UL))        /**< UART1 Tx */
-#define GPDMA_CONN_UART1_Rx         ((13UL))        /**< UART1 Rx */
-#define GPDMA_CONN_UART2_Tx         ((14UL))        /**< UART2 Tx */
-#define GPDMA_CONN_UART2_Rx         ((15UL))        /**< UART2 Rx */
-#define GPDMA_CONN_MAT0_0           ((16UL))        /**< MAT0.0 */
-#define GPDMA_CONN_MAT0_1           ((17UL))        /**< MAT0.1 */
-#define GPDMA_CONN_MAT1_0           ((18UL))        /**< MAT1.0 */
-#define GPDMA_CONN_MAT1_1           ((19UL))        /**< MAT1.1 */
-#define GPDMA_CONN_MAT2_0           ((20UL))        /**< MAT2.0 */
-#define GPDMA_CONN_MAT2_1           ((21UL))        /**< MAT2.1 */
-#define GPDMA_CONN_I2S_Channel_0    ((22UL))        /**< I2S channel 0 */
-#define GPDMA_CONN_I2S_Channel_1    ((23UL))        /**< I2S channel 1 */
-#define GPDMA_CONN_UART3_Tx         ((26UL))        /**< UART3 Tx */
-#define GPDMA_CONN_UART3_Rx         ((27UL))        /**< UART3 Rx */
-#define GPDMA_CONN_UART4_Tx         ((28UL))        /**< UART3 Tx */
-#define GPDMA_CONN_UART4_Rx         ((29UL))        /**< UART3 Rx */
-#define GPDMA_CONN_MAT3_0           ((30UL))        /**< MAT3.0 */
-#define GPDMA_CONN_MAT3_1           ((31UL))        /**< MAT3.1 */
-
-/** GPDMA Transfer type definitions: Memory to memory - DMA control */
-#define GPDMA_TRANSFERTYPE_M2M      ((0UL))
-/** GPDMA Transfer type definitions: Memory to peripheral - DMA control */
-#define GPDMA_TRANSFERTYPE_M2P      ((1UL))
-/** GPDMA Transfer type definitions: Peripheral to memory - DMA control */
-#define GPDMA_TRANSFERTYPE_P2M      ((2UL))
-/** Source peripheral to destination peripheral - DMA control */
-#define GPDMA_TRANSFERTYPE_P2P      ((3UL))
-/** Memory to peripheral - Destination peripheral control */
-#define GPDMA_TRANSFERTYPE_M2P_DEST_CTRL        ((5UL))
-/** Peripheral to memory - Source peripheral control */
-#define GPDMA_TRANSFERTYPE_P2M_SRC_CTRL         ((6UL))
-
-/** Burst size in Source and Destination definitions */
-#define GPDMA_BSIZE_1   ((0UL)) /**< Burst size = 1 */
-#define GPDMA_BSIZE_4   ((1UL)) /**< Burst size = 4 */
-#define GPDMA_BSIZE_8   ((2UL)) /**< Burst size = 8 */
-#define GPDMA_BSIZE_16  ((3UL)) /**< Burst size = 16 */
-#define GPDMA_BSIZE_32  ((4UL)) /**< Burst size = 32 */
-#define GPDMA_BSIZE_64  ((5UL)) /**< Burst size = 64 */
-#define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
-#define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
-
-/** Width in Source transfer width and Destination transfer width definitions */
-#define GPDMA_WIDTH_BYTE        ((0UL)) /**< Width = 1 byte */
-#define GPDMA_WIDTH_HALFWORD    ((1UL)) /**< Width = 2 bytes */
-#define GPDMA_WIDTH_WORD        ((2UL)) /**< Width = 4 bytes */
-
-/** DMA Request Select Mode definitions */
-#define GPDMA_REQSEL_UART   ((0UL)) /**< UART TX/RX is selected */
-#define GPDMA_REQSEL_TIMER  ((1UL)) /**< Timer match is selected */
-
-/**
- * @}
- */
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/*********************************************************************//**
- * Macro defines for DMA Interrupt Status register
- **********************************************************************/
-#define GPDMA_DMACIntStat_Ch(n)         (((1UL<<n)&0xFF))
-#define GPDMA_DMACIntStat_BITMASK       ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Interrupt Terminal Count Request Status register
- **********************************************************************/
-#define GPDMA_DMACIntTCStat_Ch(n)       (((1UL<<n)&0xFF))
-#define GPDMA_DMACIntTCStat_BITMASK     ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Interrupt Terminal Count Request Clear register
- **********************************************************************/
-#define GPDMA_DMACIntTCClear_Ch(n)      (((1UL<<n)&0xFF))
-#define GPDMA_DMACIntTCClear_BITMASK    ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Interrupt Error Status register
- **********************************************************************/
-#define GPDMA_DMACIntErrStat_Ch(n)      (((1UL<<n)&0xFF))
-#define GPDMA_DMACIntErrStat_BITMASK    ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Interrupt Error Clear register
- **********************************************************************/
-#define GPDMA_DMACIntErrClr_Ch(n)       (((1UL<<n)&0xFF))
-#define GPDMA_DMACIntErrClr_BITMASK     ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Raw Interrupt Terminal Count Status register
- **********************************************************************/
-#define GPDMA_DMACRawIntTCStat_Ch(n)    (((1UL<<n)&0xFF))
-#define GPDMA_DMACRawIntTCStat_BITMASK  ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Raw Error Interrupt Status register
- **********************************************************************/
-#define GPDMA_DMACRawIntErrStat_Ch(n)   (((1UL<<n)&0xFF))
-#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Enabled Channel register
- **********************************************************************/
-#define GPDMA_DMACEnbldChns_Ch(n)       (((1UL<<n)&0xFF))
-#define GPDMA_DMACEnbldChns_BITMASK     ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Software Burst Request register
- **********************************************************************/
-#define GPDMA_DMACSoftBReq_Src(n)       (((1UL<<n)&0xFFFF))
-#define GPDMA_DMACSoftBReq_BITMASK      ((0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Software Single Request register
- **********************************************************************/
-#define GPDMA_DMACSoftSReq_Src(n)       (((1UL<<n)&0xFFFF))
-#define GPDMA_DMACSoftSReq_BITMASK      ((0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Software Last Burst Request register
- **********************************************************************/
-#define GPDMA_DMACSoftLBReq_Src(n)      (((1UL<<n)&0xFFFF))
-#define GPDMA_DMACSoftLBReq_BITMASK     ((0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Software Last Single Request register
- **********************************************************************/
-#define GPDMA_DMACSoftLSReq_Src(n)      (((1UL<<n)&0xFFFF))
-#define GPDMA_DMACSoftLSReq_BITMASK     ((0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Configuration register
- **********************************************************************/
-#define GPDMA_DMACConfig_E              ((0x01))     /**< DMA Controller enable*/
-#define GPDMA_DMACConfig_M              ((0x02))     /**< AHB Master endianness configuration*/
-#define GPDMA_DMACConfig_BITMASK        ((0x03))
-
-/*********************************************************************//**
- * Macro defines for DMA Synchronization register
- **********************************************************************/
-#define GPDMA_DMACSync_Src(n)           (((1UL<<n)&0xFFFF))
-#define GPDMA_DMACSync_BITMASK          ((0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Request Select register
- **********************************************************************/
-#define GPDMA_DMAReqSel_Input(n)        (((1UL<<(n-8))&0xFF))
-#define GPDMA_DMAReqSel_BITMASK         ((0xFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Channel Linked List Item registers
- **********************************************************************/
-/** DMA Channel Linked List Item registers bit mask*/
-#define GPDMA_DMACCxLLI_BITMASK         ((0xFFFFFFFC))
-
-/*********************************************************************//**
- * Macro defines for DMA channel control registers
- **********************************************************************/
-/** Transfer size*/
-#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))
-/** Source burst size*/
-#define GPDMA_DMACCxControl_SBSize(n)       (((n&0x07)<<12))
-/** Destination burst size*/
-#define GPDMA_DMACCxControl_DBSize(n)       (((n&0x07)<<15))
-/** Source transfer width*/
-#define GPDMA_DMACCxControl_SWidth(n)       (((n&0x07)<<18))
-/** Destination transfer width*/
-#define GPDMA_DMACCxControl_DWidth(n)       (((n&0x07)<<21))
-/** Source increment*/
-#define GPDMA_DMACCxControl_SI              ((1UL<<26))
-/** Destination increment*/
-#define GPDMA_DMACCxControl_DI              ((1UL<<27))
-/** Indicates that the access is in user mode or privileged mode*/
-#define GPDMA_DMACCxControl_Prot1           ((1UL<<28))
-/** Indicates that the access is bufferable or not bufferable*/
-#define GPDMA_DMACCxControl_Prot2           ((1UL<<29))
-/** Indicates that the access is cacheable or not cacheable*/
-#define GPDMA_DMACCxControl_Prot3           ((1UL<<30))
-/** Terminal count interrupt enable bit */
-#define GPDMA_DMACCxControl_I               ((1UL<<31))
-/** DMA channel control registers bit mask */
-#define GPDMA_DMACCxControl_BITMASK         ((0xFCFFFFFF))
-
-/*********************************************************************//**
- * Macro defines for DMA Channel Configuration registers
- **********************************************************************/
-/** DMA control enable*/
-#define GPDMA_DMACCxConfig_E                    ((1UL<<0))
-/** Source peripheral*/
-#define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n&0x1F)<<1))
-/** Destination peripheral*/
-#define GPDMA_DMACCxConfig_DestPeripheral(n)    (((n&0x1F)<<6))
-/** This value indicates the type of transfer*/
-#define GPDMA_DMACCxConfig_TransferType(n)      (((n&0x7)<<11))
-/** Interrupt error mask*/
-#define GPDMA_DMACCxConfig_IE                   ((1UL<<14))
-/** Terminal count interrupt mask*/
-#define GPDMA_DMACCxConfig_ITC                  ((1UL<<15))
-/** Lock*/
-#define GPDMA_DMACCxConfig_L                    ((1UL<<16))
-/** Active*/
-#define GPDMA_DMACCxConfig_A                    ((1UL<<17))
-/** Halt*/
-#define GPDMA_DMACCxConfig_H                    ((1UL<<18))
-/** DMA Channel Configuration registers bit mask */
-#define GPDMA_DMACCxConfig_BITMASK              ((0x7FFFF))
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup GPDMA_Public_Types GPDMA Public Types
- * @{
- */
-
-/**
- * @brief GPDMA Status enumeration
- */
-typedef enum {
-    GPDMA_STAT_INT,         /**< GPDMA Interrupt Status */
-    GPDMA_STAT_INTTC,       /**< GPDMA Interrupt Terminal Count Request Status */
-    GPDMA_STAT_INTERR,      /**< GPDMA Interrupt Error Status */
-    GPDMA_STAT_RAWINTTC,    /**< GPDMA Raw Interrupt Terminal Count Status */
-    GPDMA_STAT_RAWINTERR,   /**< GPDMA Raw Error Interrupt Status */
-    GPDMA_STAT_ENABLED_CH   /**< GPDMA Enabled Channel Status */
-} GPDMA_Status_Type;
-
-/**
- * @brief GPDMA Interrupt clear status enumeration
- */
-typedef enum{
-    GPDMA_STATCLR_INTTC,    /**< GPDMA Interrupt Terminal Count Request Clear */
-    GPDMA_STATCLR_INTERR    /**< GPDMA Interrupt Error Clear */
-}GPDMA_StateClear_Type;
-
-/**
- * @brief GPDMA Channel configuration structure type definition
- */
-typedef struct {
-    uint32_t ChannelNum;    /**< DMA channel number, should be in
-                                range from 0 to 7.
-                                Note: DMA channel 0 has the highest priority
-                                and DMA channel 7 the lowest priority.
-                                */
-    uint32_t TransferSize;  /**< Length/Size of transfer */
-    uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
-    uint32_t SrcMemAddr;    /**< Physical Source Address, used in case TransferType is chosen as
-                                 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
-    uint32_t DstMemAddr;    /**< Physical Destination Address, used in case TransferType is chosen as
-                                 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
-    uint32_t TransferType;  /**< Transfer Type, should be one of the following:
-                            - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
-                            - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
-                            - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
-                            - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
-                            */
-    uint32_t SrcConn;       /**< Peripheral Source Connection type, used in case TransferType is chosen as
-                            GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
-                            following:
-                             - GPDMA_CONN_SSP0_Tx: SSP0, Tx
-                             - GPDMA_CONN_SSP0_Rx: SSP0, Rx
-                             - GPDMA_CONN_SSP1_Tx: SSP1, Tx
-                             - GPDMA_CONN_SSP1_Rx: SSP1, Rx
-                             - GPDMA_CONN_ADC: ADC
-                             - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
-                             - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
-                             - GPDMA_CONN_DAC: DAC
-                             - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
-                             - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
-                             - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
-                             - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
-                             - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
-                             - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
-                             - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
-                             - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
-                             */
-    uint32_t DstConn;       /**< Peripheral Destination Connection type, used in case TransferType is chosen as
-                            GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
-                            following:
-                             - GPDMA_CONN_SSP0_Tx: SSP0, Tx
-                             - GPDMA_CONN_SSP0_Rx: SSP0, Rx
-                             - GPDMA_CONN_SSP1_Tx: SSP1, Tx
-                             - GPDMA_CONN_SSP1_Rx: SSP1, Rx
-                             - GPDMA_CONN_ADC: ADC
-                             - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
-                             - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
-                             - GPDMA_CONN_DAC: DAC
-                             - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
-                             - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
-                             - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
-                             - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
-                             - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
-                             - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
-                             - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
-                             - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
-                             */
-    uint32_t DMALLI;        /**< Linker List Item structure data address
-                            if there's no Linker List, set as '0'
-                            */
-} GPDMA_Channel_CFG_Type;
-
-/**
- * @brief GPDMA Linker List Item structure type definition
- */
-typedef struct {
-    uint32_t SrcAddr;   /**< Source Address */
-    uint32_t DstAddr;   /**< Destination address */
-    uint32_t NextLLI;   /**< Next LLI address, otherwise set to '0' */
-    uint32_t Control;   /**< GPDMA Control of this LLI */
-} GPDMA_LLI_Type;
-
-
-/**
- * @}
- */
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup GPDMA_Public_Functions GPDMA Public Functions
- * @{
- */
-
-void GPDMA_Init(void);
-Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
-IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
-void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
-void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
-//void GPDMA_IntHandler(void);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_GPDMA_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_gpio.h

@@ -1,188 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_gpio.h          2011-06-02
-*//**
-* @file     lpc_gpio.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for GPIO firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup GPIO  GPIO (General Purpose Input/Output)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_GPIO_H_
-#define __LPC_GPIO_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup GPIO_Public_Macros GPIO Public Macros
- * @{
- */
-
-#define GPIO_DIRECTION_INPUT        (0)
-#define GPIO_DIRECTION_OUTPUT       (1)
-
-/** Fast GPIO port 0 byte accessible definition */
-#define GPIO0_Byte  ((GPIO_Byte_TypeDef *)(LPC_GPIO0_BASE))
-/** Fast GPIO port 1 byte accessible definition */
-#define GPIO1_Byte  ((GPIO_Byte_TypeDef *)(LPC_GPIO1_BASE))
-/** Fast GPIO port 2 byte accessible definition */
-#define GPIO2_Byte  ((GPIO_Byte_TypeDef *)(LPC_GPIO2_BASE))
-/** Fast GPIO port 3 byte accessible definition */
-#define GPIO3_Byte  ((GPIO_Byte_TypeDef *)(LPC_GPIO3_BASE))
-/** Fast GPIO port 4 byte accessible definition */
-#define GPIO4_Byte  ((GPIO_Byte_TypeDef *)(LPC_GPIO4_BASE))
-/** Fast GPIO port 4 byte accessible definition */
-#define GPIO5_Byte  ((GPIO_Byte_TypeDef *)(LPC_GPIO5_BASE))
-
-
-
-/** Fast GPIO port 0 half-word accessible definition */
-#define GPIO0_HalfWord  ((GPIO_HalfWord_TypeDef *)(LPC_GPIO0_BASE))
-/** Fast GPIO port 1 half-word accessible definition */
-#define GPIO1_HalfWord  ((GPIO_HalfWord_TypeDef *)(LPC_GPIO1_BASE))
-/** Fast GPIO port 2 half-word accessible definition */
-#define GPIO2_HalfWord  ((GPIO_HalfWord_TypeDef *)(LPC_GPIO2_BASE))
-/** Fast GPIO port 3 half-word accessible definition */
-#define GPIO3_HalfWord  ((GPIO_HalfWord_TypeDef *)(LPC_GPIO3_BASE))
-/** Fast GPIO port 4 half-word accessible definition */
-#define GPIO4_HalfWord  ((GPIO_HalfWord_TypeDef *)(LPC_GPIO4_BASE))
-/** Fast GPIO port 4 half-word accessible definition */
-#define GPIO5_HalfWord  ((GPIO_HalfWord_TypeDef *)(LPC_GPIO5_BASE))
-
-/**
- * @}
- */
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup GPIO_Public_Types GPIO Public Types
- * @{
- */
-
-/**
- * @brief Fast GPIO port byte type definition
- */
-typedef struct {
-    __IO uint8_t FIODIR[4];     /**< FIO direction register in byte-align */
-       uint32_t RESERVED0[3];   /**< Reserved */
-    __IO uint8_t FIOMASK[4];    /**< FIO mask register in byte-align */
-    __IO uint8_t FIOPIN[4];     /**< FIO pin register in byte align */
-    __IO uint8_t FIOSET[4];     /**< FIO set register in byte-align */
-    __O  uint8_t FIOCLR[4];     /**< FIO clear register in byte-align */
-} GPIO_Byte_TypeDef;
-
-
-/**
- * @brief Fast GPIO port half-word type definition
- */
-typedef struct {
-    __IO uint16_t FIODIRL;      /**< FIO direction register lower halfword part */
-    __IO uint16_t FIODIRU;      /**< FIO direction register upper halfword part */
-       uint32_t RESERVED0[3];   /**< Reserved */
-    __IO uint16_t FIOMASKL;     /**< FIO mask register lower halfword part */
-    __IO uint16_t FIOMASKU;     /**< FIO mask register upper halfword part */
-    __IO uint16_t FIOPINL;      /**< FIO pin register lower halfword part */
-    __IO uint16_t FIOPINU;      /**< FIO pin register upper halfword part */
-    __IO uint16_t FIOSETL;      /**< FIO set register lower halfword part */
-    __IO uint16_t FIOSETU;      /**< FIO set register upper halfword part */
-    __O  uint16_t FIOCLRL;      /**< FIO clear register lower halfword part */
-    __O  uint16_t FIOCLRU;      /**< FIO clear register upper halfword part */
-} GPIO_HalfWord_TypeDef;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup GPIO_Public_Functions GPIO Public Functions
- * @{
- */
-
-/* GPIO style ------------------------------- */
-void GPIO_Init(void);
-void GPIO_Deinit(void);
-void GPIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
-void GPIO_SetValue(uint8_t portNum, uint32_t bitValue);
-void GPIO_ClearValue(uint8_t portNum, uint32_t bitValue);
-void GPIO_OutputValue(uint8_t portNum, uint32_t bitMask, uint8_t value);
-uint32_t GPIO_ReadValue(uint8_t portNum);
-void GPIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
-FunctionalState GPIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
-void GPIO_ClearInt(uint8_t portNum, uint32_t bitValue);
-
-/* FIO (word-accessible) style ------------------------------- */
-void FIO_SetDir(uint8_t portNum, uint32_t bitValue, uint8_t dir);
-void FIO_SetValue(uint8_t portNum, uint32_t bitValue);
-void FIO_ClearValue(uint8_t portNum, uint32_t bitValue);
-uint32_t FIO_ReadValue(uint8_t portNum);
-void FIO_SetMask(uint8_t portNum, uint32_t bitValue, uint8_t maskValue);
-void FIO_IntCmd(uint8_t portNum, uint32_t bitValue, uint8_t edgeState);
-FunctionalState FIO_GetIntStatus(uint8_t portNum, uint32_t pinNum, uint8_t edgeState);
-void FIO_ClearInt(uint8_t portNum, uint32_t pinNum);
-
-/* FIO (halfword-accessible) style ------------------------------- */
-void FIO_HalfWordSetDir(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t dir);
-void FIO_HalfWordSetMask(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue, uint8_t maskValue);
-void FIO_HalfWordSetValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
-void FIO_HalfWordClearValue(uint8_t portNum, uint8_t halfwordNum, uint16_t bitValue);
-uint16_t FIO_HalfWordReadValue(uint8_t portNum, uint8_t halfwordNum);
-
-/* FIO (byte-accessible) style ------------------------------- */
-void FIO_ByteSetDir(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t dir);
-void FIO_ByteSetMask(uint8_t portNum, uint8_t byteNum, uint8_t bitValue, uint8_t maskValue);
-void FIO_ByteSetValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
-void FIO_ByteClearValue(uint8_t portNum, uint8_t byteNum, uint8_t bitValue);
-uint8_t FIO_ByteReadValue(uint8_t portNum, uint8_t byteNum);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_GPIO_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_i2c.h

@@ -1,420 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_i2c.h           2011-06-02
-*//**
-* @file     lpc_i2c.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for I2C firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup I2C   I2C (Inter-IC Control bus)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_I2C_H_
-#define __LPC_I2C_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup I2C_Private_Macros I2C Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/*******************************************************************//**
- * I2C Control Set register description
- *********************************************************************/
-#define I2C_I2CONSET_AA             ((0x04)) /*!< Assert acknowledge flag */
-#define I2C_I2CONSET_SI             ((0x08)) /*!< I2C interrupt flag */
-#define I2C_I2CONSET_STO            ((0x10)) /*!< STOP flag */
-#define I2C_I2CONSET_STA            ((0x20)) /*!< START flag */
-#define I2C_I2CONSET_I2EN           ((0x40)) /*!< I2C interface enable */
-
-/*******************************************************************//**
- * I2C Control Clear register description
- *********************************************************************/
-/** Assert acknowledge Clear bit */
-#define I2C_I2CONCLR_AAC            ((1<<2))
-/** I2C interrupt Clear bit */
-#define I2C_I2CONCLR_SIC            ((1<<3))
-/** I2C STOP Clear bit */
-#define I2C_I2CONCLR_STOC           ((1<<4))
-/** START flag Clear bit */
-#define I2C_I2CONCLR_STAC           ((1<<5))
-/** I2C interface Disable bit */
-#define I2C_I2CONCLR_I2ENC          ((1<<6))
-
-/********************************************************************//**
- * I2C Status Code definition (I2C Status register)
- *********************************************************************/
-/* Return Code in I2C status register */
-#define I2C_STAT_CODE_BITMASK       ((0xF8))
-
-/* I2C return status code definitions ----------------------------- */
-
-/** No relevant information */
-#define I2C_I2STAT_NO_INF                       ((0xF8))
-
-/** Bus Error */
-#define I2C_I2STAT_BUS_ERROR                    ((0x00))
-
-/* Master transmit mode -------------------------------------------- */
-/** A start condition has been transmitted */
-#define I2C_I2STAT_M_TX_START                   ((0x08))
-
-/** A repeat start condition has been transmitted */
-#define I2C_I2STAT_M_TX_RESTART                 ((0x10))
-
-/** SLA+W has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_TX_SLAW_ACK                ((0x18))
-
-/** SLA+W has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_TX_SLAW_NACK               ((0x20))
-
-/** Data has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_TX_DAT_ACK                 ((0x28))
-
-/** Data has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_TX_DAT_NACK                ((0x30))
-
-/** Arbitration lost in SLA+R/W or Data bytes */
-#define I2C_I2STAT_M_TX_ARB_LOST                ((0x38))
-
-/* Master receive mode -------------------------------------------- */
-/** A start condition has been transmitted */
-#define I2C_I2STAT_M_RX_START                   ((0x08))
-
-/** A repeat start condition has been transmitted */
-#define I2C_I2STAT_M_RX_RESTART                 ((0x10))
-
-/** Arbitration lost */
-#define I2C_I2STAT_M_RX_ARB_LOST                ((0x38))
-
-/** SLA+R has been transmitted, ACK has been received */
-#define I2C_I2STAT_M_RX_SLAR_ACK                ((0x40))
-
-/** SLA+R has been transmitted, NACK has been received */
-#define I2C_I2STAT_M_RX_SLAR_NACK               ((0x48))
-
-/** Data has been received, ACK has been returned */
-#define I2C_I2STAT_M_RX_DAT_ACK                 ((0x50))
-
-/** Data has been received, NACK has been return */
-#define I2C_I2STAT_M_RX_DAT_NACK                ((0x58))
-
-/* Slave receive mode -------------------------------------------- */
-/** Own slave address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_SLAW_ACK                ((0x60))
-
-/** Arbitration lost in SLA+R/W as master */
-#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA          ((0x68))
-
-/** General call address has been received, ACK has been returned */
-#define I2C_I2STAT_S_RX_GENCALL_ACK             ((0x70))
-
-/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
-#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL      ((0x78))
-
-/** Previously addressed with own SLV address;
- * Data has been received, ACK has been return */
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK         ((0x80))
-
-/** Previously addressed with own SLA;
- * Data has been received and NOT ACK has been return */
-#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK        ((0x88))
-
-/** Previously addressed with General Call;
- * Data has been received and ACK has been return */
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK     ((0x90))
-
-/** Previously addressed with General Call;
- * Data has been received and NOT ACK has been return */
-#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK    ((0x98))
-
-/** A STOP condition or repeated START condition has
- * been received while still addressed as SLV/REC
- * (Slave Receive) or SLV/TRX (Slave Transmit) */
-#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX   ((0xA0))
-
-/** Slave transmit mode */
-/** Own SLA+R has been received, ACK has been returned */
-#define I2C_I2STAT_S_TX_SLAR_ACK                ((0xA8))
-
-/** Arbitration lost in SLA+R/W as master */
-#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA          ((0xB0))
-
-/** Data has been transmitted, ACK has been received */
-#define I2C_I2STAT_S_TX_DAT_ACK                 ((0xB8))
-
-/** Data has been transmitted, NACK has been received */
-#define I2C_I2STAT_S_TX_DAT_NACK                ((0xC0))
-
-/** Last data byte in I2DAT has been transmitted (AA = 0);
- ACK has been received */
-#define I2C_I2STAT_S_TX_LAST_DAT_ACK            ((0xC8))
-
-/** Time out in case of using I2C slave mode */
-#define I2C_SLAVE_TIME_OUT                      0x10000UL
-
-/********************************************************************//**
- * I2C Data register definition
- *********************************************************************/
-/** Mask for I2DAT register*/
-#define I2C_I2DAT_BITMASK           ((0xFF))
-
-/** Idle data value will be send out in slave mode in case of the actual
- * expecting data requested from the master is greater than its sending data
- * length that can be supported */
-#define I2C_I2DAT_IDLE_CHAR         (0xFF)
-
-/********************************************************************//**
- * I2C Monitor mode control register description
- *********************************************************************/
-#define I2C_I2MMCTRL_MM_ENA         ((1<<0))        /**< Monitor mode enable */
-#define I2C_I2MMCTRL_ENA_SCL        ((1<<1))        /**< SCL output enable */
-#define I2C_I2MMCTRL_MATCH_ALL      ((1<<2))        /**< Select interrupt register match */
-#define I2C_I2MMCTRL_BITMASK        ((0x07))        /**< Mask for I2MMCTRL register */
-
-/********************************************************************//**
- * I2C Data buffer register description
- *********************************************************************/
-/** I2C Data buffer register bit mask */
-#define I2DATA_BUFFER_BITMASK       ((0xFF))
-
-/********************************************************************//**
- * I2C Slave Address registers definition
- *********************************************************************/
-/** General Call enable bit */
-#define I2C_I2ADR_GC                ((1<<0))
-
-/** I2C Slave Address registers bit mask */
-#define I2C_I2ADR_BITMASK           ((0xFF))
-
-/********************************************************************//**
- * I2C Mask Register definition
- *********************************************************************/
-/** I2C Mask Register mask field */
-#define I2C_I2MASK_MASK(n)          ((n&0xFE))
-
-/********************************************************************//**
- * I2C SCL HIGH duty cycle Register definition
- *********************************************************************/
-/** I2C SCL HIGH duty cycle Register bit mask */
-#define I2C_I2SCLH_BITMASK          ((0xFFFF))
-
-/********************************************************************//**
- * I2C SCL LOW duty cycle Register definition
- *********************************************************************/
-/** I2C SCL LOW duty cycle Register bit mask */
-#define I2C_I2SCLL_BITMASK          ((0xFFFF))
-
-
-/* I2C status values */
-#define I2C_SETUP_STATUS_ARBF   (1<<8)  /**< Arbitration false */
-#define I2C_SETUP_STATUS_NOACKF (1<<9)  /**< No ACK returned */
-#define I2C_SETUP_STATUS_DONE   (1<<10) /**< Status DONE */
-
-
-/* I2C state handle return values */
-#define I2C_OK                  0x00
-#define I2C_BYTE_SENT               0x01
-#define I2C_BYTE_RECV               0x02
-#define I2C_LAST_BYTE_RECV      0x04
-#define I2C_SEND_END                0x08
-#define I2C_RECV_END                0x10
-#define I2C_STA_STO_RECV            0x20
-
-
-#define I2C_ERR                     (0x10000000)
-#define I2C_NAK_RECV                (0x10000000 |0x01)
-
-#define I2C_CheckError(ErrorCode)   (ErrorCode & 0x10000000)
-
-/**
- * @}
- */
-
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup I2C_Public_Types I2C Public Types
- * @{
- */
-
-typedef enum
-{
-    I2C_0 = 0,
-    I2C_1,
-    I2C_2
-} en_I2C_unitId;
-
-typedef enum
-{
-    I2C_MASTER_MODE,
-    I2C_SLAVE_MODE,
-    I2C_GENERAL_MODE,
-} en_I2C_Mode;
-/**
- * @brief I2C Own slave address setting structure
- */
-typedef struct
-{
-    uint8_t SlaveAddrChannel;   /**< Slave Address channel in I2C control,
-                                should be in range from 0..3
-                                */
-    uint8_t SlaveAddr_7bit;     /**< Value of 7-bit slave address */
-    uint8_t GeneralCallState;   /**< Enable/Disable General Call Functionality
-                                when I2C control being in Slave mode, should be:
-                                - ENABLE: Enable General Call function.
-                                - DISABLE: Disable General Call function.
-                                */
-    uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
-                                which is set to '1' will cause an automatic compare on
-                                the corresponding bit of the received address when it
-                                is compared to the SlaveAddr_7bit value associated with this
-                                mask register. In other words, bits in SlaveAddr_7bit value
-                                which are masked are not taken into account in determining
-                                an address match
-                                */
-} I2C_OWNSLAVEADDR_CFG_Type;
-
-
-/**
- * @brief Master transfer setup data structure definitions
- */
-typedef struct
-{
-  uint32_t          sl_addr7bit;                /**< Slave address in 7bit mode */
-  __IO uint8_t*     tx_data;                    /**< Pointer to Transmit data - NULL if data transmit
-                                                      is not used */
-  uint32_t          tx_length;                  /**< Transmit data length - 0 if data transmit
-                                                      is not used*/
-  __IO uint32_t     tx_count;                   /**< Current Transmit data counter */
-  __IO uint8_t*     rx_data;                    /**< Pointer to Receive data - NULL if data receive
-                                                      is not used */
-  uint32_t          rx_length;                  /**< Receive data length - 0 if data receive is
-                                                       not used */
-  __IO uint32_t     rx_count;                   /**< Current Receive data counter */
-  uint32_t          retransmissions_max;        /**< Max Re-Transmission value */
-  uint32_t          retransmissions_count;      /**< Current Re-Transmission counter */
-  __IO uint32_t     status;                     /**< Current status of I2C activity */
-  void              (*callback)(void);          /**< Pointer to Call back function when transmission complete
-                                                    used in interrupt transfer mode */
-} I2C_M_SETUP_Type;
-
-
-/**
- * @brief Slave transfer setup data structure definitions
- */
-typedef struct
-{
-  __IO uint8_t*         tx_data;
-  uint32_t              tx_length;
-  __IO uint32_t         tx_count;
-  __IO uint8_t*         rx_data;
-  uint32_t              rx_length;
-  __IO uint32_t         rx_count;
-  __IO uint32_t         status;
-  void              (*callback)(void);
-} I2C_S_SETUP_Type;
-
-/**
- * @brief Transfer option type definitions
- */
-typedef enum
-{
-    I2C_TRANSFER_POLLING = 0,       /**< Transfer in polling mode */
-    I2C_TRANSFER_INTERRUPT          /**< Transfer in interrupt mode */
-} I2C_TRANSFER_OPT_Type;
-
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup I2C_Public_Functions I2C Public Functions
- * @{
- */
-
-/* I2C Init/DeInit functions ---------- */
-void I2C_Init(en_I2C_unitId i2cId, uint32_t clockrate);
-void I2C_DeInit(en_I2C_unitId i2cId);
-void I2C_Cmd(en_I2C_unitId i2cId, en_I2C_Mode Mode, FunctionalState NewState);
-
-/* I2C transfer data functions -------- */
-Status I2C_MasterTransferData(en_I2C_unitId i2cId,
-                I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-Status I2C_SlaveTransferData(en_I2C_unitId i2cId,
-                I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
-uint32_t I2C_MasterTransferComplete(en_I2C_unitId i2cId);
-uint32_t I2C_SlaveTransferComplete(en_I2C_unitId i2cId);
-
-
-void I2C_SetOwnSlaveAddr(en_I2C_unitId i2cId, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
-uint8_t I2C_GetLastStatusCode(en_I2C_unitId i2cId);
-
-/* I2C Monitor functions ---------------*/
-void I2C_MonitorModeConfig(en_I2C_unitId i2cId, uint32_t MonitorCfgType, FunctionalState NewState);
-void I2C_MonitorModeCmd(en_I2C_unitId i2cId, FunctionalState NewState);
-uint8_t I2C_MonitorGetDatabuffer(en_I2C_unitId i2cId);
-BOOL_8 I2C_MonitorHandler(en_I2C_unitId i2cId, uint8_t *buffer, uint32_t size);
-
-/* I2C Interrupt handler functions ------*/
-void I2C_IntCmd (en_I2C_unitId i2cId, Bool NewState);
-void I2C_MasterHandler (en_I2C_unitId i2cId);
-void I2C_SlaveHandler (en_I2C_unitId i2cId);
-
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_I2C_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_i2s.h

@@ -1,351 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_i2s.h           2011-06-02
-*//**
-* @file     lpc_i2s.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for I2S firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup I2S   I2S (Inter-IC Sound bus)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_I2S_H_
-#define __LPC_I2S_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup I2S_Public_Macros I2S Public Macros
- * @{
- */
-
-/*********************************************************************//**
- * I2S configuration parameter defines
- **********************************************************************/
-/** I2S Wordwidth bit */
-#define I2S_WORDWIDTH_8     ((uint32_t)(0))
-#define I2S_WORDWIDTH_16    ((uint32_t)(1))
-#define I2S_WORDWIDTH_32    ((uint32_t)(3))
-/** I2S Channel bit */
-#define I2S_STEREO          ((uint32_t)(0))
-#define I2S_MONO            ((uint32_t)(1))
-/** I2S Master/Slave mode bit */
-#define I2S_MASTER_MODE     ((uint8_t)(0))
-#define I2S_SLAVE_MODE      ((uint8_t)(1))
-/** I2S Stop bit */
-#define I2S_STOP_ENABLE     ((uint8_t)(1))
-#define I2S_STOP_DISABLE    ((uint8_t)(0))
-/** I2S Reset bit */
-#define I2S_RESET_ENABLE    ((uint8_t)(1))
-#define I2S_RESET_DISABLE   ((uint8_t)(0))
-/** I2S Mute bit */
-#define I2S_MUTE_ENABLE     ((uint8_t)(1))
-#define I2S_MUTE_DISABLE    ((uint8_t)(0))
-/** I2S Transmit/Receive bit */
-#define I2S_TX_MODE         ((uint8_t)(0))
-#define I2S_RX_MODE         ((uint8_t)(1))
-/** I2S Clock Select bit */
-#define I2S_CLKSEL_FRDCLK   ((uint8_t)(0))
-#define I2S_CLKSEL_MCLK     ((uint8_t)(2))
-/** I2S 4-pin Mode bit */
-#define I2S_4PIN_ENABLE     ((uint8_t)(1))
-#define I2S_4PIN_DISABLE    ((uint8_t)(0))
-/** I2S MCLK Enable bit */
-#define I2S_MCLK_ENABLE     ((uint8_t)(1))
-#define I2S_MCLK_DISABLE    ((uint8_t)(0))
-/** I2S select DMA bit */
-#define I2S_DMA_1           ((uint8_t)(0))
-#define I2S_DMA_2           ((uint8_t)(1))
-
-/**
- * @}
- */
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup I2S_Private_Macros I2S Private Macros
- * @{
- */
-
-/*********************************************************************//**
- * Macro defines for DAO-Digital Audio Output register
- **********************************************************************/
-/** I2S wordwide - the number of bytes in data output - 8 bits*/
-#define I2S_DAO_WORDWIDTH_8     ((uint32_t)(0))
-/** I2S wordwide - the number of bytes in data output - 16 bits*/
-#define I2S_DAO_WORDWIDTH_16    ((uint32_t)(1)) 
-/** I2S wordwide - the number of bytes in data output - 32 bits*/
-#define I2S_DAO_WORDWIDTH_32    ((uint32_t)(3)) 
-/** I2S control mono or stereo format */
-#define I2S_DAO_MONO            ((uint32_t)(1<<2))
-/** I2S control stop mode */
-#define I2S_DAO_STOP            ((uint32_t)(1<<3))
-/** I2S control reset mode */
-#define I2S_DAO_RESET           ((uint32_t)(1<<4))
-/** I2S control master/slave mode */
-#define I2S_DAO_SLAVE           ((uint32_t)(1<<5))
-/** I2S word select half period minus one */
-#define I2S_DAO_WS_HALFPERIOD(n)    ((uint32_t)(n<<6))
-/** I2S control mute mode */
-#define I2S_DAO_MUTE            ((uint32_t)(1<<15))
-
-/*********************************************************************//**
- * Macro defines for DAI-Digital Audio Input register
-**********************************************************************/
-/** I2S wordwide - the number of bytes in data input - 8 bit*/
-#define I2S_DAI_WORDWIDTH_8     ((uint32_t)(0))
-/** I2S wordwide - the number of bytes in data input - 16 bit*/
-#define I2S_DAI_WORDWIDTH_16    ((uint32_t)(1))
-/** I2S wordwide - the number of bytes in data input - 32 bit*/
-#define I2S_DAI_WORDWIDTH_32    ((uint32_t)(3))
-/** I2S control mono or stereo format */
-#define I2S_DAI_MONO            ((uint32_t)(1<<2))
-/** I2S control stop mode */
-#define I2S_DAI_STOP            ((uint32_t)(1<<3))
-/** I2S control reset mode */
-#define I2S_DAI_RESET           ((uint32_t)(1<<4))
-/** I2S control master/slave mode */
-#define I2S_DAI_SLAVE           ((uint32_t)(1<<5))
-/** I2S word select half period minus one (9 bits)*/
-#define I2S_DAI_WS_HALFPERIOD(n)    ((uint32_t)((n&0x1FF)<<6))
-/** I2S control mute mode */
-#define I2S_DAI_MUTE            ((uint32_t)(1<<15))
-
-/*********************************************************************//**
- * Macro defines for STAT register (Status Feedback register)
-**********************************************************************/
-/** I2S Status Receive or Transmit Interrupt */
-#define I2S_STATE_IRQ       ((uint32_t)(1))
-/** I2S Status Receive or Transmit DMA1 */
-#define I2S_STATE_DMA1      ((uint32_t)(1<<1))
-/** I2S Status Receive or Transmit DMA2 */
-#define I2S_STATE_DMA2      ((uint32_t)(1<<2))
-/** I2S Status Current level of the Receive FIFO (5 bits)*/
-#define I2S_STATE_RX_LEVEL(n)   ((uint32_t)((n&1F)<<8))
-/** I2S Status Current level of the Transmit FIFO (5 bits)*/
-#define I2S_STATE_TX_LEVEL(n)   ((uint32_t)((n&1F)<<16))
-
-/*********************************************************************//**
- * Macro defines for DMA1 register (DMA1 Configuration register)
-**********************************************************************/
-/** I2S control DMA1 for I2S receive */
-#define I2S_DMA1_RX_ENABLE      ((uint32_t)(1))
-/** I2S control DMA1 for I2S transmit */
-#define I2S_DMA1_TX_ENABLE      ((uint32_t)(1<<1))
-/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
-#define I2S_DMA1_RX_DEPTH(n)    ((uint32_t)((n&0x1F)<<8))
-/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
-#define I2S_DMA1_TX_DEPTH(n)    ((uint32_t)((n&0x1F)<<16))
-
-/*********************************************************************//**
- * Macro defines for DMA2 register (DMA2 Configuration register)
-**********************************************************************/
-/** I2S control DMA2 for I2S receive */
-#define I2S_DMA2_RX_ENABLE      ((uint32_t)(1))
-/** I2S control DMA1 for I2S transmit */
-#define I2S_DMA2_TX_ENABLE      ((uint32_t)(1<<1))
-/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
-#define I2S_DMA2_RX_DEPTH(n)    ((uint32_t)((n&0x1F)<<8))
-/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
-#define I2S_DMA2_TX_DEPTH(n)    ((uint32_t)((n&0x1F)<<16))
-
-/*********************************************************************//**
-* Macro defines for IRQ register (Interrupt Request Control register)
-**********************************************************************/
-/** I2S control I2S receive interrupt */
-#define I2S_IRQ_RX_ENABLE       ((uint32_t)(1))
-/** I2S control I2S transmit interrupt */
-#define I2S_IRQ_TX_ENABLE       ((uint32_t)(1<<1))
-/** I2S set the FIFO level on which to create an irq request */
-#define I2S_IRQ_RX_DEPTH(n)     ((uint32_t)((n&0x1F)<<8))
-/** I2S set the FIFO level on which to create an irq request */
-#define I2S_IRQ_TX_DEPTH(n)     ((uint32_t)((n&0x1F)<<16))
-
-/********************************************************************************//**
- * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
-*********************************************************************************/
-/** I2S Transmit MCLK rate denominator */
-#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
-/** I2S Transmit MCLK rate denominator */
-#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
-/** I2S Receive MCLK rate denominator */
-#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
-/** I2S Receive MCLK rate denominator */
-#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
-
-/*************************************************************************************//**
- * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
-**************************************************************************************/
-#define I2S_TXBITRATE(n)    ((uint32_t)(n&0x3F))
-#define I2S_RXBITRATE(n)    ((uint32_t)(n&0x3F))
-
-/**********************************************************************************//**
- * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
-************************************************************************************/
-/** I2S Transmit select clock source (2 bits)*/
-#define I2S_TXMODE_CLKSEL(n)    ((uint32_t)(n&0x03))
-/** I2S Transmit control 4-pin mode */
-#define I2S_TXMODE_4PIN_ENABLE  ((uint32_t)(1<<2))
-/** I2S Transmit control the TX_MCLK output */
-#define I2S_TXMODE_MCENA        ((uint32_t)(1<<3))
-/** I2S Receive select clock source */
-#define I2S_RXMODE_CLKSEL(n)    ((uint32_t)(n&0x03))
-/** I2S Receive control 4-pin mode */
-#define I2S_RXMODE_4PIN_ENABLE  ((uint32_t)(1<<2))
-/** I2S Receive control the TX_MCLK output */
-#define I2S_RXMODE_MCENA        ((uint32_t)(1<<3))
-
-/**
- * @}
- */
-
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup I2S_Public_Types I2S Public Types
- * @{
- */
-
-/**
- * @brief I2S configuration structure definition
- */
-typedef struct {
-    uint8_t wordwidth;      /** the number of bytes in data as follow:
-                            -I2S_WORDWIDTH_8: 8 bit data
-                            -I2S_WORDWIDTH_16: 16 bit data
-                            -I2S_WORDWIDTH_32: 32 bit data */
-    uint8_t mono;           /** Set mono/stereo mode, should be:
-                            - I2S_STEREO: stereo mode
-                            - I2S_MONO: mono mode */
-    uint8_t stop;           /** Disables accesses on FIFOs, should be:
-                            - I2S_STOP_ENABLE: enable stop mode
-                            - I2S_STOP_DISABLE: disable stop mode */
-    uint8_t reset;          /** Asynchronously reset tje transmit channel and FIFO, should be:
-                            - I2S_RESET_ENABLE: enable reset mode
-                            - I2S_RESET_DISABLE: disable reset mode */
-    uint8_t ws_sel;         /** Set Master/Slave mode, should be:
-                            - I2S_MASTER_MODE: I2S master mode
-                            - I2S_SLAVE_MODE: I2S slave mode */
-    uint8_t mute;           /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
-                            - I2S_MUTE_ENABLE: enable mute mode
-                            - I2S_MUTE_DISABLE: disable mute mode */
-    uint8_t Reserved0[2];
-} I2S_CFG_Type;
-
-/**
- * @brief I2S DMA configuration structure definition
- */
-typedef struct {
-    uint8_t DMAIndex;       /** Select DMA1 or DMA2, should be:
-                            - I2S_DMA_1: DMA1
-                            - I2S_DMA_2: DMA2 */
-    uint8_t depth;          /** FIFO level that triggers a DMA request */
-    uint8_t Reserved0[2];
-}I2S_DMAConf_Type;
-
-/**
- * @brief I2S mode configuration structure definition
- */
-typedef struct{
-    uint8_t clksel;         /** Clock source selection, should be:
-                            - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
-                            - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
-    uint8_t fpin;           /** Select four pin mode, should be:
-                            - I2S_4PIN_ENABLE: 4-pin enable
-                            - I2S_4PIN_DISABLE: 4-pin disable */
-    uint8_t mcena;          /** Select MCLK mode, should be:
-                            - I2S_MCLK_ENABLE: MCLK enable for output
-                            - I2S_MCLK_DISABLE: MCLK disable for output */
-    uint8_t Reserved;
-}I2S_MODEConf_Type;
-
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup I2S_Public_Functions I2S Public Functions
- * @{
- */
-/* I2S Init/DeInit functions ---------*/
-void I2S_Init(LPC_I2S_TypeDef *I2Sx);
-void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
-
-/* I2S configuration functions --------*/
-void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
-Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
-void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
-void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
-uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
-
-/* I2S operate functions -------------*/
-void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
-uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
-void I2S_Start(LPC_I2S_TypeDef *I2Sx);
-void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
-void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
-void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
-
-/* I2S DMA functions ----------------*/
-void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
-void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
-
-/* I2S IRQ functions ----------------*/
-void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
-void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
-FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
-uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_SSP_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_iap.h

@@ -1,153 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_iap.h           2011-11-21
-*//**
-* @file     lpc_iap.h
-* @brief          Contains all functions support for IAP
-*           on LPC
-* @version  1.0
-* @date     21. November. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef _LPC_IAP_H
-#define _LPC_IAP_H
-#include "lpc_types.h"
-
-/** @defgroup IAP   IAP (In Application Programming)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-/** @defgroup IAP_Public_Macros IAP Public Macros
- * @{
- */
-
-/** IAP entry location */
-#define IAP_LOCATION              (0x1FFF1FF1UL)
-
-/**
- * @}
- */
-
-/** @defgroup IAP_Public_Types IAP Public Types
- * @{
- */
-
-/**
- * @brief IAP command code definitions
- */
-typedef enum
-{
-    IAP_PREPARE = 50,       // Prepare sector(s) for write operation
-    IAP_COPY_RAM2FLASH = 51,     // Copy RAM to Flash
-    IAP_ERASE = 52,              // Erase sector(s)
-    IAP_BLANK_CHECK = 53,        // Blank check sector(s)
-    IAP_READ_PART_ID = 54,       // Read chip part ID
-    IAP_READ_BOOT_VER = 55,      // Read chip boot code version
-    IAP_COMPARE = 56,            // Compare memory areas
-    IAP_REINVOKE_ISP = 57,       // Reinvoke ISP
-    IAP_READ_SERIAL_NUMBER = 58, // Read serial number
-}  IAP_COMMAND_CODE;
-
-/**
- * @brief IAP status code definitions
- */
-typedef enum
-{
-    CMD_SUCCESS,                 // Command is executed successfully.
-    INVALID_COMMAND,             // Invalid command.
-    SRC_ADDR_ERROR,              // Source address is not on a word boundary.
-    DST_ADDR_ERROR,              // Destination address is not on a correct boundary.
-    SRC_ADDR_NOT_MAPPED,         // Source address is not mapped in the memory map.
-    DST_ADDR_NOT_MAPPED,         // Destination address is not mapped in the memory map.
-    COUNT_ERROR,                   // Byte count is not multiple of 4 or is not a permitted value.
-    INVALID_SECTOR,            // Sector number is invalid.
-    SECTOR_NOT_BLANK,              // Sector is not blank.
-    SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,    // Command to prepare sector for write operation was not executed.
-    COMPARE_ERROR,               // Source and destination data is not same.
-    BUSY,                          // Flash programming hardware interface is busy.
-} IAP_STATUS_CODE;
-
-/**
- * @brief IAP write length definitions
- */
-typedef enum {
-  IAP_WRITE_256  = 256,
-  IAP_WRITE_512  = 512,
-  IAP_WRITE_1024 = 1024,
-  IAP_WRITE_4096 = 4096,
-} IAP_WRITE_SIZE;
-
-/**
- * @brief IAP command structure
- */
-typedef struct {
-    uint32_t cmd;   // Command
-    uint32_t param[4];      // Parameters
-    uint32_t status;        // status code
-    uint32_t result[4];     // Result
-} IAP_COMMAND_Type;
-
-/**
- * @}
- */
- 
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup IAP_Public_Functions IAP Public Functions
- * @{
- */
-
-/**  Get sector number of an address */
-uint32_t GetSecNum (uint32_t adr);
-/**  Prepare sector(s) for write operation */
-IAP_STATUS_CODE PrepareSector(uint32_t start_sec, uint32_t end_sec);
-/**  Copy RAM to Flash */
-IAP_STATUS_CODE CopyRAM2Flash(uint8_t * dest, uint8_t* source, IAP_WRITE_SIZE size);
-/**  Prepare sector(s) for write operation */
-IAP_STATUS_CODE EraseSector(uint32_t start_sec, uint32_t end_sec);
-/**  Blank check sectors */
-IAP_STATUS_CODE BlankCheckSector(uint32_t start_sec, uint32_t end_sec,
-                                 uint32_t *first_nblank_loc, 
-                                 uint32_t *first_nblank_val);
-/**  Read part identification number */
-IAP_STATUS_CODE ReadPartID(uint32_t *partID);
-/**  Read boot code version */
-IAP_STATUS_CODE ReadBootCodeVer(uint8_t *major, uint8_t* minor);
-/**  Read Device serial number */
-IAP_STATUS_CODE ReadDeviceSerialNum(uint32_t *uid);
-/**  Compare memory */
-IAP_STATUS_CODE Compare(uint8_t *addr1, uint8_t *addr2, uint32_t size);
-/**  Invoke ISP */
-void InvokeISP(void);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#endif /*_LPC_IAP_H*/
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_lcd.h

@@ -1,232 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_lcd.h           2011-10-14
-*//**
-* @file     lpc_lcd.h
-* @brief    Contains all functions support for LCD firmware library
-*           on LPC
-* @version  1.0
-* @date     14. October. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-#include "lpc_types.h"
-
-#ifndef __LPC_LCD_H_
-#define __LPC_LCD_H_
-
-/** @defgroup LCD   LCD (Liquid Crystal Display)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-/** @defgroup LCD_Public_Macros LCD Public Macros
- * @{
- */
-
-#define LCD_PWR_ENA_DIS_DLY  10000
-#define LCD_FUNC_OK  0
-#define LCD_FUNC_ERR -1
-
-#define GET_CURSOR_IMG_SIZE(size)  ((size == 32) ? 64:256)
-
-/**
- * @}
- */
-
-/** @defgroup LCD_Public_Types LCD Public Types
- * @{
- */
-
-typedef enum __LCD_TYPES
-{
-  LCD_STN_MONOCHROME,
-  LCD_STN_COLOR,
-  LCD_TFT,
-  LCD_TYPE_UNKNOWN,
-} LCD_TYPES;
-
-typedef enum __LCD_BPP
-{
-  LCD_BPP_1 = 0x00,
-  LCD_BPP_2 = 0x01,
-  LCD_BPP_4 = 0x02,
-  LCD_BPP_8 = 0x03,
-  LCD_BPP_16 = 0x04,
-  LCD_BPP_24 = 0x05,
-  LCD_BPP_16_565Mode = 0x06,
-  LCD_BPP_12_444Mode = 0x07,
-} LCD_BPP;
-
-typedef enum __LCD_PANEL
-{
-  LCD_PANEL_UPPER,
-  LCD_PANEL_LOWER,
-}LCD_PANEL;
-
-/**
- * @brief A struct for Bitmap on LCD screen
- */
-typedef struct _Bmp_t 
-{
-  uint32_t  H_Size;
-  uint32_t  V_Size;
-  uint32_t  BitsPP;
-  uint32_t  BytesPP;
-  uint8_t *pPalette;
-  uint8_t *pPicStream;
-  uint8_t *pPicDesc;
-} Bmp_t, *pBmp_t;
-
-/**
- * @brief A struct for Font Type on LCD screen
- */
- 
-typedef struct _FontType_t 
-{
-  uint32_t H_Size;
-  uint32_t V_Size;
-  uint32_t CharacterOffset;
-  uint32_t CharactersNuber;
-  uint8_t *pFontStream;
-  uint8_t *pFontDesc;
-} FontType_t, *pFontType_t;
-
-/**
- * @brief A struct for LCD Palette
- */
-
-typedef struct __LCD_PALETTE_Type
-{
-    uint8_t Red;
-    uint8_t Green;
-    uint8_t Blue;
-}LCD_PALETTE_Type, *pLCD_PALETTE_Type;
-
-/**
- * @brief A struct for Horizontal configuration
- */
-
-typedef struct __LCD_HConfig_Type
-{
-  uint8_t hfp;  // Horizontal front porch
-  uint8_t hbp;  // Horizontal back porch
-  uint8_t hsw;  // Horizontal synchronization pulse width
-  uint16_t ppl;  // Number of pixels per line
-}LCD_HConfig_Type;
-
-/**
- * @brief A struct for Vertical configuration
- */
-
-typedef struct __LCD_VConfig_Type
-{
-  uint8_t vfp;  // Vertical front and back porch
-  uint8_t vbp;  // Vertical back porch
-  uint8_t vsw;  // Vertical synchronization pulse width
-  uint16_t lpp; // Number of lines per panel
-}LCD_VConfig_Type;
-
-/**
- * @brief A struct for Polarity configuration
- */
-
-typedef struct __LCD_POLARITY_Type
-{
-    uint16_t cpl; // Number of pixel clocks per line 
-    uint8_t  active_high; // Signal polarity, active HIGH or LOW
-    uint8_t acb;  // AC bias pin frequency
-    uint8_t  invert_panel_clock;   // Invert Panel clock;
-    uint8_t  invert_hsync;          // Invert HSYNC
-    uint8_t  invert_vsync;          // Invert VSYSNC
-}LCD_POLARITY_Type;
-
-/**
- * @brief A struct for LCD Configuration
- */
-
-typedef struct __LCD_Config_Type
-{
-  LCD_HConfig_Type hConfig; // Horizontal config
-  LCD_VConfig_Type vConfig; // Vertical config
-  LCD_POLARITY_Type polarity; // Polarity config
-  uint32_t panel_clk; // Panel clock frequency
-  LCD_BPP lcd_bpp;   // Bits-per-pixel
-  LCD_TYPES lcd_type; // Display type: STN monochrome, STN color, or TFT
-  uint8_t   lcd_mono8; // STN 4 or 8-bit interface mode
-  uint8_t   lcd_dual;  // STN dual or single panel mode
-  uint8_t   big_endian_byte; // byte ordering in memory
-  uint8_t   big_endian_pixel; // pixel ordering within a byte
-  uint32_t  lcd_panel_upper;  // base address of frame buffer
-  uint32_t  lcd_panel_lower;  // base address of frame buffer
-  uint8_t*  lcd_palette;      // point to palette buffer
-  Bool      lcd_bgr;          // False: RGB , TRUE: BGR
-} LCD_Config_Type;
-
-/**
- * @brief A struct for Cursor configuration
- */
-
-typedef struct __LCD_Cursor_Config_Type
-{
-   uint8_t size32;              // 32x32 or 64x64
-   uint8_t framesync;
-   LCD_PALETTE_Type palette[2];
-   uint32_t   baseaddress;
-} LCD_Cursor_Config_Type;
-
-typedef uint32_t LcdPixel_t, *pLcdPixel_t;
-typedef int32_t  LCD_RET_CODE;
-
-/**
- * @}
- */
-
-
-/** @defgroup LCD_Public_Functions LCD Public Functions
- * @{
- */
-
-LCD_RET_CODE LCD_Init (LCD_Config_Type* pConfig);
-void LCD_SetBaseAddress(LCD_PANEL panel, uint32_t pAddress);
-void LCD_SetPalette (const uint8_t* pPallete);
-void LCD_Enable (Bool bEna);
-void LCD_Cursor_Cfg(LCD_Cursor_Config_Type* pConfig);
-void LCD_Cursor_Enable(int enable, int cursor);
-void LCD_Move_Cursor(int x, int y);
-void LCD_Cursor_SetImage (const uint32_t *pCursor, int cursor, int size);
-void LCD_SetImage(LCD_PANEL panel,const uint8_t *pPain);
-void LCD_FillRect (LCD_PANEL panel, uint32_t startx,uint32_t endx, 
-                                        uint32_t starty, uint32_t endy,
-                                        LcdPixel_t color);
-void LCD_PutPixel (LCD_PANEL panel, uint32_t X_Left, uint32_t Y_Up, LcdPixel_t color);
-void LCD_LoadPic (LCD_PANEL panel,uint32_t X_Left, uint32_t Y_Up, Bmp_t * pBmp, uint32_t Mask);
-
-/**
- * @}
- */
-
-#endif // __LPC_LCD_H_
-/**
- * @}
- */
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_libcfg_default.h

@@ -1,158 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_libcfg.h            2010-05-21
-***
-* @file     lpc_libcfg.h
-* @brief    Library configuration file
-* @version  3.0
-* @date     20. June. 2010
-* @author   NXP MCU SW Application Team
-*
-* Copyright(C) 2010, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-#ifndef _LPC_LIBCFG_DEFAULT_H_
-#define _LPC_LIBCFG_DEFAULT_H_
-
-#include "lpc_types.h"
-
-
-/************************** DEBUG MODE DEFINITIONS *********************************/
-/* Un-comment the line below to compile the library in DEBUG mode, this will expanse
-   the "CHECK_PARAM" macro in the FW library code */
-
-#ifndef __CODE_RED
-#define DEBUG
-#endif
-
-
-/******************* PERIPHERAL FW LIBRARY CONFIGURATION DEFINITIONS ***********************/
-
-/* Comment the line below to disable the specific peripheral inclusion */
-
-/* DEBUG_FRAMWORK -------------------- */
-#define _DBGFWK
-
-/* Clock & Power -------------------- */
-#define _CLKPWR
-
-/* CRC -------------------- */
-#define _CRC
-
-/* GPIO ------------------------------- */
-#define _GPIO
-
-/* NVIC ------------------------------- */
-#define _NVIC
-
-/* PINSEL ------------------------------- */
-#define _PINSEL
-
-/* EXTI ------------------------------- */
-#define _EXTI
-
-/* EMC ------------------------------- */
-#define _EMC
-
-/* UART ------------------------------- */
-#define _UART
-
-/* SPI ------------------------------- */
-#define _SPI
-
-/* SYSTICK --------------------------- */
-#define _SYSTICK
-
-/* SSP ------------------------------- */
-#define _SSP
-
-
-/* I2C ------------------------------- */
-#define _I2C
-
-/* TIMER ------------------------------- */
-#define _TIM
-
-/* WDT ------------------------------- */
-#define _WDT
-
-
-/* GPDMA ------------------------------- */
-#define _GPDMA
-
-
-/* DAC ------------------------------- */
-#define _DAC
-
-/* ADC ------------------------------- */
-#define _ADC
-
-/* EEPROM ------------------------------- */
-#define _EEPROM
-
-/* PWM ------------------------------- */
-#define _PWM
-
-/* RTC ------------------------------- */
-#define _RTC
-
-/* I2S ------------------------------- */
-#define _I2S
-
-/* USB device ------------------------------- */
-#define _USBDEV
-#ifdef _USBDEV
-#define _USB_DEV_AUDIO
-#define _USB_DEV_MASS_STORAGE
-#define _USB_DEV_HID
-#define _USB_DEV_VIRTUAL_COM
-#endif /*_USBDEV*/
-
-/* USB Host ------------------------------- */
-#define _USBHost
-
-/* QEI ------------------------------- */
-#define _QEI
-
-/* MCPWM ------------------------------- */
-#define _MCPWM
-
-/* CAN--------------------------------*/
-#define _CAN
-
-/* EMAC ------------------------------ */
-#define _EMAC
-
-/* LCD ------------------------------ */
-#define _LCD
-
-/* MCI ------------------------------ */
-#define _MCI
-
-/* IAP------------------------------ */
-#define _IAP
-
-/* BOD------------------------------ */
-#define _BOD
-/************************** GLOBAL/PUBLIC MACRO DEFINITIONS *********************************/
-
-
-#endif /* _LPC_LIBCFG_DEFAULT_H_ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_mci.h

@@ -1,463 +0,0 @@
-/**********************************************************************
-* $Id$         lpc_mci.h            2011-06-02
-*//**
-* @file        lpc_mci.h
-* @brief       Contains all macro definitions and function prototypes
-*              support for MCI firmware library on LPC
-* @version     2.0
-* @date        29. June. 2011
-* @author      NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup MCI    MCI (Multimedia Card Interface)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_MCI_H_
-#define __LPC_MCI_H_
-
-/** @defgroup MCI_Public_Macros MCI Public Macros
- * @{
- */
-
-#define MCI_DMA_ENABLED          (1)
-
-#define HIGH_LVL                 (1)
-#define LOW_LVL                  (0)
-
-/* SD/MMC Command list, per MMC spec. SD Memory Card Spec. Simplified version */
-/* GO_IDLE_STATE(MMC) or RESET(SD) */
-#define CMD0_GO_IDLE_STATE       (0)
-/* SEND_OP_COND(MMC) or ACMD41(SD) */
-#define CMD1_SEND_OP_COND        (1)
-/* ALL_SEND_CID */
-#define CMD2_ALL_SEND_CID        (2)
-/* SET_RELATE_ADDR */
-#define CMD3_SET_RELATIVE_ADDR   (3)
-/* Set Bus-Width 1 bit or 4 bits */
-#define ACMD6_SET_BUS_WIDTH      (6)
-/* SELECT/DESELECT_CARD */
-#define CMD7_SELECT_CARD         (7)
-/**Sending interface condition cmd */
-#define CMD8_SEND_IF_COND        (8)
-/* SEND_CSD */
-#define CMD9_SEND_CSD            (9)
-/* Stop either READ or WRITE operation */
-#define CMD12_STOP_TRANSMISSION  12
-/* SEND_STATUS */
-#define CMD13_SEND_STATUS        (13)
-/* SET_BLOCK_LEN */
-#define CMD16_SET_BLOCK_LEN      (16)
-/* READ_SINGLE_BLOCK */
-#define CMD17_READ_SINGLE_BLOCK  (17)
-/* READ_MULTIPLE_BLOCK */
-#define CMD18_READ_MULTIPLE_BLOCK    (18)
-/* WRITE_BLOCK */
-#define CMD24_WRITE_BLOCK            (24)
-/* WRITE_MULTIPLE_BLOCK */
-#define CMD25_WRITE_MULTIPLE_BLOCK   (25)
-/* Start erase block number*/
-#define CMD32_ERASE_WR_BLK_START     (32)
-/* End erase block number*/
-#define CMD33_ERASE_WR_BLK_END       (33)
-/* Start erase*/
-#define CMD38_ERASE                  (38)
-
-/* ACMD41 for SD card */
-#define ACMD41_SEND_APP_OP_COND      (41)
-
-/* APP_CMD, the following will a ACMD */
-#define CMD55_APP_CMD                (55)
-
-#define OCR_INDEX                    (0x00FF8000)
-#define RCA_ARGUMENT_POS             (16)
-#define RCA_ARGUMENT_MASK            (0xFFFF)
-
-
-/* Card Status (coded in 32 bits) in R1 & R1b Response */
-#define CARD_STATUS_OUT_OF_RANGE    ( 1 << 31)
-#define CARD_STATUS_ADDRESS_ERROR   ( 1 << 30)
-#define CARD_STATUS_BLOCK_LEN_ERROR ( 1 << 29)
-#define CARD_STATUS_ERASE_SEQ_ERROR ( 1 << 28)
-#define CARD_STATUS_ERASE_PARAM_ERROR ( 1 << 27)
-#define CARD_STATUS_WP_VIOLATION    ( 1 << 26)
-#define CARD_STATUS_CARD_IS_LOCKED  ( 1 << 25)
-#define CARD_STATUS_COM_CRC_ERROR   ( 1 << 23)
-#define CARD_STATUS_ILLEGAL_COMMAND ( 1 << 22)
-#define CARD_STATUS_CARD_ECC_FAILED ( 1 << 21)
-#define CARD_STATUS_CC_ERROR        ( 1 << 20)
-#define CARD_STATUS_GEN_ERROR       ( 1 << 19)
-#define CARD_STATUS_CSD_OVERWRITE   ( 1 << 16)
-#define CARD_STATUS_WP_ERASE_SKIP   ( 1 << 15)
-#define CARD_STATUS_CARD_ECC_DISABLED   ( 1 << 14)
-#define CARD_STATUS_ERASE_RESET     ( 1 << 13)
-#define CARD_STATUS_READY_FOR_DATA  ( 1 << 8)
-#define CARD_STATUS_ACMD_ENABLE     ( 1 << 5)
-#define CARD_STATUS_ERR_MASK         (0xFDF88008)
-#define CARDSTATEOF(x)              ((x>>9) & 0x0F)
-#define CARD_STATE_IDLE             (0)
-#define CARD_STATE_READY            (1)
-#define CARD_STATE_IDENT            (2)
-#define CARD_STATE_STBY             (3)
-#define CARD_STATE_TRAN             (4)
-#define CARD_STATE_DATA             (5)
-#define CARD_STATE_RCV              (6)
-#define CARD_STATE_PRG              (7)
-#define CARD_STATE_DIS              (8)
-
-
-/* CID  in R2 reponse (Code length is 136 bits) */
-#define MCI_CID_MANUFACTURER_ID_WPOS           (24)    //pos in word 0
-#define MCI_CID_MANUFACTURER_ID_WBMASK         (0xFF)
-
-#define MCI_CID_OEMAPPLICATION_ID_WPOS         (8)        //pos in word 0
-#define MCI_CID_OEMAPPLICATION_ID_WBMASK       (0xFFFF)
-
-#define MCI_CID_PRODUCTNAME_ID_H_WPOS          (0)        //pos in word 0
-#define MCI_CID_PRODUCTNAME_ID_H_WBMASK        (0xFF)
-
-#define MCI_CID_PRODUCTNAME_ID_L_WPOS          (0)        //pos in word 1
-#define MCI_CID_PRODUCTNAME_ID_L_WBMASK        (0xFFFFFFFF)
-
-#define MCI_CID_PRODUCTREVISION_ID_WPOS        (24)    //pos in word 2
-#define MCI_CID_PRODUCTREVISION_ID_WBMASK      (0xFF)
-
-#define MCI_CID_PRODUCTSERIALNUM_ID_H_WPOS     (0)    //pos in word 2
-#define MCI_CID_PRODUCTSERIALNUM_ID_H_WBMASK   (0x00FFFFFF)
-#define MCI_CID_PRODUCTSERIALNUM_ID_L_WPOS     (24)    //pos in word 3
-#define MCI_CID_PRODUCTSERIALNUM_ID_L_WBMASK   (0xFF)
-#define MCI_CID_PRODUCTSERIALNUM_ID_WBMASK     (0xFFFFFFFF)
-
-#define MCI_CID_RESERVED_ID_WPOS               (20)    //pos in word 3
-#define MCI_CID_RESERVED_ID_WBMASK             (0x1F)
-
-#define MCI_CID_MANUFACTURINGDATE_ID_WPOS      (8)    //in word 3
-#define MCI_CID_MANUFACTURINGDATE_ID_WBMASK    (0x0FFF)
-
-#define MCI_CID_CHECKSUM_ID_WPOS               (1)    //in word 3
-#define MCI_CID_CHECKSUM_ID_WBMASK             (0x7F)
-
-#define MCI_CID_UNUSED_ID_WPOS                 (0)    //in word 3
-#define MCI_CID_UNUSED_ID_WBMASK               (0x01)
-
-/* R6 (Published RCA response) */
-#define RCA_RES_CARD_STATUS_POS                (0)
-#define RCA_RES_CARD_STATUS_MASK               (0xFFFF)
-
-#define RCA_RES_NEW_PUBLISHED_RCA_POS           (16)
-#define RCA_RES_NEW_PUBLISHED_RCA_MASK          (0xFFFF)
-
-/* R7 (Card interface condition) */
-#define MCI_CMD8_VOLTAGESUPPLIED_POS           (8)
-#define MCI_CMD8_VOLTAGESUPPLIED_BMASK         (0x0F)
-#define MCI_CMD8_VOLATAGESUPPLIED_NOT_DEFINED  (0)
-#define MCI_CMD8_VOLATAGESUPPLIED_27_36        (1)  /*2.7 - 3.6V*/
-
-#define MCI_CMD8_CHECKPATTERN_POS              (0)
-#define MCI_CMD8_CHECKPATTERN_BMASK            (0xFF)
-
-
-#define MCI_SLOW_RATE                (400000)    /* 400KHz */
-#define MCI_NORMAL_RATE              (20000000)  /* 20MHz */
-
-#define SD_1_BIT                     (0)
-#define SD_4_BIT                     (1)
-
-#define DATA_TIMER_VALUE_R           (MCI_NORMAL_RATE/4)    // 250ms
-#define DATA_TIMER_VALUE_W           (MCI_NORMAL_RATE)    // 1000ms
-
-#define DATA_RW_MAX_LEN              (0xFFFF)
-
-#define EXPECT_NO_RESP               (0)
-#define EXPECT_SHORT_RESP            (1)
-#define EXPECT_LONG_RESP             (2)
-
-#define MCI_OUTPUT_MODE_PUSHPULL     (0)
-#define MCI_OUTPUT_MODE_OPENDRAIN    (1)
-
-#define NOT_ALLOW_CMD_TIMER          (0)
-#define ALLOW_CMD_TIMER              (1)
-
-#define MCI_DISABLE_CMD_TIMER        (1<<8)
-
-/* For the SD card I tested, the minimum block length is 512 */
-/* For MMC, the restriction is loose, due to the variety of SD and MMC
-card support, ideally, the driver should read CSD register to find the
-speed and block length for the card, and set them accordingly. */
-/* In this driver example, it will support both MMC and SD cards, it
-does read the information by send SEND_CSD to poll the card status,
-but, it doesn't configure them accordingly. this is not intended to
-support all the SD and MMC card. */
-
-/* DATA_BLOCK_LEN table
-    DATA_BLOCK_LEN           Actual Size( BLOCK_LENGTH )
-    11                       2048
-    10                       1024
-    9                        512
-    8                        256
-    7                        128
-    6                        64
-    5                        32
-    4                        16
-    3                        8
-    2                        4
-    1                        2
-*/
-/* This is the size of the buffer of origin data */
-#define MCI_DMA_SIZE            (1000UL)
-/* This is the area original data is stored or data to be written to the SD/MMC card. */
-#define MCI_DMA_SRC_ADDR        LPC_PERI_RAM_BASE
-/* This is the area, after reading from the SD/MMC*/
-#define MCI_DMA_DST_ADDR        (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE)
-
-
-/* To simplify the programming, please note that, BLOCK_LENGTH is a multiple
-of FIFO_SIZE */
-#define DATA_BLOCK_LEN       (9)    /* Block size field in DATA_CTRL */
-#define BLOCK_LENGTH         (1 << DATA_BLOCK_LEN)
-                                /* for SD card, 128, the size of the flash */
-                                /* card is 512 * 128 = 64K */
-#define BLOCK_NUM            0x80
-#define FIFO_SIZE            16
-
-#define BUS_WIDTH_1BIT       0
-#define BUS_WIDTH_4BITS      10
-
-/* MCI Status register bit information */
-#define MCI_CMD_CRC_FAIL     (1 << 0)
-#define MCI_DATA_CRC_FAIL    (1 << 1)
-#define MCI_CMD_TIMEOUT      (1 << 2)
-#define MCI_DATA_TIMEOUT     (1 << 3)
-#define MCI_TX_UNDERRUN      (1 << 4)
-#define MCI_RX_OVERRUN       (1 << 5)
-#define MCI_CMD_RESP_END     (1 << 6)
-#define MCI_CMD_SENT         (1 << 7)
-#define MCI_DATA_END         (1 << 8)
-#define MCI_START_BIT_ERR    (1 << 9)
-#define MCI_DATA_BLK_END     (1 << 10)
-#define MCI_CMD_ACTIVE       (1 << 11)
-#define MCI_TX_ACTIVE        (1 << 12)
-#define MCI_RX_ACTIVE        (1 << 13)
-#define MCI_TX_HALF_EMPTY    (1 << 14)
-#define MCI_RX_HALF_FULL     (1 << 15)
-#define MCI_TX_FIFO_FULL     (1 << 16)
-#define MCI_RX_FIFO_FULL     (1 << 17)
-#define MCI_TX_FIFO_EMPTY    (1 << 18)
-#define MCI_RX_FIFO_EMPTY    (1 << 19)
-#define MCI_TX_DATA_AVAIL    (1 << 20)
-#define MCI_RX_DATA_AVAIL    (1 << 21)
-
-
-/***********************************************************************
- * MCI Data control register definitions
- **********************************************************************/
-/** Data transfer enable */
-#define MCI_DATACTRL_ENABLE_POS         (0)
-#define MCI_DATACTRL_ENABLE_MASK        (0x01)
-#define MCI_DATACTRL_ENABLE             (1 << MCI_DATACTRL_ENABLE_POS)
-#define MCI_DATACTRL_DISABLE            (0 << MCI_DATACTRL_ENABLE_POS)
-
-/** Data transfer direction */
-#define MCI_DATACTRL_DIR_POS            (1)
-#define MCI_DATACTRL_DIR_MASK           (0x01)
-#define MCI_DATACTRL_DIR_FROM_CARD      (1 << MCI_DATACTRL_DIR_POS)
-#define MCI_DATACTRL_DIR_TO_CARD        (0 << MCI_DATACTRL_DIR_POS)
-
-
-/** Data transfer mode */
-#define MCI_DATACTRL_XFER_MODE_POS      (2)
-#define MCI_DATACTRL_XFER_MODE_MASK     (0x01)
-#define MCI_DATACTRL_XFER_MODE_STREAM   (1 << MCI_DATACTRL_XFER_MODE_POS)
-#define MCI_DATACTRL_XFER_MODE_BLOCK    (0 << MCI_DATACTRL_XFER_MODE_POS)
-
-/** Enable DMA */
-#define MCI_DATACTRL_DMA_ENABLE_POS     (3)
-#define MCI_DATACTRL_DMA_ENABLE_MASK    (0x01)
-#define MCI_DATACTRL_DMA_ENABLE         (1 << MCI_DATACTRL_DMA_ENABLE_POS)
-#define MCI_DATACTRL_DMA_DISABLE        (0 << MCI_DATACTRL_DMA_ENABLE_POS)
-
-/** Data block length macro */
-#define MCI_DTATCTRL_BLOCKSIZE(n)    _SBF(4, (n & 0xF))
-
-
-#define CMD_INT_MASK      (MCI_CMD_CRC_FAIL | MCI_CMD_TIMEOUT | MCI_CMD_RESP_END \
-                         | MCI_CMD_SENT     | MCI_CMD_ACTIVE)
-
-#define DATA_ERR_INT_MASK    (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN \
-                           | MCI_RX_OVERRUN | MCI_START_BIT_ERR)
-
-#define ACTIVE_INT_MASK ( MCI_TX_ACTIVE | MCI_RX_ACTIVE)
-
-#define FIFO_INT_MASK        (MCI_TX_HALF_EMPTY | MCI_RX_HALF_FULL \
-                           | MCI_TX_FIFO_FULL  | MCI_RX_FIFO_FULL \
-                           | MCI_TX_FIFO_EMPTY | MCI_RX_FIFO_EMPTY \
-                           | MCI_DATA_BLK_END )
-
-#define    FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY )
-#define    FIFO_RX_INT_MASK (MCI_RX_HALF_FULL  )
-
-#define DATA_END_INT_MASK    (MCI_DATA_END | MCI_DATA_BLK_END)
-
-#define ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR)
-#define ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN  | MCI_START_BIT_ERR)
-
-/* Error code on the command response. */
-#define INVALID_RESPONSE    0xFFFFFFFF
-
-/**
- * @}
- */
- 
-
-/** @defgroup MCI_Public_Types MCI Public Types
- * @{
- */
-
-typedef enum mci_card_state
-{
-    MCI_CARDSTATE_IDLE = 0,
-    MCI_CARDSTATE_READY,
-    MCI_CARDSTATE_IDENDTIFIED,
-    MCI_CARDSTATE_STBY,
-    MCI_CARDSTATE_TRAN,
-    MCI_CARDSTATE_DATA,
-    MCI_CARDSTATE_RCV,
-    MCI_CARDSTATE_PRG,
-    MCI_CARDSTATE_DIS,
-}en_Mci_CardState;
-
-
-typedef enum mci_func_error
-{
-    MCI_FUNC_OK = 0,
-    MCI_FUNC_FAILED = -1,
-    MCI_FUNC_BAD_PARAMETERS = -2,
-    MCI_FUNC_BUS_NOT_IDLE = -3,
-    MCI_FUNC_TIMEOUT = -3,
-    MCI_FUNC_ERR_STATE = -4,
-    MCI_FUNC_NOT_READY = -5,
-}en_Mci_Func_Error;
-
-typedef enum mci_card_type
-{
-    MCI_SDHC_SDXC_CARD = 3,
-    MCI_SDSC_V2_CARD = 2,
-    MCI_MMC_CARD = 1,
-    MCI_SDSC_V1_CARD = 0,
-    MCI_CARD_UNKNOWN = -1,
-}en_Mci_CardType;
-
-typedef struct mci_cid
-{
-    /** Manufacturer ID */
-    uint8_t MID;
-    /** OEM/Application ID */
-    uint16_t OID;
-    /** Product name 8-bits higher */
-    uint8_t PNM_H;
-    /** Product name 32-bits Lower */
-    uint32_t PNM_L;
-    /** Product revision */
-    uint8_t PRV;
-    /** Product serial number */
-    uint32_t PSN;
-    /** reserved: 4 bit */
-    uint8_t reserved;
-    /** Manufacturing date: 12 bit */
-    uint16_t MDT;
-    /** CRC7 checksum: 7 bit */
-    uint8_t CRC;
-    /** not used, always: 1 bit always 1 */
-    uint8_t unused;
-} st_Mci_CardId;
-
-typedef struct cmd_info{
-    /** Command ID*/
-    uint32_t CmdIndex;
-    /** Command Argument*/
-    uint32_t Argument;
-    /** Expected response: no response, short response or long response */
-    uint32_t ExpectResp;
-    /** Allow timeout */
-    uint32_t AllowTimeout;
-    /** Command Response Info */
-    uint32_t *CmdResp;
-} st_Mci_CmdInfo;
-/**
- * @}
- */
-
-
-/** @defgroup MCI_Public_Functions MCI Public Functions
- * @{
- */
-
-int32_t MCI_Init(uint8_t powerActiveLevel );
-void  MCI_SendCmd( st_Mci_CmdInfo* pCmdIf );
-int32_t MCI_GetCmdResp( uint32_t CmdIndex, uint32_t NeedRespFlag, uint32_t *CmdRespStatus );
-int32_t MCI_CmdResp(st_Mci_CmdInfo *pCmdIf);
-
-void  MCI_Set_MCIClock( uint32_t clockrate );
-int32_t MCI_SetBusWidth( uint32_t width );
-int32_t MCI_Acmd_SendOpCond(uint8_t hcsVal);
-int32_t MCI_CardInit( void );
-en_Mci_CardType MCI_GetCardType(void);
-int32_t MCI_CardReset( void );
-int32_t MCI_Cmd_SendIfCond(void);
-int32_t MCI_GetCID(st_Mci_CardId* cidValue);
-int32_t MCI_SetCardAddress( void );
-uint32_t MCI_GetCardAddress(void);
-int32_t MCI_GetCSD(uint32_t* csdVal);
-int32_t MCI_Cmd_SelectCard( void );
-int32_t MCI_GetCardStatus(int32_t* cardStatus);
-uint32_t MCI_GetDataXferEndState(void);
-uint32_t MCI_GetXferErrState(void);
-int32_t MCI_SetBlockLen( uint32_t blockLength );
-int32_t MCI_Acmd_SendBusWidth( uint32_t buswidth );
-int32_t MCI_Cmd_StopTransmission( void );
-
-int32_t MCI_Cmd_WriteBlock(uint32_t blockNum, uint32_t numOfBlock);
-int32_t MCI_Cmd_ReadBlock(uint32_t blockNum, uint32_t numOfBlock);
-
-int32_t MCI_WriteBlock(volatile uint8_t* memblock, uint32_t blockNum, uint32_t numOfBlock);
-int32_t MCI_ReadBlock(volatile uint8_t* destBlock, uint32_t blockNum, uint32_t numOfBlock);
-#if MCI_DMA_ENABLED
-void     MCI_DMA_IRQHandler (void);
-#endif
-
-/**
- * @}
- */
-
-#endif /* end __LPC_MCI_H_ */
-
-/**
- * @}
- */
-
-/****************************************************************************
-**                            End Of File
-****************************************************************************/

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_mcpwm.h

@@ -1,348 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_mcpwm.h         2011-06-02
-*//**
-* @file     lpc_mcpwm.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for Motor Control PWM firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup MCPWM MCPWM (Motor Control PWM)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_MCPWM_H_
-#define __LPC_MCPWM_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup MCPWM_Public_Macros MCPWM Public Macros
- * @{
- */
-
-/** Edge aligned mode for channel in MCPWM */
-#define MCPWM_CHANNEL_EDGE_MODE         ((uint32_t)(0))
-
-/** Center aligned mode for channel in MCPWM */
-#define MCPWM_CHANNEL_CENTER_MODE       ((uint32_t)(1))
-
-/** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
-#define MCPWM_CHANNEL_PASSIVE_LO        ((uint32_t)(0))
-/** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
-#define MCPWM_CHANNEL_PASSIVE_HI        ((uint32_t)(1))
-
-/* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
- * the six output pins under the control of the bits in this register */
-#define MCPWM_PATENT_A0     ((uint32_t)(1<<0))  /**< MCOA0 tracks internal MCOA0 */
-#define MCPWM_PATENT_B0     ((uint32_t)(1<<1))  /**< MCOB0 tracks internal MCOA0 */
-#define MCPWM_PATENT_A1     ((uint32_t)(1<<2))  /**< MCOA1 tracks internal MCOA0 */
-#define MCPWM_PATENT_B1     ((uint32_t)(1<<3))  /**< MCOB1 tracks internal MCOA0 */
-#define MCPWM_PATENT_A2     ((uint32_t)(1<<4))  /**< MCOA2 tracks internal MCOA0 */
-#define MCPWM_PATENT_B2     ((uint32_t)(1<<5))  /**< MCOB2 tracks internal MCOA0 */
-
-/* Interrupt type in MCPWM */
-/** Limit interrupt for channel (0) */
-#define MCPWM_INTFLAG_LIM0  MCPWM_INT_ILIM(0)
-/** Match interrupt for channel (0) */
-#define MCPWM_INTFLAG_MAT0  MCPWM_INT_IMAT(0)
-/** Capture interrupt for channel (0) */
-#define MCPWM_INTFLAG_CAP0  MCPWM_INT_ICAP(0)
-
-/** Limit interrupt for channel (1) */
-#define MCPWM_INTFLAG_LIM1  MCPWM_INT_ILIM(1)
-/** Match interrupt for channel (1) */
-#define MCPWM_INTFLAG_MAT1  MCPWM_INT_IMAT(1)
-/** Capture interrupt for channel (1) */
-#define MCPWM_INTFLAG_CAP1  MCPWM_INT_ICAP(1)
-
-/** Limit interrupt for channel (2) */
-#define MCPWM_INTFLAG_LIM2  MCPWM_INT_ILIM(2)
-/** Match interrupt for channel (2) */
-#define MCPWM_INTFLAG_MAT2  MCPWM_INT_IMAT(2)
-/** Capture interrupt for channel (2) */
-#define MCPWM_INTFLAG_CAP2  MCPWM_INT_ICAP(2)
-
-/** Fast abort interrupt */
-#define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
-
-/**
- * @}
- */
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup MCPWM_Private_Macros MCPWM Private Macros
- * @{
- */
-
-/*********************************************************************//**
- * Macro defines for MCPWM Control register
- **********************************************************************/
-/* MCPWM Control register, these macro definitions below can be applied for these
- * register type:
- * - MCPWM Control read address
- * - MCPWM Control set address
- * - MCPWM Control clear address
- */
-/** Stops/starts timer channel n */
-#define MCPWM_CON_RUN(n)        ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+0))) : (0))
-/** Edge/center aligned operation for channel n */
-#define MCPWM_CON_CENTER(n)     ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+1))) : (0))
-/** Select polarity of the MCOAn and MCOBn pin */
-#define MCPWM_CON_POLAR(n)      ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+2))) : (0))
-/** Control the dead-time feature for channel n */
-#define MCPWM_CON_DTE(n)        ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+3))) : (0))
-/** Enable/Disable update of functional register for channel n */
-#define MCPWM_CON_DISUP(n)      ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*8)+4))) : (0))
-
-/** Control the polarity for all 3 channels */
-#define MCPWM_CON_INVBDC        ((uint32_t)((uint32_t)1<<29))
-/** 3-phase AC mode select */
-#define MCPWM_CON_ACMODE        ((uint32_t)((uint32_t)1<<30))
-/** 3-phase DC mode select */
-#define MCPWM_CON_DCMODE        ((uint32_t)((uint32_t)1<<31))
-
-/*********************************************************************//**
- * Macro defines for MCPWM Capture Control register
- **********************************************************************/
-/* Capture Control register, these macro definitions below can be applied for these
- * register type:
- * - MCPWM Capture Control read address
- * - MCPWM Capture Control set address
- * - MCPWM Capture control clear address
- */
-/** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
-#define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
-/** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
-#define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
-/** TC(n) is reset by channel (n) capture event */
-#define MCPWM_CAPCON_RT(n)              ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(18+(n)))) : (0))
-/** Hardware noise filter: channel (n) capture events are delayed */
-#define MCPWM_CAPCON_HNFCAP(n)          ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(21+(n)))) : (0))
-
-/*********************************************************************//**
- * Macro defines for MCPWM Interrupt register
- **********************************************************************/
-/* Interrupt registers, these macro definitions below can be applied for these
- * register type:
- * - MCPWM Interrupt Enable read address
- * - MCPWM Interrupt Enable set address
- * - MCPWM Interrupt Enable clear address
- * - MCPWM Interrupt Flags read address
- * - MCPWM Interrupt Flags set address
- * - MCPWM Interrupt Flags clear address
- */
-/** Limit interrupt for channel (n) */
-#define MCPWM_INT_ILIM(n)   ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+0))) : (0))
-/** Match interrupt for channel (n) */
-#define MCPWM_INT_IMAT(n)   ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+1))) : (0))
-/** Capture interrupt for channel (n) */
-#define MCPWM_INT_ICAP(n)   ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<((n*4)+2))) : (0))
-
-/** Fast abort interrupt */
-#define MCPWM_INT_ABORT     ((uint32_t)(1<<15))
-
-/*********************************************************************//**
- * Macro defines for MCPWM Count Control register
- **********************************************************************/
-/* MCPWM Count Control register, these macro definitions below can be applied for these
- * register type:
- * - MCPWM Count Control read address
- * - MCPWM Count Control set address
- * - MCPWM Count Control clear address
- */
-/** Counter(tc) advances on a rising edge on MCI(mci) pin */
-#define MCPWM_CNTCON_TCMCI_RE(tc,mci)   (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
-/** Counter(cnt) advances on a falling edge on MCI(mci) pin */
-#define MCPWM_CNTCON_TCMCI_FE(tc,mci)   (((tc < MCPWM_MAX_CHANNEL)&&(mci < MCPWM_MAX_CHANNEL)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
-/** Channel (n) is in counter mode */
-#define MCPWM_CNTCON_CNTR(n)            ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<(29+n))) : (0))
-
-/*********************************************************************//**
- * Macro defines for MCPWM Dead-time register
- **********************************************************************/
-/** Dead time value x for channel n */
-#define MCPWM_DT(n,x)       ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
-
-/*********************************************************************//**
- * Macro defines for MCPWM Communication Pattern register
- **********************************************************************/
-#define MCPWM_CP_A0     ((uint32_t)(1<<0))  /**< MCOA0 tracks internal MCOA0 */
-#define MCPWM_CP_B0     ((uint32_t)(1<<1))  /**< MCOB0 tracks internal MCOA0 */
-#define MCPWM_CP_A1     ((uint32_t)(1<<2))  /**< MCOA1 tracks internal MCOA0 */
-#define MCPWM_CP_B1     ((uint32_t)(1<<3))  /**< MCOB1 tracks internal MCOA0 */
-#define MCPWM_CP_A2     ((uint32_t)(1<<4))  /**< MCOA2 tracks internal MCOA0 */
-#define MCPWM_CP_B2     ((uint32_t)(1<<5))  /**< MCOB2 tracks internal MCOA0 */
-
-/*********************************************************************//**
- * Macro defines for MCPWM Capture clear address register
- **********************************************************************/
-/** Clear the MCCAP (n) register */
-#define MCPWM_CAPCLR_CAP(n)     ((n < MCPWM_MAX_CHANNEL) ? ((uint32_t)(1<<n)) : (0))
-
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup MCPWM_Public_Types MCPWM Public Types
- * @{
- */
-
-typedef enum
-{
-    MCPWM_CHANNEL_0 = 0,
-    MCPWM_CHANNEL_1,
-    MCPWM_CHANNEL_2,
-    MCPWM_MAX_CHANNEL,
-} en_MCPWM_Channel_Id;
-
-
-/**
- * @brief Motor Control PWM Channel Configuration structure type definition
- */
-typedef struct {
-    uint32_t channelType;                   /**< Edge/center aligned mode for this channel,
-                                                should be:
-                                                - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
-                                                - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
-                                                */
-    uint32_t channelPolarity;               /**< Polarity of the MCOA and MCOB pins, should be:
-                                                - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
-                                                - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
-                                                */
-    uint32_t channelDeadtimeEnable;         /**< Enable/Disable DeadTime function for channel, should be:
-                                                - ENABLE.
-                                                - DISABLE.
-                                                */
-    uint32_t channelDeadtimeValue;          /**< DeadTime value, should be less than 0x3FF */
-    uint32_t channelUpdateEnable;           /**< Enable/Disable updates of functional registers,
-                                                 should be:
-                                                - ENABLE.
-                                                - DISABLE.
-                                                */
-    uint32_t channelTimercounterValue;      /**< MCPWM Timer Counter value */
-    uint32_t channelPeriodValue;            /**< MCPWM Period value */
-    uint32_t channelPulsewidthValue;        /**< MCPWM Pulse Width value */
-} MCPWM_CHANNEL_CFG_Type;
-
-/**
- * @brief MCPWM Capture Configuration type definition
- */
-typedef struct {
-    uint32_t captureChannel;        /**< Capture Channel Number, should be in range from 0 to 2 */
-    uint32_t captureRising;         /**< Enable/Disable Capture on Rising Edge event, should be:
-                                        - ENABLE.
-                                        - DISABLE.
-                                        */
-    uint32_t captureFalling;        /**< Enable/Disable Capture on Falling Edge event, should be:
-                                        - ENABLE.
-                                        - DISABLE.
-                                        */
-    uint32_t timerReset;            /**< Enable/Disable Timer reset function an capture, should be:
-                                        - ENABLE.
-                                        - DISABLE.
-                                        */
-    uint32_t hnfEnable;             /**< Enable/Disable Hardware noise filter function, should be:
-                                        - ENABLE.
-                                        - DISABLE.
-                                        */
-} MCPWM_CAPTURE_CFG_Type;
-
-
-/**
- * @brief MCPWM Count Control Configuration type definition
- */
-typedef struct {
-    uint32_t counterChannel;        /**< Counter Channel Number, should be in range from 0 to 2 */
-    uint32_t countRising;           /**< Enable/Disable Capture on Rising Edge event, should be:
-                                        - ENABLE.
-                                        - DISABLE.
-                                        */
-    uint32_t countFalling;      /**< Enable/Disable Capture on Falling Edge event, should be:
-                                        - ENABLE.
-                                        - DISABLE.
-                                        */
-} MCPWM_COUNT_CFG_Type;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup MCPWM_Public_Functions MCPWM Public Functions
- * @{
- */
-
-void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
-void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
-                        MCPWM_CHANNEL_CFG_Type * channelSetup);
-void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
-                        MCPWM_CHANNEL_CFG_Type *channelSetup);
-void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
-                        MCPWM_CAPTURE_CFG_Type *captureConfig);
-void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
-uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
-void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
-                    uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
-void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
-void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
-void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
-void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
-                    uint32_t outputInvered, uint32_t outputPattern);
-void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
-void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
-void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
-FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_MCPWM_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_nvic.h

@@ -1,77 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_nvic.h          2011-06-02
-*//**
-* @file     lpc_nvic.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for Nesting Vectored Interrupt firmware library
-*           on LPC. The main NVIC functions are defined in
-*           core_cm3.h
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup NVIC NVIC (Nested Vectored Interrupt Controller)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_NVIC_H_
-#define __LPC_NVIC_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup NVIC_Public_Functions NVIC Public Functions
- * @{
- */
-
-void NVIC_DeInit(void);
-void NVIC_SCBDeInit(void);
-void NVIC_SetVTOR(uint32_t offset);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_NVIC_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_pinsel.h

@@ -1,199 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_pinsel.h            2011-06-02
-*//**
-* @file     lpc_pinsel.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for Pin-connection block firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup PINSEL    PINSEL (Pin Selection)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_PINSEL_H
-#define __LPC_PINSEL_H
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup PINSEL_Public_Macros PINSEL Public Macros
- * @{
- */
-
-/* Macros define IOCON bits*/
-
-/** Selects pin functions */
-#define IOCON_FUNC_POS              (0)
-#define IOCON_FUNC_MASK             (0x07<<IOCON_FUNC_POS)
-
-/** Selects output function mode (on-chip pull-up/pull-down resistor control */
-#define IOCON_MODE_POS              (3)
-#define IOCON_MODE_MASK             (0x03<<IOCON_MODE_POS)
-#define IOCON_MODE_PLAIN                ((0<<IOCON_MODE_POS))
-#define IOCON_MODE_PULLDOWN     ((1<<IOCON_MODE_POS))
-#define IOCON_MODE_PULLUP           ((2<<IOCON_MODE_POS))
-#define IOCON_MODE_REPEATER         ((3<<IOCON_MODE_POS))
-
-/** Hysteresis */
-#define IOCON_HYS_POS               (5)
-#define IOCON_HYS_MASK              (0x01<<IOCON_HYS_POS)
-#define IOCON_HYS_ENABLE                ((1<<IOCON_HYS_POS))
-
-/** Input polarity */
-#define IOCON_INVERT_POS                (6)
-#define IOCON_INVERT_MASK           (0x01<<IOCON_INVERT_POS)
-#define IOCON_INVERT_INPUT          (1<<IOCON_INVERT_POS)
-
-/** Selects Analog/Digital mode */
-#define IOCON_ADMODE_POS            (7)
-#define IOCON_ADMODE_MASK           (0x01<<IOCON_ADMODE_POS)
-#define IOCON_ANALOG_MODE           (0<<IOCON_ADMODE_POS)
-#define IOCON_DIGITIAL_MODE         (1<<IOCON_ADMODE_POS)
-
-/* Controls Glitch Filter */
-#define IOCON_FILTER_POS                (8)
-#define IOCON_FILTER_MASK               (0x01<<IOCON_FILTER_POS)
-#define IOCON_10ns_FILTER_ENABLE            (0<<IOCON_FILTER_POS)
-#define IOCON_10ns_FILTER_DISABLE           (1<<IOCON_FILTER_POS)
-
-/** I2C 50ns glitch filter and slew rate control */ 
-#define IOCON_HS_POS                    (8)
-#define IOCON_HS_MASK               (0x01<<IOCON_HS_POS)
-#define IOCON_I2C_FILTER_ENABLE     (0<<IOCON_HS_POS)
-#define IOCON_I2C_FILTER_DISABLE        (1<<IOCON_HS_POS)
-
-/** Driver Output Slew Rate Control*/
-#define IOCON_SLEW_POS              (9)
-#define IOCON_SLEW_MASK             (0x01<<IOCON_SLEW_POS)
-#define IOCON_SLEW_ENABLE           ((1<<IOCON_SLEW_POS))
-
-/** Controls sink current capability of the pin*/
-#define IOCON_HIDRIVE_POS               (9)
-#define IOCON_HIDRIVE_MASK          (0x01<<IOCON_HIDRIVE_POS)
-#define IOCON_I2CMODE_FASTPLUS      (1<<IOCON_HIDRIVE_POS)
-
-/** Controls open-drain mode */
-#define IOCON_OD_POS                    (10)
-#define IOCON_OD_MASK               (0x01<<IOCON_OD_POS)
-#define IOCON_OPENDRAIN_MODE        (1<<IOCON_OD_POS)
-
-/** DAC enable control */
-#define IOCON_DACEN_POS             (16)
-#define IOCON_DACEN_MASK            (0x01<<IOCON_DACEN_POS)
-#define IOCON_DAC_ENABLE                (1<<IOCON_DACEN_POS)
-
-/* Macros define for Return Code */
-typedef    int32_t      PINSEL_RET_CODE;
-#define PINSEL_RET_OK               (0)
-#define PINSEL_RET_INVALID_PIN      (0x10000001)
-#define PINSEL_RET_NOT_SUPPORT      (0x10000002)
-#define PINSEL_RET_ERR              (-1)
-
-/**
- * @}
- */
-
-/** @defgroup PINSEL_Public_Types PINSEL Public Types
- * @{
- */
- 
-
-typedef enum
-{
-    PINSEL_BASICMODE_PLAINOUT  = 0, /**< Plain output */
-    PINSEL_BASICMODE_PULLDOWN,      /**< Pull-down enabled */
-    PINSEL_BASICMODE_PULLUP,        /**< Pull-up enabled (default) */
-    PINSEL_BASICMODE_REPEATER       /**< Repeater mode */
-}PinSel_BasicMode;
-
-typedef enum
-{
-    /** Fast mode (400 kHz clock rate) and standard (100 kHz clock rate) */
-    PINSEL_I2CMODE_FAST_STANDARD  = 0,
-    /** Open drain I/O (not I2C). No glitch filter, 3 mA typical output drive */
-    PINSEL_I2CMODE_OPENDRAINIO,
-    /** Fast Mode Plus I2C. This includes a filter for <50 ns glitches */
-    PINSEL_I2CMODE_FASTMODEPLUS,
-}PinSel_I2cMode;
-
-typedef enum
-{
-    /** Type D IOCON registers */
-    PINSEL_PIN_TYPE_D,
-    /** Type A IOCON registers */
-    PINSEL_PIN_TYPE_A,
-    /** Type U IOCON registers */
-    PINSEL_PIN_TYPE_U,
-    /** Type I IOCON registers */
-    PINSEL_PIN_TYPE_I,
-    /** Type W IOCON registers */
-    PINSEL_PIN_TYPE_W,
-    /** Unknown type */
-    PINSEL_PIN_TYPE_UNKNOWN,
-}PinSel_PinType;
-
-
-/**
- * @}
- */
- 
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup PINSEL_Public_Functions PINSEL Public Functions
- * @{
- */
- PinSel_PinType       PINSEL_GetPinType(uint8_t portnum, uint8_t pinnum);
-PINSEL_RET_CODE PINSEL_ConfigPin(uint8_t portnum, uint8_t pinnum, uint8_t funcnum);
-PINSEL_RET_CODE PINSEL_SetPinMode(uint8_t portnum, uint8_t pinnum, PinSel_BasicMode modenum);
-PINSEL_RET_CODE PINSEL_SetHysMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
-PINSEL_RET_CODE PINSEL_SetInvertInput(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
-PINSEL_RET_CODE PINSEL_SetSlewMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
-PINSEL_RET_CODE PINSEL_SetI2CMode(uint8_t portnum, uint8_t pinnum, PinSel_I2cMode I2CMode);
-PINSEL_RET_CODE PINSEL_SetOpenDrainMode(uint8_t portnum, uint8_t pinnum, FunctionalState NewState);
-PINSEL_RET_CODE PINSEL_SetAnalogPinMode (uint8_t portnum, uint8_t pinnum, uint8_t enable);
-PINSEL_RET_CODE PINSEL_DacEnable (uint8_t portnum, uint8_t pinnum, uint8_t enable);
-PINSEL_RET_CODE PINSEL_SetFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
-PINSEL_RET_CODE PINSEL_SetI2CFilter (uint8_t portnum, uint8_t pinnum, uint8_t enable);
-
-
-/**
- * @}
- */
-
-#endif /* LPC_PINSEL_H */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_pwm.h

@@ -1,357 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_pwm.h           2011-06-02
-*//**
-* @file     lpc_pwm.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for PWM firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup PWM PWM (Pulse Width Modulator)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_PWM_H_
-#define __LPC_PWM_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup PWM_Private_Macros PWM Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/**********************************************************************
-* IR register definitions
-**********************************************************************/
-/** Interrupt flag for PWM match channel for 6 channel */
-#define PWM_IR_PWMMRn(n)        ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))
-
-/** Interrupt flag for capture input */
-#define PWM_IR_PWMCAPn(n)       ((uint32_t)(1<<(n+4)))
-
-/**  IR register mask */
-#define PWM_IR_BITMASK          ((uint32_t)(0x0000073F))
-
-/**********************************************************************
-* TCR register definitions
-**********************************************************************/
-/** TCR register mask */
-#define PWM_TCR_BITMASK             ((uint32_t)(0x0000000B))
-
-/** PWM Counter Enable */
-#define PWM_TCR_COUNTER_ENABLE      ((uint32_t)(1<<0))
-
-/** PWM Counter Reset */
-#define PWM_TCR_COUNTER_RESET       ((uint32_t)(1<<1))
-
-/** PWM Enable */
-#define PWM_TCR_PWM_ENABLE          ((uint32_t)(1<<3))
-
-/**********************************************************************
-* CTCR register definitions
-**********************************************************************/
-/** CTCR register mask */
-#define PWM_CTCR_BITMASK            ((uint32_t)(0x0000000F))
-
-/** PWM Counter-Timer Mode */
-#define PWM_CTCR_MODE(n)            ((uint32_t)(n&0x03))
-
-/** PWM Capture input select */
-#define PWM_CTCR_SELECT_INPUT(n)    ((uint32_t)((n&0x03)<<2))
-
-/**********************************************************************
-* MCR register definitions
-**********************************************************************/
-/** MCR register mask */
-#define PWM_MCR_BITMASK             ((uint32_t)(0x001FFFFF))
-
-/** generate a PWM interrupt when a MATCHn occurs */
-#define PWM_MCR_INT_ON_MATCH(n)     ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))
-
-/** reset the PWM when a MATCHn occurs */
-#define PWM_MCR_RESET_ON_MATCH(n)   ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))
-
-/** stop the PWM when a MATCHn occurs */
-#define PWM_MCR_STOP_ON_MATCH(n)    ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))
-
-/**********************************************************************
-* CCR register definitions
-**********************************************************************/
-/** CCR register mask */
-#define PWM_CCR_BITMASK             ((uint32_t)(0x0000003F))
-
-/** PCAPn is rising edge sensitive */
-#define PWM_CCR_CAP_RISING(n)       ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))
-
-/** PCAPn is falling edge sensitive */
-#define PWM_CCR_CAP_FALLING(n)      ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))
-
-/** PWM interrupt is generated on a PCAP event */
-#define PWM_CCR_INT_ON_CAP(n)       ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))
-
-/**********************************************************************
-* PCR register definitions
-**********************************************************************/
-/** PCR register mask */
-#define PWM_PCR_BITMASK         (uint32_t)0x00007E7C
-
-/** PWM output n is a single edge controlled output */
-#define PWM_PCR_PWMSELn(n)      ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))
-
-/** enable PWM output n */
-#define PWM_PCR_PWMENAn(n)      ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))
-
-/**********************************************************************
-* LER register definitions
-**********************************************************************/
-/** LER register mask*/
-#define PWM_LER_BITMASK             ((uint32_t)(0x0000007F))
-
-/** PWM MATCHn register update control */
-#define PWM_LER_EN_MATCHn_LATCH(n)   ((uint32_t)((n<7) ? (1<<n) : 0))
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup PWM_Public_Types PWM Public Types
- * @{
- */
-
-typedef enum
-{
-    PWM_0 = 0,
-    PWM_1 = 1
-} en_PWM_unitId;
-
-
-/** @brief Configuration structure in PWM TIMER mode */
-typedef struct 
-{
-
-    uint8_t PrescaleOption;     /**< Prescale option, should be:
-                                - PWM_TIMER_PRESCALE_TICKVAL: Prescale in absolute value
-                                - PWM_TIMER_PRESCALE_USVAL: Prescale in microsecond value
-                                */
-    uint8_t Reserved[3];
-    uint32_t PrescaleValue;     /**< Prescale value, 32-bit long, should be matched
-                                with PrescaleOption
-                                */
-} PWM_TIMERCFG_Type;
-
-/** @brief Configuration structure in PWM COUNTER mode */
-typedef struct 
-{
-
-    uint8_t CounterOption;      /**< Counter Option, should be:
-                                - PWM_COUNTER_RISING: Rising Edge
-                                - PWM_COUNTER_FALLING: Falling Edge
-                                - PWM_COUNTER_ANY: Both rising and falling mode
-                                */
-    uint8_t CountInputSelect;   /**< Counter input select, should be:
-                                - PWM_COUNTER_PCAP1_0: PWM Counter input selected is PCAP1.0 pin
-                                - PWM_COUNTER_PCAP1_1: PWM Counter input selected is PCAP1.1 pin
-                                */
-    uint8_t Reserved[2];
-} PWM_COUNTERCFG_Type;
-
-/** @brief PWM Match channel configuration structure */
-typedef struct 
-{
-    uint8_t MatchChannel;   /**< Match channel, should be in range
-                            from 0..6 */
-    uint8_t IntOnMatch;     /**< Interrupt On match, should be:
-                            - ENABLE: Enable this function.
-                            - DISABLE: Disable this function.
-                            */
-    uint8_t StopOnMatch;    /**< Stop On match, should be:
-                            - ENABLE: Enable this function.
-                            - DISABLE: Disable this function.
-                            */
-    uint8_t ResetOnMatch;   /**< Reset On match, should be:
-                            - ENABLE: Enable this function.
-                            - DISABLE: Disable this function.
-                            */
-} PWM_MATCHCFG_Type;
-
-
-/** @brief PWM Capture Input configuration structure */
-typedef struct 
-{
-    uint8_t CaptureChannel; /**< Capture channel, should be in range
-                            from 0..1 */
-    uint8_t RisingEdge;     /**< caption rising edge, should be:
-                            - ENABLE: Enable rising edge.
-                            - DISABLE: Disable this function.
-                            */
-    uint8_t FallingEdge;        /**< caption falling edge, should be:
-                            - ENABLE: Enable falling edge.
-                            - DISABLE: Disable this function.
-                                */
-    uint8_t IntOnCaption;   /**< Interrupt On caption, should be:
-                            - ENABLE: Enable interrupt function.
-                            - DISABLE: Disable this function.
-                            */
-} PWM_CAPTURECFG_Type;
-
-/* Timer/Counter in PWM configuration type definition -----------------------------------*/
-
-/** @brief PMW TC mode select option */
-typedef enum 
-{
-    PWM_MODE_TIMER = 0,     /*!< PWM using Timer mode */
-    PWM_MODE_COUNTER,       /*!< PWM using Counter mode */
-} PWM_TC_MODE_OPT;
-
-#define PARAM_PWM_TC_MODE(n) ((n==PWM_MODE_TIMER) || (n==PWM_MODE_COUNTER))
-
-
-/** @brief PWM Timer/Counter prescale option */
-typedef enum
-{
-    PWM_TIMER_PRESCALE_TICKVAL = 0,         /*!< Prescale in absolute value */
-    PWM_TIMER_PRESCALE_USVAL                /*!< Prescale in microsecond value */
-} PWM_TIMER_PRESCALE_OPT;
-
-#define PARAM_PWM_TIMER_PRESCALE(n) ((n==PWM_TIMER_PRESCALE_TICKVAL) || (n==PWM_TIMER_PRESCALE_USVAL))
-
-
-/** @brief PWM Input Select in counter mode */
-typedef enum 
-{
-    PWM_COUNTER_PCAP1_0 = 0,        /*!< PWM Counter input selected is PCAP1.0 pin */
-    PWM_COUNTER_PCAP1_1         /*!< PWM counter input selected is CAP1.1 pin */
-} PWM_COUNTER_INPUTSEL_OPT;
-
-#define PARAM_PWM_COUNTER_INPUTSEL(n) ((n==PWM_COUNTER_PCAP1_0) || (n==PWM_COUNTER_PCAP1_1))
-
-/** @brief PWM Input Edge Option in counter mode */
-typedef enum 
-{
-    PWM_COUNTER_RISING = 1,     /*!< Rising edge mode */
-    PWM_COUNTER_FALLING = 2,    /*!< Falling edge mode */
-    PWM_COUNTER_ANY = 3         /*!< Both rising and falling mode */
-} PWM_COUNTER_EDGE_OPT;
-
-#define PARAM_PWM_COUNTER_EDGE(n)   ((n==PWM_COUNTER_RISING) || (n==PWM_COUNTER_FALLING) \
-                                            || (n==PWM_COUNTER_ANY))
-
-
-/* PWM configuration type definition ----------------------------------------------------- */
-/** @brief PWM operating mode options */
-typedef enum 
-{
-    PWM_CHANNEL_SINGLE_EDGE,    /*!< PWM Channel Single edge mode */
-    PWM_CHANNEL_DUAL_EDGE       /*!< PWM Channel Dual edge mode */
-} PWM_CHANNEL_EDGE_OPT;
-
-#define PARAM_PWM_CHANNEL_EDGE(n)   ((n==PWM_CHANNEL_SINGLE_EDGE) || (n==PWM_CHANNEL_DUAL_EDGE))
-
-
-/** @brief PWM update type */
-typedef enum 
-{
-    PWM_MATCH_UPDATE_NOW = 0,           /**< PWM Match Channel Update Now */
-    PWM_MATCH_UPDATE_NEXT_RST           /**< PWM Match Channel Update on next
-                                            PWM Counter resetting */
-} PWM_MATCH_UPDATE_OPT;
-
-#define PARAM_PWM_MATCH_UPDATE(n)   ((n==PWM_MATCH_UPDATE_NOW) || (n==PWM_MATCH_UPDATE_NEXT_RST))
-
-
-/** @brief PWM interrupt status type definition ----------------------------------------------------- */
-/** @brief PWM Interrupt status type */
-typedef enum
-{
-    PWM_INTSTAT_MR0 = PWM_IR_PWMMRn(0),     /**< Interrupt flag for PWM match channel 0 */
-    PWM_INTSTAT_MR1 = PWM_IR_PWMMRn(1),     /**< Interrupt flag for PWM match channel 1 */
-    PWM_INTSTAT_MR2 = PWM_IR_PWMMRn(2),     /**< Interrupt flag for PWM match channel 2 */
-    PWM_INTSTAT_MR3 = PWM_IR_PWMMRn(3),     /**< Interrupt flag for PWM match channel 3 */
-    PWM_INTSTAT_CAP0 = PWM_IR_PWMCAPn(0),   /**< Interrupt flag for capture input 0 */
-    PWM_INTSTAT_CAP1 = PWM_IR_PWMCAPn(1),   /**< Interrupt flag for capture input 1 */
-    PWM_INTSTAT_MR4 = PWM_IR_PWMMRn(4),     /**< Interrupt flag for PWM match channel 4 */
-    PWM_INTSTAT_MR6 = PWM_IR_PWMMRn(5),     /**< Interrupt flag for PWM match channel 5 */
-    PWM_INTSTAT_MR5 = PWM_IR_PWMMRn(6),     /**< Interrupt flag for PWM match channel 6 */
-}PWM_INTSTAT_TYPE;
-
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup PWM_Public_Functions PWM Public Functions
- * @{
- */
-
-void PWM_PinConfig(uint8_t pwmId, uint8_t PWM_Channel, uint8_t PinselOption);
-IntStatus PWM_GetIntStatus(uint8_t pwmId, uint32_t IntFlag);
-void PWM_ClearIntPending(uint8_t pwmId, uint32_t IntFlag);
-void PWM_ConfigStructInit(uint8_t PWMTimerCounterMode, void *PWM_InitStruct);
-void PWM_Init(uint8_t pwmId, uint32_t PWMTimerCounterMode, void *PWM_ConfigStruct);
-void PWM_DeInit (uint8_t pwmId);
-void PWM_Cmd(uint8_t pwmId, FunctionalState NewState);
-void PWM_CounterCmd(uint8_t pwmId, FunctionalState NewState);
-void PWM_ResetCounter(uint8_t pwmId);
-void PWM_ConfigMatch(uint8_t pwmId, PWM_MATCHCFG_Type *PWM_MatchConfigStruct);
-void PWM_ConfigCapture(uint8_t pwmId, PWM_CAPTURECFG_Type *PWM_CaptureConfigStruct);
-uint32_t PWM_GetCaptureValue(uint8_t pwmId, uint8_t CaptureChannel);
-void PWM_MatchUpdate(uint8_t pwmId, uint8_t MatchChannel, \
-                                    uint32_t MatchValue, uint8_t UpdateType);
-void PWM_ChannelConfig(uint8_t pwmId, uint8_t PWMChannel, uint8_t ModeOption);
-void PWM_ChannelCmd(uint8_t pwmId, uint8_t PWMChannel, FunctionalState NewState);
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_PWM_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_qei.h

@@ -1,547 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_qei.h           2011-06-02
-*//**
-* @file     lpc_qei.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for QEI firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup QEI QEI (Quadrature Encoder Interface)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC17X_8X_QEI_H_
-#define __LPC17X_8X_QEI_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup QEI_Public_Macros QEI Public Macros
- * @{
- */
-
-#define QEI_0                   (0)
-
-/* QEI Reset types */
-/** QEI Reset types - Reset position counter */
-#define QEI_RESET_POS           QEI_CON_RESP
-/** QEI Reset types - Reset Posistion Counter on Index */
-#define QEI_RESET_POSOnIDX      QEI_CON_RESPI
-/** QEI Reset types - Reset Velocity */
-#define QEI_RESET_VEL           QEI_CON_RESV
-/** QEI Reset types - Reset Index Counter */
-#define QEI_RESET_IDX           QEI_CON_RESI
-
-/* QEI Direction Invert Type Option */
-/** QEI Direction Invert Type Option - Direction is not inverted */
-#define QEI_DIRINV_NONE     ((uint32_t)(0))
-/** QEI Direction Invert Type Option - Direction is complemented */
-#define QEI_DIRINV_CMPL     ((uint32_t)(1))
-
-/* QEI Signal Mode Option */
-/** Signal operation: Quadrature phase mode */
-#define QEI_SIGNALMODE_QUAD     ((uint32_t)(0))
-/** Signal operation: Clock/Direction mode */
-#define QEI_SIGNALMODE_CLKDIR   ((uint32_t)(1))
-
-/* QEI Capture Mode Option */
-/** Capture mode: Only Phase-A edges are counted (2X) */
-#define QEI_CAPMODE_2X          ((uint32_t)(0))
-/** Capture mode: BOTH PhA and PhB edges are counted (4X)*/
-#define QEI_CAPMODE_4X          ((uint32_t)(1))
-
-/* QEI Invert Index Signal Option */
-/** Invert Index signal option: None */
-#define QEI_INVINX_NONE         ((uint32_t)(0))
-/** Invert Index signal option: Enable */
-#define QEI_INVINX_EN           ((uint32_t)(1))
-
-/* QEI timer reload option */
-/** Reload value in absolute value */
-#define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0))
-/** Reload value in microsecond value */
-#define QEI_TIMERRELOAD_USVAL   ((uint8_t)(1))
-
-/* QEI Flag Status type */
-/** Direction status */
-#define QEI_STATUS_DIR          ((uint32_t)(1<<0))
-
-/* QEI Compare Position channel option */
-/** QEI compare position channel 0 */
-#define QEI_COMPPOS_CH_0            ((uint8_t)(0))
-/** QEI compare position channel 1 */
-#define QEI_COMPPOS_CH_1            ((uint8_t)(1))
-/** QEI compare position channel 2 */
-#define QEI_COMPPOS_CH_2            ((uint8_t)(2))
-
-/* QEI interrupt flag type */
-/** index pulse was detected interrupt */
-#define QEI_INTFLAG_INX_Int         ((uint32_t)(1<<0))
-/** Velocity timer over flow interrupt */
-#define QEI_INTFLAG_TIM_Int         ((uint32_t)(1<<1))
-/** Capture velocity is less than compare interrupt */
-#define QEI_INTFLAG_VELC_Int        ((uint32_t)(1<<2))
-/** Change of direction interrupt */
-#define QEI_INTFLAG_DIR_Int         ((uint32_t)(1<<3))
-/** An encoder phase error interrupt */
-#define QEI_INTFLAG_ERR_Int         ((uint32_t)(1<<4))
-/** An encoder clock pulse was detected interrupt */
-#define QEI_INTFLAG_ENCLK_Int       ((uint32_t)(1<<5))
-/** position 0 compare value is equal to the current position interrupt */
-#define QEI_INTFLAG_POS0_Int        ((uint32_t)(1<<6))
-/** position 1 compare value is equal to the current position interrupt */
-#define QEI_INTFLAG_POS1_Int        ((uint32_t)(1<<7))
-/** position 2 compare value is equal to the current position interrupt */
-#define QEI_INTFLAG_POS2_Int        ((uint32_t)(1<<8))
-/** Index compare value is equal to the current index count interrupt */
-#define QEI_INTFLAG_REV_Int         ((uint32_t)(1<<9))
-/** Combined position 0 and revolution count interrupt */
-#define QEI_INTFLAG_POS0REV_Int     ((uint32_t)(1<<10))
-/** Combined position 1 and revolution count interrupt */
-#define QEI_INTFLAG_POS1REV_Int     ((uint32_t)(1<<11))
-/** Combined position 2 and revolution count interrupt */
-#define QEI_INTFLAG_POS2REV_Int     ((uint32_t)(1<<12))
-
-/**
- * @}
- */
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup QEI_Private_Macros QEI Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/* Quadrature Encoder Interface Control Register Definition --------------------- */
-/*********************************************************************//**
- * Macro defines for QEI Control register
- **********************************************************************/
-/** Reset position counter */
-#define QEI_CON_RESP        ((uint32_t)(1<<0))
-/** Reset Posistion Counter on Index */
-#define QEI_CON_RESPI       ((uint32_t)(1<<1))
-/** Reset Velocity */
-#define QEI_CON_RESV        ((uint32_t)(1<<2))
-/** Reset Index Counter */
-#define QEI_CON_RESI        ((uint32_t)(1<<3))
-/** QEI Control register bit-mask */
-#define QEI_CON_BITMASK     ((uint32_t)(0x0F))
-
-/*********************************************************************//**
- * Macro defines for QEI Configuration register
- **********************************************************************/
-/** Direction Invert */
-#define QEI_CONF_DIRINV     ((uint32_t)(1<<0))
-/** Signal mode */
-#define QEI_CONF_SIGMODE    ((uint32_t)(1<<1))
-/** Capture mode */
-#define QEI_CONF_CAPMODE    ((uint32_t)(1<<2))
-/** Invert index */
-#define QEI_CONF_INVINX     ((uint32_t)(1<<3))
-/** QEI Configuration register bit-mask */
-#define QEI_CONF_BITMASK    ((uint32_t)(0x0F))
-
-/*********************************************************************//**
- * Macro defines for QEI Status register
- **********************************************************************/
-/** Direction bit */
-#define QEI_STAT_DIR        ((uint32_t)(1<<0))
-/** QEI status register bit-mask */
-#define QEI_STAT_BITMASK    ((uint32_t)(1<<0))
-
-/* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
-/*********************************************************************//**
- * Macro defines for QEI Interrupt Status register
- **********************************************************************/
-/** Indicates that an index pulse was detected */
-#define QEI_INTSTAT_INX_Int         ((uint32_t)(1<<0))
-/** Indicates that a velocity timer overflow occurred */
-#define QEI_INTSTAT_TIM_Int         ((uint32_t)(1<<1))
-/** Indicates that capture velocity is less than compare velocity */
-#define QEI_INTSTAT_VELC_Int        ((uint32_t)(1<<2))
-/** Indicates that a change of direction was detected */
-#define QEI_INTSTAT_DIR_Int         ((uint32_t)(1<<3))
-/** Indicates that an encoder phase error was detected */
-#define QEI_INTSTAT_ERR_Int         ((uint32_t)(1<<4))
-/** Indicates that and encoder clock pulse was detected */
-#define QEI_INTSTAT_ENCLK_Int       ((uint32_t)(1<<5))
-/** Indicates that the position 0 compare value is equal to the current position */
-#define QEI_INTSTAT_POS0_Int        ((uint32_t)(1<<6))
-/** Indicates that the position 1compare value is equal to the current position */
-#define QEI_INTSTAT_POS1_Int        ((uint32_t)(1<<7))
-/** Indicates that the position 2 compare value is equal to the current position */
-#define QEI_INTSTAT_POS2_Int        ((uint32_t)(1<<8))
-/** Indicates that the index compare value is equal to the current index count */
-#define QEI_INTSTAT_REV_Int         ((uint32_t)(1<<9))
-/** Combined position 0 and revolution count interrupt. Set when
-* both the POS0_Int bit is set and the REV_Int is set */
-#define QEI_INTSTAT_POS0REV_Int     ((uint32_t)(1<<10))
-/** Combined position 1 and revolution count interrupt. Set when
-both the POS1_Int bit is set and the REV_Int is set */
-#define QEI_INTSTAT_POS1REV_Int     ((uint32_t)(1<<11))
-/** Combined position 2 and revolution count interrupt. Set when
-both the POS2_Int bit is set and the REV_Int is set */
-#define QEI_INTSTAT_POS2REV_Int     ((uint32_t)(1<<12))
-/** QEI Interrupt Status register bit-mask */
-#define QEI_INTSTAT_BITMASK         ((uint32_t)(0x1FFF))
-
-/*********************************************************************//**
- * Macro defines for QEI Interrupt Set register
- **********************************************************************/
-/** Set Bit Indicates that an index pulse was detected */
-#define QEI_INTSET_INX_Int          ((uint32_t)(1<<0))
-/** Set Bit Indicates that a velocity timer overflow occurred */
-#define QEI_INTSET_TIM_Int          ((uint32_t)(1<<1))
-/** Set Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_INTSET_VELC_Int         ((uint32_t)(1<<2))
-/** Set Bit Indicates that a change of direction was detected */
-#define QEI_INTSET_DIR_Int          ((uint32_t)(1<<3))
-/** Set Bit Indicates that an encoder phase error was detected */
-#define QEI_INTSET_ERR_Int          ((uint32_t)(1<<4))
-/** Set Bit Indicates that and encoder clock pulse was detected */
-#define QEI_INTSET_ENCLK_Int        ((uint32_t)(1<<5))
-/** Set Bit Indicates that the position 0 compare value is equal to the current position */
-#define QEI_INTSET_POS0_Int         ((uint32_t)(1<<6))
-/** Set Bit Indicates that the position 1compare value is equal to the current position */
-#define QEI_INTSET_POS1_Int         ((uint32_t)(1<<7))
-/** Set Bit Indicates that the position 2 compare value is equal to the current position */
-#define QEI_INTSET_POS2_Int         ((uint32_t)(1<<8))
-/** Set Bit Indicates that the index compare value is equal to the current index count */
-#define QEI_INTSET_REV_Int          ((uint32_t)(1<<9))
-/** Set Bit that combined position 0 and revolution count interrupt */
-#define QEI_INTSET_POS0REV_Int      ((uint32_t)(1<<10))
-/** Set Bit that Combined position 1 and revolution count interrupt */
-#define QEI_INTSET_POS1REV_Int      ((uint32_t)(1<<11))
-/** Set Bit that Combined position 2 and revolution count interrupt */
-#define QEI_INTSET_POS2REV_Int      ((uint32_t)(1<<12))
-/** QEI Interrupt Set register bit-mask */
-#define QEI_INTSET_BITMASK          ((uint32_t)(0x1FFF))
-
-/*********************************************************************//**
- * Macro defines for QEI Interrupt Clear register
- **********************************************************************/
-/** Clear Bit Indicates that an index pulse was detected */
-#define QEI_INTCLR_INX_Int          ((uint32_t)(1<<0))
-/** Clear Bit Indicates that a velocity timer overflow occurred */
-#define QEI_INTCLR_TIM_Int          ((uint32_t)(1<<1))
-/** Clear Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_INTCLR_VELC_Int         ((uint32_t)(1<<2))
-/** Clear Bit Indicates that a change of direction was detected */
-#define QEI_INTCLR_DIR_Int          ((uint32_t)(1<<3))
-/** Clear Bit Indicates that an encoder phase error was detected */
-#define QEI_INTCLR_ERR_Int          ((uint32_t)(1<<4))
-/** Clear Bit Indicates that and encoder clock pulse was detected */
-#define QEI_INTCLR_ENCLK_Int        ((uint32_t)(1<<5))
-/** Clear Bit Indicates that the position 0 compare value is equal to the current position */
-#define QEI_INTCLR_POS0_Int         ((uint32_t)(1<<6))
-/** Clear Bit Indicates that the position 1compare value is equal to the current position */
-#define QEI_INTCLR_POS1_Int         ((uint32_t)(1<<7))
-/** Clear Bit Indicates that the position 2 compare value is equal to the current position */
-#define QEI_INTCLR_POS2_Int         ((uint32_t)(1<<8))
-/** Clear Bit Indicates that the index compare value is equal to the current index count */
-#define QEI_INTCLR_REV_Int          ((uint32_t)(1<<9))
-/** Clear Bit that combined position 0 and revolution count interrupt */
-#define QEI_INTCLR_POS0REV_Int      ((uint32_t)(1<<10))
-/** Clear Bit that Combined position 1 and revolution count interrupt */
-#define QEI_INTCLR_POS1REV_Int      ((uint32_t)(1<<11))
-/** Clear Bit that Combined position 2 and revolution count interrupt */
-#define QEI_INTCLR_POS2REV_Int      ((uint32_t)(1<<12))
-/** QEI Interrupt Clear register bit-mask */
-#define QEI_INTCLR_BITMASK          ((uint32_t)(0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for QEI Interrupt Enable register
- **********************************************************************/
-/** Enabled Interrupt Bit Indicates that an index pulse was detected */
-#define QEI_INTEN_INX_Int           ((uint32_t)(1<<0))
-/** Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
-#define QEI_INTEN_TIM_Int           ((uint32_t)(1<<1))
-/** Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_INTEN_VELC_Int          ((uint32_t)(1<<2))
-/** Enabled Interrupt Bit Indicates that a change of direction was detected */
-#define QEI_INTEN_DIR_Int           ((uint32_t)(1<<3))
-/** Enabled Interrupt Bit Indicates that an encoder phase error was detected */
-#define QEI_INTEN_ERR_Int           ((uint32_t)(1<<4))
-/** Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
-#define QEI_INTEN_ENCLK_Int         ((uint32_t)(1<<5))
-/** Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the current position */
-#define QEI_INTEN_POS0_Int          ((uint32_t)(1<<6))
-/** Enabled Interrupt Bit Indicates that the position 1compare value is equal to the current position */
-#define QEI_INTEN_POS1_Int          ((uint32_t)(1<<7))
-/** Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the current position */
-#define QEI_INTEN_POS2_Int          ((uint32_t)(1<<8))
-/** Enabled Interrupt Bit Indicates that the index compare value is equal to the current index count */
-#define QEI_INTEN_REV_Int           ((uint32_t)(1<<9))
-/** Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
-#define QEI_INTEN_POS0REV_Int       ((uint32_t)(1<<10))
-/** Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
-#define QEI_INTEN_POS1REV_Int       ((uint32_t)(1<<11))
-/** Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
-#define QEI_INTEN_POS2REV_Int       ((uint32_t)(1<<12))
-/** QEI Interrupt Enable register bit-mask */
-#define QEI_INTEN_BITMASK           ((uint32_t)(0x1FFF))
-
-/*********************************************************************//**
- * Macro defines for QEI Interrupt Enable Set register
- **********************************************************************/
-/** Set Enable Interrupt Bit Indicates that an index pulse was detected */
-#define QEI_IESET_INX_Int           ((uint32_t)(1<<0))
-/** Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
-#define QEI_IESET_TIM_Int           ((uint32_t)(1<<1))
-/** Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_IESET_VELC_Int          ((uint32_t)(1<<2))
-/** Set Enable Interrupt Bit Indicates that a change of direction was detected */
-#define QEI_IESET_DIR_Int           ((uint32_t)(1<<3))
-/** Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
-#define QEI_IESET_ERR_Int           ((uint32_t)(1<<4))
-/** Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
-#define QEI_IESET_ENCLK_Int         ((uint32_t)(1<<5))
-/** Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to 
-* the current position */
-#define QEI_IESET_POS0_Int          ((uint32_t)(1<<6))
-/** Set Enable Interrupt Bit Indicates that the position 1compare value is equal to 
-* the current position */
-#define QEI_IESET_POS1_Int          ((uint32_t)(1<<7))
-/** Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to 
-* the current position */
-#define QEI_IESET_POS2_Int          ((uint32_t)(1<<8))
-/** Set Enable Interrupt Bit Indicates that the index compare value is equal to the 
-* current index count */
-#define QEI_IESET_REV_Int           ((uint32_t)(1<<9))
-/** Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
-#define QEI_IESET_POS0REV_Int       ((uint32_t)(1<<10))
-/** Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
-#define QEI_IESET_POS1REV_Int       ((uint32_t)(1<<11))
-/** Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
-#define QEI_IESET_POS2REV_Int       ((uint32_t)(1<<12))
-/** QEI Interrupt Enable Set register bit-mask */
-#define QEI_IESET_BITMASK           ((uint32_t)(0x1FFF))
-
-/*********************************************************************//**
- * Macro defines for QEI Interrupt Enable Clear register
- **********************************************************************/
-/** Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
-#define QEI_IECLR_INX_Int           ((uint32_t)(1<<0))
-/** Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
-#define QEI_IECLR_TIM_Int           ((uint32_t)(1<<1))
-/** Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
-#define QEI_IECLR_VELC_Int          ((uint32_t)(1<<2))
-/** Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
-#define QEI_IECLR_DIR_Int           ((uint32_t)(1<<3))
-/** Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
-#define QEI_IECLR_ERR_Int           ((uint32_t)(1<<4))
-/** Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
-#define QEI_IECLR_ENCLK_Int         ((uint32_t)(1<<5))
-/** Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
-* current position */
-#define QEI_IECLR_POS0_Int          ((uint32_t)(1<<6))
-/** Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
-* current position */
-#define QEI_IECLR_POS1_Int          ((uint32_t)(1<<7))
-/** Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
-* current position */
-#define QEI_IECLR_POS2_Int          ((uint32_t)(1<<8))
-/** Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
-* index count */
-#define QEI_IECLR_REV_Int           ((uint32_t)(1<<9))
-/** Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
-#define QEI_IECLR_POS0REV_Int       ((uint32_t)(1<<10))
-/** Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
-#define QEI_IECLR_POS1REV_Int       ((uint32_t)(1<<11))
-/** Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
-#define QEI_IECLR_POS2REV_Int       ((uint32_t)(1<<12))
-/** QEI Interrupt Enable Clear register bit-mask */
-#define QEI_IECLR_BITMASK           ((uint32_t)(0xFFFF))
-
-
-/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
-/* Macro check QEI peripheral */
-#define PARAM_QEIx(n)   ((n==LPC_QEI))
-
-/* Macro check QEI reset type */
-#define PARAM_QEI_RESET(n)  ((n==QEI_CON_RESP) \
-                                    || (n==QEI_RESET_POSOnIDX) \
-                                    || (n==QEI_RESET_VEL) \
-                                    || (n==QEI_RESET_IDX))
-
-/* Macro check QEI Direction invert mode */
-#define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL))
-
-/* Macro check QEI signal mode */
-#define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR))
-
-/* Macro check QEI Capture mode */
-#define PARAM_QEI_CAPMODE(n)    ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X))
-
-/* Macro check QEI Invert index mode */
-#define PARAM_QEI_INVINX(n)     ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN))
-
-/* Macro check QEI Direction invert mode */
-#define PARAM_QEI_TIMERRELOAD(n)    ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL))
-
-/* Macro check QEI status type */
-#define PARAM_QEI_STATUS(n)     ((n==QEI_STATUS_DIR))
-
-/* Macro check QEI combine position type */
-#define PARAM_QEI_COMPPOS_CH(n)     ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2))
-
-/* Macro check QEI interrupt flag type */
-#define PARAM_QEI_INTFLAG(n)    ((n==QEI_INTFLAG_INX_Int) \
-                                    || (n==QEI_INTFLAG_TIM_Int) \
-                                    || (n==QEI_INTFLAG_VELC_Int) \
-                                    || (n==QEI_INTFLAG_DIR_Int) \
-                                    || (n==QEI_INTFLAG_ERR_Int) \
-                                    || (n==QEI_INTFLAG_ENCLK_Int) \
-                                    || (n==QEI_INTFLAG_POS0_Int) \
-                                    || (n==QEI_INTFLAG_POS1_Int) \
-                                    || (n==QEI_INTFLAG_POS2_Int) \
-                                    || (n==QEI_INTFLAG_REV_Int) \
-                                    || (n==QEI_INTFLAG_POS0REV_Int) \
-                                    || (n==QEI_INTFLAG_POS1REV_Int) \
-                                    || (n==QEI_INTFLAG_POS2REV_Int))
-/**
- * @}
- */
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup QEI_Public_Types QEI Public Types
- * @{
- */
-
-/**
- * @brief QEI Configuration structure type definition
- */
-typedef struct 
-{
-    uint32_t DirectionInvert    :1;     /**< Direction invert option:
-                                        - QEI_DIRINV_NONE: QEI Direction is normal
-                                        - QEI_DIRINV_CMPL: QEI Direction is complemented
-                                        */
-    uint32_t SignalMode         :1;     /**< Signal mode Option:
-                                        - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode
-                                        - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode
-                                        */
-    uint32_t CaptureMode        :1;     /**< Capture Mode Option:
-                                        - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X)
-                                        - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X)
-                                        */
-    uint32_t InvertIndex        :1;     /**< Invert Index Option:
-                                        - QEI_INVINX_NONE: the sense of the index input is normal
-                                        - QEI_INVINX_EN: inverts the sense of the index input
-                                        */
-} QEI_CFG_Type;
-
-/**
- * @brief Timer Reload Configuration structure type definition
- */
-typedef struct 
-{
-
-    uint8_t ReloadOption;       /**< Velocity Timer Reload Option, should be:
-                                - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value
-                                - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value
-                                */
-    uint8_t Reserved[3];
-    uint32_t ReloadValue;       /**< Velocity Timer Reload Value, 32-bit long, should be matched
-                                with Velocity Timer Reload Option
-                                */
-} QEI_RELOADCFG_Type;
-
-/**
- * @brief Filter Settings for QEI registers on PHA, PHB and IDX
- */
-
-typedef struct
-{
-    uint32_t PHA_FilterVal;/**< Digital Filter Register on PHA input */
-    uint32_t PHB_FilterVal;/**< Digital Filter Register on PHB input */
-    uint32_t INX_FilterVal;/**< Digital Filter Register on IDX input */
-} st_Qei_FilterCfg;
-
-
-/**
- * @}
- */
-
-
-
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup QEI_Public_Functions QEI Public Functions
- * @{
- */
-
-void QEI_Reset(uint8_t qeiId, uint32_t ulResetType);
-void QEI_Init(uint8_t qeiId, QEI_CFG_Type *QEI_ConfigStruct);
-void QEI_GetCfgDefault(QEI_CFG_Type *QIE_InitStruct);
-void QEI_DeInit(uint8_t qeiId);
-FlagStatus QEI_GetStatus(uint8_t qeiId, uint32_t ulFlagType);
-uint32_t QEI_GetPosition(uint8_t qeiId);
-void QEI_SetMaxPosition(uint8_t qeiId, uint32_t ulMaxPos);
-void QEI_SetPositionComp(uint8_t qeiId, uint8_t bPosCompCh, uint32_t ulPosComp);
-uint32_t QEI_GetIndex(uint8_t qeiId);
-void QEI_SetIndexComp(uint8_t qeiId, uint32_t ulIndexComp);
-void QEI_SetTimerReload(uint8_t qeiId, QEI_RELOADCFG_Type *QEIReloadStruct);
-uint32_t QEI_GetTimer(uint8_t qeiId);
-uint32_t QEI_GetVelocity(uint8_t qeiId);
-uint32_t QEI_GetVelocityCap(uint8_t qeiId);
-void QEI_SetVelocityComp(uint8_t qeiId, uint32_t ulVelComp);
-void QEI_SetDigiFilter(uint8_t qeiId, st_Qei_FilterCfg FilterVal);
-FlagStatus QEI_GetIntStatus(uint8_t qeiId, uint32_t ulIntType);
-void QEI_IntCmd(uint8_t qeiId, uint32_t ulIntType, FunctionalState NewState);
-void QEI_IntSet(uint8_t qeiId, uint32_t ulIntType);
-void QEI_IntClear(uint8_t qeiId, uint32_t ulIntType);
-uint32_t QEI_CalculateRPM(uint8_t qeiId, uint32_t ulVelCapValue, uint32_t ulPPR);
-
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_QEI_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_rtc.h

@@ -1,465 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_rtc.h           2011-06-02
-*//**
-* @file     lpc_rtc.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for RTC firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup RTC   RTC (Real Time Clock)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_RTC_H_
-#define __LPC_RTC_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup RTC_Private_Macros RTC Private Macros
- * @{
- */
-
-/* ----------------------- BIT DEFINITIONS ----------------------------------- */
-/* Miscellaneous register group --------------------------------------------- */
-/**********************************************************************
-* ILR register definitions
-**********************************************************************/
-/** ILR register mask */
-#define RTC_ILR_BITMASK         ((0x00000003))
-
-/** Bit inform the source interrupt is counter increment*/
-#define RTC_IRL_RTCCIF          ((1<<0))
-
-/** Bit inform the source interrupt is alarm match*/
-#define RTC_IRL_RTCALF          ((1<<1))
-
-/**********************************************************************
-* CCR register definitions
-**********************************************************************/
-/** CCR register mask */
-#define RTC_CCR_BITMASK         ((0x00000013))
-
-/** Clock enable */
-#define RTC_CCR_CLKEN           ((1<<0))
-
-/** Clock reset */
-#define RTC_CCR_CTCRST          ((1<<1))
-
-/** Calibration counter enable */
-#define RTC_CCR_CCALEN          ((1<<4))
-
-/**********************************************************************
-* CIIR register definitions
-**********************************************************************/
-/** Counter Increment Interrupt bit for second */
-#define RTC_CIIR_IMSEC          ((1<<0))
-
-/** Counter Increment Interrupt bit for minute */
-#define RTC_CIIR_IMMIN          ((1<<1))
-
-/** Counter Increment Interrupt bit for hour */
-#define RTC_CIIR_IMHOUR         ((1<<2))
-
-/** Counter Increment Interrupt bit for day of month */
-#define RTC_CIIR_IMDOM          ((1<<3))
-
-/** Counter Increment Interrupt bit for day of week */
-#define RTC_CIIR_IMDOW          ((1<<4))
-
-/** Counter Increment Interrupt bit for day of year */
-#define RTC_CIIR_IMDOY          ((1<<5))
-
-/** Counter Increment Interrupt bit for month */
-#define RTC_CIIR_IMMON          ((1<<6))
-
-/** Counter Increment Interrupt bit for year */
-#define RTC_CIIR_IMYEAR         ((1<<7))
-
-/** CIIR bit mask */
-#define RTC_CIIR_BITMASK        ((0xFF))
-
-/**********************************************************************
-* AMR register definitions
-**********************************************************************/
-/** Counter Increment Select Mask bit for second */
-#define RTC_AMR_AMRSEC          ((1<<0))
-
-/** Counter Increment Select Mask bit for minute */
-#define RTC_AMR_AMRMIN          ((1<<1))
-
-/** Counter Increment Select Mask bit for hour */
-#define RTC_AMR_AMRHOUR         ((1<<2))
-
-/** Counter Increment Select Mask bit for day of month */
-#define RTC_AMR_AMRDOM          ((1<<3))
-
-/** Counter Increment Select Mask bit for day of week */
-#define RTC_AMR_AMRDOW          ((1<<4))
-
-/** Counter Increment Select Mask bit for day of year */
-#define RTC_AMR_AMRDOY          ((1<<5))
-
-/** Counter Increment Select Mask bit for month */
-#define RTC_AMR_AMRMON          ((1<<6))
-
-/** Counter Increment Select Mask bit for year */
-#define RTC_AMR_AMRYEAR         ((1<<7))
-
-/** AMR bit mask */
-#define RTC_AMR_BITMASK         ((0xFF))
-
-/**********************************************************************
-* RTC_AUX register definitions
-**********************************************************************/
-/** RTC Oscillator Fail detect flag */
-#define RTC_AUX_RTC_OSCF        ((1<<4))
-
-/**********************************************************************
-* RTC_AUXEN register definitions
-**********************************************************************/
-/** Oscillator Fail Detect interrupt enable*/
-#define RTC_AUXEN_RTC_OSCFEN    ((1<<4))
-
-/* Consolidated time register group ----------------------------------- */
-/**********************************************************************
-* Consolidated Time Register 0 definitions
-**********************************************************************/
-#define RTC_CTIME0_SECONDS_MASK     ((0x3F))
-#define RTC_CTIME0_MINUTES_MASK     ((0x3F00))
-#define RTC_CTIME0_HOURS_MASK       ((0x1F0000))
-#define RTC_CTIME0_DOW_MASK         ((0x7000000))
-
-/**********************************************************************
-* Consolidated Time Register 1 definitions
-**********************************************************************/
-#define RTC_CTIME1_DOM_MASK         ((0x1F))
-#define RTC_CTIME1_MONTH_MASK       ((0xF00))
-#define RTC_CTIME1_YEAR_MASK        ((0xFFF0000))
-
-/**********************************************************************
-* Consolidated Time Register 2 definitions
-**********************************************************************/
-#define RTC_CTIME2_DOY_MASK         ((0xFFF))
-
-/**********************************************************************
-* Time Counter Group and Alarm register group
-**********************************************************************/
-/** SEC register mask */
-#define RTC_SEC_MASK            (0x0000003F)
-
-/** MIN register mask */
-#define RTC_MIN_MASK            (0x0000003F)
-
-/** HOUR register mask */
-#define RTC_HOUR_MASK           (0x0000001F)
-
-/** DOM register mask */
-#define RTC_DOM_MASK            (0x0000001F)
-
-/** DOW register mask */
-#define RTC_DOW_MASK            (0x00000007)
-
-/** DOY register mask */
-#define RTC_DOY_MASK            (0x000001FF)
-
-/** MONTH register mask */
-#define RTC_MONTH_MASK          (0x0000000F)
-
-/** YEAR register mask */
-#define RTC_YEAR_MASK           (0x00000FFF)
-
-
-/** Maximum value of second */
-#define RTC_SECOND_MAX      59
-
-/** Maximum value of minute*/
-#define RTC_MINUTE_MAX      59
-
-/** Maximum value of hour*/
-#define RTC_HOUR_MAX        23
-
-/** Minimum value of month*/
-#define RTC_MONTH_MIN       1
-
-/** Maximum value of month*/
-#define RTC_MONTH_MAX       12
-
-/** Minimum value of day of month*/
-#define RTC_DAYOFMONTH_MIN  1
-
-/** Maximum value of day of month*/
-#define RTC_DAYOFMONTH_MAX  31
-
-/** Maximum value of day of week*/
-#define RTC_DAYOFWEEK_MAX   6
-
-/** Minimum value of day of year*/
-#define RTC_DAYOFYEAR_MIN   1
-
-/** Maximum value of day of year*/
-#define RTC_DAYOFYEAR_MAX   366
-
-/** Maximum value of year*/
-#define RTC_YEAR_MAX        4095
-
-/**********************************************************************
-* Calibration register
-**********************************************************************/
-/** Calibration value */
-#define RTC_CALIBRATION_CALVAL_MASK     ((0x1FFFF))
-
-/** Calibration direction */
-#define RTC_CALIBRATION_LIBDIR          ((1<<17))
-
-/** Calibration max value */
-#define RTC_CALIBRATION_MAX             ((0x20000))
-
-/** Calibration definitions */
-#define RTC_CALIB_DIR_FORWARD           ((uint8_t)(0))
-#define RTC_CALIB_DIR_BACKWARD          ((uint8_t)(1))
-
-/**********************************************************************
-* Event Monitor/Recorder Control register
-**********************************************************************/
-#define RTC_ERCTRL_EV0_INTWAKE_ENABLE       (1<<0)
-#define RTC_ERCTRL_EV0_GPCLEAR_ENABLE       (1<<1)
-#define RTC_ERCTRL_EV0_POS_EDGE             (1<<2)
-#define RTC_ERCTRL_EV0_NEG_EDGE             (0<<2)
-#define RTC_ERCTRL_EV0_INPUT_ENABLE         (1<<3)
-
-#define RTC_ERCTRL_EV1_INTWAKE_ENABLE       (1<<10)
-#define RTC_ERCTRL_EV1_GPCLEAR_ENABLE       (1<<11)
-#define RTC_ERCTRL_EV1_POS_EDGE             (1<<12)
-#define RTC_ERCTRL_EV1_NEG_EDGE             (0<<12)
-#define RTC_ERCTRL_EV1_INPUT_ENABLE         (1<<13)
-
-
-#define RTC_ERCTRL_EV2_INTWAKE_ENABLE       (1<<20)
-#define RTC_ERCTRL_EV2_GPCLEAR_ENABLE       (1<<21)
-#define RTC_ERCTRL_EV2_POS_EDGE             (1<<22)
-#define RTC_ERCTRL_EV2_NEG_EDGE             (0<<22)
-#define RTC_ERCTRL_EV2_INPUT_ENABLE         (1<<23)
-
-#define RTC_ERCTRL_MODE_MASK                (((uint32_t)3)<<30)
-#define RTC_ERCTRL_MODE_CLK_DISABLE         (((uint32_t)0)<<30)
-#define RTC_ERCTRL_MODE_16HZ                (((uint32_t)1)<<30)
-#define RTC_ERCTRL_MODE_64HZ                (((uint32_t)2)<<30)
-#define RTC_ERCTRL_MODE_1KHZ                (((uint32_t)3)<<30)
-
-#define RTC_ER_INPUT_CHANNEL_NUM            (3)
-
-/**********************************************************************
-* Event Monitor/Recorder Status register
-**********************************************************************/
-#define RTC_ER_STATUS_EV0_BIT               (0)
-#define RTC_ER_STATUS_EV1_BIT               (1)
-#define RTC_ER_STATUS_EV2_BIT               (2)
-#define RTC_ER_STATUS_GPCLEARED_BIT         (3)
-#define RTC_ER_STATUS_WAKEUP_BIT            (31)
-
-#define RTC_ER_EVENTS_ON_EV0_FLG            (1<<RTC_ER_STATUS_EV0_BIT)
-#define RTC_ER_EVENTS_ON_EV1_FLG            (1<<RTC_ER_STATUS_EV1_BIT)
-#define RTC_ER_EVENTS_ON_EV2_FLG            (1<<RTC_ER_STATUS_EV2_BIT)
-#define RTC_ER_STATUS_GP_CLEARED_FLG        (1<<RTC_ER_STATUS_GPCLEARED_BIT)
-#define RTC_ER_STATUS_WAKEUP_REQ_PENDING    (((uint32_t)1)<<RTC_ER_STATUS_WAKEUP_BIT)
-/**********************************************************************
-* Event Monitor/Recorder Counter register
-**********************************************************************/
-#define RTC_ER_EV0_COUNTER(n)               (n&0x07)
-#define RTC_ER_EV1_COUNTER(n)               ((n>>8)&0x07)
-#define RTC_ER_EV2_COUNTER(n)               ((n>>16)&0x07)
-
-/**********************************************************************
-* Event Monitor/Recorder TimeStamp register
-**********************************************************************/
-#define RTC_ER_TIMESTAMP_SEC(n)             (n&0x3F)
-#define RTC_ER_TIMESTAMP_MIN(n)             ((n>>6)&0x3F)
-#define RTC_ER_TIMESTAMP_HOUR(n)            ((n>>12)&0x1F)
-#define RTC_ER_TIMESTAMP_DOY(n)             ((n>>17)&0x1FF)
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup RTC_Public_Types RTC Public Types
- * @{
- */
-
-/** @brief Time structure definitions for easy manipulate the data */
-typedef struct 
-{
-    /** Seconds Register */
-    uint32_t SEC;
-    /** Minutes Register */
-    uint32_t MIN;
-    /** Hours Register */
-    uint32_t HOUR;
-    /** Day of Month Register */
-    uint32_t DOM;
-    /** Day of Week Register */
-    uint32_t DOW;
-    /** Day of Year Register */
-    uint32_t DOY;
-    /** Months Register */
-    uint32_t MONTH;
-    /** Years Register */
-    uint32_t YEAR;
-} RTC_TIME_Type;
-
-/** @brief RTC interrupt source */
-typedef enum 
-{
-    /**  Counter Increment Interrupt */
-    RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF,
-    /** The alarm interrupt */
-    RTC_INT_ALARM = RTC_IRL_RTCALF,
-} RTC_INT_OPT;
-
-
-/** @brief RTC time type option */
-typedef enum 
-{
-    /** Second */
-    RTC_TIMETYPE_SECOND = 0,
-    /** Month */
-    RTC_TIMETYPE_MINUTE = 1,
-    /** Hour */
-    RTC_TIMETYPE_HOUR = 2,
-    /** Day of week */
-    RTC_TIMETYPE_DAYOFWEEK = 3,
-    /** Day of month */
-    RTC_TIMETYPE_DAYOFMONTH = 4,
-    /** Day of year */
-    RTC_TIMETYPE_DAYOFYEAR = 5,
-    /** Month */
-    RTC_TIMETYPE_MONTH = 6,
-    /** Year */
-    RTC_TIMETYPE_YEAR = 7,
-} RTC_TIMETYPE_Num;
-
-/** @brief Event Monitor/Recording Input Channel configuration */
-typedef struct
-{
-    Bool    EventOnPosEdge; // Event occurs on positive edge on the channel
-    Bool    IntWake;        // Create interrupt and wake-up request if there is an event
-    Bool    GPClear;        // Clear GP registers of RTC if there is an event.
-} RTC_ER_CHANNEL_Init_Type;
-
-/** @brief Event Monitor/Recording configuration */
-typedef struct
-{
-    RTC_ER_CHANNEL_Init_Type InputChannel[RTC_ER_INPUT_CHANNEL_NUM];
-    uint32_t                 Clk;   // Sample clock on input channel. (Hz)
-} RTC_ER_CONFIG_Type;
-
-/** @brief Event Monitor/Recording TimeStamp Type */
-typedef struct 
-{
-    /** Seconds Register */
-    uint32_t SEC;
-    /** Minutes Register */
-    uint32_t MIN;
-    /** Hours Register */
-    uint32_t HOUR;
-    /** Day of Year Register */
-    uint32_t DOY;
-} RTC_ER_TIMESTAMP_Type;
-
-
-/**
- * @}
- */
-
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup RTC_Public_Functions RTC Public Functions
- * @{
- */
-
-void RTC_Init (LPC_RTC_TypeDef *RTCx);
-void RTC_DeInit(LPC_RTC_TypeDef *RTCx);
-void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx);
-void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
-void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
-                                FunctionalState NewState);
-void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
-                                FunctionalState NewState);
-void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue);
-uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
-void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
-void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
-void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue);
-uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
-void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
-void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
-IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
-void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
-void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
-void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir);
-void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value);
-uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel);
-
-void    RTC_ER_InitConfigStruct(RTC_ER_CONFIG_Type* pConfig);
-Status  RTC_ER_Init(RTC_ER_CONFIG_Type* pConfig);
-Status  RTC_ER_Cmd(uint8_t channel, FunctionalState state);
-uint8_t RTC_ER_GetEventCount(uint8_t channel);
-uint32_t RTC_ER_GetStatus(void);
-Bool    RTC_ER_WakupReqPending(void);
-Bool    RTC_ER_GPCleared(void);
-Status  RTC_ER_GetFirstTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp);
-Status  RTC_ER_GetLastTimeStamp(uint8_t channel, RTC_ER_TIMESTAMP_Type* pTimeStamp);
-void    RTC_ER_ClearStatus(uint32_t status);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_RTC_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_spifi_rom_api.h

@@ -1,248 +0,0 @@
-/***********************************************************************
-*   Copyright(C) 2011, NXP Semiconductor
-*   All rights reserved.
-*
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-**********************************************************************/
-
-#ifndef SPIFI_ROM_API_H
-#define SPIFI_ROM_API_H
-
-#include <stdint.h>
-/* define the symbol TESTING in the environment if test output desired */
-
-/* maintain LONGEST_PROT >= the length (in bytes) of the largest
-    protection block of any serial flash that this driver handles */
-#define LONGEST_PROT 68
-
-typedef uint8_t uc;
-
-#ifndef NULL
-#define NULL ((void *)0)
-#endif
-
-/* protection/sector descriptors */
-typedef struct {
-    uint32_t base;
-    uc flags;
-    int8_t log2;
-    uint16_t rept;
-} protEnt;
-/* bits in the flags byte */
-enum {RWPROT=1};
-
-/* overall data structure includes # sectors, length of protection reg, 
-   array of descriptors 
-typedef struct {
-    uint16_t sectors;
-    uint16_t protBytes;
-    protEnt *entries;
-} protDesc; */
-
-typedef union {
-    uint16_t hw;
-    uc byte[2];
-}stat_t;
-/* the object that init returns, and other routines use as an operand */
-typedef struct {
-    uint32_t base, regbase, devSize, memSize;
-    uc mfger, devType, devID, busy;
-    stat_t stat;
-    uint16_t reserved;
-    uint16_t set_prot, write_prot;
-    uint32_t mem_cmd, prog_cmd;
-    uint16_t sectors, protBytes;
-    uint32_t opts, errCheck;
-    uc erase_shifts[4], erase_ops[4];
-    protEnt *protEnts;
-    char prot[LONGEST_PROT];
-} SPIFIobj;
-
-/* operands of program and erase */
-typedef struct {
-    char *dest;
-    uint32_t length;
-    char *scratch;
-    int32_t protect;
-    uint32_t options;
-} SPIFIopers;
-
-/* instruction classes for wait_busy */
-typedef enum {stat_inst, block_erase, prog_inst, chip_erase} inst_type;
-
-/* bits in options operands (MODE3, RCVCLK, and FULLCLK 
-    have the same relationship as in the Control register) */
-#define S_MODE3 1
-#define S_MODE0 0
-#define S_MINIMAL 2
-#define S_MAXIMAL 0
-#define S_FORCE_ERASE 4
-#define S_ERASE_NOT_REQD 8
-#define S_CALLER_ERASE 8
-#define S_ERASE_AS_REQD 0
-#define S_VERIFY_PROG 0x10
-#define S_VERIFY_ERASE 0x20
-#define S_NO_VERIFY 0
-#define S_RCVCLK 0x80
-#define S_INTCLK 0
-#define S_FULLCLK 0x40
-#define S_HALFCLK 0
-#define S_DUAL 0x100
-#define S_CALLER_PROT 0x200
-#define S_DRIVER_PROT 0
-
-/* the following values in the first post-address memory command byte work
-   for all known quad devices that support "no opcode" operation */
-#define NO_OPCODE_FOLLOWS 0xA5
-#define    OPCODE_FOLLOWS 0xFF
-
-/* basic SPI commands for serial flash */
-#define BASE_READ_CMD        (CMD_RD<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|UNL_DATA)
-#define FAST_READ_CMD (CMD_READ_FAST<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|1<<INTLEN_SHIFT|UNL_DATA)
-#define BASE_PROG_CMD      (CMD_PROG<<OPCODE_SHIFT|4<<FRAMEFORM_SHIFT|DOUT)
-
-/* the length of a standard program command is 256 on all devices */
-#define PROG_SIZE 256
-
-/* options in obj->opts (mostly for setMulti) */
-/* used by Winbond: send 0xA3 command so hardware can read faster */
-#define OPT_SEND_A3        1
-/* used by SST: send 0x38 command to enable quad and allow full command set */
-#define OPT_SEND_38        2
-/* used by Winbond and others: read status reg 2, check it, 
-    if necessary write it back with Quad Enable set */
-#define OPT_35_OR02_01     4
-/* used by Atmel: read Configuration register, if necessary set Quad Enable */
-#define OPT_3F_OR80_3E     8
-/* used by Numonyx to set all-quad mode: only for parts that include RSTQIO */
-#define OPT_65_CLR_C0_61   0x10
-/* used by Numonyx: send 0x81 command to write Volatile Configuration Register
-   to set # dummy bytes and allow XIP mode */
-#define OPT_81          0x20
-/* set for devices without full device erase command (Numonyx type 0x40) */
-#define OPT_NO_DEV_ERASE 0x40
-/* used by Macronix: status reg 2 includes selection between write-protect 
-    in status reg and command-based */
-#define OPT_WPSEL       0x80
-/* set when protection data has been read into the SPIFI object */
-#define OPT_PROT_READ  0x100
-/* set if device needs 4-byte address (and maybe 0x4B command = use 4-byte address) */
-#define OPT_4BAD       0x200
-/* set if setMulti should set the Dual bit in Control reg */
-#define OPT_DUAL       0x400
-/* send "# dummy bits" in C0 command to Winbond */
-#define OPT_C0         0x800
-/* set QE for Chingis */
-#define OPT_05_OR40_01 0x1000
-/* write status does not go busy */
-#define OPT_01_NO_BUSY 0x2000
-/* protection mode bits moved from protMode byte to opts  Fri May 13 2011 */
-#define OPT_PROT_STAT 0x4000
-#define OPT_PROT_REG  0x8000
-#define OPT_PROT_CMD3 0x10000
-#define OPT_PROT_CMDE 0x20000
-#define OPT_PROT_MASK 0x3C000
-
-#define OPT_ALL_QUAD  0x40000
-
-#ifndef OMIT_ROM_TABLE
-/* interface to ROM API */
-typedef struct {
-  int32_t (*spifi_init)      (SPIFIobj *obj, uint32_t csHigh, uint32_t options, 
-                          uint32_t mhz);
-  int32_t (*spifi_program)   (SPIFIobj *obj, char *source, SPIFIopers *opers);
-  int32_t (*spifi_erase)     (SPIFIobj *obj, SPIFIopers *opers);
-  /* mode switching */
-  void (*cancel_mem_mode)(SPIFIobj *obj);
-  void (*set_mem_mode)   (SPIFIobj *obj);
-
-  /* mid level functions */
-  int32_t (*checkAd)         (SPIFIobj *obj, SPIFIopers *opers);
-  int32_t (*setProt)         (SPIFIobj *obj, SPIFIopers *opers, char *change, 
-                          char *saveProt);
-  int32_t (*check_block)     (SPIFIobj *obj, char *source, SPIFIopers *opers, 
-                          uint32_t check_program);
-  int32_t (*send_erase_cmd)  (SPIFIobj *obj, uint8_t op, uint32_t addr);
-  uint32_t (*ck_erase)   (SPIFIobj *obj, uint32_t *addr, uint32_t length);
-  int32_t (*prog_block)      (SPIFIobj *obj, char *source, SPIFIopers *opers, 
-                          uint32_t *left_in_page);
-  uint32_t (*ck_prog)    (SPIFIobj *obj, char *source, char *dest, uint32_t length);
-
-  /* low level functions */
-  void(*setSize)         (SPIFIobj *obj, int32_t value);
-  int32_t (*setDev)          (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, 
-                          uint32_t prog_cmd);
-  uint32_t (*cmd)        (uc op, uc addrLen, uc intLen, uint16_t len);
-  uint32_t (*readAd)     (SPIFIobj *obj, uint32_t cmd, uint32_t addr);
-  void (*send04)         (SPIFIobj *obj, uc op, uc len, uint32_t value);
-  void (*wren_sendAd)    (SPIFIobj *obj, uint32_t cmd, uint32_t addr, uint32_t value);
-  int32_t (*write_stat)      (SPIFIobj *obj, uc len, uint16_t value);
-  int32_t (*wait_busy)       (SPIFIobj *obj, uc prog_or_erase);
-} SPIFI_RTNS;
-
-#define define_spifi_romPtr(name) const SPIFI_RTNS *name=*((SPIFI_RTNS **)SPIFI_ROM_PTR)
-#endif /* OMIT_ROM_TABLE */
-
-#ifdef USE_SPIFI_LIB
-extern SPIFI_RTNS spifi_table;
-#endif  /* USE_SPIFI_LIB */
- 
-/* example of using this interface:
-#include "spifi_rom_api.h"
-#define CSHIGH 4
-#define SPIFI_MHZ 80
-#define source_data_ad (char *)1234
-
-    int32_t rc;
-    SPIFIopers opers;
-
-    define_spifi_romPtr(spifi);
-    SPIFIobj *obj = malloc(sizeof(SPIFIobj));
-    if (!obj) { can't allocate memory }
-
-    rc = spifi->spifi_init (obj, CSHIGH, S_FULLCLK+S_RCVCLK, SPIFI_MHZ);
-    if (rc) { investigate init error rc }
-    printf ("the serial flash contains %d bytes\n", obj->devSize);
-
-    opers.dest = where_to_program;
-    opers.length = how_many_bytes;
-    opers.scratch = NULL;           // unprogrammed data is not saved/restored
-    opers.protect = -1;             // save & restore protection
-    opers.options = S_VERIFY_PROG;
-
-    rc = spifi->spifi_program (obj, source_data_ad, &opers);
-    if (rc) { investigate program error rc }
-*/
-
-/* these are for normal users, including boot code */
-int32_t spifi_init (SPIFIobj *obj, uint32_t csHigh, uint32_t options, uint32_t mhz);
-int32_t spifi_program (SPIFIobj *obj, char *source, SPIFIopers *opers);
-int32_t spifi_erase (SPIFIobj *obj, SPIFIopers *opers);
-
-/* these are used by the manufacturer-specific init functions */
-void setSize (SPIFIobj *obj, int32_t value);
-int32_t setDev (SPIFIobj *obj, uint32_t opts, uint32_t mem_cmd, uint32_t prog_cmd);
-uint32_t read04(SPIFIobj *obj, uc op, uc len);
-int32_t write_stat (SPIFIobj *obj, uc len, uint16_t value);
-void setProtEnts(SPIFIobj *obj, const protEnt *p, uint32_t protTabLen);
-
-/* needs to be defined for each platform */
-void pullMISO(int high);
-
-#ifdef TESTING
-/* used by testing code */
-unsigned short getProtBytes (SPIFIobj *obj, unsigned short *sectors);
-/* predeclare a debug routine */
-void wait_sample (volatile unsigned *addr, unsigned mask, unsigned value);
-#endif
-
-#endif /* SPIFI_ROM_API_H */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_ssp.h

@@ -1,422 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_ssp.h           2011-06-02
-*//**
-* @file     lpc_ssp.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for SSP firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup SSP   SSP (Synchronous Serial Port)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_SSP_H_
-#define __LPC_SSP_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup SSP_Public_Macros SSP Public Macros
- * @{
- */
-
-/*********************************************************************//**
- * SSP configuration parameter defines
- **********************************************************************/
-/** Clock phase control bit */
-#define SSP_CPHA_FIRST          ((uint32_t)(0))
-#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND
-
-
-/** Clock polarity control bit */
-/* There's no bug here!!!
- * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
- * That means the active clock is in HI state.
- * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
- * high between frames. That means the active clock is in LO state.
- */
-#define SSP_CPOL_HI             ((uint32_t)(0))
-#define SSP_CPOL_LO             SSP_CR0_CPOL_HI
-
-/** SSP master mode enable */
-#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
-#define SSP_MASTER_MODE         ((uint32_t)(0))
-
-/** SSP data bit number defines */
-#define SSP_DATABIT_4       SSP_CR0_DSS(4)          /*!< Databit number = 4 */
-#define SSP_DATABIT_5       SSP_CR0_DSS(5)          /*!< Databit number = 5 */
-#define SSP_DATABIT_6       SSP_CR0_DSS(6)          /*!< Databit number = 6 */
-#define SSP_DATABIT_7       SSP_CR0_DSS(7)          /*!< Databit number = 7 */
-#define SSP_DATABIT_8       SSP_CR0_DSS(8)          /*!< Databit number = 8 */
-#define SSP_DATABIT_9       SSP_CR0_DSS(9)          /*!< Databit number = 9 */
-#define SSP_DATABIT_10      SSP_CR0_DSS(10)         /*!< Databit number = 10 */
-#define SSP_DATABIT_11      SSP_CR0_DSS(11)         /*!< Databit number = 11 */
-#define SSP_DATABIT_12      SSP_CR0_DSS(12)         /*!< Databit number = 12 */
-#define SSP_DATABIT_13      SSP_CR0_DSS(13)         /*!< Databit number = 13 */
-#define SSP_DATABIT_14      SSP_CR0_DSS(14)         /*!< Databit number = 14 */
-#define SSP_DATABIT_15      SSP_CR0_DSS(15)         /*!< Databit number = 15 */
-#define SSP_DATABIT_16      SSP_CR0_DSS(16)         /*!< Databit number = 16 */
-
-/** SSP Frame Format definition */
-/** Motorola SPI mode */
-#define SSP_FRAME_SPI       SSP_CR0_FRF_SPI
-/** TI synchronous serial mode */
-#define SSP_FRAME_TI        SSP_CR0_FRF_TI
-/** National Micro-wire mode */
-#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
-
-/*********************************************************************//**
- * SSP Status defines
- **********************************************************************/
-/** SSP status TX FIFO Empty bit */
-#define SSP_STAT_TXFIFO_EMPTY       SSP_SR_TFE
-/** SSP status TX FIFO not full bit */
-#define SSP_STAT_TXFIFO_NOTFULL     SSP_SR_TNF
-/** SSP status RX FIFO not empty bit */
-#define SSP_STAT_RXFIFO_NOTEMPTY    SSP_SR_RNE
-/** SSP status RX FIFO full bit */
-#define SSP_STAT_RXFIFO_FULL        SSP_SR_RFF
-/** SSP status SSP Busy bit */
-#define SSP_STAT_BUSY               SSP_SR_BSY
-
-/*********************************************************************//**
- * SSP Interrupt Configuration defines
- **********************************************************************/
-/** Receive Overrun */
-#define SSP_INTCFG_ROR      SSP_IMSC_ROR
-/** Receive TimeOut */
-#define SSP_INTCFG_RT       SSP_IMSC_RT
-/** Rx FIFO is at least half full */
-#define SSP_INTCFG_RX       SSP_IMSC_RX
-/** Tx FIFO is at least half empty */
-#define SSP_INTCFG_TX       SSP_IMSC_TX
-
-/*********************************************************************//**
- * SSP Configured Interrupt Status defines
- **********************************************************************/
-/** Receive Overrun */
-#define SSP_INTSTAT_ROR     SSP_MIS_ROR
-/** Receive TimeOut */
-#define SSP_INTSTAT_RT      SSP_MIS_RT
-/** Rx FIFO is at least half full */
-#define SSP_INTSTAT_RX      SSP_MIS_RX
-/** Tx FIFO is at least half empty */
-#define SSP_INTSTAT_TX      SSP_MIS_TX
-
-/*********************************************************************//**
- * SSP Raw Interrupt Status defines
- **********************************************************************/
-/** Receive Overrun */
-#define SSP_INTSTAT_RAW_ROR     SSP_RIS_ROR
-/** Receive TimeOut */
-#define SSP_INTSTAT_RAW_RT      SSP_RIS_RT
-/** Rx FIFO is at least half full */
-#define SSP_INTSTAT_RAW_RX      SSP_RIS_RX
-/** Tx FIFO is at least half empty */
-#define SSP_INTSTAT_RAW_TX      SSP_RIS_TX
-
-/*********************************************************************//**
- * SSP Interrupt Clear defines
- **********************************************************************/
-/** Writing a 1 to this bit clears the "frame was received when
- * RxFIFO was full" interrupt */
-#define SSP_INTCLR_ROR      SSP_ICR_ROR
-/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
- * has not been read for a timeout period" interrupt */
-#define SSP_INTCLR_RT       SSP_ICR_RT
-
-/*********************************************************************//**
- * SSP DMA defines
- **********************************************************************/
-/** SSP bit for enabling RX DMA */
-#define SSP_DMA_RX      SSP_DMA_RXDMA_EN
-/** SSP bit for enabling TX DMA */
-#define SSP_DMA_TX      SSP_DMA_TXDMA_EN
-
-/* SSP Status Implementation definitions */
-#define SSP_STAT_DONE       (1UL<<8)        /**< Done */
-#define SSP_STAT_ERROR      (1UL<<9)        /**< Error */
-
-/**
- * @}
- */
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup SSP_Private_Macros SSP Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/*********************************************************************//**
- * Macro defines for CR0 register
- **********************************************************************/
-/** SSP data size select, must be 4 bits to 16 bits */
-#define SSP_CR0_DSS(n)          ((uint32_t)((n-1)&0xF))
-/** SSP control 0 Motorola SPI mode */
-#define SSP_CR0_FRF_SPI         ((uint32_t)(0<<4))
-/** SSP control 0 TI synchronous serial mode */
-#define SSP_CR0_FRF_TI          ((uint32_t)(1<<4))
-/** SSP control 0 National Micro-wire mode */
-#define SSP_CR0_FRF_MICROWIRE   ((uint32_t)(2<<4))
-/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
-   bus clock high between frames, (0) = low */
-#define SSP_CR0_CPOL_HI     ((uint32_t)(1<<6))
-/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
-   on the second clock transition of the frame, (0) = first */
-#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
-/** SSP serial clock rate value load macro, divider rate is
-   PERIPH_CLK / (cpsr * (SCR + 1)) */
-#define SSP_CR0_SCR(n)      ((uint32_t)((n&0xFF)<<8))
-/** SSP CR0 bit mask */
-#define SSP_CR0_BITMASK     ((uint32_t)(0xFFFF))
-
-/*********************************************************************//**
- * Macro defines for CR1 register
- **********************************************************************/
-/** SSP control 1 loopback mode enable bit */
-#define SSP_CR1_LBM_EN      ((uint32_t)(1<<0))
-/** SSP control 1 enable bit */
-#define SSP_CR1_SSP_EN      ((uint32_t)(1<<1))
-/** SSP control 1 slave enable */
-#define SSP_CR1_SLAVE_EN    ((uint32_t)(1<<2))
-/** SSP control 1 slave out disable bit, disables transmit line in slave
-   mode */
-#define SSP_CR1_SO_DISABLE  ((uint32_t)(1<<3))
-/** SSP CR1 bit mask */
-#define SSP_CR1_BITMASK     ((uint32_t)(0x0F))
-
-/*********************************************************************//**
- * Macro defines for DR register
- **********************************************************************/
-/** SSP data bit mask */
-#define SSP_DR_BITMASK(n)   ((n)&0xFFFF)
-
-/*********************************************************************//**
- * Macro defines for SR register
- **********************************************************************/
-/** SSP status TX FIFO Empty bit */
-#define SSP_SR_TFE      ((uint32_t)(1<<0))
-/** SSP status TX FIFO not full bit */
-#define SSP_SR_TNF      ((uint32_t)(1<<1))
-/** SSP status RX FIFO not empty bit */
-#define SSP_SR_RNE      ((uint32_t)(1<<2))
-/** SSP status RX FIFO full bit */
-#define SSP_SR_RFF      ((uint32_t)(1<<3))
-/** SSP status SSP Busy bit */
-#define SSP_SR_BSY      ((uint32_t)(1<<4))
-/** SSP SR bit mask */
-#define SSP_SR_BITMASK  ((uint32_t)(0x1F))
-
-/*********************************************************************//**
- * Macro defines for CPSR register
- **********************************************************************/
-/** SSP clock prescaler */
-#define SSP_CPSR_CPDVSR(n)  ((uint32_t)(n&0xFF))
-/** SSP CPSR bit mask */
-#define SSP_CPSR_BITMASK    ((uint32_t)(0xFF))
-
-/*********************************************************************//**
- * Macro define for (IMSC) Interrupt Mask Set/Clear registers
- **********************************************************************/
-/** Receive Overrun */
-#define SSP_IMSC_ROR    ((uint32_t)(1<<0))
-/** Receive TimeOut */
-#define SSP_IMSC_RT     ((uint32_t)(1<<1))
-/** Rx FIFO is at least half full */
-#define SSP_IMSC_RX     ((uint32_t)(1<<2))
-/** Tx FIFO is at least half empty */
-#define SSP_IMSC_TX     ((uint32_t)(1<<3))
-/** IMSC bit mask */
-#define SSP_IMSC_BITMASK    ((uint32_t)(0x0F))
-
-/*********************************************************************//**
- * Macro define for (RIS) Raw Interrupt Status registers
- **********************************************************************/
-/** Receive Overrun */
-#define SSP_RIS_ROR     ((uint32_t)(1<<0))
-/** Receive TimeOut */
-#define SSP_RIS_RT      ((uint32_t)(1<<1))
-/** Rx FIFO is at least half full */
-#define SSP_RIS_RX      ((uint32_t)(1<<2))
-/** Tx FIFO is at least half empty */
-#define SSP_RIS_TX      ((uint32_t)(1<<3))
-/** RIS bit mask */
-#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
-
-/*********************************************************************//**
- * Macro define for (MIS) Masked Interrupt Status registers
- **********************************************************************/
-/** Receive Overrun */
-#define SSP_MIS_ROR     ((uint32_t)(1<<0))
-/** Receive TimeOut */
-#define SSP_MIS_RT      ((uint32_t)(1<<1))
-/** Rx FIFO is at least half full */
-#define SSP_MIS_RX      ((uint32_t)(1<<2))
-/** Tx FIFO is at least half empty */
-#define SSP_MIS_TX      ((uint32_t)(1<<3))
-/** MIS bit mask */
-#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
-
-/*********************************************************************//**
- * Macro define for (ICR) Interrupt Clear registers
- **********************************************************************/
-/** Writing a 1 to this bit clears the "frame was received when
- * RxFIFO was full" interrupt */
-#define SSP_ICR_ROR     ((uint32_t)(1<<0))
-/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
- * has not been read for a timeout period" interrupt */
-#define SSP_ICR_RT      ((uint32_t)(1<<1))
-/** ICR bit mask */
-#define SSP_ICR_BITMASK ((uint32_t)(0x03))
-
-/*********************************************************************//**
- * Macro defines for DMACR register
- **********************************************************************/
-/** SSP bit for enabling RX DMA */
-#define SSP_DMA_RXDMA_EN    ((uint32_t)(1<<0))
-/** SSP bit for enabling TX DMA */
-#define SSP_DMA_TXDMA_EN    ((uint32_t)(1<<1))
-/** DMACR   bit mask */
-#define SSP_DMA_BITMASK     ((uint32_t)(0x03))
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup SSP_Public_Types SSP Public Types
- * @{
- */
-
-/** @brief SSP configuration structure */
-typedef struct {
-    uint32_t Databit;       /** Databit number, should be SSP_DATABIT_x,
-                            where x is in range from 4 - 16 */
-    uint32_t CPHA;          /** Clock phase, should be:
-                            - SSP_CPHA_FIRST: first clock edge
-                            - SSP_CPHA_SECOND: second clock edge */
-    uint32_t CPOL;          /** Clock polarity, should be:
-                            - SSP_CPOL_HI: high level
-                            - SSP_CPOL_LO: low level */
-    uint32_t Mode;          /** SSP mode, should be:
-                            - SSP_MASTER_MODE: Master mode
-                            - SSP_SLAVE_MODE: Slave mode */
-    uint32_t FrameFormat;   /** Frame Format:
-                            - SSP_FRAME_SPI: Motorola SPI frame format
-                            - SSP_FRAME_TI: TI frame format
-                            - SSP_FRAME_MICROWIRE: National Microwire frame format */
-    uint32_t ClockRate;     /** Clock rate,in Hz */
-} SSP_CFG_Type;
-
-/**
- * @brief SSP Transfer Type definitions
- */
-typedef enum {
-    SSP_TRANSFER_POLLING = 0,   /**< Polling transfer */
-    SSP_TRANSFER_INTERRUPT      /**< Interrupt transfer */
-} SSP_TRANSFER_Type;
-
-/**
- * @brief SPI Data configuration structure definitions
- */
-typedef struct {
-    void *tx_data;              /**< Pointer to transmit data */
-    uint32_t tx_cnt;            /**< Transmit counter */
-    void *rx_data;              /**< Pointer to transmit data */
-    uint32_t rx_cnt;            /**< Receive counter */
-    uint32_t length;            /**< Length of transfer data */
-    uint32_t status;            /**< Current status of SSP activity */
-} SSP_DATA_SETUP_Type;
-
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup SSP_Public_Functions SSP Public Functions
- * @{
- */
-
-/* SSP Init/DeInit functions --------------------------------------------------*/
-void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
-void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
-
-/* SSP configure functions ----------------------------------------------------*/
-void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
-
-/* SSP enable/disable functions -----------------------------------------------*/
-void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
-void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
-void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
-void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
-
-/* SSP get information functions ----------------------------------------------*/
-FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
-uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
-IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
-uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
-IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
-
-/* SSP transfer data functions ------------------------------------------------*/
-void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
-uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
-int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
-                        SSP_TRANSFER_Type xfType);
-
-/* SSP IRQ function ------------------------------------------------------------*/
-void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
-void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
-
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_SSP_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_systick.h

@@ -1,119 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_systick.h           2011-06-02
-*//**
-* @file     lpc_systick.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for SYSTICK firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup SYSTICK   SysTick (System tick timer)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_SYSTICK_H_
-#define __LPC_SYSTICK_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup SYSTICK_Private_Macros SysTick Private Macros
- * @{
- */
-/*********************************************************************//**
- * Macro defines for System Timer Control and status (STCTRL) register
- **********************************************************************/
-#define ST_CTRL_ENABLE      ((uint32_t)(1<<0))
-#define ST_CTRL_TICKINT     ((uint32_t)(1<<1))
-#define ST_CTRL_CLKSOURCE   ((uint32_t)(1<<2))
-#define ST_CTRL_COUNTFLAG   ((uint32_t)(1<<16))
-
-/*********************************************************************//**
- * Macro defines for System Timer Reload value (STRELOAD) register
- **********************************************************************/
-#define ST_RELOAD_RELOAD(n)     ((uint32_t)(n & 0x00FFFFFF))
-
-/*********************************************************************//**
- * Macro defines for System Timer Current value (STCURRENT) register
- **********************************************************************/
-#define ST_RELOAD_CURRENT(n)    ((uint32_t)(n & 0x00FFFFFF))
-
-/*********************************************************************//**
- * Macro defines for System Timer Calibration value (STCALIB) register
- **********************************************************************/
-#define ST_CALIB_TENMS(n)       ((uint32_t)(n & 0x00FFFFFF))
-#define ST_CALIB_SKEW           ((uint32_t)(1<<30))
-#define ST_CALIB_NOREF          ((uint32_t)(1<<31))
-
-#define CLKSOURCE_EXT           ((uint32_t)(0))
-#define CLKSOURCE_CPU           ((uint32_t)(1))
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup SYSTICK_Public_Functions Systick Public Functions
- * @{
- */
-
-void SYSTICK_InternalInit(uint32_t time);
-void SYSTICK_ExternalInit(uint32_t freq, uint32_t time);
-
-void SYSTICK_Cmd(FunctionalState NewState);
-void SYSTICK_IntCmd(FunctionalState NewState);
-uint32_t SYSTICK_GetCurrentValue(void);
-void SYSTICK_ClearCounterFlag(void);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_SYSTICK_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_timer.h

@@ -1,321 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_timer.h         2011-06-02
-*//**
-* @file     lpc_timer.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for Timer firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup TIMER TIM (Timer)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_TIMER_H_
-#define __LPC_TIMER_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup TIM_Private_Macros Timer Private Macros
- * @{
- */
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/**********************************************************************
-** Interrupt information
-**********************************************************************/
-/** Macro to clean interrupt pending */
-#define TIM_IR_CLR(n) _BIT(n)
-
-/**********************************************************************
-** Timer interrupt register definitions
-**********************************************************************/
-/** Macro for getting a timer match interrupt bit */
-#define TIM_MATCH_INT(n)        (_BIT(n & 0x0F))
-/** Macro for getting a capture event interrupt bit */
-#define TIM_CAP_INT(n)     (_BIT(((n & 0x0F) + 4)))
-
-/**********************************************************************
-* Timer control register definitions
-**********************************************************************/
-/** Timer/counter enable bit */
-#define TIM_ENABLE          ((uint32_t)(1<<0))
-/** Timer/counter reset bit */
-#define TIM_RESET           ((uint32_t)(1<<1))
-/** Timer control bit mask */
-#define TIM_TCR_MASKBIT     ((uint32_t)(3))
-
-/**********************************************************************
-* Timer match control register definitions
-**********************************************************************/
-/** Bit location for interrupt on MRx match, n = 0 to 3 */
-#define TIM_INT_ON_MATCH(n)         (_BIT((n * 3)))
-/** Bit location for reset on MRx match, n = 0 to 3 */
-#define TIM_RESET_ON_MATCH(n)       (_BIT(((n * 3) + 1)))
-/** Bit location for stop on MRx match, n = 0 to 3 */
-#define TIM_STOP_ON_MATCH(n)        (_BIT(((n * 3) + 2)))
-/** Timer Match control bit mask */
-#define TIM_MCR_MASKBIT            ((uint32_t)(0x0FFF))
-/** Timer Match control bit mask for specific channel*/
-#define TIM_MCR_CHANNEL_MASKBIT(n)      ((uint32_t)(7<<(n*3)))
-
-/**********************************************************************
-* Timer capture control register definitions
-**********************************************************************/
-/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
-#define TIM_CAP_RISING(n)       (_BIT((n * 3)))
-/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
-#define TIM_CAP_FALLING(n)      (_BIT(((n * 3) + 1)))
-/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
-#define TIM_INT_ON_CAP(n)       (_BIT(((n * 3) + 2)))
-/** Mask bit for rising and falling edge bit */
-#define TIM_EDGE_MASK(n)        (_SBF((n * 3), 0x03))
-/** Timer capture control bit mask */
-#define TIM_CCR_MASKBIT         ((uint32_t)(0x3F))
-/** Timer Capture control bit mask for specific channel*/
-#define TIM_CCR_CHANNEL_MASKBIT(n)      ((uint32_t)(7<<(n*3)))
-
-/**********************************************************************
-* Timer external match register definitions
-**********************************************************************/
-/** Bit location for output state change of MAT.n when external match
-   happens, n = 0 to 3 */
-#define TIM_EM(n)               _BIT(n)
-/** Output state change of MAT.n when external match happens: no change */
-#define TIM_EM_NOTHING      ((uint8_t)(0x0))
-/** Output state change of MAT.n when external match happens: low */
-#define TIM_EM_LOW          ((uint8_t)(0x1))
-/** Output state change of MAT.n when external match happens: high */
-#define TIM_EM_HIGH         ((uint8_t)(0x2))
-/** Output state change of MAT.n when external match happens: toggle */
-#define TIM_EM_TOGGLE       ((uint8_t)(0x3))
-/** Macro for setting for the MAT.n change state bits */
-#define TIM_EM_SET(n,s)     (_SBF(((n << 1) + 4), (s & 0x03)))
-/** Mask for the MAT.n change state bits */
-#define TIM_EM_MASK(n)      (_SBF(((n << 1) + 4), 0x03))
-/** Timer external match bit mask */
-#define TIM_EMR_MASKBIT 0x0FFF
-
-/**********************************************************************
-* Timer Count Control Register definitions
-**********************************************************************/
-/** Mask to get the Counter/timer mode bits */
-#define TIM_CTCR_MODE_MASK  0x3
-/** Mask to get the count input select bits */
-#define TIM_CTCR_INPUT_MASK 0xC
-/** Timer Count control bit mask */
-#define TIM_CTCR_MASKBIT    0xF
-#define TIM_COUNTER_MODE ((uint8_t)(1))
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup TIM_Public_Types Timer Public Types
- * @{
- */
-
-/***********************************************************************
- * Timer device enumeration
-**********************************************************************/
-/** @brief interrupt type */
-typedef enum
-{
-    TIM_MR0_INT =0, /*!< interrupt for Match channel 0*/
-    TIM_MR1_INT =1, /*!< interrupt for Match channel 1*/
-    TIM_MR2_INT =2, /*!< interrupt for Match channel 2*/
-    TIM_MR3_INT =3, /*!< interrupt for Match channel 3*/
-    TIM_CR0_INT =4, /*!< interrupt for Capture channel 0*/
-    TIM_CR1_INT =5, /*!< interrupt for Capture channel 1*/
-}TIM_INT_TYPE;
-
-/** @brief Timer/counter operating mode */
-typedef enum
-{
-    TIM_TIMER_MODE = 0,             /*!< Timer mode */
-    TIM_COUNTER_RISING_MODE,        /*!< Counter rising mode */
-    TIM_COUNTER_FALLING_MODE,       /*!< Counter falling mode */
-    TIM_COUNTER_ANY_MODE            /*!< Counter on both edges */
-} TIM_MODE_OPT;
-
-/** @brief Timer/Counter prescale option */
-typedef enum
-{
-    TIM_PRESCALE_TICKVAL = 0,       /*!< Prescale in absolute value */
-    TIM_PRESCALE_USVAL              /*!< Prescale in microsecond value */
-} TIM_PRESCALE_OPT;
-
-/** @brief Counter input option */
-typedef enum
-{
-    TIM_COUNTER_INCAP0 = 0,         /*!< CAPn.0 input pin for TIMERn */
-    TIM_COUNTER_INCAP1,             /*!< CAPn.1 input pin for TIMERn */
-} TIM_COUNTER_INPUT_OPT;
-
-/** @brief Timer/Counter external match option */
-typedef enum
-{
-    TIM_EXTMATCH_NOTHING = 0,       /*!< Do nothing for external output pin if match */
-    TIM_EXTMATCH_LOW,               /*!< Force external output pin to low if match */
-    TIM_EXTMATCH_HIGH,              /*!< Force external output pin to high if match */
-    TIM_EXTMATCH_TOGGLE             /*!< Toggle external output pin if match */
-}TIM_EXTMATCH_OPT;
-
-/** @brief Timer/counter capture mode options */
-typedef enum {
-    TIM_CAPTURE_NONE = 0,   /*!< No Capture */
-    TIM_CAPTURE_RISING,     /*!< Rising capture mode */
-    TIM_CAPTURE_FALLING,    /*!< Falling capture mode */
-    TIM_CAPTURE_ANY         /*!< On both edges */
-} TIM_CAP_MODE_OPT;
-
-/** @brief Configuration structure in TIMER mode */
-typedef struct
-{
-
-    uint8_t PrescaleOption;     /**< Timer Prescale option, should be:
-                                    - TIM_PRESCALE_TICKVAL: Prescale in absolute value
-                                    - TIM_PRESCALE_USVAL: Prescale in microsecond value
-                                    */
-    uint8_t Reserved[3];        /**< Reserved */
-    uint32_t PrescaleValue;     /**< Prescale value */
-} TIM_TIMERCFG_Type;
-
-/** @brief Configuration structure in COUNTER mode */
-typedef struct {
-
-    uint8_t CounterOption;      /**< Counter Option, should be:
-                                - TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
-                                - TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
-                                */
-    uint8_t CountInputSelect;
-    uint8_t Reserved[2];
-} TIM_COUNTERCFG_Type;
-
-/** @brief Match channel configuration structure */
-typedef struct {
-    uint8_t MatchChannel;   /**< Match channel, should be in range
-                            from 0..3 */
-    uint8_t IntOnMatch;     /**< Interrupt On match, should be:
-                            - ENABLE: Enable this function.
-                            - DISABLE: Disable this function.
-                            */
-    uint8_t StopOnMatch;    /**< Stop On match, should be:
-                            - ENABLE: Enable this function.
-                            - DISABLE: Disable this function.
-                            */
-    uint8_t ResetOnMatch;   /**< Reset On match, should be:
-                            - ENABLE: Enable this function.
-                            - DISABLE: Disable this function.
-                            */
-
-    uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
-                             -   TIM_EXTMATCH_NOTHING:  Do nothing for external output pin if match
-                             -   TIM_EXTMATCH_LOW:  Force external output pin to low if match
-                             -   TIM_EXTMATCH_HIGH: Force external output pin to high if match
-                             -   TIM_EXTMATCH_TOGGLE: Toggle external output pin if match.
-                            */
-    uint8_t Reserved[3];    /** Reserved */
-    uint32_t MatchValue;    /** Match value */
-} TIM_MATCHCFG_Type;
-
-/** @brief Capture Input configuration structure */
-typedef struct {
-    uint8_t CaptureChannel; /**< Capture channel, should be in range
-                            from 0..1 */
-    uint8_t RisingEdge;     /**< caption rising edge, should be:
-                            - ENABLE: Enable rising edge.
-                            - DISABLE: Disable this function.
-                            */
-    uint8_t FallingEdge;        /**< caption falling edge, should be:
-                            - ENABLE: Enable falling edge.
-                            - DISABLE: Disable this function.
-                                */
-    uint8_t IntOnCaption;   /**< Interrupt On caption, should be:
-                            - ENABLE: Enable interrupt function.
-                            - DISABLE: Disable this function.
-                            */
-
-} TIM_CAPTURECFG_Type;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup TIM_Public_Functions Timer Public Functions
- * @{
- */
-/* Init/DeInit TIM functions -----------*/
-void TIM_Init(LPC_TIM_TypeDef *TIMx, TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
-void TIM_DeInit(LPC_TIM_TypeDef *TIMx);
-
-/* TIM interrupt functions -------------*/
-void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
-void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
-FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
-FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, TIM_INT_TYPE IntFlag);
-
-/* TIM configuration functions --------*/
-void TIM_ConfigStructInit(TIM_MODE_OPT TimerCounterMode, void *TIM_ConfigStruct);
-void TIM_ConfigMatch(LPC_TIM_TypeDef *TIMx, TIM_MATCHCFG_Type *TIM_MatchConfigStruct);
-void TIM_UpdateMatchValue(LPC_TIM_TypeDef *TIMx,uint8_t MatchChannel, uint32_t MatchValue);
-void TIM_ConfigCapture(LPC_TIM_TypeDef *TIMx, TIM_CAPTURECFG_Type *TIM_CaptureConfigStruct);
-void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState);
-
-uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, TIM_COUNTER_INPUT_OPT CaptureChannel);
-void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx);
-
-void TIM_Waitus(uint32_t time);
-void TIM_Waitms(uint32_t time);
-
-/**
- * @}
- */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_TIMER_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_types.h

@@ -1,211 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_types.h         2011-06-02
-*//**
-* @file     lpc_types.h
-* @brief    Contains the NXP ABL typedefs for C standard types.
-*           It is intended to be used in ISO C conforming development
-*           environments and checks for this insofar as it is possible
-*           to do so.
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Type group ----------------------------------------------------------- */
-#ifndef __LPC_TYPES_H
-#define __LPC_TYPES_H
-
-/* Includes ------------------------------------------------------------------- */
-#include <stdint.h>
-
-/** @defgroup LPC_Type_Def Data Types Definitions
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
- 
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup LPC_Types_Public_Types Basic Public Data Types
- * @{
- */
-
-/**
- * @brief Boolean Type definition
- */
-typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
-
-/**
- * @brief Flag Status and Interrupt Flag Status type definition
- */
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
-#define PARAM_SETSTATE(State) ((State==RESET) || (State==SET))
-
-/**
- * @brief Functional State Definition
- */
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define PARAM_FUNCTIONALSTATE(State) ((State==DISABLE) || (State==ENABLE))
-
-/**
- * @ Status type definition
- */
-typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
-
-
-/**
- * Read/Write transfer type mode (Block or non-block)
- */
-typedef enum
-{
-    NONE_BLOCKING = 0,      /**< None Blocking type */
-    BLOCKING,               /**< Blocking type */
-} TRANSFER_BLOCK_Type;
-
-
-/** Pointer to Function returning Void (any number of parameters) */
-typedef void (*PFV)();
-
-/** Pointer to Function returning int32_t (any number of parameters) */
-typedef int32_t(*PFI)();
-
-/**
- * @}
- */
-
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup LPC_Types_Public_Macros  Basic Public Macros
- * @{
- */
-
-/** _BIT(n) sets the bit at position "n"
- * _BIT(n) is intended to be used in "OR" and "AND" expressions:
- * e.g., "(_BIT(3) | _BIT(7))".
- */
-#undef _BIT
-/** Set bit macro */
-#define _BIT(n) (1<<n)
-
-/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
- * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
- * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
- */
-#undef _SBF
-/* Set bit field macro */
-#define _SBF(f,v) (v<<f)
-
-/* _BITMASK constructs a symbol with 'field_width' least significant
- * bits set.
- * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
- * The symbol is intended to be used to limit the bit field width
- * thusly:
- * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
- * If "any_expression" results in a value that is larger than can be
- * contained in 'x' bits, the bits above 'x - 1' are masked off.  When
- * used with the _SBF example above, the example would be written:
- * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
- * This ensures that the value written to a_reg is no wider than
- * 16 bits, and makes the code easier to read and understand.
- */
-#undef _BITMASK
-/* Bitmask creation macro */
-#define _BITMASK(field_width) ( _BIT(field_width) - 1)
-
-/* NULL pointer */
-#ifndef NULL
-#define NULL ((void*) 0)
-#endif
-
-/* Number of elements in an array */
-#define NELEMENTS(array)  (sizeof (array) / sizeof (array[0]))
-
-/* Static data/function define */
-#define STATIC static
-/* External data/function define */
-#define EXTERN extern
-
-#if !defined(MAX)
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
-#endif
-#if !defined(MIN)
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-#endif
-
-/**
- * @}
- */
-
-
-/* Old Type Definition compatibility ------------------------------------------ */
-/** @addtogroup LPC_Types_Public_Types LPC_Types Public Types
- * @{
- */
-
-/** SMA type for character type */
-typedef char CHAR;
-
-/** SMA type for 8 bit unsigned value */
-typedef uint8_t UNS_8;
-
-/** SMA type for 8 bit signed value */
-typedef int8_t INT_8;
-
-/** SMA type for 16 bit unsigned value */
-typedef uint16_t UNS_16;
-
-/** SMA type for 16 bit signed value */
-typedef int16_t INT_16;
-
-/** SMA type for 32 bit unsigned value */
-typedef uint32_t UNS_32;
-
-/** SMA type for 32 bit signed value */
-typedef int32_t INT_32;
-
-/** SMA type for 64 bit signed value */
-typedef int64_t INT_64;
-
-/** SMA type for 64 bit unsigned value */
-typedef uint64_t UNS_64;
-
-/** 32 bit boolean type */
-typedef Bool BOOL_32;
-
-/** 16 bit boolean type */
-typedef Bool BOOL_16;
-
-/** 8 bit boolean type */
-typedef Bool BOOL_8;
-
-/**
- * @}
- */
-
-
-#endif /* __LPC_TYPES_H */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_uart.h

@@ -1,710 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_uart.h          2011-06-02
-*//**
-* @file     lpc_uart.h
-* @brief    Contains all macro definitions and function prototypes
-*           support for UART firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup UART  UART (Universal Asynchronous Receiver/Transmitter)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_UART_H_
-#define __LPC_UART_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/* Public Macros -------------------------------------------------------------- */
-/** @defgroup UART_Public_Macros  UART Public Macros
- * @{
- */
-
-/** UART time-out definitions in case of using Read() and Write function
- * with Blocking Flag mode
- */
-#define UART_BLOCKING_TIMEOUT           (0xFFFFFFFFUL)
-
-/**
- * @}
- */
-
-/* Private Macros ------------------------------------------------------------- */
-/** @defgroup UART_Private_Macros UART Private Macros
- * @{
- */
-
-/* Accepted Error baud rate value (in percent unit) */
-#define UART_ACCEPTED_BAUDRATE_ERROR    (3)         /*!< Acceptable UART baudrate error */
-
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/*********************************************************************//**
- * Macro defines for Macro defines for UARTn Receiver Buffer Register
- **********************************************************************/
-/** UART Received Buffer mask bit (8 bits) */
-#define UART_RBR_MASKBIT    ((uint8_t)0xFF)
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UARTn Transmit Holding Register
- **********************************************************************/
-/** UART Transmit Holding mask bit (8 bits) */
-#define UART_THR_MASKBIT    ((uint8_t)0xFF)
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UARTn Divisor Latch LSB register
- **********************************************************************/
-/** Macro for loading least significant halfs of divisors */
-#define UART_LOAD_DLL(div)  ((div) & 0xFF)
-/** Divisor latch LSB bit mask */
-#define UART_DLL_MASKBIT    ((uint8_t)0xFF)
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UARTn Divisor Latch MSB register
- **********************************************************************/
-/** Divisor latch MSB bit mask */
-#define UART_DLM_MASKBIT    ((uint8_t)0xFF)
-/** Macro for loading most significant halfs of divisors */
-#define UART_LOAD_DLM(div)  (((div) >> 8) & 0xFF)
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART interrupt enable register
- **********************************************************************/
-/** RBR Interrupt enable*/
-#define UART_IER_RBRINT_EN      ((uint32_t)(1<<0))
-/** THR Interrupt enable*/
-#define UART_IER_THREINT_EN     ((uint32_t)(1<<1))
-/** RX line status interrupt enable*/
-#define UART_IER_RLSINT_EN      ((uint32_t)(1<<2))
-/** Modem status interrupt enable */
-#define UART1_IER_MSINT_EN      ((uint32_t)(1<<3))
-/** CTS1 signal transition interrupt enable */
-#define UART1_IER_CTSINT_EN     ((uint32_t)(1<<7))
-/** Enables the end of auto-baud interrupt */
-#define UART_IER_ABEOINT_EN     ((uint32_t)(1<<8))
-/** Enables the auto-baud time-out interrupt */
-#define UART_IER_ABTOINT_EN     ((uint32_t)(1<<9))
-/** UART interrupt enable register bit mask */
-#define UART_IER_BITMASK        ((uint32_t)(0x307))
-/** UART1 interrupt enable register bit mask */
-#define UART1_IER_BITMASK       ((uint32_t)(0x38F))
-
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART interrupt identification register
- **********************************************************************/
-/** Interrupt Status - Active low */
-#define UART_IIR_INTSTAT_PEND   ((uint32_t)(1<<0))
-/** Interrupt identification: Receive line status*/
-#define UART_IIR_INTID_RLS      ((uint32_t)(3<<1))
-/** Interrupt identification: Receive data available*/
-#define UART_IIR_INTID_RDA      ((uint32_t)(2<<1))
-/** Interrupt identification: Character time-out indicator*/
-#define UART_IIR_INTID_CTI      ((uint32_t)(6<<1))
-/** Interrupt identification: THRE interrupt*/
-#define UART_IIR_INTID_THRE     ((uint32_t)(1<<1))
-/** Interrupt identification: Modem interrupt*/
-#define UART1_IIR_INTID_MODEM   ((uint32_t)(0<<1))
-/** Interrupt identification: Interrupt ID mask */
-#define UART_IIR_INTID_MASK     ((uint32_t)(7<<1))
-/** These bits are equivalent to UnFCR[0] */
-#define UART_IIR_FIFO_EN        ((uint32_t)(3<<6))
-/** End of auto-baud interrupt */
-#define UART_IIR_ABEO_INT       ((uint32_t)(1<<8))
-/** Auto-baud time-out interrupt */
-#define UART_IIR_ABTO_INT       ((uint32_t)(1<<9))
-/** UART interrupt identification register bit mask */
-#define UART_IIR_BITMASK        ((uint32_t)(0x3CF))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART FIFO control register
- **********************************************************************/
-/** UART FIFO enable */
-#define UART_FCR_FIFO_EN        ((uint8_t)(1<<0))
-/** UART FIFO RX reset */
-#define UART_FCR_RX_RS          ((uint8_t)(1<<1))
-/** UART FIFO TX reset */
-#define UART_FCR_TX_RS          ((uint8_t)(1<<2))
-/** UART DMA mode selection */
-#define UART_FCR_DMAMODE_SEL    ((uint8_t)(1<<3))
-/** UART FIFO trigger level 0: 1 character */
-#define UART_FCR_TRG_LEV0       ((uint8_t)(0))
-/** UART FIFO trigger level 1: 4 character */
-#define UART_FCR_TRG_LEV1       ((uint8_t)(1<<6))
-/** UART FIFO trigger level 2: 8 character */
-#define UART_FCR_TRG_LEV2       ((uint8_t)(2<<6))
-/** UART FIFO trigger level 3: 14 character */
-#define UART_FCR_TRG_LEV3       ((uint8_t)(3<<6))
-/** UART FIFO control bit mask */
-#define UART_FCR_BITMASK        ((uint8_t)(0xCF))
-
-#define UART_TX_FIFO_SIZE       (16)
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART line control register
- **********************************************************************/
-/** UART 5 bit data mode */
-#define UART_LCR_WLEN5          ((uint8_t)(0))
-/** UART 6 bit data mode */
-#define UART_LCR_WLEN6          ((uint8_t)(1<<0))
-/** UART 7 bit data mode */
-#define UART_LCR_WLEN7          ((uint8_t)(2<<0))
-/** UART 8 bit data mode */
-#define UART_LCR_WLEN8          ((uint8_t)(3<<0))
-/** UART Two Stop Bits Select */
-#define UART_LCR_STOPBIT_SEL    ((uint8_t)(1<<2))
-/** UART Parity Enable */
-#define UART_LCR_PARITY_EN      ((uint8_t)(1<<3))
-/** UART Odd Parity Select */
-#define UART_LCR_PARITY_ODD     ((uint8_t)(0))
-/** UART Even Parity Select */
-#define UART_LCR_PARITY_EVEN    ((uint8_t)(1<<4))
-/** UART force 1 stick parity */
-#define UART_LCR_PARITY_F_1     ((uint8_t)(2<<4))
-/** UART force 0 stick parity */
-#define UART_LCR_PARITY_F_0     ((uint8_t)(3<<4))
-/** UART Transmission Break enable */
-#define UART_LCR_BREAK_EN       ((uint8_t)(1<<6))
-/** UART Divisor Latches Access bit enable */
-#define UART_LCR_DLAB_EN        ((uint8_t)(1<<7))
-/** UART line control bit mask */
-#define UART_LCR_BITMASK        ((uint8_t)(0xFF))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART1 Modem Control Register
- **********************************************************************/
-/** Source for modem output pin DTR */
-#define UART1_MCR_DTR_CTRL      ((uint8_t)(1<<0))
-/** Source for modem output pin RTS */
-#define UART1_MCR_RTS_CTRL      ((uint8_t)(1<<1))
-/** Loop back mode select */
-#define UART1_MCR_LOOPB_EN      ((uint8_t)(1<<4))
-/** Enable Auto RTS flow-control */
-#define UART1_MCR_AUTO_RTS_EN   ((uint8_t)(1<<6))
-/** Enable Auto CTS flow-control */
-#define UART1_MCR_AUTO_CTS_EN   ((uint8_t)(1<<7))
-/** UART1 bit mask value */
-#define UART1_MCR_BITMASK       ((uint8_t)(0x0F3))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART line status register
- **********************************************************************/
-/** Line status register: Receive data ready*/
-#define UART_LSR_RDR        ((uint8_t)(1<<0))
-/** Line status register: Overrun error*/
-#define UART_LSR_OE         ((uint8_t)(1<<1))
-/** Line status register: Parity error*/
-#define UART_LSR_PE         ((uint8_t)(1<<2))
-/** Line status register: Framing error*/
-#define UART_LSR_FE         ((uint8_t)(1<<3))
-/** Line status register: Break interrupt*/
-#define UART_LSR_BI         ((uint8_t)(1<<4))
-/** Line status register: Transmit holding register empty*/
-#define UART_LSR_THRE       ((uint8_t)(1<<5))
-/** Line status register: Transmitter empty*/
-#define UART_LSR_TEMT       ((uint8_t)(1<<6))
-/** Error in RX FIFO*/
-#define UART_LSR_RXFE       ((uint8_t)(1<<7))
-/** UART Line status bit mask */
-#define UART_LSR_BITMASK    ((uint8_t)(0xFF))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART Modem (UART1 only) status register
- **********************************************************************/
-/** Set upon state change of input CTS */
-#define UART1_MSR_DELTA_CTS     ((uint8_t)(1<<0))
-/** Set upon state change of input DSR */
-#define UART1_MSR_DELTA_DSR     ((uint8_t)(1<<1))
-/** Set upon low to high transition of input RI */
-#define UART1_MSR_LO2HI_RI      ((uint8_t)(1<<2))
-/** Set upon state change of input DCD */
-#define UART1_MSR_DELTA_DCD     ((uint8_t)(1<<3))
-/** Clear To Send State */
-#define UART1_MSR_CTS           ((uint8_t)(1<<4))
-/** Data Set Ready State */
-#define UART1_MSR_DSR           ((uint8_t)(1<<5))
-/** Ring Indicator State */
-#define UART1_MSR_RI            ((uint8_t)(1<<6))
-/** Data Carrier Detect State */
-#define UART1_MSR_DCD           ((uint8_t)(1<<7))
-/** MSR register bit-mask value */
-#define UART1_MSR_BITMASK       ((uint8_t)(0xFF))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART Scratch Pad Register
- **********************************************************************/
-/** UART Scratch Pad bit mask */
-#define UART_SCR_BIMASK     ((uint8_t)(0xFF))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART Auto baudrate control register
- **********************************************************************/
-/** UART Auto-baud start */
-#define UART_ACR_START              ((uint32_t)(1<<0))
-/** UART Auto baudrate Mode 1 */
-#define UART_ACR_MODE               ((uint32_t)(1<<1))
-/** UART Auto baudrate restart */
-#define UART_ACR_AUTO_RESTART       ((uint32_t)(1<<2))
-/** UART End of auto-baud interrupt clear */
-#define UART_ACR_ABEOINT_CLR        ((uint32_t)(1<<8))
-/** UART Auto-baud time-out interrupt clear */
-#define UART_ACR_ABTOINT_CLR        ((uint32_t)(1<<9))
-/** UART Auto Baudrate register bit mask */
-#define UART_ACR_BITMASK            ((uint32_t)(0x307))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART IrDA control register
- **********************************************************************/
-/** IrDA mode enable */
-#define UART_ICR_IRDAEN         ((uint32_t)(1<<0))
-/** IrDA serial input inverted */
-#define UART_ICR_IRDAINV        ((uint32_t)(1<<1))
-/** IrDA fixed pulse width mode */
-#define UART_ICR_FIXPULSE_EN    ((uint32_t)(1<<2))
-/** PulseDiv - Configures the pulse when FixPulseEn = 1 */
-#define UART_ICR_PULSEDIV(n)    ((uint32_t)((n&0x07)<<3))
-/** UART IRDA bit mask */
-#define UART_ICR_BITMASK        ((uint32_t)(0x3F))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART Fractional divider register
- **********************************************************************/
-/** Baud-rate generation pre-scaler divisor */
-#define UART_FDR_DIVADDVAL(n)   ((uint32_t)(n&0x0F))
-/** Baud-rate pre-scaler multiplier value */
-#define UART_FDR_MULVAL(n)      ((uint32_t)((n<<4)&0xF0))
-/** UART Fractional Divider register bit mask */
-#define UART_FDR_BITMASK        ((uint32_t)(0xFF))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART Tx Enable register
- **********************************************************************/
-/** Transmit enable bit */
-#define UART_TER_TXEN           ((uint8_t)(1<<7))
-/** UART Transmit Enable Register bit mask */
-#define UART_TER_BITMASK        ((uint8_t)(0x80))
-/** Transmit enable bit on UART4 */
-#define UART4_TER_TXEN          ((uint8_t)(1<<0))
-/** UART4 Transmit Enable Register bit mask */
-#define UART4_TER_BITMASK       ((uint8_t)(0x01))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART RS485 Control register
- **********************************************************************/
-/** RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
-#define UART_RS485CTRL_NMM_EN       ((uint32_t)(1<<0))
-/** The receiver is disabled */
-#define UART_RS485CTRL_RX_DIS       ((uint32_t)(1<<1))
-/** Auto Address Detect (AAD) is enabled */
-#define UART_RS485CTRL_AADEN        ((uint32_t)(1<<2))
-/** If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control */
-#define UART_RS485CTRL_SEL_DTR      ((uint32_t)(1<<3))
-/** Enable Auto Direction Control */
-#define UART_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4))
-/** This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 
-The direction control pin will be driven to logic "1" when the transmitter has data to be sent */
-#define UART_RS485CTRL_OINV_1       ((uint32_t)(1<<5))
-
-/** RS485 control bit-mask value */
-#define UART_RS485CTRL_BITMASK      ((uint32_t)(0x3F))
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART RS-485 Address Match register
- **********************************************************************/
-#define UART_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF))    /**< Bit mask value */
-
-/*********************************************************************//**
- * Macro defines for Macro defines for UART1 RS-485 Delay value register
- **********************************************************************/
-/* Macro defines for UART1 RS-485 Delay value register */
-#define UART_RS485DLY_BITMASK       ((uint8_t)(0xFF))   /** Bit mask value */
-
-
-/**
- * @}
- */
-
-
-/* Public Types --------------------------------------------------------------- */
-/** @defgroup UART_Public_Types UART Public Types
- * @{
- */
-
-/**
- * @brief UART ID
- */
- typedef enum
-{
-    UART_0 = 0,
-    UART_1,
-    UART_2,
-    UART_3,
-    UART_4,
-} UART_ID_Type;
-
-/**
- * @brief UART Databit type definitions
- */
-typedef enum {
-    UART_DATABIT_5      = 0,            /*!< UART 5 bit data mode */
-    UART_DATABIT_6,                     /*!< UART 6 bit data mode */
-    UART_DATABIT_7,                     /*!< UART 7 bit data mode */
-    UART_DATABIT_8                      /*!< UART 8 bit data mode */
-} UART_DATABIT_Type;
-
-/**
- * @brief UART Stop bit type definitions
- */
-typedef enum {
-    UART_STOPBIT_1      = (0),                      /*!< UART 1 Stop Bits Select */
-    UART_STOPBIT_2,                                 /*!< UART Two Stop Bits Select */
-} UART_STOPBIT_Type;
-
-/**
- * @brief UART Parity type definitions
- */
-typedef enum {
-    UART_PARITY_NONE    = 0,                    /*!< No parity */
-    UART_PARITY_ODD,                            /*!< Odd parity */
-    UART_PARITY_EVEN,                           /*!< Even parity */
-    UART_PARITY_SP_1,                           /*!< Forced "1" stick parity */
-    UART_PARITY_SP_0                            /*!< Forced "0" stick parity */
-} UART_PARITY_Type;
-
-/**
- * @brief FIFO Level type definitions
- */
-typedef enum {
-    UART_FIFO_TRGLEV0 = 0,  /*!< UART FIFO trigger level 0: 1 character */
-    UART_FIFO_TRGLEV1,      /*!< UART FIFO trigger level 1: 4 character */
-    UART_FIFO_TRGLEV2,      /*!< UART FIFO trigger level 2: 8 character */
-    UART_FIFO_TRGLEV3       /*!< UART FIFO trigger level 3: 14 character */
-} UART_FITO_LEVEL_Type;
-
-/********************************************************************//**
-* @brief UART Interrupt Type definitions
-**********************************************************************/
-typedef enum {
-    UART_INTCFG_RBR = 0,    /*!< RBR Interrupt enable*/
-    UART_INTCFG_THRE,       /*!< THR Interrupt enable*/
-    UART_INTCFG_RLS,        /*!< RX line status interrupt enable*/
-    UART_INTCFG_MS,     /*!< Modem status interrupt enable (UART1 only) */
-    UART_INTCFG_CTS,        /*!< CTS1 signal transition interrupt enable (UART1 only) */
-    UART_INTCFG_ABEO,       /*!< Enables the end of auto-baud interrupt */
-    UART_INTCFG_ABTO        /*!< Enables the auto-baud time-out interrupt */
-} UART_INT_Type;
-
-/**
- * @brief UART Line Status Type definition
- */
-typedef enum {
-    UART_LINESTAT_RDR   = UART_LSR_RDR,         /*!<Line status register: Receive data ready*/
-    UART_LINESTAT_OE    = UART_LSR_OE,          /*!<Line status register: Overrun error*/
-    UART_LINESTAT_PE    = UART_LSR_PE,          /*!<Line status register: Parity error*/
-    UART_LINESTAT_FE    = UART_LSR_FE,          /*!<Line status register: Framing error*/
-    UART_LINESTAT_BI    = UART_LSR_BI,          /*!<Line status register: Break interrupt*/
-    UART_LINESTAT_THRE  = UART_LSR_THRE,        /*!<Line status register: Transmit holding register empty*/
-    UART_LINESTAT_TEMT  = UART_LSR_TEMT,        /*!<Line status register: Transmitter empty*/
-    UART_LINESTAT_RXFE  = UART_LSR_RXFE         /*!<Error in RX FIFO*/
-} UART_LS_Type;
-
-/**
- * @brief UART Auto-baudrate mode type definition
- */
-typedef enum {
-    UART_AUTOBAUD_MODE0             = 0,            /**< UART Auto baudrate Mode 0 */
-    UART_AUTOBAUD_MODE1,                            /**< UART Auto baudrate Mode 1 */
-} UART_AB_MODE_Type;
-
-/**
- * @brief Auto Baudrate mode configuration type definition
- */
-typedef struct {
-    UART_AB_MODE_Type   ABMode;         /**< Autobaudrate mode */
-    FunctionalState     AutoRestart;    /**< Auto Restart state */
-} UART_AB_CFG_Type;
-
-/**
- * @brief UART End of Auto-baudrate type definition
- */
-typedef enum {
-    UART_AUTOBAUD_INTSTAT_ABEO      = UART_IIR_ABEO_INT,        /**< UART End of auto-baud interrupt  */
-    UART_AUTOBAUD_INTSTAT_ABTO      = UART_IIR_ABTO_INT         /**< UART Auto-baud time-out interrupt  */
-}UART_ABEO_Type;
-
-/**
- * UART IrDA Control type Definition
- */
-typedef enum 
-{
-    /** Pulse width = 2 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV2     = 0,
-
-    /** Pulse width = 4 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV4,
-
-    /** Pulse width = 8 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV8,
-
-    /** Pulse width = 16 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV16,
-
-    /** Pulse width = 32 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV32,
-
-    /**< Pulse width = 64 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV64,
-
-    /**< Pulse width = 128 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV128,
-
-    /**< Pulse width = 256 * Tpclk
-    - Configures the pulse when FixPulseEn = 1 */
-    UART_IrDA_PULSEDIV256
-} UART_IrDA_PULSE_Type;
-
-/********************************************************************//**
-* @brief UART1 Full modem -  Signal states definition
-**********************************************************************/
-typedef enum {
-    INACTIVE = 0,           /* In-active state */
-    ACTIVE = !INACTIVE      /* Active state */
-}UART1_SignalState;
-
-/**
- * @brief UART modem status type definition
- */
-typedef enum {
-    UART1_MODEM_STAT_DELTA_CTS  = UART1_MSR_DELTA_CTS,      /*!< Set upon state change of input CTS */
-    UART1_MODEM_STAT_DELTA_DSR  = UART1_MSR_DELTA_DSR,      /*!< Set upon state change of input DSR */
-    UART1_MODEM_STAT_LO2HI_RI   = UART1_MSR_LO2HI_RI,       /*!< Set upon low to high transition of input RI */
-    UART1_MODEM_STAT_DELTA_DCD  = UART1_MSR_DELTA_DCD,      /*!< Set upon state change of input DCD */
-    UART1_MODEM_STAT_CTS        = UART1_MSR_CTS,            /*!< Clear To Send State */
-    UART1_MODEM_STAT_DSR        = UART1_MSR_DSR,            /*!< Data Set Ready State */
-    UART1_MODEM_STAT_RI         = UART1_MSR_RI,             /*!< Ring Indicator State */
-    UART1_MODEM_STAT_DCD        = UART1_MSR_DCD             /*!< Data Carrier Detect State */
-} UART_MODEM_STAT_type;
-
-/**
- * @brief Modem output pin type definition
- */
-typedef enum {
-    UART1_MODEM_PIN_DTR         = 0,        /*!< Source for modem output pin DTR */
-    UART1_MODEM_PIN_RTS                     /*!< Source for modem output pin RTS */
-} UART_MODEM_PIN_Type;
-
-/**
- * @brief UART Modem mode type definition
- */
-typedef enum {
-    UART1_MODEM_MODE_LOOPBACK   = 0,        /*!< Loop back mode select */
-    UART1_MODEM_MODE_AUTO_RTS,              /*!< Enable Auto RTS flow-control */
-    UART1_MODEM_MODE_AUTO_CTS               /*!< Enable Auto CTS flow-control */
-} UART_MODEM_MODE_Type;
-
-/**
- * @brief UART Direction Control Pin type definition
- */
-typedef enum {
-    UART_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */
-    UART_RS485_DIRCTRL_DTR          /**< Pin DTR is used for direction control */
-} UART_RS485_DIRCTRL_PIN_Type;
-
-/********************************************************************//**
-* @brief UART Configuration Structure definition
-**********************************************************************/
-typedef struct {
-  uint32_t Baud_rate;           /**< UART baud rate */
-  UART_PARITY_Type Parity;      /**< Parity selection, should be:
-                               - UART_PARITY_NONE: No parity
-                               - UART_PARITY_ODD: Odd parity
-                               - UART_PARITY_EVEN: Even parity
-                               - UART_PARITY_SP_1: Forced "1" stick parity
-                               - UART_PARITY_SP_0: Forced "0" stick parity
-                               */
-  UART_DATABIT_Type Databits;   /**< Number of data bits, should be:
-                               - UART_DATABIT_5: UART 5 bit data mode
-                               - UART_DATABIT_6: UART 6 bit data mode
-                               - UART_DATABIT_7: UART 7 bit data mode
-                               - UART_DATABIT_8: UART 8 bit data mode
-                               */
-  UART_STOPBIT_Type Stopbits;   /**< Number of stop bits, should be:
-                               - UART_STOPBIT_1: UART 1 Stop Bits Select
-                               - UART_STOPBIT_2: UART 2 Stop Bits Select
-                               */
-} UART_CFG_Type;
-
-/********************************************************************//**
-* @brief UART FIFO Configuration Structure definition
-**********************************************************************/
-
-typedef struct {
-    FunctionalState FIFO_ResetRxBuf;    /**< Reset Rx FIFO command state , should be:
-                                         - ENABLE: Reset Rx FIFO in UART
-                                         - DISABLE: Do not reset Rx FIFO  in UART
-                                         */
-    FunctionalState FIFO_ResetTxBuf;    /**< Reset Tx FIFO command state , should be:
-                                         - ENABLE: Reset Tx FIFO in UART
-                                         - DISABLE: Do not reset Tx FIFO  in UART
-                                         */
-    FunctionalState FIFO_DMAMode;       /**< DMA mode, should be:
-                                         - ENABLE: Enable DMA mode in UART
-                                         - DISABLE: Disable DMA mode in UART
-                                         */
-    UART_FITO_LEVEL_Type FIFO_Level;    /**< Rx FIFO trigger level, should be:
-                                        - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character
-                                        - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character
-                                        - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character
-                                        - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character
-                                        */
-} UART_FIFO_CFG_Type;
-
-/********************************************************************//**
-* @brief UART1 Full modem -  RS485 Control configuration type
-**********************************************************************/
-typedef struct {
-    FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State:
-                                                    - ENABLE: Enable this function.
-                                                    - DISABLE: Disable this function. */
-    FunctionalState Rx_State;                   /*!< Receiver State:
-                                                    - ENABLE: Enable Receiver.
-                                                    - DISABLE: Disable Receiver. */
-    FunctionalState AutoAddrDetect_State;       /*!< Auto Address Detect mode state:
-                                                - ENABLE: ENABLE this function.
-                                                - DISABLE: Disable this function. */
-    FunctionalState AutoDirCtrl_State;          /*!< Auto Direction Control State:
-                                                - ENABLE: Enable this function.
-                                                - DISABLE: Disable this function. */
-    UART_RS485_DIRCTRL_PIN_Type DirCtrlPin;     /*!< If direction control is enabled, state:
-                                                - UART1_RS485_DIRCTRL_RTS:
-                                                pin RTS is used for direction control.
-                                                - UART1_RS485_DIRCTRL_DTR:
-                                                pin DTR is used for direction control. */
-     SetState DirCtrlPol_Level;                 /*!< Polarity of the direction control signal on
-                                                the RTS (or DTR) pin:
-                                                - RESET: The direction control pin will be driven
-                                                to logic "0" when the transmitter has data to be sent.
-                                                - SET: The direction control pin will be driven
-                                                to logic "1" when the transmitter has data to be sent. */
-    uint8_t MatchAddrValue;                 /*!< address match value for RS-485/EIA-485 mode, 8-bit long */
-    uint8_t DelayValue;                     /*!< delay time is in periods of the baud clock, 8-bit long */
-} UART1_RS485_CTRLCFG_Type;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup UART_Public_Functions UART Public Functions
- * @{
- */
-/* UART Init/DeInit functions --------------------------------------------------*/
-void UART_Init(UART_ID_Type UartID, UART_CFG_Type *UART_ConfigStruct);
-void UART_DeInit(UART_ID_Type UartID);
-void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct);
-
-/* UART Send/Receive functions -------------------------------------------------*/
-void UART_SendByte(UART_ID_Type UartID, uint8_t Data);
-uint8_t UART_ReceiveByte(UART_ID_Type UartID);
-uint32_t UART_Send(UART_ID_Type UartID, uint8_t *txbuf,
-        uint32_t buflen, TRANSFER_BLOCK_Type flag);
-uint32_t UART_Receive(UART_ID_Type UartID, uint8_t *rxbuf, \
-        uint32_t buflen, TRANSFER_BLOCK_Type flag);
-
-/* UART FIFO functions ----------------------------------------------------------*/
-void UART_FIFOConfig(UART_ID_Type UartID, UART_FIFO_CFG_Type *FIFOCfg);
-void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct);
-
-/* UART get information functions -----------------------------------------------*/
-uint32_t UART_GetIntId(UART_ID_Type UartID);
-uint8_t UART_GetLineStatus(UART_ID_Type UartID);
-
-/* UART operate functions -------------------------------------------------------*/
-void UART_IntConfig(UART_ID_Type UartID, UART_INT_Type UARTIntCfg, \
-                FunctionalState NewState);
-void UART_TxCmd(UART_ID_Type UartID, FunctionalState NewState);
-FlagStatus UART_CheckBusy(UART_ID_Type UartID);
-void UART_ForceBreak(UART_ID_Type UartID);
-
-/* UART Auto-baud functions -----------------------------------------------------*/
-void UART_ABClearIntPending(UART_ID_Type UartID, UART_ABEO_Type ABIntType);
-void UART_ABCmd(UART_ID_Type UartID, UART_AB_CFG_Type *ABConfigStruct, \
-                FunctionalState NewState);
-
-/* UART1 FullModem functions ----------------------------------------------------*/
-void UART_FullModemForcePinState(UART_ID_Type UartID, UART_MODEM_PIN_Type Pin, \
-                            UART1_SignalState NewState);
-void UART_FullModemConfigMode(UART_ID_Type UartID, UART_MODEM_MODE_Type Mode, \
-                            FunctionalState NewState);
-uint8_t UART_FullModemGetStatus(UART_ID_Type UartID);
-
-/* UART RS485 functions ----------------------------------------------------------*/
-void UART_RS485Config(UART_ID_Type UartID,
-                                    UART1_RS485_CTRLCFG_Type *RS485ConfigStruct);
-void UART_RS485ReceiverCmd(UART_ID_Type UartID, FunctionalState NewState);
-void UART_RS485SendSlvAddr(UART_ID_Type UartID, uint8_t SlvAddr);
-uint32_t UART_RS485SendData(UART_ID_Type UartID, uint8_t *pData, uint32_t size);
-
-/* UART IrDA functions-------------------------------------------------------------*/
-void UART_IrDAInvtInputCmd(UART_ID_Type UartID, FunctionalState NewState);
-void UART_IrDACmd(UART_ID_Type UartID, FunctionalState NewState);
-void UART_IrDAPulseDivConfig(UART_ID_Type UartID, UART_IrDA_PULSE_Type PulseDiv);
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __LPC_UART_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/include/lpc_wwdt.h

@@ -1,188 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_wwdt.h          2011-06-02
-*//**
-* @file     lpc_wwdt.h
-* @brief    Contains all macro definitions and function prototypes
-*           support forWindow Watchdog Timer firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @defgroup WWDT  WWDT (Windowed Watchdog Timer)
- * @ingroup LPC_CMSIS_FwLib_Drivers
- * @{
- */
-
-#ifndef __LPC_WWDT_H_
-#define __LPC_WWDT_H_
-
-/* Includes ------------------------------------------------------------------- */
-#include "LPC407x_8x_177x_8x.h"
-#include "lpc_types.h"
-
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/** @defgroup WDT_Private_Macros WDT Private Macros
- * @{
- */
-
-
-// time is calculated by usec
-#define WDT_GET_FROM_USEC(time)     (time/((WWDT_US_INDEX * 4)/WDT_OSC))
-#define WDT_GET_USEC(counter)       (counter * ((WWDT_US_INDEX * 4)/WDT_OSC))
-
-
-#define WWDT_FUNC_OK            (0)
-#define WWDT_FUNC_BAD_PARAM     (-1)
-
-
-/* --------------------- BIT DEFINITIONS -------------------------------------- */
-/** WWDT interrupt enable bit */
-#define WWDT_WDMOD_WDEN             ((uint32_t)(1<<0))
-/** WWDT interrupt enable bit */
-#define WWDT_WDMOD_WDRESET          ((uint32_t)(1<<1))
-/** WWDT time out flag bit */
-#define WWDT_WDMOD_WDTOF            ((uint32_t)(1<<2))
-/** WDT Time Out flag bit */
-#define WWDT_WDMOD_WDINT            ((uint32_t)(1<<3))
-/** WWDT Protect flag bit */
-#define WWDT_WDMOD_WDPROTECT        ((uint32_t)(1<<4))
-
-/** Define divider index for microsecond ( us ) */
-#define WWDT_US_INDEX       ((uint32_t)(1000000))
-
-/** WWDT Time out minimum value */
-#define WWDT_TIMEOUT_MIN    ((uint32_t)(0xFF))
-/** WWDT Time out maximum value */
-#define WWDT_TIMEOUT_MAX    ((uint32_t)(0x00FFFFFF))
-
-/** WWDT Warning minimum value */
-#define WWDT_WARNINT_MIN    ((uint32_t)(0xFF))
-/** WWDT Warning maximum value */
-#define WWDT_WARNINT_MAX    ((uint32_t)(0x000003FF))
-
-/** WWDT Windowed minimum value */
-#define WWDT_WINDOW_MIN     ((uint32_t)(0xFF))
-/** WWDT Windowed minimum value */
-#define WWDT_WINDOW_MAX     ((uint32_t)(0x00FFFFFF))
-
-/** WWDT timer constant register mask */
-#define WWDT_WDTC_MASK          ((uint32_t)(0x00FFFFFF))
-/** WWDT warning value register mask */
-#define WWDT_WDWARNINT_MASK     ((uint32_t)(0x000003FF))
-/** WWDT feed sequence register mask */
-#define WWDT_WDFEED_MASK        ((uint32_t)(0x000000FF))
-
-/** WWDT flag */
-#define WWDT_WARNINT_FLAG       ((uint8_t)(0))
-#define WWDT_TIMEOUT_FLAG       ((uint8_t)(1))
-
-/** WWDT mode definitions */
-#define WWDT_PROTECT_MODE       ((uint8_t)(0))
-#define WWDT_RESET_MODE         ((uint8_t)(1))
-
-
-/* WWDT Timer value definition (us) */
-#define WWDT_TIMEOUT_USEC_MIN           ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MIN)))//microseconds
-#define WWDT_TIMEOUT_USEC_MAX           ((uint32_t)(WDT_GET_USEC(WWDT_TIMEOUT_MAX)))
-
-#define WWDT_TIMEWARN_USEC_MIN          ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MIN)))
-#define WWDT_TIMEWARN_USEC_MAX          ((uint32_t)(WDT_GET_USEC(WWDT_WARNINT_MAX)))
-
-#define WWDT_TIMEWINDOWED_USEC_MIN      ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MIN)))
-#define WWDT_TIMEWINDOWED_USEC_MAX      ((uint32_t)(WDT_GET_USEC(WWDT_WINDOW_MAX)))
-
-
-/**
- * @}
- */
-
-/** @defgroup WDT_Public_Types WDT Public Types
- * @{
- */
-
-/**
- * @brief The field to configurate the WatchDog Timer
- */
-
-typedef struct Wdt_Config
-{
-    uint8_t wdtEnable;      /**< if ENABLE -> the enable bit is enabled */
-    uint8_t wdtReset;       /**< if ENABLE -> the Reset bit is enabled */
-    uint8_t wdtProtect;     /**< if ENABLE -> the Protect bit is enabled */
-    uint32_t wdtTmrConst;   /**< Set the constant value to timeout the WDT */
-    uint32_t wdtWarningVal; /**< Set the value to warn the WDT with interrupt */
-    uint32_t wdtWindowVal;  /**< Set a window vaule for WDT */
-}st_Wdt_Config;
-
-/**
- * @}
- */
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @defgroup WDT_Public_Functions WDT Public Functions
- * @{
- */
-
-int8_t WWDT_Init(uint32_t TimeOut);
-int8_t WWDT_Start(uint32_t TimeOut);
-void WWDT_SetMode(uint8_t mode, FunctionalState NewState);
-void WWDT_SetTimerConstant(uint32_t constVal);
-void WWDT_Enable(FunctionalState NewState);
-void WWDT_Cmd(FunctionalState NewState);
-int8_t WWDT_SetWarningRaw(uint32_t warnVal);
-int8_t WWDT_SetWarning(uint32_t WarnTime);
-int8_t WWDT_SetWindowRaw(uint32_t wndVal);
-int8_t WWDT_SetWindow(uint32_t WindowedTime);
-void WWDT_UpdateTimeOut(uint32_t TimeOut);
-FlagStatus WWDT_GetStatus (uint8_t Status);
-void WWDT_ClearStatusFlag (uint8_t flag);
-void WWDT_ClrTimeOutFlag (void);
-void WWDT_FeedStdSeq (void);
-void WWDT_Feed (void);
-uint32_t WWDT_GetCurrentCount(void);
-
-/**
- * @}
- */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __LPC_WWDT_H_ */
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_adc.c

@@ -1,326 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_adc.c           2011-06-02
-*//**
-* @file     lpc_adc.c
-* @brief    Contains all functions support for ADC firmware library on
-*           LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @addtogroup ADC
- * @{
- */
-#ifdef __BUILD_WITH_EXAMPLE__
-#include "lpc_libcfg.h"
-#else
-#include "lpc_libcfg_default.h"
-#endif /* __BUILD_WITH_EXAMPLE__ */
-#ifdef _ADC
- 
-/* Includes ------------------------------------------------------------------- */
-#include "lpc_types.h"
-#include "lpc_adc.h"
-#include "lpc_clkpwr.h"
-
-/* Public Functions ----------------------------------------------------------- */
-/** @addtogroup ADC_Public_Functions
- * @{
- */
-
-/*********************************************************************//**
- * @brief       Initial for ADC
- *                  + Set bit PCADC
- *                  + Set clock for ADC
- *                  + Set Clock Frequency
- * @param[in]   ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
- * @param[in]   rate ADC conversion rate, should be <=200KHz
- * @return      None
- **********************************************************************/
-void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate)
-{
-    uint32_t ADCPClk, temp, tmp;
-
-    // Turn on power and clock
-    CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCADC, ENABLE);
-
-    ADCx->CR = 0;
-
-    //Enable PDN bit
-    tmp = ADC_CR_PDN;
-
-    // Set clock frequency
-    ADCPClk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
-
-    /* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
-     * A/D converter, which should be less than or equal to 12.4MHz.
-     * A fully conversion requires 31 of these clocks.
-     * ADC clock = PCLK_ADC0 / (CLKDIV + 1);
-     * ADC rate = ADC clock / 31;
-     */
-    temp = rate * 31;
-    temp = (ADCPClk * 2 + temp)/(2 * temp) - 1; //get the round value by fomular: (2*A + B)/(2*A)
-    tmp |=  ADC_CR_CLKDIV(temp);
-
-    ADCx->CR = tmp;
-}
-
-
-/*********************************************************************//**
-* @brief        Close ADC
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @return       None
-**********************************************************************/
-void ADC_DeInit(LPC_ADC_TypeDef *ADCx)
-{
-    if (ADCx->CR & ADC_CR_START_MASK) //need to stop START bits before DeInit
-        ADCx->CR &= ~ADC_CR_START_MASK;
-     // Clear SEL bits
-     ADCx->CR &= ~0xFF;
-
-    // Clear PDN bit
-    ADCx->CR &= ~ADC_CR_PDN;
-    // Turn on power and clock
-    CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCADC, DISABLE);
-}
-
-
-/*********************************************************************//**
-* @brief        Get Result conversion from A/D data register
-* @param[in]    channel number which want to read back the result
-* @return       Result of conversion
-*********************************************************************/
-uint32_t ADC_GetData(uint32_t channel)
-{
-    uint32_t adc_value;
-
-    adc_value = *(uint32_t *)((&LPC_ADC->DR[0]) + channel);
-    return ADC_GDR_RESULT(adc_value);
-}
-
-/*********************************************************************//**
-* @brief        Set start mode for ADC
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    start_mode Start mode choose one of modes in
-*               'ADC_START_OPT' enumeration type definition, should be:
-*               - ADC_START_CONTINUOUS
-*               - ADC_START_NOW
-*               - ADC_START_ON_EINT0
-*               - ADC_START_ON_CAP01
-*               - ADC_START_ON_MAT01
-*               - ADC_START_ON_MAT03
-*               - ADC_START_ON_MAT10
-*               - ADC_START_ON_MAT11
-* @return       None
-*********************************************************************/
-void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode)
-{
-    ADCx->CR &= ~ADC_CR_START_MASK;
-    ADCx->CR |=ADC_CR_START_MODE_SEL((uint32_t)start_mode);
-}
-
-
-/*********************************************************************//**
-* @brief        ADC Burst mode setting
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    NewState
-*               -   1: Set Burst mode
-*               -   0: reset Burst mode
-* @return       None
-**********************************************************************/
-void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState)
-{
-    ADCx->CR &= ~ADC_CR_BURST;
-    if (NewState){
-        ADCx->CR |= ADC_CR_BURST;
-    }
-}
-
-/*********************************************************************//**
-* @brief        Set AD conversion in power mode
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    NewState
-*               -   1: AD converter is optional
-*               -   0: AD Converter is in power down mode
-* @return       None
-**********************************************************************/
-void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState)
-{
-    ADCx->CR &= ~ADC_CR_PDN;
-    if (NewState){
-        ADCx->CR |= ADC_CR_PDN;
-    }
-}
-
-/*********************************************************************//**
-* @brief        Set Edge start configuration
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    EdgeOption is ADC_START_ON_RISING and ADC_START_ON_FALLING
-*                   0:ADC_START_ON_RISING
-*                   1:ADC_START_ON_FALLING
-* @return       None
-**********************************************************************/
-void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption)
-{
-    ADCx->CR &= ~ADC_CR_EDGE;
-    if (EdgeOption){
-        ADCx->CR |= ADC_CR_EDGE;
-    }
-}
-
-/*********************************************************************//**
-* @brief        ADC interrupt configuration
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    IntType: type of interrupt, should be:
-*               - ADC_ADINTEN0: Interrupt channel 0
-*               - ADC_ADINTEN1: Interrupt channel 1
-*               ...
-*               - ADC_ADINTEN7: Interrupt channel 7
-*               - ADC_ADGINTEN: Individual channel/global flag done generate an interrupt
-* @param[in]    NewState:
-*                   - SET : enable ADC interrupt
-*                   - RESET: disable ADC interrupt
-* @return       None
-**********************************************************************/
-void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState)
-{
-    ADCx->INTEN &= ~ADC_INTEN_CH(IntType);
-    if (NewState){
-        ADCx->INTEN |= ADC_INTEN_CH(IntType);
-    }
-}
-
-/*********************************************************************//**
-* @brief        Enable/Disable ADC channel number
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    Channel channel number
-* @param[in]    NewState Enable or Disable
-*
-* @return       None
-**********************************************************************/
-void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState)
-{
-    if (NewState == ENABLE) {
-        ADCx->CR |= ADC_CR_CH_SEL(Channel);
-    } else {        
-        if (ADCx->CR & ADC_CR_START_MASK) //need to stop START bits before disable channel
-           ADCx->CR &= ~ADC_CR_START_MASK;
-        ADCx->CR &= ~ADC_CR_CH_SEL(Channel);
-    }
-}
-
-/*********************************************************************//**
-* @brief        Get ADC result
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    channel: channel number, should be 0...7
-* @return       Data conversion
-**********************************************************************/
-uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel)
-{
-    uint32_t adc_value;
-    adc_value = *(uint32_t *) ((&ADCx->DR[0]) + channel);
-    return ADC_DR_RESULT(adc_value);
-}
-
-/*********************************************************************//**
-* @brief        Get ADC Chanel status from ADC data register
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    channel: channel number, should be 0..7
-* @param[in]    StatusType
-*                       0:Burst status
-*                       1:Done  status
-* @return       SET / RESET
-**********************************************************************/
-FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType)
-{
-    uint32_t temp;
-    temp =  *(uint32_t *) ((&ADCx->DR[0]) + channel);
-    if (StatusType)
-    {
-        temp &= ADC_DR_DONE_FLAG;
-    }
-    else
-    {
-        temp &= ADC_DR_OVERRUN_FLAG;
-    }
-
-    if (temp)
-    {
-        return SET;
-    }
-    else
-    {
-        return RESET;
-    }
-
-}
-
-/*********************************************************************//**
-* @brief        Get ADC Data from AD Global register
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @return       Result of conversion
-**********************************************************************/
-uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx)
-{
-    return ((uint32_t)(ADCx->GDR));
-}
-
-/*********************************************************************//**
-* @brief        Get ADC Chanel status from AD global data register
-* @param[in]    ADCx pointer to LPC_ADC_TypeDef, should be: LPC_ADC
-* @param[in]    StatusType
-*                       0:Burst status
-*                       1:Done  status
-* @return       SET / RESET
-**********************************************************************/
-FlagStatus  ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType)
-{
-    uint32_t temp;
-
-    temp =  ADCx->GDR;
-    if (StatusType){
-        temp &= ADC_DR_DONE_FLAG;
-    }else{
-        temp &= ADC_DR_OVERRUN_FLAG;
-    }
-    if (temp){
-        return SET;
-    }else{
-        return RESET;
-    }
-}
-
-/**
- * @}
- */
-#endif /*_ADC*/
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */
-

bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_bod.c

@@ -1,119 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_bod.c           2011-12-09
-*//**
-* @file     lpc_bod.c
-* @brief    Contain functions related to BOD.
-* @version  1.0
-* @date     09 December. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-/* Peripheral group ----------------------------------------------------------- */
-/** @addtogroup BOD
- * @{
- */
-#ifdef __BUILD_WITH_EXAMPLE__
-#include "lpc_libcfg.h"
-#else
-#include "lpc_libcfg_default.h"
-#endif /* __BUILD_WITH_EXAMPLE__ */
-#ifdef _BOD
-#include "LPC407x_8x_177x_8x.h"         /* LPC407x_8x_177x_8x Peripheral Registers */
-#include "lpc_bod.h"
-
-/* Public Functions ----------------------------------------------------------- */
-/** @addtogroup BOD_Public_Functions
- * @{
- */
-/*********************************************************************//**
- * @brief       Initialize BOD control register
- * @param[in]   pConfig    BOD Configuration
- * @return      None
- **********************************************************************/
-void BOD_Init( BOD_Config_Type* pConfig )
-{
-  /* Turn on/off BOD. */
-  if(pConfig->Enabled == DISABLE)
-  {
-    LPC_SC->PCON |= BOD_PCON_BOGD;
-    return;
-  }
-  LPC_SC->PCON &= ~BOD_PCON_BOGD;
-
-  /* Brown-Out Reduced Power Mode */
-  if(pConfig->PowerReduced == ENABLE)
-  {
-       LPC_SC->PCON |= BOD_PCON_BODRPM;
-  }
-  else
-  {
-        LPC_SC->PCON &= ~BOD_PCON_BODRPM;
-  }
-
-  /* Brown-Out Reset */
-  if(pConfig->ResetOnVoltageDown == DISABLE)
-  {
-       LPC_SC->PCON |= BOD_PCON_BORD;
-  }
-  else
-  {
-        LPC_SC->PCON &= ~BOD_PCON_BORD;
-  }
-
-  /* Enable the BOD Interrupt */
-  NVIC_EnableIRQ(BOD_IRQn);
-
-  return;
-}
-
-
-/*********************************************************************//**
- * @brief       Get BOD reset source status
- * @param[in]   None
- * @return      TRUE/FALSE
- **********************************************************************/
-int32_t BOD_ResetSourceStatus( void )
-{
-   if((LPC_SC->RSID & BOD_RSID_POR) == 1)
-    return DISABLE;
-   return ((LPC_SC->RSID & BOD_RSID_BODR)? ENABLE:DISABLE);
-}
-/*********************************************************************//**
- * @brief       Clear BOD reset source bit
- * @param[in]   None
- * @return      None
- **********************************************************************/
-void BOD_ResetSourceClr( void )
-{
-   LPC_SC->RSID |= BOD_RSID_BODR;
-}
-/**
- * @}
- */
-#endif /*_BOD */
-/**
- * @}
- */
-/******************************************************************************
-**                            End Of File
-******************************************************************************/

bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_can.c

@@ -1,2197 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_can.c           2011-06-02
-*//**
-* @file     lpc_can.c
-* @brief    Contains all functions support for CAN firmware library on
-*           LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @addtogroup CAN
- * @{
- */
-#ifdef __BUILD_WITH_EXAMPLE__
-#include "lpc_libcfg.h"
-#else
-#include "lpc_libcfg_default.h"
-#endif /* __BUILD_WITH_EXAMPLE__ */
-#ifdef _CAN
- 
-/* Includes ------------------------------------------------------------------- */
-#include "lpc_can.h"
-#include "lpc_clkpwr.h"
-
-/* Private Variables ---------------------------------------------------------- */
-/** @defgroup CAN_Private_Variables CAN Private Variables
- * @{
- */
-
-FunctionalState FULLCAN_ENABLE;
-
-
-/* Counts number of filters (CAN message objects) used */
-uint16_t CANAF_FullCAN_cnt = 0;
-uint16_t CANAF_std_cnt = 0;
-uint16_t CANAF_gstd_cnt = 0;
-uint16_t CANAF_ext_cnt = 0;
-uint16_t CANAF_gext_cnt = 0;
-
-/* End of Private Variables ----------------------------------------------------*/
-/**
- * @}
- */
-
-/* Private Variables ---------------------------------------------------------- */
-static LPC_CAN_TypeDef* CAN_GetPointer (uint8_t canId);
-
-
-static void can_SetBaudrate (LPC_CAN_TypeDef *CANx, uint32_t baudrate);
-
-/*********************************************************************//**
- * @brief       Setting CAN baud rate (bps)
- * @param[in]   canId point to LPC_CAN_TypeDef object, should be:
- *              - LPC_CAN1: CAN1 peripheral
- *              - LPC_CAN2: CAN2 peripheral
- * @return      The pointer to CAN peripheral that's expected to use
- ***********************************************************************/
-static LPC_CAN_TypeDef* CAN_GetPointer (uint8_t canId)
-{
-    LPC_CAN_TypeDef* pCan;
-
-    switch (canId)
-    {
-        case CAN_ID_1:
-            pCan = LPC_CAN1;
-            break;
-
-        case CAN_ID_2:
-            pCan = LPC_CAN2;
-            break;
-
-        default:
-            pCan = NULL;
-            break;
-    }
-
-    return pCan;
-}
-
-
-/*********************************************************************//**
- * @brief       Setting CAN baud rate (bps)
- * @param[in]   CANx point to LPC_CAN_TypeDef object, should be:
- *              - LPC_CAN1: CAN1 peripheral
- *              - LPC_CAN2: CAN2 peripheral
- * @param[in]   baudrate: is the baud rate value will be set
- * @return      None
- ***********************************************************************/
-static void can_SetBaudrate (LPC_CAN_TypeDef *CANx, uint32_t baudrate)
-{
-    uint32_t result = 0;
-    uint8_t NT, TSEG1, TSEG2;
-    uint32_t CANPclk = 0;
-    uint32_t BRP;
-
-    CANPclk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
-
-    result = CANPclk / baudrate;
-
-    /* Calculate suitable nominal time value
-     * NT (nominal time) = (TSEG1 + TSEG2 + 3)
-     * NT <= 24
-     * TSEG1 >= 2*TSEG2
-     */
-    for(NT = 24; NT > 0; NT = NT-2)
-    {
-        if ((result%NT) == 0)
-        {
-            BRP = result / NT - 1;
-
-            NT--;
-
-            TSEG2 = (NT/3) - 1;
-
-            TSEG1 = NT -(NT/3) - 1;
-
-            break;
-        }
-    }
-
-    /* Enter reset mode */
-    CANx->MOD = 0x01;
-
-    /* Set bit timing
-     * Default: SAM = 0x00;
-     *          SJW = 0x03;
-     */
-    CANx->BTR = (TSEG2 << 20) | (TSEG1 << 16) | (3 << 14) | BRP;
-
-    /* Return to normal operating */
-    CANx->MOD = 0;
-}
-/* End of Private Functions ----------------------------------------------------*/
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @addtogroup CAN_Public_Functions
- * @{
- */
-
-/********************************************************************//**
- * @brief       Initialize CAN peripheral with given baudrate
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   baudrate: the value of CAN baudrate will be set (bps)
- * @return      None
- *********************************************************************/
-void CAN_Init(uint8_t canId, uint32_t baudrate)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    uint16_t i;
-
-    if(canId == CAN_ID_1)
-    {
-        /* Turn on power and clock for CAN1 */
-        CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, ENABLE);
-    }
-    else if(canId == CAN_ID_2)
-    {
-        /* Turn on power and clock for CAN2 */
-        CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, ENABLE);
-    }
-    else
-    {
-        return;
-    }
-
-    pCan->MOD = 1; // Enter Reset Mode
-    pCan->IER = 0; // Disable All CAN Interrupts
-    pCan->GSR = 0;
-
-    /* Request command to release Rx, Tx buffer and clear data overrun */
-    //pCan->CMR = CAN_CMR_AT | CAN_CMR_RRB | CAN_CMR_CDO;
-    pCan->CMR = (1 << 1) | (1 << 2) | (1 << 3);
-
-    /* Read to clear interrupt pending in interrupt capture register */
-    i = pCan->ICR;
-    pCan->MOD = 0;// Return Normal operating
-
-    //Reset CANAF value
-    LPC_CANAF->AFMR = 0x01;
-
-    //clear ALUT RAM
-    for (i = 0; i < 512; i++)
-    {
-        LPC_CANAF_RAM->mask[i] = 0x00;
-    }
-
-    LPC_CANAF->SFF_sa = 0x00;
-    LPC_CANAF->SFF_GRP_sa = 0x00;
-    LPC_CANAF->EFF_sa = 0x00;
-    LPC_CANAF->EFF_GRP_sa = 0x00;
-    LPC_CANAF->ENDofTable = 0x00;
-
-    LPC_CANAF->AFMR = 0x00;
-
-    /* Set baudrate */
-    can_SetBaudrate (pCan, baudrate);
-}
-
-/********************************************************************//**
- * @brief       CAN deInit
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @return      None
- *********************************************************************/
-void CAN_DeInit(uint8_t canId)
-{
-    if(canId == CAN_ID_1)
-    {
-        /* Turn on power and clock for CAN1 */
-        CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN1, DISABLE);
-    }
-    else if(canId == CAN_ID_2)
-    {
-        /* Turn on power and clock for CAN1 */
-        CLKPWR_ConfigPPWR(CLKPWR_PCONP_PCAN2, DISABLE);
-    }
-
-    return;
-}
-
-/********************************************************************//**
- * @brief       Setup Acceptance Filter Look-Up Table
- * @param[in]   CANAFx  pointer to LPC_CANAF_TypeDef
- *              Should be: LPC_CANAF
- * @param[in]   AFSection   the pointer to AF_SectionDef structure
- *              It contain information about 5 sections will be install in AFLUT
- * @return      CAN Error   could be:
- *              - CAN_OBJECTS_FULL_ERROR: No more rx or tx objects available
- *              - CAN_AF_ENTRY_ERROR: table error-violation of ascending numerical order
- *              - CAN_OK: ID is added into table successfully
- *********************************************************************/
-CAN_ERROR CAN_SetupAFLUT(AF_SectionDef* AFSection)
-{
-    uint8_t ctrl1,ctrl2;
-    uint8_t dis1, dis2;
-    uint16_t SID, ID_temp,i, count = 0;
-    uint32_t EID, entry, buf;
-    uint16_t lowerSID, upperSID;
-    uint32_t lowerEID, upperEID;
-
-    LPC_CANAF->AFMR = 0x01;
-
-    /***** setup FullCAN Table *****/
-    if(AFSection->FullCAN_Sec == NULL)
-    {
-        FULLCAN_ENABLE = DISABLE;
-    }
-    else
-    {
-        FULLCAN_ENABLE = ENABLE;
-
-        for(i = 0; i < (AFSection->FC_NumEntry); i++)
-        {
-            if(count + 1 > 64)
-            {
-                return CAN_OBJECTS_FULL_ERROR;
-            }
-
-            ctrl1 = AFSection->FullCAN_Sec->controller;
-
-            SID = AFSection->FullCAN_Sec->id_11;
-
-            dis1 = AFSection->FullCAN_Sec->disable;
-
-            entry = 0x00; //reset entry value
-
-            if((CANAF_FullCAN_cnt & 0x00000001)==0)
-            {
-                if(count != 0x00)
-                {
-                    buf = LPC_CANAF_RAM->mask[count-1];
-                    ID_temp = (buf & 0xE7FF); //mask controller & identifier bits
-                    if(ID_temp > ((ctrl1<<13)|SID))
-                    {
-                        return CAN_AF_ENTRY_ERROR;
-                    }
-                }
-
-                entry = (ctrl1<<29)|(dis1<<28)|(SID<<16)|(1<<27);
-
-                LPC_CANAF_RAM->mask[count] &= 0x0000FFFF;
-
-                LPC_CANAF_RAM->mask[count] |= entry;
-
-                CANAF_FullCAN_cnt++;
-                if(CANAF_FullCAN_cnt == AFSection->FC_NumEntry) //this is the lastest FullCAN entry
-                    count++;
-            }
-            else
-            {
-                buf = LPC_CANAF_RAM->mask[count];
-                ID_temp = (buf >>16) & 0xE7FF;
-                if(ID_temp > ((ctrl1<<13)|SID))
-                {
-                    return CAN_AF_ENTRY_ERROR;
-                }
-
-                entry = (ctrl1 << 13) | (dis1 << 12) | (SID << 0) | (1 << 11);
-
-                LPC_CANAF_RAM->mask[count] &= 0xFFFF0000;
-
-                LPC_CANAF_RAM->mask[count]|= entry;
-
-                count++;
-
-                CANAF_FullCAN_cnt++;
-            }
-
-            AFSection->FullCAN_Sec = (FullCAN_Entry *)((uint32_t)(AFSection->FullCAN_Sec)+ sizeof(FullCAN_Entry));
-        }
-    }
-
-    /***** Setup Explicit Standard Frame Format Section *****/
-    if(AFSection->SFF_Sec != NULL)
-    {
-        for(i=0;i<(AFSection->SFF_NumEntry);i++)
-        {
-            if(count + 1 > 512)
-            {
-                return CAN_OBJECTS_FULL_ERROR;
-            }
-
-            ctrl1 = AFSection->SFF_Sec->controller;
-
-            SID = AFSection->SFF_Sec->id_11;
-
-            dis1 = AFSection->SFF_Sec->disable;
-
-            entry = 0x00; //reset entry value
-
-            if((CANAF_std_cnt & 0x00000001)==0)
-            {
-                if(CANAF_std_cnt !=0 )
-                {
-                    buf = LPC_CANAF_RAM->mask[count-1];
-                    ID_temp = (buf & 0xE7FF); //mask controller & identifier bits
-                    if(ID_temp > ((ctrl1<<13)|SID))
-                    {
-                        return CAN_AF_ENTRY_ERROR;
-                    }
-                }
-
-                entry = (ctrl1<<29)|(dis1<<28)|(SID<<16);
-
-                LPC_CANAF_RAM->mask[count] &= 0x0000FFFF;
-
-                LPC_CANAF_RAM->mask[count] |= entry;
-
-                CANAF_std_cnt++;
-                if(CANAF_std_cnt == AFSection->SFF_NumEntry)//if this is the last SFF entry
-                    count++;
-            }
-            else
-            {
-                buf = LPC_CANAF_RAM->mask[count];
-                ID_temp = (buf >>16) & 0xE7FF;
-                if(ID_temp > ((ctrl1<<13)|SID))
-                {
-                    return CAN_AF_ENTRY_ERROR;
-                }
-
-                entry = (ctrl1 << 13) | (dis1 << 12) | (SID << 0);
-
-                LPC_CANAF_RAM->mask[count] &= 0xFFFF0000;
-
-                LPC_CANAF_RAM->mask[count] |= entry;
-
-                count++;
-
-                CANAF_std_cnt++;
-            }
-
-            AFSection->SFF_Sec = (SFF_Entry *)((uint32_t)(AFSection->SFF_Sec)+ sizeof(SFF_Entry));
-        }
-    }
-
-    /***** Setup Group of Standard Frame Format Identifier Section *****/
-    if(AFSection->SFF_GPR_Sec != NULL)
-    {
-        for(i=0;i<(AFSection->SFF_GPR_NumEntry);i++)
-        {
-            if(count + 1 > 512)
-            {
-                return CAN_OBJECTS_FULL_ERROR;
-            }
-
-            ctrl1 = AFSection->SFF_GPR_Sec->controller1;
-
-            ctrl2 = AFSection->SFF_GPR_Sec->controller2;
-
-            dis1 = AFSection->SFF_GPR_Sec->disable1;
-
-            dis2 = AFSection->SFF_GPR_Sec->disable2;
-
-            lowerSID = AFSection->SFF_GPR_Sec->lowerID;
-
-            upperSID = AFSection->SFF_GPR_Sec->upperID;
-
-            entry = 0x00;
-
-            if(CANAF_gstd_cnt!=0)
-            {
-                buf = LPC_CANAF_RAM->mask[count-1];
-                ID_temp = buf & 0xE7FF;
-                if((ctrl1 != ctrl2)||(lowerSID > upperSID)||(ID_temp > ((ctrl1<<13)|lowerSID)))
-                {
-                    return CAN_AF_ENTRY_ERROR;
-                }
-            }
-            entry = (ctrl1 << 29)|(dis1 << 28)|(lowerSID << 16)|  \
-                    (ctrl2 << 13)|(dis2 << 12)|(upperSID << 0);
-            LPC_CANAF_RAM->mask[count] = entry;
-
-            CANAF_gstd_cnt++;
-
-            count++;
-
-            AFSection->SFF_GPR_Sec = (SFF_GPR_Entry *)((uint32_t)(AFSection->SFF_GPR_Sec)+ sizeof(SFF_GPR_Entry));
-        }
-    }
-
-    /***** Setup Explicit Extend Frame Format Identifier Section *****/
-    if(AFSection->EFF_Sec != NULL)
-    {
-        for(i=0;i<(AFSection->EFF_NumEntry);i++)
-        {
-            if(count + 1 > 512)
-            {
-                return CAN_OBJECTS_FULL_ERROR;
-            }
-
-            EID = AFSection->EFF_Sec->ID_29;
-
-            ctrl1 = AFSection->EFF_Sec->controller;
-
-            entry = 0x00; //reset entry value
-
-            entry = (ctrl1 << 29)|(EID << 0);
-            if(CANAF_ext_cnt != 0)
-            {
-                buf = LPC_CANAF_RAM->mask[count-1];
-//              EID_temp = buf & 0x0FFFFFFF;
-                if(buf > entry)
-                {
-                    return CAN_AF_ENTRY_ERROR;
-                }
-            }
-            LPC_CANAF_RAM->mask[count] = entry;
-
-            CANAF_ext_cnt ++;
-
-            count++;
-
-            AFSection->EFF_Sec = (EFF_Entry *)((uint32_t)(AFSection->EFF_Sec)+ sizeof(EFF_Entry));
-        }
-    }
-
-    /***** Setup Group of Extended Frame Format Identifier Section *****/
-    if(AFSection->EFF_GPR_Sec != NULL)
-    {
-        for(i=0;i<(AFSection->EFF_GPR_NumEntry);i++)
-        {
-            if(count + 2 > 512)
-            {
-                return CAN_OBJECTS_FULL_ERROR;
-            }
-
-            ctrl1 = AFSection->EFF_GPR_Sec->controller1;
-
-            ctrl2 = AFSection->EFF_GPR_Sec->controller2;
-
-            lowerEID = AFSection->EFF_GPR_Sec->lowerEID;
-
-            upperEID = AFSection->EFF_GPR_Sec->upperEID;
-
-            entry = 0x00;
-
-            if(CANAF_gext_cnt != 0)
-            {
-                buf = LPC_CANAF_RAM->mask[count-1];
-//              EID_temp = buf & 0x0FFFFFFF;
-                if((ctrl1 != ctrl2) || (lowerEID > upperEID) || (buf > ((ctrl1 << 29)|(lowerEID << 0))))
-                {
-                    return CAN_AF_ENTRY_ERROR;
-                }
-            }
-
-            entry = (ctrl1 << 29)|(lowerEID << 0);
-
-            LPC_CANAF_RAM->mask[count++] = entry;
-
-            entry = (ctrl2 << 29)|(upperEID << 0);
-
-            LPC_CANAF_RAM->mask[count++] = entry;
-
-            CANAF_gext_cnt++;
-
-            AFSection->EFF_GPR_Sec = (EFF_GPR_Entry *)((uint32_t)(AFSection->EFF_GPR_Sec)+ sizeof(EFF_GPR_Entry));
-        }
-    }
-
-    //update address values
-    LPC_CANAF->SFF_sa = ((CANAF_FullCAN_cnt + 1)>>1)<<2;
-
-    LPC_CANAF->SFF_GRP_sa = LPC_CANAF->SFF_sa + (((CANAF_std_cnt+1)>>1)<< 2);
-
-    LPC_CANAF->EFF_sa = LPC_CANAF->SFF_GRP_sa + (CANAF_gstd_cnt << 2);
-
-    LPC_CANAF->EFF_GRP_sa = LPC_CANAF->EFF_sa + (CANAF_ext_cnt << 2);
-
-    LPC_CANAF->ENDofTable = LPC_CANAF->EFF_GRP_sa + (CANAF_gext_cnt << 3);
-
-    if(FULLCAN_ENABLE == DISABLE)
-    {
-        LPC_CANAF->AFMR = 0x00; // Normal mode
-    }
-    else
-    {
-        LPC_CANAF->AFMR = 0x04;
-    }
-
-    return CAN_OK;
-}
-/********************************************************************//**
- * @brief       Add Explicit ID into AF Look-Up Table dynamically.
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   id: The ID of entry will be added
- * @param[in]   format: is the type of ID Frame Format, should be:
- *              - STD_ID_FORMAT: 11-bit ID value
- *              - EXT_ID_FORMAT: 29-bit ID value
- * @return      CAN Error, could be:
- *              - CAN_OBJECTS_FULL_ERROR: No more rx or tx objects available
- *              - CAN_ID_EXIT_ERROR: ID exited in table
- *              - CAN_OK: ID is added into table successfully
- *********************************************************************/
-CAN_ERROR CAN_LoadExplicitEntry(uint8_t canId, uint32_t id, CAN_ID_FORMAT_Type format)
-{
-    uint32_t buf0 = 0, buf1 = 0;
-    int16_t cnt1 = 0, cnt2 = 0, bound1 = 0, total = 0;
-
-    /* Acceptance Filter Memory full - return */
-    total =((CANAF_FullCAN_cnt + 1) >> 1) + CANAF_FullCAN_cnt * 3 + ((CANAF_std_cnt + 1) >> 1)  \
-                + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt << 1);
-
-    if (total >= 512)
-    {
-        //don't have enough space
-        return CAN_OBJECTS_FULL_ERROR;
-    }
-
-    /* Setup Acceptance Filter Configuration
-    Acceptance Filter Mode Register = Off */
-    LPC_CANAF->AFMR = 0x00000001;
-
-    /*********** Add Explicit Standard Identifier Frame Format entry *********/
-    if(format == STD_ID_FORMAT)
-    {
-        id &= 0x07FF;
-
-        id |= canId << 13;/* Add controller number */
-
-        /* Move all remaining sections one place up
-        if new entry will increase FullCAN list */
-        if ((CANAF_std_cnt & 0x0001) == 0)
-        {
-            cnt1   = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1);
-
-            bound1 = total - cnt1;
-
-            buf0   = LPC_CANAF_RAM->mask[cnt1];
-
-            while(bound1--)
-            {
-                cnt1++;
-
-                buf1 = LPC_CANAF_RAM->mask[cnt1];
-
-                LPC_CANAF_RAM->mask[cnt1] = buf0;
-
-                buf0 = buf1;
-            }
-        }
-
-        if (CANAF_std_cnt == 0)
-        {
-            cnt2 = (CANAF_FullCAN_cnt + 1)>>1;
-
-            /* For entering first ID */
-            LPC_CANAF_RAM->mask[cnt2] = 0x0000FFFF | (id << 16);
-        }
-        else if (CANAF_std_cnt == 1)
-        {
-            cnt2 = (CANAF_FullCAN_cnt + 1) >> 1;
-
-            /* For entering second ID */
-            if (((LPC_CANAF_RAM->mask[cnt2] >> 16)& 0xE7FF) > id)
-            {
-                LPC_CANAF_RAM->mask[cnt2] = (LPC_CANAF_RAM->mask[cnt2] >> 16) | (id << 16);
-            }
-            else
-            {
-                LPC_CANAF_RAM->mask[cnt2] = (LPC_CANAF_RAM->mask[cnt2] & 0xFFFF0000) | id;
-            }
-        }
-        else
-        {
-            /* Find where to insert new ID */
-            cnt1 = (CANAF_FullCAN_cnt+1)>>1;
-
-            cnt2 = CANAF_std_cnt;
-
-            bound1 = ((CANAF_FullCAN_cnt+1)>>1)+((CANAF_std_cnt+1)>>1);
-
-            while (cnt1 < bound1)
-            {
-                /* Loop through standard existing IDs */
-                if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > id)
-                {
-                    cnt2 = cnt1 * 2;
-                    break;
-                }
-
-                if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > id)
-                {
-                    cnt2 = cnt1 * 2 + 1;
-                    break;
-                }
-
-                cnt1++;
-            }
-
-            /* cnt1 = U32 where to insert new ID */
-            /* cnt2 = U16 where to insert new ID */
-
-            if (cnt1 == bound1)
-            {
-                /* Adding ID as last entry */
-                /* Even number of IDs exists */
-                if ((CANAF_std_cnt & 0x0001) == 0)
-                {
-                    LPC_CANAF_RAM->mask[cnt1]  = 0x0000FFFF | (id << 16);
-                }
-                /* Odd  number of IDs exists */
-                else
-                {
-                    LPC_CANAF_RAM->mask[cnt1]  = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id;
-                }
-            }
-            else
-            {
-                buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
-
-                if ((cnt2 & 0x0001) == 0)
-                {
-                    /* Insert new mask to even address*/
-                    buf1 = (id << 16) | (buf0 >> 16);
-                }
-                else
-                {
-                    /* Insert new mask to odd  address */
-                    buf1 = (buf0 & 0xFFFF0000) | id;
-                }
-
-                LPC_CANAF_RAM->mask[cnt1] = buf1;/* Insert mask */
-
-                bound1 = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt+1) >> 1) - 1;
-
-                /* Move all remaining standard mask entries one place up */
-                while (cnt1 < bound1)
-                {
-                    cnt1++;
-
-                    buf1  = LPC_CANAF_RAM->mask[cnt1];
-
-                    LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16);
-
-                    buf0  = buf1;
-                }
-
-                if ((CANAF_std_cnt & 0x0001) == 0)
-                {
-                    /* Even number of IDs exists */
-                    LPC_CANAF_RAM->mask[cnt1+1] = (buf0 <<16) |(0x0000FFFF);
-                }
-            }
-        }
-
-        CANAF_std_cnt++;
-
-        //update address values
-        LPC_CANAF->SFF_GRP_sa += 0x04 ;
-
-        LPC_CANAF->EFF_sa     += 0x04 ;
-
-        LPC_CANAF->EFF_GRP_sa += 0x04;
-
-        LPC_CANAF->ENDofTable += 0x04;
-    }
-
-    /*********** Add Explicit Extended Identifier Frame Format entry *********/
-    else
-    {
-        /* Add controller number */
-        id |= canId << 29;
-
-        cnt1 = ((CANAF_FullCAN_cnt+1) >> 1) + (((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt);
-
-        cnt2 = 0;
-
-        while (cnt2 < CANAF_ext_cnt)
-        {
-            /* Loop through extended existing masks*/
-            if (LPC_CANAF_RAM->mask[cnt1] > id)
-            {
-                break;
-            }
-
-            cnt1++;/* cnt1 = U32 where to insert new mask */
-
-            cnt2++;
-        }
-
-        buf0 = LPC_CANAF_RAM->mask[cnt1];  /* Remember current entry */
-
-        LPC_CANAF_RAM->mask[cnt1] = id;    /* Insert mask */
-
-        CANAF_ext_cnt++;
-
-        bound1 = total;
-
-        /* Move all remaining extended mask entries one place up*/
-        while (cnt2 < bound1)
-        {
-            cnt1++;
-
-            cnt2++;
-
-            buf1 = LPC_CANAF_RAM->mask[cnt1];
-
-            LPC_CANAF_RAM->mask[cnt1] = buf0;
-
-            buf0 = buf1;
-        }
-
-        /* update address values */
-        LPC_CANAF->EFF_GRP_sa += 4;
-
-        LPC_CANAF->ENDofTable += 4;
-    }
-
-    if(CANAF_FullCAN_cnt == 0) //not use FullCAN mode
-    {
-        LPC_CANAF->AFMR = 0x00;//not use FullCAN mode
-    }
-    else
-    {
-        LPC_CANAF->AFMR = 0x04;
-    }
-
-    return CAN_OK;
-}
-
-/********************************************************************//**
- * @brief       Load FullCAN entry into AFLUT
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   id: identifier of entry that will be added
- * @return      CAN_ERROR, could be:
- *              - CAN_OK: loading is successful
- *              - CAN_ID_EXIT_ERROR: ID exited in FullCAN Section
- *              - CAN_OBJECTS_FULL_ERROR: no more space available
- *********************************************************************/
-CAN_ERROR CAN_LoadFullCANEntry (uint8_t canId, uint16_t id)
-{
-    uint32_t buf0 = 0, buf1 = 0, buf2 = 0;
-    uint32_t tmp0 = 0, tmp1 = 0, tmp2 = 0;
-    int16_t cnt1 = 0, cnt2 = 0, bound1 = 0, total = 0;
-
-    /* Acceptance Filter Memory full - return */
-    total =((CANAF_FullCAN_cnt + 1) >> 1) + CANAF_FullCAN_cnt*3 + ((CANAF_std_cnt + 1) >> 1)  \
-                + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt << 1);
-
-    //don't have enough space for this fullCAN Entry and its Object(3*32 bytes)
-    if ((total >= 508) || (CANAF_FullCAN_cnt >= 64))
-    {
-        return CAN_OBJECTS_FULL_ERROR;
-    }
-
-    /* Setup Acceptance Filter Configuration
-    Acceptance Filter Mode Register = Off */
-    LPC_CANAF->AFMR = 0x00000001;
-
-    /* Add mask for standard identifiers   */
-    id &= 0x07FF;
-
-    id |= (canId << 13) | (1 << 11);
-
-    /* Move all remaining sections one place up
-    if new entry will increase FullCAN list */
-    if (((CANAF_FullCAN_cnt & 0x0001) == 0)&&(total!=0))
-    {
-        //then remove remaining section
-        cnt1   = (CANAF_FullCAN_cnt >> 1);
-
-        bound1 = total;
-
-        buf0   = LPC_CANAF_RAM->mask[cnt1];
-
-        while (bound1--)
-        {
-            cnt1++;
-
-            buf1 = LPC_CANAF_RAM->mask[cnt1];
-
-            LPC_CANAF_RAM->mask[cnt1] = buf0;
-
-            buf0 = buf1;
-        }
-    }
-    if (CANAF_FullCAN_cnt == 0)
-    {
-        /* For entering first ID */
-        LPC_CANAF_RAM->mask[0] = 0x0000FFFF | (id << 16);
-    }
-    else if (CANAF_FullCAN_cnt == 1)
-    {
-        /* For entering second ID */
-        if (((LPC_CANAF_RAM->mask[0] >> 16)& 0xE7FF) > id)
-        {
-            LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] >> 16) | (id << 16);
-        }
-        else
-        {
-            LPC_CANAF_RAM->mask[0] = (LPC_CANAF_RAM->mask[0] & 0xFFFF0000) | id;
-        }
-    }
-    else
-    {
-        /* Find where to insert new ID */
-        cnt1 = 0;
-
-        cnt2 = CANAF_FullCAN_cnt;
-
-        bound1 = (CANAF_FullCAN_cnt - 1) >> 1;
-
-        while (cnt1 <= bound1)
-        {
-            /* Loop through standard existing IDs */
-            if (((LPC_CANAF_RAM->mask[cnt1] >> 16) & 0xE7FF) > (id & 0xE7FF))
-            {
-                cnt2 = cnt1 * 2;
-                break;
-            }
-
-
-            if ((LPC_CANAF_RAM->mask[cnt1] & 0x0000E7FF) > (id & 0xE7FF))
-            {
-                cnt2 = cnt1 * 2 + 1;
-                break;
-            }
-
-            cnt1++;
-        }
-        /* cnt1 = U32 where to insert new ID */
-        /* cnt2 = U16 where to insert new ID */
-
-        if (cnt1 > bound1)
-        {
-            /* Adding ID as last entry */
-            /* Even number of IDs exists */
-            if ((CANAF_FullCAN_cnt & 0x0001) == 0)
-            {
-                LPC_CANAF_RAM->mask[cnt1]  = 0x0000FFFF | (id << 16);
-            }
-            /* Odd  number of IDs exists */
-            else
-            {
-                LPC_CANAF_RAM->mask[cnt1]  = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000) | id;
-            }
-        }
-        else
-        {
-            buf0 = LPC_CANAF_RAM->mask[cnt1]; /* Remember current entry */
-
-            if ((cnt2 & 0x0001) == 0)
-            {
-                /* Insert new mask to even address*/
-                buf1 = (id << 16) | (buf0 >> 16);
-            }
-            else
-            {
-                /* Insert new mask to odd  address */
-                buf1 = (buf0 & 0xFFFF0000) | id;
-            }
-
-            LPC_CANAF_RAM->mask[cnt1] = buf1;/* Insert mask */
-
-            bound1 = CANAF_FullCAN_cnt >> 1;
-
-            /* Move all remaining standard mask entries one place up */
-            while (cnt1 < bound1)
-            {
-                cnt1++;
-
-                buf1  = LPC_CANAF_RAM->mask[cnt1];
-
-                LPC_CANAF_RAM->mask[cnt1] = (buf1 >> 16) | (buf0 << 16);
-
-                buf0  = buf1;
-            }
-
-            if ((CANAF_FullCAN_cnt & 0x0001) == 0)
-            {
-                /* Even number of IDs exists */
-                LPC_CANAF_RAM->mask[cnt1] = (LPC_CANAF_RAM->mask[cnt1] & 0xFFFF0000)
-                                            | (0x0000FFFF);
-            }
-        }
-    }
-
-    //restruct FulCAN Object Section
-    bound1 = CANAF_FullCAN_cnt - cnt2;
-
-    cnt1 = total - (CANAF_FullCAN_cnt)*3 + cnt2*3 + 1;
-
-    buf0 = LPC_CANAF_RAM->mask[cnt1];
-
-    buf1 = LPC_CANAF_RAM->mask[cnt1+1];
-
-    buf2 = LPC_CANAF_RAM->mask[cnt1+2];
-
-    LPC_CANAF_RAM->mask[cnt1]=LPC_CANAF_RAM->mask[cnt1+1]= LPC_CANAF_RAM->mask[cnt1+2]=0x00;
-
-    cnt1+=3;
-
-    while(bound1--)
-    {
-        tmp0 = LPC_CANAF_RAM->mask[cnt1];
-
-        tmp1 = LPC_CANAF_RAM->mask[cnt1+1];
-
-        tmp2 = LPC_CANAF_RAM->mask[cnt1+2];
-
-        LPC_CANAF_RAM->mask[cnt1]= buf0;
-
-        LPC_CANAF_RAM->mask[cnt1+1]= buf1;
-
-        LPC_CANAF_RAM->mask[cnt1+2]= buf2;
-
-        buf0 = tmp0;
-
-        buf1 = tmp1;
-
-        buf2 = tmp2;
-
-        cnt1+=3;
-    }
-
-    CANAF_FullCAN_cnt++;
-
-    //update address values
-    LPC_CANAF->SFF_sa     += 0x04;
-
-    LPC_CANAF->SFF_GRP_sa += 0x04 ;
-
-    LPC_CANAF->EFF_sa     += 0x04 ;
-
-    LPC_CANAF->EFF_GRP_sa += 0x04;
-
-    LPC_CANAF->ENDofTable += 0x04;
-
-    LPC_CANAF->AFMR = 0x04;
-
-    return CAN_OK;
-}
-
-/********************************************************************//**
- * @brief       Load Group entry into AFLUT
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   lowerID, upperID: lower and upper identifier of entry
- * @param[in]   format: type of ID format, should be:
- *              - STD_ID_FORMAT: Standard ID format (11-bit value)
- *              - EXT_ID_FORMAT: Extended ID format (29-bit value)
- * @return      CAN_ERROR, could be:
- *              - CAN_OK: loading is successful
- *              - CAN_CONFLICT_ID_ERROR: Conflict ID occurs
- *              - CAN_OBJECTS_FULL_ERROR: no more space available
- *********************************************************************/
-CAN_ERROR CAN_LoadGroupEntry(uint8_t canId, uint32_t lowerID,
-                                        uint32_t upperID, CAN_ID_FORMAT_Type format)
-{
-    uint32_t buf0, buf1, entry1, entry2, LID,UID;
-    int16_t cnt1, bound1, total;
-
-    if(lowerID > upperID)
-        return CAN_CONFLICT_ID_ERROR;
-
-    total =((CANAF_FullCAN_cnt+1) >> 1)+ CANAF_FullCAN_cnt*3 +((CANAF_std_cnt + 1) >> 1)  \
-                + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
-
-    /* Setup Acceptance Filter Configuration
-    Acceptance Filter Mode Register = Off */
-    LPC_CANAF->AFMR = 0x00000001;
-
-    /*********Add Group of Standard Identifier Frame Format************/
-    if(format == STD_ID_FORMAT)
-    {
-        if ((total >= 512))
-        {
-            //don't have enough space
-            return CAN_OBJECTS_FULL_ERROR;
-        }
-
-        lowerID &=0x7FF; //mask ID
-
-        upperID &=0x7FF;
-
-        entry1  = (canId << 29) | (lowerID << 16) | (canId << 13)|(upperID << 0);
-
-        cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1);
-
-        //if this is the first Group standard ID entry
-        if(CANAF_gstd_cnt == 0)
-        {
-            LPC_CANAF_RAM->mask[cnt1] = entry1;
-        }
-        else
-        {
-            //find the position to add new Group entry
-            bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt;
-
-            while(cnt1 < bound1)
-            {
-                //compare controller first
-                while((LPC_CANAF_RAM->mask[cnt1] >> 29)< (entry1 >> 29))//increase until meet greater or equal controller
-                    cnt1++;
-                buf0 = LPC_CANAF_RAM->mask[cnt1];
-                if((LPC_CANAF_RAM->mask[cnt1] >> 29)> (entry1 >> 29)) //meet greater controller
-                {
-                    //add at this position
-                    LPC_CANAF_RAM->mask[cnt1] = entry1;
-                    break;
-                }
-                else //meet equal controller
-                {
-                    LID  = (buf0 >> 16)&0x7FF;
-                    UID  = buf0 & 0x7FF;
-                    if (upperID <= LID)
-                    {
-                        //add new entry before this entry
-                        LPC_CANAF_RAM->mask[cnt1] = entry1;
-                        break;
-                    }
-                    else if (lowerID >= UID)
-                    {
-                        //load next entry to compare
-                        cnt1 ++;
-                    }
-                    else
-                        return CAN_CONFLICT_ID_ERROR;
-                }
-            }
-            if(cnt1 >= bound1)
-            {
-                //add new entry at the last position in this list
-                buf0 = LPC_CANAF_RAM->mask[cnt1];
-
-                LPC_CANAF_RAM->mask[cnt1] = entry1;
-            }
-
-            //remove all remaining entry of this section one place up
-            bound1 = total - cnt1;
-
-            while(bound1--)
-            {
-                cnt1++;
-
-                buf1 = LPC_CANAF_RAM->mask[cnt1];
-
-                LPC_CANAF_RAM->mask[cnt1] = buf0;
-
-                buf0 = buf1;
-            }
-        }
-
-        CANAF_gstd_cnt++;
-
-        //update address values
-        LPC_CANAF->EFF_sa     +=0x04 ;
-
-        LPC_CANAF->EFF_GRP_sa +=0x04;
-
-        LPC_CANAF->ENDofTable +=0x04;
-    }
-
-
-    /*********Add Group of Extended Identifier Frame Format************/
-    else
-    {
-        if ((total >= 511))
-        {
-            //don't have enough space
-            return CAN_OBJECTS_FULL_ERROR;
-        }
-
-        lowerID  &= 0x1FFFFFFF; //mask ID
-
-        upperID &= 0x1FFFFFFF;
-
-        entry1   = (canId << 29)|(lowerID << 0);
-
-        entry2   = (canId << 29)|(upperID << 0);
-
-        cnt1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt + CANAF_ext_cnt;
-
-        //if this is the first Group standard ID entry
-        if(CANAF_gext_cnt == 0)
-        {
-            LPC_CANAF_RAM->mask[cnt1] = entry1;
-
-            LPC_CANAF_RAM->mask[cnt1+1] = entry2;
-        }
-        else
-        {
-            //find the position to add new Group entry
-            bound1 = ((CANAF_FullCAN_cnt+1)>>1) + ((CANAF_std_cnt + 1) >> 1) + CANAF_gstd_cnt \
-                        + CANAF_ext_cnt + (CANAF_gext_cnt<<1);
-
-            while(cnt1 < bound1)
-            {
-                while((LPC_CANAF_RAM->mask[cnt1] >>29)< canId) //increase until meet greater or equal controller
-                    cnt1++;
-                buf0 = LPC_CANAF_RAM->mask[cnt1];
-
-                buf1 = LPC_CANAF_RAM->mask[cnt1+1];
-                if((LPC_CANAF_RAM->mask[cnt1] >> 29)> canId) //meet greater controller
-                {
-                    //add at this position
-                    LPC_CANAF_RAM->mask[cnt1] = entry1;
-                    LPC_CANAF_RAM->mask[++cnt1] = entry2;
-                    break;
-                }
-                else //meet equal controller
-                {
-                    LID  = buf0 & 0x1FFFFFFF; //mask ID
-                    UID  = buf1 & 0x1FFFFFFF;
-                    if (upperID <= LID)
-                    {
-                        //add new entry before this entry
-                        LPC_CANAF_RAM->mask[cnt1] = entry1;
-                        LPC_CANAF_RAM->mask[++cnt1] = entry2;
-                        break;
-                    }
-                    else if (lowerID >= UID)
-                    {
-                        //load next entry to compare
-                        cnt1 +=2;
-                    }
-                    else
-                        return CAN_CONFLICT_ID_ERROR;
-                }
-            }
-            if(cnt1 >= bound1)
-            {
-                //add new entry at the last position in this list
-                buf0 = LPC_CANAF_RAM->mask[cnt1];
-
-                buf1 = LPC_CANAF_RAM->mask[cnt1+1];
-
-                LPC_CANAF_RAM->mask[cnt1]   = entry1;
-
-                LPC_CANAF_RAM->mask[++cnt1] = entry2;
-            }
-
-            //remove all remaining entry of this section two place up
-            bound1 = total - cnt1 + 1;
-
-            cnt1++;
-
-            while(bound1>0)
-            {
-                entry1 = LPC_CANAF_RAM->mask[cnt1];
-
-                entry2 = LPC_CANAF_RAM->mask[cnt1+1];
-
-                LPC_CANAF_RAM->mask[cnt1]   = buf0;
-
-                LPC_CANAF_RAM->mask[cnt1+1] = buf1;
-
-                buf0 = entry1;
-
-                buf1 = entry2;
-
-                cnt1   +=2;
-
-                bound1 -=2;
-            }
-        }
-
-        CANAF_gext_cnt++;
-
-        //update address values
-        LPC_CANAF->ENDofTable +=0x08;
-    }
-
-    LPC_CANAF->AFMR = 0x04;
-
-    return CAN_OK;
-}
-
-/********************************************************************//**
- * @brief       Remove AFLUT entry (FullCAN entry and Explicit Standard entry)
- * @param[in]   EntryType: the type of entry that want to remove, should be:
- *              - FULLCAN_ENTRY
- *              - EXPLICIT_STANDARD_ENTRY
- *              - GROUP_STANDARD_ENTRY
- *              - EXPLICIT_EXTEND_ENTRY
- *              - GROUP_EXTEND_ENTRY
- * @param[in]   position: the position of this entry in its section
- * Note: the first position is 0
- * @return      CAN_ERROR, could be:
- *              - CAN_OK: removing is successful
- *              - CAN_ENTRY_NOT_EXIT_ERROR: entry want to remove is not exit
- *********************************************************************/
-CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position)
-{
-    uint16_t cnt, bound, total;
-    uint32_t buf0, buf1;
-
-    /* Setup Acceptance Filter Configuration
-    Acceptance Filter Mode Register = Off */
-    LPC_CANAF->AFMR = 0x00000001;
-
-    total = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt + 1) >> 1) + \
-                    + CANAF_gstd_cnt + CANAF_ext_cnt + (CANAF_gext_cnt << 1);
-
-
-    /************** Remove FullCAN Entry *************/
-    if(EntryType == FULLCAN_ENTRY)
-    {
-        if((CANAF_FullCAN_cnt == 0)||(position >= CANAF_FullCAN_cnt))
-        {
-            return CAN_ENTRY_NOT_EXIT_ERROR;
-        }
-        else
-        {
-            cnt = position >> 1;
-
-            buf0 = LPC_CANAF_RAM->mask[cnt];
-
-            bound = (CANAF_FullCAN_cnt - position -1)>>1;
-
-            if((position & 0x0001) == 0) //event position
-            {
-                while(bound--)
-                {
-                    //remove all remaining FullCAN entry one place down
-                    buf1  = LPC_CANAF_RAM->mask[cnt+1];
-
-                    LPC_CANAF_RAM->mask[cnt] = (buf1 >> 16) | (buf0 << 16);
-
-                    buf0  = buf1;
-
-                    cnt++;
-                }
-            }
-            else //odd position
-            {
-                while(bound--)
-                {
-                    //remove all remaining FullCAN entry one place down
-                    buf1  = LPC_CANAF_RAM->mask[cnt+1];
-
-                    LPC_CANAF_RAM->mask[cnt] = (buf0 & 0xFFFF0000)|(buf1 >> 16);
-
-                    LPC_CANAF_RAM->mask[cnt+1] = LPC_CANAF_RAM->mask[cnt+1] << 16;
-
-                    buf0  = buf1<<16;
-
-                    cnt++;
-                }
-            }
-            if((CANAF_FullCAN_cnt & 0x0001) == 0)
-            {
-                if((position & 0x0001)==0)
-                    LPC_CANAF_RAM->mask[cnt] = (buf0 << 16) | (0x0000FFFF);
-                else
-                    LPC_CANAF_RAM->mask[cnt] = buf0 | 0x0000FFFF;
-            }
-            else
-            {
-                //remove all remaining section one place down
-                cnt = (CANAF_FullCAN_cnt + 1)>>1;
-
-                bound = total + CANAF_FullCAN_cnt * 3;
-
-                while(bound>cnt)
-                {
-                    LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt];
-                    cnt++;
-                }
-
-                LPC_CANAF_RAM->mask[cnt-1]=0x00;
-
-                //update address values
-                LPC_CANAF->SFF_sa     -= 0x04;
-
-                LPC_CANAF->SFF_GRP_sa -= 0x04 ;
-
-                LPC_CANAF->EFF_sa     -= 0x04 ;
-
-                LPC_CANAF->EFF_GRP_sa -= 0x04;
-
-                LPC_CANAF->ENDofTable -= 0x04;
-            }
-
-            CANAF_FullCAN_cnt--;
-
-            //delete its FullCAN Object in the FullCAN Object section
-            //remove all remaining FullCAN Object three place down
-            cnt = total + position * 3;
-
-            bound = (CANAF_FullCAN_cnt - position + 1) * 3;
-
-            while(bound)
-            {
-                LPC_CANAF_RAM->mask[cnt]= LPC_CANAF_RAM->mask[cnt+3];;
-
-                LPC_CANAF_RAM->mask[cnt+1]= LPC_CANAF_RAM->mask[cnt+4];
-
-                LPC_CANAF_RAM->mask[cnt+2]= LPC_CANAF_RAM->mask[cnt+5];
-
-                bound -= 3;
-
-                cnt   += 3;
-            }
-        }
-    }
-
-    /************** Remove Explicit Standard ID Entry *************/
-    else if(EntryType == EXPLICIT_STANDARD_ENTRY)
-    {
-        if((CANAF_std_cnt == 0)||(position >= CANAF_std_cnt))
-        {
-            return CAN_ENTRY_NOT_EXIT_ERROR;
-        }
-        else
-        {
-            cnt = ((CANAF_FullCAN_cnt+1) >> 1) + (position >> 1);
-
-            buf0 = LPC_CANAF_RAM->mask[cnt];
-
-            bound = (CANAF_std_cnt - position - 1) >> 1;
-
-            if((position & 0x0001) == 0) //event position
-            {
-                while(bound--)
-                {
-                    //remove all remaining FullCAN entry one place down
-                    buf1  = LPC_CANAF_RAM->mask[cnt + 1];
-
-                    LPC_CANAF_RAM->mask[cnt] = (buf1 >> 16) | (buf0 << 16);
-
-                    buf0  = buf1;
-
-                    cnt++;
-                }
-            }
-            else //odd position
-            {
-                while(bound--)
-                {
-                    //remove all remaining FullCAN entry one place down
-                    buf1  = LPC_CANAF_RAM->mask[cnt + 1];
-
-                    LPC_CANAF_RAM->mask[cnt] = (buf0 & 0xFFFF0000) | (buf1 >> 16);
-
-                    LPC_CANAF_RAM->mask[cnt + 1] = LPC_CANAF_RAM->mask[cnt + 1] << 16;
-
-                    buf0  = buf1<<16;
-
-                    cnt++;
-                }
-            }
-            if((CANAF_std_cnt & 0x0001) == 0)
-            {
-                if((position & 0x0001)==0)
-                    LPC_CANAF_RAM->mask[cnt] = (buf0 << 16) | (0x0000FFFF);
-                else
-                    LPC_CANAF_RAM->mask[cnt] = buf0 | 0x0000FFFF;
-            }
-            else
-            {
-                //remove all remaining section one place down
-                cnt = ((CANAF_FullCAN_cnt + 1)>>1) + ((CANAF_std_cnt + 1) >> 1);
-
-                bound = total + CANAF_FullCAN_cnt * 3;
-
-                while(bound>cnt)
-                {
-                    LPC_CANAF_RAM->mask[cnt-1] = LPC_CANAF_RAM->mask[cnt];
-                    cnt++;
-                }
-
-                LPC_CANAF_RAM->mask[cnt-1]=0x00;
-
-                //update address value
-                LPC_CANAF->SFF_GRP_sa -= 0x04 ;
-
-                LPC_CANAF->EFF_sa     -= 0x04 ;
-
-                LPC_CANAF->EFF_GRP_sa -= 0x04;
-
-                LPC_CANAF->ENDofTable -= 0x04;
-            }
-
-            CANAF_std_cnt--;
-        }
-    }
-
-    /************** Remove Group of Standard ID Entry *************/
-    else if(EntryType == GROUP_STANDARD_ENTRY)
-    {
-        if((CANAF_gstd_cnt == 0)||(position >= CANAF_gstd_cnt))
-        {
-            return CAN_ENTRY_NOT_EXIT_ERROR;
-        }
-        else
-        {
-            cnt = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt + 1) >> 1)+ position + 1;
-
-            bound = total + CANAF_FullCAN_cnt * 3;
-
-            while (cnt < bound)
-            {
-                LPC_CANAF_RAM->mask[cnt - 1] = LPC_CANAF_RAM->mask[cnt];
-                cnt++;
-            }
-            LPC_CANAF_RAM->mask[cnt - 1]=0x00;
-        }
-
-        CANAF_gstd_cnt--;
-
-        //update address value
-        LPC_CANAF->EFF_sa     -= 0x04;
-
-        LPC_CANAF->EFF_GRP_sa -= 0x04;
-
-        LPC_CANAF->ENDofTable -= 0x04;
-    }
-
-    /************** Remove Explicit Extended ID Entry *************/
-    else if(EntryType == EXPLICIT_EXTEND_ENTRY)
-    {
-        if((CANAF_ext_cnt == 0)||(position >= CANAF_ext_cnt))
-        {
-            return CAN_ENTRY_NOT_EXIT_ERROR;
-        }
-        else
-        {
-            cnt = ((CANAF_FullCAN_cnt + 1) >> 1) + ((CANAF_std_cnt + 1) >> 1)+ CANAF_gstd_cnt + position + 1;
-
-            bound = total + CANAF_FullCAN_cnt * 3;
-
-            while (cnt<bound)
-            {
-                LPC_CANAF_RAM->mask[cnt - 1] = LPC_CANAF_RAM->mask[cnt];
-                cnt++;
-            }
-            LPC_CANAF_RAM->mask[cnt - 1]=0x00;
-        }
-
-        CANAF_ext_cnt--;
-
-        LPC_CANAF->EFF_GRP_sa -= 0x04;
-
-        LPC_CANAF->ENDofTable -= 0x04;
-    }
-
-    /************** Remove Group of Extended ID Entry *************/
-    else
-    {
-        if((CANAF_gext_cnt == 0)||(position >= CANAF_gext_cnt))
-        {
-            return CAN_ENTRY_NOT_EXIT_ERROR;
-        }
-        else
-        {
-            cnt = total - (CANAF_gext_cnt << 1) + (position << 1);
-
-            bound = total + CANAF_FullCAN_cnt * 3;
-
-            while (cnt<bound)
-            {
-                //remove all remaining entry two place up
-                LPC_CANAF_RAM->mask[cnt] = LPC_CANAF_RAM->mask[cnt + 2];
-
-                LPC_CANAF_RAM->mask[cnt + 1] = LPC_CANAF_RAM->mask[cnt + 3];
-
-                cnt += 2;
-            }
-        }
-
-        CANAF_gext_cnt--;
-
-        LPC_CANAF->ENDofTable -= 0x08;
-    }
-
-    LPC_CANAF->AFMR = 0x04;
-
-    return CAN_OK;
-}
-
-/********************************************************************//**
- * @brief       Send message data
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   CAN_Msg point to the CAN_MSG_Type Structure, it contains message
- *              information such as: ID, DLC, RTR, ID Format
- * @return      Status:
- *              - SUCCESS: send message successfully
- *              - ERROR: send message unsuccessfully
- *********************************************************************/
-Status CAN_SendMsg (uint8_t canId, CAN_MSG_Type *CAN_Msg)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    uint32_t data;
-
-    //Check status of Transmit Buffer 1
-    if (pCan->SR & (1 << 2))
-    {
-        /* Transmit Channel 1 is available */
-        /* Write frame informations and frame data into its CANxTFI1,
-         * CANxTID1, CANxTDA1, CANxTDB1 register */
-        pCan->TFI1 &= ~ 0x000F0000;
-
-        pCan->TFI1 |= (CAN_Msg->len) << 16;
-
-        if(CAN_Msg->type == REMOTE_FRAME)
-        {
-            pCan->TFI1 |= (1 << 30); //set bit RTR
-        }
-        else
-        {
-            pCan->TFI1 &= ~(1 << 30);
-        }
-
-        if(CAN_Msg->format == EXT_ID_FORMAT)
-        {
-            pCan->TFI1 |= (((uint32_t)1) << 31); //set bit FF
-        }
-        else
-        {
-            pCan->TFI1 &= ~(((uint32_t)1) << 31);
-        }
-
-        /* Write CAN ID*/
-        pCan->TID1 = CAN_Msg->id;
-
-        /*Write first 4 data bytes*/
-        data = (CAN_Msg->dataA[0]) | (((CAN_Msg->dataA[1]))<< 8) | ((CAN_Msg->dataA[2]) << 16) | ((CAN_Msg->dataA[3]) << 24);
-
-        pCan->TDA1 = data;
-
-        /*Write second 4 data bytes*/
-        data = (CAN_Msg->dataB[0]) | (((CAN_Msg->dataB[1])) << 8)|((CAN_Msg->dataB[2]) << 16)|((CAN_Msg->dataB[3]) << 24);
-
-        pCan->TDB1 = data;
-
-         /*Write transmission request*/
-         pCan->CMR = 0x21;
-
-         return SUCCESS;
-    }
-
-    //check status of Transmit Buffer 2
-    else if((pCan->SR) & (1 << 10))
-    {
-        /* Transmit Channel 2 is available */
-        /* Write frame informations and frame data into its CANxTFI2,
-         * CANxTID2, CANxTDA2, CANxTDB2 register */
-        pCan->TFI2 &= ~0x000F0000;
-
-        pCan->TFI2 |= (CAN_Msg->len) << 16;
-
-        if(CAN_Msg->type == REMOTE_FRAME)
-        {
-            pCan->TFI2 |= (1 << 30); //set bit RTR
-        }
-        else
-        {
-            pCan->TFI2 &= ~(1 << 30);
-        }
-
-        if(CAN_Msg->format == EXT_ID_FORMAT)
-        {
-            pCan->TFI2 |= (((uint32_t)1) << 31); //set bit FF
-        }
-        else
-        {
-            pCan->TFI2 &= ~(((uint32_t)1) << 31);
-        }
-
-        /* Write CAN ID*/
-        pCan->TID2 = CAN_Msg->id;
-
-        /*Write first 4 data bytes*/
-        data = (CAN_Msg->dataA[0]) | (((CAN_Msg->dataA[1])) << 8) | ((CAN_Msg->dataA[2]) << 16)|((CAN_Msg->dataA[3]) << 24);
-
-        pCan->TDA2 = data;
-
-        /*Write second 4 data bytes*/
-        data = (CAN_Msg->dataB[0]) | (((CAN_Msg->dataB[1])) << 8) | ((CAN_Msg->dataB[2]) << 16) | ((CAN_Msg->dataB[3]) << 24);
-
-        pCan->TDB2 = data;
-
-        /*Write transmission request*/
-        pCan->CMR = 0x41;
-
-        return SUCCESS;
-    }
-
-    //check status of Transmit Buffer 3
-    else if (pCan->SR & (1<<18))
-    {
-        /* Transmit Channel 3 is available */
-        /* Write frame informations and frame data into its CANxTFI3,
-         * CANxTID3, CANxTDA3, CANxTDB3 register */
-        pCan->TFI3 &= ~0x000F0000;
-
-        pCan->TFI3 |= (CAN_Msg->len) << 16;
-
-        if(CAN_Msg->type == REMOTE_FRAME)
-        {
-            pCan->TFI3 |= (1 << 30); //set bit RTR
-        }
-        else
-        {
-            pCan->TFI3 &= ~(1 << 30);
-        }
-
-        if(CAN_Msg->format == EXT_ID_FORMAT)
-        {
-            pCan->TFI3 |= (((uint32_t)1) << 31); //set bit FF
-        }
-        else
-        {
-            pCan->TFI3 &= ~(((uint32_t)1) << 31);
-        }
-
-        /* Write CAN ID*/
-        pCan->TID3 = CAN_Msg->id;
-
-        /*Write first 4 data bytes*/
-        data = (CAN_Msg->dataA[0]) | (((CAN_Msg->dataA[1])) << 8) | ((CAN_Msg->dataA[2]) << 16) | ((CAN_Msg->dataA[3]) << 24);
-
-        pCan->TDA3 = data;
-
-        /*Write second 4 data bytes*/
-        data = (CAN_Msg->dataB[0]) | (((CAN_Msg->dataB[1])) << 8) | ((CAN_Msg->dataB[2]) << 16) | ((CAN_Msg->dataB[3]) << 24);
-
-        pCan->TDB3 = data;
-
-        /*Write transmission request*/
-        pCan->CMR = 0x81;
-
-        return SUCCESS;
-    }
-    else
-    {
-        return ERROR;
-    }
-}
-
-/********************************************************************//**
- * @brief       Receive message data
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   CAN_Msg point to the CAN_MSG_Type Struct, it will contain received
- *              message information such as: ID, DLC, RTR, ID Format
- * @return      Status:
- *              - SUCCESS: receive message successfully
- *              - ERROR: receive message unsuccessfully
- *********************************************************************/
-Status CAN_ReceiveMsg (uint8_t canId, CAN_MSG_Type *CAN_Msg)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    uint32_t data;
-
-    //check status of Receive Buffer
-    if((pCan->SR &0x00000001))
-    {
-        /* Receive message is available */
-        /* Read frame informations */
-        CAN_Msg->format = (uint8_t)(((pCan->RFS) & 0x80000000) >> 31);
-
-        CAN_Msg->type = (uint8_t)(((pCan->RFS) & 0x40000000) >> 30);
-
-        CAN_Msg->len = (uint8_t)(((pCan->RFS) & 0x000F0000) >> 16);
-
-        /* Read CAN message identifier */
-        CAN_Msg->id = pCan->RID;
-
-        /* Read the data if received message was DATA FRAME */
-        if (CAN_Msg->type == DATA_FRAME)
-        {
-            /* Read first 4 data bytes */
-            data = pCan->RDA;
-
-            *((uint8_t *) &CAN_Msg->dataA[0])= data & 0x000000FF;
-
-            *((uint8_t *) &CAN_Msg->dataA[1])= (data & 0x0000FF00) >> 8;;
-
-            *((uint8_t *) &CAN_Msg->dataA[2])= (data & 0x00FF0000) >> 16;
-
-            *((uint8_t *) &CAN_Msg->dataA[3])= (data & 0xFF000000) >> 24;
-
-            /* Read second 4 data bytes */
-            data = pCan->RDB;
-
-            *((uint8_t *) &CAN_Msg->dataB[0])= data & 0x000000FF;
-
-            *((uint8_t *) &CAN_Msg->dataB[1])= (data & 0x0000FF00) >> 8;
-
-            *((uint8_t *) &CAN_Msg->dataB[2])= (data & 0x00FF0000) >> 16;
-
-            *((uint8_t *) &CAN_Msg->dataB[3])= (data & 0xFF000000) >> 24;
-
-            /*release receive buffer*/
-            pCan->CMR = 0x04;
-        }
-        else
-        {
-            /* Received Frame is a Remote Frame, not have data, we just receive
-             * message information only */
-            pCan->CMR = 0x04; /*release receive buffer*/
-
-            return SUCCESS;
-        }
-    }
-    else
-    {
-        // no receive message available
-        return ERROR;
-    }
-
-    return SUCCESS;
-}
-
-/********************************************************************//**
- * @brief       Receive FullCAN Object
- * @param[in]   CANAFx: CAN Acceptance Filter register, should be: LPC_CANAF
- * @param[in]   CAN_Msg point to the CAN_MSG_Type Struct, it will contain received
- *              message information such as: ID, DLC, RTR, ID Format
- * @return      CAN_ERROR, could be:
- *              - CAN_FULL_OBJ_NOT_RCV: FullCAN Object is not be received
- *              - CAN_OK: Received FullCAN Object successful
- *
- *********************************************************************/
-CAN_ERROR FCAN_ReadObj (CAN_MSG_Type *CAN_Msg)
-{
-    uint32_t *pSrc, data;
-    uint32_t interrut_word, msg_idx, test_bit, head_idx, tail_idx;
-
-    interrut_word = 0;
-
-    if (LPC_CANAF->FCANIC0 != 0)
-    {
-        interrut_word = LPC_CANAF->FCANIC0;
-
-        head_idx = 0;
-
-        tail_idx = 31;
-    }
-    else if (LPC_CANAF->FCANIC1 != 0)
-    {
-        interrut_word = LPC_CANAF->FCANIC1;
-
-        head_idx = 32;
-
-        tail_idx = 63;
-    }
-
-    if (interrut_word != 0)
-    {
-        /* Detect for interrupt pending */
-        msg_idx = 0;
-
-        for (msg_idx = head_idx; msg_idx <= tail_idx; msg_idx++)
-        {
-            test_bit = interrut_word & 0x1;
-
-            interrut_word = interrut_word >> 1;
-
-            if (test_bit)
-            {
-                pSrc = (uint32_t *) (LPC_CANAF->ENDofTable + LPC_CANAF_RAM_BASE + msg_idx * 12);
-
-                /* Has been finished updating the content */
-                if ((*pSrc & 0x03000000L) == 0x03000000L)
-                {
-                    /*clear semaphore*/
-                    *pSrc &= 0xFCFFFFFF;
-
-                    /*Set to DatA*/
-                    pSrc++;
-
-                    /* Copy to dest buf */
-                    data = *pSrc;
-
-                    *((uint8_t *) &CAN_Msg->dataA[0])= data & 0x000000FF;
-
-                    *((uint8_t *) &CAN_Msg->dataA[1])= (data & 0x0000FF00) >> 8;
-
-                    *((uint8_t *) &CAN_Msg->dataA[2])= (data & 0x00FF0000) >> 16;
-
-                    *((uint8_t *) &CAN_Msg->dataA[3])= (data & 0xFF000000) >> 24;
-
-                    /*Set to DatB*/
-                    pSrc++;
-
-                    /* Copy to dest buf */
-                    data = *pSrc;
-
-                    *((uint8_t *) &CAN_Msg->dataB[0])= data & 0x000000FF;
-
-                    *((uint8_t *) &CAN_Msg->dataB[1])= (data & 0x0000FF00) >> 8;
-
-                    *((uint8_t *) &CAN_Msg->dataB[2])= (data & 0x00FF0000) >> 16;
-
-                    *((uint8_t *) &CAN_Msg->dataB[3])= (data & 0xFF000000) >> 24;
-
-                    /*Back to Dat1*/
-                    pSrc -= 2;
-
-                    CAN_Msg->id = *pSrc & 0x7FF;
-
-                    CAN_Msg->len = (uint8_t) (*pSrc >> 16) & 0x0F;
-
-                    CAN_Msg->format = 0; //FullCAN Object ID always is 11-bit value
-
-                    CAN_Msg->type = (uint8_t)(*pSrc >> 30) &0x01;
-
-                    /*Re-read semaphore*/
-                    if ((*pSrc & 0x03000000L) == 0)
-                    {
-                        return CAN_OK;
-                    }
-                }
-            }
-        }
-    }
-
-    return CAN_FULL_OBJ_NOT_RCV;
-}
-
-/********************************************************************//**
- * @brief       Get CAN Control Status
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   arg: type of CAN status to get from CAN status register
- *              Should be:
- *              - CANCTRL_GLOBAL_STS: CAN Global Status
- *              - CANCTRL_INT_CAP: CAN Interrupt and Capture
- *              - CANCTRL_ERR_WRN: CAN Error Warning Limit
- *              - CANCTRL_STS: CAN Control Status
- * @return      Current Control Status that you want to get value
- *********************************************************************/
-uint32_t CAN_GetCTRLStatus (uint8_t canId, CAN_CTRL_STS_Type arg)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    switch (arg)
-    {
-        case CANCTRL_GLOBAL_STS:
-            return pCan->GSR;
-
-        case CANCTRL_INT_CAP:
-            return pCan->ICR;
-
-        case CANCTRL_ERR_WRN:
-            return pCan->EWL;
-
-        default: // CANCTRL_STS
-            return pCan->SR;
-    }
-}
-/********************************************************************//**
- * @brief       Get CAN Central Status
- * @param[in]   CANCRx point to LPC_CANCR_TypeDef, should be: LPC_CANCR
- * @param[in]   arg: type of CAN status to get from CAN Central status register
- *              Should be:
- *              - CANCR_TX_STS: Central CAN Tx Status
- *              - CANCR_RX_STS: Central CAN Rx Status
- *              - CANCR_MS: Central CAN Miscellaneous Status
- * @return      Current Central Status that you want to get value
- *********************************************************************/
-uint32_t CAN_GetCRStatus (CAN_CR_STS_Type arg)
-{
-    switch (arg)
-    {
-        case CANCR_TX_STS:
-            return LPC_CANCR->TxSR;
-
-        case CANCR_RX_STS:
-            return LPC_CANCR->RxSR;
-
-        default:    // CANCR_MS
-            return LPC_CANCR->MSR;
-    }
-}
-/********************************************************************//**
- * @brief       Enable/Disable CAN Interrupt
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   arg: type of CAN interrupt that you want to enable/disable
- *              Should be:
- *              - CANINT_RIE: CAN Receiver Interrupt Enable
- *              - CANINT_TIE1: CAN Transmit Interrupt Enable
- *              - CANINT_EIE: CAN Error Warning Interrupt Enable
- *              - CANINT_DOIE: CAN Data Overrun Interrupt Enable
- *              - CANINT_WUIE: CAN Wake-Up Interrupt Enable
- *              - CANINT_EPIE: CAN Error Passive Interrupt Enable
- *              - CANINT_ALIE: CAN Arbitration Lost Interrupt Enable
- *              - CANINT_BEIE: CAN Bus Error Interrupt Enable
- *              - CANINT_IDIE: CAN ID Ready Interrupt Enable
- *              - CANINT_TIE2: CAN Transmit Interrupt Enable for Buffer2
- *              - CANINT_TIE3: CAN Transmit Interrupt Enable for Buffer3
- *              - CANINT_FCE: FullCAN Interrupt Enable
- * @param[in]   NewState: New state of this function, should be:
- *              - ENABLE
- *              - DISABLE
- * @return      none
- *********************************************************************/
-void CAN_IRQCmd (uint8_t canId, CAN_INT_EN_Type arg, FunctionalState NewState)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    if(NewState == ENABLE)
-    {
-        if(arg == CANINT_FCE)
-        {
-            LPC_CANAF->AFMR = 0x01;
-
-            LPC_CANAF->FCANIE = 0x01;
-
-            LPC_CANAF->AFMR = 0x04;
-        }
-        else
-            pCan->IER |= (1 << arg);
-    }
-    else
-    {
-        if(arg == CANINT_FCE)
-        {
-            LPC_CANAF->AFMR = 0x01;
-
-            LPC_CANAF->FCANIE = 0x01;
-
-            LPC_CANAF->AFMR = 0x00;
-        }
-        else
-            pCan->IER &= ~(1 << arg);
-    }
-}
-
-/********************************************************************//**
- * @brief       Setting Acceptance Filter mode
- * @param[in]   CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF
- * @param[in]   AFMode: type of AF mode that you want to set, should be:
- *              - CAN_NORMAL: Normal mode
- *              - CAN_ACC_OFF: Acceptance Filter Off Mode
- *              - CAN_ACC_BP: Acceptance Fileter Bypass Mode
- *              - CAN_EFCAN: FullCAN Mode Enhancement
- * @return      none
- *********************************************************************/
-void CAN_SetAFMode (CAN_AFMODE_Type AFMode)
-{
-    switch(AFMode)
-    {
-        case CAN_NORMAL:
-            LPC_CANAF->AFMR = 0x00;
-            break;
-
-        case CAN_ACC_OFF:
-            LPC_CANAF->AFMR = 0x01;
-            break;
-
-        case CAN_ACC_BP:
-            LPC_CANAF->AFMR = 0x02;
-            break;
-
-        case CAN_EFCAN:
-            LPC_CANAF->AFMR = 0x04;
-            break;
-    }
-}
-
-/********************************************************************//**
- * @brief       Enable/Disable CAN Mode
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   mode: type of CAN mode that you want to enable/disable, should be:
- *              - CAN_OPERATING_MODE: Normal Operating Mode
- *              - CAN_RESET_MODE: Reset Mode
- *              - CAN_LISTENONLY_MODE: Listen Only Mode
- *              - CAN_SELFTEST_MODE: Self Test Mode
- *              - CAN_TXPRIORITY_MODE: Transmit Priority Mode
- *              - CAN_SLEEP_MODE: Sleep Mode
- *              - CAN_RXPOLARITY_MODE: Receive Polarity Mode
- *              - CAN_TEST_MODE: Test Mode
- * @param[in]   NewState: New State of this function, should be:
- *              - ENABLE
- *              - DISABLE
- * @return      none
- *********************************************************************/
-void CAN_ModeConfig(uint8_t canId, CAN_MODE_Type mode, FunctionalState NewState)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    switch(mode)
-    {
-        case CAN_OPERATING_MODE:
-            pCan->MOD = 0x00;
-            break;
-
-        case CAN_RESET_MODE:
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_RM;
-            else
-                pCan->MOD &= ~CAN_MOD_RM;
-
-            break;
-
-        case CAN_LISTENONLY_MODE:
-            pCan->MOD |=CAN_MOD_RM;//Enter Reset mode
-
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_LOM;
-            else
-                pCan->MOD &= ~ CAN_MOD_LOM;
-
-            pCan->MOD &= ~ CAN_MOD_RM;//Release Reset mode
-
-            break;
-
-        case CAN_SELFTEST_MODE:
-            pCan->MOD |= CAN_MOD_RM;//Enter Reset mode
-
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_STM;
-            else
-                pCan->MOD &= ~ CAN_MOD_STM;
-
-            pCan->MOD &= ~ CAN_MOD_RM;//Release Reset mode
-
-            break;
-
-        case CAN_TXPRIORITY_MODE:
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_TPM;
-            else
-                pCan->MOD &= ~ CAN_MOD_TPM;
-
-            break;
-
-        case CAN_SLEEP_MODE:
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_SM;
-            else
-                pCan->MOD &= ~ CAN_MOD_SM;
-
-            break;
-
-        case CAN_RXPOLARITY_MODE:
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_RPM;
-            else
-                pCan->MOD &= ~ CAN_MOD_RPM;
-
-            break;
-
-        case CAN_TEST_MODE:
-            if(NewState == ENABLE)
-                pCan->MOD |= CAN_MOD_TM;
-            else
-                pCan->MOD &= ~ CAN_MOD_TM;
-
-            break;
-    }
-}
-/*********************************************************************//**
- * @brief       Set CAN command request
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @param[in]   CMRType command request type, should be:
- *              - CAN_CMR_TR: Transmission request
- *              - CAN_CMR_AT: Abort Transmission request
- *              - CAN_CMR_RRB: Release Receive Buffer request
- *              - CAN_CMR_CDO: Clear Data Overrun request
- *              - CAN_CMR_SRR: Self Reception request
- *              - CAN_CMR_STB1: Select Tx Buffer 1 request
- *              - CAN_CMR_STB2: Select Tx Buffer 2 request
- *              - CAN_CMR_STB3: Select Tx Buffer 3 request
- * @return      CANICR (CAN interrupt and Capture register) value
- **********************************************************************/
-void CAN_SetCommand(uint8_t canId, uint32_t CMRType)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    pCan->CMR |= CMRType;
-}
-
-/*********************************************************************//**
- * @brief       Get CAN interrupt status
- * @param[in]    canId           The Id of the expected CAN component
- *
- * @return      CANICR (CAN interrupt and Capture register) value
- **********************************************************************/
-uint32_t CAN_IntGetStatus(uint8_t canId)
-{
-    LPC_CAN_TypeDef* pCan = CAN_GetPointer(canId);
-
-    return pCan->ICR;
-}
-
-/*********************************************************************//**
- * @brief       Check if FullCAN interrupt enable or not
- * @param[in]   CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF
- * @return      IntStatus, could be:
- *              - SET: if FullCAN interrupt is enable
- *              - RESET: if FullCAN interrupt is disable
- **********************************************************************/
-IntStatus CAN_FullCANIntGetStatus (void)
-{
-    if (LPC_CANAF->FCANIE)
-        return SET;
-
-    return RESET;
-}
-
-/*********************************************************************//**
- * @brief       Get value of FullCAN interrupt and capture register
- * @param[in]   CANAFx point to LPC_CANAF_TypeDef object, should be: LPC_CANAF
- * @param[in]   type: FullCAN IC type, should be:
- *              - FULLCAN_IC0: FullCAN Interrupt Capture 0
- *              - FULLCAN_IC1: FullCAN Interrupt Capture 1
- * @return      FCANIC0 or FCANIC1 (FullCAN interrupt and Capture register) value
- **********************************************************************/
-uint32_t CAN_FullCANPendGetStatus(FullCAN_IC_Type type)
-{
-    if (type == FULLCAN_IC0)
-        return LPC_CANAF->FCANIC0;
-
-    return LPC_CANAF->FCANIC1;
-}
-/* End of Public Variables ---------------------------------------------------------- */
-/**
- * @}
- */
-#endif /*_CAN*/
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */

bsp/nxp/lpc/lpc408x/Libraries/Drivers/source/lpc_clkpwr.c

@@ -1,326 +0,0 @@
-/**********************************************************************
-* $Id$      lpc_clkpwr.c            2011-06-02
-*//**
-* @file     lpc_clkpwr.c
-* @brief    Contains all functions support for Clock and Power Control
-*           firmware library on LPC
-* @version  1.0
-* @date     02. June. 2011
-* @author   NXP MCU SW Application Team
-* 
-* Copyright(C) 2011, NXP Semiconductor
-* All rights reserved.
-*
-***********************************************************************
-* Software that is described herein is for illustrative purposes only
-* which provides customers with programming information regarding the
-* products. This software is supplied "AS IS" without any warranties.
-* NXP Semiconductors assumes no responsibility or liability for the
-* use of the software, conveys no license or title under any patent,
-* copyright, or mask work right to the product. NXP Semiconductors
-* reserves the right to make changes in the software without
-* notification. NXP Semiconductors also make no representation or
-* warranty that such application will be suitable for the specified
-* use without further testing or modification.
-* Permission to use, copy, modify, and distribute this software and its
-* documentation is hereby granted, under NXP Semiconductors'
-* relevant copyright in the software, without fee, provided that it
-* is used in conjunction with NXP Semiconductors microcontrollers.  This
-* copyright, permission, and disclaimer notice must appear in all copies of
-* this code.
-**********************************************************************/
-
-/* Peripheral group ----------------------------------------------------------- */
-/** @addtogroup CLKPWR
- * @{
- */
-#ifdef __BUILD_WITH_EXAMPLE__
-#include "lpc_libcfg.h"
-#else
-#include "lpc_libcfg_default.h"
-#endif /* __BUILD_WITH_EXAMPLE__ */
-#ifdef _CLKPWR
- 
-/* Includes ------------------------------------------------------------------- */
-#include "lpc_clkpwr.h"
-
-uint32_t USBFrequency = 0;
-
-
-/* Public Functions ----------------------------------------------------------- */
-/** @addtogroup CLKPWR_Public_Functions
- * @{
- */
-
-/*********************************************************************//**
- * @brief       Set value of each Peripheral Clock Selection
- * @param[in]   ClkType clock type that will be divided, should be:
- *              - CLKPWR_CLKTYPE_CPU        : CPU clock
- *              - CLKPWR_CLKTYPE_PER        : Peripheral clock
- *              - CLKPWR_CLKTYPE_EMC        : EMC clock
- *              - CLKPWR_CLKTYPE_USB        : USB clock
- * @param[in]   DivVal  Value of divider. This value should be set as follows:
- *                  - CPU clock: DivVal must be in range: 0..31
- *                  - Peripheral clock: DivVal must be in range: 0..31
- *                  - EMC clock: DivVal must be:
- *                          + 0: The EMC uses the same clock as the CPU
- *                          + 1: The EMC uses a clock at half the rate of the CPU
- *                  - USB clock: DivVal must be:
- *                          + 0: the divider is turned off, no clock will
- *                               be provided to the USB subsystem
- *                          + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
- *                          + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
- * @return none
- * Note: Pls assign right DivVal, this function will not check if it is illegal.
- **********************************************************************/
-void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
-{
-    uint32_t tmp;
-    switch(ClkType)
-    {
-    case CLKPWR_CLKTYPE_CPU:
-        tmp =   LPC_SC->CCLKSEL & ~(0x1F);
-        tmp |=  DivVal & 0x1F;
-        LPC_SC->CCLKSEL = tmp;
-        SystemCoreClockUpdate(); //Update clock
-        break;
-    case CLKPWR_CLKTYPE_PER:
-        tmp =   LPC_SC->PCLKSEL & ~(0x1F);
-        tmp |=  DivVal & 0x1F;
-        LPC_SC->PCLKSEL = tmp;
-        SystemCoreClockUpdate(); //Update clock
-        break;
-    case CLKPWR_CLKTYPE_EMC:
-        tmp =   LPC_SC->EMCCLKSEL & ~(0x01);
-        tmp |=  DivVal & 0x01;
-        LPC_SC->EMCCLKSEL = tmp;
-        SystemCoreClockUpdate(); //Update clock
-        break;
-    case CLKPWR_CLKTYPE_USB:
-        tmp =   LPC_SC->USBCLKSEL & ~(0x1F);
-        tmp |=  DivVal & 0x1F;
-        LPC_SC->USBCLKSEL |= DivVal & 0x1F;
-        SystemCoreClockUpdate(); //Update clock
-        break;
-    default:
-        while(1);//Error Loop;
-    }
-}
-
-/*********************************************************************//**
- * @brief       Get current clock value
- * @param[in]   ClkType clock type that will be divided, should be:
- *              - CLKPWR_CLKTYPE_CPU        : CPU clock
- *              - CLKPWR_CLKTYPE_PER        : Peripheral clock
- *              - CLKPWR_CLKTYPE_EMC        : EMC clock
- *              - CLKPWR_CLKTYPE_USB        : USB clock
- **********************************************************************/
-uint32_t CLKPWR_GetCLK (uint8_t ClkType)
-{
-    switch(ClkType)
-    {
-        case CLKPWR_CLKTYPE_CPU:
-            return SystemCoreClock;
-
-        case CLKPWR_CLKTYPE_PER:
-            return PeripheralClock;
-
-        case CLKPWR_CLKTYPE_EMC:
-            return EMCClock;
-
-        case CLKPWR_CLKTYPE_USB:
-            return USBClock;
-
-        default:
-            while(1);//error loop
-    }
-}
-
-/*********************************************************************//**
- * @brief       Configure power supply for each peripheral according to NewState
- * @param[in]   PPType  Type of peripheral used to enable power,
- *              should be one of the following:
- *              -  CLKPWR_PCONP_PCLCD       : LCD
- *              -  CLKPWR_PCONP_PCTIM0      : Timer 0
- *              -  CLKPWR_PCONP_PCTIM1      : Timer 1
- *              -  CLKPWR_PCONP_PCUART0     : UART 0
- *              -  CLKPWR_PCONP_PCUART1     : UART 1
- *              -  CLKPWR_PCONP_PCPWM0      : PWM 0
- *              -  CLKPWR_PCONP_PCPWM1      : PWM 1
- *              -  CLKPWR_PCONP_PCI2C0      : I2C 0
- *              -  CLKPWR_PCONP_PCUART4     : UART4
- *              -  CLKPWR_PCONP_PCLCD       : LCD
- *              -  CLKPWR_PCONP_PCTIM0      : Timer 0
- *              -  CLKPWR_PCONP_PCRTC       : RTC
- *              -  CLKPWR_PCONP_PCSSP1      : SSP 1
- *              -  CLKPWR_PCONP_PCEMC       : EMC
- *              -  CLKPWR_PCONP_PCADC       : ADC
- *              -  CLKPWR_PCONP_PCAN1       : CAN 1
- *              -  CLKPWR_PCONP_PCAN2       : CAN 2
- *              -  CLKPWR_PCONP_PCGPIO      : GPIO
- *              -  CLKPWR_PCONP_PCMC        : MCPWM
- *              -  CLKPWR_PCONP_PCQEI       : QEI
- *              -  CLKPWR_PCONP_PCI2C1      : I2C 1
- *              -  CLKPWR_PCONP_PCSSP2      : SSP 2
- *              -  CLKPWR_PCONP_PCSSP0      : SSP 0
- *              -  CLKPWR_PCONP_PCTIM2      : Timer 2
- *              -  CLKPWR_PCONP_PCTIM3      : Timer 3
- *              -  CLKPWR_PCONP_PCUART2     : UART 2
- *              -  CLKPWR_PCONP_PCUART3     : UART 3
- *              -  CLKPWR_PCONP_PCI2C2      : I2C 2
- *              -  CLKPWR_PCONP_PCI2S       : I2S
- *              -  CLKPWR_PCONP_PCSDC       : SDC
- *              -  CLKPWR_PCONP_PCGPDMA     : GPDMA
- *              -  CLKPWR_PCONP_PCENET      : Ethernet
- *              -  CLKPWR_PCONP_PCUSB       : USB
- *
- * @param[in]   NewState    New state of Peripheral Power, should be:
- *              - ENABLE    : Enable power for this peripheral
- *              - DISABLE   : Disable power for this peripheral
- *
- * @return none
- **********************************************************************/
-void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
-{
-    if (NewState == ENABLE)
-    {
-        LPC_SC->PCONP |= PPType;
-    }
-    else if (NewState == DISABLE)
-    {
-        LPC_SC->PCONP &= ~PPType;
-    }
-}
-
-#if 0
-// nxp21346
-/*********************************************************************//**
- * @brief       Configure hardware reset for each peripheral according to NewState
- * @param[in]   PPType  Type of peripheral used to enable power,
- *              should be one of the following:
- *              -  CLKPWR_RSTCON0_LCD       : LCD
- *              -  CLKPWR_RSTCON0_TIM0      : Timer 0
-                -  CLKPWR_RSTCON0_TIM1      : Timer 1
-                -  CLKPWR_RSTCON0_UART0     : UART 0
-                -  CLKPWR_RSTCON0_UART1     : UART 1
-                -  CLKPWR_RSTCON0_PWM0      : PWM 0
-                -  CLKPWR_RSTCON0_PWM1      : PWM 1
-                -  CLKPWR_RSTCON0_I2C0      : I2C 0
-                -  CLKPWR_RSTCON0_UART4     : UART 4
-                -  CLKPWR_RSTCON0_RTC       : RTC
-                -  CLKPWR_RSTCON0_SSP1      : SSP 1
-                -  CLKPWR_RSTCON0_EMC       : EMC
-                -  CLKPWR_RSTCON0_ADC       : ADC
-                -  CLKPWR_RSTCON0_CAN1      : CAN 1
-                -  CLKPWR_RSTCON0_CAN2      : CAN 2
-                -  CLKPWR_RSTCON0_GPIO      : GPIO
-                -  CLKPWR_RSTCON0_MCPWM     : MCPWM
-                -  CLKPWR_RSTCON0_QEI       : QEI
-                -  CLKPWR_RSTCON0_I2C1      : I2C 1
-                -  CLKPWR_RSTCON0_SSP2      : SSP 2
-                -  CLKPWR_RSTCON0_SSP0      : SSP 0
-                -  CLKPWR_RSTCON0_TIM2      : Timer 2
-                -  CLKPWR_RSTCON0_TIM3      : Timer 3
-                -  CLKPWR_RSTCON0_UART2     : UART 2
-                -  CLKPWR_RSTCON0_UART3     : UART 3
-                -  CLKPWR_RSTCON0_I2C2      : I2C 2
-                -  CLKPWR_RSTCON0_I2S       : I2S
-                -  CLKPWR_RSTCON0_SDC       : SDC
-                -  CLKPWR_RSTCON0_GPDMA     : GPDMA
-                -  CLKPWR_RSTCON0_ENET      : Ethernet
-                -  CLKPWR_RSTCON0_USB       : USB
- *
- * @param[in]   NewState    New state of Peripheral Power, should be:
- *              - ENABLE    : Enable power for this peripheral
- *              - DISABLE   : Disable power for this peripheral
- *
- * @return none
- **********************************************************************/
-void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
-{
-    if(PType < 32)
-    {
-        if(NewState == ENABLE)
-            LPC_SC->RSTCON0 |=(1<<PType);
-        else
-            LPC_SC->RSTCON0 &=~(1<<PType);
-    }
-    else
-    {
-        if(NewState == ENABLE)
-            LPC_SC->RSTCON1 |= (1<<(PType - 31));
-        else
-            LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
-    }
-}
-// nxp21346
-#endif
-
-/*********************************************************************//**
- * @brief       Enter Sleep mode with co-operated instruction by the Cortex-M3.
- * @param[in]   None
- * @return      None
- **********************************************************************/
-void CLKPWR_Sleep(void)
-{
-    LPC_SC->PCON = 0x00;
-    /* Sleep Mode*/
-    __WFI();
-}
-
-
-/*********************************************************************//**
- * @brief       Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
- * @param[in]   None
- * @return      None
- **********************************************************************/
-void CLKPWR_DeepSleep(void)
-{
-    /* Deep-Sleep Mode, set SLEEPDEEP bit */
-    SCB->SCR = 0x4;
-    LPC_SC->PCON = 0x00;
-    /* Deep Sleep Mode*/
-    __WFI();
-}
-
-
-/*********************************************************************//**
- * @brief       Enter Power Down mode with co-operated instruction by the Cortex-M3.
- * @param[in]   None
- * @return      None
- **********************************************************************/
-void CLKPWR_PowerDown(void)
-{
-    /* Deep-Sleep Mode, set SLEEPDEEP bit */
-    SCB->SCR = 0x4;
-    LPC_SC->PCON = 0x01;
-    /* Power Down Mode*/
-    __WFI();
-}
-
-
-/*********************************************************************//**
- * @brief       Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
- * @param[in]   None
- * @return      None
- **********************************************************************/
-void CLKPWR_DeepPowerDown(void)
-{
-    /* Deep-Sleep Mode, set SLEEPDEEP bit */
-    SCB->SCR = 0x4;
-    LPC_SC->PCON = 0x03;
-    /* Deep Power Down Mode*/
-    __WFI();
-}
-
-/**
- * @}
- */
- 
-#endif /*_CLKPWR*/
-
-/**
- * @}
- */
-
-/* --------------------------------- End Of File ------------------------------ */