bsp: all Renesas bsp support the nano one-click switch. (#10629)

* bsp: all Renesas bsp support the nano one-click switch.

* fix pr conflicts.

bsp/renesas/ebf_qi_min_6m5/.config

@@ -1,3 +1,4 @@
+CONFIG_SOC_R7FA6M5BH=y
 
 #
 # RT-Thread Kernel
@@ -210,6 +211,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_CMD_SIZE=80
 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -387,6 +389,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
 # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
 
 #
 # Wi-Fi
@@ -494,6 +497,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_QMODBUS is not set
 # CONFIG_PKG_USING_PNET is not set
 # CONFIG_PKG_USING_OPENER is not set
+# CONFIG_PKG_USING_FREEMQTT is not set
 # end of IoT - internet of things
 
 #
@@ -721,6 +725,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_RMP is not set
 # CONFIG_PKG_USING_R_RHEALSTONE is not set
 # CONFIG_PKG_USING_HEARTBEAT is not set
+# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set
 # end of system packages
 
 #
@@ -844,6 +849,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 #
 # HC32 DDL Drivers
 #
+# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set
 # end of HC32 DDL Drivers
 
 #
@@ -857,6 +864,21 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set
 # CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set
 # end of NXP HAL & SDK Drivers
+
+#
+# NUVOTON Drivers
+#
+# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set
+# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set
+# end of NUVOTON Drivers
+
+#
+# GD32 Drivers
+#
+# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set
+# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set
+# end of GD32 Drivers
 # end of HAL & SDK Drivers
 
 #
@@ -1374,7 +1396,6 @@ CONFIG_SOC_SERIES_R7FA6M5=y
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_R7FA6M5BH=y
 
 #
 # Onboard Peripheral Drivers
@@ -1395,7 +1416,6 @@ CONFIG_BSP_USING_UART4=y
 CONFIG_BSP_UART4_RX_BUFSIZE=256
 CONFIG_BSP_UART4_TX_BUFSIZE=0
 # CONFIG_BSP_USING_HW_I2C is not set
-# CONFIG_BSP_USING_SOFT_I2C is not set
 # CONFIG_BSP_USING_SPI is not set
 # CONFIG_BSP_USING_SCI is not set
 # CONFIG_BSP_USING_ADC is not set

bsp/renesas/ebf_qi_min_6m5/Kconfig

@@ -11,7 +11,17 @@ PKGS_DIR := packages
 
 ENV_DIR := /
 
+config SOC_R7FA6M5BH
+    bool
+    select SOC_SERIES_R7FA6M5
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
 source "$(RTT_DIR)/Kconfig"
 osource "$PKGS_DIR/Kconfig"
 rsource "../libraries/Kconfig"
-source "$(BSP_DIR)/board/Kconfig"
+
+if !RT_USING_NANO
+rsource "$(BSP_DIR)/board/Kconfig"
+endif

bsp/renesas/ebf_qi_min_6m5/board/Kconfig

@@ -1,19 +1,12 @@
 menu "Hardware Drivers Config"
 
-    config SOC_R7FA6M5BH
-        bool
-        select SOC_SERIES_R7FA6M5
-        select RT_USING_COMPONENTS_INIT
-        select RT_USING_USER_MAIN
-        default y
-
     menu "Onboard Peripheral Drivers"
 
     endmenu
 
     menu "On-chip Peripheral Drivers"
 
-        rsource "../../libraries/HAL_Drivers/Kconfig"
+        rsource "../../libraries/HAL_Drivers/drivers/Kconfig"
 
         menuconfig BSP_USING_UART
             bool "Enable UART"
@@ -89,30 +82,6 @@ menu "Hardware Drivers Config"
                     default n
             endif
 
-        menuconfig BSP_USING_SOFT_I2C
-            bool "Enable software I2C bus"
-            select RT_USING_I2C
-            select RT_USING_I2C_BITOPS
-            select RT_USING_PIN
-            default n
-            if BSP_USING_SOFT_I2C
-                config BSP_USING_SOFT_I2C
-                menuconfig BSP_USING_I2C1
-                    bool "Enable I2C1 Bus (software simulation)"
-                    default n
-                    if BSP_USING_I2C1
-                        comment "Please refer to the 'bsp_io.h' file to configure the pins"
-                        config BSP_I2C1_SCL_PIN
-                            hex "i2c1 scl pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x050C
-                        config BSP_I2C1_SDA_PIN
-                            hex "i2c1 sda pin number (hex)"
-                            range 0x0000 0xFFFF
-                            default 0x050B
-                    endif
-            endif
-
         menuconfig BSP_USING_SPI
             bool "Enable SPI BUS"
             default n

bsp/renesas/ebf_qi_min_6m5/rtconfig.h

@@ -1,6 +1,8 @@
 #ifndef RT_CONFIG_H__
 #define RT_CONFIG_H__
 
+#define SOC_R7FA6M5BH
+
 /* RT-Thread Kernel */
 
 /* klibc options */
@@ -308,6 +310,14 @@
 /* NXP HAL & SDK Drivers */
 
 /* end of NXP HAL & SDK Drivers */
+
+/* NUVOTON Drivers */
+
+/* end of NUVOTON Drivers */
+
+/* GD32 Drivers */
+
+/* end of GD32 Drivers */
 /* end of HAL & SDK Drivers */
 
 /* sensors drivers */
@@ -392,8 +402,6 @@
 
 /* Hardware Drivers Config */
 
-#define SOC_R7FA6M5BH
-
 /* Onboard Peripheral Drivers */
 
 /* On-chip Peripheral Drivers */

bsp/renesas/ebf_qi_min_6m5/src/hal_entry.c

@@ -10,7 +10,11 @@
 
 #include <rtthread.h>
 #include "hal_data.h"
+#ifdef RT_USING_NANO
+#include <drv_gpio.h>
+#else
 #include <rtdevice.h>
+#endif /* RT_USING_NANO */
 
 #define LED_PIN    BSP_IO_PORT_04_PIN_00 /* RED LED pins */
 

bsp/renesas/libraries/HAL_Drivers/SConscript

@@ -1,72 +1,18 @@
 Import('RTT_ROOT')
 Import('rtconfig')
 from building import *
+import os
 
 cwd = GetCurrentDir()
+group = []
+src = ['drv_common.c']
+path = [cwd]
 
-# add the general drivers.
-src = Split("""
-    drv_common.c
-""")
+if GetDepend(['RT_USING_NANO']):
+    group = group + SConscript(os.path.join(cwd, 'nano', 'SConscript'))
+else:
+    group = group + SConscript(os.path.join(cwd, 'drivers', 'SConscript'))
 
-if GetDepend(['BSP_USING_UART']):
-    if GetDepend(['RT_USING_SERIAL_V2']):
-        src += ['drv_usart_v2.c']
-    else:
-        print("\nThe current project does not support serial-v1\n")
-        Return('group')
-
-if GetDepend(['BSP_USING_GPIO']):
-    src += ['drv_gpio.c']
-
-if GetDepend(['BSP_USING_WDT']):
-    src += ['drv_wdt.c']
-
-if GetDepend(['BSP_USING_ONCHIP_RTC']):
-    src += ['drv_rtc.c']
-
-if GetDepend(['BSP_USING_HW_I2C']):
-        src += ['drv_i2c.c']
-
-if GetDepend(['BSP_USING_SPI']):
-    src += ['drv_spi.c']
-
-if GetDepend(['BSP_USING_SOFT_SPI']):
-    src += ['drv_soft_spi.c']
-
-if GetDepend(['BSP_USING_SCI']):
-    src += ['drv_sci.c']
-
-if GetDepend(['BSP_USING_ADC']):
-    src += ['drv_adc.c']
-
-if GetDepend(['BSP_USING_DAC']):
-    src += ['drv_dac.c']
-
-if GetDepend(['BSP_USING_ONCHIP_FLASH']):
-    src += ['drv_flash.c']
-
-if GetDepend(['BSP_USING_PWM']):
-    src += ['drv_pwm.c']
-
-if GetDepend(['BSP_USING_TIM']):
-    src += ['drv_hwtimer.c']
-
-if GetDepend(['BSP_USING_ETH']):
-    src += ['drv_eth.c']
-
-if GetDepend(['BSP_USING_CAN']) or GetDepend('BSP_USING_CANFD'):
-    src += ['drv_can.c']
-
-if GetDepend(['BSP_USING_SDHI']):
-    src += ['drv_sdhi.c']
-
-if GetDepend(['BSP_USING_LCD']):
-    src += ['drv_lcd.c']
-
-path =  [cwd]
-path += [cwd + '/config']
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+group = group + DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
 
 Return('group')

bsp/renesas/libraries/HAL_Drivers/drivers/SConscript

@@ -0,0 +1,70 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = []
+
+if GetDepend(['BSP_USING_UART']):
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        print("\nThe current project does not support serial-v1\n")
+        Return('group')
+
+if GetDepend(['BSP_USING_GPIO']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_ONCHIP_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_HW_I2C']):
+        src += ['drv_i2c.c']
+
+if GetDepend(['BSP_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['BSP_USING_SOFT_SPI']):
+    src += ['drv_soft_spi.c']
+
+if GetDepend(['BSP_USING_SCI']):
+    src += ['drv_sci.c']
+
+if GetDepend(['BSP_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['BSP_USING_DAC']):
+    src += ['drv_dac.c']
+
+if GetDepend(['BSP_USING_ONCHIP_FLASH']):
+    src += ['drv_flash.c']
+
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['BSP_USING_TIM']):
+    src += ['drv_hwtimer.c']
+
+if GetDepend(['BSP_USING_ETH']):
+    src += ['drv_eth.c']
+
+if GetDepend(['BSP_USING_CAN']) or GetDepend('BSP_USING_CANFD'):
+    src += ['drv_can.c']
+
+if GetDepend(['BSP_USING_SDHI']):
+    src += ['drv_sdhi.c']
+
+if GetDepend(['BSP_USING_LCD']):
+    src += ['drv_lcd.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2a1/adc_config.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-17     CYFS         first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+
+struct rt_adc_dev
+{
+    struct rt_adc_ops ops;
+    struct rt_adc_device adc_device;
+};
+
+struct ra_adc_map
+{
+    const char *device_name;
+    const adc_cfg_t *g_cfg;
+    const adc_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2a1/can_config.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_CAN0)
+#ifndef CAN0_CONFIG
+#define CAN0_CONFIG                                                 \
+    {                                                               \
+        .name = "can0",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0,             \
+        .p_api_ctrl = &g_can0_ctrl,                                \
+        .p_cfg = &g_can0_cfg,                                      \
+    }
+#endif /* CAN0_CONFIG */
+#endif /* BSP_USING_CAN0 */
+
+#if defined(BSP_USING_CAN1)
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                                                 \
+    {                                                               \
+        .name = "can1",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1,             \
+        .p_api_ctrl = &g_can1_ctrl,                                \
+        .p_cfg = &g_can1_cfg,                                      \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2a1/dac_config.h

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-17     CYFS         first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC
+struct ra_dac_map
+{
+    char name;
+    const struct st_dac_cfg *g_cfg;
+    const struct st_dac_instance_ctrl *g_ctrl;
+};
+
+struct ra_dac_dev
+{
+    rt_dac_device_t       ra_dac_device_t;
+    struct ra_dac_map    *ra_dac_map_dev;
+};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2a1/pwm_config.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/config/ra2a1/uart_config.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-17     CYFS              first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART0)
+#ifndef UART0_CONFIG
+#define UART0_CONFIG                                                \
+    {                                                               \
+        .name = "uart0",                                            \
+        .p_api_ctrl = &g_uart0_ctrl,                                \
+        .p_cfg = &g_uart0_cfg,                                      \
+    }
+#endif /* UART0_CONFIG */
+#endif /* BSP_USING_UART0 */
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .p_api_ctrl = &g_uart1_ctrl,                                \
+        .p_cfg = &g_uart1_cfg,                                      \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART9)
+#ifndef UART9_CONFIG
+#define UART9_CONFIG                                                \
+    {                                                               \
+        .name = "uart9",                                            \
+        .p_api_ctrl = &g_uart9_ctrl,                                \
+        .p_cfg = &g_uart9_cfg,                                      \
+    }
+#endif /* UART9_CONFIG */
+#endif /* BSP_USING_UART9 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/renesas/libraries/HAL_Drivers/drv_common.c

@@ -11,6 +11,7 @@
 #include <drv_common.h>
 #include <bsp_api.h>
 #include "board.h"
+#include <hal_data.h>
 
 #ifdef RT_USING_PIN
     #include <drv_gpio.h>
@@ -191,6 +192,11 @@ rt_weak void rt_hw_board_init()
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_NANO)
+    extern void rt_hw_console_init(void);
+    rt_hw_console_init();
+#endif
+
     /* Board underlying hardware initialization */
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();

bsp/renesas/libraries/HAL_Drivers/nano/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+group = []
+src = ['drv_gpio.c']
+path = [cwd]
+
+if GetDepend(['RT_USING_CONSOLE']):
+    src += ['drv_console.c']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/renesas/libraries/HAL_Drivers/nano/drv_console.c

@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-20     kurisaw      First version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <hal_data.h>
+
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_SEMAPHORE)
+
+static rt_sem_t console_sem = RT_NULL;
+
+#if defined(RT_NANO_CONSOLE_UART0)
+#define renesas_uart_ctrl       g_uart0_ctrl
+#define renesas_uart_cfg        g_uart0_cfg
+#define renesas_uart_callback   user_uart0_callback
+#elif defined(RT_NANO_CONSOLE_UART1)
+#define renesas_uart_ctrl       g_uart1_ctrl
+#define renesas_uart_cfg        g_uart1_cfg
+#define renesas_uart_callback   user_uart1_callback
+#elif defined(RT_NANO_CONSOLE_UART2)
+#define renesas_uart_ctrl       g_uart2_ctrl
+#define renesas_uart_cfg        g_uart2_cfg
+#define renesas_uart_callback   user_uart2_callback
+#elif defined(RT_NANO_CONSOLE_UART3)
+#define renesas_uart_ctrl       g_uart3_ctrl
+#define renesas_uart_cfg        g_uart3_cfg
+#define renesas_uart_callback   user_uart3_callback
+#elif defined(RT_NANO_CONSOLE_UART4)
+#define renesas_uart_ctrl       g_uart4_ctrl
+#define renesas_uart_cfg        g_uart4_cfg
+#define renesas_uart_callback   user_uart4_callback
+#elif defined(RT_NANO_CONSOLE_UART5)
+#define renesas_uart_ctrl       g_uart5_ctrl
+#define renesas_uart_cfg        g_uart5_cfg
+#define renesas_uart_callback   user_uart5_callback
+#elif defined(RT_NANO_CONSOLE_UART6)
+#define renesas_uart_ctrl       g_uart6_ctrl
+#define renesas_uart_cfg        g_uart6_cfg
+#define renesas_uart_callback   user_uart6_callback
+#elif defined(RT_NANO_CONSOLE_UART7)
+#define renesas_uart_ctrl       g_uart7_ctrl
+#define renesas_uart_cfg        g_uart7_cfg
+#define renesas_uart_callback   user_uart7_callback
+#elif defined(RT_NANO_CONSOLE_UART8)
+#define renesas_uart_ctrl       g_uart8_ctrl
+#define renesas_uart_cfg        g_uart8_cfg
+#define renesas_uart_callback   user_uart8_callback
+#elif defined(RT_NANO_CONSOLE_UART9)
+#define renesas_uart_ctrl       g_uart9_ctrl
+#define renesas_uart_cfg        g_uart9_cfg
+#define renesas_uart_callback   user_uart9_callback
+#endif
+
+void rt_hw_console_init(void)
+{
+    fsp_err_t err;
+    console_sem = rt_sem_create("console", 0, RT_IPC_FLAG_FIFO);
+
+    /* Initialize UART using FSP */
+#ifdef SOC_SERIES_R7FA8M85
+    err = R_SCI_B_UART_Open(&renesas_uart_ctrl, &renesas_uart_cfg);
+#else
+    err = R_SCI_UART_Open(&renesas_uart_ctrl, &renesas_uart_cfg);
+#endif
+    if (FSP_SUCCESS != err)
+    {
+        while (1); /* Trap on failure */
+    }
+    return;
+}
+
+void console_send_byte(uint8_t ch)
+{
+#if defined(SOC_SERIES_R7FA8M85) || defined(SOC_SERIES_R9A07G0)
+    while ((renesas_uart_ctrl.p_reg->CSR_b.TEND) == 0);
+#else
+    while ((renesas_uart_ctrl.p_reg->SSR_b.TEND) == 0);
+#endif
+    renesas_uart_ctrl.p_reg->TDR = ch;
+}
+
+void rt_hw_console_output(const char *str)
+{
+    rt_size_t i = 0, size = 0;
+    char a = '\r';
+
+    size = rt_strlen(str);
+
+    for (i = 0; i < size; i++)
+    {
+        if (*(str + i) == '\n')
+        {
+            console_send_byte((uint8_t) a);
+        }
+        console_send_byte(*(str + i));
+    }
+}
+
+void renesas_uart_callback(uart_callback_args_t *p_args)
+{
+    /* Handle the UART event */
+    switch (p_args->event)
+    {
+        /* Received a character or receive completed */
+        case UART_EVENT_RX_CHAR:
+        case UART_EVENT_RX_COMPLETE:
+            rt_sem_release(console_sem);
+            break;
+
+        default:
+            break;
+    }
+}
+
+char rt_hw_console_getchar(void)
+{
+    int ch = -1;
+    rt_sem_take(console_sem, RT_WAITING_FOREVER);
+#ifdef SOC_SERIES_R7FA8M85
+    fsp_err_t ret = R_SCI_B_UART_Read(&renesas_uart_ctrl, (uint8_t *)&ch, 1);
+#else
+    fsp_err_t ret = R_SCI_UART_Read(&renesas_uart_ctrl, (uint8_t *)&ch, 1);
+#endif
+    if(ret != FSP_SUCCESS)
+    {
+        ch = -1;
+        rt_thread_mdelay(10);
+    }
+    return ch;
+}
+#endif

bsp/renesas/libraries/HAL_Drivers/nano/drv_gpio.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date             Author              Notes
+ * 2025-08-21       kurisaw             first version
+ */
+
+#include <drv_gpio.h>
+#include <rtthread.h>
+
+void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode)
+{
+    fsp_err_t err;
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_OUTPUT);
+        if (err != FSP_SUCCESS)
+        {
+            return;
+        }
+        break;
+
+    case PIN_MODE_INPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, BSP_IO_DIRECTION_INPUT);
+        if (err != FSP_SUCCESS)
+        {
+            return;
+        }
+        break;
+
+    case PIN_MODE_OUTPUT_OD:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, IOPORT_CFG_NMOS_ENABLE);
+        if (err != FSP_SUCCESS)
+        {
+            return;
+        }
+        break;
+    }
+}
+
+void rt_pin_write(rt_uint64_t pin, rt_uint8_t value)
+{
+    bsp_io_level_t level = BSP_IO_LEVEL_HIGH;
+
+    if (value != level)
+    {
+        level = BSP_IO_LEVEL_LOW;
+    }
+
+    R_BSP_PinAccessEnable();
+#ifdef SOC_SERIES_R9A07G0
+    R_IOPORT_PinWrite(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, (bsp_io_level_t)level);
+#else
+    R_BSP_PinWrite(pin, level);
+#endif
+    R_BSP_PinAccessDisable();
+}
+
+rt_int8_t rt_pin_read(rt_uint64_t pin)
+{
+    if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
+    {
+        return -RT_EINVAL;
+    }
+#ifdef SOC_SERIES_R9A07G0
+    bsp_io_level_t io_level;
+    R_IOPORT_PinRead(&g_ioport_ctrl, (bsp_io_port_pin_t)pin, &io_level);
+    return io_level;
+#else
+    return R_BSP_PinRead(pin);
+#endif
+}

bsp/renesas/libraries/HAL_Drivers/nano/drv_gpio.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2025-08-20     kurisaw           first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtdef.h>
+#include <hal_data.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_LOW                 0x00
+#define PIN_HIGH                0x01
+
+#define PIN_MODE_OUTPUT         0x00
+#define PIN_MODE_INPUT          0x01
+#define PIN_MODE_INPUT_PULLUP   0x02
+#define PIN_MODE_INPUT_PULLDOWN 0x03
+#define PIN_MODE_OUTPUT_OD      0x04
+
+#ifdef SOC_SERIES_R9A07G0
+#define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_0
+#define RA_MAX_PIN_VALUE    BSP_IO_PORT_24_PIN_7
+#else
+#define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_00
+#define RA_MAX_PIN_VALUE    BSP_IO_PORT_11_PIN_15
+#endif
+
+void rt_pin_mode(rt_uint64_t pin, rt_uint8_t mode);
+void rt_pin_write(rt_uint64_t pin, rt_uint8_t value);
+rt_int8_t rt_pin_read(rt_uint64_t pin);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+

bsp/renesas/libraries/Kconfig

@@ -65,4 +65,32 @@ config SOC_SERIES_R7FA2A1
     bool
     select ARCH_ARM_CORTEX_M23
     select SOC_FAMILY_RENESAS_RA
-    default n
+    default n
+
+if RT_USING_NANO
+choice
+prompt "Choice nano console device(Renesas)"
+default RT_NANO_CONSOLE_UART0
+depends on RT_USING_CONSOLE
+config RT_NANO_CONSOLE_UART0
+    bool "UART0"
+config RT_NANO_CONSOLE_UART1
+    bool "UART1"
+config RT_NANO_CONSOLE_UART2
+    bool "UART2"
+config RT_NANO_CONSOLE_UART3
+    bool "UART3"
+config RT_NANO_CONSOLE_UART4
+    bool "UART4"
+config RT_NANO_CONSOLE_UART5
+    bool "UART5"
+config RT_NANO_CONSOLE_UART6
+    bool "UART6"
+config RT_NANO_CONSOLE_UART7
+    bool "UART7"
+config RT_NANO_CONSOLE_UART8
+    bool "UART8"
+config RT_NANO_CONSOLE_UART9
+    bool "UART9"
+endchoice
+endif

bsp/renesas/libraries/bsp-template/board/Kconfig

@@ -13,7 +13,7 @@ menu "Hardware Drivers Config"
 
     menu "On-chip Peripheral Drivers"
 
-        rsource "../../libraries/HAL_Drivers/Kconfig"
+        rsource "../../libraries/HAL_Drivers/drivers/Kconfig"
 
         menuconfig BSP_USING_UART
             bool "Enable UART"

bsp/renesas/ra2a1-ek/.config

@@ -1,3 +1,4 @@
+CONFIG_SOC_R7FA2A1AB=y
 
 #
 # RT-Thread Kernel
@@ -209,6 +210,7 @@ CONFIG_FINSH_THREAD_PRIORITY=20
 CONFIG_FINSH_THREAD_STACK_SIZE=4096
 CONFIG_FINSH_USING_HISTORY=y
 CONFIG_FINSH_HISTORY_LINES=5
+# CONFIG_FINSH_USING_WORD_OPERATION is not set
 CONFIG_FINSH_USING_SYMTAB=y
 CONFIG_FINSH_CMD_SIZE=80
 CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
@@ -386,6 +388,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0
 # CONFIG_PKG_USING_FREEMODBUS is not set
 # CONFIG_PKG_USING_NANOPB is not set
 # CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
+# CONFIG_PKG_USING_ESP_HOSTED is not set
 
 #
 # Wi-Fi
@@ -1392,7 +1395,6 @@ CONFIG_SOC_SERIES_R7FA2A1=y
 #
 # Hardware Drivers Config
 #
-CONFIG_SOC_R7FA2A1AB=y
 
 #
 # Onboard Peripheral Drivers
@@ -1411,6 +1413,8 @@ CONFIG_BSP_USING_UART0=y
 # CONFIG_BSP_UART0_TX_USING_DMA is not set
 CONFIG_BSP_UART0_RX_BUFSIZE=256
 CONFIG_BSP_UART0_TX_BUFSIZE=0
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART9 is not set
 # end of On-chip Peripheral Drivers
 
 #