rt-thread/bsp/microchip/saml10/bsp/atmel_start_config.atstart

format_version: '2'
name: SAML10 LED switcher
versions:
  api: '1.0'
  backend: 1.8.580
  commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c
  content: unknown
  content_pack_name: unknown
  format: '2'
  frontend: 1.8.580
  packs_version_avr8: 1.0.1463
  packs_version_qtouch: unknown
  packs_version_sam: 1.0.1726
  version_backend: 1.8.580
  version_frontend: ''
board:
  identifier: SAML10XplainedPro
  device: ATSAML10E16A-AU
details: null
application:
  definition: 'Atmel:Application_Examples:0.0.1::Application:EDBG_UART:'
  configuration: {}
middlewares: {}
drivers:
  ADC_0:
    user_label: ADC_0
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync
    functionality: ADC
    api: HAL:Driver:ADC_Sync
    configuration:
      adc_advanced_settings: true
      adc_arch_adjres: 0
      adc_arch_corren: false
      adc_arch_dbgrun: false
      adc_arch_event_settings: false
      adc_arch_flushei: false
      adc_arch_flushinv: false
      adc_arch_gaincorr: 0
      adc_arch_leftadj: false
      adc_arch_offcomp: false
      adc_arch_offsetcorr: 0
      adc_arch_ondemand: false
      adc_arch_refcomp: false
      adc_arch_resrdyeo: false
      adc_arch_runstdby: false
      adc_arch_samplen: 0
      adc_arch_samplenum: 4 samples
      adc_arch_seqen: 0
      adc_arch_startei: false
      adc_arch_startinv: false
      adc_arch_winlt: 0
      adc_arch_winmode: No window mode
      adc_arch_winmoneo: false
      adc_arch_winut: 0
      adc_differential_mode: false
      adc_freerunning_mode: false
      adc_pinmux_negative: Internal ground
      adc_pinmux_positive: ADC AIN0 pin
      adc_prescaler: Peripheral clock divided by 2
      adc_reference: VDDANA
      adc_resolution: 12-bit
    optional_signals:
    - identifier: ADC_0:AIN/0
      pad: PA02
      mode: Enabled
      configuration: null
      definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::optional_signal_definition::ADC.AIN.0
      name: ADC/AIN/0
      label: AIN/0
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: ADC
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        configuration:
          adc_gclk_selection: Generic clock generator 0
  DMAC:
    user_label: DMAC
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
    functionality: System
    api: HAL:HPL:DMAC
    configuration:
      dmac_beatsize_0: 8-bit bus transfer
      dmac_beatsize_1: 8-bit bus transfer
      dmac_beatsize_2: 8-bit bus transfer
      dmac_beatsize_3: 8-bit bus transfer
      dmac_beatsize_4: 8-bit bus transfer
      dmac_beatsize_5: 8-bit bus transfer
      dmac_beatsize_6: 8-bit bus transfer
      dmac_beatsize_7: 8-bit bus transfer
      dmac_blockact_0: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_1: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_2: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_3: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_4: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_5: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_6: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_blockact_7: Channel will be disabled if it is the last block transfer in
        the transaction
      dmac_channel_0_settings: false
      dmac_channel_1_settings: false
      dmac_channel_2_settings: false
      dmac_channel_3_settings: false
      dmac_channel_4_settings: false
      dmac_channel_5_settings: false
      dmac_channel_6_settings: false
      dmac_channel_7_settings: false
      dmac_dbgrun: false
      dmac_dqos: Background (no sensitive operation)
      dmac_dstinc_0: false
      dmac_dstinc_1: false
      dmac_dstinc_2: false
      dmac_dstinc_3: false
      dmac_dstinc_4: false
      dmac_dstinc_5: false
      dmac_dstinc_6: false
      dmac_dstinc_7: false
      dmac_enable: false
      dmac_enable_0: false
      dmac_enable_1: false
      dmac_enable_2: false
      dmac_enable_3: false
      dmac_enable_4: false
      dmac_enable_5: false
      dmac_enable_6: false
      dmac_enable_7: false
      dmac_evact_0: No action
      dmac_evact_1: No action
      dmac_evact_2: No action
      dmac_evact_3: No action
      dmac_evact_4: No action
      dmac_evact_5: No action
      dmac_evact_6: No action
      dmac_evact_7: No action
      dmac_evie_0: false
      dmac_evie_1: false
      dmac_evie_2: false
      dmac_evie_3: false
      dmac_evie_4: false
      dmac_evie_5: false
      dmac_evie_6: false
      dmac_evie_7: false
      dmac_evoe_0: false
      dmac_evoe_1: false
      dmac_evoe_2: false
      dmac_evoe_3: false
      dmac_evoe_4: false
      dmac_evoe_5: false
      dmac_evoe_6: false
      dmac_evoe_7: false
      dmac_evosel_0: Event generation disabled
      dmac_evosel_1: Event generation disabled
      dmac_evosel_2: Event generation disabled
      dmac_evosel_3: Event generation disabled
      dmac_evosel_4: Event generation disabled
      dmac_evosel_5: Event generation disabled
      dmac_evosel_6: Event generation disabled
      dmac_evosel_7: Event generation disabled
      dmac_fqos: Background (no sensitive operation)
      dmac_lvl_0: Channel priority 0
      dmac_lvl_1: Channel priority 0
      dmac_lvl_2: Channel priority 0
      dmac_lvl_3: Channel priority 0
      dmac_lvl_4: Channel priority 0
      dmac_lvl_5: Channel priority 0
      dmac_lvl_6: Channel priority 0
      dmac_lvl_7: Channel priority 0
      dmac_lvlen0: false
      dmac_lvlen1: false
      dmac_lvlen2: false
      dmac_lvlen3: false
      dmac_lvlpri0: 0
      dmac_lvlpri1: 0
      dmac_lvlpri2: 0
      dmac_lvlpri3: 0
      dmac_rrlvlen0: Static arbitration scheme for channel with priority 0
      dmac_rrlvlen1: Static arbitration scheme for channel with priority 1
      dmac_rrlvlen2: Static arbitration scheme for channel with priority 2
      dmac_rrlvlen3: Static arbitration scheme for channel with priority 3
      dmac_runstdby_0: false
      dmac_runstdby_1: false
      dmac_runstdby_2: false
      dmac_runstdby_3: false
      dmac_runstdby_4: false
      dmac_runstdby_5: false
      dmac_runstdby_6: false
      dmac_runstdby_7: false
      dmac_srcinc_0: false
      dmac_srcinc_1: false
      dmac_srcinc_2: false
      dmac_srcinc_3: false
      dmac_srcinc_4: false
      dmac_srcinc_5: false
      dmac_srcinc_6: false
      dmac_srcinc_7: false
      dmac_stepsel_0: Step size settings apply to the destination address
      dmac_stepsel_1: Step size settings apply to the destination address
      dmac_stepsel_2: Step size settings apply to the destination address
      dmac_stepsel_3: Step size settings apply to the destination address
      dmac_stepsel_4: Step size settings apply to the destination address
      dmac_stepsel_5: Step size settings apply to the destination address
      dmac_stepsel_6: Step size settings apply to the destination address
      dmac_stepsel_7: Step size settings apply to the destination address
      dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1
      dmac_trifsrc_0: Only software/event triggers
      dmac_trifsrc_1: Only software/event triggers
      dmac_trifsrc_2: Only software/event triggers
      dmac_trifsrc_3: Only software/event triggers
      dmac_trifsrc_4: Only software/event triggers
      dmac_trifsrc_5: Only software/event triggers
      dmac_trifsrc_6: Only software/event triggers
      dmac_trifsrc_7: Only software/event triggers
      dmac_trigact_0: One trigger required for each block transfer
      dmac_trigact_1: One trigger required for each block transfer
      dmac_trigact_2: One trigger required for each block transfer
      dmac_trigact_3: One trigger required for each block transfer
      dmac_trigact_4: One trigger required for each block transfer
      dmac_trigact_5: One trigger required for each block transfer
      dmac_trigact_6: One trigger required for each block transfer
      dmac_trigact_7: One trigger required for each block transfer
      dmac_wrbqos: Background (no sensitive operation)
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  GCLK:
    user_label: GCLK
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK
    functionality: System
    api: HAL:HPL:GCLK
    configuration:
      $input: 32000000
      $input_id: Digital Phase Locked Loop (DPLL)
      RESERVED_InputFreq: 32000000
      RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL)
      _$freq_output_Generic clock generator 0: 32000000
      _$freq_output_Generic clock generator 1: 32768
      _$freq_output_Generic clock generator 2: 400000
      _$freq_output_Generic clock generator 3: 32768
      _$freq_output_Generic clock generator 4: 400000
      enable_gclk_gen_0: true
      enable_gclk_gen_0__externalclock: 1000000
      enable_gclk_gen_1: true
      enable_gclk_gen_1__externalclock: 1000000
      enable_gclk_gen_2: false
      enable_gclk_gen_2__externalclock: 1000000
      enable_gclk_gen_3: false
      enable_gclk_gen_3__externalclock: 1000000
      enable_gclk_gen_4: false
      enable_gclk_gen_4__externalclock: 1000000
      gclk_arch_gen_0_enable: true
      gclk_arch_gen_0_idc: true
      gclk_arch_gen_0_oe: false
      gclk_arch_gen_0_oov: false
      gclk_arch_gen_0_runstdby: false
      gclk_arch_gen_1_enable: true
      gclk_arch_gen_1_idc: true
      gclk_arch_gen_1_oe: false
      gclk_arch_gen_1_oov: false
      gclk_arch_gen_1_runstdby: false
      gclk_arch_gen_2_enable: false
      gclk_arch_gen_2_idc: false
      gclk_arch_gen_2_oe: false
      gclk_arch_gen_2_oov: false
      gclk_arch_gen_2_runstdby: false
      gclk_arch_gen_3_enable: false
      gclk_arch_gen_3_idc: false
      gclk_arch_gen_3_oe: false
      gclk_arch_gen_3_oov: false
      gclk_arch_gen_3_runstdby: false
      gclk_arch_gen_4_enable: false
      gclk_arch_gen_4_idc: false
      gclk_arch_gen_4_oe: false
      gclk_arch_gen_4_oov: false
      gclk_arch_gen_4_runstdby: false
      gclk_gen_0_div: 1
      gclk_gen_0_div_sel: false
      gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL)
      gclk_gen_1_div: 1
      gclk_gen_1_div_sel: false
      gclk_gen_1_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
      gclk_gen_2_div: 1
      gclk_gen_2_div_sel: false
      gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
      gclk_gen_3_div: 1
      gclk_gen_3_div_sel: false
      gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K)
      gclk_gen_4_div: 1
      gclk_gen_4_div_sel: false
      gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC)
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  MCLK:
    user_label: MCLK
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK
    functionality: System
    api: HAL:HPL:MCLK
    configuration:
      $input: 32000000
      $input_id: Generic clock generator 0
      RESERVED_InputFreq: 32000000
      RESERVED_InputFreq_id: Generic clock generator 0
      _$freq_output_CPU: 32000000
      cpu_clock_source: Generic clock generator 0
      cpu_div: '1'
      enable_cpu_clock: true
      nvm_wait_states: '3'
      performance_level: Performance Level 0 (PL0)
    optional_signals: []
    variant: null
    clocks:
      domain_group:
        nodes:
        - name: CPU
          input: CPU
          external: false
          external_frequency: 0
        configuration: {}
  OSC32KCTRL:
    user_label: OSC32KCTRL
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL
    functionality: System
    api: HAL:HPL:OSC32KCTRL
    configuration:
      $input: 32768
      $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      RESERVED_InputFreq: 32768
      RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      _$freq_output_RTC source: 1024
      enable_osculp32k: true
      enable_rtc_source: false
      enable_xosc32k: true
      osculp32k_arch_ulp32ksw: false
      osculp32k_calib: 0
      osculp32k_calib_enable: false
      rtc_1khz_selection: true
      rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
      xosc32k_arch_cfden: false
      xosc32k_arch_cfdeo: false
      xosc32k_arch_en1k: false
      xosc32k_arch_en32k: false
      xosc32k_arch_enable: true
      xosc32k_arch_ondemand: false
      xosc32k_arch_runstdby: false
      xosc32k_arch_startup: 125092us
      xosc32k_arch_swben: false
      xosc32k_arch_xtalen: true
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  OSCCTRL:
    user_label: OSCCTRL
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL
    functionality: System
    api: HAL:HPL:OSCCTRL
    configuration:
      $input: 32768
      $input_id: Generic clock generator 1
      RESERVED_InputFreq: 32768
      RESERVED_InputFreq_id: Generic clock generator 1
      _$freq_output_16MHz Internal Oscillator (OSC16M): 4000000
      _$freq_output_DFLLULP clock: 4194304
      _$freq_output_Digital Frequency Locked Loop (DFLLULP): 4194304
      _$freq_output_Digital Phase Locked Loop (DPLL): 32000000
      _$freq_output_External Crystal Oscillator 0.4-32MHz (XOSC): 400000
      dfllulp_arch_binse: false
      dfllulp_arch_delay: 128
      dfllulp_arch_dither: false
      dfllulp_arch_dither_per: Dither over 1 reference clock period
      dfllulp_arch_dither_step: Dither step is 1
      dfllulp_arch_enable: true
      dfllulp_arch_ondemand: true
      dfllulp_arch_ratio: 128
      dfllulp_arch_runstdby: false
      dfllulp_arch_safe: false
      dfllulp_mode: Closed Loop Mode
      dfllulp_ref_clock: Generic clock generator 1
      dfllulp_source_oscillator: Digital Frequency Locked Loop (DFLLULP)
      enable_dfllulp: true
      enable_dfllulp_as_mclk_source: false
      enable_fdpll96m: true
      enable_osc16m: true
      enable_xosc: false
      fdpll96m_arch_enable: true
      fdpll96m_arch_filter: Default filter mode
      fdpll96m_arch_lbypass: false
      fdpll96m_arch_lpen: false
      fdpll96m_arch_ltime: No time-out, automatic lock
      fdpll96m_arch_ondemand: true
      fdpll96m_arch_refclk: XOSC32K clock reference
      fdpll96m_arch_runstdby: false
      fdpll96m_arch_wuf: false
      fdpll96m_clock_div: 0
      fdpll96m_ldr: 975
      fdpll96m_ldrfrac: 9
      fdpll96m_presc: '1'
      fdpll96m_ref_clock: Generic clock generator 1
      osc16m_arch_enable: true
      osc16m_arch_ondemand: true
      osc16m_arch_runstdby: false
      osc16m_freq: '4'
      xosc_arch_ampgc: false
      xosc_arch_cfden: false
      xosc_arch_cfdeo: false
      xosc_arch_enable: false
      xosc_arch_gain: 2MHz
      xosc_arch_ondemand: true
      xosc_arch_runstdby: false
      xosc_arch_startup: 31us
      xosc_arch_swben: false
      xosc_arch_xtalen: false
      xosc_frequency: 400000
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  PORT:
    user_label: PORT
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT
    functionality: System
    api: HAL:HPL:PORT
    configuration:
      enable_port_input_event_0: false
      enable_port_input_event_1: false
      enable_port_input_event_2: false
      enable_port_input_event_3: false
      porta_event_action_0: Output register of pin will be set to level of event
      porta_event_action_1: Output register of pin will be set to level of event
      porta_event_action_2: Output register of pin will be set to level of event
      porta_event_action_3: Output register of pin will be set to level of event
      porta_event_pin_identifier_0: 0
      porta_event_pin_identifier_1: 0
      porta_event_pin_identifier_2: 0
      porta_event_pin_identifier_3: 0
      porta_input_event_enable_0: false
      porta_input_event_enable_1: false
      porta_input_event_enable_2: false
      porta_input_event_enable_3: false
    optional_signals: []
    variant: null
    clocks:
      domain_group: null
  I2C_0:
    user_label: I2C_0
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
    functionality: I2C
    api: HAL:Driver:I2C_Master_Sync
    configuration:
      i2c_master_advanced: true
      i2c_master_arch_dbgstop: Keep running
      i2c_master_arch_inactout: 20-21 SCL cycle time-out(200-210us)
      i2c_master_arch_lowtout: true
      i2c_master_arch_mexttoen: true
      i2c_master_arch_runstdby: false
      i2c_master_arch_sdahold: 400-800ns hold time
      i2c_master_arch_sexttoen: false
      i2c_master_arch_trise: 215
      i2c_master_baud_rate: 100000
    optional_signals: []
    variant:
      specification: SDA=0, SCL=1
      required_signals:
      - name: SERCOM0/PAD/0
        pad: PA16
        label: SDA
      - name: SERCOM0/PAD/1
        pad: PA17
        label: SCL
    clocks:
      domain_group:
        nodes:
        - name: Core
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Slow
          input: Generic clock generator 1
          external: false
          external_frequency: 0
        configuration:
          core_gclk_selection: Generic clock generator 0
          slow_gclk_selection: Generic clock generator 1
  TARGET_IO:
    user_label: TARGET_IO
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async
    functionality: USART
    api: HAL:Driver:USART_Async
    configuration:
      usart_advanced: true
      usart_arch_clock_mode: USART with internal clock
      usart_arch_cloden: false
      usart_arch_dbgstop: Keep running
      usart_arch_dord: LSB is transmitted first
      usart_arch_enc: No encoding
      usart_arch_fractional: 0
      usart_arch_ibon: false
      usart_arch_lin_slave_enable: Disable
      usart_arch_runstdby: false
      usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling)
      usart_arch_sampr: 16x arithmetic
      usart_arch_sfde: false
      usart_baud_rate: 115200
      usart_character_size: 8 bits
      usart_parity: No parity
      usart_rx_enable: true
      usart_stop_bit: One stop bit
      usart_tx_enable: true
    optional_signals: []
    variant:
      specification: TXPO=1, RXPO=3, CMODE=0
      required_signals:
      - name: SERCOM2/PAD/2
        pad: PA24
        label: TX
      - name: SERCOM2/PAD/3
        pad: PA25
        label: RX
    clocks:
      domain_group:
        nodes:
        - name: Core
          input: Generic clock generator 0
          external: false
          external_frequency: 0
        - name: Slow
          input: Generic clock generator 1
          external: false
          external_frequency: 0
        configuration:
          core_gclk_selection: Generic clock generator 0
          slow_gclk_selection: Generic clock generator 1
pads:
  PA02:
    name: PA02
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA02
    mode: Analog
    user_label: PA02
    configuration: null
  LED0:
    name: PA07
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA07
    mode: Digital output
    user_label: LED0
    configuration: null
  PA16:
    name: PA16
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA16
    mode: I2C
    user_label: PA16
    configuration: null
  PA17:
    name: PA17
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA17
    mode: I2C
    user_label: PA17
    configuration: null
  EDBG_COM_TX:
    name: PA24
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA24
    mode: Peripheral IO
    user_label: EDBG_COM_TX
    configuration: null
  EDBG_COM_RX:
    name: PA25
    definition: Atmel:SAML10_Drivers:0.0.1::ATSAML10E16A-AU::pad::PA25
    mode: Peripheral IO
    user_label: EDBG_COM_RX
    configuration: null
toolchain_options: []
static_files: []