rt-thread/bsp/hpmicro/hpm6p00evk/board/board.c

/*
 * Copyright (c) 2024,2025 HPMicro
 * SPDX-License-Identifier: BSD-3-Clause
 *
 *
 */

#include "board.h"
#include "hpm_uart_drv.h"
#include "hpm_gptmr_drv.h"
#include "hpm_i2c_drv.h"
#include "hpm_gpio_drv.h"
#include "pinmux.h"
#include "hpm_pmp_drv.h"
#include "hpm_clock_drv.h"
#include "hpm_sysctl_drv.h"
#include "hpm_pllctlv2_drv.h"
#include "hpm_pcfg_drv.h"
#include "hpm_enet_drv.h"
#include "hpm_usb_drv.h"
#include "hpm_femc_drv.h"
#include <rtconfig.h>

/**
 * @brief FLASH configuration option definitions:
 * option[0]:
 *    [31:16] 0xfcf9 - FLASH configuration option tag
 *    [15:4]  0 - Reserved
 *    [3:0]   option words (exclude option[0])
 * option[1]:
 *    [31:28] Flash probe type
 *      0 - SFDP SDR / 1 - SFDP DDR
 *      2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
 *      4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
 *      6 - OctaBus DDR (SPI -> OPI DDR)
 *      8 - Xccela DDR (SPI -> OPI DDR)
 *      10 - EcoXiP DDR (SPI -> OPI DDR)
 *    [27:24] Command Pads after Power-on Reset
 *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
 *    [23:20] Command Pads after Configuring FLASH
 *      0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
 *    [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
 *      0 - Not needed
 *      1 - QE bit is at bit 6 in Status Register 1
 *      2 - QE bit is at bit1 in Status Register 2
 *      3 - QE bit is at bit7 in Status Register 2
 *      4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
 *    [15:8] Dummy cycles
 *      0 - Auto-probed / detected / default value
 *      Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
 *    [7:4] Misc.
 *      0 - Not used
 *      1 - SPI mode
 *      2 - Internal loopback
 *      3 - External DQS
 *    [3:0] Frequency option
 *      1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 114MHz / 7 - 133MHz / 8 - 166MHz
 *
 * option[2] (Effective only if the bit[3:0] in option[0] > 1)
 *    [31:20]  Reserved
 *    [19:16] IO voltage
 *      0 - 3V / 1 - 1.8V
 *    [15:12] Pin group
 *      0 - 1st group / 1 - 2nd group
 *    [11:8] Connection selection
 *      0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
 *    [7:0] Drive Strength
 *      0 - Default value
 * option[3] (Effective only if the bit[3:0] in option[0] > 2, required only for the QSPI NOR FLASH that not supports
 *              JESD216)
 *    [31:16] reserved
 *    [15:12] Sector Erase Command Option, not required here
 *    [11:8]  Sector Size Option, not required here
 *    [7:0] Flash Size Option
 *      0 - 4MB / 1 - 8MB / 2 - 16MB
 */
#if defined(FLASH_XIP) && FLASH_XIP
__attribute__((section(".nor_cfg_option"), used)) const uint32_t option[4] = { 0xfcf90002, 0x00000005, 0x1000, 0x0 };
#endif

#if defined(FLASH_UF2) && FLASH_UF2
ATTR_PLACE_AT(".uf2_signature") __attribute__((used)) const uint32_t uf2_signature = BOARD_UF2_SIGNATURE;
#endif

void board_init_console(void)
{
#if !defined(CONFIG_NDEBUG_CONSOLE) || !CONFIG_NDEBUG_CONSOLE
#if BOARD_CONSOLE_TYPE == CONSOLE_TYPE_UART
    console_config_t cfg;

    /* uart needs to configure pin function before enabling clock, otherwise the level change of
     * uart rx pin when configuring pin function will cause a wrong data to be received.
     * And a uart rx dma request will be generated by default uart fifo dma trigger level.
     */
    init_uart_pins((UART_Type *) BOARD_CONSOLE_UART_BASE);

    clock_add_to_group(BOARD_CONSOLE_UART_CLK_NAME, 0);

    cfg.type = BOARD_CONSOLE_TYPE;
    cfg.base = (uint32_t) BOARD_CONSOLE_UART_BASE;
    cfg.src_freq_in_hz = clock_get_frequency(BOARD_CONSOLE_UART_CLK_NAME);
    cfg.baudrate = BOARD_CONSOLE_UART_BAUDRATE;

    if (status_success != console_init(&cfg)) {
        /* failed to  initialize debug console */
        while (1) {
        }
    }
#else
    while (1)
        ;
#endif
#endif
}

void board_print_clock_freq(void)
{
    printf("==============================\n");
    printf(" %s clock summary\n", BOARD_NAME);
    printf("==============================\n");
    printf("cpu0:\t\t %dHz\n", clock_get_frequency(clock_cpu0));
    printf("cpu1:\t\t %dHz\n", clock_get_frequency(clock_cpu1));
    printf("ahb:\t\t %luHz\n", clock_get_frequency(clock_ahb0));
    printf("axif:\t\t %dHz\n", clock_get_frequency(clock_axif));
    printf("axis:\t\t %dHz\n", clock_get_frequency(clock_axis));
    printf("axic:\t\t %dHz\n", clock_get_frequency(clock_axic));
    printf("xpi0:\t\t %dHz\n", clock_get_frequency(clock_xpi0));
    printf("femc:\t\t %luHz\n", clock_get_frequency(clock_femc));
    printf("mchtmr0:\t %dHz\n", clock_get_frequency(clock_mchtmr0));
    printf("mchtmr1:\t %dHz\n", clock_get_frequency(clock_mchtmr1));
    printf("==============================\n");
}

void board_init_uart(UART_Type *ptr)
{
    /* configure uart's pin before opening uart's clock */
    init_uart_pins(ptr);
    board_init_uart_clock(ptr);
}

void board_print_banner(void)
{
    const uint8_t banner[] = { "\n\
----------------------------------------------------------------------\n\
$$\\   $$\\ $$$$$$$\\  $$\\      $$\\ $$\\\n\
$$ |  $$ |$$  __$$\\ $$$\\    $$$ |\\__|\n\
$$ |  $$ |$$ |  $$ |$$$$\\  $$$$ |$$\\  $$$$$$$\\  $$$$$$\\   $$$$$$\\\n\
$$$$$$$$ |$$$$$$$  |$$\\$$\\$$ $$ |$$ |$$  _____|$$  __$$\\ $$  __$$\\\n\
$$  __$$ |$$  ____/ $$ \\$$$  $$ |$$ |$$ /      $$ |  \\__|$$ /  $$ |\n\
$$ |  $$ |$$ |      $$ |\\$  /$$ |$$ |$$ |      $$ |      $$ |  $$ |\n\
$$ |  $$ |$$ |      $$ | \\_/ $$ |$$ |\\$$$$$$$\\ $$ |      \\$$$$$$  |\n\
\\__|  \\__|\\__|      \\__|     \\__|\\__| \\_______|\\__|       \\______/\n\
----------------------------------------------------------------------\n" };
#ifdef SDK_VERSION_STRING
    printf("hpm_sdk: %s\n", SDK_VERSION_STRING);
#endif
    printf("%s", banner);
}

void board_ungate_mchtmr_at_lp_mode(void)
{
    /* Keep cpu clock on wfi, so that mchtmr irq can still work after wfi */
    sysctl_set_cpu_lp_mode(HPM_SYSCTL, BOARD_RUNNING_CORE, cpu_lp_mode_ungate_cpu_clock);
}

void board_init(void)
{
    board_init_clock();
    board_init_console();
    board_init_pmp();
#if BOARD_SHOW_CLOCK
    board_print_clock_freq();
#endif
#if BOARD_SHOW_BANNER
    board_print_banner();
#endif
}

void board_init_core1(void)
{
    clock_update_core_clock();
    board_init_console();
    board_init_pmp();
}

void board_init_sdram_pins(void)
{
    init_femc_pins();
}

uint32_t board_init_femc_clock(void)
{
    clock_add_to_group(clock_femc, 0);

    /* Default FEMC clock is 166MHz */

    /* Configure the FEMC to clk_src_pll1_clk0 / div, the clk_src_pll1_clk0 default frequency is 800MHz. */
    clock_set_source_divider(clock_femc, clk_src_pll1_clk0, 6U);    /* Set FEMC clock to 133MHz */

    return clock_get_frequency(clock_femc);
}

void board_delay_us(uint32_t us)
{
    clock_cpu_delay_us(us);
}

void board_delay_ms(uint32_t ms)
{
    clock_cpu_delay_ms(ms);
}

#if !defined(NO_BOARD_TIMER_SUPPORT) || !NO_BOARD_TIMER_SUPPORT
static board_timer_cb timer_cb;
SDK_DECLARE_EXT_ISR_M(BOARD_CALLBACK_TIMER_IRQ, board_timer_isr)
void board_timer_isr(void)
{
    if (gptmr_check_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH))) {
        gptmr_clear_status(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_STAT_MASK(BOARD_CALLBACK_TIMER_CH));
        timer_cb();
    }
}

void board_timer_create(uint32_t ms, board_timer_cb cb)
{
    uint32_t gptmr_freq;
    gptmr_channel_config_t config;

    timer_cb = cb;
    gptmr_channel_get_default_config(BOARD_CALLBACK_TIMER, &config);

    clock_add_to_group(BOARD_CALLBACK_TIMER_CLK_NAME, 0);
    gptmr_freq = clock_get_frequency(BOARD_CALLBACK_TIMER_CLK_NAME);

    config.reload = gptmr_freq / 1000 * ms;
    gptmr_channel_config(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH, &config, false);
    gptmr_enable_irq(BOARD_CALLBACK_TIMER, GPTMR_CH_RLD_IRQ_MASK(BOARD_CALLBACK_TIMER_CH));
    intc_m_enable_irq_with_priority(BOARD_CALLBACK_TIMER_IRQ, 1);

    gptmr_start_counter(BOARD_CALLBACK_TIMER, BOARD_CALLBACK_TIMER_CH);
}
#endif

void board_i2c_bus_clear(I2C_Type *ptr)
{
    if (i2c_get_line_scl_status(ptr) == false) {
        printf("CLK is low, please power cycle the board\n");
        while (1) {
        }
    }
    if (i2c_get_line_sda_status(ptr) == false) {
        printf("SDA is low, try to issue I2C bus clear\n");
    } else {
        printf("I2C bus is ready\n");
        return;
    }
    i2c_gen_reset_signal(ptr, 9);
    board_delay_ms(100);
    printf("I2C bus is cleared\n");
}

uint32_t board_init_i2c_clock(I2C_Type *ptr)
{
    uint32_t freq = 0;

    if (ptr == HPM_I2C0) {
        clock_add_to_group(clock_i2c0, 0);
        freq = clock_get_frequency(clock_i2c0);
    } else if (ptr == HPM_I2C1) {
        clock_add_to_group(clock_i2c1, 0);
        freq = clock_get_frequency(clock_i2c1);
    } else if (ptr == HPM_I2C2) {
        clock_add_to_group(clock_i2c2, 0);
        freq = clock_get_frequency(clock_i2c2);
    } else if (ptr == HPM_I2C3) {
        clock_add_to_group(clock_i2c3, 0);
        freq = clock_get_frequency(clock_i2c3);
    } else {
        ;
    }

    return freq;
}

void board_init_i2c(I2C_Type *ptr)
{
    i2c_config_t config;
    hpm_stat_t stat;
    uint32_t freq;

    freq = board_init_i2c_clock(ptr);
    init_i2c_pins(ptr);
    board_i2c_bus_clear(ptr);

    config.i2c_mode = i2c_mode_normal;
    config.is_10bit_addressing = false;
    stat = i2c_init_master(ptr, freq, &config);
    if (stat != status_success) {
        printf("failed to initialize i2c 0x%lx\n", (uint32_t) ptr);
        while (1) {
        }
    }
}

uint32_t board_init_spi_clock(SPI_Type *ptr)
{
    if (ptr == HPM_SPI0) {
        clock_add_to_group(clock_spi0, 0);
        return clock_get_frequency(clock_spi0);
    } else if (ptr == HPM_SPI1) {
        clock_add_to_group(clock_spi1, 0);
        return clock_get_frequency(clock_spi1);
    } else if (ptr == HPM_SPI2) {
        clock_add_to_group(clock_spi2, 0);
        return clock_get_frequency(clock_spi2);
    } else if (ptr == HPM_SPI3) {
        clock_add_to_group(clock_spi3, 0);
        return clock_get_frequency(clock_spi3);
    }
    return 0;
}

void board_init_gpio_pins(void)
{
    init_gpio_pins();
}

void board_init_spi_pins(SPI_Type *ptr)
{
    init_spi_pins(ptr);
}

void board_init_spi_pins_with_gpio_as_cs(SPI_Type *ptr)
{
    init_spi_pins_with_gpio_as_cs(ptr);
    gpio_set_pin_output_with_initial(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(BOARD_SPI_CS_PIN),
                                    GPIO_GET_PIN_INDEX(BOARD_SPI_CS_PIN), !BOARD_SPI_CS_ACTIVE_LEVEL);
}

void board_write_spi_cs(uint32_t pin, uint8_t state)
{
    gpio_write_pin(BOARD_SPI_CS_GPIO_CTRL, GPIO_GET_PORT_INDEX(pin), GPIO_GET_PIN_INDEX(pin), state);
}

uint8_t board_get_led_pwm_off_level(void)
{
    return BOARD_LED_OFF_LEVEL;
}

uint8_t board_get_led_gpio_off_level(void)
{
    return BOARD_LED_OFF_LEVEL;
}

void board_init_led_pins(void)
{
    init_led_pins_as_gpio();
    gpio_set_pin_output_with_initial(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, board_get_led_gpio_off_level());
}

void board_led_toggle(void)
{
    gpio_toggle_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN);
}

void board_led_write(uint8_t state)
{
    gpio_write_pin(BOARD_LED_GPIO_CTRL, BOARD_LED_GPIO_INDEX, BOARD_LED_GPIO_PIN, state);
}

void board_init_pmp(void)
{
    uint32_t start_addr;
    uint32_t end_addr;
    uint32_t length;
    pmp_entry_t pmp_entry[16];
    uint8_t index = 0;

    /* Init noncachable memory */
    extern uint32_t __noncacheable_start__[];
    extern uint32_t __noncacheable_end__[];
    start_addr = (uint32_t) __noncacheable_start__;
    end_addr = (uint32_t) __noncacheable_end__;
    length = end_addr - start_addr;
    if (length > 0) {
        /* Ensure the address and the length are power of 2 aligned */
        assert((length & (length - 1U)) == 0U);
        assert((start_addr & (length - 1U)) == 0U);
        pmp_entry[index].pmp_addr = PMP_NAPOT_ADDR(start_addr, length);
        pmp_entry[index].pmp_cfg.val = PMP_CFG(READ_EN, WRITE_EN, EXECUTE_EN, ADDR_MATCH_NAPOT, REG_UNLOCK);
        pmp_entry[index].pma_addr = PMA_NAPOT_ADDR(start_addr, length);
        pmp_entry[index].pma_cfg.val = PMA_CFG(ADDR_MATCH_NAPOT, MEM_TYPE_MEM_NON_CACHE_BUF, AMO_EN);
        index++;
    }

    pmp_config(&pmp_entry[0], index);
}

void board_init_clock(void)
{
    uint32_t cpu0_freq = clock_get_frequency(clock_cpu0);
    if (cpu0_freq == PLLCTL_SOC_PLL_REFCLK_FREQ) {
        /* Configure the External OSC ramp-up time: ~9ms */
        pllctlv2_xtal_set_rampup_time(HPM_PLLCTLV2, 32ul * 1000ul * 9u);

        /* select clock setting preset1 */
        sysctl_clock_set_preset(HPM_SYSCTL, 2);
    }
    /* Add Clocks to group 0 */
    clock_add_to_group(clock_cpu0, 0);
    clock_add_to_group(clock_mchtmr0, 0);
    clock_add_to_group(clock_ahb0, 0);
    clock_add_to_group(clock_axif, 0);
    clock_add_to_group(clock_axis, 0);
    clock_add_to_group(clock_axic, 0);
    clock_add_to_group(clock_rom0, 0);
    clock_add_to_group(clock_xpi0, 0);
    clock_add_to_group(clock_lmm0, 0);
    clock_add_to_group(clock_lmm1, 0);
    clock_add_to_group(clock_ram0, 0);
    clock_add_to_group(clock_hdma, 0);
    clock_add_to_group(clock_xdma, 0);
    clock_add_to_group(clock_gpio, 0);
    clock_add_to_group(clock_ptpc, 0);
    /* Motor Related */
    clock_add_to_group(clock_qei0, 0);
    clock_add_to_group(clock_qei1, 0);
    clock_add_to_group(clock_qeo0, 0);
    clock_add_to_group(clock_qeo1, 0);
    clock_add_to_group(clock_pwm0, 0);
    clock_add_to_group(clock_pwm1, 0);
    clock_add_to_group(clock_pwm2, 0);
    clock_add_to_group(clock_pwm3, 0);
    clock_add_to_group(clock_rdc0, 0);
    clock_add_to_group(clock_plb0, 0);
    clock_add_to_group(clock_sei0, 0);
    clock_add_to_group(clock_mtg0, 0);
    clock_add_to_group(clock_vsc0, 0);
    clock_add_to_group(clock_clc0, 0);
    clock_add_to_group(clock_emds, 0);
    /* Connect Group0 to CPU0 */
    clock_connect_group_to_cpu(0, 0);

    /* Add the CPU1 clock to Group1 */
    clock_add_to_group(clock_cpu1, 1);
    clock_add_to_group(clock_mchtmr1, 1);
    /* Connect Group1 to CPU1 */
    clock_connect_group_to_cpu(1, 1);

    /* Bump up DCDC voltage to 1275mv */
    pcfg_dcdc_set_voltage(HPM_PCFG, 1275);

    /* Set CPU clock to 600MHz */
    clock_set_source_divider(clock_cpu0, clk_src_pll0_clk0, 1);
    clock_set_source_divider(clock_cpu1, clk_src_pll0_clk0, 1);

    /* Configure mchtmr to 24MHz */
    clock_set_source_divider(clock_mchtmr0, clk_src_osc24m, 1);
    clock_set_source_divider(clock_mchtmr1, clk_src_osc24m, 1);

    clock_update_core_clock();
}

uint32_t board_init_uart_clock(UART_Type *ptr)
{
    uint32_t freq = 0U;
    if (ptr == HPM_UART0) {
        clock_add_to_group(clock_uart0, 0);
        freq = clock_get_frequency(clock_uart0);
    } else if (ptr == HPM_UART1) {
        clock_add_to_group(clock_uart1, 0);
        freq = clock_get_frequency(clock_uart1);
    } else if (ptr == HPM_UART2) {
        clock_add_to_group(clock_uart2, 0);
        freq = clock_get_frequency(clock_uart2);
    } else if (ptr == HPM_UART3) {
        clock_add_to_group(clock_uart3, 0);
        freq = clock_get_frequency(clock_uart3);
    } else if (ptr == HPM_UART4) {
        clock_add_to_group(clock_uart4, 0);
        freq = clock_get_frequency(clock_uart4);
    } else if (ptr == HPM_UART5) {
        clock_add_to_group(clock_uart5, 0);
        freq = clock_get_frequency(clock_uart5);
    } else if (ptr == HPM_UART6) {
        clock_add_to_group(clock_uart6, 0);
        freq = clock_get_frequency(clock_uart6);
    } else if (ptr == HPM_UART7) {
        clock_add_to_group(clock_uart7, 0);
        freq = clock_get_frequency(clock_uart7);
    } else {
        /* Not supported */
    }
    return freq;
}

#ifdef INIT_EXT_RAM_FOR_DATA
/*
 * this function will be called during startup to initialize external memory for data use
 */
void _init_ext_ram(void)
{
    uint32_t femc_clk_in_hz;
    femc_config_t config = {0};
    femc_sdram_config_t sdram_config = {0};

    board_init_sdram_pins();
    femc_clk_in_hz = board_init_femc_clock();
    femc_default_config(HPM_FEMC, &config);
    femc_init(HPM_FEMC, &config);

    femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);

    sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
    sdram_config.prescaler = 0x3;
    sdram_config.burst_len_in_byte = 8;
    sdram_config.auto_refresh_count_in_one_burst = 1;
    sdram_config.col_addr_bits = BOARD_SDRAM_COLUMN_ADDR_BITS;
    sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;

    sdram_config.refresh_to_refresh_in_ns = 60;     /* Trc */
    sdram_config.refresh_recover_in_ns = 60;        /* Trc */
    sdram_config.act_to_precharge_in_ns = 42;       /* Tras */
    sdram_config.act_to_rw_in_ns = 18;              /* Trcd */
    sdram_config.precharge_to_act_in_ns = 18;       /* Trp */
    sdram_config.act_to_act_in_ns = 12;             /* Trrd */
    sdram_config.write_recover_in_ns = 12;          /* Twr/Tdpl */
    sdram_config.self_refresh_recover_in_ns = 72;   /* Txsr */

    sdram_config.cs = BOARD_SDRAM_CS;
    sdram_config.base_address = BOARD_SDRAM_ADDRESS;
    sdram_config.size_in_byte = BOARD_SDRAM_SIZE;
    sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
    sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
    sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
    sdram_config.delay_cell_disable = false;
    sdram_config.delay_cell_value = 13;

    femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
}
#endif

void board_init_usb(USB_Type *ptr)
{
    if (ptr == HPM_USB0) {
        init_usb_pins(ptr);
        clock_add_to_group(clock_usb0, 0);

        usb_hcd_set_power_ctrl_polarity(ptr, true);
        /* Wait USB_PWR pin control vbus power stable. Time depend on decoupling capacitor, you can decrease or increase this time */
        board_delay_ms(100);
    }
}

uint32_t board_init_dao_clock(void)
{
    clock_add_to_group(clock_dao, 0);

    board_config_i2s_clock(DAO_I2S, 48000);

    return clock_get_frequency(clock_dao);
}

uint32_t board_init_pdm_clock(void)
{
    clock_add_to_group(clock_pdm, 0);

    board_config_i2s_clock(PDM_I2S, 16000);

    return clock_get_frequency(clock_pdm);
}

void board_init_i2s_pins(I2S_Type *ptr)
{
    init_i2s_pins(ptr);
}

uint32_t board_config_i2s_clock(I2S_Type *ptr, uint32_t sample_rate)
{
    uint32_t freq = 0;

    if (ptr == HPM_I2S0) {
        clock_add_to_group(clock_i2s0, 0);
        if ((sample_rate % 22050) == 0) {
            clock_set_source_divider(clock_aud0, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */
        } else {
            clock_set_source_divider(clock_aud0, clk_src_pll2_clk0, 21); /* default 24576000Hz */
        }
        clock_set_i2s_source(clock_i2s0, clk_i2s_src_audn);  /* clk_i2s_src_audn is equal to clk_i2s_src_aud0 */
        freq = clock_get_frequency(clock_i2s0);
    } else if (ptr == HPM_I2S1) {
        clock_add_to_group(clock_i2s1, 0);
        if ((sample_rate % 22050) == 0) {
            clock_set_source_divider(clock_aud1, clk_src_pll1_clk0, 71); /* config clock_aud1 for 22050*n sample rate */
        } else {
            clock_set_source_divider(clock_aud1, clk_src_pll2_clk0, 21); /* default 24576000Hz */
        }
        clock_set_i2s_source(clock_i2s1, clk_i2s_src_audn);  /* clk_i2s_src_audn is equal to clk_i2s_src_aud1 */
        freq = clock_get_frequency(clock_i2s1);
    } else {
        ;
    }

    return freq;
}

void board_init_adc16_pins(void)
{
    init_adc16_pins();
}

uint32_t board_init_adc_clock(void *ptr, bool clk_src_bus)  /* motor system should be use clk_adc_src_ahb0 */
{
    uint32_t freq = 0;

    if (ptr == (void *)HPM_ADC0) {
        clock_add_to_group(clock_adc0, 0);
        if (clk_src_bus) {
            /* Configure the ADC clock from AHB (@200MHz by default)*/
            clock_set_adc_source(clock_adc0, clk_adc_src_ahb0);
        } else {
            /* Configure the ADC clock from ANA (@200MHz by default)*/
            clock_set_adc_source(clock_adc0, clk_adc_src_ana0);
            clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
        }
        freq = clock_get_frequency(clock_adc0);
    } else if (ptr == (void *)HPM_ADC1) {
        clock_add_to_group(clock_adc1, 0);
        if (clk_src_bus) {
            /* Configure the ADC clock from AHB (@200MHz by default)*/
            clock_set_adc_source(clock_adc1, clk_adc_src_ahb0);
        } else {
            /* Configure the ADC clock from ANA (@200MHz by default)*/
            clock_set_adc_source(clock_adc1, clk_adc_src_ana1);
            clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
        }
        freq = clock_get_frequency(clock_adc1);
    } else if (ptr == (void *)HPM_ADC2) {
        clock_add_to_group(clock_adc2, 0);
        if (clk_src_bus) {
            /* Configure the ADC clock from AHB (@200MHz by default)*/
            clock_set_adc_source(clock_adc2, clk_adc_src_ahb0);
        } else {
            /* Configure the ADC clock from ANA (@200MHz by default)*/
            clock_set_adc_source(clock_adc2, clk_adc_src_ana2);
            clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
        }
        freq = clock_get_frequency(clock_adc2);
    } else if (ptr == (void *)HPM_ADC3) {
        clock_add_to_group(clock_adc3, 0);
        if (clk_src_bus) {
            /* Configure the ADC clock from AHB (@200MHz by default)*/
            clock_set_adc_source(clock_adc3, clk_adc_src_ahb0);
        } else {
            /* Configure the ADC clock from ANA (@200MHz by default)*/
            clock_set_adc_source(clock_adc3, clk_adc_src_ana3);
            clock_set_source_divider(clock_ana0, clk_src_pll1_clk0, 4U);
        }
        freq = clock_get_frequency(clock_adc3);
    } else {
        ;
    }

    return freq;
}

void board_init_acmp_pins(void)
{
    init_acmp_pins();
}

void board_init_acmp_clock(ACMP_Type *ptr)
{
    (void)ptr;
    clock_add_to_group(BOARD_ACMP_CLK, BOARD_RUNNING_CORE & 0x1);
}

void board_init_can(MCAN_Type *ptr)
{
    init_can_pins(ptr);
}

uint32_t board_init_can_clock(MCAN_Type *ptr)
{
    uint32_t freq = 0;
    if (ptr == HPM_MCAN0) {
        /* Set the CAN0 peripheral clock to 80MHz */
        clock_add_to_group(clock_can0, 0);
        clock_set_source_divider(clock_can0, clk_src_pll1_clk0, 10);
        freq = clock_get_frequency(clock_can0);
    } else if (ptr == HPM_MCAN1) {
        /* Set the CAN1 peripheral clock to 80MHz */
        clock_add_to_group(clock_can1, 0);
        clock_set_source_divider(clock_can1, clk_src_pll1_clk0, 10);
        freq = clock_get_frequency(clock_can1);
    } else if (ptr == HPM_MCAN2) {
        /* Set the CAN2 peripheral clock to 80MHz */
        clock_add_to_group(clock_can2, 0);
        clock_set_source_divider(clock_can2, clk_src_pll1_clk0, 10);
        freq = clock_get_frequency(clock_can2);
    } else if (ptr == HPM_MCAN3) {
        /* Set the CAN3 peripheral clock to 80MHz */
        clock_add_to_group(clock_can3, 0);
        clock_set_source_divider(clock_can3, clk_src_pll1_clk0, 10);
        freq = clock_get_frequency(clock_can3);
    } else {
        /* Invalid CAN instance */
    }
    return freq;
}

hpm_stat_t board_init_enet_ptp_clock(ENET_Type *ptr)
{
    /* set clock source */
    if (ptr == HPM_ENET0) {
        clock_add_to_group(clock_ptp0, BOARD_RUNNING_CORE & 0x1);
        /* make sure pll0_clk0 output clock at 400MHz to get a clock at 100MHz for the enet0 ptp function */
        /* clock_set_source_divider(clock_ptp0, clk_src_pll1_clk1, 4); */ /* 100MHz */
    } else {
        return status_invalid_argument;
    }

    return status_success;
}

hpm_stat_t board_init_enet_pins(ENET_Type *ptr)
{
    init_enet_pins(ptr);

    if (ptr == HPM_ENET0) {
        gpio_set_pin_output_with_initial(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
    }  else {
        return status_invalid_argument;
    }

    return status_success;
}

hpm_stat_t board_reset_enet_phy(ENET_Type *ptr)
{
    if (ptr == HPM_ENET0) {
        gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 0);
        board_delay_ms(1);
        gpio_write_pin(BOARD_ENET_RGMII_RST_GPIO, BOARD_ENET_RGMII_RST_GPIO_INDEX, BOARD_ENET_RGMII_RST_GPIO_PIN, 1);
    } else {
        return status_invalid_argument;
    }

    return status_success;
}

uint8_t board_get_enet_dma_pbl(ENET_Type *ptr)
{
    (void) ptr;
    return enet_pbl_32;
}

hpm_stat_t board_enable_enet_irq(ENET_Type *ptr)
{
    if (ptr == HPM_ENET0) {
        intc_m_enable_irq(IRQn_ENET0);
    } else {
        return status_invalid_argument;
    }

    return status_success;
}

hpm_stat_t board_disable_enet_irq(ENET_Type *ptr)
{
    if (ptr == HPM_ENET0) {
        intc_m_disable_irq(IRQn_ENET0);
    }  else {
        return status_invalid_argument;
    }

    return status_success;
}

void board_init_enet_pps_pins(ENET_Type *ptr)
{
    (void) ptr;
    init_enet_pps_pins();
}

hpm_stat_t board_init_enet_rmii_reference_clock(ENET_Type *ptr, bool internal)
{
    /* Configure Enet clock to output reference clock */
    if (ptr == HPM_ENET0) {
        clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1);
        if (internal) {
            /* set pll output frequency at 1GHz */
            if (pllctlv2_init_pll_with_freq(HPM_PLLCTLV2, pllctlv2_pll2, 1000000000UL) == status_success) {
                /* set pll2_clk1 output frequency at 250MHz from PLL2 divided by 4 (1 + 15 / 5) */
                pllctlv2_set_postdiv(HPM_PLLCTLV2, pllctlv2_pll2, pllctlv2_clk1, pllctlv2_div_4p0);
                /* set eth clock frequency at 50MHz for enet0 */
                /* clock_set_source_divider(clock_eth0, clk_src_pll2_clk1, 5); */
            } else {
                return status_fail;
            }
        }
    } else {
        return status_invalid_argument;
    }

    enet_rmii_enable_clock(ptr, internal);  /* defined in hpm_enet_soc_drv.h, not sure */

    return status_success;
}

hpm_stat_t board_init_enet_rgmii_clock_delay(ENET_Type *ptr)
{
    if (ptr == HPM_ENET0) {
        clock_add_to_group(clock_eth0, BOARD_RUNNING_CORE & 0x1);
        return enet_rgmii_set_clock_delay(ptr, BOARD_ENET_RGMII_TX_DLY, BOARD_ENET_RGMII_RX_DLY);
    }

    return status_invalid_argument;
}

void board_init_dao_pins(void)
{
    init_dao_pins();
}

void board_init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx)
{
    init_sei_pins(ptr, sei_ctrl_idx);
}

void board_init_adc_qeiv2_pins(void)
{
    init_adc_qeiv2_pins();
}

uint32_t board_init_dac_clock(DAC_Type *ptr, bool clk_src_ahb)
{
    (void)ptr;
    (void)clk_src_ahb;

    if (ptr == HPM_DAC0) {
        clock_add_to_group(clock_dac0, 0);
    } else if (ptr == HPM_DAC1) {
        clock_add_to_group(clock_dac1, 0);
    } else {
        ;
    }

    return clock_get_frequency(clock_ahb0);
}

void board_init_dac_pins(DAC_Type *ptr)
{
    init_dac_pins(ptr);
}

void board_init_gptmr_channel_pin(GPTMR_Type *ptr, uint32_t channel, bool as_comp)
{
    init_gptmr_channel_pin(ptr, channel, as_comp);
}

uint32_t board_init_gptmr_clock(GPTMR_Type *ptr)
{
    uint32_t freq = 0U;
    if (ptr == HPM_GPTMR0) {
        clock_add_to_group(clock_gptmr0, BOARD_RUNNING_CORE & 0x1);
        freq = clock_get_frequency(clock_gptmr0);
    } else if (ptr == HPM_GPTMR1) {
        clock_add_to_group(clock_gptmr1, BOARD_RUNNING_CORE & 0x1);
        freq = clock_get_frequency(clock_gptmr1);
    } else if (ptr == HPM_GPTMR2) {
        clock_add_to_group(clock_gptmr2, BOARD_RUNNING_CORE & 0x1);
        freq = clock_get_frequency(clock_gptmr2);
    } else if (ptr == HPM_GPTMR3) {
        clock_add_to_group(clock_gptmr3, BOARD_RUNNING_CORE & 0x1);
        freq = clock_get_frequency(clock_gptmr3);
    } else if (ptr == HPM_PTMR) {
        clock_add_to_group(clock_ptmr, BOARD_RUNNING_CORE & 0x1);
        freq = clock_get_frequency(clock_ptmr);
    } else {
        /* Not supported */
    }
    return freq;
}