drv_usart_v2.c 49 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449
  1. /*
  2. * Copyright (c) 2006-2025, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2025-07-16 CYFS first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include "board.h"
  13. #include "drv_usart_v2.h"
  14. #ifdef RT_USING_SERIAL_V2
  15. #if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_LPUART1)
  16. #error "Please define at least one BSP_USING_UARTx"
  17. /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
  18. #endif
  19. /******************************* declare ****************************************************************************************** */
  20. enum
  21. {
  22. #ifdef BSP_USING_UART1
  23. UART1_INDEX,
  24. #endif
  25. #ifdef BSP_USING_UART2
  26. UART2_INDEX,
  27. #endif
  28. #ifdef BSP_USING_UART3
  29. UART3_INDEX,
  30. #endif
  31. #ifdef BSP_USING_UART4
  32. UART4_INDEX,
  33. #endif
  34. #ifdef BSP_USING_UART5
  35. UART5_INDEX,
  36. #endif
  37. #ifdef BSP_USING_UART6
  38. UART6_INDEX,
  39. #endif
  40. #ifdef BSP_USING_UART7
  41. UART7_INDEX,
  42. #endif
  43. #ifdef BSP_USING_UART8
  44. UART8_INDEX,
  45. #endif
  46. };
  47. struct DMA_HandleTypeDef
  48. {
  49. DMA_Channel_TypeDef *Instance; /* DMA registers base address */
  50. struct UART_HandleTypeDef *Parent;
  51. DMA_InitTypeDef Init; /* DMA initialization parameters */
  52. rt_uint32_t dma_rcc;
  53. IRQn_Type dma_irq;
  54. void (*DMA_ITC_Callback)(struct UART_HandleTypeDef *huart) ;/* DMA transfer complete callback */
  55. void (*DMA_IE_Callback)(void); /* DMA error complete callback */
  56. };
  57. struct UART_HandleTypeDef
  58. {
  59. USART_TypeDef *Instance; /*!< UART registers base address */
  60. USART_InitTypeDef Init; /*!< UART communication parameters */
  61. struct DMA_HandleTypeDef *HDMA_Tx; /*!< UART Tx DMA handle parameters */
  62. struct DMA_HandleTypeDef *HDMA_Rx; /*!< UART Rx DMA handle parameters */
  63. };
  64. struct ch32_uart_config
  65. {
  66. const char *name;
  67. USART_TypeDef *Instance;
  68. rt_uint32_t rcc;
  69. IRQn_Type irq_type;
  70. GPIO_TypeDef *tx_port;
  71. uint16_t tx_pin;
  72. GPIO_TypeDef *rx_port;
  73. uint16_t rx_pin;
  74. };
  75. struct ch32_uart
  76. {
  77. struct UART_HandleTypeDef handle;
  78. struct ch32_uart_config *config;
  79. #ifdef RT_SERIAL_USING_DMA
  80. struct
  81. {
  82. struct DMA_HandleTypeDef handle;
  83. rt_size_t remaining_cnt;
  84. } dma_rx;
  85. struct
  86. {
  87. struct DMA_HandleTypeDef handle;
  88. } dma_tx;
  89. #endif
  90. rt_uint16_t uart_dma_flag;
  91. struct rt_serial_device serial;
  92. };
  93. /********************************************************************************************************************************** */
  94. /******************************* funtion ****************************************************************************************** */
  95. static void ch32_uart_get_config(void);
  96. static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
  97. static void NVIC_Set(IRQn_Type irq, FunctionalState state);
  98. #ifdef RT_SERIAL_USING_DMA
  99. static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag);
  100. static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag);
  101. void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart);
  102. void HAL_UART_RxCpltCallback(struct UART_HandleTypeDef *huart);
  103. static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma);
  104. #endif
  105. static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin);
  106. /********************************************************************************************************************************** */
  107. /******************************** value ******************************************************************************************* */
  108. static struct ch32_uart_config uart_config[] =
  109. {
  110. #ifdef BSP_USING_UART1
  111. {
  112. .name = "uart1",
  113. .Instance = USART1,
  114. .rcc = RCC_APB2Periph_USART1,
  115. .irq_type = USART1_IRQn,
  116. .tx_port = GPIOA,
  117. .tx_pin = GPIO_Pin_9,
  118. .rx_port = GPIOA,
  119. .rx_pin = GPIO_Pin_10
  120. },
  121. #endif
  122. #ifdef BSP_USING_UART2
  123. {
  124. .name = "uart2",
  125. .Instance = USART2,
  126. .rcc = RCC_APB1Periph_USART2,
  127. .irq_type = USART2_IRQn,
  128. .tx_port = GPIOA,
  129. .tx_pin = GPIO_Pin_2,
  130. .rx_port = GPIOA,
  131. .rx_pin = GPIO_Pin_3
  132. },
  133. #endif
  134. #ifdef BSP_USING_UART3
  135. {
  136. .name = "uart3",
  137. .Instance = USART3,
  138. .rcc = RCC_APB1Periph_USART3,
  139. .irq_type = USART3_IRQn,
  140. .tx_port = GPIOB,
  141. .tx_pin = GPIO_Pin_10,
  142. .rx_port = GPIOB,
  143. .rx_pin = GPIO_Pin_11,
  144. },
  145. #endif
  146. #ifdef BSP_USING_UART4
  147. {
  148. .name = "uart4",
  149. .Instance = UART4,
  150. .rcc = RCC_APB1Periph_UART4,
  151. .irq_type = UART4_IRQn,
  152. .tx_port = GPIOC,
  153. .tx_pin = GPIO_Pin_10,
  154. .rx_port = GPIOC,
  155. .rx_pin = GPIO_Pin_11,
  156. },
  157. #endif
  158. #ifdef BSP_USING_UART5
  159. {
  160. .name = "uart5",
  161. .Instance = UART5,
  162. .rcc = RCC_APB1Periph_UART5,
  163. .irq_type = UART5_IRQn,
  164. .tx_port = GPIOC,
  165. .tx_pin = GPIO_Pin_12,
  166. .rx_port = GPIOD,
  167. .rx_pin = GPIO_Pin_2,
  168. },
  169. #endif
  170. #ifdef BSP_USING_UART6
  171. {
  172. .name = "uart6",
  173. .Instance = UART6,
  174. .rcc = RCC_APB1Periph_UART6,
  175. .irq_type = UART6_IRQn,
  176. .tx_port = GPIOC,
  177. .tx_pin = GPIO_Pin_0,
  178. .rx_port = GPIOC,
  179. .rx_pin = GPIO_Pin_1,
  180. },
  181. #endif
  182. #ifdef BSP_USING_UART7
  183. {
  184. .name = "uart7",
  185. .Instance = UART7,
  186. .rcc = RCC_APB1Periph_UART7,
  187. .irq_type = UART7_IRQn,
  188. .tx_port = GPIOC,
  189. .tx_pin = GPIO_Pin_2,
  190. .rx_port = GPIOC,
  191. .rx_pin = GPIO_Pin_3,
  192. },
  193. #endif
  194. #ifdef BSP_USING_UART8
  195. {
  196. .name = "uart8",
  197. .Instance = UART8,
  198. .rcc = RCC_APB1Periph_UART8,
  199. .irq_type = UART8_IRQn,
  200. .tx_port = GPIOC,
  201. .tx_pin = GPIO_Pin_4,
  202. .rx_port = GPIOC,
  203. .rx_pin = GPIO_Pin_5,
  204. },
  205. #endif
  206. };
  207. static struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(struct ch32_uart_config)];
  208. /********************************************************************************************************************************** */
  209. static void GPIOInit(GPIO_TypeDef* GPIOx, GPIOMode_TypeDef mode, GPIOSpeed_TypeDef speed, uint16_t Pin)
  210. {
  211. GPIO_InitTypeDef GPIO_InitStructure;
  212. /* Enable the GPIO Clock */
  213. if (GPIOx == GPIOA)
  214. {
  215. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
  216. }
  217. else if (GPIOx == GPIOB)
  218. {
  219. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
  220. }
  221. else if (GPIOx == GPIOC)
  222. {
  223. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
  224. }
  225. else if (GPIOx == GPIOD)
  226. {
  227. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
  228. }
  229. else if (GPIOx == GPIOE)
  230. {
  231. RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE);
  232. }
  233. /* Configure the GPIO pin */
  234. GPIO_InitStructure.GPIO_Pin = Pin;
  235. GPIO_InitStructure.GPIO_Mode = mode;
  236. GPIO_InitStructure.GPIO_Speed = speed;
  237. GPIO_Init(GPIOx, &GPIO_InitStructure);
  238. }
  239. static void ch32_uart_init(struct ch32_uart_config *uart)
  240. {
  241. if (uart->Instance==USART1)
  242. {
  243. RCC_APB2PeriphClockCmd(uart->rcc, ENABLE);
  244. }
  245. else
  246. {
  247. RCC_APB1PeriphClockCmd(uart->rcc, ENABLE);
  248. }
  249. NVIC_SetPriority(uart->irq_type, 0);
  250. GPIOInit(uart->rx_port, GPIO_Mode_IPU, GPIO_Speed_50MHz, uart->rx_pin);
  251. GPIOInit(uart->tx_port, GPIO_Mode_AF_PP, GPIO_Speed_50MHz, uart->tx_pin);
  252. }
  253. static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  254. {
  255. struct ch32_uart *uart;
  256. RT_ASSERT(serial != RT_NULL);
  257. RT_ASSERT(cfg != RT_NULL);
  258. uart = rt_container_of(serial, struct ch32_uart, serial);
  259. ch32_uart_init(uart->config);
  260. uart->handle.Init.USART_BaudRate = cfg->baud_rate;
  261. switch (cfg->data_bits)
  262. {
  263. case DATA_BITS_8:
  264. uart->handle.Init.USART_WordLength = USART_WordLength_8b;
  265. break;
  266. case DATA_BITS_9:
  267. uart->handle.Init.USART_WordLength = USART_WordLength_9b;
  268. break;
  269. default:
  270. uart->handle.Init.USART_WordLength = USART_WordLength_8b;
  271. ;
  272. break;
  273. }
  274. switch (cfg->stop_bits)
  275. {
  276. case STOP_BITS_1:
  277. uart->handle.Init.USART_StopBits = USART_StopBits_1;
  278. break;
  279. case STOP_BITS_2:
  280. uart->handle.Init.USART_StopBits = USART_StopBits_0_5;
  281. break;
  282. case STOP_BITS_3:
  283. uart->handle.Init.USART_StopBits = USART_StopBits_2;
  284. break;
  285. case STOP_BITS_4:
  286. uart->handle.Init.USART_StopBits = USART_StopBits_1_5;
  287. break;
  288. default:
  289. break;
  290. }
  291. switch (cfg->parity)
  292. {
  293. case PARITY_ODD:
  294. uart->handle.Init.USART_Parity = USART_Parity_Odd;
  295. break;
  296. case PARITY_EVEN:
  297. uart->handle.Init.USART_Parity = USART_Parity_Even;
  298. break;
  299. case PARITY_NONE:
  300. uart->handle.Init.USART_Parity = USART_Parity_No;
  301. break;
  302. default:
  303. break;
  304. }
  305. switch (cfg->flowcontrol)
  306. {
  307. case RT_SERIAL_FLOWCONTROL_NONE:
  308. uart->handle.Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
  309. break;
  310. case RT_SERIAL_FLOWCONTROL_CTSRTS:
  311. uart->handle.Init.USART_HardwareFlowControl = USART_HardwareFlowControl_CTS;
  312. break;
  313. default:
  314. uart->handle.Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
  315. break;
  316. }
  317. uart->handle.Init.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
  318. USART_DeInit(uart->handle.Instance);
  319. USART_Init(uart->handle.Instance, &uart->handle.Init);
  320. USART_Cmd(uart->handle.Instance, ENABLE);
  321. #ifdef RT_SERIAL_USING_DMA
  322. uart->dma_rx.remaining_cnt = serial->config.dma_ping_bufsz;
  323. #endif
  324. return RT_EOK;
  325. }
  326. /**
  327. * @brief Configures the nested vectored interrupt controller.
  328. */
  329. static void NVIC_Set(IRQn_Type irq, FunctionalState state)
  330. {
  331. if (state == ENABLE)
  332. {
  333. NVIC_SetPriority(irq, 0);
  334. NVIC_EnableIRQ(irq);
  335. }
  336. else if (state == DISABLE)
  337. {
  338. NVIC_DisableIRQ(irq);
  339. }
  340. }
  341. static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg)
  342. {
  343. struct ch32_uart *uart;
  344. rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
  345. RT_ASSERT(serial != RT_NULL);
  346. uart = rt_container_of(serial, struct ch32_uart, serial);
  347. if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
  348. {
  349. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX)
  350. ctrl_arg = RT_DEVICE_FLAG_DMA_RX;
  351. else
  352. ctrl_arg = RT_DEVICE_FLAG_INT_RX;
  353. }
  354. else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING))
  355. {
  356. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  357. ctrl_arg = RT_DEVICE_FLAG_DMA_TX;
  358. else
  359. ctrl_arg = RT_DEVICE_FLAG_INT_TX;
  360. }
  361. switch (cmd)
  362. {
  363. /* disable interrupt */
  364. case RT_DEVICE_CTRL_CLR_INT:
  365. NVIC_Set(uart->config->irq_type, DISABLE);
  366. if (ctrl_arg & RT_DEVICE_FLAG_INT_RX)
  367. {
  368. USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, DISABLE);
  369. }
  370. if (ctrl_arg & RT_DEVICE_FLAG_INT_TX)
  371. {
  372. USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE);
  373. }
  374. #ifdef RT_SERIAL_USING_DMA
  375. if (ctrl_arg & RT_DEVICE_FLAG_DMA_RX)
  376. {
  377. NVIC_Set(uart->dma_rx.handle.dma_irq, DISABLE);
  378. USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, DISABLE);
  379. DMA_DeInit(uart->dma_rx.handle.Instance);
  380. }
  381. else if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
  382. {
  383. NVIC_Set(uart->dma_tx.handle.dma_irq, DISABLE);
  384. USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE);
  385. USART_ClearFlag(uart->handle.Instance, USART_FLAG_TC);
  386. DMA_DeInit(uart->dma_tx.handle.Instance);
  387. }
  388. #endif
  389. break;
  390. case RT_DEVICE_CTRL_CONFIG:
  391. #ifdef RT_SERIAL_USING_DMA
  392. if (ctrl_arg & (RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_DMA_TX))
  393. {
  394. ch32_uart_dma_config(serial, ctrl_arg);
  395. }
  396. else
  397. ch32_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)ctrl_arg);
  398. break;
  399. #endif
  400. case RT_DEVICE_CTRL_SET_INT:
  401. NVIC_Set(uart->config->irq_type, ENABLE);
  402. if (ctrl_arg & RT_DEVICE_FLAG_INT_RX)
  403. {
  404. USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, ENABLE);
  405. USART_ClearITPendingBit(uart->config->Instance, USART_IT_RXNE);
  406. USART_ClearFlag(uart->handle.Instance, USART_FLAG_RXNE);
  407. }
  408. else if (ctrl_arg & RT_DEVICE_FLAG_INT_TX)
  409. {
  410. USART_ITConfig(uart->handle.Instance, USART_IT_TC, ENABLE);
  411. USART_ClearFlag(uart->handle.Instance, USART_FLAG_TC);
  412. }
  413. NVIC_Set(uart->config->irq_type, ENABLE);
  414. break;
  415. case RT_DEVICE_CHECK_OPTMODE:
  416. if (ctrl_arg & RT_DEVICE_FLAG_DMA_TX)
  417. return RT_SERIAL_TX_BLOCKING_NO_BUFFER;
  418. else
  419. return RT_SERIAL_TX_BLOCKING_BUFFER;
  420. case RT_DEVICE_CTRL_CLOSE:
  421. #ifdef RT_SERIAL_USING_DMA
  422. DMA_Cmd(uart->dma_tx.handle.Instance, DISABLE);
  423. DMA_Cmd(uart->dma_rx.handle.Instance, DISABLE);
  424. NVIC_Set(uart->dma_rx.handle.dma_irq, DISABLE);
  425. #endif
  426. USART_DeInit(uart->handle.Instance);
  427. NVIC_Set(uart->config->irq_type, DISABLE);
  428. USART_ITConfig(uart->handle.Instance, USART_IT_TC, DISABLE);
  429. USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, DISABLE);
  430. USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, DISABLE);
  431. USART_ITConfig(uart->handle.Instance, USART_IT_RXNE, DISABLE);
  432. break;
  433. }
  434. return RT_EOK;
  435. }
  436. static int ch32_putc(struct rt_serial_device *serial, char c)
  437. {
  438. struct ch32_uart *uart;
  439. RT_ASSERT(serial != RT_NULL);
  440. uart = rt_container_of(serial, struct ch32_uart, serial);
  441. while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET);
  442. uart->config->Instance->DATAR = c;
  443. /* Transmit Data */
  444. return 1;
  445. }
  446. static int ch32_getc(struct rt_serial_device *serial)
  447. {
  448. struct ch32_uart *uart;
  449. RT_ASSERT(serial != RT_NULL);
  450. uart = rt_container_of(serial, struct ch32_uart, serial);
  451. return (int)(uart->handle.Instance->DATAR & (uint16_t)0xFF);
  452. }
  453. static rt_ssize_t ch32_transmit(struct rt_serial_device *serial,
  454. rt_uint8_t *buf,
  455. rt_size_t size,
  456. rt_uint32_t tx_flag)
  457. {
  458. struct ch32_uart *uart;
  459. RT_ASSERT(serial != RT_NULL);
  460. RT_ASSERT(buf != RT_NULL);
  461. uart = rt_container_of(serial, struct ch32_uart, serial);
  462. #ifdef RT_SERIAL_USING_DMA
  463. if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX)
  464. {
  465. DMA_Cmd(uart->dma_tx.handle.Instance, DISABLE);
  466. uart->dma_tx.handle.Instance->MADDR = (unsigned int)buf;
  467. uart->dma_tx.handle.Instance->CNTR = size & 0xFFFF;
  468. DMA_Cmd(uart->dma_tx.handle.Instance, ENABLE);
  469. return size & 0xFFFF;
  470. }
  471. #endif
  472. return size;
  473. }
  474. /**
  475. * Uart common interrupt process. This need add to uart ISR.
  476. *
  477. * @param serial serial device
  478. */
  479. static void uart_isr(struct rt_serial_device *serial)
  480. {
  481. struct ch32_uart *uart;
  482. RT_ASSERT(serial != RT_NULL);
  483. uart = rt_container_of(serial, struct ch32_uart, serial);
  484. /* If the Read data register is not empty and the RXNE interrupt is enabled (RDR) */
  485. if (USART_GetITStatus(uart->handle.Instance, USART_IT_RXNE) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_RXNE) != RESET)
  486. {
  487. char chr = uart->handle.Instance->DATAR;
  488. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_PUTC, &chr);
  489. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  490. USART_ClearITPendingBit(uart->config->Instance, USART_IT_RXNE);
  491. }
  492. /* If the Transmit data register is empty and the TXE interrupt enable is enabled (TDR)*/
  493. else if (USART_GetITStatus(uart->handle.Instance, USART_IT_TXE) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TXE) != RESET)
  494. {
  495. rt_uint8_t put_char = 0;
  496. if (rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GETC, &put_char) == RT_EOK)
  497. {
  498. USART_SendData(uart->handle.Instance, put_char);
  499. }
  500. USART_ClearITPendingBit(uart->config->Instance, USART_IT_TXE);
  501. }
  502. else if (USART_GetITStatus(uart->handle.Instance, USART_IT_TC) != RESET && USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_TC))
  503. {
  504. /* Clear Transmission complete interrupt flag ( ISR Register ) */
  505. USART_ClearITPendingBit(uart->handle.Instance, USART_IT_TC);
  506. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
  507. }
  508. #ifdef RT_SERIAL_USING_DMA
  509. else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->handle.Instance, USART_FLAG_IDLE) != RESET)
  510. && (USART_GetITStatus(uart->handle.Instance, USART_IT_IDLE) != RESET))
  511. {
  512. /* clean IDLEF flag */
  513. dma_recv_isr(serial, UART_RX_DMA_IT_IDLE_FLAG);
  514. USART_ReceiveData(uart->handle.Instance);
  515. }
  516. #endif
  517. }
  518. #if defined(BSP_USING_UART1)
  519. #if defined (SOC_RISCV_SERIES_CH32V2)
  520. void USART1_IRQHandler(void) __attribute__((interrupt()));
  521. #else
  522. void USART1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  523. #endif
  524. void USART1_IRQHandler(void)
  525. {
  526. GET_INT_SP();
  527. /* enter interrupt */
  528. rt_interrupt_enter();
  529. uart_isr(&(uart_obj[UART1_INDEX].serial));
  530. /* leave interrupt */
  531. rt_interrupt_leave();
  532. FREE_INT_SP();
  533. }
  534. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA)
  535. #if defined (SOC_RISCV_SERIES_CH32V2)
  536. void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt()));
  537. #else
  538. void DMA1_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  539. #endif
  540. void DMA1_Channel5_IRQHandler(void)
  541. {
  542. GET_INT_SP();
  543. /* enter interrupt */
  544. rt_interrupt_enter();
  545. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_rx.handle);
  546. /* leave interrupt */
  547. rt_interrupt_leave();
  548. FREE_INT_SP();
  549. }
  550. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */
  551. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA)
  552. #if defined (SOC_RISCV_SERIES_CH32V2)
  553. void DMA1_Channel4_IRQHandler(void) __attribute__((interrupt()));
  554. #else
  555. void DMA1_Channel4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  556. #endif
  557. void DMA1_Channel4_IRQHandler(void)
  558. {
  559. GET_INT_SP();
  560. /* enter interrupt */
  561. rt_interrupt_enter();
  562. HAL_DMA_IRQHandler(&uart_obj[UART1_INDEX].dma_tx.handle);
  563. /* leave interrupt */
  564. rt_interrupt_leave();
  565. FREE_INT_SP();
  566. }
  567. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */
  568. #endif /* BSP_USING_UART1 */
  569. #if defined(BSP_USING_UART2)
  570. #if defined (SOC_RISCV_SERIES_CH32V2)
  571. void USART2_IRQHandler(void) __attribute__((interrupt()));
  572. #else
  573. void USART2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  574. #endif
  575. void USART2_IRQHandler(void)
  576. {
  577. GET_INT_SP();
  578. /* enter interrupt */
  579. rt_interrupt_enter();
  580. uart_isr(&(uart_obj[UART2_INDEX].serial));
  581. /* leave interrupt */
  582. rt_interrupt_leave();
  583. FREE_INT_SP();
  584. }
  585. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA)
  586. #if defined (SOC_RISCV_SERIES_CH32V2)
  587. void DMA1_Channel6_IRQHandler(void) __attribute__((interrupt()));
  588. #else
  589. void DMA1_Channel6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  590. #endif
  591. void DMA1_Channel6_IRQHandler(void)
  592. {
  593. GET_INT_SP();
  594. /* enter interrupt */
  595. rt_interrupt_enter();
  596. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_rx.handle);
  597. /* leave interrupt */
  598. rt_interrupt_leave();
  599. FREE_INT_SP();
  600. }
  601. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */
  602. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA)
  603. #if defined (SOC_RISCV_SERIES_CH32V2)
  604. void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt()));
  605. #else
  606. void DMA1_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  607. #endif
  608. void DMA1_Channel7_IRQHandler(void)
  609. {
  610. GET_INT_SP();
  611. /* enter interrupt */
  612. rt_interrupt_enter();
  613. HAL_DMA_IRQHandler(&uart_obj[UART2_INDEX].dma_tx.handle);
  614. /* leave interrupt */
  615. rt_interrupt_leave();
  616. FREE_INT_SP();
  617. }
  618. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */
  619. #endif /* BSP_USING_UART2 */
  620. #if defined(BSP_USING_UART3)
  621. #if defined (SOC_RISCV_SERIES_CH32V2)
  622. void USART3_IRQHandler(void) __attribute__((interrupt()));
  623. #else
  624. void USART3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  625. #endif
  626. void USART3_IRQHandler(void)
  627. {
  628. GET_INT_SP();
  629. /* enter interrupt */
  630. rt_interrupt_enter();
  631. uart_isr(&(uart_obj[UART3_INDEX].serial));
  632. /* leave interrupt */
  633. rt_interrupt_leave();
  634. FREE_INT_SP();
  635. }
  636. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_RX_USING_DMA)
  637. #if defined (SOC_RISCV_SERIES_CH32V2)
  638. void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt()));
  639. #else
  640. void DMA1_Channel3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  641. #endif
  642. void DMA1_Channel3_IRQHandler(void)
  643. {
  644. GET_INT_SP();
  645. /* enter interrupt */
  646. rt_interrupt_enter();
  647. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_rx.handle);
  648. /* leave interrupt */
  649. rt_interrupt_leave();
  650. FREE_INT_SP();
  651. }
  652. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART3_RX_USING_DMA) */
  653. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART3_TX_USING_DMA)
  654. #if defined (SOC_RISCV_SERIES_CH32V2)
  655. void DMA1_Channel2_IRQHandler(void) __attribute__((interrupt()));
  656. #else
  657. void DMA1_Channel2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  658. #endif
  659. void DMA1_Channel2_IRQHandler(void)
  660. {
  661. GET_INT_SP();
  662. /* enter interrupt */
  663. rt_interrupt_enter();
  664. HAL_DMA_IRQHandler(&uart_obj[UART3_INDEX].dma_tx.handle);
  665. /* leave interrupt */
  666. rt_interrupt_leave();
  667. FREE_INT_SP();
  668. }
  669. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART3_TX_USING_DMA) */
  670. #endif /* BSP_USING_UART3*/
  671. #if defined(BSP_USING_UART4)
  672. #if defined (SOC_RISCV_SERIES_CH32V2)
  673. void UART4_IRQHandler(void) __attribute__((interrupt()));
  674. #else
  675. void UART4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  676. #endif
  677. void UART4_IRQHandler(void)
  678. {
  679. GET_INT_SP();
  680. /* enter interrupt */
  681. rt_interrupt_enter();
  682. uart_isr(&(uart_obj[UART4_INDEX].serial));
  683. /* leave interrupt */
  684. rt_interrupt_leave();
  685. FREE_INT_SP();
  686. }
  687. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_RX_USING_DMA)
  688. #if defined (SOC_RISCV_SERIES_CH32V2)
  689. void DMA2_Channel3_IRQHandler(void) __attribute__((interrupt()));
  690. #else
  691. void DMA2_Channel3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  692. #endif
  693. void DMA2_Channel3_IRQHandler(void)
  694. {
  695. GET_INT_SP();
  696. /* enter interrupt */
  697. rt_interrupt_enter();
  698. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_rx.handle);
  699. /* leave interrupt */
  700. rt_interrupt_leave();
  701. FREE_INT_SP();
  702. }
  703. #endif /* defined(BSP_UART_USING_DMA_RX) && defined(BSP_UART4_RX_USING_DMA) */
  704. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART4_TX_USING_DMA)
  705. #if defined (SOC_RISCV_SERIES_CH32V2)
  706. void DMA2_Channel5_IRQHandler(void) __attribute__((interrupt()));
  707. #else
  708. void DMA2_Channel5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  709. #endif
  710. void DMA2_Channel5_IRQHandler(void)
  711. {
  712. GET_INT_SP();
  713. /* enter interrupt */
  714. rt_interrupt_enter();
  715. HAL_DMA_IRQHandler(&uart_obj[UART4_INDEX].dma_tx.handle);
  716. /* leave interrupt */
  717. rt_interrupt_leave();
  718. FREE_INT_SP();
  719. }
  720. #endif /* defined(BSP_UART_USING_DMA_TX) && defined(BSP_UART4_TX_USING_DMA) */
  721. #endif /* BSP_USING_UART4*/
  722. #if defined(BSP_USING_UART5)
  723. #if defined (SOC_RISCV_SERIES_CH32V2)
  724. void UART5_IRQHandler(void) __attribute__((interrupt()));
  725. #else
  726. void UART5_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  727. #endif
  728. void UART5_IRQHandler(void)
  729. {
  730. GET_INT_SP();
  731. /* enter interrupt */
  732. rt_interrupt_enter();
  733. uart_isr(&(uart_obj[UART5_INDEX].serial));
  734. /* leave interrupt */
  735. rt_interrupt_leave();
  736. FREE_INT_SP();
  737. }
  738. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA)
  739. #if defined (SOC_RISCV_SERIES_CH32V2)
  740. void DMA2_Channel2_IRQHandler(void) __attribute__((interrupt()));
  741. #else
  742. void DMA2_Channel2_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  743. #endif
  744. void DMA2_Channel2_IRQHandler(void)
  745. {
  746. GET_INT_SP();
  747. /* enter interrupt */
  748. rt_interrupt_enter();
  749. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_rx.handle);
  750. /* leave interrupt */
  751. rt_interrupt_leave();
  752. FREE_INT_SP();
  753. }
  754. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_RX_USING_DMA) */
  755. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA)
  756. #if defined (SOC_RISCV_SERIES_CH32V2)
  757. void DMA2_Channel4_IRQHandler(void) __attribute__((interrupt()));
  758. #else
  759. void DMA2_Channel4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  760. #endif
  761. void DMA2_Channel4_IRQHandler(void)
  762. {
  763. GET_INT_SP();
  764. /* enter interrupt */
  765. rt_interrupt_enter();
  766. HAL_DMA_IRQHandler(&uart_obj[UART5_INDEX].dma_tx.handle);
  767. /* leave interrupt */
  768. rt_interrupt_leave();
  769. FREE_INT_SP();
  770. }
  771. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART5_TX_USING_DMA) */
  772. #endif /* BSP_USING_UART5*/
  773. #if defined(BSP_USING_UART6)
  774. #if defined (SOC_RISCV_SERIES_CH32V2)
  775. void UART6_IRQHandler(void) __attribute__((interrupt()));
  776. #else
  777. void UART6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  778. #endif
  779. void UART6_IRQHandler(void)
  780. {
  781. GET_INT_SP();
  782. /* enter interrupt */
  783. rt_interrupt_enter();
  784. uart_isr(&(uart_obj[UART6_INDEX].serial));
  785. /* leave interrupt */
  786. rt_interrupt_leave();
  787. FREE_INT_SP();
  788. }
  789. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA)
  790. #if defined (SOC_RISCV_SERIES_CH32V2)
  791. void DMA2_Channel7_IRQHandler(void) __attribute__((interrupt()));
  792. #else
  793. void DMA2_Channel7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  794. #endif
  795. void DMA2_Channel7_IRQHandler(void)
  796. {
  797. GET_INT_SP();
  798. /* enter interrupt */
  799. rt_interrupt_enter();
  800. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_rx.handle);
  801. /* leave interrupt */
  802. rt_interrupt_leave();
  803. FREE_INT_SP();
  804. }
  805. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_RX_USING_DMA) */
  806. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA)
  807. #if defined (SOC_RISCV_SERIES_CH32V2)
  808. void DMA2_Channel6_IRQHandler(void) __attribute__((interrupt()));
  809. #else
  810. void DMA2_Channel6_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  811. #endif
  812. void DMA2_Channel6_IRQHandler(void)
  813. {
  814. GET_INT_SP();
  815. /* enter interrupt */
  816. rt_interrupt_enter();
  817. HAL_DMA_IRQHandler(&uart_obj[UART6_INDEX].dma_tx.handle);
  818. /* leave interrupt */
  819. rt_interrupt_leave();
  820. FREE_INT_SP();
  821. }
  822. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART6_TX_USING_DMA) */
  823. #endif /* BSP_USING_UART6*/
  824. #if defined(BSP_USING_UART7)
  825. #if defined (SOC_RISCV_SERIES_CH32V2)
  826. void UART7_IRQHandler(void) __attribute__((interrupt()));
  827. #else
  828. void UART7_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  829. #endif
  830. void UART7_IRQHandler(void)
  831. {
  832. GET_INT_SP();
  833. /* enter interrupt */
  834. rt_interrupt_enter();
  835. uart_isr(&(uart_obj[UART7_INDEX].serial));
  836. /* leave interrupt */
  837. rt_interrupt_leave();
  838. FREE_INT_SP();
  839. }
  840. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA)
  841. #if defined (SOC_RISCV_SERIES_CH32V2)
  842. void DMA2_Channel9_IRQHandler(void) __attribute__((interrupt()));
  843. #else
  844. void DMA2_Channel9_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  845. #endif
  846. void DMA2_Channel9_IRQHandler(void)
  847. {
  848. GET_INT_SP();
  849. /* enter interrupt */
  850. rt_interrupt_enter();
  851. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_rx.handle);
  852. /* leave interrupt */
  853. rt_interrupt_leave();
  854. FREE_INT_SP();
  855. }
  856. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_RX_USING_DMA) */
  857. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA)
  858. #if defined (SOC_RISCV_SERIES_CH32V2)
  859. void DMA2_Channel8_IRQHandler(void) __attribute__((interrupt()));
  860. #else
  861. void DMA2_Channel8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  862. #endif
  863. void DMA2_Channel8_IRQHandler(void)
  864. {
  865. GET_INT_SP();
  866. /* enter interrupt */
  867. rt_interrupt_enter();
  868. HAL_DMA_IRQHandler(&uart_obj[UART7_INDEX].dma_tx.handle);
  869. /* leave interrupt */
  870. rt_interrupt_leave();
  871. FREE_INT_SP();
  872. }
  873. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART7_TX_USING_DMA) */
  874. #endif /* BSP_USING_UART7*/
  875. #if defined(BSP_USING_UART8)
  876. #if defined (SOC_RISCV_SERIES_CH32V2)
  877. void UART8_IRQHandler(void) __attribute__((interrupt()));
  878. #else
  879. void UART8_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  880. #endif
  881. void UART8_IRQHandler(void)
  882. {
  883. GET_INT_SP();
  884. /* enter interrupt */
  885. rt_interrupt_enter();
  886. uart_isr(&(uart_obj[UART8_INDEX].serial));
  887. /* leave interrupt */
  888. rt_interrupt_leave();
  889. FREE_INT_SP();
  890. }
  891. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA)
  892. #if defined (SOC_RISCV_SERIES_CH32V2)
  893. void DMA2_Channel11_IRQHandler(void) __attribute__((interrupt()));
  894. #else
  895. void DMA2_Channel11_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  896. #endif
  897. void DMA2_Channel11_IRQHandler(void)
  898. {
  899. GET_INT_SP();
  900. /* enter interrupt */
  901. rt_interrupt_enter();
  902. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_rx.handle);
  903. /* leave interrupt */
  904. rt_interrupt_leave();
  905. FREE_INT_SP();
  906. }
  907. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_RX_USING_DMA) */
  908. #if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA)
  909. #if defined (SOC_RISCV_SERIES_CH32V2)
  910. void DMA2_Channel10_IRQHandler(void) __attribute__((interrupt()));
  911. #else
  912. void DMA2_Channel10_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
  913. #endif
  914. void DMA2_Channel10_IRQHandler(void)
  915. {
  916. GET_INT_SP();
  917. /* enter interrupt */
  918. rt_interrupt_enter();
  919. HAL_DMA_IRQHandler(&uart_obj[UART8_INDEX].dma_tx.handle);
  920. /* leave interrupt */
  921. rt_interrupt_leave();
  922. FREE_INT_SP();
  923. }
  924. #endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART8_TX_USING_DMA) */
  925. #endif /* BSP_USING_UART8*/
  926. static void ch32_uart_get_config(void)
  927. {
  928. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  929. #ifdef BSP_USING_UART1
  930. uart_obj[UART1_INDEX].serial.config = config;
  931. uart_obj[UART1_INDEX].serial.config.rx_bufsz = BSP_UART1_RX_BUFSIZE;
  932. uart_obj[UART1_INDEX].serial.config.tx_bufsz = BSP_UART1_TX_BUFSIZE;
  933. uart_obj[UART1_INDEX].handle.Instance = USART1;
  934. uart_obj[UART1_INDEX].uart_dma_flag = 0;
  935. #ifdef BSP_UART1_RX_USING_DMA
  936. uart_obj[UART1_INDEX].handle.HDMA_Rx = &uart_obj[UART1_INDEX].dma_rx.handle;
  937. uart_obj[UART1_INDEX].serial.config.dma_ping_bufsz = BSP_UART1_DMA_PING_BUFSIZE;
  938. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  939. uart_obj[UART1_INDEX].dma_rx.handle.Parent = &uart_obj[UART1_INDEX].handle;
  940. uart_obj[UART1_INDEX].dma_rx.handle.Instance = DMA1_Channel5;
  941. uart_obj[UART1_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
  942. uart_obj[UART1_INDEX].dma_rx.handle.dma_irq = DMA1_Channel5_IRQn;
  943. #endif
  944. #ifdef BSP_UART1_TX_USING_DMA
  945. uart_obj[UART1_INDEX].handle.HDMA_Tx = &uart_obj[UART1_INDEX].dma_tx.handle;
  946. uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  947. uart_obj[UART1_INDEX].dma_tx.handle.Parent = &uart_obj[UART1_INDEX].handle;
  948. uart_obj[UART1_INDEX].dma_tx.handle.Instance = DMA1_Channel4;
  949. uart_obj[UART1_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
  950. uart_obj[UART1_INDEX].dma_tx.handle.dma_irq = DMA1_Channel4_IRQn;
  951. #endif
  952. #endif
  953. #ifdef BSP_USING_UART2
  954. uart_obj[UART2_INDEX].serial.config = config;
  955. uart_obj[UART2_INDEX].serial.config.rx_bufsz = BSP_UART2_RX_BUFSIZE;
  956. uart_obj[UART2_INDEX].serial.config.tx_bufsz = BSP_UART2_TX_BUFSIZE;
  957. uart_obj[UART2_INDEX].handle.Instance = USART2;
  958. uart_obj[UART2_INDEX].uart_dma_flag = 0;
  959. #ifdef BSP_UART2_RX_USING_DMA
  960. uart_obj[UART2_INDEX].handle.HDMA_Rx = &uart_obj[UART2_INDEX].dma_rx.handle;
  961. uart_obj[UART2_INDEX].serial.config.dma_ping_bufsz = BSP_UART2_DMA_PING_BUFSIZE;
  962. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  963. uart_obj[UART2_INDEX].dma_rx.handle.Parent = &uart_obj[UART2_INDEX].handle;
  964. uart_obj[UART2_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  965. uart_obj[UART2_INDEX].dma_rx.handle.Instance = DMA1_Channel6;
  966. uart_obj[UART2_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
  967. uart_obj[UART2_INDEX].dma_rx.handle.dma_irq = DMA1_Channel6_IRQn;
  968. #endif
  969. #ifdef BSP_UART2_TX_USING_DMA
  970. uart_obj[UART2_INDEX].handle.HDMA_Tx = &uart_obj[UART2_INDEX].dma_tx.handle;
  971. uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  972. uart_obj[UART2_INDEX].dma_tx.handle.Parent = &uart_obj[UART2_INDEX].handle;
  973. uart_obj[UART2_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  974. uart_obj[UART2_INDEX].dma_tx.handle.Instance = DMA1_Channel7;
  975. uart_obj[UART2_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
  976. uart_obj[UART2_INDEX].dma_tx.handle.dma_irq = DMA1_Channel7_IRQn;
  977. #endif
  978. #endif
  979. #ifdef BSP_USING_UART3
  980. uart_obj[UART3_INDEX].serial.config = config;
  981. uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
  982. uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
  983. uart_obj[UART3_INDEX].handle.Instance = USART3;
  984. uart_obj[UART3_INDEX].uart_dma_flag = 0;
  985. #ifdef BSP_UART3_RX_USING_DMA
  986. uart_obj[UART3_INDEX].handle.HDMA_Rx = &uart_obj[UART3_INDEX].dma_rx.handle;
  987. uart_obj[UART3_INDEX].serial.config.dma_ping_bufsz = BSP_UART3_DMA_PING_BUFSIZE;
  988. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  989. uart_obj[UART3_INDEX].dma_rx.handle.Parent = &uart_obj[UART3_INDEX].handle;
  990. uart_obj[UART3_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  991. uart_obj[UART3_INDEX].dma_rx.handle.Instance = DMA1_Channel3;
  992. uart_obj[UART3_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
  993. uart_obj[UART3_INDEX].dma_rx.handle.dma_irq = DMA1_Channel3_IRQn;
  994. #endif
  995. #ifdef BSP_UART3_TX_USING_DMA
  996. uart_obj[UART3_INDEX].handle.HDMA_Tx = &uart_obj[UART3_INDEX].dma_tx.handle;
  997. uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  998. uart_obj[UART3_INDEX].dma_tx.handle.Parent = &uart_obj[UART3_INDEX].handle;
  999. uart_obj[UART3_INDEX].dma_tx.handle.Instance = DMA1_Channel2;
  1000. uart_obj[UART3_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  1001. uart_obj[UART3_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA1;
  1002. uart_obj[UART3_INDEX].dma_tx.handle.dma_irq = DMA1_Channel2_IRQn;
  1003. #endif
  1004. #endif
  1005. #ifdef BSP_USING_UART4
  1006. uart_obj[UART4_INDEX].serial.config = config;
  1007. uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
  1008. uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
  1009. uart_obj[UART4_INDEX].handle.Instance = UART4;
  1010. uart_obj[UART4_INDEX].uart_dma_flag = 0;
  1011. #ifdef BSP_UART4_RX_USING_DMA
  1012. uart_obj[UART4_INDEX].handle.HDMA_Rx = &uart_obj[UART4_INDEX].dma_rx.handle;
  1013. uart_obj[UART4_INDEX].serial.config.dma_ping_bufsz = BSP_UART4_DMA_PING_BUFSIZE;
  1014. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  1015. uart_obj[UART4_INDEX].dma_rx.handle.Parent = &uart_obj[UART4_INDEX].handle;
  1016. uart_obj[UART4_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  1017. uart_obj[UART4_INDEX].dma_rx.handle.Instance = DMA2_Channel3;
  1018. uart_obj[UART4_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1019. uart_obj[UART4_INDEX].dma_rx.handle.dma_irq = DMA2_Channel3_IRQn;
  1020. #endif
  1021. #ifdef BSP_UART4_TX_USING_DMA
  1022. uart_obj[UART4_INDEX].handle.HDMA_Tx = &uart_obj[UART4_INDEX].dma_tx.handle;
  1023. uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  1024. uart_obj[UART4_INDEX].dma_tx.handle.Parent = &uart_obj[UART4_INDEX].handle;
  1025. uart_obj[UART4_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  1026. uart_obj[UART4_INDEX].dma_tx.handle.Instance = DMA2_Channel5;
  1027. uart_obj[UART4_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1028. uart_obj[UART4_INDEX].dma_tx.handle.dma_irq = DMA2_Channel5_IRQn;
  1029. #endif
  1030. #endif
  1031. #ifdef BSP_USING_UART5
  1032. uart_obj[UART5_INDEX].serial.config = config;
  1033. uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
  1034. uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
  1035. uart_obj[UART5_INDEX].handle.Instance = UART5;
  1036. uart_obj[UART5_INDEX].uart_dma_flag = 0;
  1037. #ifdef BSP_UART5_RX_USING_DMA
  1038. uart_obj[UART5_INDEX].handle.HDMA_Rx = &uart_obj[UART5_INDEX].dma_rx.handle;
  1039. uart_obj[UART5_INDEX].serial.config.dma_ping_bufsz = BSP_UART5_DMA_PING_BUFSIZE;
  1040. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  1041. uart_obj[UART5_INDEX].dma_rx.handle.Parent = &uart_obj[UART5_INDEX].handle;
  1042. uart_obj[UART5_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  1043. uart_obj[UART5_INDEX].dma_rx.handle.Instance = DMA2_Channel2;
  1044. uart_obj[UART5_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1045. uart_obj[UART5_INDEX].dma_rx.handle.dma_irq = DMA2_Channel2_IRQn;
  1046. #endif
  1047. #ifdef BSP_UART5_TX_USING_DMA
  1048. uart_obj[UART5_INDEX].handle.HDMA_Tx = &uart_obj[UART5_INDEX].dma_tx.handle;
  1049. uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  1050. uart_obj[UART5_INDEX].dma_tx.handle.Parent = &uart_obj[UART5_INDEX].handle;
  1051. uart_obj[UART5_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  1052. uart_obj[UART5_INDEX].dma_tx.handle.Instance = DMA2_Channel4;
  1053. uart_obj[UART5_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1054. uart_obj[UART5_INDEX].dma_tx.handle.dma_irq = DMA2_Channel4_IRQn;
  1055. #endif
  1056. #endif
  1057. #ifdef BSP_USING_UART6
  1058. uart_obj[UART6_INDEX].serial.config = config;
  1059. uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
  1060. uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
  1061. uart_obj[UART6_INDEX].handle.Instance = UART6;
  1062. uart_obj[UART6_INDEX].uart_dma_flag = 0;
  1063. #ifdef BSP_UART6_RX_USING_DMA
  1064. uart_obj[UART6_INDEX].handle.HDMA_Rx = &uart_obj[UART6_INDEX].dma_rx.handle;
  1065. uart_obj[UART6_INDEX].serial.config.dma_ping_bufsz = BSP_UART6_DMA_PING_BUFSIZE;
  1066. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  1067. uart_obj[UART6_INDEX].dma_rx.handle.Parent = &uart_obj[UART6_INDEX].handle;
  1068. uart_obj[UART6_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  1069. uart_obj[UART6_INDEX].dma_rx.handle.Instance = DMA2_Channel7;
  1070. uart_obj[UART6_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1071. uart_obj[UART6_INDEX].dma_rx.handle.dma_irq = DMA2_Channel7_IRQn;
  1072. #endif
  1073. #ifdef BSP_UART6_TX_USING_DMA
  1074. uart_obj[UART6_INDEX].handle.HDMA_Tx = &uart_obj[UART6_INDEX].dma_tx.handle;
  1075. uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  1076. uart_obj[UART6_INDEX].dma_tx.handle.Parent = &uart_obj[UART6_INDEX].handle;
  1077. uart_obj[UART6_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  1078. uart_obj[UART6_INDEX].dma_tx.handle.Instance = DMA2_Channel6;
  1079. uart_obj[UART6_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1080. uart_obj[UART6_INDEX].dma_tx.handle.dma_irq = DMA2_Channel6_IRQn;
  1081. #endif
  1082. #endif
  1083. #ifdef BSP_USING_UART7
  1084. uart_obj[UART7_INDEX].serial.config = config;
  1085. uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
  1086. uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
  1087. uart_obj[UART7_INDEX].handle.Instance = UART7;
  1088. uart_obj[UART7_INDEX].uart_dma_flag = 0;
  1089. #ifdef BSP_UART7_RX_USING_DMA
  1090. uart_obj[UART7_INDEX].handle.HDMA_Rx = &uart_obj[UART7_INDEX].dma_rx.handle;
  1091. uart_obj[UART7_INDEX].serial.config.dma_ping_bufsz = BSP_UART7_DMA_PING_BUFSIZE;
  1092. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  1093. uart_obj[UART7_INDEX].dma_rx.handle.Parent = &uart_obj[UART7_INDEX].handle;
  1094. uart_obj[UART7_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  1095. uart_obj[UART7_INDEX].dma_rx.handle.Instance = DMA2_Channel9;
  1096. uart_obj[UART7_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1097. uart_obj[UART7_INDEX].dma_rx.handle.dma_irq = DMA2_Channel9_IRQn;
  1098. #endif
  1099. #ifdef BSP_UART7_TX_USING_DMA
  1100. uart_obj[UART7_INDEX].handle.HDMA_Tx = &uart_obj[UART7_INDEX].dma_tx.handle;
  1101. uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  1102. uart_obj[UART7_INDEX].dma_tx.handle.Parent = &uart_obj[UART7_INDEX].handle;
  1103. uart_obj[UART7_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  1104. uart_obj[UART7_INDEX].dma_tx.handle.Instance = DMA2_Channel8;
  1105. uart_obj[UART7_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1106. uart_obj[UART7_INDEX].dma_tx.handle.dma_irq = DMA2_Channel8_IRQn;
  1107. #endif
  1108. #endif
  1109. #ifdef BSP_USING_UART8
  1110. uart_obj[UART8_INDEX].serial.config = config;
  1111. uart_obj[UART8_INDEX].serial.config.rx_bufsz = BSP_UART8_RX_BUFSIZE;
  1112. uart_obj[UART8_INDEX].serial.config.tx_bufsz = BSP_UART8_TX_BUFSIZE;
  1113. uart_obj[UART8_INDEX].handle.Instance = UART8;
  1114. uart_obj[UART8_INDEX].uart_dma_flag = 0;
  1115. #ifdef BSP_UART8_RX_USING_DMA
  1116. uart_obj[UART8_INDEX].handle.HDMA_Rx = &uart_obj[UART8_INDEX].dma_rx.handle;
  1117. uart_obj[UART8_INDEX].serial.config.dma_ping_bufsz = BSP_UART8_DMA_PING_BUFSIZE;
  1118. uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
  1119. uart_obj[UART8_INDEX].dma_rx.handle.Parent = &uart_obj[UART8_INDEX].handle;
  1120. uart_obj[UART8_INDEX].dma_rx.handle.DMA_ITC_Callback = HAL_UART_RxCpltCallback;
  1121. uart_obj[UART8_INDEX].dma_rx.handle.Instance = DMA2_Channel10;
  1122. uart_obj[UART8_INDEX].dma_rx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1123. uart_obj[UART8_INDEX].dma_rx.handle.dma_irq = DMA2_Channel10_IRQn;
  1124. #endif
  1125. #ifdef BSP_UART8_TX_USING_DMA
  1126. uart_obj[UART8_INDEX].handle.HDMA_Tx = &uart_obj[UART8_INDEX].dma_tx.handle;
  1127. uart_obj[UART8_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
  1128. uart_obj[UART8_INDEX].dma_tx.handle.Parent = &uart_obj[UART8_INDEX].handle;
  1129. uart_obj[UART8_INDEX].dma_tx.handle.DMA_ITC_Callback = HAL_UART_TxCpltCallback;
  1130. uart_obj[UART8_INDEX].dma_tx.handle.Instance = DMA2_Channel11;
  1131. uart_obj[UART8_INDEX].dma_tx.handle.dma_rcc = RCC_AHBPeriph_DMA2;
  1132. uart_obj[UART8_INDEX].dma_tx.handle.dma_irq = DMA2_Channel11_IRQn;
  1133. #endif
  1134. #endif
  1135. }
  1136. #ifdef RT_SERIAL_USING_DMA
  1137. static void ch32_uart_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
  1138. {
  1139. struct DMA_HandleTypeDef *DMA_Handle;
  1140. struct ch32_uart *uart;
  1141. RT_ASSERT(serial != RT_NULL);
  1142. RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX);
  1143. uart = rt_container_of(serial, struct ch32_uart, serial);
  1144. if (RT_DEVICE_FLAG_DMA_RX == flag)
  1145. {
  1146. DMA_Handle = &uart->dma_rx.handle;
  1147. }
  1148. else /* RT_DEVICE_FLAG_DMA_TX == flag */
  1149. {
  1150. DMA_Handle = &uart->dma_tx.handle;
  1151. }
  1152. RCC_AHBPeriphClockCmd(DMA_Handle->dma_rcc, ENABLE);
  1153. DMA_DeInit(DMA_Handle->Instance);
  1154. DMA_Handle->Init.DMA_PeripheralBaseAddr = (unsigned int)uart->config->Instance + 0x4;
  1155. DMA_Handle->Init.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
  1156. DMA_Handle->Init.DMA_MemoryInc = DMA_MemoryInc_Enable;
  1157. DMA_Handle->Init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
  1158. DMA_Handle->Init.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
  1159. DMA_Handle->Init.DMA_M2M = DMA_M2M_Disable;
  1160. if (RT_DEVICE_FLAG_DMA_RX == flag)
  1161. {
  1162. rt_uint8_t *ptr = NULL;
  1163. rt_hw_serial_control_isr(serial, RT_HW_SERIAL_CTRL_GET_DMA_PING_BUF, &ptr);
  1164. DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralSRC;
  1165. DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)ptr;
  1166. DMA_Handle->Init.DMA_BufferSize = serial->config.dma_ping_bufsz;
  1167. DMA_Handle->Init.DMA_Mode = DMA_Mode_Circular;
  1168. DMA_Handle->Init.DMA_Priority = DMA_Priority_VeryHigh;
  1169. }
  1170. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  1171. {
  1172. DMA_Handle->Init.DMA_DIR = DMA_DIR_PeripheralDST;
  1173. DMA_Handle->Init.DMA_MemoryBaseAddr = (unsigned int)1;
  1174. DMA_Handle->Init.DMA_BufferSize = 1;
  1175. DMA_Handle->Init.DMA_Mode = DMA_Mode_Normal;
  1176. DMA_Handle->Init.DMA_Priority = DMA_Priority_High;
  1177. }
  1178. DMA_Init(DMA_Handle->Instance, &DMA_Handle->Init);
  1179. NVIC_Set(DMA_Handle->dma_irq, ENABLE);
  1180. /* Enable USART DMA Rx or TX request */
  1181. if (RT_DEVICE_FLAG_DMA_RX == flag)
  1182. {
  1183. DMA_Cmd(DMA_Handle->Instance, DISABLE);
  1184. USART_DMACmd(uart->handle.Instance, USART_DMAReq_Rx, ENABLE);
  1185. USART_ITConfig(uart->handle.Instance, USART_IT_IDLE, ENABLE);
  1186. USART_ReceiveData(uart->handle.Instance);
  1187. DMA_ITConfig(DMA_Handle->Instance, DMA_IT_TC, ENABLE);
  1188. NVIC_Set(uart->config->irq_type, ENABLE);
  1189. DMA_Cmd(DMA_Handle->Instance, ENABLE);
  1190. }
  1191. else if (RT_DEVICE_FLAG_DMA_TX == flag)
  1192. {
  1193. USART_DMACmd(uart->handle.Instance, USART_DMAReq_Tx, ENABLE);
  1194. DMA_ITConfig(uart->dma_tx.handle.Instance, DMA_IT_TC, ENABLE);
  1195. }
  1196. USART_Cmd(uart->handle.Instance, ENABLE);
  1197. }
  1198. /**
  1199. * @brief Handle DMA interrupt request.
  1200. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1201. * the configuration information for the specified DMA Channel.
  1202. * @retval None
  1203. */
  1204. static void HAL_DMA_IRQHandler(struct DMA_HandleTypeDef *hdma)
  1205. {
  1206. DMA_TypeDef *dmax = RT_NULL;
  1207. if ((unsigned int)hdma->Instance < DMA2_BASE)
  1208. {
  1209. dmax = DMA1;
  1210. }
  1211. else
  1212. {
  1213. dmax = DMA2;
  1214. }
  1215. unsigned int flag_it = dmax->INTFR;
  1216. unsigned int channel_offset = ((unsigned int)hdma->Instance - (unsigned int)dmax - 8) / 20;
  1217. /* Transfer Complete Interrupt management ***********************************/
  1218. if ((flag_it & 2u << (4 * channel_offset)))
  1219. {
  1220. /* Clear the transfer complete flag */
  1221. dmax->INTFCR |= 2u << (4 * channel_offset);
  1222. struct ch32_uart *uart = (struct ch32_uart *)hdma->Parent;
  1223. /* Call the transfer complete callback */
  1224. if (hdma->DMA_ITC_Callback != RT_NULL)
  1225. {
  1226. hdma->DMA_ITC_Callback(&uart->handle);
  1227. }
  1228. }
  1229. if(flag_it & (8u << (4 * channel_offset)))
  1230. {
  1231. rt_kprintf("DMA error: %d\n", flag_it & (8u << (4 * channel_offset)));
  1232. dmax->INTFCR |= 8u << (4 * channel_offset);
  1233. }
  1234. }
  1235. static void dma_recv_isr(struct rt_serial_device *serial, rt_uint8_t isr_flag)
  1236. {
  1237. struct ch32_uart *uart;
  1238. rt_base_t level;
  1239. rt_size_t recv_len, counter;
  1240. RT_ASSERT(serial != RT_NULL);
  1241. uart = rt_container_of(serial, struct ch32_uart, serial);
  1242. recv_len = 0;
  1243. counter = uart->dma_rx.handle.Instance->CNTR;
  1244. switch (isr_flag)
  1245. {
  1246. case UART_RX_DMA_IT_IDLE_FLAG:
  1247. if (counter <= uart->dma_rx.remaining_cnt)
  1248. recv_len = uart->dma_rx.remaining_cnt - counter;
  1249. else
  1250. recv_len = serial->config.dma_ping_bufsz + uart->dma_rx.remaining_cnt - counter;
  1251. break;
  1252. case UART_RX_DMA_IT_HT_FLAG:
  1253. if (counter < uart->dma_rx.remaining_cnt)
  1254. recv_len = uart->dma_rx.remaining_cnt - counter;
  1255. else
  1256. recv_len = 0;
  1257. break;
  1258. case UART_RX_DMA_IT_TC_FLAG:
  1259. recv_len = uart->dma_rx.remaining_cnt;
  1260. break;
  1261. default:
  1262. recv_len = 0;
  1263. break;
  1264. }
  1265. if (recv_len)
  1266. {
  1267. uart->dma_rx.remaining_cnt = counter;
  1268. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
  1269. }
  1270. }
  1271. void HAL_UART_TxCpltCallback(struct UART_HandleTypeDef *huart)
  1272. {
  1273. RT_ASSERT(huart != NULL);
  1274. struct ch32_uart *uart = (struct ch32_uart *)huart;
  1275. rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE);
  1276. }
  1277. void HAL_UART_RxCpltCallback(struct UART_HandleTypeDef *huart)
  1278. {
  1279. struct ch32_uart *uart;
  1280. RT_ASSERT(huart != NULL);
  1281. uart = (struct ch32_uart *)huart;
  1282. dma_recv_isr(&uart->serial, UART_RX_DMA_IT_TC_FLAG);
  1283. }
  1284. #endif /* RT_SERIAL_USING_DMA */
  1285. static const struct rt_uart_ops ch32_uart_ops =
  1286. {
  1287. .configure = ch32_configure,
  1288. .control = ch32_control,
  1289. .putc = ch32_putc,
  1290. .getc = ch32_getc,
  1291. .transmit = ch32_transmit
  1292. };
  1293. int rt_hw_usart_init(void)
  1294. {
  1295. rt_err_t result = 0;
  1296. rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ch32_uart);
  1297. ch32_uart_get_config();
  1298. for (int i = 0; i < obj_num; i++)
  1299. {
  1300. uart_obj[i].config = &uart_config[i];
  1301. /* init UART object */
  1302. uart_obj[i].serial.ops = &ch32_uart_ops;
  1303. /* register UART device */
  1304. rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX | RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_TX, NULL);
  1305. RT_ASSERT(result == RT_EOK);
  1306. }
  1307. return result;
  1308. }
  1309. #endif /* RT_USING_SERIAL_V2 */