io-domain.c 17 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-11-21 GuEe-GUI first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #define DBG_TAG "soc.rockchip.io-domain"
  14. #define DBG_LVL DBG_INFO
  15. #include <rtdbg.h>
  16. #define MAX_SUPPLIES 16
  17. /*
  18. * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
  19. * "Recommended Operating Conditions" for "Digital GPIO". When the typical
  20. * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
  21. *
  22. * They are used like this:
  23. * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
  24. * SoC we're at 3.3.
  25. * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
  26. * that to be an error.
  27. */
  28. #define MAX_VOLTAGE_1_8 1980000
  29. #define MAX_VOLTAGE_3_3 3600000
  30. struct rockchip_iodomain;
  31. struct rockchip_iodomain_supply
  32. {
  33. struct rockchip_iodomain *domain;
  34. struct rt_regulator *reg;
  35. struct rt_regulator_notifier notifier;
  36. int idx;
  37. };
  38. struct rockchip_iodomain_soc_data
  39. {
  40. int grf_offset;
  41. const char *supply_names[MAX_SUPPLIES];
  42. void (*init)(struct rockchip_iodomain *domain);
  43. rt_err_t (*write)(struct rockchip_iodomain_supply *supply, int uvolt);
  44. };
  45. struct rockchip_iodomain
  46. {
  47. struct rt_device *dev;
  48. struct rt_syscon *grf;
  49. const struct rockchip_iodomain_soc_data *soc_data;
  50. struct rockchip_iodomain_supply supplies[MAX_SUPPLIES];
  51. rt_err_t (*write)(struct rockchip_iodomain_supply *supply, int uvolt);
  52. };
  53. #define PX30_IO_VSEL 0x180
  54. #define PX30_IO_VSEL_VCCIO6_SRC RT_BIT(0)
  55. #define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
  56. static void px30_iodomain_init(struct rockchip_iodomain *domain)
  57. {
  58. rt_uint32_t val;
  59. /* if no VCCIO6 supply we should leave things alone */
  60. if (!domain->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg)
  61. {
  62. return;
  63. }
  64. /* set vccio6 iodomain to also use this framework instead of a special gpio. */
  65. val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16);
  66. if (rt_syscon_write(domain->grf, PX30_IO_VSEL, val) < 0)
  67. {
  68. LOG_W("Couldn't update %s ctrl", "vccio6");
  69. }
  70. }
  71. static const struct rockchip_iodomain_soc_data soc_data_px30 =
  72. {
  73. .grf_offset = 0x180,
  74. .supply_names =
  75. {
  76. [1] =
  77. "vccio6",
  78. "vccio1",
  79. "vccio2",
  80. "vccio3",
  81. "vccio4",
  82. "vccio5",
  83. "vccio-oscgpi",
  84. },
  85. .init = px30_iodomain_init,
  86. };
  87. static const struct rockchip_iodomain_soc_data soc_data_px30_pmu =
  88. {
  89. .grf_offset = 0x100,
  90. .supply_names =
  91. {
  92. [14] =
  93. "pmuio1",
  94. "pmuio2",
  95. },
  96. };
  97. /*
  98. * On the rk3188 the io-domains are handled by a shared register with the lower
  99. * 8 bits being still being continuing drive-strength settings.
  100. */
  101. static const struct rockchip_iodomain_soc_data soc_data_rk3188 =
  102. {
  103. .grf_offset = 0x104,
  104. .supply_names =
  105. {
  106. [8] =
  107. "ap0",
  108. "ap1",
  109. "cif",
  110. "flash",
  111. "vccio0",
  112. "vccio1",
  113. "lcdc0",
  114. "lcdc1",
  115. },
  116. };
  117. static const struct rockchip_iodomain_soc_data soc_data_rk3228 =
  118. {
  119. .grf_offset = 0x418,
  120. .supply_names =
  121. {
  122. "vccio1",
  123. "vccio2",
  124. "vccio3",
  125. "vccio4",
  126. },
  127. };
  128. #define RK3288_SOC_CON2 0x24c
  129. #define RK3288_SOC_CON2_FLASH0 RT_BIT(7)
  130. #define RK3288_SOC_FLASH_SUPPLY_NUM 2
  131. static void rk3288_iodomain_init(struct rockchip_iodomain *domain)
  132. {
  133. rt_uint32_t val;
  134. /* if no flash supply we should leave things alone */
  135. if (!domain->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg)
  136. {
  137. return;
  138. }
  139. /* set flash0 iodomain to also use this framework instead of a special gpio. */
  140. val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16);
  141. if (rt_syscon_write(domain->grf, RK3288_SOC_CON2, val) < 0)
  142. {
  143. LOG_W("Couldn't update %s ctrl", "flash0");
  144. }
  145. }
  146. static const struct rockchip_iodomain_soc_data soc_data_rk3288 =
  147. {
  148. .grf_offset = 0x380,
  149. .supply_names =
  150. {
  151. "lcdc", /* LCDC_VDD */
  152. "dvp", /* DVPIO_VDD */
  153. "flash0", /* FLASH0_VDD (emmc) */
  154. "flash1", /* FLASH1_VDD (sdio1) */
  155. "wifi", /* APIO3_VDD (sdio0) */
  156. "bb", /* APIO5_VDD */
  157. "audio", /* APIO4_VDD */
  158. "sdcard", /* SDMMC0_VDD (sdmmc) */
  159. "gpio30", /* APIO1_VDD */
  160. "gpio1830", /* APIO2_VDD */
  161. },
  162. .init = rk3288_iodomain_init,
  163. };
  164. #define RK3308_SOC_CON0 0x300
  165. #define RK3308_SOC_CON0_VCCIO3 RT_BIT(8)
  166. #define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
  167. static void rk3308_iodomain_init(struct rockchip_iodomain *domain)
  168. {
  169. rt_uint32_t val;
  170. /* if no vccio3 supply we should leave things alone */
  171. if (!domain->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
  172. {
  173. return;
  174. }
  175. /* set vccio3 iodomain to also use this framework instead of a special gpio. */
  176. val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
  177. if (rt_syscon_write(domain->grf, RK3308_SOC_CON0, val) < 0)
  178. {
  179. LOG_W("Couldn't update %s ctrl", "vccio3");
  180. }
  181. }
  182. static const struct rockchip_iodomain_soc_data soc_data_rk3308 =
  183. {
  184. .grf_offset = 0x300,
  185. .supply_names =
  186. {
  187. "vccio0",
  188. "vccio1",
  189. "vccio2",
  190. "vccio3",
  191. "vccio4",
  192. "vccio5",
  193. },
  194. .init = rk3308_iodomain_init,
  195. };
  196. #define RK3328_SOC_CON4 0x410
  197. #define RK3328_SOC_CON4_VCCIO2 RT_BIT(7)
  198. #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
  199. static void rk3328_iodomain_init(struct rockchip_iodomain *domain)
  200. {
  201. rt_uint32_t val;
  202. /* if no vccio2 supply we should leave things alone */
  203. if (!domain->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg)
  204. {
  205. return;
  206. }
  207. /* set vccio2 iodomain to also use this framework instead of a special gpio. */
  208. val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16);
  209. if (rt_syscon_write(domain->grf, RK3328_SOC_CON4, val) < 0)
  210. {
  211. LOG_W("Couldn't update %s ctrl", "vccio2 vsel");
  212. }
  213. }
  214. static const struct rockchip_iodomain_soc_data soc_data_rk3328 =
  215. {
  216. .grf_offset = 0x410,
  217. .supply_names =
  218. {
  219. "vccio1",
  220. "vccio2",
  221. "vccio3",
  222. "vccio4",
  223. "vccio5",
  224. "vccio6",
  225. "pmuio",
  226. },
  227. .init = rk3328_iodomain_init,
  228. };
  229. #define RK3368_SOC_CON15 0x43c
  230. #define RK3368_SOC_CON15_FLASH0 RT_BIT(14)
  231. #define RK3368_SOC_FLASH_SUPPLY_NUM 2
  232. static void rk3368_iodomain_init(struct rockchip_iodomain *domain)
  233. {
  234. rt_uint32_t val;
  235. /* if no flash supply we should leave things alone */
  236. if (!domain->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg)
  237. {
  238. return;
  239. }
  240. /* set flash0 iodomain to also use this framework instead of a special gpio. */
  241. val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16);
  242. if (rt_syscon_write(domain->grf, RK3368_SOC_CON15, val) < 0)
  243. {
  244. LOG_W("Couldn't update %s ctrl", "flash0");
  245. }
  246. }
  247. static const struct rockchip_iodomain_soc_data soc_data_rk3368 =
  248. {
  249. .grf_offset = 0x900,
  250. .supply_names =
  251. {
  252. RT_NULL, /* Reserved */
  253. "dvp", /* DVPIO_VDD */
  254. "flash0", /* FLASH0_VDD (emmc) */
  255. "wifi", /* APIO2_VDD (sdio0) */
  256. RT_NULL,
  257. "audio", /* APIO3_VDD */
  258. "sdcard", /* SDMMC0_VDD (sdmmc) */
  259. "gpio30", /* APIO1_VDD */
  260. "gpio1830", /* APIO4_VDD (gpujtag) */
  261. },
  262. .init = rk3368_iodomain_init,
  263. };
  264. static const struct rockchip_iodomain_soc_data soc_data_rk3368_pmu =
  265. {
  266. .grf_offset = 0x100,
  267. .supply_names =
  268. {
  269. [4] =
  270. "pmu", /* PMU IO domain*/
  271. "vop", /* LCDC IO domain*/
  272. },
  273. };
  274. static const struct rockchip_iodomain_soc_data soc_data_rk3399 =
  275. {
  276. .grf_offset = 0xe640,
  277. .supply_names =
  278. {
  279. "bt656", /* APIO2_VDD */
  280. "audio", /* APIO5_VDD */
  281. "sdmmc", /* SDMMC0_VDD */
  282. "gpio1830", /* APIO4_VDD */
  283. },
  284. };
  285. #define RK3399_PMUGRF_CON0 0x180
  286. #define RK3399_PMUGRF_CON0_VSEL RT_BIT(8)
  287. #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
  288. static void rk3399_pmu_iodomain_init(struct rockchip_iodomain *domain)
  289. {
  290. rt_uint32_t val;
  291. /* if no pmu io supply we should leave things alone */
  292. if (!domain->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg)
  293. {
  294. return;
  295. }
  296. /* set pmu io iodomain to also use this framework instead of a special gpio. */
  297. val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16);
  298. if (rt_syscon_write(domain->grf, RK3399_PMUGRF_CON0, val) < 0)
  299. {
  300. LOG_W("couldn't update %s ctrl", "pmu io iodomain");
  301. }
  302. }
  303. static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu =
  304. {
  305. .grf_offset = 0x180,
  306. .supply_names =
  307. {
  308. [9] =
  309. "pmu1830", /* PMUIO2_VDD */
  310. },
  311. .init = rk3399_pmu_iodomain_init,
  312. };
  313. #define RK3568_PMU_GRF_IO_VSEL0 0x0140
  314. #define RK3568_PMU_GRF_IO_VSEL1 0x0144
  315. #define RK3568_PMU_GRF_IO_VSEL2 0x0148
  316. static rt_err_t rk3568_iodomain_write(struct rockchip_iodomain_supply *supply, int uvolt)
  317. {
  318. rt_uint32_t bit, is_3v3 = uvolt > MAX_VOLTAGE_1_8, val0, val1;
  319. struct rockchip_iodomain *domain = supply->domain;
  320. switch (supply->idx)
  321. {
  322. case 0: /* pmuio1 */
  323. break;
  324. case 1: /* pmuio2 */
  325. bit = supply->idx;
  326. val0 = RT_BIT(16 + bit) | (is_3v3 ? 0 : RT_BIT(bit));
  327. bit = supply->idx + 4;
  328. val1 = RT_BIT(16 + bit) | (is_3v3 ? RT_BIT(bit) : 0);
  329. rt_syscon_write(domain->grf, RK3568_PMU_GRF_IO_VSEL2, val0);
  330. rt_syscon_write(domain->grf, RK3568_PMU_GRF_IO_VSEL2, val1);
  331. break;
  332. case 3: /* vccio2 */
  333. break;
  334. case 2: /* vccio1 */
  335. case 4: /* vccio3 */
  336. case 5: /* vccio4 */
  337. case 6: /* vccio5 */
  338. case 7: /* vccio6 */
  339. case 8: /* vccio7 */
  340. bit = supply->idx - 1;
  341. val0 = RT_BIT(16 + bit) | (is_3v3 ? 0 : RT_BIT(bit));
  342. val1 = RT_BIT(16 + bit) | (is_3v3 ? RT_BIT(bit) : 0);
  343. rt_syscon_write(domain->grf, RK3568_PMU_GRF_IO_VSEL0, val0);
  344. rt_syscon_write(domain->grf, RK3568_PMU_GRF_IO_VSEL1, val1);
  345. break;
  346. default:
  347. return -RT_EINVAL;
  348. }
  349. return 0;
  350. }
  351. static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu =
  352. {
  353. .grf_offset = 0x140,
  354. .supply_names =
  355. {
  356. "pmuio1",
  357. "pmuio2",
  358. "vccio1",
  359. "vccio2",
  360. "vccio3",
  361. "vccio4",
  362. "vccio5",
  363. "vccio6",
  364. "vccio7",
  365. },
  366. .write = rk3568_iodomain_write,
  367. };
  368. static const struct rockchip_iodomain_soc_data soc_data_rv1108 =
  369. {
  370. .grf_offset = 0x404,
  371. .supply_names =
  372. {
  373. [11] =
  374. "vccio1",
  375. "vccio2",
  376. "vccio3",
  377. "vccio5",
  378. "vccio6",
  379. },
  380. };
  381. static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu =
  382. {
  383. .grf_offset = 0x104,
  384. .supply_names =
  385. {
  386. "pmu",
  387. },
  388. };
  389. static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu =
  390. {
  391. .grf_offset = 0x140,
  392. .supply_names =
  393. {
  394. [1] =
  395. "vccio1",
  396. "vccio2",
  397. "vccio3",
  398. "vccio4",
  399. "vccio5",
  400. "vccio6",
  401. "vccio7",
  402. "pmuio0",
  403. "pmuio1",
  404. },
  405. };
  406. static rt_err_t rockchip_iodomain_write(struct rockchip_iodomain_supply *supply, int uvolt)
  407. {
  408. rt_err_t err;
  409. rt_uint32_t val;
  410. struct rockchip_iodomain *domain = supply->domain;
  411. /* set value bit */
  412. val = (uvolt > MAX_VOLTAGE_1_8) ? 0 : 1;
  413. val <<= supply->idx;
  414. /* apply hiword-mask */
  415. val |= (RT_BIT(supply->idx) << 16);
  416. if ((err = rt_syscon_write(domain->grf, domain->soc_data->grf_offset, val)))
  417. {
  418. LOG_E("Couldn't write to GRF");
  419. }
  420. return err;
  421. }
  422. static rt_err_t rockchip_iodomain_notify(struct rt_regulator_notifier *notifier,
  423. rt_ubase_t msg, void *data)
  424. {
  425. int uvolt = 0;
  426. rt_err_t err;
  427. struct rockchip_iodomain_supply *supply;
  428. supply = rt_container_of(notifier, struct rockchip_iodomain_supply, notifier);
  429. if (msg == RT_REGULATOR_MSG_VOLTAGE_CHANGE)
  430. {
  431. union rt_regulator_notifier_args *args = data;
  432. uvolt = rt_max(args->old_uvolt, args->max_uvolt);
  433. }
  434. else if (msg == RT_REGULATOR_MSG_VOLTAGE_CHANGE_ERR)
  435. {
  436. uvolt = (int)(rt_base_t)data;
  437. }
  438. if (uvolt > MAX_VOLTAGE_3_3)
  439. {
  440. LOG_E("Voltage too high: %d", uvolt);
  441. if (msg == RT_REGULATOR_MSG_VOLTAGE_CHANGE)
  442. {
  443. return -RT_EIO;
  444. }
  445. }
  446. err = supply->domain->write(supply, uvolt);
  447. if (err && msg == RT_REGULATOR_MSG_VOLTAGE_CHANGE)
  448. {
  449. return -RT_EIO;
  450. }
  451. LOG_D("Setting to %d done", uvolt);
  452. return err;
  453. }
  454. static rt_err_t rockchip_iodomain_probe(struct rt_platform_device *pdev)
  455. {
  456. rt_err_t err = RT_EOK;
  457. struct rt_ofw_node *np, *grf_np;
  458. struct rockchip_iodomain *domain = rt_calloc(1, sizeof(*domain));
  459. if (!domain)
  460. {
  461. return -RT_ENOMEM;
  462. }
  463. domain->dev = &pdev->parent;
  464. domain->soc_data = pdev->id->data;
  465. domain->write = domain->soc_data->write ? : rockchip_iodomain_write;
  466. np = pdev->parent.ofw_node;
  467. if ((grf_np = rt_ofw_get_parent(np)))
  468. {
  469. domain->grf = rt_syscon_find_by_ofw_node(grf_np);
  470. rt_ofw_node_put(grf_np);
  471. }
  472. else
  473. {
  474. domain->grf = rt_syscon_find_by_ofw_phandle(np, "rockchip,grf");
  475. }
  476. if (!domain->grf)
  477. {
  478. err = -RT_EIO;
  479. goto _fail;
  480. }
  481. for (int i = 0; i < MAX_SUPPLIES; ++i)
  482. {
  483. int uvolt;
  484. struct rt_regulator *reg;
  485. struct rockchip_iodomain_supply *supply;
  486. const char *supply_name = domain->soc_data->supply_names[i];
  487. if (!supply_name)
  488. {
  489. continue;
  490. }
  491. supply = &domain->supplies[i];
  492. reg = rt_regulator_get(domain->dev, supply_name);
  493. if (rt_is_err(reg))
  494. {
  495. err = rt_ptr_err(reg);
  496. goto _fail;
  497. }
  498. if (!reg)
  499. {
  500. continue;
  501. }
  502. uvolt = rt_regulator_get_voltage(reg);
  503. if (uvolt < 0)
  504. {
  505. /* Maybe is a switch */
  506. if (uvolt == -RT_ENOSYS)
  507. {
  508. rt_regulator_put(reg);
  509. continue;
  510. }
  511. LOG_E("Can't determine voltage: %s", supply_name);
  512. err = uvolt;
  513. goto _fail;
  514. }
  515. if (uvolt > MAX_VOLTAGE_3_3)
  516. {
  517. LOG_E("Voltage too high: %d", uvolt);
  518. err = -RT_EIO;
  519. goto _fail;
  520. }
  521. supply->idx = i;
  522. supply->domain = domain;
  523. supply->reg = reg;
  524. supply->notifier.callback = rockchip_iodomain_notify;
  525. if (domain->write(supply, uvolt))
  526. {
  527. rt_regulator_put(supply->reg);
  528. supply->reg = RT_NULL;
  529. goto _fail;
  530. }
  531. if ((err = rt_regulator_notifier_register(supply->reg, &supply->notifier)))
  532. {
  533. rt_regulator_put(supply->reg);
  534. supply->reg = RT_NULL;
  535. goto _fail;
  536. }
  537. }
  538. if (domain->soc_data->init)
  539. {
  540. domain->soc_data->init(domain);
  541. }
  542. return RT_EOK;
  543. _fail:
  544. for (int i = MAX_SUPPLIES - 1; i >= 0; --i)
  545. {
  546. struct rockchip_iodomain_supply *supply = &domain->supplies[i];
  547. if (!rt_is_err_or_null(supply->reg))
  548. {
  549. rt_regulator_notifier_unregister(supply->reg, &supply->notifier);
  550. rt_regulator_put(supply->reg);
  551. }
  552. }
  553. rt_free(domain);
  554. return err;
  555. }
  556. static const struct rt_ofw_node_id rockchip_iodomain_ofw_ids[] =
  557. {
  558. { .compatible = "rockchip,px30-io-voltage-domain", .data = &soc_data_px30 },
  559. { .compatible = "rockchip,px30-pmu-io-voltage-domain", .data = &soc_data_px30_pmu },
  560. { .compatible = "rockchip,rk3188-io-voltage-domain", .data = &soc_data_rk3188 },
  561. { .compatible = "rockchip,rk3228-io-voltage-domain", .data = &soc_data_rk3228 },
  562. { .compatible = "rockchip,rk3288-io-voltage-domain", .data = &soc_data_rk3288 },
  563. { .compatible = "rockchip,rk3308-io-voltage-domain", .data = &soc_data_rk3308 },
  564. { .compatible = "rockchip,rk3328-io-voltage-domain", .data = &soc_data_rk3328 },
  565. { .compatible = "rockchip,rk3368-io-voltage-domain", .data = &soc_data_rk3368 },
  566. { .compatible = "rockchip,rk3368-pmu-io-voltage-domain", .data = &soc_data_rk3368_pmu },
  567. { .compatible = "rockchip,rk3399-io-voltage-domain", .data = &soc_data_rk3399 },
  568. { .compatible = "rockchip,rk3399-pmu-io-voltage-domain", .data = &soc_data_rk3399_pmu },
  569. { .compatible = "rockchip,rk3568-pmu-io-voltage-domain", .data = &soc_data_rk3568_pmu },
  570. { .compatible = "rockchip,rv1108-io-voltage-domain", .data = &soc_data_rv1108 },
  571. { .compatible = "rockchip,rv1108-pmu-io-voltage-domain", .data = &soc_data_rv1108_pmu },
  572. { .compatible = "rockchip,rv1126-pmu-io-voltage-domain", .data = &soc_data_rv1126_pmu },
  573. { /* sentinel */ }
  574. };
  575. static struct rt_platform_driver rockchip_iodomain_driver =
  576. {
  577. .name = "rockchip-iodomain",
  578. .ids = rockchip_iodomain_ofw_ids,
  579. .probe = rockchip_iodomain_probe,
  580. };
  581. static int rockchip_iodomain_register(void)
  582. {
  583. rt_platform_driver_register(&rockchip_iodomain_driver);
  584. return 0;
  585. }
  586. INIT_PREV_EXPORT(rockchip_iodomain_register);