drv_i2c.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419
  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Email: opensource_embedded@phytium.com.cn
  7. *
  8. * Change Logs:
  9. * Date Author Notes
  10. * 2023-10-23 zhangyan first version
  11. *
  12. */
  13. #include "rtconfig.h"
  14. #include <rtdevice.h>
  15. #define LOG_TAG "i2c_drv"
  16. #include "drv_log.h"
  17. #include "drv_i2c.h"
  18. #include "fi2c.h"
  19. #include "fi2c_hw.h"
  20. #include "fio_mux.h"
  21. #include "fmio_hw.h"
  22. #include "fmio.h"
  23. #include "drivers/i2c.h"
  24. #include "fparameters.h"
  25. #ifdef RT_USING_SMART
  26. #include <ioremap.h>
  27. #endif
  28. /*Please define the length of the mem_addr of the device*/
  29. #ifndef FI2C_DEVICE_MEMADDR_LEN
  30. #define FI2C_DEVICE_MEMADDR_LEN 2
  31. #endif
  32. #define FI2C_DEFAULT_ID 0
  33. #define I2C_USE_MIO
  34. #if defined(I2C_USE_MIO)
  35. static FMioCtrl mio_handle;
  36. #endif
  37. struct phytium_i2c_bus
  38. {
  39. struct rt_i2c_bus_device device;
  40. FI2c i2c_handle;
  41. struct rt_i2c_msg *msg;
  42. const char *name;
  43. };
  44. #if defined(I2C_USE_CONTROLLER)
  45. static rt_err_t i2c_config(struct phytium_i2c_bus *i2c_bus)
  46. {
  47. RT_ASSERT(i2c_bus);
  48. FI2cConfig input_cfg;
  49. const FI2cConfig *config_p = NULL;
  50. FI2c *instance_p = &i2c_bus->i2c_handle;
  51. FError ret = FI2C_SUCCESS;
  52. /* Lookup default configs by instance id */
  53. config_p = FI2cLookupConfig(instance_p->config.instance_id);
  54. input_cfg = *config_p;
  55. #ifdef RT_USING_SMART
  56. input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000);
  57. #endif
  58. input_cfg.speed_rate = FI2C_SPEED_STANDARD_RATE;
  59. input_cfg.work_mode = FI2C_MASTER;
  60. FI2cDeInitialize(&i2c_bus->i2c_handle);
  61. /* Initialization */
  62. ret = FI2cCfgInitialize(instance_p, &input_cfg);
  63. if (ret != FI2C_SUCCESS)
  64. {
  65. LOG_E("Init master I2c failed, ret: 0x%x", ret);
  66. return -RT_ERROR;
  67. }
  68. return RT_EOK;
  69. }
  70. #endif
  71. #if defined(I2C_USE_MIO)
  72. static rt_err_t i2c_mio_config(struct phytium_i2c_bus *i2c_bus)
  73. {
  74. RT_ASSERT(i2c_bus);
  75. FI2cConfig input_cfg;
  76. const FI2cConfig *config_p = NULL;
  77. FI2c *instance_p = &i2c_bus->i2c_handle;
  78. FError ret = FI2C_SUCCESS;
  79. mio_handle.config = *FMioLookupConfig(instance_p->config.instance_id);
  80. #ifdef RT_USING_SMART
  81. mio_handle.config.func_base_addr = (uintptr)rt_ioremap((void *)mio_handle.config.func_base_addr, 0x1200);
  82. mio_handle.config.mio_base_addr = (uintptr)rt_ioremap((void *)mio_handle.config.mio_base_addr, 0x200);
  83. #endif
  84. ret = FMioFuncInit(&mio_handle, FMIO_FUNC_SET_I2C);
  85. if (ret != FT_SUCCESS)
  86. {
  87. LOG_E("MIO initialize error.");
  88. return -RT_ERROR;
  89. }
  90. FIOPadSetMioMux(instance_p->config.instance_id);
  91. config_p = FI2cLookupConfig(FI2C_DEFAULT_ID);
  92. if (NULL == config_p)
  93. {
  94. LOG_E("Config of mio instance %d non found.", instance_p->config.instance_id);
  95. return -RT_ERROR;
  96. }
  97. input_cfg = *config_p;
  98. input_cfg.instance_id = instance_p->config.instance_id;
  99. input_cfg.base_addr = FMioFuncGetAddress(&mio_handle, FMIO_FUNC_SET_I2C);
  100. input_cfg.irq_num = FMioFuncGetIrqNum(&mio_handle, FMIO_FUNC_SET_I2C);
  101. input_cfg.ref_clk_hz = FMIO_CLK_FREQ_HZ;
  102. input_cfg.speed_rate = FI2C_SPEED_STANDARD_RATE;
  103. ret = FI2cCfgInitialize(&i2c_bus->i2c_handle, &input_cfg);
  104. if (FI2C_SUCCESS != ret)
  105. {
  106. LOG_E("Init mio master failed, ret: 0x%x", ret);
  107. return -RT_ERROR;
  108. }
  109. mio_handle.is_ready = 0;
  110. memset(&mio_handle, 0, sizeof(mio_handle));
  111. return RT_EOK;
  112. }
  113. #endif
  114. static rt_err_t phytium_i2c_set_speed(struct phytium_i2c_bus *i2c_bus, rt_uint32_t speed)
  115. {
  116. RT_ASSERT(i2c_bus);
  117. u32 ret;
  118. uintptr base_addr = i2c_bus->i2c_handle.config.base_addr;
  119. ret = FI2cSetSpeed(base_addr, speed);
  120. if (ret != FI2C_SUCCESS)
  121. {
  122. LOG_E("Set i2c speed failed!\n");
  123. return -RT_ERROR;
  124. }
  125. return RT_EOK;
  126. }
  127. static rt_err_t i2c_bus_control(struct rt_i2c_bus_device *device, int cmd, void *args)
  128. {
  129. RT_ASSERT(device);
  130. struct phytium_i2c_bus *i2c_bus;
  131. i2c_bus = (struct phytium_i2c_bus *)(device);
  132. FI2cConfig *config_p;
  133. switch (cmd)
  134. {
  135. case RT_I2C_DEV_CTRL_CLK:
  136. phytium_i2c_set_speed(i2c_bus, *(rt_uint32_t *)args);
  137. break;
  138. case RT_I2C_DEV_CTRL_10BIT:
  139. config_p = &i2c_bus->i2c_handle.config;
  140. config_p->use_7bit_addr = FALSE;
  141. FI2cCfgInitialize(&i2c_bus->i2c_handle, config_p);
  142. break;
  143. default:
  144. return -RT_EIO;
  145. }
  146. return RT_EOK;
  147. }
  148. static rt_ssize_t i2c_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2c_msg msgs[], rt_uint32_t num)
  149. {
  150. RT_ASSERT(device);
  151. u32 ret;
  152. struct rt_i2c_msg *pmsg;
  153. rt_ssize_t i;
  154. struct phytium_i2c_bus *i2c_bus;
  155. i2c_bus = (struct phytium_i2c_bus *)(device);
  156. uintptr mem_addr = 0;
  157. for (i = 0; i < num; i++)
  158. {
  159. pmsg = &msgs[i];
  160. for (u32 j = 0; j <FI2C_DEVICE_MEMADDR_LEN; j++)
  161. {
  162. mem_addr |= msgs[i].buf[j] << (8 * (FI2C_DEVICE_MEMADDR_LEN - 1 - j));
  163. }
  164. i2c_bus->i2c_handle.config.slave_addr = pmsg->addr;
  165. if (pmsg->flags & RT_I2C_RD)
  166. {
  167. rt_thread_delay(100);
  168. ret = FI2cMasterReadPoll(&i2c_bus->i2c_handle, mem_addr, FI2C_DEVICE_MEMADDR_LEN, &pmsg->buf[0], pmsg->len - FI2C_DEVICE_MEMADDR_LEN);
  169. if (ret != FI2C_SUCCESS)
  170. {
  171. LOG_E("I2C master read failed!\n");
  172. return -RT_ERROR;
  173. }
  174. }
  175. else
  176. {
  177. rt_thread_delay(100);
  178. ret = FI2cMasterWritePoll(&i2c_bus->i2c_handle, mem_addr, FI2C_DEVICE_MEMADDR_LEN, &pmsg->buf[FI2C_DEVICE_MEMADDR_LEN], pmsg->len - FI2C_DEVICE_MEMADDR_LEN);
  179. if (ret != FI2C_SUCCESS)
  180. {
  181. LOG_E("I2C master write failed!\n");
  182. return -RT_ERROR;
  183. }
  184. }
  185. }
  186. return i;
  187. }
  188. static const struct rt_i2c_bus_device_ops _i2c_ops =
  189. {
  190. .master_xfer = i2c_master_xfer,
  191. .slave_xfer = NULL,
  192. .i2c_bus_control = i2c_bus_control
  193. };
  194. #if defined(I2C_USE_CONTROLLER)
  195. static int i2c_controller_init(struct phytium_i2c_bus *i2c_controller_bus)
  196. {
  197. rt_err_t ret = RT_EOK;
  198. ret = i2c_config(i2c_controller_bus);
  199. if (ret != RT_EOK)
  200. {
  201. LOG_E("I2C config failed.\n");
  202. return -RT_ERROR;
  203. }
  204. i2c_controller_bus->device.ops = &_i2c_ops;
  205. ret = rt_i2c_bus_device_register(&i2c_controller_bus->device, i2c_controller_bus->name);
  206. RT_ASSERT(RT_EOK == ret);
  207. LOG_D("I2C bus reg success.\n");
  208. return ret;
  209. }
  210. #endif
  211. #if defined(I2C_USE_MIO)
  212. static int i2c_mio_init(struct phytium_i2c_bus *i2c_mio_bus)
  213. {
  214. rt_err_t ret = RT_EOK;
  215. ret = i2c_mio_config(i2c_mio_bus);
  216. if (ret != RT_EOK)
  217. {
  218. LOG_E("I2C mio config failed.\n");
  219. return -RT_ERROR;
  220. }
  221. i2c_mio_bus->device.ops = &_i2c_ops;
  222. ret = rt_i2c_bus_device_register(&i2c_mio_bus->device, i2c_mio_bus->name);
  223. RT_ASSERT(RT_EOK == ret);
  224. LOG_D("I2C mio bus reg success.\n");
  225. return ret;
  226. }
  227. #endif
  228. #if defined(RT_USING_I2C0)
  229. static struct phytium_i2c_bus i2c_controller0_bus;
  230. #endif
  231. #if defined(RT_USING_I2C1)
  232. static struct phytium_i2c_bus i2c_controller1_bus;
  233. #endif
  234. #if defined(RT_USING_I2C2)
  235. static struct phytium_i2c_bus i2c_controller2_bus;
  236. #endif
  237. #if defined(RT_USING_MIO0)
  238. static struct phytium_i2c_bus i2c_mio0_bus;
  239. #endif
  240. #if defined(RT_USING_MIO1)
  241. static struct phytium_i2c_bus i2c_mio1_bus;
  242. #endif
  243. #if defined(RT_USING_MIO2)
  244. static struct phytium_i2c_bus i2c_mio2_bus;
  245. #endif
  246. #if defined(RT_USING_MIO3)
  247. static struct phytium_i2c_bus i2c_mio3_bus;
  248. #endif
  249. #if defined(RT_USING_MIO4)
  250. static struct phytium_i2c_bus i2c_mio4_bus;
  251. #endif
  252. #if defined(RT_USING_MIO5)
  253. static struct phytium_i2c_bus i2c_mio5_bus;
  254. #endif
  255. #if defined(RT_USING_MIO6)
  256. static struct phytium_i2c_bus i2c_mio6_bus;
  257. #endif
  258. #if defined(RT_USING_MIO7)
  259. static struct phytium_i2c_bus i2c_mio7_bus;
  260. #endif
  261. #if defined(RT_USING_MIO8)
  262. static struct phytium_i2c_bus i2c_mio8_bus;
  263. #endif
  264. #if defined(RT_USING_MIO9)
  265. static struct phytium_i2c_bus i2c_mio9_bus;
  266. #endif
  267. #if defined(RT_USING_MIO10)
  268. static struct phytium_i2c_bus i2c_mio10_bus;
  269. #endif
  270. #if defined(RT_USING_MIO11)
  271. static struct phytium_i2c_bus i2c_mio11_bus;
  272. #endif
  273. #if defined(RT_USING_MIO12)
  274. static struct phytium_i2c_bus i2c_mio12_bus;
  275. #endif
  276. #if defined(RT_USING_MIO13)
  277. static struct phytium_i2c_bus i2c_mio13_bus;
  278. #endif
  279. #if defined(RT_USING_MIO14)
  280. static struct phytium_i2c_bus i2c_mio14_bus;
  281. #endif
  282. #if defined(RT_USING_MIO15)
  283. static struct phytium_i2c_bus i2c_mio15_bus;
  284. #endif
  285. int rt_hw_i2c_init(void)
  286. {
  287. #if defined(RT_USING_I2C0)
  288. i2c_controller0_bus.name = "I2C0";
  289. i2c_controller0_bus.i2c_handle.config.instance_id = FI2C0_ID;
  290. i2c_controller_init(&i2c_controller0_bus);
  291. #endif
  292. #if defined(RT_USING_I2C1)
  293. i2c_controller1_bus.name = "I2C1";
  294. i2c_controller1_bus.i2c_handle.config.instance_id = FI2C1_ID;
  295. i2c_controller_init(&i2c_controller1_bus);
  296. #endif
  297. #if defined(RT_USING_I2C2)
  298. i2c_controller2_bus.name = "I2C2";
  299. i2c_controller2_bus.i2c_handle.config.instance_id = FI2C2_ID;
  300. i2c_controller_init(&i2c_controller2_bus);
  301. #endif
  302. #if defined(RT_USING_MIO0)
  303. i2c_mio0_bus.name = "MIO0";
  304. i2c_mio0_bus.i2c_handle.config.instance_id = FMIO0_ID;
  305. i2c_mio_init(&i2c_mio0_bus);
  306. #endif
  307. #if defined(RT_USING_MIO1)
  308. i2c_mio1_bus.name = "MIO1";
  309. i2c_mio1_bus.i2c_handle.config.instance_id = FMIO1_ID;
  310. i2c_mio_init(&i2c_mio1_bus);
  311. #endif
  312. #if defined(RT_USING_MIO2)
  313. i2c_mio2_bus.name = "MIO2";
  314. i2c_mio2_bus.i2c_handle.config.instance_id = FMIO2_ID;
  315. i2c_mio_init(&i2c_mio2_bus);
  316. #endif
  317. #if defined(RT_USING_MIO3)
  318. i2c_mio3_bus.name = "MIO3";
  319. i2c_mio3_bus.i2c_handle.config.instance_id = FMIO3_ID;
  320. i2c_mio_init(&i2c_mio3_bus);
  321. #endif
  322. #if defined(RT_USING_MIO4)
  323. i2c_mio4_bus.name = "MIO4";
  324. i2c_mio4_bus.i2c_handle.config.instance_id = FMIO4_ID;
  325. i2c_mio_init(&i2c_mio4_bus);
  326. #endif
  327. #if defined(RT_USING_MIO5)
  328. i2c_mio5_bus.name = "MIO5";
  329. i2c_mio5_bus.i2c_handle.config.instance_id = FMIO5_ID;
  330. i2c_mio_init(&i2c_mio5_bus);
  331. #endif
  332. #if defined(RT_USING_MIO6)
  333. i2c_mio6_bus.name = "MIO6";
  334. i2c_mio6_bus.i2c_handle.config.instance_id = FMIO6_ID;
  335. i2c_mio_init(&i2c_mio6_bus);
  336. #endif
  337. #if defined(RT_USING_MIO7)
  338. i2c_mio7_bus.name = "MIO2";
  339. i2c_mio7_bus.i2c_handle.config.instance_id = FMIO7_ID;
  340. i2c_mio_init(&i2c_mio7_bus);
  341. #endif
  342. #if defined(RT_USING_MIO8)
  343. i2c_mio8_bus.name = "MIO8";
  344. i2c_mio8_bus.i2c_handle.config.instance_id = FMIO8_ID;
  345. i2c_mio_init(&i2c_mio8_bus);
  346. #endif
  347. #if defined(RT_USING_MIO9)
  348. i2c_mio9_bus.name = "MIO9";
  349. i2c_mio9_bus.i2c_handle.config.instance_id = FMIO9_ID;
  350. i2c_mio_init(&i2c_mio9_bus);
  351. #endif
  352. #if defined(RT_USING_MIO10)
  353. i2c_mio10_bus.name = "MIO10";
  354. i2c_mio10_bus.i2c_handle.config.instance_id = FMIO10_ID;
  355. i2c_mio_init(&i2c_mio10_bus);
  356. #endif
  357. #if defined(RT_USING_MIO11)
  358. i2c_mio11_bus.name = "MIO11";
  359. i2c_mio11_bus.i2c_handle.config.instance_id = FMIO11_ID;
  360. i2c_mio_init(&i2c_mio11_bus);
  361. #endif
  362. #if defined(RT_USING_MIO12)
  363. i2c_mio12_bus.name = "MIO12";
  364. i2c_mio12_bus.i2c_handle.config.instance_id = FMIO12_ID;
  365. i2c_mio_init(&i2c_mio12_bus);
  366. #endif
  367. #if defined(RT_USING_MIO13)
  368. i2c_mio13_bus.name = "MIO13";
  369. i2c_mio13_bus.i2c_handle.config.instance_id = FMIO13_ID;
  370. i2c_mio_init(&i2c_mio13_bus);
  371. #endif
  372. #if defined(RT_USING_MIO14)
  373. i2c_mio14_bus.name = "MIO14";
  374. i2c_mio14_bus.i2c_handle.config.instance_id = FMIO14_ID;
  375. i2c_mio_init(&i2c_mio14_bus);
  376. #endif
  377. #if defined(RT_USING_MIO15)
  378. i2c_mio15_bus.name = "MIO15";
  379. i2c_mio15_bus.i2c_handle.config.instance_id = FMIO15_ID;
  380. i2c_mio_init(&i2c_mio15_bus);
  381. #endif
  382. return 0;
  383. }
  384. INIT_DEVICE_EXPORT(rt_hw_i2c_init);