cyhal_timer.c 12 KB

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  1. /***************************************************************************//**
  2. * \file cyhal_timer.c
  3. *
  4. * \brief
  5. * Provides a high level interface for interacting with the Infineon Timer/Counter.
  6. * This interface abstracts out the chip specific details. If any chip specific
  7. * functionality is necessary, or performance is critical the low level functions
  8. * can be used directly.
  9. *
  10. ********************************************************************************
  11. * \copyright
  12. * Copyright 2018-2021 Cypress Semiconductor Corporation (an Infineon company) or
  13. * an affiliate of Cypress Semiconductor Corporation
  14. *
  15. * SPDX-License-Identifier: Apache-2.0
  16. *
  17. * Licensed under the Apache License, Version 2.0 (the "License");
  18. * you may not use this file except in compliance with the License.
  19. * You may obtain a copy of the License at
  20. *
  21. * http://www.apache.org/licenses/LICENSE-2.0
  22. *
  23. * Unless required by applicable law or agreed to in writing, software
  24. * distributed under the License is distributed on an "AS IS" BASIS,
  25. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  26. * See the License for the specific language governing permissions and
  27. * limitations under the License.
  28. *******************************************************************************/
  29. #include <string.h>
  30. #include "cy_device_headers.h"
  31. #include "cyhal_timer_impl.h"
  32. #include "cyhal_hwmgr.h"
  33. #include "cyhal_gpio.h"
  34. #include "cyhal_interconnect.h"
  35. #include "cyhal_syspm.h"
  36. #include "cyhal_clock.h"
  37. #if (CYHAL_DRIVER_AVAILABLE_TIMER)
  38. #if defined(__cplusplus)
  39. extern "C" {
  40. #endif
  41. static const cy_stc_tcpwm_counter_config_t _cyhal_timer_default_config =
  42. {
  43. .period = 32768,
  44. .clockPrescaler = CY_TCPWM_COUNTER_PRESCALER_DIVBY_1,
  45. .runMode = CY_TCPWM_COUNTER_CONTINUOUS,
  46. .countDirection = CY_TCPWM_COUNTER_COUNT_UP,
  47. .compareOrCapture = CY_TCPWM_COUNTER_MODE_CAPTURE,
  48. .compare0 = 16384,
  49. .compare1 = 16384,
  50. .enableCompareSwap = false,
  51. .interruptSources = CY_TCPWM_INT_NONE,
  52. .captureInputMode = 0x3U,
  53. .captureInput = CY_TCPWM_INPUT_0,
  54. .reloadInputMode = 0x3U,
  55. .reloadInput = CY_TCPWM_INPUT_0,
  56. .startInputMode = 0x3U,
  57. .startInput = CY_TCPWM_INPUT_0,
  58. .stopInputMode = 0x3U,
  59. .stopInput = CY_TCPWM_INPUT_0,
  60. .countInputMode = 0x3U,
  61. .countInput = CY_TCPWM_INPUT_1,
  62. };
  63. /** Convert timer direction from the HAL enum to the corresponding PDL constant
  64. *
  65. * @param[in] direction The direction, as a HAL enum value
  66. * @return The direction, as a PDL constant
  67. */
  68. static inline uint32_t _cyhal_timer_convert_direction(cyhal_timer_direction_t direction)
  69. {
  70. switch (direction)
  71. {
  72. case CYHAL_TIMER_DIR_UP:
  73. return CY_TCPWM_COUNTER_COUNT_UP;
  74. case CYHAL_TIMER_DIR_DOWN:
  75. return CY_TCPWM_COUNTER_COUNT_DOWN;
  76. case CYHAL_TIMER_DIR_UP_DOWN:
  77. return CY_TCPWM_COUNTER_COUNT_UP_DOWN_2;
  78. default:
  79. CY_ASSERT(false);
  80. return CY_TCPWM_COUNTER_COUNT_UP;
  81. }
  82. }
  83. /*******************************************************************************
  84. * Timer HAL Functions
  85. *******************************************************************************/
  86. cy_rslt_t _cyhal_timer_init_hw(cyhal_timer_t *obj, const cy_stc_tcpwm_counter_config_t *config, const cyhal_clock_t *clk)
  87. {
  88. cy_rslt_t result = CY_RSLT_SUCCESS;
  89. cyhal_resource_inst_t *timer = &obj->tcpwm.resource;
  90. obj->tcpwm.base = _CYHAL_TCPWM_DATA[_CYHAL_TCPWM_ADJUST_BLOCK_INDEX(timer->block_num)].base;
  91. en_clk_dst_t pclk = (en_clk_dst_t)(_CYHAL_TCPWM_DATA[_CYHAL_TCPWM_ADJUST_BLOCK_INDEX(timer->block_num)].clock_dst + timer->channel_num);
  92. if (NULL != clk)
  93. {
  94. obj->tcpwm.clock = *clk;
  95. obj->tcpwm.clock_hz = cyhal_clock_get_frequency(&obj->tcpwm.clock);
  96. if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock)))
  97. {
  98. result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT;
  99. }
  100. }
  101. else if (CY_RSLT_SUCCESS == (result = _cyhal_utils_allocate_clock(&(obj->tcpwm.clock), timer, CYHAL_CLOCK_BLOCK_PERIPHERAL_16BIT, true)))
  102. {
  103. obj->tcpwm.dedicated_clock = true;
  104. result = cyhal_timer_set_frequency(obj, CYHAL_TIMER_DEFAULT_FREQ);
  105. if (CY_RSLT_SUCCESS == result)
  106. {
  107. if (CY_SYSCLK_SUCCESS != _cyhal_utils_peri_pclk_assign_divider(pclk, &(obj->tcpwm.clock)))
  108. {
  109. result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT;
  110. }
  111. }
  112. }
  113. if (CY_RSLT_SUCCESS == result)
  114. {
  115. result = Cy_TCPWM_Counter_Init(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource), config);
  116. }
  117. if (result == CY_RSLT_SUCCESS)
  118. {
  119. _cyhal_tcpwm_init_data(&obj->tcpwm);
  120. Cy_TCPWM_Counter_Enable(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  121. }
  122. return result;
  123. }
  124. cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clock_t *clk)
  125. {
  126. CY_ASSERT(NULL != obj);
  127. // No support currently for pin connections on this device
  128. if (CYHAL_NC_PIN_VALUE != pin)
  129. return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT;
  130. memset(obj, 0, sizeof(cyhal_timer_t));
  131. obj->tcpwm.resource.type = CYHAL_RSC_INVALID;
  132. cy_rslt_t result = cyhal_hwmgr_allocate(CYHAL_RSC_TCPWM, &obj->tcpwm.resource);
  133. if (CY_RSLT_SUCCESS == result)
  134. {
  135. result = _cyhal_timer_init_hw(obj, &_cyhal_timer_default_config, clk);
  136. }
  137. if (CY_RSLT_SUCCESS != result)
  138. {
  139. cyhal_timer_free(obj);
  140. }
  141. return result;
  142. }
  143. cy_rslt_t cyhal_timer_init_cfg(cyhal_timer_t *obj, const cyhal_timer_configurator_t *cfg)
  144. {
  145. memset(obj, 0, sizeof(cyhal_timer_t));
  146. obj->tcpwm.resource = *cfg->resource;
  147. obj->tcpwm.owned_by_configurator = true;
  148. cy_rslt_t result = _cyhal_timer_init_hw(obj, cfg->config, cfg->clock);
  149. if(CY_RSLT_SUCCESS != result)
  150. {
  151. cyhal_timer_free(obj);
  152. }
  153. return result;
  154. }
  155. cy_rslt_t cyhal_timer_configure(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg)
  156. {
  157. cy_rslt_t rslt;
  158. obj->default_value = cfg->value;
  159. cy_stc_tcpwm_counter_config_t config = _cyhal_timer_default_config;
  160. config.period = cfg->period;
  161. config.compare0 = cfg->compare_value;
  162. config.runMode = cfg->is_continuous ? CY_TCPWM_COUNTER_CONTINUOUS : CY_TCPWM_COUNTER_ONESHOT;
  163. config.compareOrCapture = cfg->is_compare ? CY_TCPWM_COUNTER_MODE_COMPARE : CY_TCPWM_COUNTER_MODE_CAPTURE;
  164. config.countDirection = _cyhal_timer_convert_direction(cfg->direction);
  165. // DeInit will clear the interrupt mask; save it now and restore after we re-nit
  166. uint32_t old_mask = Cy_TCPWM_GetInterruptMask(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  167. Cy_TCPWM_Counter_DeInit(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource), &config);
  168. rslt = (cy_rslt_t)Cy_TCPWM_Counter_Init(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource), &config);
  169. Cy_TCPWM_Counter_Enable(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  170. Cy_TCPWM_SetInterruptMask(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource), old_mask);
  171. // This must be called after Cy_TCPWM_Counter_Init
  172. cyhal_timer_reset(obj);
  173. return rslt;
  174. }
  175. cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz)
  176. {
  177. cy_rslt_t result = CY_RSLT_SUCCESS;
  178. if(!obj->tcpwm.dedicated_clock)
  179. {
  180. result = CYHAL_TIMER_RSLT_ERR_SHARED_CLOCK;
  181. }
  182. const cyhal_clock_tolerance_t tolerance = {
  183. .type = CYHAL_TOLERANCE_PERCENT,
  184. .value = 2,
  185. };
  186. if(CY_RSLT_SUCCESS == result)
  187. {
  188. if((CY_RSLT_SUCCESS == cyhal_clock_set_enabled(&obj->tcpwm.clock, false, false)) &&
  189. (CY_RSLT_SUCCESS == cyhal_clock_set_frequency(&obj->tcpwm.clock, hz, &tolerance)) &&
  190. (CY_RSLT_SUCCESS == cyhal_clock_set_enabled(&obj->tcpwm.clock, true, false)))
  191. {
  192. obj->tcpwm.clock_hz = cyhal_clock_get_frequency(&obj->tcpwm.clock);
  193. }
  194. else
  195. {
  196. result = CYHAL_TIMER_RSLT_ERR_CLOCK_INIT;
  197. }
  198. }
  199. return result;
  200. }
  201. cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj)
  202. {
  203. CY_ASSERT(NULL != obj);
  204. if (_cyhal_tcpwm_pm_transition_pending())
  205. {
  206. return CYHAL_SYSPM_RSLT_ERR_PM_PENDING;
  207. }
  208. Cy_TCPWM_Counter_Enable(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  209. #if defined(CY_IP_MXTCPWM) && (CY_IP_MXTCPWM_VERSION >= 2)
  210. Cy_TCPWM_TriggerStart_Single(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  211. #else
  212. Cy_TCPWM_TriggerStart(obj->tcpwm.base, (1 << _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource)));
  213. #endif
  214. return CY_RSLT_SUCCESS;
  215. }
  216. cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj)
  217. {
  218. CY_ASSERT(NULL != obj);
  219. Cy_TCPWM_Counter_Disable(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  220. return CY_RSLT_SUCCESS;
  221. }
  222. cy_rslt_t cyhal_timer_reset(cyhal_timer_t *obj)
  223. {
  224. CY_ASSERT(NULL != obj);
  225. Cy_TCPWM_Counter_SetCounter(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource), obj->default_value);
  226. return CY_RSLT_SUCCESS;
  227. }
  228. uint32_t cyhal_timer_read(const cyhal_timer_t *obj)
  229. {
  230. CY_ASSERT(NULL != obj);
  231. return Cy_TCPWM_Counter_GetCounter(obj->tcpwm.base, _CYHAL_TCPWM_CNT_NUMBER(obj->tcpwm.resource));
  232. }
  233. static cyhal_tcpwm_input_t _cyhal_timer_translate_input_signal(cyhal_timer_input_t event)
  234. {
  235. switch(event)
  236. {
  237. case CYHAL_TIMER_INPUT_START:
  238. return CYHAL_TCPWM_INPUT_START;
  239. case CYHAL_TIMER_INPUT_STOP:
  240. return CYHAL_TCPWM_INPUT_STOP;
  241. case CYHAL_TIMER_INPUT_RELOAD:
  242. return CYHAL_TCPWM_INPUT_RELOAD;
  243. case CYHAL_TIMER_INPUT_COUNT:
  244. return CYHAL_TCPWM_INPUT_COUNT;
  245. case CYHAL_TIMER_INPUT_CAPTURE:
  246. return CYHAL_TCPWM_INPUT_CAPTURE;
  247. default:
  248. CY_ASSERT(false);
  249. return (cyhal_tcpwm_input_t)0;
  250. }
  251. }
  252. static cyhal_tcpwm_output_t _cyhal_timer_translate_output_signal(cyhal_timer_output_t signal)
  253. {
  254. switch(signal)
  255. {
  256. case CYHAL_TIMER_OUTPUT_OVERFLOW:
  257. return CYHAL_TCPWM_OUTPUT_OVERFLOW;
  258. case CYHAL_TIMER_OUTPUT_UNDERFLOW:
  259. return CYHAL_TCPWM_OUTPUT_UNDERFLOW;
  260. case CYHAL_TIMER_OUTPUT_COMPARE_MATCH:
  261. return CYHAL_TCPWM_OUTPUT_COMPARE_MATCH;
  262. case CYHAL_TIMER_OUTPUT_TERMINAL_COUNT:
  263. return CYHAL_TCPWM_OUTPUT_TERMINAL_COUNT;
  264. default:
  265. CY_ASSERT(false);
  266. return (cyhal_tcpwm_output_t)0;
  267. }
  268. }
  269. cy_rslt_t cyhal_timer_connect_digital2(cyhal_timer_t *obj, cyhal_source_t source, cyhal_timer_input_t signal, cyhal_edge_type_t edge_type)
  270. {
  271. cyhal_tcpwm_input_t tcpwm_signal = _cyhal_timer_translate_input_signal(signal);
  272. return _cyhal_tcpwm_connect_digital(&(obj->tcpwm), source, tcpwm_signal, edge_type);
  273. }
  274. cy_rslt_t cyhal_timer_connect_digital(cyhal_timer_t *obj, cyhal_source_t source, cyhal_timer_input_t signal)
  275. {
  276. #if defined(CY_IP_M0S8PERI_TR) || defined(CY_IP_MXPERI_TR) || defined(CY_IP_MXSPERI)
  277. /* Signal type just tells us edge vs. level, but TCPWM lets you customize which edge you want. So default
  278. * to rising edge. If the application cares about the edge type, it can use connect_digital2 */
  279. cyhal_signal_type_t signal_type = _CYHAL_TRIGGER_GET_SOURCE_TYPE(source);
  280. cyhal_edge_type_t edge_type = (signal_type == CYHAL_SIGNAL_TYPE_LEVEL) ? CYHAL_EDGE_TYPE_LEVEL : CYHAL_EDGE_TYPE_RISING_EDGE;
  281. return cyhal_timer_connect_digital2(obj, source, signal, edge_type);
  282. #else
  283. CY_UNUSED_PARAMETER(obj);
  284. CY_UNUSED_PARAMETER(source);
  285. CY_UNUSED_PARAMETER(signal);
  286. return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT;
  287. #endif
  288. }
  289. cy_rslt_t cyhal_timer_enable_output(cyhal_timer_t *obj, cyhal_timer_output_t signal, cyhal_source_t *source)
  290. {
  291. cyhal_tcpwm_output_t tcpwm_signal = _cyhal_timer_translate_output_signal(signal);
  292. return _cyhal_tcpwm_enable_output(&(obj->tcpwm), tcpwm_signal, source);
  293. }
  294. cy_rslt_t cyhal_timer_disconnect_digital(cyhal_timer_t *obj, cyhal_source_t source, cyhal_timer_input_t signal)
  295. {
  296. return _cyhal_tcpwm_disconnect_digital(&(obj->tcpwm), source, _cyhal_timer_translate_input_signal(signal));
  297. }
  298. cy_rslt_t cyhal_timer_disable_output(cyhal_timer_t *obj, cyhal_timer_output_t signal)
  299. {
  300. return _cyhal_tcpwm_disable_output(&(obj->tcpwm), _cyhal_timer_translate_output_signal(signal));
  301. }
  302. #if defined(__cplusplus)
  303. }
  304. #endif
  305. #endif /* CYHAL_DRIVER_AVAILABLE_TIMER */