drv_adc.c 2.8 KB

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  1. /*
  2. * Copyright (c) 2006-2024, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024/02/22 flyingcys first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include "drv_adc.h"
  13. #ifdef BSP_USING_ADC
  14. #define DBG_LEVEL DBG_LOG
  15. #include <rtdbg.h>
  16. #define LOG_TAG "DRV.ADC"
  17. struct cvi_adc_dev
  18. {
  19. struct rt_adc_device device;
  20. const char *name;
  21. rt_ubase_t base;
  22. };
  23. static struct cvi_adc_dev adc_dev_config[] =
  24. {
  25. {
  26. .name = "adc1",
  27. .base = SARADC_BASE
  28. },
  29. };
  30. static rt_err_t _adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
  31. {
  32. struct cvi_adc_dev *adc_dev = (struct cvi_adc_dev *)device->parent.user_data;
  33. uint32_t value;
  34. RT_ASSERT(adc_dev != RT_NULL);
  35. if (channel > SARADC_CH_MAX)
  36. return -RT_EINVAL;
  37. if (enabled)
  38. {
  39. //set channel
  40. cvi_set_saradc_ctrl(adc_dev->base, (rt_uint32_t)channel << (SARADC_CTRL_SEL_POS + 1));
  41. //set saradc clock cycle
  42. cvi_set_cyc(adc_dev->base);
  43. //start
  44. cvi_set_saradc_ctrl(adc_dev->base, SARADC_CTRL_START);
  45. LOG_D("enable saradc...");
  46. }
  47. else
  48. {
  49. cvi_reset_saradc_ctrl(adc_dev->base, (rt_uint32_t)channel << (SARADC_CTRL_SEL_POS + 1));
  50. LOG_D("disable saradc...");
  51. }
  52. return RT_EOK;
  53. }
  54. static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
  55. {
  56. struct cvi_adc_dev *adc_dev = (struct cvi_adc_dev *)device->parent.user_data;
  57. rt_uint32_t result;
  58. rt_uint32_t cnt = 0;
  59. RT_ASSERT(adc_dev != RT_NULL);
  60. if (channel > SARADC_CH_MAX)
  61. return -RT_EINVAL;
  62. while (cvi_get_saradc_status(adc_dev->base) & SARADC_STATUS_BUSY)
  63. {
  64. rt_thread_delay(10);
  65. LOG_D("wait saradc ready");
  66. cnt ++;
  67. if (cnt > 100)
  68. return -RT_ETIMEOUT;
  69. }
  70. result = mmio_read_32(adc_dev->base + SARADC_RESULT(channel - 1));
  71. if (result & SARADC_RESULT_VALID)
  72. {
  73. *value = result & SARADC_RESULT_MASK;
  74. LOG_D("saradc channel %d value: %04x", channel, *value);
  75. }
  76. else
  77. {
  78. LOG_E("saradc channel %d read failed. result:0x%04x", channel, result);
  79. return -RT_ERROR;
  80. }
  81. return RT_EOK;
  82. }
  83. static const struct rt_adc_ops _adc_ops =
  84. {
  85. .enabled = _adc_enabled,
  86. .convert = _adc_convert,
  87. };
  88. int rt_hw_adc_init(void)
  89. {
  90. rt_uint8_t i;
  91. for (i = 0; i < sizeof(adc_dev_config) / sizeof(adc_dev_config[0]); i ++)
  92. {
  93. if (rt_hw_adc_register(&adc_dev_config[i].device, adc_dev_config[i].name, &_adc_ops, &adc_dev_config[i]) != RT_EOK)
  94. {
  95. LOG_E("%s register failed!", adc_dev_config[i].name);
  96. return -RT_ERROR;
  97. }
  98. }
  99. return RT_EOK;
  100. }
  101. INIT_BOARD_EXPORT(rt_hw_adc_init);
  102. #endif /* BSP_USING_ADC */