H3LIS331DL.h 13 KB

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  1. /*
  2. H3LIS331DL.h
  3. A library for 3-Axis Digital Accelerometer(±400g)
  4. Copyright (c) 2014 seeed technology inc.
  5. Website : www.seeed.cc
  6. Author : lawliet zou
  7. Create Time: April 2014
  8. Change Log :
  9. The MIT License (MIT)
  10. Permission is hereby granted, free of charge, to any person obtaining a copy
  11. of this software and associated documentation files (the "Software"), to deal
  12. in the Software without restriction, including without limitation the rights
  13. to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  14. copies of the Software, and to permit persons to whom the Software is
  15. furnished to do so, subject to the following conditions:
  16. The above copyright notice and this permission notice shall be included in
  17. all copies or substantial portions of the Software.
  18. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  21. AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22. LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23. OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24. THE SOFTWARE.
  25. */
  26. #include "Arduino.h"
  27. #ifndef H3LIS331DL_H
  28. #define H3LIS331DL_H
  29. #define MEMS_SET 0x01
  30. #define MEMS_RESET 0x00
  31. #define H3LIS331DL_MEMS_I2C_ADDRESS 0x18//0x32
  32. //Register and define
  33. #define H3LIS331DL_WHO_AM_I 0x0F // device identification register
  34. // CONTROL REGISTER 1
  35. #define H3LIS331DL_CTRL_REG1 0x20
  36. #define H3LIS331DL_PM BIT(5) //PowerMode selection: 000 - power down / 001 - normal mode / other - low power
  37. #define H3LIS331DL_DR BIT(3) //output data rate: 00 - 50hz / 01 - 100hz / 10 - 400hz / 11 - 1000hz
  38. #define H3LIS331DL_ZEN BIT(2) //Z-axis enable: 0 - disable / 1 - enable
  39. #define H3LIS331DL_YEN BIT(1) //Y-axis enable: 0 - disable / 1 - enable
  40. #define H3LIS331DL_XEN BIT(0) //Y-axis enable: 0 - disable / 1 - enable
  41. //CONTROL REGISTER 2
  42. #define H3LIS331DL_CTRL_REG2 0x21
  43. #define H3LIS331DL_BOOT BIT(7) //reboot memory content, default is 0
  44. #define H3LIS331DL_HPM BIT(5) //High-pass-filter mode selection, default is 00
  45. #define H3LIS331DL_FDS BIT(4) //Filter data selection, default is 0
  46. #define H3LIS331DL_HPEN2 BIT(3) //High-pass filter enabled for interrupt 2 source, default is 0
  47. #define H3LIS331DL_HPEN1 BIT(2) //High-pass filter enabled for interrupt 1 source, default is 0
  48. #define H3LIS331DL_HPCF BIT(0) //High-pass filter cutoff frequency configuration, default is 00
  49. //CONTROL REGISTER 3
  50. #define H3LIS331DL_CTRL_REG3 0x22
  51. #define H3LIS331DL_IHL BIT(7) //Interrupt active high,low. default is 0
  52. #define H3LIS331DL_PP_OD BIT(6) //Push-pull/open drain selection on interrupt pad. default is 0
  53. #define H3LIS331DL_LIR2 BIT(5) //Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by read INT2_SRC itself. default is 0
  54. #define H3LIS331DL_I2_CFG BIT(3) //Data signal on INT2 pad control bits, default is 00
  55. #define H3LIS331DL_LIR1 BIT(2) //Latch interrupt request on the INT1_SRC register, with the INT1_SRC register cleared by reading the INT1_SRC register.
  56. #define H3LIS331DL_I1_CFG BIT(0) //Data signal on INT1 pad control bits, default is 00
  57. //CONTROL REGISTER 4
  58. #define H3LIS331DL_CTRL_REG4 0x23
  59. #define H3LIS331DL_BDU BIT(7) //Block data update, default is 0
  60. #define H3LIS331DL_BLE BIT(6) //Big/little endian data selection, default is 0
  61. #define H3LIS331DL_FS BIT(4) //Full scale selection, default is 00(00:100g;01:200g;11:400g)
  62. #define H3LIS331DL_ST_SIGN BIT(3) //
  63. #define H3LIS331DL_ST BIT(1) //
  64. #define H3LIS331DL_SIM BIT(0) // SPI serial interface mode selection, default is 0
  65. //CONTROL REGISTER 5
  66. #define H3LIS331DL_CTRL_REG5 0x24
  67. #define H3LIS331DL_TURN_ON BIT(0) // Turn-on mode selection selection for sleep to wake function. default is 00
  68. #define H3LIS331DL_HP_FILTER_RESET 0x25 //
  69. //REFERENCE/DATA_CAPTURE
  70. #define H3LIS331DL_REFERENCE_REG 0x26 //
  71. #define H3LIS331DL_REF BIT(0) //
  72. //STATUS_REG_AXIES
  73. #define H3LIS331DL_STATUS_REG 0x27 //
  74. //OUTPUT REGISTER
  75. #define H3LIS331DL_OUT_X_L 0x28 //x-axis acceleration data
  76. #define H3LIS331DL_OUT_X_H 0x29
  77. #define H3LIS331DL_OUT_Y_L 0x2A //y-axis acceleration data
  78. #define H3LIS331DL_OUT_Y_H 0x2B
  79. #define H3LIS331DL_OUT_Z_L 0x2C //z-axis acceleration data
  80. #define H3LIS331DL_OUT_Z_H 0x2D
  81. //INTERRUPT 1 CONFIGURATION
  82. #define H3LIS331DL_INT1_CFG 0x30
  83. //INTERRUPT 2 CONFIGURATION
  84. #define H3LIS331DL_INT2_CFG 0x34
  85. #define H3LIS331DL_ANDOR BIT(7)
  86. #define H3LIS331DL_INT_6D BIT(6)
  87. //INT REGISTERS
  88. #define H3LIS331DL_INT1_THS 0x32
  89. #define H3LIS331DL_INT1_DURATION 0x33
  90. #define H3LIS331DL_INT2_THS 0x36
  91. #define H3LIS331DL_INT2_DURATION 0x37
  92. //INTERRUPT 1 SOURCE REGISTER
  93. #define H3LIS331DL_INT1_SRC 0x31
  94. #define H3LIS331DL_INT2_SRC 0x35
  95. //INT_CFG bit mask
  96. #define H3LIS331DL_INT_AND 0x80
  97. #define H3LIS331DL_INT_OR 0x00
  98. #define H3LIS331DL_INT_ZHIE_ENABLE 0x20
  99. #define H3LIS331DL_INT_ZHIE_DISABLE 0x00
  100. #define H3LIS331DL_INT_ZLIE_ENABLE 0x10
  101. #define H3LIS331DL_INT_ZLIE_DISABLE 0x00
  102. #define H3LIS331DL_INT_YHIE_ENABLE 0x08
  103. #define H3LIS331DL_INT_YHIE_DISABLE 0x00
  104. #define H3LIS331DL_INT_YLIE_ENABLE 0x04
  105. #define H3LIS331DL_INT_YLIE_DISABLE 0x00
  106. #define H3LIS331DL_INT_XHIE_ENABLE 0x02
  107. #define H3LIS331DL_INT_XHIE_DISABLE 0x00
  108. #define H3LIS331DL_INT_XLIE_ENABLE 0x01
  109. #define H3LIS331DL_INT_XLIE_DISABLE 0x00
  110. //INT_SRC bit mask
  111. #define H3LIS331DL_INT_SRC_IA 0x40
  112. #define H3LIS331DL_INT_SRC_ZH 0x20
  113. #define H3LIS331DL_INT_SRC_ZL 0x10
  114. #define H3LIS331DL_INT_SRC_YH 0x08
  115. #define H3LIS331DL_INT_SRC_YL 0x04
  116. #define H3LIS331DL_INT_SRC_XH 0x02
  117. #define H3LIS331DL_INT_SRC_XL 0x01
  118. //STATUS REGISTER bit mask
  119. #define H3LIS331DL_STATUS_REG_ZYXOR 0x80 // 1:new data set has over written the previous one
  120. // 0:no overrun has occurred (default)
  121. #define H3LIS331DL_STATUS_REG_ZOR 0x40 // 0:no overrun has occurred (default)
  122. // 1:new Z-axis data has over written the previous one
  123. #define H3LIS331DL_STATUS_REG_YOR 0x20 // 0:no overrun has occurred (default)
  124. // 1:new Y-axis data has over written the previous one
  125. #define H3LIS331DL_STATUS_REG_XOR 0x10 // 0:no overrun has occurred (default)
  126. // 1:new X-axis data has over written the previous one
  127. #define H3LIS331DL_STATUS_REG_ZYXDA 0x08 // 0:a new set of data is not yet avvious one
  128. // 1:a new set of data is available
  129. #define H3LIS331DL_STATUS_REG_ZDA 0x04 // 0:a new data for the Z-Axis is not availvious one
  130. // 1:a new data for the Z-Axis is available
  131. #define H3LIS331DL_STATUS_REG_YDA 0x02 // 0:a new data for the Y-Axis is not available
  132. // 1:a new data for the Y-Axis is available
  133. #define H3LIS331DL_STATUS_REG_XDA 0x01 // 0:a new data for the X-Axis is not available
  134. // 1:a new data for the X-Axis is available
  135. #define H3LIS331DL_DATAREADY_BIT H3LIS331DL_STATUS_REG_ZYXDA
  136. #define ValBit(VAR,Place) (VAR & (1<<Place))
  137. #define BIT(x) ( (x) )
  138. typedef uint8_t H3LIS331DL_Axis_t;
  139. typedef uint8_t H3LIS331DL_IntConf_t;
  140. //define structure
  141. typedef enum {
  142. MEMS_SUCCESS = 0x01,
  143. MEMS_ERROR = 0x00
  144. } status_t;
  145. typedef enum {
  146. MEMS_ENABLE = 0x01,
  147. MEMS_DISABLE = 0x00
  148. } State_t;
  149. typedef struct {
  150. int16_t AXIS_X;
  151. int16_t AXIS_Y;
  152. int16_t AXIS_Z;
  153. } AxesRaw_t;
  154. typedef enum {
  155. H3LIS331DL_ODR_50Hz = 0x00,
  156. H3LIS331DL_ODR_100Hz = 0x01,
  157. H3LIS331DL_ODR_400Hz = 0x02,
  158. H3LIS331DL_ODR_1000Hz = 0x03
  159. } H3LIS331DL_ODR_t;
  160. typedef enum {
  161. H3LIS331DL_CONTINUOUS_MODE = 0x00,
  162. H3LIS331DL_SINGLE_MODE = 0x01,
  163. H3LIS331DL_SLEEP_MODE = 0x02
  164. } H3LIS331DL_Mode_M_t;
  165. typedef enum {
  166. H3LIS331DL_POWER_DOWN = 0x00,
  167. H3LIS331DL_NORMAL = 0x01,
  168. H3LIS331DL_LOW_POWER_05 = 0x02,
  169. H3LIS331DL_LOW_POWER_1 = 0x03,
  170. H3LIS331DL_LOW_POWER_2 = 0x04,
  171. H3LIS331DL_LOW_POWER_5 = 0x05,
  172. H3LIS331DL_LOW_POWER_10 = 0x06,
  173. } H3LIS331DL_Mode_t;
  174. typedef enum {
  175. H3LIS331DL_HPM_NORMAL_MODE_RES = 0x00,
  176. H3LIS331DL_HPM_REF_SIGNAL = 0x01,
  177. H3LIS331DL_HPM_NORMAL_MODE = 0x02,
  178. } H3LIS331DL_HPFMode_t;
  179. typedef enum {
  180. H3LIS331DL_HPFCF_0 = 0x00,
  181. H3LIS331DL_HPFCF_1 = 0x01,
  182. H3LIS331DL_HPFCF_2 = 0x02,
  183. H3LIS331DL_HPFCF_3 = 0x03,
  184. } H3LIS331DL_HPFCutOffFreq_t;
  185. typedef enum {
  186. H3LIS331DL_INT_SOURCE = 0x00,
  187. H3LIS331DL_INT_1OR2_SOURCE = 0x01,
  188. H3LIS331DL_DATA_READY = 0x02,
  189. H3LIS331DL_BOOT_RUNNING = 0x03
  190. } H3LIS331DL_INT_Conf_t;
  191. typedef enum {
  192. H3LIS331DL_SLEEP_TO_WAKE_DIS = 0x00,
  193. H3LIS331DL_SLEEP_TO_WAKE_ENA = 0x03,
  194. } H3LIS331DL_Sleep_To_Wake_Conf_t;
  195. typedef enum {
  196. H3LIS331DL_FULLSCALE_2 = 0x00,
  197. H3LIS331DL_FULLSCALE_4 = 0x01,
  198. H3LIS331DL_FULLSCALE_8 = 0x03,
  199. } H3LIS331DL_Fullscale_t;
  200. typedef enum {
  201. H3LIS331DL_BLE_LSB = 0x00,
  202. H3LIS331DL_BLE_MSB = 0x01
  203. } H3LIS331DL_Endianess_t;
  204. typedef enum {
  205. H3LIS331DL_SPI_4_WIRE = 0x00,
  206. H3LIS331DL_SPI_3_WIRE = 0x01
  207. } H3LIS331DL_SPIMode_t;
  208. typedef enum {
  209. H3LIS331DL_X_ENABLE = 0x01,
  210. H3LIS331DL_X_DISABLE = 0x00,
  211. H3LIS331DL_Y_ENABLE = 0x02,
  212. H3LIS331DL_Y_DISABLE = 0x00,
  213. H3LIS331DL_Z_ENABLE = 0x04,
  214. H3LIS331DL_Z_DISABLE = 0x00
  215. } H3LIS331DL_AXISenable_t;
  216. typedef enum {
  217. H3LIS331DL_UP_SX = 0x44,
  218. H3LIS331DL_UP_DX = 0x42,
  219. H3LIS331DL_DW_SX = 0x41,
  220. H3LIS331DL_DW_DX = 0x48,
  221. H3LIS331DL_TOP = 0x60,
  222. H3LIS331DL_BOTTOM = 0x50
  223. } H3LIS331DL_POSITION_6D_t;
  224. typedef enum {
  225. H3LIS331DL_INT_MODE_OR = 0x00,
  226. H3LIS331DL_INT_MODE_6D_MOVEMENT = 0x01,
  227. H3LIS331DL_INT_MODE_AND = 0x02,
  228. H3LIS331DL_INT_MODE_6D_POSITION = 0x03
  229. } H3LIS331DL_IntMode_t;
  230. class H3LIS331DL {
  231. public:
  232. H3LIS331DL() {
  233. _adjVal[0] = _adjVal[1] = _adjVal[2] = 0;
  234. };
  235. void init(H3LIS331DL_ODR_t odr = H3LIS331DL_ODR_100Hz,
  236. H3LIS331DL_Mode_t mode = H3LIS331DL_NORMAL, H3LIS331DL_Fullscale_t fullScale = H3LIS331DL_FULLSCALE_2);
  237. void importPara(int16_t val_x, int16_t val_y, int16_t val_z);
  238. void readXYZ(int16_t* x, int16_t* y, int16_t* z);
  239. void getAcceleration(double* xyz);
  240. //Sensor Configuration Functions
  241. status_t getWHO_AM_I(byte* val);
  242. status_t setODR(H3LIS331DL_ODR_t dr);
  243. status_t setMode(H3LIS331DL_Mode_t pm);
  244. status_t setAxis(H3LIS331DL_Axis_t axis);
  245. status_t setFullScale(H3LIS331DL_Fullscale_t fs);
  246. status_t setBDU(State_t bdu);
  247. status_t setBLE(H3LIS331DL_Endianess_t ble);
  248. status_t setSelfTest(State_t st);
  249. status_t setSelfTestSign(State_t st_sign);
  250. status_t turnONEnable(H3LIS331DL_Sleep_To_Wake_Conf_t stw);
  251. status_t setBOOT(State_t boot);
  252. status_t setFDS(State_t fds);
  253. status_t setSPI34Wire(H3LIS331DL_SPIMode_t sim);
  254. //Filtering Functions
  255. status_t setHPFMode(H3LIS331DL_HPFMode_t hpm);
  256. status_t setHPFCutOFF(H3LIS331DL_HPFCutOffFreq_t hpf);
  257. status_t setFilterDataSel(State_t state);
  258. status_t setReference(int8_t ref);
  259. //Interrupt Functions
  260. status_t setIntHighLow(State_t hil);
  261. status_t setIntPPOD(State_t pp_od);
  262. status_t setInt1DataSign(H3LIS331DL_INT_Conf_t i_cfg);
  263. status_t setInt2DataSign(H3LIS331DL_INT_Conf_t i_cfg);
  264. status_t setInt1HPEnable(State_t stat);
  265. status_t setInt2HPEnable(State_t stat);
  266. status_t int1LatchEnable(State_t latch);
  267. status_t int2LatchEnable(State_t latch);
  268. status_t resetInt1Latch(void);
  269. status_t resetInt2Latch(void);
  270. status_t setInt1Configuration(H3LIS331DL_IntConf_t ic);
  271. status_t setInt2Configuration(H3LIS331DL_IntConf_t ic);
  272. status_t setInt1Threshold(byte ths);
  273. status_t setInt2Threshold(byte ths);
  274. status_t setInt1Duration(byte id);
  275. status_t setInt2Duration(byte id);
  276. status_t setInt1Mode(H3LIS331DL_IntMode_t int_mode);
  277. status_t setInt2Mode(H3LIS331DL_IntMode_t int_mode);
  278. status_t getInt1Src(byte* val);
  279. status_t getInt2Src(byte* val);
  280. status_t getInt1SrcBit(byte statusBIT, byte* val);
  281. status_t getInt2SrcBit(byte statusBIT, byte* val);
  282. //Other Reading Functions
  283. status_t getStatusReg(byte* val);
  284. status_t getStatusBit(byte statusBIT, byte* val);
  285. status_t getAccAxesRaw(AxesRaw_t* buff);
  286. status_t get6DPositionInt1(byte* val);
  287. status_t get6DPositionInt2(byte* val);
  288. private:
  289. uint8_t readReg(byte deviceAddr, byte Reg, byte* Data);
  290. uint8_t writeReg(byte deviceAddress, byte WriteAddr, byte Data);
  291. int16_t _adjVal[3];
  292. };
  293. #endif /*__H3LIS331DL_H */