[bsp] Add MB9BF618 porting.

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610s.h

@@ -0,0 +1,29269 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/*                                                                      */
+/*  Header File for Device MB9BF618S                                    */
+/*  Version V1.00                                                       */
+/*  Date    2011-08-04                                                  */
+/*                                                                      */
+/************************************************************************/
+
+#ifndef _MB9BF618S_H_
+#define _MB9BF618S_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/******************************************************************************
+ * Configuration of the Cortex-M3 Processor and Core Peripherals
+ ******************************************************************************/
+#define __MPU_PRESENT           1 /* FM3 provide an MPU                           */
+#define __NVIC_PRIO_BITS        4 /* FM3 uses 4 Bits for the Priority Levels      */
+#define __Vendor_SysTickConfig  0 /* Set to 1 if different SysTick Config is used */
+
+
+/******************************************************************************
+ * Interrupt Number Definition
+ ******************************************************************************/
+typedef enum IRQn
+{
+    NMI_IRQn          = -14, /*  2 Non Maskable      */
+    HardFault_IRQn    = -13, /*  3 Hard Fault        */
+    MemManage_IRQn    = -12, /*  4 Memory Management */
+    BusFault_IRQn     = -11, /*  5 Bus Fault         */
+    UsageFault_IRQn   = -10, /*  6 Usage Fault       */
+    SVC_IRQn          = -5,  /* 11 SV Call           */
+    DebugMonitor_IRQn = -4,  /* 12 Debug Monitor     */
+    PendSV_IRQn       = -2,  /* 14 Pend SV           */
+    SysTick_IRQn      = -1,  /* 15 System Tick       */
+
+    CSV_IRQn          =  0, /* Clock Super Visor                             */
+    SWDT_IRQn         =  1, /* Software Watchdog Timer                       */
+    LVD_IRQn          =  2, /* Low Voltage Detector                          */
+    WFG_IRQn          =  3, /* Wave Form Generator                           */
+    EXINT0_7_IRQn     =  4, /* External Interrupt Request ch.0 to ch.7       */
+    EXINT8_31_IRQn    =  5, /* External Interrupt Request ch.8 to ch.31      */
+    DTIM_QDU_IRQn     =  6, /* Dual Timer / Quad Decoder                     */
+    MFS0RX_IRQn       =  7, /* MultiFunction Serial Reception ch.0           */
+    MFS0TX_IRQn       =  8, /* MultiFunction Serial Transmission ch.0        */
+    MFS1RX_IRQn       =  9, /* MultiFunction Serial Reception ch.1           */
+    MFS1TX_IRQn       = 10, /* MultiFunction Serial Transmission ch.1        */
+    MFS2RX_IRQn       = 11, /* MultiFunction Serial Reception ch.2           */
+    MFS2TX_IRQn       = 12, /* MultiFunction Serial Transmission ch.2        */
+    MFS3RX_IRQn       = 13, /* MultiFunction Serial Reception ch.3           */
+    MFS3TX_IRQn       = 14, /* MultiFunction Serial Transmission ch.3        */
+    MFS4RX_IRQn       = 15, /* MultiFunction Serial Reception ch.4           */
+    MFS4TX_IRQn       = 16, /* MultiFunction Serial Transmission ch.4        */
+    MFS5RX_IRQn       = 17, /* MultiFunction Serial Reception ch.5           */
+    MFS5TX_IRQn       = 18, /* MultiFunction Serial Transmission ch.5        */
+    MFS6RX_IRQn       = 19, /* MultiFunction Serial Reception ch.6           */
+    MFS6TX_IRQn       = 20, /* MultiFunction Serial Transmission ch.6        */
+    MFS7RX_IRQn       = 21, /* MultiFunction Serial Reception ch.7           */
+    MFS7TX_IRQn       = 22, /* MultiFunction Serial Transmission ch.7        */
+    PPG_IRQn          = 23, /* PPG                                           */
+    OSC_PLL_WC_IRQn   = 24, /* OSC / PLL / Watch Counter                     */
+    ADC0_IRQn         = 25, /* ADC0                                          */
+    ADC1_IRQn         = 26, /* ADC1                                          */
+    ADC2_IRQn         = 27, /* ADC2                                          */
+    FRTIM_IRQn        = 28, /* Free-run Timer                                */
+    INCAP_IRQn        = 29, /* Input Capture                                 */
+    OUTCOMP_IRQn      = 30, /* Output Compare                                */
+    BTIM0_7_IRQn      = 31, /* Base Timer ch.0 to ch.7                       */
+    ETHER_MAC0_IRQn   = 32, /* Ethernet MAC ch.0                             */
+    ETHER_MAC1_IRQn   = 33, /* Ethernet MAC ch.1                             */
+    USB0F_IRQn        = 34, /* USB Function ch.0                             */
+    USB0F_USB0H_IRQn  = 35, /* USB Function ch.0 / USB Host ch.0             */
+    USB1F_IRQn        = 36, /* USB Function ch.1                             */
+    USB1F_USB1H_IRQn  = 37, /* USB Function ch.1 / USB Host ch.1             */
+    DMAC0_IRQn        = 38, /* DMAC ch.0                                     */
+    DMAC1_IRQn        = 39, /* DMAC ch.1                                     */
+    DMAC2_IRQn        = 40, /* DMAC ch.2                                     */
+    DMAC3_IRQn        = 41, /* DMAC ch.3                                     */
+    DMAC4_IRQn        = 42, /* DMAC ch.4                                     */
+    DMAC5_IRQn        = 43, /* DMAC ch.5                                     */
+    DMAC6_IRQn        = 44, /* DMAC ch.6                                     */
+    DMAC7_IRQn        = 45, /* DMAC ch.7                                     */
+    BTIM8_15_IRQn     = 46  /* Base Timer ch.8 to ch.15                      */
+    /* Reserved       = 47                                                   */
+} IRQn_Type;
+
+
+#include <core_cm3.h>
+#include "system_mb9bf61x.h"
+#include <stdint.h>
+
+#define SUCCESS  0
+#define ERROR    -1
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/******************************************************************************
+ * Peripheral register bit fields
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash_IF_MODULE register bit fields */
+typedef struct stc_flash_if_faszr_field
+{
+  __IO uint32_t ASZ0       : 1;
+  __IO uint32_t ASZ1       : 1;
+} stc_flash_if_faszr_field_t;
+
+typedef struct stc_flash_if_frwtr_field
+{
+  __IO uint32_t RWT0       : 1;
+  __IO uint32_t RWT1       : 1;
+} stc_flash_if_frwtr_field_t;
+
+typedef struct stc_flash_if_fstr_field
+{
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t HNG        : 1;
+  __IO uint32_t EER        : 1;
+} stc_flash_if_fstr_field_t;
+
+typedef struct stc_flash_if_fsyndn_field
+{
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+} stc_flash_if_fsyndn_field_t;
+
+typedef struct stc_flash_if_crtrmm_field
+{
+  __IO uint32_t TRMM0      : 1;
+  __IO uint32_t TRMM1      : 1;
+  __IO uint32_t TRMM2      : 1;
+  __IO uint32_t TRMM3      : 1;
+  __IO uint32_t TRMM4      : 1;
+  __IO uint32_t TRMM5      : 1;
+  __IO uint32_t TRMM6      : 1;
+  __IO uint32_t TRMM7      : 1;
+  __IO uint32_t TRMM8      : 1;
+  __IO uint32_t TRMM9      : 1;
+} stc_flash_if_crtrmm_field_t;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock_Reset_MODULE register bit fields */
+typedef struct stc_crg_scm_ctl_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MOSCE      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SOSCE      : 1;
+  __IO  uint8_t PLLE       : 1;
+  __IO  uint8_t RCS0       : 1;
+  __IO  uint8_t RCS1       : 1;
+  __IO  uint8_t RCS2       : 1;
+} stc_crg_scm_ctl_field_t;
+
+typedef struct stc_crg_scm_str_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MORDY      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SORDY      : 1;
+  __IO  uint8_t PLRDY      : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t RCM2       : 1;
+} stc_crg_scm_str_field_t;
+
+typedef struct stc_crg_rst_str_field
+{
+  __IO uint16_t PONR       : 1;
+  __IO uint16_t INITX      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SWDT       : 1;
+  __IO uint16_t HWDT       : 1;
+  __IO uint16_t CSVR       : 1;
+  __IO uint16_t FCSR       : 1;
+  __IO uint16_t SRST       : 1;
+} stc_crg_rst_str_field_t;
+
+typedef struct stc_crg_bsc_psr_field
+{
+  __IO  uint8_t BSR0       : 1;
+  __IO  uint8_t BSR1       : 1;
+  __IO  uint8_t BSR2       : 1;
+} stc_crg_bsc_psr_field_t;
+
+typedef struct stc_crg_apbc0_psr_field
+{
+  __IO  uint8_t APBC00     : 1;
+  __IO  uint8_t APBC01     : 1;
+} stc_crg_apbc0_psr_field_t;
+
+typedef struct stc_crg_apbc1_psr_field
+{
+  __IO  uint8_t APBC10     : 1;
+  __IO  uint8_t APBC11     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC1RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC1EN    : 1;
+} stc_crg_apbc1_psr_field_t;
+
+typedef struct stc_crg_apbc2_psr_field
+{
+  __IO  uint8_t APBC20     : 1;
+  __IO  uint8_t APBC21     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC2RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC2EN    : 1;
+} stc_crg_apbc2_psr_field_t;
+
+typedef struct stc_crg_swc_psr_field
+{
+  __IO  uint8_t SWDS0      : 1;
+  __IO  uint8_t SWDS1      : 1;
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t TESTB      : 1;
+} stc_crg_swc_psr_field_t;
+
+typedef struct stc_crg_ttc_psr_field
+{
+  __IO  uint8_t TTC0       : 1;
+  __IO  uint8_t TTC1       : 1;
+} stc_crg_ttc_psr_field_t;
+
+typedef struct stc_crg_csw_tmr_field
+{
+  __IO  uint8_t MOWT0      : 1;
+  __IO  uint8_t MOWT1      : 1;
+  __IO  uint8_t MOWT2      : 1;
+  __IO  uint8_t MOWT3      : 1;
+  __IO  uint8_t SOWT0      : 1;
+  __IO  uint8_t SOWT1      : 1;
+  __IO  uint8_t SOWT2      : 1;
+} stc_crg_csw_tmr_field_t;
+
+typedef struct stc_crg_psw_tmr_field
+{
+  __IO  uint8_t POWT0      : 1;
+  __IO  uint8_t POWT1      : 1;
+  __IO  uint8_t POWT2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t PINC       : 1;
+} stc_crg_psw_tmr_field_t;
+
+typedef struct stc_crg_pll_ctl1_field
+{
+  __IO  uint8_t PLLM0      : 1;
+  __IO  uint8_t PLLM1      : 1;
+  __IO  uint8_t PLLM2      : 1;
+  __IO  uint8_t PLLM3      : 1;
+  __IO  uint8_t PLLK0      : 1;
+  __IO  uint8_t PLLK1      : 1;
+  __IO  uint8_t PLLK2      : 1;
+  __IO  uint8_t PLLK3      : 1;
+} stc_crg_pll_ctl1_field_t;
+
+typedef struct stc_crg_pll_ctl2_field
+{
+  __IO  uint8_t PLLN0      : 1;
+  __IO  uint8_t PLLN1      : 1;
+  __IO  uint8_t PLLN2      : 1;
+  __IO  uint8_t PLLN3      : 1;
+  __IO  uint8_t PLLN4      : 1;
+  __IO  uint8_t PLLN5      : 1;
+} stc_crg_pll_ctl2_field_t;
+
+typedef struct stc_crg_csv_ctl_field
+{
+  __IO uint16_t MCSVE      : 1;
+  __IO uint16_t SCSVE      : 1;
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t FCSDE      : 1;
+  __IO uint16_t FCSRE      : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t FCD0       : 1;
+  __IO uint16_t FCD1       : 1;
+  __IO uint16_t FCD2       : 1;
+} stc_crg_csv_ctl_field_t;
+
+typedef struct stc_crg_csv_str_field
+{
+  __IO  uint8_t MCMF       : 1;
+  __IO  uint8_t SCMF       : 1;
+} stc_crg_csv_str_field_t;
+
+typedef struct stc_crg_dbwdt_ctl_field
+{
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t DPSWBE     : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t DPHWBE     : 1;
+} stc_crg_dbwdt_ctl_field_t;
+
+typedef struct stc_crg_int_enr_field
+{
+  __IO  uint8_t MCSE       : 1;
+  __IO  uint8_t SCSE       : 1;
+  __IO  uint8_t PCSE       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSE       : 1;
+} stc_crg_int_enr_field_t;
+
+typedef struct stc_crg_int_str_field
+{
+  __IO  uint8_t MCSI       : 1;
+  __IO  uint8_t SCSI       : 1;
+  __IO  uint8_t PCSI       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSI       : 1;
+} stc_crg_int_str_field_t;
+
+typedef struct stc_crg_int_clr_field
+{
+  __IO  uint8_t MCSC       : 1;
+  __IO  uint8_t SCSC       : 1;
+  __IO  uint8_t PCSC       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSC       : 1;
+} stc_crg_int_clr_field_t;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* HWWDT_MODULE register bit fields */
+typedef struct stc_hwwdt_wdg_ctl_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_hwwdt_wdg_ctl_field_t;
+
+typedef struct stc_hwwdt_wdg_ris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_hwwdt_wdg_ris_field_t;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* SWWDT_MODULE register bit fields */
+typedef struct stc_swwdt_wdogcontrol_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_swwdt_wdogcontrol_field_t;
+
+typedef struct stc_swwdt_wdogris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_swwdt_wdogris_field_t;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* DTIM_MODULE register bit fields */
+typedef struct stc_dtim_timer1control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer1control_field_t;
+
+typedef struct stc_dtim_timer1ris_field
+{
+  __IO uint32_t TIMER1RIS  : 1;
+} stc_dtim_timer1ris_field_t;
+
+typedef struct stc_dtim_timer1mis_field
+{
+  __IO uint32_t TIMER1MIS  : 1;
+} stc_dtim_timer1mis_field_t;
+
+typedef struct stc_dtim_timer2control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer2control_field_t;
+
+typedef struct stc_dtim_timer2ris_field
+{
+  __IO uint32_t TIMER2RIS  : 1;
+} stc_dtim_timer2ris_field_t;
+
+typedef struct stc_dtim_timer2mis_field
+{
+  __IO uint32_t TIMER2MIS  : 1;
+} stc_dtim_timer2mis_field_t;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* MFT_FRT_MODULE register bit fields */
+typedef struct stc_mft_frt_tcsa0_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa0_field_t;
+
+typedef struct stc_mft_frt_tcsb0_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb0_field_t;
+
+typedef struct stc_mft_frt_tcsa1_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa1_field_t;
+
+typedef struct stc_mft_frt_tcsb1_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb1_field_t;
+
+typedef struct stc_mft_frt_tcsa2_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa2_field_t;
+
+typedef struct stc_mft_frt_tcsb2_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb2_field_t;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* MFT_OCU_MODULE register bit fields */
+typedef struct stc_mft_ocu_ocsa10_field
+{
+  __IO  uint8_t CST0       : 1;
+  __IO  uint8_t CST1       : 1;
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t IOE0       : 1;
+  __IO  uint8_t IOE1       : 1;
+  __IO  uint8_t IOP0       : 1;
+  __IO  uint8_t IOP1       : 1;
+} stc_mft_ocu_ocsa10_field_t;
+
+typedef struct stc_mft_ocu_ocsb10_field
+{
+  __IO  uint8_t OTD0       : 1;
+  __IO  uint8_t OTD1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+} stc_mft_ocu_ocsb10_field_t;
+
+typedef struct stc_mft_ocu_ocsa32_field
+{
+  __IO  uint8_t CST2       : 1;
+  __IO  uint8_t CST3       : 1;
+  __IO  uint8_t BDIS2      : 1;
+  __IO  uint8_t BDIS3      : 1;
+  __IO  uint8_t IOE2       : 1;
+  __IO  uint8_t IOE3       : 1;
+  __IO  uint8_t IOP2       : 1;
+  __IO  uint8_t IOP3       : 1;
+} stc_mft_ocu_ocsa32_field_t;
+
+typedef struct stc_mft_ocu_ocsb32_field
+{
+  __IO  uint8_t OTD2       : 1;
+  __IO  uint8_t OTD3       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS2       : 1;
+  __IO  uint8_t BTS3       : 1;
+} stc_mft_ocu_ocsb32_field_t;
+
+typedef struct stc_mft_ocu_ocsa54_field
+{
+  __IO  uint8_t CST4       : 1;
+  __IO  uint8_t CST5       : 1;
+  __IO  uint8_t BDIS4      : 1;
+  __IO  uint8_t BDIS5      : 1;
+  __IO  uint8_t IOE4       : 1;
+  __IO  uint8_t IOE5       : 1;
+  __IO  uint8_t IOP4       : 1;
+  __IO  uint8_t IOP5       : 1;
+} stc_mft_ocu_ocsa54_field_t;
+
+typedef struct stc_mft_ocu_ocsb54_field
+{
+  __IO  uint8_t OTD4       : 1;
+  __IO  uint8_t OTD5       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS4       : 1;
+  __IO  uint8_t BTS5       : 1;
+} stc_mft_ocu_ocsb54_field_t;
+
+typedef struct stc_mft_ocu_ocsc_field
+{
+  __IO  uint8_t MOD0       : 1;
+  __IO  uint8_t MOD1       : 1;
+  __IO  uint8_t MOD2       : 1;
+  __IO  uint8_t MOD3       : 1;
+  __IO  uint8_t MOD4       : 1;
+  __IO  uint8_t MOD5       : 1;
+} stc_mft_ocu_ocsc_field_t;
+
+typedef struct stc_mft_ocu_ocfs10_field
+{
+  __IO  uint8_t FSO00      : 1;
+  __IO  uint8_t FSO01      : 1;
+  __IO  uint8_t FSO02      : 1;
+  __IO  uint8_t FSO03      : 1;
+  __IO  uint8_t FSO10      : 1;
+  __IO  uint8_t FSO11      : 1;
+  __IO  uint8_t FSO12      : 1;
+  __IO  uint8_t FSO13      : 1;
+} stc_mft_ocu_ocfs10_field_t;
+
+typedef struct stc_mft_ocu_ocfs32_field
+{
+  __IO  uint8_t FSO20      : 1;
+  __IO  uint8_t FSO21      : 1;
+  __IO  uint8_t FSO22      : 1;
+  __IO  uint8_t FSO23      : 1;
+  __IO  uint8_t FSO30      : 1;
+  __IO  uint8_t FSO31      : 1;
+  __IO  uint8_t FSO32      : 1;
+  __IO  uint8_t FSO33      : 1;
+} stc_mft_ocu_ocfs32_field_t;
+
+typedef struct stc_mft_ocu_ocfs54_field
+{
+  __IO  uint8_t FSO40      : 1;
+  __IO  uint8_t FSO41      : 1;
+  __IO  uint8_t FSO42      : 1;
+  __IO  uint8_t FSO43      : 1;
+  __IO  uint8_t FSO50      : 1;
+  __IO  uint8_t FSO51      : 1;
+  __IO  uint8_t FSO52      : 1;
+  __IO  uint8_t FSO53      : 1;
+} stc_mft_ocu_ocfs54_field_t;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* MFT_WFG_MODULE register bit fields */
+typedef struct stc_mft_wfg_wfsa10_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD0       : 1;
+  __IO uint16_t TMD1       : 1;
+  __IO uint16_t TMD2       : 1;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa10_field_t;
+
+typedef struct stc_mft_wfg_wfsa32_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD0       : 1;
+  __IO uint16_t TMD1       : 1;
+  __IO uint16_t TMD2       : 1;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa32_field_t;
+
+typedef struct stc_mft_wfg_wfsa54_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD0       : 1;
+  __IO uint16_t TMD1       : 1;
+  __IO uint16_t TMD2       : 1;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa54_field_t;
+
+typedef struct stc_mft_wfg_wfir_field
+{
+  __IO uint16_t DTIF       : 1;
+  __IO uint16_t DTIC       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t TMIF10     : 1;
+  __IO uint16_t TMIC10     : 1;
+  __IO uint16_t TMIE10     : 1;
+  __IO uint16_t TMIS10     : 1;
+  __IO uint16_t TMIF32     : 1;
+  __IO uint16_t TMIC32     : 1;
+  __IO uint16_t TMIE32     : 1;
+  __IO uint16_t TMIS32     : 1;
+  __IO uint16_t TMIF54     : 1;
+  __IO uint16_t TMIC54     : 1;
+  __IO uint16_t TMIE54     : 1;
+  __IO uint16_t TMIS54     : 1;
+} stc_mft_wfg_wfir_field_t;
+
+typedef struct stc_mft_wfg_nzcl_field
+{
+  __IO uint16_t DTIE       : 1;
+  __IO uint16_t NWS0       : 1;
+  __IO uint16_t NWS1       : 1;
+  __IO uint16_t NWS2       : 1;
+  __IO uint16_t SDTI       : 1;
+} stc_mft_wfg_nzcl_field_t;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* MFT_ICU_MODULE register bit fields */
+typedef struct stc_mft_icu_icfs10_field
+{
+  __IO  uint8_t FSI00      : 1;
+  __IO  uint8_t FSI01      : 1;
+  __IO  uint8_t FSI02      : 1;
+  __IO  uint8_t FSI03      : 1;
+  __IO  uint8_t FSI10      : 1;
+  __IO  uint8_t FSI11      : 1;
+  __IO  uint8_t FSI12      : 1;
+  __IO  uint8_t FSI13      : 1;
+} stc_mft_icu_icfs10_field_t;
+
+typedef struct stc_mft_icu_icfs32_field
+{
+  __IO  uint8_t FSI20      : 1;
+  __IO  uint8_t FSI21      : 1;
+  __IO  uint8_t FSI22      : 1;
+  __IO  uint8_t FSI23      : 1;
+  __IO  uint8_t FSI30      : 1;
+  __IO  uint8_t FSI31      : 1;
+  __IO  uint8_t FSI32      : 1;
+  __IO  uint8_t FSI33      : 1;
+} stc_mft_icu_icfs32_field_t;
+
+typedef struct stc_mft_icu_icsa10_field
+{
+  __IO  uint8_t EG00       : 1;
+  __IO  uint8_t EG01       : 1;
+  __IO  uint8_t EG10       : 1;
+  __IO  uint8_t EG11       : 1;
+  __IO  uint8_t ICE0       : 1;
+  __IO  uint8_t ICE1       : 1;
+  __IO  uint8_t ICP0       : 1;
+  __IO  uint8_t ICP1       : 1;
+} stc_mft_icu_icsa10_field_t;
+
+typedef struct stc_mft_icu_icsb10_field
+{
+  __IO  uint8_t IEI0       : 1;
+  __IO  uint8_t IEI1       : 1;
+} stc_mft_icu_icsb10_field_t;
+
+typedef struct stc_mft_icu_icsa32_field
+{
+  __IO  uint8_t EG20       : 1;
+  __IO  uint8_t EG21       : 1;
+  __IO  uint8_t EG30       : 1;
+  __IO  uint8_t EG31       : 1;
+  __IO  uint8_t ICE2       : 1;
+  __IO  uint8_t ICE3       : 1;
+  __IO  uint8_t ICP2       : 1;
+  __IO  uint8_t ICP3       : 1;
+} stc_mft_icu_icsa32_field_t;
+
+typedef struct stc_mft_icu_icsb32_field
+{
+  __IO  uint8_t IEI2       : 1;
+  __IO  uint8_t IEI3       : 1;
+} stc_mft_icu_icsb32_field_t;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* MFT_ADCMP_MODULE register bit fields */
+typedef struct stc_mft_adcmp_acsb_field
+{
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t BDIS2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+  __IO  uint8_t BTS2       : 1;
+} stc_mft_adcmp_acsb_field_t;
+
+typedef struct stc_mft_adcmp_acsa_field
+{
+  __IO uint16_t CE00       : 1;
+  __IO uint16_t CE01       : 1;
+  __IO uint16_t CE10       : 1;
+  __IO uint16_t CE11       : 1;
+  __IO uint16_t CE20       : 1;
+  __IO uint16_t CE21       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SEL00      : 1;
+  __IO uint16_t SEL01      : 1;
+  __IO uint16_t SEL10      : 1;
+  __IO uint16_t SEL11      : 1;
+  __IO uint16_t SEL20      : 1;
+  __IO uint16_t SEL21      : 1;
+} stc_mft_adcmp_acsa_field_t;
+
+typedef struct stc_mft_adcmp_atsa_field
+{
+  __IO uint16_t AD0S0      : 1;
+  __IO uint16_t AD0S1      : 1;
+  __IO uint16_t AD1S0      : 1;
+  __IO uint16_t AD1S1      : 1;
+  __IO uint16_t AD2S0      : 1;
+  __IO uint16_t AD2S1      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t AD0P0      : 1;
+  __IO uint16_t AD0P1      : 1;
+  __IO uint16_t AD1P0      : 1;
+  __IO uint16_t AD1P1      : 1;
+  __IO uint16_t AD2P0      : 1;
+  __IO uint16_t AD2P1      : 1;
+} stc_mft_adcmp_atsa_field_t;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* MFT_PPG_MODULE register bit fields */
+typedef struct stc_mft_ppg_ttcr0_field
+{
+  __IO  uint8_t STR0       : 1;
+  __IO  uint8_t MONI0      : 1;
+  __IO  uint8_t CS00       : 1;
+  __IO  uint8_t CS01       : 1;
+  __IO  uint8_t TRG0O      : 1;
+  __IO  uint8_t TRG2O      : 1;
+  __IO  uint8_t TRG4O      : 1;
+  __IO  uint8_t TRG6O      : 1;
+} stc_mft_ppg_ttcr0_field_t;
+
+typedef struct stc_mft_ppg_ttcr1_field
+{
+  __IO  uint8_t STR1       : 1;
+  __IO  uint8_t MONI1      : 1;
+  __IO  uint8_t CS10       : 1;
+  __IO  uint8_t CS11       : 1;
+  __IO  uint8_t TRG1O      : 1;
+  __IO  uint8_t TRG3O      : 1;
+  __IO  uint8_t TRG5O      : 1;
+  __IO  uint8_t TRG7O      : 1;
+} stc_mft_ppg_ttcr1_field_t;
+
+typedef struct stc_mft_ppg_ttcr2_field
+{
+  __IO  uint8_t STR2       : 1;
+  __IO  uint8_t MONI2      : 1;
+  __IO  uint8_t CS20       : 1;
+  __IO  uint8_t CS21       : 1;
+  __IO  uint8_t TRG16O     : 1;
+  __IO  uint8_t TRG18O     : 1;
+  __IO  uint8_t TRG20O     : 1;
+  __IO  uint8_t TRG22O     : 1;
+} stc_mft_ppg_ttcr2_field_t;
+
+typedef struct stc_mft_ppg_trg_field
+{
+  __IO uint16_t PEN00      : 1;
+  __IO uint16_t PEN01      : 1;
+  __IO uint16_t PEN02      : 1;
+  __IO uint16_t PEN03      : 1;
+  __IO uint16_t PEN04      : 1;
+  __IO uint16_t PEN05      : 1;
+  __IO uint16_t PEN06      : 1;
+  __IO uint16_t PEN07      : 1;
+  __IO uint16_t PEN08      : 1;
+  __IO uint16_t PEN09      : 1;
+  __IO uint16_t PEN10      : 1;
+  __IO uint16_t PEN11      : 1;
+  __IO uint16_t PEN12      : 1;
+  __IO uint16_t PEN13      : 1;
+  __IO uint16_t PEN14      : 1;
+  __IO uint16_t PEN15      : 1;
+} stc_mft_ppg_trg_field_t;
+
+typedef struct stc_mft_ppg_trg1_field
+{
+  __IO uint16_t PEN16      : 1;
+  __IO uint16_t PEN17      : 1;
+  __IO uint16_t PEN18      : 1;
+  __IO uint16_t PEN19      : 1;
+  __IO uint16_t PEN20      : 1;
+  __IO uint16_t PEN21      : 1;
+  __IO uint16_t PEN22      : 1;
+  __IO uint16_t PEN23      : 1;
+} stc_mft_ppg_trg1_field_t;
+
+typedef struct stc_mft_ppg_revc_field
+{
+  __IO uint16_t REV00      : 1;
+  __IO uint16_t REV01      : 1;
+  __IO uint16_t REV02      : 1;
+  __IO uint16_t REV03      : 1;
+  __IO uint16_t REV04      : 1;
+  __IO uint16_t REV05      : 1;
+  __IO uint16_t REV06      : 1;
+  __IO uint16_t REV07      : 1;
+  __IO uint16_t REV08      : 1;
+  __IO uint16_t REV09      : 1;
+  __IO uint16_t REV10      : 1;
+  __IO uint16_t REV11      : 1;
+  __IO uint16_t REV12      : 1;
+  __IO uint16_t REV13      : 1;
+  __IO uint16_t REV14      : 1;
+  __IO uint16_t REV15      : 1;
+} stc_mft_ppg_revc_field_t;
+
+typedef struct stc_mft_ppg_revc1_field
+{
+  __IO uint16_t REV16      : 1;
+  __IO uint16_t REV17      : 1;
+  __IO uint16_t REV18      : 1;
+  __IO uint16_t REV19      : 1;
+  __IO uint16_t REV20      : 1;
+  __IO uint16_t REV21      : 1;
+  __IO uint16_t REV22      : 1;
+  __IO uint16_t REV23      : 1;
+} stc_mft_ppg_revc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc1_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc0_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc0_field_t;
+
+typedef struct stc_mft_ppg_ppgc3_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc3_field_t;
+
+typedef struct stc_mft_ppg_ppgc2_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc2_field_t;
+
+typedef struct stc_mft_ppg_gatec0_field
+{
+  __IO  uint8_t EDGE0      : 1;
+  __IO  uint8_t STRG0      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE2      : 1;
+  __IO  uint8_t STRG2      : 1;
+} stc_mft_ppg_gatec0_field_t;
+
+typedef struct stc_mft_ppg_ppgc5_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc5_field_t;
+
+typedef struct stc_mft_ppg_ppgc4_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc4_field_t;
+
+typedef struct stc_mft_ppg_ppgc7_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc7_field_t;
+
+typedef struct stc_mft_ppg_ppgc6_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc6_field_t;
+
+typedef struct stc_mft_ppg_gatec4_field
+{
+  __IO  uint8_t EDGE4      : 1;
+  __IO  uint8_t STRG4      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE6      : 1;
+  __IO  uint8_t STRG6      : 1;
+} stc_mft_ppg_gatec4_field_t;
+
+typedef struct stc_mft_ppg_ppgc9_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc9_field_t;
+
+typedef struct stc_mft_ppg_ppgc8_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc8_field_t;
+
+typedef struct stc_mft_ppg_ppgc11_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc11_field_t;
+
+typedef struct stc_mft_ppg_ppgc10_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc10_field_t;
+
+typedef struct stc_mft_ppg_gatec8_field
+{
+  __IO  uint8_t EDGE8      : 1;
+  __IO  uint8_t STRG8      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE10     : 1;
+  __IO  uint8_t STRG10     : 1;
+} stc_mft_ppg_gatec8_field_t;
+
+typedef struct stc_mft_ppg_ppgc13_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc13_field_t;
+
+typedef struct stc_mft_ppg_ppgc12_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc12_field_t;
+
+typedef struct stc_mft_ppg_ppgc15_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc15_field_t;
+
+typedef struct stc_mft_ppg_ppgc14_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc14_field_t;
+
+typedef struct stc_mft_ppg_gatec12_field
+{
+  __IO  uint8_t EDGE12     : 1;
+  __IO  uint8_t STRG12     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE14     : 1;
+  __IO  uint8_t STRG14     : 1;
+} stc_mft_ppg_gatec12_field_t;
+
+typedef struct stc_mft_ppg_ppgc17_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc17_field_t;
+
+typedef struct stc_mft_ppg_ppgc16_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc16_field_t;
+
+typedef struct stc_mft_ppg_ppgc19_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc19_field_t;
+
+typedef struct stc_mft_ppg_ppgc18_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc18_field_t;
+
+typedef struct stc_mft_ppg_gatec16_field
+{
+  __IO  uint8_t EDGE16     : 1;
+  __IO  uint8_t STRG16     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE18     : 1;
+  __IO  uint8_t STRG18     : 1;
+} stc_mft_ppg_gatec16_field_t;
+
+typedef struct stc_mft_ppg_ppgc21_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc21_field_t;
+
+typedef struct stc_mft_ppg_ppgc20_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc20_field_t;
+
+typedef struct stc_mft_ppg_ppgc23_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc23_field_t;
+
+typedef struct stc_mft_ppg_ppgc22_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc22_field_t;
+
+typedef struct stc_mft_ppg_gatec20_field
+{
+  __IO  uint8_t EDGE20     : 1;
+  __IO  uint8_t STRG20     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE22     : 1;
+  __IO  uint8_t STRG22     : 1;
+} stc_mft_ppg_gatec20_field_t;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* BT_PPG_MODULE register bit fields */
+typedef struct stc_bt_ppg_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_ppg_tmcr_field_t;
+
+typedef struct stc_bt_ppg_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_ppg_stc_field_t;
+
+typedef struct stc_bt_ppg_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_ppg_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* BT_PWM_MODULE register bit fields */
+typedef struct stc_bt_pwm_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwm_tmcr_field_t;
+
+typedef struct stc_bt_pwm_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+  __IO  uint8_t DTIR       : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t UDIE       : 1;
+  __IO  uint8_t DTIE       : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_pwm_stc_field_t;
+
+typedef struct stc_bt_pwm_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwm_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* BT_RT_MODULE register bit fields */
+typedef struct stc_bt_rt_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_rt_tmcr_field_t;
+
+typedef struct stc_bt_rt_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_rt_stc_field_t;
+
+typedef struct stc_bt_rt_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_rt_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* BT_PWC_MODULE register bit fields */
+typedef struct stc_bt_pwc_tmcr_field
+{
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FMD0       : 1;
+  __IO uint16_t FMD1       : 1;
+  __IO uint16_t FMD2       : 1;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t EGS2       : 1;
+       uint16_t RESERVED3  : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwc_tmcr_field_t;
+
+typedef struct stc_bt_pwc_stc_field
+{
+  __IO  uint8_t OVIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t EDIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t OVIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t EDIE       : 1;
+  __IO  uint8_t ERR        : 1;
+} stc_bt_pwc_stc_field_t;
+
+typedef struct stc_bt_pwc_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwc_tmcr2_field_t;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* BTIOSEL03_MODULE register bit fields */
+typedef struct stc_btiosel03_btsel0123_field
+{
+  __IO  uint8_t SEL01_0    : 1;
+  __IO  uint8_t SEL01_1    : 1;
+  __IO  uint8_t SEL01_2    : 1;
+  __IO  uint8_t SEL01_3    : 1;
+  __IO  uint8_t SEL23_0    : 1;
+  __IO  uint8_t SEL23_1    : 1;
+  __IO  uint8_t SEL23_2    : 1;
+  __IO  uint8_t SEL23_3    : 1;
+} stc_btiosel03_btsel0123_field_t;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* BTIOSEL47_MODULE register bit fields */
+typedef struct stc_btiosel47_btsel4567_field
+{
+  __IO  uint8_t SEL45_0    : 1;
+  __IO  uint8_t SEL45_1    : 1;
+  __IO  uint8_t SEL45_2    : 1;
+  __IO  uint8_t SEL45_3    : 1;
+  __IO  uint8_t SEL67_0    : 1;
+  __IO  uint8_t SEL67_1    : 1;
+  __IO  uint8_t SEL67_2    : 1;
+  __IO  uint8_t SEL67_3    : 1;
+} stc_btiosel47_btsel4567_field_t;
+
+/******************************************************************************
+ * BTIOSEL811_MODULE
+ ******************************************************************************/
+/* BTIOSEL811_MODULE register bit fields */
+typedef struct stc_btiosel8b_btsel89ab_field
+{
+  __IO  uint8_t SEL89_0    : 1;
+  __IO  uint8_t SEL89_1    : 1;
+  __IO  uint8_t SEL89_2    : 1;
+  __IO  uint8_t SEL89_3    : 1;
+  __IO  uint8_t SELAB_0    : 1;
+  __IO  uint8_t SELAB_1    : 1;
+  __IO  uint8_t SELAB_2    : 1;
+  __IO  uint8_t SELAB_3    : 1;
+} stc_btiosel8b_btsel89ab_field_t;
+
+/******************************************************************************
+ * BTIOSEL1215_MODULE
+ ******************************************************************************/
+/* BTIOSEL1215_MODULE register bit fields */
+typedef struct stc_btioselcf_btselcdef_field
+{
+  __IO  uint8_t SELCD_0    : 1;
+  __IO  uint8_t SELCD_1    : 1;
+  __IO  uint8_t SELCD_2    : 1;
+  __IO  uint8_t SELCD_3    : 1;
+  __IO  uint8_t SELEF_0    : 1;
+  __IO  uint8_t SELEF_1    : 1;
+  __IO  uint8_t SELEF_2    : 1;
+  __IO  uint8_t SELEF_3    : 1;
+} stc_btioselcf_btselcdef_field_t;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* SBSSR_MODULE register bit fields */
+typedef struct stc_sbssr_btsssr_field
+{
+  __IO uint16_t SSR0       : 1;
+  __IO uint16_t SSR1       : 1;
+  __IO uint16_t SSR2       : 1;
+  __IO uint16_t SSR3       : 1;
+  __IO uint16_t SSR4       : 1;
+  __IO uint16_t SSR5       : 1;
+  __IO uint16_t SSR6       : 1;
+  __IO uint16_t SSR7       : 1;
+  __IO uint16_t SSR8       : 1;
+  __IO uint16_t SSR9       : 1;
+  __IO uint16_t SSR10      : 1;
+  __IO uint16_t SSR11      : 1;
+  __IO uint16_t SSR12      : 1;
+  __IO uint16_t SSR13      : 1;
+  __IO uint16_t SSR14      : 1;
+  __IO uint16_t SSR15      : 1;
+} stc_sbssr_btsssr_field_t;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* QPRC_MODULE register bit fields */
+typedef struct stc_qprc_qicr_field
+{
+  __IO uint16_t QPCMIE     : 1;
+  __IO uint16_t QPCMF      : 1;
+  __IO uint16_t QPRCMIE    : 1;
+  __IO uint16_t QPRCMF     : 1;
+  __IO uint16_t OUZIE      : 1;
+  __IO uint16_t UFDF       : 1;
+  __IO uint16_t OFDF       : 1;
+  __IO uint16_t ZIIF       : 1;
+  __IO uint16_t CDCIE      : 1;
+  __IO uint16_t CDCF       : 1;
+  __IO uint16_t DIRPC      : 1;
+  __IO uint16_t DIROU      : 1;
+  __IO uint16_t QPCNRCMIE  : 1;
+  __IO uint16_t QPCNRCMF   : 1;
+} stc_qprc_qicr_field_t;
+
+typedef struct stc_qprc_qicrl_field
+{
+  __IO  uint8_t QPCMIE     : 1;
+  __IO  uint8_t QPCMF      : 1;
+  __IO  uint8_t QPRCMIE    : 1;
+  __IO  uint8_t QPRCMF     : 1;
+  __IO  uint8_t OUZIE      : 1;
+  __IO  uint8_t UFDF       : 1;
+  __IO  uint8_t OFDF       : 1;
+  __IO  uint8_t ZIIF       : 1;
+} stc_qprc_qicrl_field_t;
+
+typedef struct stc_qprc_qicrh_field
+{
+  __IO  uint8_t CDCIE      : 1;
+  __IO  uint8_t CDCF       : 1;
+  __IO  uint8_t DIRPC      : 1;
+  __IO  uint8_t DIROU      : 1;
+  __IO  uint8_t QPCNRCMIE  : 1;
+  __IO  uint8_t QPCNRCMF   : 1;
+} stc_qprc_qicrh_field_t;
+
+typedef struct stc_qprc_qcr_field
+{
+  __IO uint16_t PCM0       : 1;
+  __IO uint16_t PCM1       : 1;
+  __IO uint16_t RCM0       : 1;
+  __IO uint16_t RCM1       : 1;
+  __IO uint16_t PSTP       : 1;
+  __IO uint16_t CGSC       : 1;
+  __IO uint16_t RSEL       : 1;
+  __IO uint16_t SWAP       : 1;
+  __IO uint16_t PCRM0      : 1;
+  __IO uint16_t PCRM1      : 1;
+  __IO uint16_t AES0       : 1;
+  __IO uint16_t AES1       : 1;
+  __IO uint16_t BES0       : 1;
+  __IO uint16_t BES1       : 1;
+  __IO uint16_t CGE0       : 1;
+  __IO uint16_t CGE1       : 1;
+} stc_qprc_qcr_field_t;
+
+typedef struct stc_qprc_qcrl_field
+{
+  __IO  uint8_t PCM0       : 1;
+  __IO  uint8_t PCM1       : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t PSTP       : 1;
+  __IO  uint8_t CGSC       : 1;
+  __IO  uint8_t RSEL       : 1;
+  __IO  uint8_t SWAP       : 1;
+} stc_qprc_qcrl_field_t;
+
+typedef struct stc_qprc_qcrh_field
+{
+  __IO  uint8_t PCRM0      : 1;
+  __IO  uint8_t PCRM1      : 1;
+  __IO  uint8_t AES0       : 1;
+  __IO  uint8_t AES1       : 1;
+  __IO  uint8_t BES0       : 1;
+  __IO  uint8_t BES1       : 1;
+  __IO  uint8_t CGE0       : 1;
+  __IO  uint8_t CGE1       : 1;
+} stc_qprc_qcrh_field_t;
+
+typedef struct stc_qprc_qecr_field
+{
+  __IO uint16_t ORNGMD     : 1;
+  __IO uint16_t ORNGF      : 1;
+  __IO uint16_t ORNGIE     : 1;
+} stc_qprc_qecr_field_t;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* ADC12_MODULE register bit fields */
+typedef struct stc_adc_adsr_field
+{
+  __IO  uint8_t SCS        : 1;
+  __IO  uint8_t PCS        : 1;
+  __IO  uint8_t PCNS       : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t FDAS       : 1;
+  __IO  uint8_t ADSTP      : 1;
+} stc_adc_adsr_field_t;
+
+typedef struct stc_adc_adcr_field
+{
+  __IO  uint8_t OVRIE      : 1;
+  __IO  uint8_t CMPIE      : 1;
+  __IO  uint8_t PCIE       : 1;
+  __IO  uint8_t SCIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t CMPIF      : 1;
+  __IO  uint8_t PCIF       : 1;
+  __IO  uint8_t SCIF       : 1;
+} stc_adc_adcr_field_t;
+
+typedef struct stc_adc_sfns_field
+{
+  __IO  uint8_t SFS0       : 1;
+  __IO  uint8_t SFS1       : 1;
+  __IO  uint8_t SFS2       : 1;
+  __IO  uint8_t SFS3       : 1;
+} stc_adc_sfns_field_t;
+
+typedef struct stc_adc_sccr_field
+{
+  __IO  uint8_t SSTR       : 1;
+  __IO  uint8_t SHEN       : 1;
+  __IO  uint8_t RPT        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t SFCLR      : 1;
+  __IO  uint8_t SOVR       : 1;
+  __IO  uint8_t SFUL       : 1;
+  __IO  uint8_t SEMP       : 1;
+} stc_adc_sccr_field_t;
+
+typedef struct stc_adc_scfd_field
+{
+  __IO uint32_t SC0        : 1;
+  __IO uint32_t SC1        : 1;
+  __IO uint32_t SC2        : 1;
+  __IO uint32_t SC3        : 1;
+  __IO uint32_t SC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+  __IO uint32_t SD3        : 1;
+  __IO uint32_t SD4        : 1;
+  __IO uint32_t SD5        : 1;
+  __IO uint32_t SD6        : 1;
+  __IO uint32_t SD7        : 1;
+  __IO uint32_t SD8        : 1;
+  __IO uint32_t SD9        : 1;
+  __IO uint32_t SD10       : 1;
+  __IO uint32_t SD11       : 1;
+} stc_adc_scfd_field_t;
+
+typedef struct stc_adc_scfdl_field
+{
+  __IO uint16_t SC0        : 1;
+  __IO uint16_t SC1        : 1;
+  __IO uint16_t SC2        : 1;
+  __IO uint16_t SC3        : 1;
+  __IO uint16_t SC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t INVL       : 1;
+} stc_adc_scfdl_field_t;
+
+typedef struct stc_adc_scfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t SD0        : 1;
+  __IO uint16_t SD1        : 1;
+  __IO uint16_t SD2        : 1;
+  __IO uint16_t SD3        : 1;
+  __IO uint16_t SD4        : 1;
+  __IO uint16_t SD5        : 1;
+  __IO uint16_t SD6        : 1;
+  __IO uint16_t SD7        : 1;
+  __IO uint16_t SD8        : 1;
+  __IO uint16_t SD9        : 1;
+  __IO uint16_t SD10       : 1;
+  __IO uint16_t SD11       : 1;
+} stc_adc_scfdh_field_t;
+
+typedef struct stc_adc_scis23_field
+{
+  __IO uint16_t AN16       : 1;
+  __IO uint16_t AN17       : 1;
+  __IO uint16_t AN18       : 1;
+  __IO uint16_t AN19       : 1;
+  __IO uint16_t AN20       : 1;
+  __IO uint16_t AN21       : 1;
+  __IO uint16_t AN22       : 1;
+  __IO uint16_t AN23       : 1;
+  __IO uint16_t AN24       : 1;
+  __IO uint16_t AN25       : 1;
+  __IO uint16_t AN26       : 1;
+  __IO uint16_t AN27       : 1;
+  __IO uint16_t AN28       : 1;
+  __IO uint16_t AN29       : 1;
+  __IO uint16_t AN30       : 1;
+  __IO uint16_t AN31       : 1;
+} stc_adc_scis23_field_t;
+
+typedef struct stc_adc_scis2_field
+{
+  __IO  uint8_t AN16       : 1;
+  __IO  uint8_t AN17       : 1;
+  __IO  uint8_t AN18       : 1;
+  __IO  uint8_t AN19       : 1;
+  __IO  uint8_t AN20       : 1;
+  __IO  uint8_t AN21       : 1;
+  __IO  uint8_t AN22       : 1;
+  __IO  uint8_t AN23       : 1;
+} stc_adc_scis2_field_t;
+
+typedef struct stc_adc_scis3_field
+{
+  __IO  uint8_t AN24       : 1;
+  __IO  uint8_t AN25       : 1;
+  __IO  uint8_t AN26       : 1;
+  __IO  uint8_t AN27       : 1;
+  __IO  uint8_t AN28       : 1;
+  __IO  uint8_t AN29       : 1;
+  __IO  uint8_t AN30       : 1;
+  __IO  uint8_t AN31       : 1;
+} stc_adc_scis3_field_t;
+
+typedef struct stc_adc_scis01_field
+{
+  __IO uint16_t AN0        : 1;
+  __IO uint16_t AN1        : 1;
+  __IO uint16_t AN2        : 1;
+  __IO uint16_t AN3        : 1;
+  __IO uint16_t AN4        : 1;
+  __IO uint16_t AN5        : 1;
+  __IO uint16_t AN6        : 1;
+  __IO uint16_t AN7        : 1;
+  __IO uint16_t AN8        : 1;
+  __IO uint16_t AN9        : 1;
+  __IO uint16_t AN10       : 1;
+  __IO uint16_t AN11       : 1;
+  __IO uint16_t AN12       : 1;
+  __IO uint16_t AN13       : 1;
+  __IO uint16_t AN14       : 1;
+  __IO uint16_t AN15       : 1;
+} stc_adc_scis01_field_t;
+
+typedef struct stc_adc_scis0_field
+{
+  __IO  uint8_t AN0        : 1;
+  __IO  uint8_t AN1        : 1;
+  __IO  uint8_t AN2        : 1;
+  __IO  uint8_t AN3        : 1;
+  __IO  uint8_t AN4        : 1;
+  __IO  uint8_t AN5        : 1;
+  __IO  uint8_t AN6        : 1;
+  __IO  uint8_t AN7        : 1;
+} stc_adc_scis0_field_t;
+
+typedef struct stc_adc_scis1_field
+{
+  __IO  uint8_t AN8        : 1;
+  __IO  uint8_t AN9        : 1;
+  __IO  uint8_t AN10       : 1;
+  __IO  uint8_t AN11       : 1;
+  __IO  uint8_t AN12       : 1;
+  __IO  uint8_t AN13       : 1;
+  __IO  uint8_t AN14       : 1;
+  __IO  uint8_t AN15       : 1;
+} stc_adc_scis1_field_t;
+
+typedef struct stc_adc_pfns_field
+{
+  __IO  uint8_t PFS0       : 1;
+  __IO  uint8_t PFS1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TEST0      : 1;
+  __IO  uint8_t TEST1      : 1;
+} stc_adc_pfns_field_t;
+
+typedef struct stc_adc_pccr_field
+{
+  __IO  uint8_t PSTR       : 1;
+  __IO  uint8_t PHEN       : 1;
+  __IO  uint8_t PEEN       : 1;
+  __IO  uint8_t ESCE       : 1;
+  __IO  uint8_t PFCLR      : 1;
+  __IO  uint8_t POVR       : 1;
+  __IO  uint8_t PFUL       : 1;
+  __IO  uint8_t PEMP       : 1;
+} stc_adc_pccr_field_t;
+
+typedef struct stc_adc_pcfd_field
+{
+  __IO uint32_t PC0        : 1;
+  __IO uint32_t PC1        : 1;
+  __IO uint32_t PC2        : 1;
+  __IO uint32_t PC3        : 1;
+  __IO uint32_t PC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t PD0        : 1;
+  __IO uint32_t PD1        : 1;
+  __IO uint32_t PD2        : 1;
+  __IO uint32_t PD3        : 1;
+  __IO uint32_t PD4        : 1;
+  __IO uint32_t PD5        : 1;
+  __IO uint32_t PD6        : 1;
+  __IO uint32_t PD7        : 1;
+  __IO uint32_t PD8        : 1;
+  __IO uint32_t PD9        : 1;
+  __IO uint32_t PD10       : 1;
+  __IO uint32_t PD11       : 1;
+} stc_adc_pcfd_field_t;
+
+typedef struct stc_adc_pcfdl_field
+{
+  __IO uint16_t PC0        : 1;
+  __IO uint16_t PC1        : 1;
+  __IO uint16_t PC2        : 1;
+  __IO uint16_t PC3        : 1;
+  __IO uint16_t PC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+  __IO uint16_t RS2        : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t INVL       : 1;
+} stc_adc_pcfdl_field_t;
+
+typedef struct stc_adc_pcfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t PD0        : 1;
+  __IO uint16_t PD1        : 1;
+  __IO uint16_t PD2        : 1;
+  __IO uint16_t PD3        : 1;
+  __IO uint16_t PD4        : 1;
+  __IO uint16_t PD5        : 1;
+  __IO uint16_t PD6        : 1;
+  __IO uint16_t PD7        : 1;
+  __IO uint16_t PD8        : 1;
+  __IO uint16_t PD9        : 1;
+  __IO uint16_t PD10       : 1;
+  __IO uint16_t PD11       : 1;
+} stc_adc_pcfdh_field_t;
+
+typedef struct stc_adc_pcis_field
+{
+  __IO  uint8_t P1A0       : 1;
+  __IO  uint8_t P1A1       : 1;
+  __IO  uint8_t P1A2       : 1;
+  __IO  uint8_t P2A0       : 1;
+  __IO  uint8_t P2A1       : 1;
+  __IO  uint8_t P2A2       : 1;
+  __IO  uint8_t P2A3       : 1;
+  __IO  uint8_t P2A4       : 1;
+} stc_adc_pcis_field_t;
+
+typedef struct stc_adc_cmpcr_field
+{
+  __IO  uint8_t CCH0       : 1;
+  __IO  uint8_t CCH1       : 1;
+  __IO  uint8_t CCH2       : 1;
+  __IO  uint8_t CCH3       : 1;
+  __IO  uint8_t CCH4       : 1;
+  __IO  uint8_t CMD0       : 1;
+  __IO  uint8_t CMD1       : 1;
+  __IO  uint8_t CMPEN      : 1;
+} stc_adc_cmpcr_field_t;
+
+typedef struct stc_adc_cmpd_field
+{
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t CMAD2      : 1;
+  __IO uint16_t CMAD3      : 1;
+  __IO uint16_t CMAD4      : 1;
+  __IO uint16_t CMAD5      : 1;
+  __IO uint16_t CMAD6      : 1;
+  __IO uint16_t CMAD7      : 1;
+  __IO uint16_t CMAD8      : 1;
+  __IO uint16_t CMAD9      : 1;
+  __IO uint16_t CMAD10     : 1;
+  __IO uint16_t CMAD11     : 1;
+} stc_adc_cmpd_field_t;
+
+typedef struct stc_adc_adss23_field
+{
+  __IO uint16_t TS16       : 1;
+  __IO uint16_t TS17       : 1;
+  __IO uint16_t TS18       : 1;
+  __IO uint16_t TS19       : 1;
+  __IO uint16_t TS20       : 1;
+  __IO uint16_t TS21       : 1;
+  __IO uint16_t TS22       : 1;
+  __IO uint16_t TS23       : 1;
+  __IO uint16_t TS24       : 1;
+  __IO uint16_t TS25       : 1;
+  __IO uint16_t TS26       : 1;
+  __IO uint16_t TS27       : 1;
+  __IO uint16_t TS28       : 1;
+  __IO uint16_t TS29       : 1;
+  __IO uint16_t TS30       : 1;
+  __IO uint16_t TS31       : 1;
+} stc_adc_adss23_field_t;
+
+typedef struct stc_adc_adss2_field
+{
+  __IO  uint8_t TS16       : 1;
+  __IO  uint8_t TS17       : 1;
+  __IO  uint8_t TS18       : 1;
+  __IO  uint8_t TS19       : 1;
+  __IO  uint8_t TS20       : 1;
+  __IO  uint8_t TS21       : 1;
+  __IO  uint8_t TS22       : 1;
+  __IO  uint8_t TS23       : 1;
+} stc_adc_adss2_field_t;
+
+typedef struct stc_adc_adss3_field
+{
+  __IO  uint8_t TS24       : 1;
+  __IO  uint8_t TS25       : 1;
+  __IO  uint8_t TS26       : 1;
+  __IO  uint8_t TS27       : 1;
+  __IO  uint8_t TS28       : 1;
+  __IO  uint8_t TS29       : 1;
+  __IO  uint8_t TS30       : 1;
+  __IO  uint8_t TS31       : 1;
+} stc_adc_adss3_field_t;
+
+typedef struct stc_adc_adss01_field
+{
+  __IO uint16_t TS0        : 1;
+  __IO uint16_t TS1        : 1;
+  __IO uint16_t TS2        : 1;
+  __IO uint16_t TS3        : 1;
+  __IO uint16_t TS4        : 1;
+  __IO uint16_t TS5        : 1;
+  __IO uint16_t TS6        : 1;
+  __IO uint16_t TS7        : 1;
+  __IO uint16_t TS8        : 1;
+  __IO uint16_t TS9        : 1;
+  __IO uint16_t TS10       : 1;
+  __IO uint16_t TS11       : 1;
+  __IO uint16_t TS12       : 1;
+  __IO uint16_t TS13       : 1;
+  __IO uint16_t TS14       : 1;
+  __IO uint16_t TS15       : 1;
+} stc_adc_adss01_field_t;
+
+typedef struct stc_adc_adss0_field
+{
+  __IO  uint8_t TS0        : 1;
+  __IO  uint8_t TS1        : 1;
+  __IO  uint8_t TS2        : 1;
+  __IO  uint8_t TS3        : 1;
+  __IO  uint8_t TS4        : 1;
+  __IO  uint8_t TS5        : 1;
+  __IO  uint8_t TS6        : 1;
+  __IO  uint8_t TS7        : 1;
+} stc_adc_adss0_field_t;
+
+typedef struct stc_adc_adss1_field
+{
+  __IO  uint8_t TS8        : 1;
+  __IO  uint8_t TS9        : 1;
+  __IO  uint8_t TS10       : 1;
+  __IO  uint8_t TS11       : 1;
+  __IO  uint8_t TS12       : 1;
+  __IO  uint8_t TS13       : 1;
+  __IO  uint8_t TS14       : 1;
+  __IO  uint8_t TS15       : 1;
+} stc_adc_adss1_field_t;
+
+typedef struct stc_adc_adst01_field
+{
+  __IO uint16_t ST10       : 1;
+  __IO uint16_t ST11       : 1;
+  __IO uint16_t ST12       : 1;
+  __IO uint16_t ST13       : 1;
+  __IO uint16_t ST14       : 1;
+  __IO uint16_t STX10      : 1;
+  __IO uint16_t STX11      : 1;
+  __IO uint16_t STX12      : 1;
+  __IO uint16_t ST00       : 1;
+  __IO uint16_t ST01       : 1;
+  __IO uint16_t ST02       : 1;
+  __IO uint16_t ST03       : 1;
+  __IO uint16_t ST04       : 1;
+  __IO uint16_t STX00      : 1;
+  __IO uint16_t STX01      : 1;
+  __IO uint16_t STX02      : 1;
+} stc_adc_adst01_field_t;
+
+typedef struct stc_adc_adst1_field
+{
+  __IO  uint8_t ST10       : 1;
+  __IO  uint8_t ST11       : 1;
+  __IO  uint8_t ST12       : 1;
+  __IO  uint8_t ST13       : 1;
+  __IO  uint8_t ST14       : 1;
+  __IO  uint8_t STX10      : 1;
+  __IO  uint8_t STX11      : 1;
+  __IO  uint8_t STX12      : 1;
+} stc_adc_adst1_field_t;
+
+typedef struct stc_adc_adst0_field
+{
+  __IO  uint8_t ST00       : 1;
+  __IO  uint8_t ST01       : 1;
+  __IO  uint8_t ST02       : 1;
+  __IO  uint8_t ST03       : 1;
+  __IO  uint8_t ST04       : 1;
+  __IO  uint8_t STX00      : 1;
+  __IO  uint8_t STX01      : 1;
+  __IO  uint8_t STX02      : 1;
+} stc_adc_adst0_field_t;
+
+typedef struct stc_adc_adct_field
+{
+  __IO  uint8_t CT0        : 1;
+  __IO  uint8_t CT1        : 1;
+  __IO  uint8_t CT2        : 1;
+  __IO  uint8_t CT3        : 1;
+  __IO  uint8_t CT4        : 1;
+  __IO  uint8_t CT5        : 1;
+  __IO  uint8_t CT6        : 1;
+  __IO  uint8_t CT7        : 1;
+} stc_adc_adct_field_t;
+
+typedef struct stc_adc_prtsl_field
+{
+  __IO  uint8_t PRTSL0     : 1;
+  __IO  uint8_t PRTSL1     : 1;
+  __IO  uint8_t PRTSL2     : 1;
+  __IO  uint8_t PRTSL3     : 1;
+} stc_adc_prtsl_field_t;
+
+typedef struct stc_adc_sctsl_field
+{
+  __IO  uint8_t SCTSL0     : 1;
+  __IO  uint8_t SCTSL1     : 1;
+  __IO  uint8_t SCTSL2     : 1;
+  __IO  uint8_t SCTSL3     : 1;
+} stc_adc_sctsl_field_t;
+
+typedef struct stc_adc_adcen_field
+{
+  __IO  uint8_t ENBL       : 1;
+  __IO  uint8_t READY      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CYCLSL0    : 1;
+  __IO  uint8_t CYCLSL1    : 1;
+} stc_adc_adcen_field_t;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CRTRIM_MODULE register bit fields */
+typedef struct stc_crtrim_mcr_psr_field
+{
+  __IO  uint8_t CSR0       : 1;
+  __IO  uint8_t CSR1       : 1;
+} stc_crtrim_mcr_psr_field_t;
+
+typedef struct stc_crtrim_mcr_ftrm_field
+{
+  __IO uint16_t TRD0       : 1;
+  __IO uint16_t TRD1       : 1;
+  __IO uint16_t TRD2       : 1;
+  __IO uint16_t TRD3       : 1;
+  __IO uint16_t TRD4       : 1;
+  __IO uint16_t TRD5       : 1;
+  __IO uint16_t TRD6       : 1;
+  __IO uint16_t TRD7       : 1;
+} stc_crtrim_mcr_ftrm_field_t;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* EXTI_MODULE registEN bit fields */
+typedef struct stc_exti_enir_field
+{
+  __IO uint16_t EN0        : 1;
+  __IO uint16_t EN1        : 1;
+  __IO uint16_t EN2        : 1;
+  __IO uint16_t EN3        : 1;
+  __IO uint16_t EN4        : 1;
+  __IO uint16_t EN5        : 1;
+  __IO uint16_t EN6        : 1;
+  __IO uint16_t EN7        : 1;
+  __IO uint16_t EN8        : 1;
+  __IO uint16_t EN9        : 1;
+  __IO uint16_t EN10       : 1;
+  __IO uint16_t EN11       : 1;
+  __IO uint16_t EN12       : 1;
+  __IO uint16_t EN13       : 1;
+  __IO uint16_t EN14       : 1;
+  __IO uint16_t EN15       : 1;
+  __IO uint16_t EN16       : 1;
+  __IO uint16_t EN17       : 1;
+  __IO uint16_t EN18       : 1;
+  __IO uint16_t EN19       : 1;
+  __IO uint16_t EN20       : 1;
+  __IO uint16_t EN21       : 1;
+  __IO uint16_t EN22       : 1;
+  __IO uint16_t EN23       : 1;
+  __IO uint16_t EN24       : 1;
+  __IO uint16_t EN25       : 1;
+  __IO uint16_t EN26       : 1;
+  __IO uint16_t EN27       : 1;
+  __IO uint16_t EN28       : 1;
+  __IO uint16_t EN29       : 1;
+  __IO uint16_t EN30       : 1;
+  __IO uint16_t EN31       : 1;
+} stc_exti_enir_field_t;
+
+typedef struct stc_exti_eirr_field
+{
+  __IO uint16_t ER0        : 1;
+  __IO uint16_t ER1        : 1;
+  __IO uint16_t ER2        : 1;
+  __IO uint16_t ER3        : 1;
+  __IO uint16_t ER4        : 1;
+  __IO uint16_t ER5        : 1;
+  __IO uint16_t ER6        : 1;
+  __IO uint16_t ER7        : 1;
+  __IO uint16_t ER8        : 1;
+  __IO uint16_t ER9        : 1;
+  __IO uint16_t ER10       : 1;
+  __IO uint16_t ER11       : 1;
+  __IO uint16_t ER12       : 1;
+  __IO uint16_t ER13       : 1;
+  __IO uint16_t ER14       : 1;
+  __IO uint16_t ER15       : 1;
+  __IO uint16_t ER16       : 1;
+  __IO uint16_t ER17       : 1;
+  __IO uint16_t ER18       : 1;
+  __IO uint16_t ER19       : 1;
+  __IO uint16_t ER20       : 1;
+  __IO uint16_t ER21       : 1;
+  __IO uint16_t ER22       : 1;
+  __IO uint16_t ER23       : 1;
+  __IO uint16_t ER24       : 1;
+  __IO uint16_t ER25       : 1;
+  __IO uint16_t ER26       : 1;
+  __IO uint16_t ER27       : 1;
+  __IO uint16_t ER28       : 1;
+  __IO uint16_t ER29       : 1;
+  __IO uint16_t ER30       : 1;
+  __IO uint16_t ER31       : 1;
+} stc_exti_eirr_field_t;
+
+typedef struct stc_exti_eicl_field
+{
+  __IO uint16_t ECL0       : 1;
+  __IO uint16_t ECL1       : 1;
+  __IO uint16_t ECL2       : 1;
+  __IO uint16_t ECL3       : 1;
+  __IO uint16_t ECL4       : 1;
+  __IO uint16_t ECL5       : 1;
+  __IO uint16_t ECL6       : 1;
+  __IO uint16_t ECL7       : 1;
+  __IO uint16_t ECL8       : 1;
+  __IO uint16_t ECL9       : 1;
+  __IO uint16_t ECL10      : 1;
+  __IO uint16_t ECL11      : 1;
+  __IO uint16_t ECL12      : 1;
+  __IO uint16_t ECL13      : 1;
+  __IO uint16_t ECL14      : 1;
+  __IO uint16_t ECL15      : 1;
+  __IO uint16_t ECL16      : 1;
+  __IO uint16_t ECL17      : 1;
+  __IO uint16_t ECL18      : 1;
+  __IO uint16_t ECL19      : 1;
+  __IO uint16_t ECL20      : 1;
+  __IO uint16_t ECL21      : 1;
+  __IO uint16_t ECL22      : 1;
+  __IO uint16_t ECL23      : 1;
+  __IO uint16_t ECL24      : 1;
+  __IO uint16_t ECL25      : 1;
+  __IO uint16_t ECL26      : 1;
+  __IO uint16_t ECL27      : 1;
+  __IO uint16_t ECL28      : 1;
+  __IO uint16_t ECL29      : 1;
+  __IO uint16_t ECL30      : 1;
+  __IO uint16_t ECL31      : 1;
+} stc_exti_eicl_field_t;
+
+typedef struct stc_exti_elvr_field
+{
+  __IO uint32_t LA0        : 1;
+  __IO uint32_t LB0        : 1;
+  __IO uint32_t LA1        : 1;
+  __IO uint32_t LB1        : 1;
+  __IO uint32_t LA2        : 1;
+  __IO uint32_t LB2        : 1;
+  __IO uint32_t LA3        : 1;
+  __IO uint32_t LB3        : 1;
+  __IO uint32_t LA4        : 1;
+  __IO uint32_t LB4        : 1;
+  __IO uint32_t LA5        : 1;
+  __IO uint32_t LB5        : 1;
+  __IO uint32_t LA6        : 1;
+  __IO uint32_t LB6        : 1;
+  __IO uint32_t LA7        : 1;
+  __IO uint32_t LB7        : 1;
+  __IO uint32_t LA8        : 1;
+  __IO uint32_t LB8        : 1;
+  __IO uint32_t LA9        : 1;
+  __IO uint32_t LB9        : 1;
+  __IO uint32_t LA10       : 1;
+  __IO uint32_t LB10       : 1;
+  __IO uint32_t LA11       : 1;
+  __IO uint32_t LB11       : 1;
+  __IO uint32_t LA12       : 1;
+  __IO uint32_t LB12       : 1;
+  __IO uint32_t LA13       : 1;
+  __IO uint32_t LB13       : 1;
+  __IO uint32_t LA14       : 1;
+  __IO uint32_t LB14       : 1;
+  __IO uint32_t LA15       : 1;
+  __IO uint32_t LB15       : 1;
+} stc_exti_elvr_field_t;
+
+typedef struct stc_exti_elvr1_field
+{
+  __IO uint32_t LA16       : 1;
+  __IO uint32_t LB16       : 1;
+  __IO uint32_t LA17       : 1;
+  __IO uint32_t LB17       : 1;
+  __IO uint32_t LA18       : 1;
+  __IO uint32_t LB18       : 1;
+  __IO uint32_t LA19       : 1;
+  __IO uint32_t LB19       : 1;
+  __IO uint32_t LA20       : 1;
+  __IO uint32_t LB20       : 1;
+  __IO uint32_t LA21       : 1;
+  __IO uint32_t LB21       : 1;
+  __IO uint32_t LA22       : 1;
+  __IO uint32_t LB22       : 1;
+  __IO uint32_t LA23       : 1;
+  __IO uint32_t LB23       : 1;
+  __IO uint32_t LA24       : 1;
+  __IO uint32_t LB24       : 1;
+  __IO uint32_t LA25       : 1;
+  __IO uint32_t LB25       : 1;
+  __IO uint32_t LA26       : 1;
+  __IO uint32_t LB26       : 1;
+  __IO uint32_t LA27       : 1;
+  __IO uint32_t LB27       : 1;
+  __IO uint32_t LA28       : 1;
+  __IO uint32_t LB28       : 1;
+  __IO uint32_t LA29       : 1;
+  __IO uint32_t LB29       : 1;
+  __IO uint32_t LA30       : 1;
+  __IO uint32_t LB30       : 1;
+  __IO uint32_t LA31       : 1;
+  __IO uint32_t LB31       : 1;
+} stc_exti_elvr1_field_t;
+
+typedef struct stc_exti_nmirr_field
+{
+  __IO  uint8_t NR0        : 1;
+} stc_exti_nmirr_field_t;
+
+typedef struct stc_exti_nmicl_field
+{
+  __IO  uint8_t NCL0       : 1;
+} stc_exti_nmicl_field_t;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* INTREQ_MODULE register bit fields */
+typedef struct stc_intreq_drqsel_field
+{
+  __IO uint32_t DRQSEL0    : 1;
+  __IO uint32_t DRQSEL1    : 1;
+  __IO uint32_t DRQSEL2    : 1;
+  __IO uint32_t DRQSEL3    : 1;
+  __IO uint32_t DRQSEL4    : 1;
+  __IO uint32_t DRQSEL5    : 1;
+  __IO uint32_t DRQSEL6    : 1;
+  __IO uint32_t DRQSEL7    : 1;
+  __IO uint32_t DRQSEL8    : 1;
+  __IO uint32_t DRQSEL9    : 1;
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+  __IO uint32_t DRQSEL15   : 1;
+  __IO uint32_t DRQSEL16   : 1;
+  __IO uint32_t DRQSEL17   : 1;
+  __IO uint32_t DRQSEL18   : 1;
+  __IO uint32_t DRQSEL19   : 1;
+  __IO uint32_t DRQSEL20   : 1;
+  __IO uint32_t DRQSEL21   : 1;
+  __IO uint32_t DRQSEL22   : 1;
+  __IO uint32_t DRQSEL23   : 1;
+  __IO uint32_t DRQSEL24   : 1;
+  __IO uint32_t DRQSEL25   : 1;
+  __IO uint32_t DRQSEL26   : 1;
+  __IO uint32_t DRQSEL27   : 1;
+  __IO uint32_t DRQSEL28   : 1;
+  __IO uint32_t DRQSEL29   : 1;
+  __IO uint32_t DRQSEL30   : 1;
+  __IO uint32_t DRQSEL31   : 1;
+} stc_intreq_drqsel_field_t;
+
+typedef struct stc_intreq_oddpks_field
+{
+  __IO  uint8_t ODDPKS0    : 1;
+  __IO  uint8_t ODDPKS1    : 1;
+  __IO  uint8_t ODDPKS2    : 1;
+  __IO  uint8_t ODDPKS3    : 1;
+  __IO  uint8_t ODDPKS4    : 1;
+} stc_intreq_oddpks_field_t;
+
+typedef struct stc_intreq_exc02mon_field
+{
+  __IO uint32_t NMI        : 1;
+  __IO uint32_t HWINT      : 1;
+} stc_intreq_exc02mon_field_t;
+
+typedef struct stc_intreq_irq00mon_field
+{
+  __IO uint32_t FCSINT     : 1;
+} stc_intreq_irq00mon_field_t;
+
+typedef struct stc_intreq_irq01mon_field
+{
+  __IO uint32_t SWWDTINT   : 1;
+} stc_intreq_irq01mon_field_t;
+
+typedef struct stc_intreq_irq02mon_field
+{
+  __IO uint32_t LVDINT     : 1;
+} stc_intreq_irq02mon_field_t;
+
+typedef struct stc_intreq_irq03mon_field
+{
+  __IO uint32_t WAVE0INT0  : 1;
+  __IO uint32_t WAVE0INT1  : 1;
+  __IO uint32_t WAVE0INT2  : 1;
+  __IO uint32_t WAVE0INT3  : 1;
+  __IO uint32_t WAVE1INT0  : 1;
+  __IO uint32_t WAVE1INT1  : 1;
+  __IO uint32_t WAVE1INT2  : 1;
+  __IO uint32_t WAVE1INT3  : 1;
+  __IO uint32_t WAVE2INT0  : 1;
+  __IO uint32_t WAVE2INT1  : 1;
+  __IO uint32_t WAVE2INT2  : 1;
+  __IO uint32_t WAVE2INT3  : 1;
+} stc_intreq_irq03mon_field_t;
+
+typedef struct stc_intreq_irq04mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+} stc_intreq_irq04mon_field_t;
+
+typedef struct stc_intreq_irq05mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+  __IO uint32_t EXTINT8    : 1;
+  __IO uint32_t EXTINT9    : 1;
+  __IO uint32_t EXTINT10   : 1;
+  __IO uint32_t EXTINT11   : 1;
+  __IO uint32_t EXTINT12   : 1;
+  __IO uint32_t EXTINT13   : 1;
+  __IO uint32_t EXTINT14   : 1;
+  __IO uint32_t EXTINT15   : 1;
+  __IO uint32_t EXTINT16   : 1;
+  __IO uint32_t EXTINT17   : 1;
+  __IO uint32_t EXTINT18   : 1;
+  __IO uint32_t EXTINT19   : 1;
+  __IO uint32_t EXTINT20   : 1;
+  __IO uint32_t EXTINT21   : 1;
+  __IO uint32_t EXTINT22   : 1;
+  __IO uint32_t EXTINT23   : 1;
+} stc_intreq_irq05mon_field_t;
+
+typedef struct stc_intreq_irq06mon_field
+{
+  __IO uint32_t TIMINT1    : 1;
+  __IO uint32_t TIMINT2    : 1;
+  __IO uint32_t QUD0INT0   : 1;
+  __IO uint32_t QUD0INT1   : 1;
+  __IO uint32_t QUD0INT2   : 1;
+  __IO uint32_t QUD0INT3   : 1;
+  __IO uint32_t QUD0INT4   : 1;
+  __IO uint32_t QUD0INT5   : 1;
+  __IO uint32_t QUD1INT0   : 1;
+  __IO uint32_t QUD1INT1   : 1;
+  __IO uint32_t QUD1INT2   : 1;
+  __IO uint32_t QUD1INT3   : 1;
+  __IO uint32_t QUD1INT4   : 1;
+  __IO uint32_t QUD1INT5   : 1;
+  __IO uint32_t QUD2INT0   : 1;
+  __IO uint32_t QUD2INT1   : 1;
+  __IO uint32_t QUD2INT2   : 1;
+  __IO uint32_t QUD2INT3   : 1;
+  __IO uint32_t QUD2INT4   : 1;
+  __IO uint32_t QUD2INT5   : 1;
+} stc_intreq_irq06mon_field_t;
+
+typedef struct stc_intreq_irq07mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq07mon_field_t;
+
+typedef struct stc_intreq_irq08mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq08mon_field_t;
+
+typedef struct stc_intreq_irq09mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq09mon_field_t;
+
+typedef struct stc_intreq_irq10mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq10mon_field_t;
+
+typedef struct stc_intreq_irq11mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq11mon_field_t;
+
+typedef struct stc_intreq_irq12mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq12mon_field_t;
+
+typedef struct stc_intreq_irq13mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq13mon_field_t;
+
+typedef struct stc_intreq_irq14mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq14mon_field_t;
+
+typedef struct stc_intreq_irq15mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq15mon_field_t;
+
+typedef struct stc_intreq_irq16mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq16mon_field_t;
+
+typedef struct stc_intreq_irq17mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq17mon_field_t;
+
+typedef struct stc_intreq_irq18mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq18mon_field_t;
+
+typedef struct stc_intreq_irq19mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq19mon_field_t;
+
+typedef struct stc_intreq_irq20mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq20mon_field_t;
+
+typedef struct stc_intreq_irq21mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq21mon_field_t;
+
+typedef struct stc_intreq_irq22mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq22mon_field_t;
+
+typedef struct stc_intreq_irq23mon_field
+{
+  __IO uint32_t PPGINT0    : 1;
+  __IO uint32_t PPGINT1    : 1;
+  __IO uint32_t PPGINT2    : 1;
+  __IO uint32_t PPGINT3    : 1;
+  __IO uint32_t PPGINT4    : 1;
+  __IO uint32_t PPGINT5    : 1;
+  __IO uint32_t PPGINT6    : 1;
+  __IO uint32_t PPGINT7    : 1;
+  __IO uint32_t PPGINT8    : 1;
+} stc_intreq_irq23mon_field_t;
+
+typedef struct stc_intreq_irq24mon_field
+{
+  __IO uint32_t MOSCINT    : 1;
+  __IO uint32_t SOSCINT    : 1;
+  __IO uint32_t MPLLINT    : 1;
+  __IO uint32_t UPLLINT    : 1;
+  __IO uint32_t WCINT      : 1;
+} stc_intreq_irq24mon_field_t;
+
+typedef struct stc_intreq_irq25mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq25mon_field_t;
+
+typedef struct stc_intreq_irq26mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq26mon_field_t;
+
+typedef struct stc_intreq_irq27mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq27mon_field_t;
+
+typedef struct stc_intreq_irq28mon_field
+{
+  __IO uint32_t FRT0INT0   : 1;
+  __IO uint32_t FRT0INT1   : 1;
+  __IO uint32_t FRT0INT2   : 1;
+  __IO uint32_t FRT0INT3   : 1;
+  __IO uint32_t FRT0INT4   : 1;
+  __IO uint32_t FRT0INT5   : 1;
+  __IO uint32_t FRT1INT0   : 1;
+  __IO uint32_t FRT1INT1   : 1;
+  __IO uint32_t FRT1INT2   : 1;
+  __IO uint32_t FRT1INT3   : 1;
+  __IO uint32_t FRT1INT4   : 1;
+  __IO uint32_t FRT1INT5   : 1;
+  __IO uint32_t FRT2INT0   : 1;
+  __IO uint32_t FRT2INT1   : 1;
+  __IO uint32_t FRT2INT2   : 1;
+  __IO uint32_t FRT2INT3   : 1;
+  __IO uint32_t FRT2INT4   : 1;
+  __IO uint32_t FRT2INT5   : 1;
+} stc_intreq_irq28mon_field_t;
+
+typedef struct stc_intreq_irq29mon_field
+{
+  __IO uint32_t ICU0INT0   : 1;
+  __IO uint32_t ICU0INT1   : 1;
+  __IO uint32_t ICU0INT2   : 1;
+  __IO uint32_t ICU0INT3   : 1;
+  __IO uint32_t ICU1INT0   : 1;
+  __IO uint32_t ICU1INT1   : 1;
+  __IO uint32_t ICU1INT2   : 1;
+  __IO uint32_t ICU1INT3   : 1;
+  __IO uint32_t ICU2INT0   : 1;
+  __IO uint32_t ICU2INT1   : 1;
+  __IO uint32_t ICU2INT2   : 1;
+  __IO uint32_t ICU2INT3   : 1;
+} stc_intreq_irq29mon_field_t;
+
+typedef struct stc_intreq_irq30mon_field
+{
+  __IO uint32_t OCU0INT0   : 1;
+  __IO uint32_t OCU0INT1   : 1;
+  __IO uint32_t OCU0INT2   : 1;
+  __IO uint32_t OCU0INT3   : 1;
+  __IO uint32_t OCU0INT4   : 1;
+  __IO uint32_t OCU0INT5   : 1;
+  __IO uint32_t OCU1INT0   : 1;
+  __IO uint32_t OCU1INT1   : 1;
+  __IO uint32_t OCU1INT2   : 1;
+  __IO uint32_t OCU1INT3   : 1;
+  __IO uint32_t OCU1INT4   : 1;
+  __IO uint32_t OCU1INT5   : 1;
+  __IO uint32_t OCU2INT0   : 1;
+  __IO uint32_t OCU2INT1   : 1;
+  __IO uint32_t OCU2INT2   : 1;
+  __IO uint32_t OCU2INT3   : 1;
+  __IO uint32_t OCU2INT4   : 1;
+  __IO uint32_t OCU2INT5   : 1;
+} stc_intreq_irq30mon_field_t;
+
+typedef struct stc_intreq_irq31mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq31mon_field_t;
+
+typedef struct stc_intreq_irq32mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC0SBD    : 1;
+  __IO uint32_t MAC0PMI    : 1;
+  __IO uint32_t MAC0LPI    : 1;
+} stc_intreq_irq32mon_field_t;
+
+typedef struct stc_intreq_irq33mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC1SBD    : 1;
+  __IO uint32_t MAC1PMI    : 1;
+} stc_intreq_irq33mon_field_t;
+
+typedef struct stc_intreq_irq34mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+} stc_intreq_irq34mon_field_t;
+
+typedef struct stc_intreq_irq35mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+  __IO uint32_t USB0INT5   : 1;
+} stc_intreq_irq35mon_field_t;
+
+typedef struct stc_intreq_irq36mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+} stc_intreq_irq36mon_field_t;
+
+typedef struct stc_intreq_irq37mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+  __IO uint32_t USB1INT5   : 1;
+} stc_intreq_irq37mon_field_t;
+
+typedef struct stc_intreq_irq38mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq38mon_field_t;
+
+typedef struct stc_intreq_irq39mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq39mon_field_t;
+
+typedef struct stc_intreq_irq40mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq40mon_field_t;
+
+typedef struct stc_intreq_irq41mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq41mon_field_t;
+
+typedef struct stc_intreq_irq42mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq42mon_field_t;
+
+typedef struct stc_intreq_irq43mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq43mon_field_t;
+
+typedef struct stc_intreq_irq44mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq44mon_field_t;
+
+typedef struct stc_intreq_irq45mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq45mon_field_t;
+
+typedef struct stc_intreq_irq46mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq46mon_field_t;
+
+typedef struct stc_intreq_drqsel1_field
+{
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+} stc_intreq_drqsel1_field_t;
+
+typedef struct stc_intreq_dqesel_field
+{
+  __IO uint32_t ESEL100    : 1;
+  __IO uint32_t ESEL101    : 1;
+  __IO uint32_t ESEL102    : 1;
+  __IO uint32_t ESEL103    : 1;
+  __IO uint32_t ESEL110    : 1;
+  __IO uint32_t ESEL111    : 1;
+  __IO uint32_t ESEL112    : 1;
+  __IO uint32_t ESEL113    : 1;
+  __IO uint32_t ESEL240    : 1;
+  __IO uint32_t ESEL241    : 1;
+  __IO uint32_t ESEL242    : 1;
+  __IO uint32_t ESEL243    : 1;
+  __IO uint32_t ESEL250    : 1;
+  __IO uint32_t ESEL251    : 1;
+  __IO uint32_t ESEL252    : 1;
+  __IO uint32_t ESEL253    : 1;
+  __IO uint32_t ESEL260    : 1;
+  __IO uint32_t ESEL261    : 1;
+  __IO uint32_t ESEL262    : 1;
+  __IO uint32_t ESEL263    : 1;
+  __IO uint32_t ESEL270    : 1;
+  __IO uint32_t ESEL271    : 1;
+  __IO uint32_t ESEL272    : 1;
+  __IO uint32_t ESEL273    : 1;
+  __IO uint32_t ESEL300    : 1;
+  __IO uint32_t ESEL301    : 1;
+  __IO uint32_t ESEL302    : 1;
+  __IO uint32_t ESEL303    : 1;
+  __IO uint32_t ESEL310    : 1;
+  __IO uint32_t ESEL311    : 1;
+  __IO uint32_t ESEL312    : 1;
+  __IO uint32_t ESEL313    : 1;
+} stc_intreq_dqesel_field_t;
+
+typedef struct stc_intreq_oddpks1_field
+{
+  __IO  uint8_t ODDPKS10   : 1;
+  __IO  uint8_t ODDPKS11   : 1;
+  __IO  uint8_t ODDPKS12   : 1;
+  __IO  uint8_t ODDPKS13   : 1;
+  __IO  uint8_t ODDPKS14   : 1;
+} stc_intreq_oddpks1_field_t;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* GPIO_MODULE register bit fields */
+typedef struct stc_gpio_pfr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr0_field_t;
+
+typedef struct stc_gpio_pfr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr1_field_t;
+
+typedef struct stc_gpio_pfr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr2_field_t;
+
+typedef struct stc_gpio_pfr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr3_field_t;
+
+typedef struct stc_gpio_pfr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pfr4_field_t;
+
+typedef struct stc_gpio_pfr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pfr5_field_t;
+
+typedef struct stc_gpio_pfr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pfr6_field_t;
+
+typedef struct stc_gpio_pfr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pfr7_field_t;
+
+typedef struct stc_gpio_pfr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfr8_field_t;
+
+
+typedef struct stc_gpio_pfra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pfra_field_t;
+
+typedef struct stc_gpio_pfrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfrc_field_t;
+
+typedef struct stc_gpio_pfrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfrd_field_t;
+
+typedef struct stc_gpio_pfre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfre_field_t;
+
+typedef struct stc_gpio_pfrf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pfrf_field_t;
+
+typedef struct stc_gpio_pcr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr0_field_t;
+
+typedef struct stc_gpio_pcr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr1_field_t;
+
+typedef struct stc_gpio_pcr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr2_field_t;
+
+typedef struct stc_gpio_pcr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr3_field_t;
+
+typedef struct stc_gpio_pcr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pcr4_field_t;
+
+typedef struct stc_gpio_pcr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pcr5_field_t;
+
+typedef struct stc_gpio_pcr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pcr6_field_t;
+
+typedef struct stc_gpio_pcr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pcr7_field_t;
+
+typedef struct stc_gpio_pcra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pcra_field_t;
+
+typedef struct stc_gpio_pcrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcrc_field_t;
+
+typedef struct stc_gpio_pcrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcrd_field_t;
+
+typedef struct stc_gpio_pcre_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcre_field_t;
+
+typedef struct stc_gpio_ddr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr0_field_t;
+
+typedef struct stc_gpio_ddr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr1_field_t;
+
+typedef struct stc_gpio_ddr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr2_field_t;
+
+typedef struct stc_gpio_ddr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr3_field_t;
+
+typedef struct stc_gpio_ddr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_ddr4_field_t;
+
+typedef struct stc_gpio_ddr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_ddr5_field_t;
+
+typedef struct stc_gpio_ddr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_ddr6_field_t;
+
+typedef struct stc_gpio_ddr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_ddr7_field_t;
+
+typedef struct stc_gpio_ddr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddr8_field_t;
+
+typedef struct stc_gpio_ddra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_ddra_field_t;
+
+typedef struct stc_gpio_ddrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddrc_field_t;
+
+typedef struct stc_gpio_ddrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddrd_field_t;
+
+typedef struct stc_gpio_ddre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddre_field_t;
+
+typedef struct stc_gpio_ddrf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_ddrf_field_t;
+
+typedef struct stc_gpio_pdir0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir0_field_t;
+
+typedef struct stc_gpio_pdir1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir1_field_t;
+
+typedef struct stc_gpio_pdir2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir2_field_t;
+
+typedef struct stc_gpio_pdir3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir3_field_t;
+
+typedef struct stc_gpio_pdir4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdir4_field_t;
+
+typedef struct stc_gpio_pdir5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pdir5_field_t;
+
+typedef struct stc_gpio_pdir6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdir6_field_t;
+
+typedef struct stc_gpio_pdir7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pdir7_field_t;
+
+typedef struct stc_gpio_pdir8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdir8_field_t;
+
+typedef struct stc_gpio_pdira_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdira_field_t;
+
+typedef struct stc_gpio_pdirc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdirc_field_t;
+
+typedef struct stc_gpio_pdird_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdird_field_t;
+
+typedef struct stc_gpio_pdire_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdire_field_t;
+
+typedef struct stc_gpio_pdirf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdirf_field_t;
+
+typedef struct stc_gpio_pdor0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor0_field_t;
+
+typedef struct stc_gpio_pdor1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor1_field_t;
+
+typedef struct stc_gpio_pdor2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor2_field_t;
+
+typedef struct stc_gpio_pdor3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor3_field_t;
+
+typedef struct stc_gpio_pdor4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdor4_field_t;
+
+typedef struct stc_gpio_pdor5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pdor5_field_t;
+
+typedef struct stc_gpio_pdor6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdor6_field_t;
+
+typedef struct stc_gpio_pdor7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pdor7_field_t;
+
+typedef struct stc_gpio_pdor8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdor8_field_t;
+
+typedef struct stc_gpio_pdora_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdora_field_t;
+
+typedef struct stc_gpio_pdorc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdorc_field_t;
+
+typedef struct stc_gpio_pdord_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdord_field_t;
+
+typedef struct stc_gpio_pdore_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdore_field_t;
+
+typedef struct stc_gpio_pdorf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdorf_field_t;
+
+typedef struct stc_gpio_ade_field
+{
+  __IO uint32_t AN0        : 1;
+  __IO uint32_t AN1        : 1;
+  __IO uint32_t AN2        : 1;
+  __IO uint32_t AN3        : 1;
+  __IO uint32_t AN4        : 1;
+  __IO uint32_t AN5        : 1;
+  __IO uint32_t AN6        : 1;
+  __IO uint32_t AN7        : 1;
+  __IO uint32_t AN8        : 1;
+  __IO uint32_t AN9        : 1;
+  __IO uint32_t AN10       : 1;
+  __IO uint32_t AN11       : 1;
+  __IO uint32_t AN12       : 1;
+  __IO uint32_t AN13       : 1;
+  __IO uint32_t AN14       : 1;
+  __IO uint32_t AN15       : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t AN24       : 1;
+  __IO uint32_t AN25       : 1;
+  __IO uint32_t AN26       : 1;
+  __IO uint32_t AN27       : 1;
+  __IO uint32_t AN28       : 1;
+  __IO uint32_t AN29       : 1;
+  __IO uint32_t AN30       : 1;
+  __IO uint32_t AN31       : 1;
+} stc_gpio_ade_field_t;
+
+typedef struct stc_gpio_spsr_field
+{
+  __IO uint32_t SUBXC      : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAINXC     : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USB0C      : 1;
+  __IO uint32_t USB1C      : 1;
+} stc_gpio_spsr_field_t;
+
+typedef struct stc_gpio_epfr00_field
+{
+  __IO uint32_t NMIS       : 1;
+  __IO uint32_t CROUTE0    : 1;
+  __IO uint32_t CROUTE1    : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t SUBOUTE0   : 1;
+  __IO uint32_t SUBOUTE1   : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USBP0E     : 1;
+       uint32_t RESERVED3  : 3;
+  __IO uint32_t USBP1E     : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t JTAGEN0B   : 1;
+  __IO uint32_t JTAGEN1S   : 1;
+       uint32_t RESERVED5  : 6;
+  __IO uint32_t TRC0E      : 1;
+  __IO uint32_t TRC1E      : 1;
+} stc_gpio_epfr00_field_t;
+
+typedef struct stc_gpio_epfr01_field
+{
+  __IO uint32_t RTO00E0    : 1;
+  __IO uint32_t RTO00E1    : 1;
+  __IO uint32_t RTO01E0    : 1;
+  __IO uint32_t RTO01E1    : 1;
+  __IO uint32_t RTO02E0    : 1;
+  __IO uint32_t RTO02E1    : 1;
+  __IO uint32_t RTO03E0    : 1;
+  __IO uint32_t RTO03E1    : 1;
+  __IO uint32_t RTO04E0    : 1;
+  __IO uint32_t RTO04E1    : 1;
+  __IO uint32_t RTO05E0    : 1;
+  __IO uint32_t RTO05E1    : 1;
+  __IO uint32_t DTTI0C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI0S0    : 1;
+  __IO uint32_t DTTI0S1    : 1;
+  __IO uint32_t FRCK0S0    : 1;
+  __IO uint32_t FRCK0S1    : 1;
+  __IO uint32_t IC00S0     : 1;
+  __IO uint32_t IC00S1     : 1;
+  __IO uint32_t IC00S2     : 1;
+  __IO uint32_t IC01S0     : 1;
+  __IO uint32_t IC01S1     : 1;
+  __IO uint32_t IC01S2     : 1;
+  __IO uint32_t IC02S0     : 1;
+  __IO uint32_t IC02S1     : 1;
+  __IO uint32_t IC02S2     : 1;
+  __IO uint32_t IC03S0     : 1;
+  __IO uint32_t IC03S1     : 1;
+  __IO uint32_t IC03S2     : 1;
+} stc_gpio_epfr01_field_t;
+
+typedef struct stc_gpio_epfr02_field
+{
+  __IO uint32_t RTO10E0    : 1;
+  __IO uint32_t RTO10E1    : 1;
+  __IO uint32_t RTO11E0    : 1;
+  __IO uint32_t RTO11E1    : 1;
+  __IO uint32_t RTO12E0    : 1;
+  __IO uint32_t RTO12E1    : 1;
+  __IO uint32_t RTO13E0    : 1;
+  __IO uint32_t RTO13E1    : 1;
+  __IO uint32_t RTO14E0    : 1;
+  __IO uint32_t RTO14E1    : 1;
+  __IO uint32_t RTO15E0    : 1;
+  __IO uint32_t RTO15E1    : 1;
+  __IO uint32_t DTTI1C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI1S0    : 1;
+  __IO uint32_t DTTI1S1    : 1;
+  __IO uint32_t FRCK1S0    : 1;
+  __IO uint32_t FRCK1S1    : 1;
+  __IO uint32_t IC10S0     : 1;
+  __IO uint32_t IC10S1     : 1;
+  __IO uint32_t IC10S2     : 1;
+  __IO uint32_t IC11S0     : 1;
+  __IO uint32_t IC11S1     : 1;
+  __IO uint32_t IC11S2     : 1;
+  __IO uint32_t IC12S0     : 1;
+  __IO uint32_t IC12S1     : 1;
+  __IO uint32_t IC12S2     : 1;
+  __IO uint32_t IC13S0     : 1;
+  __IO uint32_t IC13S1     : 1;
+  __IO uint32_t IC13S2     : 1;
+} stc_gpio_epfr02_field_t;
+
+typedef struct stc_gpio_epfr03_field
+{
+  __IO uint32_t RTO20E0    : 1;
+  __IO uint32_t RTO20E1    : 1;
+  __IO uint32_t RTO21E0    : 1;
+  __IO uint32_t RTO21E1    : 1;
+  __IO uint32_t RTO22E0    : 1;
+  __IO uint32_t RTO22E1    : 1;
+  __IO uint32_t RTO23E0    : 1;
+  __IO uint32_t RTO23E1    : 1;
+  __IO uint32_t RTO24E0    : 1;
+  __IO uint32_t RTO24E1    : 1;
+  __IO uint32_t RTO25E0    : 1;
+  __IO uint32_t RTO25E1    : 1;
+  __IO uint32_t DTTI2C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI2S0    : 1;
+  __IO uint32_t DTTI2S1    : 1;
+  __IO uint32_t FRCK2S0    : 1;
+  __IO uint32_t FRCK2S1    : 1;
+  __IO uint32_t IC20S0     : 1;
+  __IO uint32_t IC20S1     : 1;
+  __IO uint32_t IC20S2     : 1;
+  __IO uint32_t IC21S0     : 1;
+  __IO uint32_t IC21S1     : 1;
+  __IO uint32_t IC21S2     : 1;
+  __IO uint32_t IC22S0     : 1;
+  __IO uint32_t IC22S1     : 1;
+  __IO uint32_t IC22S2     : 1;
+  __IO uint32_t IC23S0     : 1;
+  __IO uint32_t IC23S1     : 1;
+  __IO uint32_t IC23S2     : 1;
+} stc_gpio_epfr03_field_t;
+
+typedef struct stc_gpio_epfr04_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA0E0    : 1;
+  __IO uint32_t TIOA0E1    : 1;
+  __IO uint32_t TIOB0S0    : 1;
+  __IO uint32_t TIOB0S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA1S0    : 1;
+  __IO uint32_t TIOA1S1    : 1;
+  __IO uint32_t TIOA1E0    : 1;
+  __IO uint32_t TIOA1E1    : 1;
+  __IO uint32_t TIOB1S0    : 1;
+  __IO uint32_t TIOB1S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA2E0    : 1;
+  __IO uint32_t TIOA2E1    : 1;
+  __IO uint32_t TIOB2S0    : 1;
+  __IO uint32_t TIOB2S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA3S0    : 1;
+  __IO uint32_t TIOA3S1    : 1;
+  __IO uint32_t TIOA3E0    : 1;
+  __IO uint32_t TIOA3E1    : 1;
+  __IO uint32_t TIOB3S0    : 1;
+  __IO uint32_t TIOB3S1    : 1;
+} stc_gpio_epfr04_field_t;
+
+typedef struct stc_gpio_epfr05_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA4E0    : 1;
+  __IO uint32_t TIOA4E1    : 1;
+  __IO uint32_t TIOB4S0    : 1;
+  __IO uint32_t TIOB4S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA5S0    : 1;
+  __IO uint32_t TIOA5S1    : 1;
+  __IO uint32_t TIOA5E0    : 1;
+  __IO uint32_t TIOA5E1    : 1;
+  __IO uint32_t TIOB5S0    : 1;
+  __IO uint32_t TIOB5S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA6E0    : 1;
+  __IO uint32_t TIOA6E1    : 1;
+  __IO uint32_t TIOB6S0    : 1;
+  __IO uint32_t TIOB6S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA7S0    : 1;
+  __IO uint32_t TIOA7S1    : 1;
+  __IO uint32_t TIOA7E0    : 1;
+  __IO uint32_t TIOA7E1    : 1;
+  __IO uint32_t TIOB7S0    : 1;
+  __IO uint32_t TIOB7S1    : 1;
+} stc_gpio_epfr05_field_t;
+
+typedef struct stc_gpio_epfr06_field
+{
+  __IO uint32_t EINT00S0   : 1;
+  __IO uint32_t EINT00S1   : 1;
+  __IO uint32_t EINT01S0   : 1;
+  __IO uint32_t EINT01S1   : 1;
+  __IO uint32_t EINT02S0   : 1;
+  __IO uint32_t EINT02S1   : 1;
+  __IO uint32_t EINT03S0   : 1;
+  __IO uint32_t EINT03S1   : 1;
+  __IO uint32_t EINT04S0   : 1;
+  __IO uint32_t EINT04S1   : 1;
+  __IO uint32_t EINT05S0   : 1;
+  __IO uint32_t EINT05S1   : 1;
+  __IO uint32_t EINT06S0   : 1;
+  __IO uint32_t EINT06S1   : 1;
+  __IO uint32_t EINT07S0   : 1;
+  __IO uint32_t EINT07S1   : 1;
+  __IO uint32_t EINT08S0   : 1;
+  __IO uint32_t EINT08S1   : 1;
+  __IO uint32_t EINT09S0   : 1;
+  __IO uint32_t EINT09S1   : 1;
+  __IO uint32_t EINT10S0   : 1;
+  __IO uint32_t EINT10S1   : 1;
+  __IO uint32_t EINT11S0   : 1;
+  __IO uint32_t EINT11S1   : 1;
+  __IO uint32_t EINT12S0   : 1;
+  __IO uint32_t EINT12S1   : 1;
+  __IO uint32_t EINT13S0   : 1;
+  __IO uint32_t EINT13S1   : 1;
+  __IO uint32_t EINT14S0   : 1;
+  __IO uint32_t EINT14S1   : 1;
+  __IO uint32_t EINT15S0   : 1;
+  __IO uint32_t EINT15S1   : 1;
+} stc_gpio_epfr06_field_t;
+
+typedef struct stc_gpio_epfr07_field
+{
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t SIN0S0     : 1;
+  __IO uint32_t SIN0S1     : 1;
+  __IO uint32_t SOT0B0     : 1;
+  __IO uint32_t SOT0B1     : 1;
+  __IO uint32_t SCK0B0     : 1;
+  __IO uint32_t SCK0B1     : 1;
+  __IO uint32_t SIN1S0     : 1;
+  __IO uint32_t SIN1S1     : 1;
+  __IO uint32_t SOT1B0     : 1;
+  __IO uint32_t SOT1B1     : 1;
+  __IO uint32_t SCK1B0     : 1;
+  __IO uint32_t SCK1B1     : 1;
+  __IO uint32_t SIN2S0     : 1;
+  __IO uint32_t SIN2S1     : 1;
+  __IO uint32_t SOT2B0     : 1;
+  __IO uint32_t SOT2B1     : 1;
+  __IO uint32_t SCK2B0     : 1;
+  __IO uint32_t SCK2B1     : 1;
+  __IO uint32_t SIN3S0     : 1;
+  __IO uint32_t SIN3S1     : 1;
+  __IO uint32_t SOT3B0     : 1;
+  __IO uint32_t SOT3B1     : 1;
+  __IO uint32_t SCK3B0     : 1;
+  __IO uint32_t SCK3B1     : 1;
+} stc_gpio_epfr07_field_t;
+
+typedef struct stc_gpio_epfr08_field
+{
+  __IO uint32_t RTS4E0     : 1;
+  __IO uint32_t RTS4E1     : 1;
+  __IO uint32_t CTS4S0     : 1;
+  __IO uint32_t CTS4S1     : 1;
+  __IO uint32_t SIN4S0     : 1;
+  __IO uint32_t SIN4S1     : 1;
+  __IO uint32_t SOT4B0     : 1;
+  __IO uint32_t SOT4B1     : 1;
+  __IO uint32_t SCK4B0     : 1;
+  __IO uint32_t SCK4B1     : 1;
+  __IO uint32_t SIN5S0     : 1;
+  __IO uint32_t SIN5S1     : 1;
+  __IO uint32_t SOT5B0     : 1;
+  __IO uint32_t SOT5B1     : 1;
+  __IO uint32_t SCK5B0     : 1;
+  __IO uint32_t SCK5B1     : 1;
+  __IO uint32_t SIN6S0     : 1;
+  __IO uint32_t SIN6S1     : 1;
+  __IO uint32_t SOT6B0     : 1;
+  __IO uint32_t SOT6B1     : 1;
+  __IO uint32_t SCK6B0     : 1;
+  __IO uint32_t SCK6B1     : 1;
+  __IO uint32_t SIN7S0     : 1;
+  __IO uint32_t SIN7S1     : 1;
+  __IO uint32_t SOT7B0     : 1;
+  __IO uint32_t SOT7B1     : 1;
+  __IO uint32_t SCK7B0     : 1;
+  __IO uint32_t SCK7B1     : 1;
+} stc_gpio_epfr08_field_t;
+
+typedef struct stc_gpio_epfr09_field
+{
+  __IO uint32_t QAIN0S0    : 1;
+  __IO uint32_t QAIN0S1    : 1;
+  __IO uint32_t QBIN0S0    : 1;
+  __IO uint32_t QBIN0S1    : 1;
+  __IO uint32_t QZIN0S0    : 1;
+  __IO uint32_t QZIN0S1    : 1;
+  __IO uint32_t QAIN1S0    : 1;
+  __IO uint32_t QAIN1S1    : 1;
+  __IO uint32_t QBIN1S0    : 1;
+  __IO uint32_t QBIN1S1    : 1;
+  __IO uint32_t QZIN1S0    : 1;
+  __IO uint32_t QZIN1S1    : 1;
+  __IO uint32_t ADTRG0S0   : 1;
+  __IO uint32_t ADTRG0S1   : 1;
+  __IO uint32_t ADTRG0S2   : 1;
+  __IO uint32_t ADTRG0S3   : 1;
+  __IO uint32_t ADTRG1S0   : 1;
+  __IO uint32_t ADTRG1S1   : 1;
+  __IO uint32_t ADTRG1S2   : 1;
+  __IO uint32_t ADTRG1S3   : 1;
+  __IO uint32_t ADTRG2S0   : 1;
+  __IO uint32_t ADTRG2S1   : 1;
+  __IO uint32_t ADTRG2S2   : 1;
+  __IO uint32_t ADTRG2S3   : 1;
+} stc_gpio_epfr09_field_t;
+
+typedef struct stc_gpio_epfr10_field
+{
+  __IO uint32_t UEDEFB     : 1;
+  __IO uint32_t UEDTHB     : 1;
+  __IO uint32_t UECLKE     : 1;
+  __IO uint32_t UEWEXE     : 1;
+  __IO uint32_t UEDQME     : 1;
+  __IO uint32_t UEOEXE     : 1;
+  __IO uint32_t UEFLSE     : 1;
+  __IO uint32_t UECS1E     : 1;
+  __IO uint32_t UECS2E     : 1;
+  __IO uint32_t UECS3E     : 1;
+  __IO uint32_t UECS4E     : 1;
+  __IO uint32_t UECS5E     : 1;
+  __IO uint32_t UECS6E     : 1;
+  __IO uint32_t UECS7E     : 1;
+  __IO uint32_t UEAOOE     : 1;
+  __IO uint32_t UEA08E     : 1;
+  __IO uint32_t UEA09E     : 1;
+  __IO uint32_t UEA10E     : 1;
+  __IO uint32_t UEA11E     : 1;
+  __IO uint32_t UEA12E     : 1;
+  __IO uint32_t UEA13E     : 1;
+  __IO uint32_t UEA14E     : 1;
+  __IO uint32_t UEA15E     : 1;
+  __IO uint32_t UEA16E     : 1;
+  __IO uint32_t UEA17E     : 1;
+  __IO uint32_t UEA18E     : 1;
+} stc_gpio_epfr10_field_t;
+
+typedef struct stc_gpio_epfr11_field
+{
+  __IO uint32_t UEALEE     : 1;
+  __IO uint32_t UECS0E     : 1;
+  __IO uint32_t UEA01E     : 1;
+  __IO uint32_t UEA02E     : 1;
+  __IO uint32_t UEA03E     : 1;
+  __IO uint32_t UEA04E     : 1;
+  __IO uint32_t UEA05E     : 1;
+  __IO uint32_t UEA06E     : 1;
+  __IO uint32_t UEA07E     : 1;
+  __IO uint32_t UED00B     : 1;
+  __IO uint32_t UED01B     : 1;
+  __IO uint32_t UED02B     : 1;
+  __IO uint32_t UED03B     : 1;
+  __IO uint32_t UED04B     : 1;
+  __IO uint32_t UED05B     : 1;
+  __IO uint32_t UED06B     : 1;
+  __IO uint32_t UED07B     : 1;
+  __IO uint32_t UED08B     : 1;
+  __IO uint32_t UED09B     : 1;
+  __IO uint32_t UED10B     : 1;
+  __IO uint32_t UED11B     : 1;
+  __IO uint32_t UED12B     : 1;
+  __IO uint32_t UED13B     : 1;
+  __IO uint32_t UED14B     : 1;
+  __IO uint32_t UED15B     : 1;
+  __IO uint32_t UERLC      : 1;
+} stc_gpio_epfr11_field_t;
+
+typedef struct stc_gpio_epfr12_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA8E0    : 1;
+  __IO uint32_t TIOA8E1    : 1;
+  __IO uint32_t TIOB8S0    : 1;
+  __IO uint32_t TIOB8S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA9S0    : 1;
+  __IO uint32_t TIOA9S1    : 1;
+  __IO uint32_t TIOA9E0    : 1;
+  __IO uint32_t TIOA9E1    : 1;
+  __IO uint32_t TIOB9S0    : 1;
+  __IO uint32_t TIOB9S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA10E0   : 1;
+  __IO uint32_t TIOA10E1   : 1;
+  __IO uint32_t TIOB10S0   : 1;
+  __IO uint32_t TIOB10S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA11S0   : 1;
+  __IO uint32_t TIOA11S1   : 1;
+  __IO uint32_t TIOA11E0   : 1;
+  __IO uint32_t TIOA11E1   : 1;
+  __IO uint32_t TIOB11S0   : 1;
+  __IO uint32_t TIOB11S1   : 1;
+} stc_gpio_epfr12_field_t;
+
+typedef struct stc_gpio_epfr13_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA12E0   : 1;
+  __IO uint32_t TIOA12E1   : 1;
+  __IO uint32_t TIOB12S0   : 1;
+  __IO uint32_t TIOB12S1   : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA13S0   : 1;
+  __IO uint32_t TIOA13S1   : 1;
+  __IO uint32_t TIOA13E0   : 1;
+  __IO uint32_t TIOA13E1   : 1;
+  __IO uint32_t TIOB13S0   : 1;
+  __IO uint32_t TIOB13S1   : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA14E0   : 1;
+  __IO uint32_t TIOA14E1   : 1;
+  __IO uint32_t TIOB14S0   : 1;
+  __IO uint32_t TIOB14S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA15S0   : 1;
+  __IO uint32_t TIOA15S1   : 1;
+  __IO uint32_t TIOA15E0   : 1;
+  __IO uint32_t TIOA15E1   : 1;
+  __IO uint32_t TIOB15S0   : 1;
+  __IO uint32_t TIOB15S1   : 1;
+} stc_gpio_epfr13_field_t;
+
+typedef struct stc_gpio_epfr14_field
+{
+  __IO uint32_t QAIN2S0    : 1;
+  __IO uint32_t QAIN2S1    : 1;
+  __IO uint32_t QBIN2S0    : 1;
+  __IO uint32_t QBIN2S1    : 1;
+  __IO uint32_t QZIN2S0    : 1;
+  __IO uint32_t QZIN2S1    : 1;
+       uint32_t RESERVED1  : 12;
+  __IO uint32_t E_TD0E     : 1;
+  __IO uint32_t E_TD1E     : 1;
+  __IO uint32_t E_TE0E     : 1;
+  __IO uint32_t E_TE1E     : 1;
+  __IO uint32_t E_MC0E     : 1;
+  __IO uint32_t E_MC1B     : 1;
+  __IO uint32_t E_MD0B     : 1;
+  __IO uint32_t E_MD1B     : 1;
+  __IO uint32_t E_CKE      : 1;
+  __IO uint32_t E_PSE      : 1;
+  __IO uint32_t E_SPLC0    : 1;
+  __IO uint32_t E_SPLC1    : 1;
+} stc_gpio_epfr14_field_t;
+
+typedef struct stc_gpio_epfr15_field
+{
+  __IO uint32_t EINT16S0   : 1;
+  __IO uint32_t EINT16S1   : 1;
+  __IO uint32_t EINT17S0   : 1;
+  __IO uint32_t EINT17S1   : 1;
+  __IO uint32_t EINT18S0   : 1;
+  __IO uint32_t EINT18S1   : 1;
+  __IO uint32_t EINT19S0   : 1;
+  __IO uint32_t EINT19S1   : 1;
+  __IO uint32_t EINT20S0   : 1;
+  __IO uint32_t EINT20S1   : 1;
+  __IO uint32_t EINT21S0   : 1;
+  __IO uint32_t EINT21S1   : 1;
+  __IO uint32_t EINT22S0   : 1;
+  __IO uint32_t EINT22S1   : 1;
+  __IO uint32_t EINT23S0   : 1;
+  __IO uint32_t EINT23S1   : 1;
+  __IO uint32_t EINT24S0   : 1;
+  __IO uint32_t EINT24S1   : 1;
+  __IO uint32_t EINT25S0   : 1;
+  __IO uint32_t EINT25S1   : 1;
+  __IO uint32_t EINT26S0   : 1;
+  __IO uint32_t EINT26S1   : 1;
+  __IO uint32_t EINT27S0   : 1;
+  __IO uint32_t EINT27S1   : 1;
+  __IO uint32_t EINT28S0   : 1;
+  __IO uint32_t EINT28S1   : 1;
+  __IO uint32_t EINT29S0   : 1;
+  __IO uint32_t EINT29S1   : 1;
+  __IO uint32_t EINT30S0   : 1;
+  __IO uint32_t EINT30S1   : 1;
+  __IO uint32_t EINT31S0   : 1;
+  __IO uint32_t EINT31S1   : 1;
+} stc_gpio_epfr15_field_t;
+
+typedef struct stc_gpio_pzr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr0_field_t;
+
+typedef struct stc_gpio_pzr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr1_field_t;
+
+typedef struct stc_gpio_pzr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr2_field_t;
+
+typedef struct stc_gpio_pzr3_field
+{
+       uint32_t RESERVED1  : 6;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr3_field_t;
+
+typedef struct stc_gpio_pzr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pzr4_field_t;
+
+typedef struct stc_gpio_pzr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+} stc_gpio_pzr5_field_t;
+
+typedef struct stc_gpio_pzr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pzr6_field_t;
+
+typedef struct stc_gpio_pzr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+} stc_gpio_pzr7_field_t;
+
+typedef struct stc_gpio_pzr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzr8_field_t;
+
+typedef struct stc_gpio_pzra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pzra_field_t;
+
+typedef struct stc_gpio_pzrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzrc_field_t;
+
+typedef struct stc_gpio_pzrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzrd_field_t;
+
+typedef struct stc_gpio_pzre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzre_field_t;
+
+typedef struct stc_gpio_pzrf_field
+{
+       uint32_t RESERVED1  : 5;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pzrf_field_t;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* LVD_MODULE register bit fields */
+typedef struct stc_lvd_lvd_ctl_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SVHI0      : 1;
+  __IO  uint8_t SVHI1      : 1;
+  __IO  uint8_t SVHI2      : 1;
+  __IO  uint8_t SVHI3      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t LVDIE      : 1;
+} stc_lvd_lvd_ctl_field_t;
+
+typedef struct stc_lvd_lvd_str_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIR      : 1;
+} stc_lvd_lvd_str_field_t;
+
+typedef struct stc_lvd_lvd_clr_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDCL      : 1;
+} stc_lvd_lvd_clr_field_t;
+
+typedef struct stc_lvd_lvd_str2_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIRDY    : 1;
+} stc_lvd_lvd_str2_field_t;
+
+/******************************************************************************
+ * USB Ethernet CLK
+ ******************************************************************************/
+/* USB ETHERNET CLK register bit fields */
+typedef struct stc_usbethernetclk_uccr_field
+{
+  __IO  uint8_t UCEN0      : 1;
+  __IO  uint8_t UCSEL0     : 1;
+  __IO  uint8_t UCSEL1     : 1;
+  __IO  uint8_t UCEN1      : 1;
+  __IO  uint8_t ECEN       : 1;
+  __IO  uint8_t ECSEL0     : 1;
+  __IO  uint8_t ECSEL1     : 1;
+} stc_usbethernetclk_uccr_field_t;
+
+typedef struct stc_usbethernetclk_upcr1_field
+{
+  __IO  uint8_t UPLLEN     : 1;
+  __IO  uint8_t UPINC      : 1;
+} stc_usbethernetclk_upcr1_field_t;
+
+typedef struct stc_usbethernetclk_upcr2_field
+{
+  __IO  uint8_t UPOWT0     : 1;
+  __IO  uint8_t UPOWT1     : 1;
+  __IO  uint8_t UPOWT2     : 1;
+} stc_usbethernetclk_upcr2_field_t;
+
+typedef struct stc_usbethernetclk_upcr3_field
+{
+  __IO  uint8_t UPLLK0     : 1;
+  __IO  uint8_t UPLLK1     : 1;
+  __IO  uint8_t UPLLK2     : 1;
+  __IO  uint8_t UPLLK3     : 1;
+  __IO  uint8_t UPLLK4     : 1;
+} stc_usbethernetclk_upcr3_field_t;
+
+typedef struct stc_usbethernetclk_upcr4_field
+{
+  __IO  uint8_t UPLLN0     : 1;
+  __IO  uint8_t UPLLN1     : 1;
+  __IO  uint8_t UPLLN2     : 1;
+  __IO  uint8_t UPLLN3     : 1;
+  __IO  uint8_t UPLLN4     : 1;
+  __IO  uint8_t UPLLN5     : 1;
+  __IO  uint8_t UPLLN6     : 1;
+} stc_usbethernetclk_upcr4_field_t;
+
+typedef struct stc_usbethernetclk_up_str_field
+{
+  __IO  uint8_t UPRDY      : 1;
+} stc_usbethernetclk_up_str_field_t;
+
+typedef struct stc_usbethernetclk_upint_enr_field
+{
+  __IO  uint8_t UPCSE      : 1;
+} stc_usbethernetclk_upint_enr_field_t;
+
+typedef struct stc_usbethernetclk_upint_clr_field
+{
+  __IO  uint8_t UPCSC      : 1;
+} stc_usbethernetclk_upint_clr_field_t;
+
+typedef struct stc_usbethernetclk_upint_str_field
+{
+  __IO  uint8_t UPCSI      : 1;
+} stc_usbethernetclk_upint_str_field_t;
+
+typedef struct stc_usbethernetclk_upcr5_field
+{
+  __IO  uint8_t UPLLM0     : 1;
+  __IO  uint8_t UPLLM1     : 1;
+  __IO  uint8_t UPLLM2     : 1;
+  __IO  uint8_t UPLLM3     : 1;
+} stc_usbethernetclk_upcr5_field_t;
+
+typedef struct stc_usbethernetclk_upcr6_field
+{
+  __IO  uint8_t UBSR0      : 1;
+  __IO  uint8_t UBSR1      : 1;
+  __IO  uint8_t UBSR2      : 1;
+  __IO  uint8_t UBSR3      : 1;
+} stc_usbethernetclk_upcr6_field_t;
+
+typedef struct stc_usbethernetclk_upcr7_field
+{
+  __IO  uint8_t EPLLEN     : 1;
+} stc_usbethernetclk_upcr7_field_t;
+
+typedef struct stc_usbethernetclk_usben0_field
+{
+  __IO  uint8_t USBEN0     : 1;
+} stc_usbethernetclk_usben0_field_t;
+
+typedef struct stc_usbethernetclk_usben1_field
+{
+  __IO  uint8_t USBEN1     : 1;
+} stc_usbethernetclk_usben1_field_t;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* MFS03_UART_MODULE register bit fields */
+typedef struct stc_mfs03_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_uart_smr_field_t;
+
+typedef struct stc_mfs03_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_uart_scr_field_t;
+
+typedef struct stc_mfs03_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs03_uart_escr_field_t;
+
+typedef struct stc_mfs03_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_uart_ssr_field_t;
+
+typedef struct stc_mfs03_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_rdr_field_t;
+
+typedef struct stc_mfs03_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_tdr_field_t;
+
+typedef struct stc_mfs03_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_uart_bgr_field_t;
+
+typedef struct stc_mfs03_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_uart_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* MFS03_CSIO_MODULE register bit fields */
+typedef struct stc_mfs03_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_csio_smr_field_t;
+
+typedef struct stc_mfs03_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_csio_scr_field_t;
+
+typedef struct stc_mfs03_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs03_csio_escr_field_t;
+
+typedef struct stc_mfs03_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_csio_ssr_field_t;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* MFS03_LIN_MODULE register bit fields */
+typedef struct stc_mfs03_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_lin_smr_field_t;
+
+typedef struct stc_mfs03_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_lin_scr_field_t;
+
+typedef struct stc_mfs03_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs03_lin_escr_field_t;
+
+typedef struct stc_mfs03_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_lin_ssr_field_t;
+
+typedef struct stc_mfs03_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_lin_bgr_field_t;
+
+typedef struct stc_mfs03_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_lin_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* MFS03_I2C_MODULE register bit fields */
+typedef struct stc_mfs03_i2c_smr_field
+{
+  __IO  uint8_t ITST0      : 1;
+  __IO  uint8_t ITST1      : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs03_i2c_smr_field_t;
+
+typedef struct stc_mfs03_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs03_i2c_ibcr_field_t;
+
+typedef struct stc_mfs03_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs03_i2c_ibsr_field_t;
+
+typedef struct stc_mfs03_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_i2c_ssr_field_t;
+
+typedef struct stc_mfs03_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs03_i2c_isba_field_t;
+
+typedef struct stc_mfs03_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs03_i2c_ismk_field_t;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* MFS47_UART_MODULE register bit fields */
+typedef struct stc_mfs47_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_uart_smr_field_t;
+
+typedef struct stc_mfs47_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_uart_scr_field_t;
+
+typedef struct stc_mfs47_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs47_uart_escr_field_t;
+
+typedef struct stc_mfs47_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_uart_ssr_field_t;
+
+typedef struct stc_mfs47_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_rdr_field_t;
+
+typedef struct stc_mfs47_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_tdr_field_t;
+
+typedef struct stc_mfs47_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_uart_bgr_field_t;
+
+typedef struct stc_mfs47_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_uart_bgr1_field_t;
+
+typedef struct stc_mfs47_uart_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_uart_fcr_field_t;
+
+typedef struct stc_mfs47_uart_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_uart_fcr0_field_t;
+
+typedef struct stc_mfs47_uart_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_uart_fcr1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_uart_fbyte_field_t;
+
+typedef struct stc_mfs47_uart_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_uart_fbyte1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_uart_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* MFS47_CSIO_MODULE register bit fields */
+typedef struct stc_mfs47_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_csio_smr_field_t;
+
+typedef struct stc_mfs47_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_csio_scr_field_t;
+
+typedef struct stc_mfs47_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs47_csio_escr_field_t;
+
+typedef struct stc_mfs47_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_csio_ssr_field_t;
+
+typedef struct stc_mfs47_csio_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_csio_fcr_field_t;
+
+typedef struct stc_mfs47_csio_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_csio_fcr0_field_t;
+
+typedef struct stc_mfs47_csio_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_csio_fcr1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_csio_fbyte_field_t;
+
+typedef struct stc_mfs47_csio_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_csio_fbyte1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_csio_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* MFS47_LIN_MODULE register bit fields */
+typedef struct stc_mfs47_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_lin_smr_field_t;
+
+typedef struct stc_mfs47_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_lin_scr_field_t;
+
+typedef struct stc_mfs47_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs47_lin_escr_field_t;
+
+typedef struct stc_mfs47_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_lin_ssr_field_t;
+
+typedef struct stc_mfs47_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_lin_bgr_field_t;
+
+typedef struct stc_mfs47_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_lin_bgr1_field_t;
+
+typedef struct stc_mfs47_lin_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_lin_fcr_field_t;
+
+typedef struct stc_mfs47_lin_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_lin_fcr0_field_t;
+
+typedef struct stc_mfs47_lin_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_lin_fcr1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_lin_fbyte_field_t;
+
+typedef struct stc_mfs47_lin_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_lin_fbyte1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_lin_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* MFS47_I2C_MODULE register bit fields */
+typedef struct stc_mfs47_i2c_smr_field
+{
+  __IO  uint8_t ITST0      : 1;
+  __IO  uint8_t ITST1      : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD0        : 1;
+  __IO  uint8_t MD1        : 1;
+  __IO  uint8_t MD2        : 1;
+} stc_mfs47_i2c_smr_field_t;
+
+typedef struct stc_mfs47_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs47_i2c_ibcr_field_t;
+
+typedef struct stc_mfs47_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs47_i2c_ibsr_field_t;
+
+typedef struct stc_mfs47_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_i2c_ssr_field_t;
+
+typedef struct stc_mfs47_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs47_i2c_isba_field_t;
+
+typedef struct stc_mfs47_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs47_i2c_ismk_field_t;
+
+typedef struct stc_mfs47_i2c_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_i2c_fcr_field_t;
+
+typedef struct stc_mfs47_i2c_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_i2c_fcr0_field_t;
+
+typedef struct stc_mfs47_i2c_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_i2c_fcr1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_i2c_fbyte_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_i2c_fbyte1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_i2c_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct stc_mfs_nfc_i2cdnf_field
+{
+  __IO uint16_t I2CDNF00   : 1;
+  __IO uint16_t I2CDNF01   : 1;
+  __IO uint16_t I2CDNF10   : 1;
+  __IO uint16_t I2CDNF11   : 1;
+  __IO uint16_t I2CDNF20   : 1;
+  __IO uint16_t I2CDNF21   : 1;
+  __IO uint16_t I2CDNF30   : 1;
+  __IO uint16_t I2CDNF31   : 1;
+  __IO uint16_t I2CDNF40   : 1;
+  __IO uint16_t I2CDNF41   : 1;
+  __IO uint16_t I2CDNF50   : 1;
+  __IO uint16_t I2CDNF51   : 1;
+  __IO uint16_t I2CDNF60   : 1;
+  __IO uint16_t I2CDNF61   : 1;
+  __IO uint16_t I2CDNF70   : 1;
+  __IO uint16_t I2CDNF71   : 1;
+} stc_mfs_nfc_i2cdnf_field_t;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC_MODULE register bit fields */
+typedef struct stc_crc_crccr_field
+{
+  __IO  uint8_t INIT       : 1;
+  __IO  uint8_t CRC32      : 1;
+  __IO  uint8_t LTLEND     : 1;
+  __IO  uint8_t LSBFST     : 1;
+  __IO  uint8_t CRCLTE     : 1;
+  __IO  uint8_t CRCLSF     : 1;
+  __IO  uint8_t FXOR       : 1;
+} stc_crc_crccr_field_t;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* WC_MODULE register bit fields */
+typedef struct stc_wc_wcrd_field
+{
+  __IO  uint8_t CTR0       : 1;
+  __IO  uint8_t CTR1       : 1;
+  __IO  uint8_t CTR2       : 1;
+  __IO  uint8_t CTR3       : 1;
+  __IO  uint8_t CTR4       : 1;
+  __IO  uint8_t CTR5       : 1;
+} stc_wc_wcrd_field_t;
+
+typedef struct stc_wc_wcrl_field
+{
+  __IO  uint8_t RLC0       : 1;
+  __IO  uint8_t RLC1       : 1;
+  __IO  uint8_t RLC2       : 1;
+  __IO  uint8_t RLC3       : 1;
+  __IO  uint8_t RLC4       : 1;
+  __IO  uint8_t RLC5       : 1;
+} stc_wc_wcrl_field_t;
+
+typedef struct stc_wc_wccr_field
+{
+  __IO  uint8_t WCIF       : 1;
+  __IO  uint8_t WCIE       : 1;
+  __IO  uint8_t CS0        : 1;
+  __IO  uint8_t CS1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t WCOP       : 1;
+  __IO  uint8_t WCEN       : 1;
+} stc_wc_wccr_field_t;
+
+typedef struct stc_wc_clk_sel_field
+{
+  __IO uint16_t SEL_IN     : 1;
+       uint16_t RESERVED1  : 7;
+  __IO uint16_t SEL_OUT    : 1;
+} stc_wc_clk_sel_field_t;
+
+typedef struct stc_wc_clk_en_field
+{
+  __IO  uint8_t CLK_EN     : 1;
+  __IO  uint8_t CLK_EN_R   : 1;
+} stc_wc_clk_en_field_t;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* EXBUS_MODULE register bit fields */
+typedef struct stc_exbus_mode0_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode0_field_t;
+
+typedef struct stc_exbus_mode1_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode1_field_t;
+
+typedef struct stc_exbus_mode2_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode2_field_t;
+
+typedef struct stc_exbus_mode3_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode3_field_t;
+
+typedef struct stc_exbus_mode4_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode4_field_t;
+
+typedef struct stc_exbus_mode5_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode5_field_t;
+
+typedef struct stc_exbus_mode6_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode6_field_t;
+
+typedef struct stc_exbus_mode7_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode7_field_t;
+
+typedef struct stc_exbus_tim0_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim0_field_t;
+
+typedef struct stc_exbus_tim1_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim1_field_t;
+
+typedef struct stc_exbus_tim2_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim2_field_t;
+
+typedef struct stc_exbus_tim3_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim3_field_t;
+
+typedef struct stc_exbus_tim4_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim4_field_t;
+
+typedef struct stc_exbus_tim5_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim5_field_t;
+
+typedef struct stc_exbus_tim6_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim6_field_t;
+
+typedef struct stc_exbus_tim7_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim7_field_t;
+
+typedef struct stc_exbus_area0_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area0_field_t;
+
+typedef struct stc_exbus_area1_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area1_field_t;
+
+typedef struct stc_exbus_area2_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area2_field_t;
+
+typedef struct stc_exbus_area3_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area3_field_t;
+
+typedef struct stc_exbus_area4_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area4_field_t;
+
+typedef struct stc_exbus_area5_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area5_field_t;
+
+typedef struct stc_exbus_area6_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area6_field_t;
+
+typedef struct stc_exbus_area7_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area7_field_t;
+
+typedef struct stc_exbus_atim0_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim0_field_t;
+
+typedef struct stc_exbus_atim1_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim1_field_t;
+
+typedef struct stc_exbus_atim2_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim2_field_t;
+
+typedef struct stc_exbus_atim3_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim3_field_t;
+
+typedef struct stc_exbus_atim4_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim4_field_t;
+
+typedef struct stc_exbus_atim5_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim5_field_t;
+
+typedef struct stc_exbus_atim6_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim6_field_t;
+
+typedef struct stc_exbus_atim7_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim7_field_t;
+
+typedef struct stc_exbus_dclkr_field
+{
+  __IO  uint8_t MDIV0      : 1;
+  __IO  uint8_t MDIV1      : 1;
+  __IO  uint8_t MDIV2      : 1;
+  __IO  uint8_t MDIV3      : 1;
+  __IO  uint8_t MCLKON     : 1;
+} stc_exbus_dclkr_field_t;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB_MODULE register bit fields */
+typedef struct stc_usb_hcnt_field
+{
+  __IO uint16_t HOST       : 1;
+  __IO uint16_t URST       : 1;
+  __IO uint16_t SOFIRE     : 1;
+  __IO uint16_t DIRE       : 1;
+  __IO uint16_t CNNIRE     : 1;
+  __IO uint16_t CMPIRE     : 1;
+  __IO uint16_t URIRE      : 1;
+  __IO uint16_t RWKIRE     : 1;
+  __IO uint16_t RETRY      : 1;
+  __IO uint16_t CANCEL     : 1;
+  __IO uint16_t SOFSTEP    : 1;
+} stc_usb_hcnt_field_t;
+
+typedef struct stc_usb_hcnt0_field
+{
+  __IO  uint8_t HOST       : 1;
+  __IO  uint8_t URST       : 1;
+  __IO  uint8_t SOFIRE     : 1;
+  __IO  uint8_t DIRE       : 1;
+  __IO  uint8_t CNNIRE     : 1;
+  __IO  uint8_t CMPIRE     : 1;
+  __IO  uint8_t URIRE      : 1;
+  __IO  uint8_t RWKIRE     : 1;
+} stc_usb_hcnt0_field_t;
+
+typedef struct stc_usb_hcnt1_field
+{
+  __IO  uint8_t RETRY      : 1;
+  __IO  uint8_t CANCEL     : 1;
+  __IO  uint8_t SOFSTEP    : 1;
+} stc_usb_hcnt1_field_t;
+
+typedef struct stc_usb_hirq_field
+{
+  __IO  uint8_t SOFIRQ     : 1;
+  __IO  uint8_t DIRQ       : 1;
+  __IO  uint8_t CNNIRQ     : 1;
+  __IO  uint8_t CMPIRQ     : 1;
+  __IO  uint8_t URIRQ      : 1;
+  __IO  uint8_t RWKIRQ     : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TCAN       : 1;
+} stc_usb_hirq_field_t;
+
+typedef struct stc_usb_herr_field
+{
+  __IO  uint8_t HS0        : 1;
+  __IO  uint8_t HS1        : 1;
+  __IO  uint8_t STUFF      : 1;
+  __IO  uint8_t TGERR      : 1;
+  __IO  uint8_t CRC        : 1;
+  __IO  uint8_t TOUT       : 1;
+  __IO  uint8_t RERR       : 1;
+  __IO  uint8_t LSTOF      : 1;
+} stc_usb_herr_field_t;
+
+typedef struct stc_usb_hstate_field
+{
+  __IO  uint8_t CSTAT      : 1;
+  __IO  uint8_t TMODE      : 1;
+  __IO  uint8_t SUSP       : 1;
+  __IO  uint8_t SOFBUSY    : 1;
+  __IO  uint8_t CLKSEL     : 1;
+  __IO  uint8_t ALIVE      : 1;
+} stc_usb_hstate_field_t;
+
+typedef struct stc_usb_hfcomp_field
+{
+  __IO  uint8_t FRAMECOMP0 : 1;
+  __IO  uint8_t FRAMECOMP1 : 1;
+  __IO  uint8_t FRAMECOMP2 : 1;
+  __IO  uint8_t FRAMECOMP3 : 1;
+  __IO  uint8_t FRAMECOMP4 : 1;
+  __IO  uint8_t FRAMECOMP5 : 1;
+  __IO  uint8_t FRAMECOMP6 : 1;
+  __IO  uint8_t FRAMECOMP7 : 1;
+} stc_usb_hfcomp_field_t;
+
+typedef struct stc_usb_hrtimer_field
+{
+  __IO uint16_t RTIMER0    : 1;
+  __IO uint16_t RTIMER1    : 1;
+  __IO uint16_t RTIMER2    : 1;
+  __IO uint16_t RTIMER3    : 1;
+  __IO uint16_t RTIMER4    : 1;
+  __IO uint16_t RTIMER5    : 1;
+  __IO uint16_t RTIMER6    : 1;
+  __IO uint16_t RTIMER7    : 1;
+  __IO uint16_t RTIMER8    : 1;
+  __IO uint16_t RTIMER9    : 1;
+  __IO uint16_t RTIMER10   : 1;
+  __IO uint16_t RTIMER11   : 1;
+  __IO uint16_t RTIMER12   : 1;
+  __IO uint16_t RTIMER13   : 1;
+  __IO uint16_t RTIMER14   : 1;
+  __IO uint16_t RTIMER15   : 1;
+} stc_usb_hrtimer_field_t;
+
+typedef struct stc_usb_hrtimer0_field
+{
+  __IO  uint8_t RTIMER00   : 1;
+  __IO  uint8_t RTIMER01   : 1;
+  __IO  uint8_t RTIMER02   : 1;
+  __IO  uint8_t RTIMER03   : 1;
+  __IO  uint8_t RTIMER04   : 1;
+  __IO  uint8_t RTIMER05   : 1;
+  __IO  uint8_t RTIMER06   : 1;
+  __IO  uint8_t RTIMER07   : 1;
+} stc_usb_hrtimer0_field_t;
+
+typedef struct stc_usb_hrtimer1_field
+{
+  __IO  uint8_t RTIMER10   : 1;
+  __IO  uint8_t RTIMER11   : 1;
+  __IO  uint8_t RTIMER12   : 1;
+  __IO  uint8_t RTIMER13   : 1;
+  __IO  uint8_t RTIMER14   : 1;
+  __IO  uint8_t RTIMER15   : 1;
+  __IO  uint8_t RTIMER16   : 1;
+  __IO  uint8_t RTIMER17   : 1;
+} stc_usb_hrtimer1_field_t;
+
+typedef struct stc_usb_hrtimer2_field
+{
+  __IO  uint8_t RTIMER20   : 1;
+  __IO  uint8_t RTIMER21   : 1;
+  __IO  uint8_t RTIMER22   : 1;
+} stc_usb_hrtimer2_field_t;
+
+typedef struct stc_usb_hadr_field
+{
+  __IO  uint8_t ADDRESS0   : 1;
+  __IO  uint8_t ADDRESS1   : 1;
+  __IO  uint8_t ADDRESS2   : 1;
+  __IO  uint8_t ADDRESS3   : 1;
+  __IO  uint8_t ADDRESS4   : 1;
+  __IO  uint8_t ADDRESS5   : 1;
+  __IO  uint8_t ADDRESS6   : 1;
+} stc_usb_hadr_field_t;
+
+typedef struct stc_usb_heof_field
+{
+  __IO uint16_t EOF0       : 1;
+  __IO uint16_t EOF1       : 1;
+  __IO uint16_t EOF2       : 1;
+  __IO uint16_t EOF3       : 1;
+  __IO uint16_t EOF4       : 1;
+  __IO uint16_t EOF5       : 1;
+  __IO uint16_t EOF6       : 1;
+  __IO uint16_t EOF7       : 1;
+  __IO uint16_t EOF8       : 1;
+  __IO uint16_t EOF9       : 1;
+  __IO uint16_t EOF10      : 1;
+  __IO uint16_t EOF11      : 1;
+  __IO uint16_t EOF12      : 1;
+  __IO uint16_t EOF13      : 1;
+  __IO uint16_t EOF14      : 1;
+  __IO uint16_t EOF15      : 1;
+} stc_usb_heof_field_t;
+
+typedef struct stc_usb_heof0_field
+{
+  __IO  uint8_t EOF00      : 1;
+  __IO  uint8_t EOF01      : 1;
+  __IO  uint8_t EOF02      : 1;
+  __IO  uint8_t EOF03      : 1;
+  __IO  uint8_t EOF04      : 1;
+  __IO  uint8_t EOF05      : 1;
+  __IO  uint8_t EOF06      : 1;
+  __IO  uint8_t EOF07      : 1;
+} stc_usb_heof0_field_t;
+
+typedef struct stc_usb_heof1_field
+{
+  __IO  uint8_t EOF10      : 1;
+  __IO  uint8_t EOF11      : 1;
+  __IO  uint8_t EOF12      : 1;
+  __IO  uint8_t EOF13      : 1;
+  __IO  uint8_t EOF14      : 1;
+  __IO  uint8_t EOF15      : 1;
+} stc_usb_heof1_field_t;
+
+typedef struct stc_usb_hframe_field
+{
+  __IO uint16_t FRAME0     : 1;
+  __IO uint16_t FRAME1     : 1;
+  __IO uint16_t FRAME2     : 1;
+  __IO uint16_t FRAME3     : 1;
+  __IO uint16_t FRAME4     : 1;
+  __IO uint16_t FRAME5     : 1;
+  __IO uint16_t FRAME6     : 1;
+  __IO uint16_t FRAME7     : 1;
+  __IO uint16_t FRAME8     : 1;
+  __IO uint16_t FRAME9     : 1;
+  __IO uint16_t FRAME10    : 1;
+} stc_usb_hframe_field_t;
+
+typedef struct stc_usb_hframe0_field
+{
+  __IO  uint8_t FRAME00    : 1;
+  __IO  uint8_t FRAME01    : 1;
+  __IO  uint8_t FRAME02    : 1;
+  __IO  uint8_t FRAME03    : 1;
+  __IO  uint8_t FRAME04    : 1;
+  __IO  uint8_t FRAME05    : 1;
+  __IO  uint8_t FRAME06    : 1;
+  __IO  uint8_t FRAME07    : 1;
+} stc_usb_hframe0_field_t;
+
+typedef struct stc_usb_hframe1_field
+{
+  __IO  uint8_t FRAME10    : 1;
+  __IO  uint8_t FRAME11    : 1;
+  __IO  uint8_t FRAME12    : 1;
+  __IO  uint8_t FRAME13    : 1;
+} stc_usb_hframe1_field_t;
+
+typedef struct stc_usb_htoken_field
+{
+  __IO  uint8_t ENDPT0     : 1;
+  __IO  uint8_t ENDPT1     : 1;
+  __IO  uint8_t ENDPT2     : 1;
+  __IO  uint8_t ENDPT3     : 1;
+  __IO  uint8_t TKNEN0     : 1;
+  __IO  uint8_t TKNEN1     : 1;
+  __IO  uint8_t TKNEN2     : 1;
+  __IO  uint8_t TGGL       : 1;
+} stc_usb_htoken_field_t;
+
+typedef struct stc_usb_udcc_field
+{
+  __IO uint16_t PWC        : 1;
+  __IO uint16_t RFBK       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t STALCLREN  : 1;
+  __IO uint16_t USTP       : 1;
+  __IO uint16_t HCONX      : 1;
+  __IO uint16_t RESUM      : 1;
+  __IO uint16_t RST        : 1;
+} stc_usb_udcc_field_t;
+
+typedef struct stc_usb_ep0c_field
+{
+  __IO uint16_t PKS00      : 1;
+  __IO uint16_t PKS01      : 1;
+  __IO uint16_t PKS02      : 1;
+  __IO uint16_t PKS03      : 1;
+  __IO uint16_t PKS04      : 1;
+  __IO uint16_t PKS05      : 1;
+  __IO uint16_t PKS06      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+} stc_usb_ep0c_field_t;
+
+typedef struct stc_usb_ep1c_field
+{
+  __IO uint16_t PKS10      : 1;
+  __IO uint16_t PKS11      : 1;
+  __IO uint16_t PKS12      : 1;
+  __IO uint16_t PKS13      : 1;
+  __IO uint16_t PKS14      : 1;
+  __IO uint16_t PKS15      : 1;
+  __IO uint16_t PKS16      : 1;
+  __IO uint16_t PKS17      : 1;
+  __IO uint16_t PKS18      : 1;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep1c_field_t;
+
+typedef struct stc_usb_ep2c_field
+{
+  __IO uint16_t PKS20      : 1;
+  __IO uint16_t PKS21      : 1;
+  __IO uint16_t PKS22      : 1;
+  __IO uint16_t PKS23      : 1;
+  __IO uint16_t PKS24      : 1;
+  __IO uint16_t PKS25      : 1;
+  __IO uint16_t PKS26      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep2c_field_t;
+
+typedef struct stc_usb_ep3c_field
+{
+  __IO uint16_t PKS30      : 1;
+  __IO uint16_t PKS31      : 1;
+  __IO uint16_t PKS32      : 1;
+  __IO uint16_t PKS33      : 1;
+  __IO uint16_t PKS34      : 1;
+  __IO uint16_t PKS35      : 1;
+  __IO uint16_t PKS36      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep3c_field_t;
+
+typedef struct stc_usb_ep4c_field
+{
+  __IO uint16_t PKS40      : 1;
+  __IO uint16_t PKS41      : 1;
+  __IO uint16_t PKS42      : 1;
+  __IO uint16_t PKS43      : 1;
+  __IO uint16_t PKS44      : 1;
+  __IO uint16_t PKS45      : 1;
+  __IO uint16_t PKS46      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep4c_field_t;
+
+typedef struct stc_usb_ep5c_field
+{
+  __IO uint16_t PKS50      : 1;
+  __IO uint16_t PKS51      : 1;
+  __IO uint16_t PKS52      : 1;
+  __IO uint16_t PKS53      : 1;
+  __IO uint16_t PKS54      : 1;
+  __IO uint16_t PKS55      : 1;
+  __IO uint16_t PKS56      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep5c_field_t;
+
+typedef struct stc_usb_tmsp_field
+{
+  __IO uint16_t TMSP0      : 1;
+  __IO uint16_t TMSP1      : 1;
+  __IO uint16_t TMSP2      : 1;
+  __IO uint16_t TMSP3      : 1;
+  __IO uint16_t TMSP4      : 1;
+  __IO uint16_t TMSP5      : 1;
+  __IO uint16_t TMSP6      : 1;
+  __IO uint16_t TMSP7      : 1;
+  __IO uint16_t TMSP8      : 1;
+  __IO uint16_t TMSP9      : 1;
+  __IO uint16_t TMSP10     : 1;
+} stc_usb_tmsp_field_t;
+
+typedef struct stc_usb_udcs_field
+{
+  __IO  uint8_t CONF       : 1;
+  __IO  uint8_t SETP       : 1;
+  __IO  uint8_t WKUP       : 1;
+  __IO  uint8_t BRST       : 1;
+  __IO  uint8_t SOF        : 1;
+  __IO  uint8_t SUSP       : 1;
+} stc_usb_udcs_field_t;
+
+typedef struct stc_usb_udcie_field
+{
+  __IO  uint8_t CONFIE     : 1;
+  __IO  uint8_t CONFN      : 1;
+  __IO  uint8_t WKUPIE     : 1;
+  __IO  uint8_t BRSTIE     : 1;
+  __IO  uint8_t SOFIE      : 1;
+  __IO  uint8_t SUSPIE     : 1;
+} stc_usb_udcie_field_t;
+
+typedef struct stc_usb_ep0is_field
+{
+       uint16_t RESERVED1  : 10;
+  __IO uint16_t DRQI       : 1;
+       uint16_t RESERVED2  : 3;
+  __IO uint16_t DRQIIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0is_field_t;
+
+typedef struct stc_usb_ep0os_field
+{
+  __IO uint16_t SIZE0      : 1;
+  __IO uint16_t SIZE1      : 1;
+  __IO uint16_t SIZE2      : 1;
+  __IO uint16_t SIZE3      : 1;
+  __IO uint16_t SIZE4      : 1;
+  __IO uint16_t SIZE5      : 1;
+  __IO uint16_t SIZE6      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQO       : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQOIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0os_field_t;
+
+typedef struct stc_usb_ep1s_field
+{
+  __IO uint16_t SIZE10     : 1;
+  __IO uint16_t SIZE11     : 1;
+  __IO uint16_t SIZE12     : 1;
+  __IO uint16_t SIZE13     : 1;
+  __IO uint16_t SIZE14     : 1;
+  __IO uint16_t SIZE15     : 1;
+  __IO uint16_t SIZE16     : 1;
+  __IO uint16_t SIZE17     : 1;
+  __IO uint16_t SIZE18     : 1;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep1s_field_t;
+
+typedef struct stc_usb_ep2s_field
+{
+  __IO uint16_t SIZE20     : 1;
+  __IO uint16_t SIZE21     : 1;
+  __IO uint16_t SIZE22     : 1;
+  __IO uint16_t SIZE23     : 1;
+  __IO uint16_t SIZE24     : 1;
+  __IO uint16_t SIZE25     : 1;
+  __IO uint16_t SIZE26     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep2s_field_t;
+
+typedef struct stc_usb_ep4s_field
+{
+  __IO uint16_t SIZE40     : 1;
+  __IO uint16_t SIZE41     : 1;
+  __IO uint16_t SIZE42     : 1;
+  __IO uint16_t SIZE43     : 1;
+  __IO uint16_t SIZE44     : 1;
+  __IO uint16_t SIZE45     : 1;
+  __IO uint16_t SIZE46     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep4s_field_t;
+
+typedef struct stc_usb_ep5s_field
+{
+  __IO uint16_t SIZE50     : 1;
+  __IO uint16_t SIZE51     : 1;
+  __IO uint16_t SIZE52     : 1;
+  __IO uint16_t SIZE53     : 1;
+  __IO uint16_t SIZE54     : 1;
+  __IO uint16_t SIZE55     : 1;
+  __IO uint16_t SIZE56     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep5s_field_t;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMAC_MODULE register bit fields */
+typedef struct stc_dmac_dmacr_field
+{
+       uint32_t RESERVED1  : 24;
+  __IO uint32_t DH0        : 1;
+  __IO uint32_t DH1        : 1;
+  __IO uint32_t DH2        : 1;
+  __IO uint32_t DH3        : 1;
+  __IO uint32_t PR         : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t DS         : 1;
+  __IO uint32_t DE         : 1;
+} stc_dmac_dmacr_field_t;
+
+typedef struct stc_dmac_dmaca0_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca0_field_t;
+
+typedef struct stc_dmac_dmacb0_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb0_field_t;
+
+typedef struct stc_dmac_dmaca1_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca1_field_t;
+
+typedef struct stc_dmac_dmacb1_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb1_field_t;
+
+typedef struct stc_dmac_dmaca2_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca2_field_t;
+
+typedef struct stc_dmac_dmacb2_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb2_field_t;
+
+typedef struct stc_dmac_dmaca3_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca3_field_t;
+
+typedef struct stc_dmac_dmacb3_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb3_field_t;
+
+typedef struct stc_dmac_dmaca4_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca4_field_t;
+
+typedef struct stc_dmac_dmacb4_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb4_field_t;
+
+typedef struct stc_dmac_dmaca5_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca5_field_t;
+
+typedef struct stc_dmac_dmacb5_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb5_field_t;
+
+typedef struct stc_dmac_dmaca6_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca6_field_t;
+
+typedef struct stc_dmac_dmacb6_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb6_field_t;
+
+typedef struct stc_dmac_dmaca7_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca7_field_t;
+
+typedef struct stc_dmac_dmacb7_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb7_field_t;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET_MAC_MODULE register bit fields */
+typedef struct stc_ethernet_mac_mcr_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t RE         : 1;
+  __IO uint32_t TE         : 1;
+  __IO uint32_t DC         : 1;
+  __IO uint32_t BL0        : 1;
+  __IO uint32_t BL1        : 1;
+  __IO uint32_t ACS        : 1;
+  __IO uint32_t LUD        : 1;
+  __IO uint32_t DR         : 1;
+  __IO uint32_t IPC        : 1;
+  __IO uint32_t DM         : 1;
+  __IO uint32_t LM         : 1;
+  __IO uint32_t DO         : 1;
+  __IO uint32_t FES        : 1;
+  __IO uint32_t PS         : 1;
+  __IO uint32_t DCRS       : 1;
+  __IO uint32_t IFG0       : 1;
+  __IO uint32_t IFG1       : 1;
+  __IO uint32_t IFG2       : 1;
+  __IO uint32_t JE         : 1;
+  __IO uint32_t BE         : 1;
+  __IO uint32_t JD         : 1;
+  __IO uint32_t WD         : 1;
+  __IO uint32_t TC         : 1;
+  __IO uint32_t CST        : 1;
+} stc_ethernet_mac_mcr_field_t;
+
+typedef struct stc_ethernet_mac_mffr_field
+{
+  __IO uint32_t PR         : 1;
+  __IO uint32_t HUC        : 1;
+  __IO uint32_t HMC        : 1;
+  __IO uint32_t DAIF       : 1;
+  __IO uint32_t PM         : 1;
+  __IO uint32_t DB         : 1;
+  __IO uint32_t PCF0       : 1;
+  __IO uint32_t PCF1       : 1;
+  __IO uint32_t SAIF       : 1;
+  __IO uint32_t SAF        : 1;
+  __IO uint32_t HPF        : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t RA         : 1;
+} stc_ethernet_mac_mffr_field_t;
+
+typedef struct stc_ethernet_mac_mhtrh_field
+{
+  __IO uint32_t HTH0       : 1;
+  __IO uint32_t HTH1       : 1;
+  __IO uint32_t HTH2       : 1;
+  __IO uint32_t HTH3       : 1;
+  __IO uint32_t HTH4       : 1;
+  __IO uint32_t HTH5       : 1;
+  __IO uint32_t HTH6       : 1;
+  __IO uint32_t HTH7       : 1;
+  __IO uint32_t HTH8       : 1;
+  __IO uint32_t HTH9       : 1;
+  __IO uint32_t HTH10      : 1;
+  __IO uint32_t HTH11      : 1;
+  __IO uint32_t HTH12      : 1;
+  __IO uint32_t HTH13      : 1;
+  __IO uint32_t HTH14      : 1;
+  __IO uint32_t HTH15      : 1;
+  __IO uint32_t HTH16      : 1;
+  __IO uint32_t HTH17      : 1;
+  __IO uint32_t HTH18      : 1;
+  __IO uint32_t HTH19      : 1;
+  __IO uint32_t HTH20      : 1;
+  __IO uint32_t HTH21      : 1;
+  __IO uint32_t HTH22      : 1;
+  __IO uint32_t HTH23      : 1;
+  __IO uint32_t HTH24      : 1;
+  __IO uint32_t HTH25      : 1;
+  __IO uint32_t HTH26      : 1;
+  __IO uint32_t HTH27      : 1;
+  __IO uint32_t HTH28      : 1;
+  __IO uint32_t HTH29      : 1;
+  __IO uint32_t HTH30      : 1;
+  __IO uint32_t HTH31      : 1;
+} stc_ethernet_mac_mhtrh_field_t;
+
+typedef struct stc_ethernet_mac_mhtrl_field
+{
+  __IO uint32_t HTL0       : 1;
+  __IO uint32_t HTL1       : 1;
+  __IO uint32_t HTL2       : 1;
+  __IO uint32_t HTL3       : 1;
+  __IO uint32_t HTL4       : 1;
+  __IO uint32_t HTL5       : 1;
+  __IO uint32_t HTL6       : 1;
+  __IO uint32_t HTL7       : 1;
+  __IO uint32_t HTL8       : 1;
+  __IO uint32_t HTL9       : 1;
+  __IO uint32_t HTL10      : 1;
+  __IO uint32_t HTL11      : 1;
+  __IO uint32_t HTL12      : 1;
+  __IO uint32_t HTL13      : 1;
+  __IO uint32_t HTL14      : 1;
+  __IO uint32_t HTL15      : 1;
+  __IO uint32_t HTL16      : 1;
+  __IO uint32_t HTL17      : 1;
+  __IO uint32_t HTL18      : 1;
+  __IO uint32_t HTL19      : 1;
+  __IO uint32_t HTL20      : 1;
+  __IO uint32_t HTL21      : 1;
+  __IO uint32_t HTL22      : 1;
+  __IO uint32_t HTL23      : 1;
+  __IO uint32_t HTL24      : 1;
+  __IO uint32_t HTL25      : 1;
+  __IO uint32_t HTL26      : 1;
+  __IO uint32_t HTL27      : 1;
+  __IO uint32_t HTL28      : 1;
+  __IO uint32_t HTL29      : 1;
+  __IO uint32_t HTL30      : 1;
+  __IO uint32_t HTL31      : 1;
+} stc_ethernet_mac_mhtrl_field_t;
+
+typedef struct stc_ethernet_mac_gar_field
+{
+  __IO uint32_t GB         : 1;
+  __IO uint32_t GW         : 1;
+  __IO uint32_t CR0        : 1;
+  __IO uint32_t CR1        : 1;
+  __IO uint32_t CR2        : 1;
+  __IO uint32_t CR3        : 1;
+  __IO uint32_t GR0        : 1;
+  __IO uint32_t GR1        : 1;
+  __IO uint32_t GR2        : 1;
+  __IO uint32_t GR3        : 1;
+  __IO uint32_t GR4        : 1;
+  __IO uint32_t PA0        : 1;
+  __IO uint32_t PA1        : 1;
+  __IO uint32_t PA2        : 1;
+  __IO uint32_t PA3        : 1;
+  __IO uint32_t PA4        : 1;
+} stc_ethernet_mac_gar_field_t;
+
+typedef struct stc_ethernet_mac_gdr_field
+{
+  __IO uint32_t GD0        : 1;
+  __IO uint32_t GD1        : 1;
+  __IO uint32_t GD2        : 1;
+  __IO uint32_t GD3        : 1;
+  __IO uint32_t GD4        : 1;
+  __IO uint32_t GD5        : 1;
+  __IO uint32_t GD6        : 1;
+  __IO uint32_t GD7        : 1;
+  __IO uint32_t GD8        : 1;
+  __IO uint32_t GD9        : 1;
+  __IO uint32_t GD10       : 1;
+  __IO uint32_t GD11       : 1;
+  __IO uint32_t GD12       : 1;
+  __IO uint32_t GD13       : 1;
+  __IO uint32_t GD14       : 1;
+  __IO uint32_t GD15       : 1;
+} stc_ethernet_mac_gdr_field_t;
+
+typedef struct stc_ethernet_mac_fcr_field
+{
+  __IO uint32_t FCB_BPA    : 1;
+  __IO uint32_t TFE        : 1;
+  __IO uint32_t RFE        : 1;
+  __IO uint32_t UP         : 1;
+  __IO uint32_t PLT0       : 1;
+  __IO uint32_t PLT1       : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t DZPQ       : 1;
+       uint32_t RESERVED2  : 8;
+  __IO uint32_t PT0        : 1;
+  __IO uint32_t PT1        : 1;
+  __IO uint32_t PT2        : 1;
+  __IO uint32_t PT3        : 1;
+  __IO uint32_t PT4        : 1;
+  __IO uint32_t PT5        : 1;
+  __IO uint32_t PT6        : 1;
+  __IO uint32_t PT7        : 1;
+  __IO uint32_t PT8        : 1;
+  __IO uint32_t PT9        : 1;
+  __IO uint32_t PT10       : 1;
+  __IO uint32_t PT11       : 1;
+  __IO uint32_t PT12       : 1;
+  __IO uint32_t PT13       : 1;
+  __IO uint32_t PT14       : 1;
+  __IO uint32_t PT15       : 1;
+} stc_ethernet_mac_fcr_field_t;
+
+typedef struct stc_ethernet_mac_vtr_field
+{
+  __IO uint32_t VL0        : 1;
+  __IO uint32_t VL1        : 1;
+  __IO uint32_t VL2        : 1;
+  __IO uint32_t VL3        : 1;
+  __IO uint32_t VL4        : 1;
+  __IO uint32_t VL5        : 1;
+  __IO uint32_t VL6        : 1;
+  __IO uint32_t VL7        : 1;
+  __IO uint32_t VL8        : 1;
+  __IO uint32_t VL9        : 1;
+  __IO uint32_t VL10       : 1;
+  __IO uint32_t VL11       : 1;
+  __IO uint32_t VL12       : 1;
+  __IO uint32_t VL13       : 1;
+  __IO uint32_t VL14       : 1;
+  __IO uint32_t VL15       : 1;
+  __IO uint32_t ETV        : 1;
+} stc_ethernet_mac_vtr_field_t;
+
+typedef struct stc_ethernet_mac_rwffr_field
+{
+  __IO uint32_t RWFFR0     : 1;
+  __IO uint32_t RWFFR1     : 1;
+  __IO uint32_t RWFFR2     : 1;
+  __IO uint32_t RWFFR3     : 1;
+  __IO uint32_t RWFFR4     : 1;
+  __IO uint32_t RWFFR5     : 1;
+  __IO uint32_t RWFFR6     : 1;
+  __IO uint32_t RWFFR7     : 1;
+  __IO uint32_t RWFFR8     : 1;
+  __IO uint32_t RWFFR9     : 1;
+  __IO uint32_t RWFFR10    : 1;
+  __IO uint32_t RWFFR11    : 1;
+  __IO uint32_t RWFFR12    : 1;
+  __IO uint32_t RWFFR13    : 1;
+  __IO uint32_t RWFFR14    : 1;
+  __IO uint32_t RWFFR15    : 1;
+  __IO uint32_t RWFFR16    : 1;
+  __IO uint32_t RWFFR17    : 1;
+  __IO uint32_t RWFFR18    : 1;
+  __IO uint32_t RWFFR19    : 1;
+  __IO uint32_t RWFFR20    : 1;
+  __IO uint32_t RWFFR21    : 1;
+  __IO uint32_t RWFFR22    : 1;
+  __IO uint32_t RWFFR23    : 1;
+  __IO uint32_t RWFFR24    : 1;
+  __IO uint32_t RWFFR25    : 1;
+  __IO uint32_t RWFFR26    : 1;
+  __IO uint32_t RWFFR27    : 1;
+  __IO uint32_t RWFFR28    : 1;
+  __IO uint32_t RWFFR29    : 1;
+  __IO uint32_t RWFFR30    : 1;
+  __IO uint32_t RWFFR31    : 1;
+} stc_ethernet_mac_rwffr_field_t;
+
+typedef struct stc_ethernet_mac_pmtr_field
+{
+  __IO uint32_t PD         : 1;
+  __IO uint32_t MPE        : 1;
+  __IO uint32_t WFE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t MPR        : 1;
+  __IO uint32_t WPR        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t GU         : 1;
+       uint32_t RESERVED3  :21;
+  __IO uint32_t RWFFRPR    : 1;
+} stc_ethernet_mac_pmtr_field_t;
+
+typedef struct stc_ethernet_mac_lpicsr_field
+{
+  __IO uint32_t TLPIEN     : 1;
+  __IO uint32_t TLPIEX     : 1;
+  __IO uint32_t RLPIEN     : 1;
+  __IO uint32_t RLPIEX     : 1;
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t TLPIST     : 1;
+  __IO uint32_t RLPIST     : 1;
+       uint32_t RESERVED2  : 6;
+  __IO uint32_t LPIEN      : 1;
+  __IO uint32_t PLS        : 1;
+  __IO uint32_t PLSEN      : 1;
+  __IO uint32_t LPITXA     : 1;
+} stc_ethernet_mac_lpicsr_field_t;
+
+typedef struct stc_ethernet_mac_lpitcr_field
+{
+  __IO uint32_t TWT0       : 1;
+  __IO uint32_t TWT1       : 1;
+  __IO uint32_t TWT2       : 1;
+  __IO uint32_t TWT3       : 1;
+  __IO uint32_t TWT4       : 1;
+  __IO uint32_t TWT5       : 1;
+  __IO uint32_t TWT6       : 1;
+  __IO uint32_t TWT7       : 1;
+  __IO uint32_t TWT8       : 1;
+  __IO uint32_t TWT9       : 1;
+  __IO uint32_t TWT10      : 1;
+  __IO uint32_t TWT11      : 1;
+  __IO uint32_t TWT12      : 1;
+  __IO uint32_t TWT13      : 1;
+  __IO uint32_t TWT14      : 1;
+  __IO uint32_t TWT15      : 1;
+  __IO uint32_t LIT0       : 1;
+  __IO uint32_t LIT1       : 1;
+  __IO uint32_t LIT2       : 1;
+  __IO uint32_t LIT3       : 1;
+  __IO uint32_t LIT4       : 1;
+  __IO uint32_t LIT5       : 1;
+  __IO uint32_t LIT6       : 1;
+  __IO uint32_t LIT7       : 1;
+  __IO uint32_t LIT8       : 1;
+  __IO uint32_t LIT9       : 1;
+} stc_ethernet_mac_lpitcr_field_t;
+
+typedef struct stc_ethernet_mac_isr_field
+{
+  __IO uint32_t RGIS       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIS        : 1;
+  __IO uint32_t MIS        : 1;
+  __IO uint32_t RIS        : 1;
+  __IO uint32_t TIS        : 1;
+  __IO uint32_t COIS       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t TSIS       : 1;
+  __IO uint32_t LPIIS      : 1;
+} stc_ethernet_mac_isr_field_t;
+
+typedef struct stc_ethernet_mac_imr_field
+{
+  __IO uint32_t RGIM       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIM        : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t TSIM       : 1;
+  __IO uint32_t LPIIM      : 1;
+} stc_ethernet_mac_imr_field_t;
+
+typedef struct stc_ethernet_mac_mar0h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  :15;
+  __IO uint32_t MO         : 1;
+} stc_ethernet_mac_mar0h_field_t;
+
+typedef struct stc_ethernet_mac_mar0l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar0l_field_t;
+
+typedef struct stc_ethernet_mac_mar1h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar1h_field_t;
+
+typedef struct stc_ethernet_mac_mar1l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar1l_field_t;
+
+typedef struct stc_ethernet_mac_mar2h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar2h_field_t;
+
+typedef struct stc_ethernet_mac_mar2l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar2l_field_t;
+
+typedef struct stc_ethernet_mac_mar3h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar3h_field_t;
+
+typedef struct stc_ethernet_mac_mar3l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar3l_field_t;
+
+typedef struct stc_ethernet_mac_mar4h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar4h_field_t;
+
+typedef struct stc_ethernet_mac_mar4l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar4l_field_t;
+
+typedef struct stc_ethernet_mac_mar5h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar5h_field_t;
+
+typedef struct stc_ethernet_mac_mar5l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar5l_field_t;
+
+typedef struct stc_ethernet_mac_mar6h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar6h_field_t;
+
+typedef struct stc_ethernet_mac_mar6l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar6l_field_t;
+
+typedef struct stc_ethernet_mac_mar7h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar7h_field_t;
+
+typedef struct stc_ethernet_mac_mar7l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar7l_field_t;
+
+typedef struct stc_ethernet_mac_mar8h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar8h_field_t;
+
+typedef struct stc_ethernet_mac_mar8l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar8l_field_t;
+
+typedef struct stc_ethernet_mac_mar9h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar9h_field_t;
+
+typedef struct stc_ethernet_mac_mar9l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar9l_field_t;
+
+typedef struct stc_ethernet_mac_mar10h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar10h_field_t;
+
+typedef struct stc_ethernet_mac_mar10l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar10l_field_t;
+
+typedef struct stc_ethernet_mac_mar11h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar11h_field_t;
+
+typedef struct stc_ethernet_mac_mar11l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar11l_field_t;
+
+typedef struct stc_ethernet_mac_mar12h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar12h_field_t;
+
+typedef struct stc_ethernet_mac_mar12l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar12l_field_t;
+
+typedef struct stc_ethernet_mac_mar13h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar13h_field_t;
+
+typedef struct stc_ethernet_mac_mar13l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar13l_field_t;
+
+typedef struct stc_ethernet_mac_mar14h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar14h_field_t;
+
+typedef struct stc_ethernet_mac_mar14l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar14l_field_t;
+
+typedef struct stc_ethernet_mac_mar15h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar15h_field_t;
+
+typedef struct stc_ethernet_mac_mar15l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar15l_field_t;
+
+typedef struct stc_ethernet_mac_rgsr_field
+{
+  __IO uint32_t LM         : 1;
+  __IO uint32_t LSP0       : 1;
+  __IO uint32_t LSP1       : 1;
+  __IO uint32_t LS         : 1;
+} stc_ethernet_mac_rgsr_field_t;
+
+typedef struct stc_ethernet_mac_tscr_field
+{
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TFCU       : 1;
+  __IO uint32_t TSI        : 1;
+  __IO uint32_t TSU        : 1;
+  __IO uint32_t TITE       : 1;
+  __IO uint32_t TARU       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TSEA       : 1;
+  __IO uint32_t TSDB       : 1;
+  __IO uint32_t TSV2E      : 1;
+  __IO uint32_t TETSP      : 1;
+  __IO uint32_t TSIP6E     : 1;
+  __IO uint32_t TSIP4E     : 1;
+  __IO uint32_t TETSEM     : 1;
+  __IO uint32_t TSMRM      : 1;
+  __IO uint32_t TSPS0      : 1;
+  __IO uint32_t TSPS1      : 1;
+  __IO uint32_t TSENMF     : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t ATSFC      : 1;
+} stc_ethernet_mac_tscr_field_t;
+
+typedef struct stc_ethernet_mac_ssir_field
+{
+  __IO uint32_t SSINC0     : 1;
+  __IO uint32_t SSINC1     : 1;
+  __IO uint32_t SSINC2     : 1;
+  __IO uint32_t SSINC3     : 1;
+  __IO uint32_t SSINC4     : 1;
+  __IO uint32_t SSINC5     : 1;
+  __IO uint32_t SSINC6     : 1;
+  __IO uint32_t SSINC7     : 1;
+} stc_ethernet_mac_ssir_field_t;
+
+typedef struct stc_ethernet_mac_stsr_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsr_field_t;
+
+typedef struct stc_ethernet_mac_stnr_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+} stc_ethernet_mac_stnr_field_t;
+
+typedef struct stc_ethernet_mac_stsur_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsur_field_t;
+
+typedef struct stc_ethernet_mac_stnur_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+  __IO uint32_t ADDSUB     : 1;
+} stc_ethernet_mac_stnur_field_t;
+
+typedef struct stc_ethernet_mac_tsar_field
+{
+  __IO uint32_t TSAR0      : 1;
+  __IO uint32_t TSAR1      : 1;
+  __IO uint32_t TSAR2      : 1;
+  __IO uint32_t TSAR3      : 1;
+  __IO uint32_t TSAR4      : 1;
+  __IO uint32_t TSAR5      : 1;
+  __IO uint32_t TSAR6      : 1;
+  __IO uint32_t TSAR7      : 1;
+  __IO uint32_t TSAR8      : 1;
+  __IO uint32_t TSAR9      : 1;
+  __IO uint32_t TSAR10     : 1;
+  __IO uint32_t TSAR11     : 1;
+  __IO uint32_t TSAR12     : 1;
+  __IO uint32_t TSAR13     : 1;
+  __IO uint32_t TSAR14     : 1;
+  __IO uint32_t TSAR15     : 1;
+  __IO uint32_t TSAR16     : 1;
+  __IO uint32_t TSAR17     : 1;
+  __IO uint32_t TSAR18     : 1;
+  __IO uint32_t TSAR19     : 1;
+  __IO uint32_t TSAR20     : 1;
+  __IO uint32_t TSAR21     : 1;
+  __IO uint32_t TSAR22     : 1;
+  __IO uint32_t TSAR23     : 1;
+  __IO uint32_t TSAR24     : 1;
+  __IO uint32_t TSAR25     : 1;
+  __IO uint32_t TSAR26     : 1;
+  __IO uint32_t TSAR27     : 1;
+  __IO uint32_t TSAR28     : 1;
+  __IO uint32_t TSAR29     : 1;
+  __IO uint32_t TSAR30     : 1;
+  __IO uint32_t TSAR31     : 1;
+} stc_ethernet_mac_tsar_field_t;
+
+typedef struct stc_ethernet_mac_ttsr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+  __IO uint32_t TSTR31     : 1;
+} stc_ethernet_mac_ttsr_field_t;
+
+typedef struct stc_ethernet_mac_ttnr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+} stc_ethernet_mac_ttnr_field_t;
+
+typedef struct stc_ethernet_mac_sthwsr_field
+{
+  __IO uint32_t TSHWR0     : 1;
+  __IO uint32_t TSHWR1     : 1;
+  __IO uint32_t TSHWR2     : 1;
+  __IO uint32_t TSHWR3     : 1;
+  __IO uint32_t TSHWR4     : 1;
+  __IO uint32_t TSHWR5     : 1;
+  __IO uint32_t TSHWR6     : 1;
+  __IO uint32_t TSHWR7     : 1;
+  __IO uint32_t TSHWR8     : 1;
+  __IO uint32_t TSHWR9     : 1;
+  __IO uint32_t TSHWR10    : 1;
+  __IO uint32_t TSHWR11    : 1;
+  __IO uint32_t TSHWR12    : 1;
+  __IO uint32_t TSHWR13    : 1;
+  __IO uint32_t TSHWR14    : 1;
+  __IO uint32_t TSHWR15    : 1;
+} stc_ethernet_mac_sthwsr_field_t;
+
+typedef struct stc_ethernet_mac_tsr_field
+{
+  __IO uint32_t TSSOVF     : 1;
+  __IO uint32_t TSTART     : 1;
+  __IO uint32_t ATSTS      : 1;
+  __IO uint32_t TRGTER     : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t ATSSTM     : 1;
+  __IO uint32_t ATSNS0     : 1;
+  __IO uint32_t ATSNS1     : 1;
+  __IO uint32_t ATSNS2     : 1;
+} stc_ethernet_mac_tsr_field_t;
+
+typedef struct stc_ethernet_mac_ppscr_field
+{
+  __IO uint32_t PPSCTRL0   : 1;
+  __IO uint32_t PPSCTRL1   : 1;
+  __IO uint32_t PPSCTRL2   : 1;
+  __IO uint32_t PPSCTRL3   : 1;
+} stc_ethernet_mac_ppscr_field_t;
+
+typedef struct stc_ethernet_mac_atnr_field
+{
+  __IO uint32_t ATN0       : 1;
+  __IO uint32_t ATN1       : 1;
+  __IO uint32_t ATN2       : 1;
+  __IO uint32_t ATN3       : 1;
+  __IO uint32_t ATN4       : 1;
+  __IO uint32_t ATN5       : 1;
+  __IO uint32_t ATN6       : 1;
+  __IO uint32_t ATN7       : 1;
+  __IO uint32_t ATN8       : 1;
+  __IO uint32_t ATN9       : 1;
+  __IO uint32_t ATN10      : 1;
+  __IO uint32_t ATN11      : 1;
+  __IO uint32_t ATN12      : 1;
+  __IO uint32_t ATN13      : 1;
+  __IO uint32_t ATN14      : 1;
+  __IO uint32_t ATN15      : 1;
+  __IO uint32_t ATN16      : 1;
+  __IO uint32_t ATN17      : 1;
+  __IO uint32_t ATN18      : 1;
+  __IO uint32_t ATN19      : 1;
+  __IO uint32_t ATN20      : 1;
+  __IO uint32_t ATN21      : 1;
+  __IO uint32_t ATN22      : 1;
+  __IO uint32_t ATN23      : 1;
+  __IO uint32_t ATN24      : 1;
+  __IO uint32_t ATN25      : 1;
+  __IO uint32_t ATN26      : 1;
+  __IO uint32_t ATN27      : 1;
+  __IO uint32_t ATN28      : 1;
+  __IO uint32_t ATN29      : 1;
+  __IO uint32_t ATN30      : 1;
+} stc_ethernet_mac_atnr_field_t;
+
+typedef struct stc_ethernet_mac_atsr_field
+{
+  __IO uint32_t ATS0       : 1;
+  __IO uint32_t ATS1       : 1;
+  __IO uint32_t ATS2       : 1;
+  __IO uint32_t ATS3       : 1;
+  __IO uint32_t ATS4       : 1;
+  __IO uint32_t ATS5       : 1;
+  __IO uint32_t ATS6       : 1;
+  __IO uint32_t ATS7       : 1;
+  __IO uint32_t ATS8       : 1;
+  __IO uint32_t ATS9       : 1;
+  __IO uint32_t ATS10      : 1;
+  __IO uint32_t ATS11      : 1;
+  __IO uint32_t ATS12      : 1;
+  __IO uint32_t ATS13      : 1;
+  __IO uint32_t ATS14      : 1;
+  __IO uint32_t ATS15      : 1;
+  __IO uint32_t ATS16      : 1;
+  __IO uint32_t ATS17      : 1;
+  __IO uint32_t ATS18      : 1;
+  __IO uint32_t ATS19      : 1;
+  __IO uint32_t ATS20      : 1;
+  __IO uint32_t ATS21      : 1;
+  __IO uint32_t ATS22      : 1;
+  __IO uint32_t ATS23      : 1;
+  __IO uint32_t ATS24      : 1;
+  __IO uint32_t ATS25      : 1;
+  __IO uint32_t ATS26      : 1;
+  __IO uint32_t ATS27      : 1;
+  __IO uint32_t ATS28      : 1;
+  __IO uint32_t ATS29      : 1;
+  __IO uint32_t ATS30      : 1;
+  __IO uint32_t ATS31      : 1;
+} stc_ethernet_mac_atsr_field_t;
+
+typedef struct stc_ethernet_mac_mar16h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar16h_field_t;
+
+typedef struct stc_ethernet_mac_mar16l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar16l_field_t;
+
+typedef struct stc_ethernet_mac_mar17h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar17h_field_t;
+
+typedef struct stc_ethernet_mac_mar17l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar17l_field_t;
+
+typedef struct stc_ethernet_mac_mar18h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar18h_field_t;
+
+typedef struct stc_ethernet_mac_mar18l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar18l_field_t;
+
+typedef struct stc_ethernet_mac_mar19h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar19h_field_t;
+
+typedef struct stc_ethernet_mac_mar19l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar19l_field_t;
+
+typedef struct stc_ethernet_mac_mar20h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar20h_field_t;
+
+typedef struct stc_ethernet_mac_mar20l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar20l_field_t;
+
+typedef struct stc_ethernet_mac_mar21h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar21h_field_t;
+
+typedef struct stc_ethernet_mac_mar21l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar21l_field_t;
+
+typedef struct stc_ethernet_mac_mar22h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar22h_field_t;
+
+typedef struct stc_ethernet_mac_mar22l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar22l_field_t;
+
+typedef struct stc_ethernet_mac_mar23h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar23h_field_t;
+
+typedef struct stc_ethernet_mac_mar23l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar23l_field_t;
+
+typedef struct stc_ethernet_mac_mar24h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar24h_field_t;
+
+typedef struct stc_ethernet_mac_mar24l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar24l_field_t;
+
+typedef struct stc_ethernet_mac_mar25h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar25h_field_t;
+
+typedef struct stc_ethernet_mac_mar25l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar25l_field_t;
+
+typedef struct stc_ethernet_mac_mar26h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar26h_field_t;
+
+typedef struct stc_ethernet_mac_mar26l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar26l_field_t;
+
+typedef struct stc_ethernet_mac_mar27h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar27h_field_t;
+
+typedef struct stc_ethernet_mac_mar27l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar27l_field_t;
+
+typedef struct stc_ethernet_mac_mar28h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar28h_field_t;
+
+typedef struct stc_ethernet_mac_mar28l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar28l_field_t;
+
+typedef struct stc_ethernet_mac_mar29h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar29h_field_t;
+
+typedef struct stc_ethernet_mac_mar29l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar29l_field_t;
+
+typedef struct stc_ethernet_mac_mar30h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar30h_field_t;
+
+typedef struct stc_ethernet_mac_mar30l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar30l_field_t;
+
+typedef struct stc_ethernet_mac_mar31h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar31h_field_t;
+
+typedef struct stc_ethernet_mac_mar31l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar31l_field_t;
+
+typedef struct stc_ethernet_mac_bmr_field
+{
+  __IO uint32_t SWR        : 1;
+  __IO uint32_t DA         : 1;
+  __IO uint32_t DSL0       : 1;
+  __IO uint32_t DSL1       : 1;
+  __IO uint32_t DSL2       : 1;
+  __IO uint32_t DSL3       : 1;
+  __IO uint32_t DSL4       : 1;
+  __IO uint32_t ATDS       : 1;
+  __IO uint32_t PBL0       : 1;
+  __IO uint32_t PBL1       : 1;
+  __IO uint32_t PBL2       : 1;
+  __IO uint32_t PBL3       : 1;
+  __IO uint32_t PBL4       : 1;
+  __IO uint32_t PBL5       : 1;
+  __IO uint32_t PR0        : 1;
+  __IO uint32_t PR1        : 1;
+  __IO uint32_t FB         : 1;
+  __IO uint32_t RPBL0      : 1;
+  __IO uint32_t RPBL1      : 1;
+  __IO uint32_t RPBL2      : 1;
+  __IO uint32_t RPBL3      : 1;
+  __IO uint32_t RPBL4      : 1;
+  __IO uint32_t RPBL5      : 1;
+  __IO uint32_t USP        : 1;
+  __IO uint32_t _8XPBL     : 1;
+  __IO uint32_t AAL        : 1;
+  __IO uint32_t MB         : 1;
+  __IO uint32_t TXPR       : 1;
+} stc_ethernet_mac_bmr_field_t;
+
+typedef struct stc_ethernet_mac_tpdr_field
+{
+  __IO uint32_t TPD0       : 1;
+  __IO uint32_t TPD1       : 1;
+  __IO uint32_t TPD2       : 1;
+  __IO uint32_t TPD3       : 1;
+  __IO uint32_t TPD4       : 1;
+  __IO uint32_t TPD5       : 1;
+  __IO uint32_t TPD6       : 1;
+  __IO uint32_t TPD7       : 1;
+  __IO uint32_t TPD8       : 1;
+  __IO uint32_t TPD9       : 1;
+  __IO uint32_t TPD10      : 1;
+  __IO uint32_t TPD11      : 1;
+  __IO uint32_t TPD12      : 1;
+  __IO uint32_t TPD13      : 1;
+  __IO uint32_t TPD14      : 1;
+  __IO uint32_t TPD15      : 1;
+  __IO uint32_t TPD16      : 1;
+  __IO uint32_t TPD17      : 1;
+  __IO uint32_t TPD18      : 1;
+  __IO uint32_t TPD19      : 1;
+  __IO uint32_t TPD20      : 1;
+  __IO uint32_t TPD21      : 1;
+  __IO uint32_t TPD22      : 1;
+  __IO uint32_t TPD23      : 1;
+  __IO uint32_t TPD24      : 1;
+  __IO uint32_t TPD25      : 1;
+  __IO uint32_t TPD26      : 1;
+  __IO uint32_t TPD27      : 1;
+  __IO uint32_t TPD28      : 1;
+  __IO uint32_t TPD29      : 1;
+  __IO uint32_t TPD30      : 1;
+  __IO uint32_t TPD31      : 1;
+} stc_ethernet_mac_tpdr_field_t;
+
+typedef struct stc_ethernet_mac_rpdr_field
+{
+  __IO uint32_t RPD0       : 1;
+  __IO uint32_t RPD1       : 1;
+  __IO uint32_t RPD2       : 1;
+  __IO uint32_t RPD3       : 1;
+  __IO uint32_t RPD4       : 1;
+  __IO uint32_t RPD5       : 1;
+  __IO uint32_t RPD6       : 1;
+  __IO uint32_t RPD7       : 1;
+  __IO uint32_t RPD8       : 1;
+  __IO uint32_t RPD9       : 1;
+  __IO uint32_t RPD10      : 1;
+  __IO uint32_t RPD11      : 1;
+  __IO uint32_t RPD12      : 1;
+  __IO uint32_t RPD13      : 1;
+  __IO uint32_t RPD14      : 1;
+  __IO uint32_t RPD15      : 1;
+  __IO uint32_t RPD16      : 1;
+  __IO uint32_t RPD17      : 1;
+  __IO uint32_t RPD18      : 1;
+  __IO uint32_t RPD19      : 1;
+  __IO uint32_t RPD20      : 1;
+  __IO uint32_t RPD21      : 1;
+  __IO uint32_t RPD22      : 1;
+  __IO uint32_t RPD23      : 1;
+  __IO uint32_t RPD24      : 1;
+  __IO uint32_t RPD25      : 1;
+  __IO uint32_t RPD26      : 1;
+  __IO uint32_t RPD27      : 1;
+  __IO uint32_t RPD28      : 1;
+  __IO uint32_t RPD29      : 1;
+  __IO uint32_t RPD30      : 1;
+  __IO uint32_t RPD31      : 1;
+} stc_ethernet_mac_rpdr_field_t;
+
+typedef struct stc_ethernet_mac_rdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t SRL2       : 1;
+  __IO uint32_t SRL3       : 1;
+  __IO uint32_t SRL4       : 1;
+  __IO uint32_t SRL5       : 1;
+  __IO uint32_t SRL6       : 1;
+  __IO uint32_t SRL7       : 1;
+  __IO uint32_t SRL8       : 1;
+  __IO uint32_t SRL9       : 1;
+  __IO uint32_t SRL10      : 1;
+  __IO uint32_t SRL11      : 1;
+  __IO uint32_t SRL12      : 1;
+  __IO uint32_t SRL13      : 1;
+  __IO uint32_t SRL14      : 1;
+  __IO uint32_t SRL15      : 1;
+  __IO uint32_t SRL16      : 1;
+  __IO uint32_t SRL17      : 1;
+  __IO uint32_t SRL18      : 1;
+  __IO uint32_t SRL19      : 1;
+  __IO uint32_t SRL20      : 1;
+  __IO uint32_t SRL21      : 1;
+  __IO uint32_t SRL22      : 1;
+  __IO uint32_t SRL23      : 1;
+  __IO uint32_t SRL24      : 1;
+  __IO uint32_t SRL25      : 1;
+  __IO uint32_t SRL26      : 1;
+  __IO uint32_t SRL27      : 1;
+  __IO uint32_t SRL28      : 1;
+  __IO uint32_t SRL29      : 1;
+  __IO uint32_t SRL30      : 1;
+  __IO uint32_t SRL31      : 1;
+} stc_ethernet_mac_rdlar_field_t;
+
+typedef struct stc_ethernet_mac_tdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t STL2       : 1;
+  __IO uint32_t STL3       : 1;
+  __IO uint32_t STL4       : 1;
+  __IO uint32_t STL5       : 1;
+  __IO uint32_t STL6       : 1;
+  __IO uint32_t STL7       : 1;
+  __IO uint32_t STL8       : 1;
+  __IO uint32_t STL9       : 1;
+  __IO uint32_t STL10      : 1;
+  __IO uint32_t STL11      : 1;
+  __IO uint32_t STL12      : 1;
+  __IO uint32_t STL13      : 1;
+  __IO uint32_t STL14      : 1;
+  __IO uint32_t STL15      : 1;
+  __IO uint32_t STL16      : 1;
+  __IO uint32_t STL17      : 1;
+  __IO uint32_t STL18      : 1;
+  __IO uint32_t STL19      : 1;
+  __IO uint32_t STL20      : 1;
+  __IO uint32_t STL21      : 1;
+  __IO uint32_t STL22      : 1;
+  __IO uint32_t STL23      : 1;
+  __IO uint32_t STL24      : 1;
+  __IO uint32_t STL25      : 1;
+  __IO uint32_t STL26      : 1;
+  __IO uint32_t STL27      : 1;
+  __IO uint32_t STL28      : 1;
+  __IO uint32_t STL29      : 1;
+  __IO uint32_t STL30      : 1;
+  __IO uint32_t STL31      : 1;
+} stc_ethernet_mac_tdlar_field_t;
+
+typedef struct stc_ethernet_mac_sr_field
+{
+  __IO uint32_t TI         : 1;
+  __IO uint32_t TPS        : 1;
+  __IO uint32_t TU         : 1;
+  __IO uint32_t TJT        : 1;
+  __IO uint32_t OVF        : 1;
+  __IO uint32_t UNF        : 1;
+  __IO uint32_t RI         : 1;
+  __IO uint32_t RU         : 1;
+  __IO uint32_t RPS        : 1;
+  __IO uint32_t RWT        : 1;
+  __IO uint32_t ETI        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBI        : 1;
+  __IO uint32_t ERI        : 1;
+  __IO uint32_t AIS        : 1;
+  __IO uint32_t NIS        : 1;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+  __IO uint32_t TS0        : 1;
+  __IO uint32_t TS1        : 1;
+  __IO uint32_t TS2        : 1;
+  __IO uint32_t EB0        : 1;
+  __IO uint32_t EB1        : 1;
+  __IO uint32_t EB2        : 1;
+  __IO uint32_t GLI        : 1;
+  __IO uint32_t GMI        : 1;
+  __IO uint32_t GPI        : 1;
+  __IO uint32_t TTI        : 1;
+  __IO uint32_t GLPII      : 1;
+} stc_ethernet_mac_sr_field_t;
+
+typedef struct stc_ethernet_mac_omr_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t SR         : 1;
+  __IO uint32_t OSF        : 1;
+  __IO uint32_t RTC0       : 1;
+  __IO uint32_t RTC1       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t FUF        : 1;
+  __IO uint32_t FEF        : 1;
+       uint32_t RESERVED3  : 5;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t TTC0       : 1;
+  __IO uint32_t TTC1       : 1;
+  __IO uint32_t TTC2       : 1;
+       uint32_t RESERVED4  : 3;
+  __IO uint32_t FTF        : 1;
+  __IO uint32_t TSF        : 1;
+       uint32_t RESERVED5  : 2;
+  __IO uint32_t DFF        : 1;
+  __IO uint32_t RSF        : 1;
+  __IO uint32_t DT         : 1;
+} stc_ethernet_mac_omr_field_t;
+
+typedef struct stc_ethernet_mac_ier_field
+{
+  __IO uint32_t TIE        : 1;
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TUE        : 1;
+  __IO uint32_t TJE        : 1;
+  __IO uint32_t OVE        : 1;
+  __IO uint32_t UNE        : 1;
+  __IO uint32_t RIE        : 1;
+  __IO uint32_t RUE        : 1;
+  __IO uint32_t RSE        : 1;
+  __IO uint32_t RWE        : 1;
+  __IO uint32_t ETE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBE        : 1;
+  __IO uint32_t ERE        : 1;
+  __IO uint32_t AIE        : 1;
+  __IO uint32_t NIE        : 1;
+} stc_ethernet_mac_ier_field_t;
+
+typedef struct stc_ethernet_mac_mfbocr_field
+{
+  __IO uint32_t NMFH0      : 1;
+  __IO uint32_t NMFH1      : 1;
+  __IO uint32_t NMFH2      : 1;
+  __IO uint32_t NMFH3      : 1;
+  __IO uint32_t NMFH4      : 1;
+  __IO uint32_t NMFH5      : 1;
+  __IO uint32_t NMFH6      : 1;
+  __IO uint32_t NMFH7      : 1;
+  __IO uint32_t NMFH8      : 1;
+  __IO uint32_t NMFH9      : 1;
+  __IO uint32_t NMFH10     : 1;
+  __IO uint32_t NMFH11     : 1;
+  __IO uint32_t NMFH12     : 1;
+  __IO uint32_t NMFH13     : 1;
+  __IO uint32_t NMFH14     : 1;
+  __IO uint32_t NMFH15     : 1;
+  __IO uint32_t ONMFH      : 1;
+  __IO uint32_t NMFF0      : 1;
+  __IO uint32_t NMFF1      : 1;
+  __IO uint32_t NMFF2      : 1;
+  __IO uint32_t NMFF3      : 1;
+  __IO uint32_t NMFF4      : 1;
+  __IO uint32_t NMFF5      : 1;
+  __IO uint32_t NMFF6      : 1;
+  __IO uint32_t NMFF7      : 1;
+  __IO uint32_t NMFF8      : 1;
+  __IO uint32_t NMFF9      : 1;
+  __IO uint32_t NMFF10     : 1;
+  __IO uint32_t ONMFF      : 1;
+} stc_ethernet_mac_mfbocr_field_t;
+
+typedef struct stc_ethernet_mac_riwtr_field
+{
+  __IO uint32_t RIWT0      : 1;
+  __IO uint32_t RIWT1      : 1;
+  __IO uint32_t RIWT2      : 1;
+  __IO uint32_t RIWT3      : 1;
+  __IO uint32_t RIWT4      : 1;
+  __IO uint32_t RIWT5      : 1;
+  __IO uint32_t RIWT6      : 1;
+  __IO uint32_t RIWT7      : 1;
+} stc_ethernet_mac_riwtr_field_t;
+
+typedef struct stc_ethernet_mac_ahbsr_field
+{
+  __IO uint32_t AHBS       : 1;
+} stc_ethernet_mac_ahbsr_field_t;
+
+typedef struct stc_ethernet_mac_chtdr_field
+{
+  __IO uint32_t HTDAP0     : 1;
+  __IO uint32_t HTDAP1     : 1;
+  __IO uint32_t HTDAP2     : 1;
+  __IO uint32_t HTDAP3     : 1;
+  __IO uint32_t HTDAP4     : 1;
+  __IO uint32_t HTDAP5     : 1;
+  __IO uint32_t HTDAP6     : 1;
+  __IO uint32_t HTDAP7     : 1;
+  __IO uint32_t HTDAP8     : 1;
+  __IO uint32_t HTDAP9     : 1;
+  __IO uint32_t HTDAP10    : 1;
+  __IO uint32_t HTDAP11    : 1;
+  __IO uint32_t HTDAP12    : 1;
+  __IO uint32_t HTDAP13    : 1;
+  __IO uint32_t HTDAP14    : 1;
+  __IO uint32_t HTDAP15    : 1;
+  __IO uint32_t HTDAP16    : 1;
+  __IO uint32_t HTDAP17    : 1;
+  __IO uint32_t HTDAP18    : 1;
+  __IO uint32_t HTDAP19    : 1;
+  __IO uint32_t HTDAP20    : 1;
+  __IO uint32_t HTDAP21    : 1;
+  __IO uint32_t HTDAP22    : 1;
+  __IO uint32_t HTDAP23    : 1;
+  __IO uint32_t HTDAP24    : 1;
+  __IO uint32_t HTDAP25    : 1;
+  __IO uint32_t HTDAP26    : 1;
+  __IO uint32_t HTDAP27    : 1;
+  __IO uint32_t HTDAP28    : 1;
+  __IO uint32_t HTDAP29    : 1;
+  __IO uint32_t HTDAP30    : 1;
+  __IO uint32_t HTDAP31    : 1;
+} stc_ethernet_mac_chtdr_field_t;
+
+typedef struct stc_ethernet_mac_chrdr_field
+{
+  __IO uint32_t HRDAP0     : 1;
+  __IO uint32_t HRDAP1     : 1;
+  __IO uint32_t HRDAP2     : 1;
+  __IO uint32_t HRDAP3     : 1;
+  __IO uint32_t HRDAP4     : 1;
+  __IO uint32_t HRDAP5     : 1;
+  __IO uint32_t HRDAP6     : 1;
+  __IO uint32_t HRDAP7     : 1;
+  __IO uint32_t HRDAP8     : 1;
+  __IO uint32_t HRDAP9     : 1;
+  __IO uint32_t HRDAP10    : 1;
+  __IO uint32_t HRDAP11    : 1;
+  __IO uint32_t HRDAP12    : 1;
+  __IO uint32_t HRDAP13    : 1;
+  __IO uint32_t HRDAP14    : 1;
+  __IO uint32_t HRDAP15    : 1;
+  __IO uint32_t HRDAP16    : 1;
+  __IO uint32_t HRDAP17    : 1;
+  __IO uint32_t HRDAP18    : 1;
+  __IO uint32_t HRDAP19    : 1;
+  __IO uint32_t HRDAP20    : 1;
+  __IO uint32_t HRDAP21    : 1;
+  __IO uint32_t HRDAP22    : 1;
+  __IO uint32_t HRDAP23    : 1;
+  __IO uint32_t HRDAP24    : 1;
+  __IO uint32_t HRDAP25    : 1;
+  __IO uint32_t HRDAP26    : 1;
+  __IO uint32_t HRDAP27    : 1;
+  __IO uint32_t HRDAP28    : 1;
+  __IO uint32_t HRDAP29    : 1;
+  __IO uint32_t HRDAP30    : 1;
+  __IO uint32_t HRDAP31    : 1;
+} stc_ethernet_mac_chrdr_field_t;
+
+typedef struct stc_ethernet_mac_chtbar_field
+{
+  __IO uint32_t HTBAR0     : 1;
+  __IO uint32_t HTBAR1     : 1;
+  __IO uint32_t HTBAR2     : 1;
+  __IO uint32_t HTBAR3     : 1;
+  __IO uint32_t HTBAR4     : 1;
+  __IO uint32_t HTBAR5     : 1;
+  __IO uint32_t HTBAR6     : 1;
+  __IO uint32_t HTBAR7     : 1;
+  __IO uint32_t HTBAR8     : 1;
+  __IO uint32_t HTBAR9     : 1;
+  __IO uint32_t HTBAR10    : 1;
+  __IO uint32_t HTBAR11    : 1;
+  __IO uint32_t HTBAR12    : 1;
+  __IO uint32_t HTBAR13    : 1;
+  __IO uint32_t HTBAR14    : 1;
+  __IO uint32_t HTBAR15    : 1;
+  __IO uint32_t HTBAR16    : 1;
+  __IO uint32_t HTBAR17    : 1;
+  __IO uint32_t HTBAR18    : 1;
+  __IO uint32_t HTBAR19    : 1;
+  __IO uint32_t HTBAR20    : 1;
+  __IO uint32_t HTBAR21    : 1;
+  __IO uint32_t HTBAR22    : 1;
+  __IO uint32_t HTBAR23    : 1;
+  __IO uint32_t HTBAR24    : 1;
+  __IO uint32_t HTBAR25    : 1;
+  __IO uint32_t HTBAR26    : 1;
+  __IO uint32_t HTBAR27    : 1;
+  __IO uint32_t HTBAR28    : 1;
+  __IO uint32_t HTBAR29    : 1;
+  __IO uint32_t HTBAR30    : 1;
+  __IO uint32_t HTBAR31    : 1;
+} stc_ethernet_mac_chtbar_field_t;
+
+typedef struct stc_ethernet_mac_chrbar_field
+{
+  __IO uint32_t HRBAR0     : 1;
+  __IO uint32_t HRBAR1     : 1;
+  __IO uint32_t HRBAR2     : 1;
+  __IO uint32_t HRBAR3     : 1;
+  __IO uint32_t HRBAR4     : 1;
+  __IO uint32_t HRBAR5     : 1;
+  __IO uint32_t HRBAR6     : 1;
+  __IO uint32_t HRBAR7     : 1;
+  __IO uint32_t HRBAR8     : 1;
+  __IO uint32_t HRBAR9     : 1;
+  __IO uint32_t HRBAR10    : 1;
+  __IO uint32_t HRBAR11    : 1;
+  __IO uint32_t HRBAR12    : 1;
+  __IO uint32_t HRBAR13    : 1;
+  __IO uint32_t HRBAR14    : 1;
+  __IO uint32_t HRBAR15    : 1;
+  __IO uint32_t HRBAR16    : 1;
+  __IO uint32_t HRBAR17    : 1;
+  __IO uint32_t HRBAR18    : 1;
+  __IO uint32_t HRBAR19    : 1;
+  __IO uint32_t HRBAR20    : 1;
+  __IO uint32_t HRBAR21    : 1;
+  __IO uint32_t HRBAR22    : 1;
+  __IO uint32_t HRBAR23    : 1;
+  __IO uint32_t HRBAR24    : 1;
+  __IO uint32_t HRBAR25    : 1;
+  __IO uint32_t HRBAR26    : 1;
+  __IO uint32_t HRBAR27    : 1;
+  __IO uint32_t HRBAR28    : 1;
+  __IO uint32_t HRBAR29    : 1;
+  __IO uint32_t HRBAR30    : 1;
+  __IO uint32_t HRBAR31    : 1;
+} stc_ethernet_mac_chrbar_field_t;
+
+/* ETHERNET_CONTROL_MODULE register bit fields */
+typedef struct stc_ethernet_control_eth_mode_field
+{
+  __IO uint32_t IFMODE     : 1;
+       uint32_t RESERVED1  : 7;
+  __IO uint32_t RST0       : 1;
+  __IO uint32_t RST1       : 1;
+       uint32_t RESERVED2  :18;
+  __IO uint32_t ASZPPSSEL  : 1;
+} stc_ethernet_control_eth_mode_field_t;
+
+typedef struct stc_ethernet_control_eth_clkg_field
+{
+  __IO uint32_t MACEN0     : 1;
+  __IO uint32_t MACEN1     : 1;
+} stc_ethernet_control_eth_clkg_field_t;
+
+/******************************************************************************
+ * Peripheral register structures
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t FASZR;
+    stc_flash_if_faszr_field_t FASZR_f;
+  };
+  union {
+    __IO uint32_t FRWTR;
+    stc_flash_if_frwtr_field_t FRWTR_f;
+  };
+  union {
+    __IO uint32_t FSTR;
+    stc_flash_if_fstr_field_t FSTR_f;
+  };
+        uint8_t RESERVED0[4];
+  union {
+    __IO uint32_t FSYNDN;
+    stc_flash_if_fsyndn_field_t FSYNDN_f;
+  };
+        uint8_t RESERVED1[236];
+  union {
+    __IO uint32_t CRTRMM;
+    stc_flash_if_crtrmm_field_t CRTRMM_f;
+  };
+}FM3_FLASH_IF_TypeDef;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock and reset registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SCM_CTL;
+    stc_crg_scm_ctl_field_t SCM_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t SCM_STR;
+    stc_crg_scm_str_field_t SCM_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  __IO uint32_t STB_CTL;
+  union {
+    __IO uint16_t RST_STR;
+    stc_crg_rst_str_field_t RST_STR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t BSC_PSR;
+    stc_crg_bsc_psr_field_t BSC_PSR_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t APBC0_PSR;
+    stc_crg_apbc0_psr_field_t APBC0_PSR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t APBC1_PSR;
+    stc_crg_apbc1_psr_field_t APBC1_PSR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t APBC2_PSR;
+    stc_crg_apbc2_psr_field_t APBC2_PSR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t SWC_PSR;
+    stc_crg_swc_psr_field_t SWC_PSR_f;
+  };
+        uint8_t RESERVED7[7];
+  union {
+    __IO  uint8_t TTC_PSR;
+    stc_crg_ttc_psr_field_t TTC_PSR_f;
+  };
+        uint8_t RESERVED8[7];
+  union {
+    __IO  uint8_t CSW_TMR;
+    stc_crg_csw_tmr_field_t CSW_TMR_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t PSW_TMR;
+    stc_crg_psw_tmr_field_t PSW_TMR_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PLL_CTL1;
+    stc_crg_pll_ctl1_field_t PLL_CTL1_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t PLL_CTL2;
+    stc_crg_pll_ctl2_field_t PLL_CTL2_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO uint16_t CSV_CTL;
+    stc_crg_csv_ctl_field_t CSV_CTL_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO  uint8_t CSV_STR;
+    stc_crg_csv_str_field_t CSV_STR_f;
+  };
+        uint8_t RESERVED14[3];
+  __IO uint16_t FCSWH_CTL;
+        uint8_t RESERVED15[2];
+  __IO uint16_t FCSWL_CTL;
+        uint8_t RESERVED16[2];
+  __IO uint16_t FCSWD_CTL;
+        uint8_t RESERVED17[2];
+  union {
+    __IO  uint8_t DBWDT_CTL;
+    stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
+  };
+        uint8_t RESERVED18[11];
+  union {
+    __IO  uint8_t INT_ENR;
+    stc_crg_int_enr_field_t INT_ENR_f;
+  };
+        uint8_t RESERVED19[3];
+  union {
+    __IO  uint8_t INT_STR;
+    stc_crg_int_str_field_t INT_STR_f;
+  };
+        uint8_t RESERVED20[3];
+  union {
+    __IO  uint8_t INT_CLR;
+    stc_crg_int_clr_field_t INT_CLR_f;
+  };
+}FM3_CRG_TypeDef;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* Hardware watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDG_LDR;
+  __IO uint32_t WDG_VLR;
+  union {
+    __IO  uint8_t WDG_CTL;
+    stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO  uint8_t WDG_ICL;
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t WDG_RIS;
+    stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
+  };
+        uint8_t RESERVED2[3055];
+  __IO uint32_t WDG_LCK;
+}FM3_HWWDT_TypeDef;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* Software watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDOGLOAD;
+  __IO uint32_t WDOGVALUE;
+  union {
+    __IO  uint8_t WDOGCONTROL;
+    stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t WDOGINTCLR;
+  union {
+    __IO  uint8_t WDOGRIS;
+    stc_swwdt_wdogris_field_t WDOGRIS_f;
+  };
+        uint8_t RESERVED1[3055];
+  __IO uint32_t WDOGLOCK;
+}FM3_SWWDT_TypeDef;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* Dual timer 1/2 registers */
+typedef struct
+{
+  __IO uint32_t TIMER1LOAD;
+  __IO uint32_t TIMER1VALUE;
+  union {
+    __IO uint32_t TIMER1CONTROL;
+    stc_dtim_timer1control_field_t TIMER1CONTROL_f;
+  };
+  __IO uint32_t TIMER1INTCLR;
+  union {
+    __IO uint32_t TIMER1RIS;
+    stc_dtim_timer1ris_field_t TIMER1RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER1MIS;
+    stc_dtim_timer1mis_field_t TIMER1MIS_f;
+  };
+  __IO uint32_t TIMER1BGLOAD;
+        uint8_t RESERVED0[4];
+  __IO uint32_t TIMER2LOAD;
+  __IO uint32_t TIMER2VALUE;
+  union {
+    __IO uint32_t TIMER2CONTROL;
+    stc_dtim_timer2control_field_t TIMER2CONTROL_f;
+  };
+  __IO uint32_t TIMER2INTCLR;
+  union {
+    __IO uint32_t TIMER2RIS;
+    stc_dtim_timer2ris_field_t TIMER2RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER2MIS;
+    stc_dtim_timer2mis_field_t TIMER2MIS_f;
+  };
+  __IO uint32_t TIMER2BGLOAD;
+}FM3_DTIM_TypeDef;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Free Running Timer registers */
+typedef struct
+{
+        uint8_t RESERVED0[40];
+  __IO uint16_t TCCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TCDT0;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TCSA0;
+    stc_mft_frt_tcsa0_field_t TCSA0_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t TCSB0;
+    stc_mft_frt_tcsb0_field_t TCSB0_f;
+  };
+        uint8_t RESERVED4[2];
+  __IO uint16_t TCCP1;
+        uint8_t RESERVED5[2];
+  __IO uint16_t TCDT1;
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t TCSA1;
+    stc_mft_frt_tcsa1_field_t TCSA1_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t TCSB1;
+    stc_mft_frt_tcsb1_field_t TCSB1_f;
+  };
+        uint8_t RESERVED8[2];
+  __IO uint16_t TCCP2;
+        uint8_t RESERVED9[2];
+  __IO uint16_t TCDT2;
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t TCSA2;
+    stc_mft_frt_tcsa2_field_t TCSA2_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t TCSB2;
+    stc_mft_frt_tcsb2_field_t TCSB2_f;
+  };
+}FM3_MFT_FRT_TypeDef;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+typedef struct
+{
+  __IO uint16_t OCCP0;
+        uint8_t RESERVED0[2];
+  __IO uint16_t OCCP1;
+        uint8_t RESERVED1[2];
+  __IO uint16_t OCCP2;
+        uint8_t RESERVED2[2];
+  __IO uint16_t OCCP3;
+        uint8_t RESERVED3[2];
+  __IO uint16_t OCCP4;
+        uint8_t RESERVED4[2];
+  __IO uint16_t OCCP5;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t OCSA10;
+    stc_mft_ocu_ocsa10_field_t OCSA10_f;
+  };
+  union {
+    __IO  uint8_t OCSB10;
+    stc_mft_ocu_ocsb10_field_t OCSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t OCSA32;
+    stc_mft_ocu_ocsa32_field_t OCSA32_f;
+  };
+  union {
+    __IO  uint8_t OCSB32;
+    stc_mft_ocu_ocsb32_field_t OCSB32_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO  uint8_t OCSA54;
+    stc_mft_ocu_ocsa54_field_t OCSA54_f;
+  };
+  union {
+    __IO  uint8_t OCSB54;
+    stc_mft_ocu_ocsb54_field_t OCSB54_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t OCSC;
+    stc_mft_ocu_ocsc_field_t OCSC_f;
+  };
+        uint8_t RESERVED9[50];
+  union {
+    __IO  uint8_t OCFS10;
+    stc_mft_ocu_ocfs10_field_t OCFS10_f;
+  };
+  union {
+    __IO  uint8_t OCFS32;
+    stc_mft_ocu_ocfs32_field_t OCFS32_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO  uint8_t OCFS54;
+    stc_mft_ocu_ocfs54_field_t OCFS54_f;
+  };
+}FM3_MFT_OCU_TypeDef;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+typedef struct
+{
+        uint8_t RESERVED0[128];
+  __IO uint16_t WFTM10;
+        uint8_t RESERVED1[2];
+  __IO uint16_t WFTM32;
+        uint8_t RESERVED2[2];
+  __IO uint16_t WFTM54;
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t WFSA10;
+    stc_mft_wfg_wfsa10_field_t WFSA10_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t WFSA32;
+    stc_mft_wfg_wfsa32_field_t WFSA32_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t WFSA54;
+    stc_mft_wfg_wfsa54_field_t WFSA54_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t WFIR;
+    stc_mft_wfg_wfir_field_t WFIR_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t NZCL;
+    stc_mft_wfg_nzcl_field_t NZCL_f;
+  };
+}FM3_MFT_WFG_TypeDef;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[96];
+  union {
+    __IO  uint8_t ICFS10;
+    stc_mft_icu_icfs10_field_t ICFS10_f;
+  };
+  union {
+    __IO  uint8_t ICFS32;
+    stc_mft_icu_icfs32_field_t ICFS32_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint16_t ICCP0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ICCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ICCP2;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ICCP3;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t ICSA10;
+    stc_mft_icu_icsa10_field_t ICSA10_f;
+  };
+  union {
+    __IO  uint8_t ICSB10;
+    stc_mft_icu_icsb10_field_t ICSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ICSA32;
+    stc_mft_icu_icsa32_field_t ICSA32_f;
+  };
+  union {
+    __IO  uint8_t ICSB32;
+    stc_mft_icu_icsb32_field_t ICSB32_f;
+  };
+}FM3_MFT_ICU_TypeDef;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[160];
+  __IO uint16_t ACCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t ACCPDN0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ACCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ACCPDN1;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ACCP2;
+        uint8_t RESERVED5[2];
+  __IO uint16_t ACCPDN2;
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ACSB;
+    stc_mft_adcmp_acsb_field_t ACSB_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t ACSA;
+    stc_mft_adcmp_acsa_field_t ACSA_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t ATSA;
+    stc_mft_adcmp_atsa_field_t ATSA_f;
+  };
+}FM3_MFT_ADCMP_TypeDef;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer PPG registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t TTCR0;
+    stc_mft_ppg_ttcr0_field_t TTCR0_f;
+  };
+        uint8_t RESERVED1[7];
+  __IO  uint8_t COMP0;
+        uint8_t RESERVED2[2];
+  __IO  uint8_t COMP2;
+        uint8_t RESERVED3[4];
+  __IO  uint8_t COMP4;
+        uint8_t RESERVED4[2];
+  __IO  uint8_t COMP6;
+        uint8_t RESERVED5[12];
+  union {
+    __IO  uint8_t TTCR1;
+    stc_mft_ppg_ttcr1_field_t TTCR1_f;
+  };
+        uint8_t RESERVED6[7];
+  __IO  uint8_t COMP1;
+        uint8_t RESERVED7[2];
+  __IO  uint8_t COMP3;
+        uint8_t RESERVED8[4];
+  __IO  uint8_t COMP5;
+        uint8_t RESERVED9[2];
+  __IO  uint8_t COMP7;
+        uint8_t RESERVED10[12];
+  union {
+    __IO  uint8_t TTCR2;
+    stc_mft_ppg_ttcr2_field_t TTCR2_f;
+  };
+        uint8_t RESERVED11[7];
+  __IO  uint8_t COMP8;
+        uint8_t RESERVED12[2];
+  __IO  uint8_t COMP10;
+        uint8_t RESERVED13[4];
+  __IO  uint8_t COMP12;
+        uint8_t RESERVED14[2];
+  __IO  uint8_t COMP14;
+        uint8_t RESERVED15[171];
+  union {
+    __IO uint16_t TRG;
+    stc_mft_ppg_trg_field_t TRG_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t REVC;
+    stc_mft_ppg_revc_field_t REVC_f;
+  };
+        uint8_t RESERVED17[58];
+  union {
+    __IO uint16_t TRG1;
+    stc_mft_ppg_trg1_field_t TRG1_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t REVC1;
+    stc_mft_ppg_revc1_field_t REVC1_f;
+  };
+        uint8_t RESERVED19[186];
+  union {
+    __IO  uint8_t PPGC1;
+    stc_mft_ppg_ppgc1_field_t PPGC1_f;
+  };
+  union {
+    __IO  uint8_t PPGC0;
+    stc_mft_ppg_ppgc0_field_t PPGC0_f;
+  };
+        uint8_t RESERVED20[2];
+  union {
+    __IO  uint8_t PPGC3;
+    stc_mft_ppg_ppgc3_field_t PPGC3_f;
+  };
+  union {
+    __IO  uint8_t PPGC2;
+    stc_mft_ppg_ppgc2_field_t PPGC2_f;
+  };
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t PRL0;
+    struct {
+      __IO  uint8_t PRLL0;
+      __IO  uint8_t PRLH0;
+    };
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t PRL1;
+    struct {
+      __IO  uint8_t PRLL1;
+      __IO  uint8_t PRLH1;
+    };
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t PRL2;
+    struct {
+      __IO  uint8_t PRLL2;
+      __IO  uint8_t PRLH2;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t PRL3;
+    struct {
+      __IO  uint8_t PRLL3;
+      __IO  uint8_t PRLH3;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO  uint8_t GATEC0;
+    stc_mft_ppg_gatec0_field_t GATEC0_f;
+  };
+        uint8_t RESERVED26[39];
+  union {
+    __IO  uint8_t PPGC5;
+    stc_mft_ppg_ppgc5_field_t PPGC5_f;
+  };
+  union {
+    __IO  uint8_t PPGC4;
+    stc_mft_ppg_ppgc4_field_t PPGC4_f;
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO  uint8_t PPGC7;
+    stc_mft_ppg_ppgc7_field_t PPGC7_f;
+  };
+  union {
+    __IO  uint8_t PPGC6;
+    stc_mft_ppg_ppgc6_field_t PPGC6_f;
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t PRL4;
+    struct {
+      __IO  uint8_t PRLL4;
+      __IO  uint8_t PRLH4;
+    };
+  };
+        uint8_t RESERVED29[2];
+  union {
+    __IO uint16_t PRL5;
+    struct {
+      __IO  uint8_t PRLL5;
+      __IO  uint8_t PRLH5;
+    };
+  };
+        uint8_t RESERVED30[2];
+  union {
+    __IO uint16_t PRL6;
+    struct {
+      __IO  uint8_t PRLL6;
+      __IO  uint8_t PRLH6;
+    };
+  };
+        uint8_t RESERVED31[2];
+  union {
+    __IO uint16_t PRL7;
+    struct {
+      __IO  uint8_t PRLL7;
+      __IO  uint8_t PRLH7;
+    };
+  };
+        uint8_t RESERVED32[2];
+  union {
+    __IO  uint8_t GATEC4;
+    stc_mft_ppg_gatec4_field_t GATEC4_f;
+  };
+        uint8_t RESERVED33[39];
+  union {
+    __IO  uint8_t PPGC9;
+    stc_mft_ppg_ppgc9_field_t PPGC9_f;
+  };
+  union {
+    __IO  uint8_t PPGC8;
+    stc_mft_ppg_ppgc8_field_t PPGC8_f;
+  };
+        uint8_t RESERVED34[2];
+  union {
+    __IO  uint8_t PPGC11;
+    stc_mft_ppg_ppgc11_field_t PPGC11_f;
+  };
+  union {
+    __IO  uint8_t PPGC10;
+    stc_mft_ppg_ppgc10_field_t PPGC10_f;
+  };
+        uint8_t RESERVED35[2];
+  union {
+    __IO uint16_t PRL8;
+    struct {
+      __IO  uint8_t PRLL8;
+      __IO  uint8_t PRLH8;
+    };
+  };
+        uint8_t RESERVED36[2];
+  union {
+    __IO uint16_t PRL9;
+    struct {
+      __IO  uint8_t PRLL9;
+      __IO  uint8_t PRLH9;
+    };
+  };
+        uint8_t RESERVED37[2];
+  union {
+    __IO uint16_t PRL10;
+    struct {
+      __IO  uint8_t PRLL10;
+      __IO  uint8_t PRLH10;
+    };
+  };
+        uint8_t RESERVED38[2];
+  union {
+    __IO uint16_t PRL11;
+    struct {
+      __IO  uint8_t PRLL11;
+      __IO  uint8_t PRLH11;
+    };
+  };
+        uint8_t RESERVED39[2];
+  union {
+    __IO  uint8_t GATEC8;
+    stc_mft_ppg_gatec8_field_t GATEC8_f;
+  };
+        uint8_t RESERVED40[39];
+  union {
+    __IO  uint8_t PPGC13;
+    stc_mft_ppg_ppgc13_field_t PPGC13_f;
+  };
+  union {
+    __IO  uint8_t PPGC12;
+    stc_mft_ppg_ppgc12_field_t PPGC12_f;
+  };
+        uint8_t RESERVED41[2];
+  union {
+    __IO  uint8_t PPGC15;
+    stc_mft_ppg_ppgc15_field_t PPGC15_f;
+  };
+  union {
+    __IO  uint8_t PPGC14;
+    stc_mft_ppg_ppgc14_field_t PPGC14_f;
+  };
+        uint8_t RESERVED42[2];
+  union {
+    __IO uint16_t PRL12;
+    struct {
+      __IO  uint8_t PRLL12;
+      __IO  uint8_t PRLH12;
+    };
+  };
+        uint8_t RESERVED43[2];
+  union {
+    __IO uint16_t PRL13;
+    struct {
+      __IO  uint8_t PRLL13;
+      __IO  uint8_t PRLH13;
+    };
+  };
+        uint8_t RESERVED44[2];
+  union {
+    __IO uint16_t PRL14;
+    struct {
+      __IO  uint8_t PRLL14;
+      __IO  uint8_t PRLH14;
+    };
+  };
+        uint8_t RESERVED45[2];
+  union {
+    __IO uint16_t PRL15;
+    struct {
+      __IO  uint8_t PRLL15;
+      __IO  uint8_t PRLH15;
+    };
+  };
+        uint8_t RESERVED46[2];
+  union {
+    __IO  uint8_t GATEC12;
+    stc_mft_ppg_gatec12_field_t GATEC12_f;
+  };
+        uint8_t RESERVED47[39];
+  union {
+    __IO  uint8_t PPGC17;
+    stc_mft_ppg_ppgc17_field_t PPGC17_f;
+  };
+  union {
+    __IO  uint8_t PPGC16;
+    stc_mft_ppg_ppgc16_field_t PPGC16_f;
+  };
+        uint8_t RESERVED48[2];
+  union {
+    __IO  uint8_t PPGC19;
+    stc_mft_ppg_ppgc19_field_t PPGC19_f;
+  };
+  union {
+    __IO  uint8_t PPGC18;
+    stc_mft_ppg_ppgc18_field_t PPGC18_f;
+  };
+        uint8_t RESERVED49[2];
+  union {
+    __IO uint16_t PRL16;
+    struct {
+      __IO  uint8_t PRLL16;
+      __IO  uint8_t PRLH16;
+    };
+  };
+        uint8_t RESERVED50[2];
+  union {
+    __IO uint16_t PRL17;
+    struct {
+      __IO  uint8_t PRLL17;
+      __IO  uint8_t PRLH17;
+    };
+  };
+        uint8_t RESERVED51[2];
+  union {
+    __IO uint16_t PRL18;
+    struct {
+      __IO  uint8_t PRLL18;
+      __IO  uint8_t PRLH18;
+    };
+  };
+        uint8_t RESERVED52[2];
+  union {
+    __IO uint16_t PRL19;
+    struct {
+      __IO  uint8_t PRLL19;
+      __IO  uint8_t PRLH19;
+    };
+  };
+        uint8_t RESERVED53[2];
+  union {
+    __IO  uint8_t GATEC16;
+    stc_mft_ppg_gatec16_field_t GATEC16_f;
+  };
+        uint8_t RESERVED54[39];
+  union {
+    __IO  uint8_t PPGC21;
+    stc_mft_ppg_ppgc21_field_t PPGC21_f;
+  };
+  union {
+    __IO  uint8_t PPGC20;
+    stc_mft_ppg_ppgc20_field_t PPGC20_f;
+  };
+        uint8_t RESERVED55[2];
+  union {
+    __IO  uint8_t PPGC23;
+    stc_mft_ppg_ppgc23_field_t PPGC23_f;
+  };
+  union {
+    __IO  uint8_t PPGC22;
+    stc_mft_ppg_ppgc22_field_t PPGC22_f;
+  };
+        uint8_t RESERVED56[2];
+  union {
+    __IO uint16_t PRL20;
+    struct {
+      __IO  uint8_t PRLL20;
+      __IO  uint8_t PRLH20;
+    };
+  };
+        uint8_t RESERVED57[2];
+  union {
+    __IO uint16_t PRL21;
+    struct {
+      __IO  uint8_t PRLL21;
+      __IO  uint8_t PRLH21;
+    };
+  };
+        uint8_t RESERVED58[2];
+  union {
+    __IO uint16_t PRL22;
+    struct {
+      __IO  uint8_t PRLL22;
+      __IO  uint8_t PRLH22;
+    };
+  };
+        uint8_t RESERVED59[2];
+  union {
+    __IO uint16_t PRL23;
+    struct {
+      __IO  uint8_t PRLL23;
+      __IO  uint8_t PRLH23;
+    };
+  };
+        uint8_t RESERVED60[2];
+  union {
+    __IO  uint8_t GATEC20;
+    stc_mft_ppg_gatec20_field_t GATEC20_f;
+  };
+}FM3_MFT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PPG registers */
+typedef struct
+{
+  __IO uint16_t PRLL;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PRLH;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_ppg_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_ppg_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_ppg_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWM registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PDUT;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwm_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwm_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwm_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWM_TypeDef;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* Base Timer 0 RT registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[6];
+  __IO uint16_t TMR;
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_rt_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_rt_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_rt_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_RT_TypeDef;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWC registers */
+typedef struct
+{
+        uint8_t RESERVED0[4];
+  __IO uint16_t DTBF;
+        uint8_t RESERVED1[6];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwc_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwc_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwc_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWC_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL0123;
+    stc_btiosel03_btsel0123_field_t BTSEL0123_f;
+  };
+}FM3_BTIOSEL03_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL4567;
+    stc_btiosel47_btsel4567_field_t BTSEL4567_f;
+  };
+}FM3_BTIOSEL47_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL8B_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL89AB;
+    stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f;
+  };
+}FM3_BTIOSEL8B_TypeDef;
+
+/******************************************************************************
+ * BTIOSELCF_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSELCDEF;
+    stc_btioselcf_btselcdef_field_t BTSELCDEF_f;
+  };
+}FM3_BTIOSELCF_TypeDef;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* Software based Simulation Startup (Base Timer) register */
+typedef struct
+{
+  union {
+    __IO uint16_t BTSSSR;
+    stc_sbssr_btsssr_field_t BTSSSR_f;
+  };
+}FM3_SBSSR_TypeDef;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* Quad position and revolution counter channel 0 registers */
+typedef struct
+{
+  __IO uint16_t QPCR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t QRCR;
+        uint8_t RESERVED1[2];
+  __IO uint16_t QPCCR;
+        uint8_t RESERVED2[2];
+  __IO uint16_t QPRCR;
+        uint8_t RESERVED3[2];
+  __IO uint16_t QMPR;
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t QICR;
+      stc_qprc_qicr_field_t QICR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QICRL;
+        stc_qprc_qicrl_field_t QICRL_f;
+      };
+      union {
+        __IO  uint8_t QICRH;
+        stc_qprc_qicrh_field_t QICRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t QCR;
+      stc_qprc_qcr_field_t QCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QCRL;
+        stc_qprc_qcrl_field_t QCRL_f;
+      };
+      union {
+        __IO  uint8_t QCRH;
+        stc_qprc_qcrh_field_t QCRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t QECR;
+    stc_qprc_qecr_field_t QECR_f;
+  };
+        uint8_t RESERVED7[30];
+  __IO uint16_t QRCRR;
+  __IO uint16_t QPCRR;
+}FM3_QPRC_TypeDef;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* 12-bit ADC unit 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t ADSR;
+    stc_adc_adsr_field_t ADSR_f;
+  };
+  union {
+    __IO  uint8_t ADCR;
+    stc_adc_adcr_field_t ADCR_f;
+  };
+        uint8_t RESERVED0[6];
+  union {
+    __IO  uint8_t SFNS;
+    stc_adc_sfns_field_t SFNS_f;
+  };
+  union {
+    __IO  uint8_t SCCR;
+    stc_adc_sccr_field_t SCCR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint32_t SCFD;
+      stc_adc_scfd_field_t SCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t SCFDL;
+        stc_adc_scfdl_field_t SCFDL_f;
+      };
+      union {
+        __IO uint16_t SCFDH;
+        stc_adc_scfdh_field_t SCFDH_f;
+      };
+    };
+  };
+  union {
+    union {
+      __IO uint16_t SCIS23;
+      stc_adc_scis23_field_t SCIS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS2;
+        stc_adc_scis2_field_t SCIS2_f;
+      };
+      union {
+        __IO  uint8_t SCIS3;
+        stc_adc_scis3_field_t SCIS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t SCIS01;
+      stc_adc_scis01_field_t SCIS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS0;
+        stc_adc_scis0_field_t SCIS0_f;
+      };
+      union {
+        __IO  uint8_t SCIS1;
+        stc_adc_scis1_field_t SCIS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t PFNS;
+    stc_adc_pfns_field_t PFNS_f;
+  };
+  union {
+    __IO  uint8_t PCCR;
+    stc_adc_pccr_field_t PCCR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint32_t PCFD;
+      stc_adc_pcfd_field_t PCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t PCFDL;
+        stc_adc_pcfdl_field_t PCFDL_f;
+      };
+      union {
+        __IO uint16_t PCFDH;
+        stc_adc_pcfdh_field_t PCFDH_f;
+      };
+    };
+  };
+  union {
+    __IO  uint8_t PCIS;
+    stc_adc_pcis_field_t PCIS_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t CMPCR;
+    stc_adc_cmpcr_field_t CMPCR_f;
+  };
+        uint8_t RESERVED6;
+  union {
+    __IO uint16_t CMPD;
+    stc_adc_cmpd_field_t CMPD_f;
+  };
+  union {
+    union {
+      __IO uint16_t ADSS23;
+      stc_adc_adss23_field_t ADSS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS2;
+        stc_adc_adss2_field_t ADSS2_f;
+      };
+      union {
+        __IO  uint8_t ADSS3;
+        stc_adc_adss3_field_t ADSS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED7[2];
+  union {
+    union {
+      __IO uint16_t ADSS01;
+      stc_adc_adss01_field_t ADSS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS0;
+        stc_adc_adss0_field_t ADSS0_f;
+      };
+      union {
+        __IO  uint8_t ADSS1;
+        stc_adc_adss1_field_t ADSS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED8[2];
+  union {
+    union {
+      __IO uint16_t ADST01;
+      stc_adc_adst01_field_t ADST01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADST1;
+        stc_adc_adst1_field_t ADST1_f;
+      };
+      union {
+        __IO  uint8_t ADST0;
+        stc_adc_adst0_field_t ADST0_f;
+      };
+    };
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO  uint8_t ADCT;
+    stc_adc_adct_field_t ADCT_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PRTSL;
+    stc_adc_prtsl_field_t PRTSL_f;
+  };
+  union {
+    __IO  uint8_t SCTSL;
+    stc_adc_sctsl_field_t SCTSL_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO  uint8_t ADCEN;
+    stc_adc_adcen_field_t ADCEN_f;
+  };
+}FM3_ADC_TypeDef;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CR trimming registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t MCR_PSR;
+    stc_crtrim_mcr_psr_field_t MCR_PSR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO uint16_t MCR_FTRM;
+    stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint32_t MCR_RLR;
+}FM3_CRTRIM_TypeDef;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* External interrupt registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ENIR;
+    stc_exti_enir_field_t ENIR_f;
+  };
+  union {
+    __IO uint32_t EIRR;
+    stc_exti_eirr_field_t EIRR_f;
+  };
+  union {
+    __IO uint32_t EICL;
+    stc_exti_eicl_field_t EICL_f;
+  };
+  union {
+    __IO uint32_t ELVR;
+    stc_exti_elvr_field_t ELVR_f;
+  };
+  union {
+    __IO uint32_t ELVR1;
+    stc_exti_elvr1_field_t ELVR1_f;
+  };
+  union {
+    __IO  uint8_t NMIRR;
+    stc_exti_nmirr_field_t NMIRR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t NMICL;
+    stc_exti_nmicl_field_t NMICL_f;
+  };
+}FM3_EXTI_TypeDef;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* Interrupt request read registers */
+typedef struct
+{
+  union {
+    __IO uint32_t DRQSEL;
+    stc_intreq_drqsel_field_t DRQSEL_f;
+  };
+        uint8_t RESERVED0[7];
+  union {
+    __IO  uint8_t ODDPKS;
+    stc_intreq_oddpks_field_t ODDPKS_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t EXC02MON;
+    stc_intreq_exc02mon_field_t EXC02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ00MON;
+    stc_intreq_irq00mon_field_t IRQ00MON_f;
+  };
+  union {
+    __IO uint32_t IRQ01MON;
+    stc_intreq_irq01mon_field_t IRQ01MON_f;
+  };
+  union {
+    __IO uint32_t IRQ02MON;
+    stc_intreq_irq02mon_field_t IRQ02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ03MON;
+    stc_intreq_irq03mon_field_t IRQ03MON_f;
+  };
+  union {
+    __IO uint32_t IRQ04MON;
+    stc_intreq_irq04mon_field_t IRQ04MON_f;
+  };
+  union {
+    __IO uint32_t IRQ05MON;
+    stc_intreq_irq05mon_field_t IRQ05MON_f;
+  };
+  union {
+    __IO uint32_t IRQ06MON;
+    stc_intreq_irq06mon_field_t IRQ06MON_f;
+  };
+  union {
+    __IO uint32_t IRQ07MON;
+    stc_intreq_irq07mon_field_t IRQ07MON_f;
+  };
+  union {
+    __IO uint32_t IRQ08MON;
+    stc_intreq_irq08mon_field_t IRQ08MON_f;
+  };
+  union {
+    __IO uint32_t IRQ09MON;
+    stc_intreq_irq09mon_field_t IRQ09MON_f;
+  };
+  union {
+    __IO uint32_t IRQ10MON;
+    stc_intreq_irq10mon_field_t IRQ10MON_f;
+  };
+  union {
+    __IO uint32_t IRQ11MON;
+    stc_intreq_irq11mon_field_t IRQ11MON_f;
+  };
+  union {
+    __IO uint32_t IRQ12MON;
+    stc_intreq_irq12mon_field_t IRQ12MON_f;
+  };
+  union {
+    __IO uint32_t IRQ13MON;
+    stc_intreq_irq13mon_field_t IRQ13MON_f;
+  };
+  union {
+    __IO uint32_t IRQ14MON;
+    stc_intreq_irq14mon_field_t IRQ14MON_f;
+  };
+  union {
+    __IO uint32_t IRQ15MON;
+    stc_intreq_irq15mon_field_t IRQ15MON_f;
+  };
+  union {
+    __IO uint32_t IRQ16MON;
+    stc_intreq_irq16mon_field_t IRQ16MON_f;
+  };
+  union {
+    __IO uint32_t IRQ17MON;
+    stc_intreq_irq17mon_field_t IRQ17MON_f;
+  };
+  union {
+    __IO uint32_t IRQ18MON;
+    stc_intreq_irq18mon_field_t IRQ18MON_f;
+  };
+  union {
+    __IO uint32_t IRQ19MON;
+    stc_intreq_irq19mon_field_t IRQ19MON_f;
+  };
+  union {
+    __IO uint32_t IRQ20MON;
+    stc_intreq_irq20mon_field_t IRQ20MON_f;
+  };
+  union {
+    __IO uint32_t IRQ21MON;
+    stc_intreq_irq21mon_field_t IRQ21MON_f;
+  };
+  union {
+    __IO uint32_t IRQ22MON;
+    stc_intreq_irq22mon_field_t IRQ22MON_f;
+  };
+  union {
+    __IO uint32_t IRQ23MON;
+    stc_intreq_irq23mon_field_t IRQ23MON_f;
+  };
+  union {
+    __IO uint32_t IRQ24MON;
+    stc_intreq_irq24mon_field_t IRQ24MON_f;
+  };
+  union {
+    __IO uint32_t IRQ25MON;
+    stc_intreq_irq25mon_field_t IRQ25MON_f;
+  };
+  union {
+    __IO uint32_t IRQ26MON;
+    stc_intreq_irq26mon_field_t IRQ26MON_f;
+  };
+  union {
+    __IO uint32_t IRQ27MON;
+    stc_intreq_irq27mon_field_t IRQ27MON_f;
+  };
+  union {
+    __IO uint32_t IRQ28MON;
+    stc_intreq_irq28mon_field_t IRQ28MON_f;
+  };
+  union {
+    __IO uint32_t IRQ29MON;
+    stc_intreq_irq29mon_field_t IRQ29MON_f;
+  };
+  union {
+    __IO uint32_t IRQ30MON;
+    stc_intreq_irq30mon_field_t IRQ30MON_f;
+  };
+  union {
+    __IO uint32_t IRQ31MON;
+    stc_intreq_irq31mon_field_t IRQ31MON_f;
+  };
+  union {
+    __IO uint32_t IRQ32MON;
+    stc_intreq_irq32mon_field_t IRQ32MON_f;
+  };
+  union {
+    __IO uint32_t IRQ33MON;
+    stc_intreq_irq33mon_field_t IRQ33MON_f;
+  };
+  union {
+    __IO uint32_t IRQ34MON;
+    stc_intreq_irq34mon_field_t IRQ34MON_f;
+  };
+  union {
+    __IO uint32_t IRQ35MON;
+    stc_intreq_irq35mon_field_t IRQ35MON_f;
+  };
+  union {
+    __IO uint32_t IRQ36MON;
+    stc_intreq_irq36mon_field_t IRQ36MON_f;
+  };
+  union {
+    __IO uint32_t IRQ37MON;
+    stc_intreq_irq37mon_field_t IRQ37MON_f;
+  };
+  union {
+    __IO uint32_t IRQ38MON;
+    stc_intreq_irq38mon_field_t IRQ38MON_f;
+  };
+  union {
+    __IO uint32_t IRQ39MON;
+    stc_intreq_irq39mon_field_t IRQ39MON_f;
+  };
+  union {
+    __IO uint32_t IRQ40MON;
+    stc_intreq_irq40mon_field_t IRQ40MON_f;
+  };
+  union {
+    __IO uint32_t IRQ41MON;
+    stc_intreq_irq41mon_field_t IRQ41MON_f;
+  };
+  union {
+    __IO uint32_t IRQ42MON;
+    stc_intreq_irq42mon_field_t IRQ42MON_f;
+  };
+  union {
+    __IO uint32_t IRQ43MON;
+    stc_intreq_irq43mon_field_t IRQ43MON_f;
+  };
+  union {
+    __IO uint32_t IRQ44MON;
+    stc_intreq_irq44mon_field_t IRQ44MON_f;
+  };
+  union {
+    __IO uint32_t IRQ45MON;
+    stc_intreq_irq45mon_field_t IRQ45MON_f;
+  };
+  union {
+    __IO uint32_t IRQ46MON;
+    stc_intreq_irq46mon_field_t IRQ46MON_f;
+  };
+        uint8_t RESERVED2[300];
+  union {
+    __IO uint32_t DRQSEL1;
+    stc_intreq_drqsel1_field_t DRQSEL1_f;
+  };
+  union {
+    __IO uint32_t DQESEL;
+    stc_intreq_dqesel_field_t DQESEL_f;
+  };
+        uint8_t RESERVED3[7];
+  union {
+    __IO  uint8_t ODDPKS1;
+    stc_intreq_oddpks1_field_t ODDPKS1_f;
+  };
+}FM3_INTREQ_TypeDef;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* General purpose I/O registers */
+typedef struct
+{
+  union {
+    __IO uint32_t PFR0;
+    stc_gpio_pfr0_field_t PFR0_f;
+  };
+  union {
+    __IO uint32_t PFR1;
+    stc_gpio_pfr1_field_t PFR1_f;
+  };
+  union {
+    __IO uint32_t PFR2;
+    stc_gpio_pfr2_field_t PFR2_f;
+  };
+  union {
+    __IO uint32_t PFR3;
+    stc_gpio_pfr3_field_t PFR3_f;
+  };
+  union {
+    __IO uint32_t PFR4;
+    stc_gpio_pfr4_field_t PFR4_f;
+  };
+  union {
+    __IO uint32_t PFR5;
+    stc_gpio_pfr5_field_t PFR5_f;
+  };
+  union {
+    __IO uint32_t PFR6;
+    stc_gpio_pfr6_field_t PFR6_f;
+  };
+  union {
+    __IO uint32_t PFR7;
+    stc_gpio_pfr7_field_t PFR7_f;
+  };
+  union {
+    __IO uint32_t PFR8;
+    stc_gpio_pfr8_field_t PFR8_f;
+  };
+  __IO uint32_t PFR9;
+  union {
+    __IO uint32_t PFRA;
+    stc_gpio_pfra_field_t PFRA_f;
+  };
+  __IO uint32_t PFRB;
+  union {
+    __IO uint32_t PFRC;
+    stc_gpio_pfrc_field_t PFRC_f;
+  };
+  union {
+    __IO uint32_t PFRD;
+    stc_gpio_pfrd_field_t PFRD_f;
+  };
+  union {
+    __IO uint32_t PFRE;
+    stc_gpio_pfre_field_t PFRE_f;
+  };
+  union {
+    __IO uint32_t PFRF;
+    stc_gpio_pfrf_field_t PFRF_f;
+  };
+        uint8_t RESERVED0[192];
+  union {
+    __IO uint32_t PCR0;
+    stc_gpio_pcr0_field_t PCR0_f;
+  };
+  union {
+    __IO uint32_t PCR1;
+    stc_gpio_pcr1_field_t PCR1_f;
+  };
+  union {
+    __IO uint32_t PCR2;
+    stc_gpio_pcr2_field_t PCR2_f;
+  };
+  union {
+    __IO uint32_t PCR3;
+    stc_gpio_pcr3_field_t PCR3_f;
+  };
+  union {
+    __IO uint32_t PCR4;
+    stc_gpio_pcr4_field_t PCR4_f;
+  };
+  union {
+    __IO uint32_t PCR5;
+    stc_gpio_pcr5_field_t PCR5_f;
+  };
+  union {
+    __IO uint32_t PCR6;
+    stc_gpio_pcr6_field_t PCR6_f;
+  };
+  union {
+    __IO uint32_t PCR7;
+    stc_gpio_pcr7_field_t PCR7_f;
+  };
+  __IO uint32_t PCR8;
+  __IO uint32_t PCR9;
+  union {
+    __IO uint32_t PCRA;
+    stc_gpio_pcra_field_t PCRA_f;
+  };
+  __IO uint32_t PCRB;
+  union {
+    __IO uint32_t PCRC;
+    stc_gpio_pcrc_field_t PCRC_f;
+  };
+  union {
+    __IO uint32_t PCRD;
+    stc_gpio_pcrd_field_t PCRD_f;
+  };
+  union {
+    __IO uint32_t PCRE;
+    stc_gpio_pcre_field_t PCRE_f;
+  };
+  __IO uint32_t PCRF;
+        uint8_t RESERVED1[192];
+  union {
+    __IO uint32_t DDR0;
+    stc_gpio_ddr0_field_t DDR0_f;
+  };
+  union {
+    __IO uint32_t DDR1;
+    stc_gpio_ddr1_field_t DDR1_f;
+  };
+  union {
+    __IO uint32_t DDR2;
+    stc_gpio_ddr2_field_t DDR2_f;
+  };
+  union {
+    __IO uint32_t DDR3;
+    stc_gpio_ddr3_field_t DDR3_f;
+  };
+  union {
+    __IO uint32_t DDR4;
+    stc_gpio_ddr4_field_t DDR4_f;
+  };
+  union {
+    __IO uint32_t DDR5;
+    stc_gpio_ddr5_field_t DDR5_f;
+  };
+  union {
+    __IO uint32_t DDR6;
+    stc_gpio_ddr6_field_t DDR6_f;
+  };
+  union {
+    __IO uint32_t DDR7;
+    stc_gpio_ddr7_field_t DDR7_f;
+  };
+  union {
+    __IO uint32_t DDR8;
+    stc_gpio_ddr8_field_t DDR8_f;
+  };
+  __IO uint32_t DDR9;
+  union {
+    __IO uint32_t DDRA;
+    stc_gpio_ddra_field_t DDRA_f;
+  };
+  __IO uint32_t DDRB;
+  union {
+    __IO uint32_t DDRC;
+    stc_gpio_ddrc_field_t DDRC_f;
+  };
+  union {
+    __IO uint32_t DDRD;
+    stc_gpio_ddrd_field_t DDRD_f;
+  };
+  union {
+    __IO uint32_t DDRE;
+    stc_gpio_ddre_field_t DDRE_f;
+  };
+  union {
+    __IO uint32_t DDRF;
+    stc_gpio_ddrf_field_t DDRF_f;
+  };
+        uint8_t RESERVED2[192];
+  union {
+    __IO uint32_t PDIR0;
+    stc_gpio_pdir0_field_t PDIR0_f;
+  };
+  union {
+    __IO uint32_t PDIR1;
+    stc_gpio_pdir1_field_t PDIR1_f;
+  };
+  union {
+    __IO uint32_t PDIR2;
+    stc_gpio_pdir2_field_t PDIR2_f;
+  };
+  union {
+    __IO uint32_t PDIR3;
+    stc_gpio_pdir3_field_t PDIR3_f;
+  };
+  union {
+    __IO uint32_t PDIR4;
+    stc_gpio_pdir4_field_t PDIR4_f;
+  };
+  union {
+    __IO uint32_t PDIR5;
+    stc_gpio_pdir5_field_t PDIR5_f;
+  };
+  union {
+    __IO uint32_t PDIR6;
+    stc_gpio_pdir6_field_t PDIR6_f;
+  };
+  union {
+    __IO uint32_t PDIR7;
+    stc_gpio_pdir7_field_t PDIR7_f;
+  };
+  union {
+    __IO uint32_t PDIR8;
+    stc_gpio_pdir8_field_t PDIR8_f;
+  };
+  __IO uint32_t PDIR9;
+  union {
+    __IO uint32_t PDIRA;
+    stc_gpio_pdira_field_t PDIRA_f;
+  };
+  __IO uint32_t PDIRB;
+  union {
+    __IO uint32_t PDIRC;
+    stc_gpio_pdirc_field_t PDIRC_f;
+  };
+  union {
+    __IO uint32_t PDIRD;
+    stc_gpio_pdird_field_t PDIRD_f;
+  };
+  union {
+    __IO uint32_t PDIRE;
+    stc_gpio_pdire_field_t PDIRE_f;
+  };
+  union {
+    __IO uint32_t PDIRF;
+    stc_gpio_pdirf_field_t PDIRF_f;
+  };
+        uint8_t RESERVED3[192];
+  union {
+    __IO uint32_t PDOR0;
+    stc_gpio_pdor0_field_t PDOR0_f;
+  };
+  union {
+    __IO uint32_t PDOR1;
+    stc_gpio_pdor1_field_t PDOR1_f;
+  };
+  union {
+    __IO uint32_t PDOR2;
+    stc_gpio_pdor2_field_t PDOR2_f;
+  };
+  union {
+    __IO uint32_t PDOR3;
+    stc_gpio_pdor3_field_t PDOR3_f;
+  };
+  union {
+    __IO uint32_t PDOR4;
+    stc_gpio_pdor4_field_t PDOR4_f;
+  };
+  union {
+    __IO uint32_t PDOR5;
+    stc_gpio_pdor5_field_t PDOR5_f;
+  };
+  union {
+    __IO uint32_t PDOR6;
+    stc_gpio_pdor6_field_t PDOR6_f;
+  };
+  union {
+    __IO uint32_t PDOR7;
+    stc_gpio_pdor7_field_t PDOR7_f;
+  };
+  union {
+    __IO uint32_t PDOR8;
+    stc_gpio_pdor8_field_t PDOR8_f;
+  };
+  __IO uint32_t PDOR9;
+  union {
+    __IO uint32_t PDORA;
+    stc_gpio_pdora_field_t PDORA_f;
+  };
+  __IO uint32_t PDORB;
+  union {
+    __IO uint32_t PDORC;
+    stc_gpio_pdorc_field_t PDORC_f;
+  };
+  union {
+    __IO uint32_t PDORD;
+    stc_gpio_pdord_field_t PDORD_f;
+  };
+  union {
+    __IO uint32_t PDORE;
+    stc_gpio_pdore_field_t PDORE_f;
+  };
+  union {
+    __IO uint32_t PDORF;
+    stc_gpio_pdorf_field_t PDORF_f;
+  };
+        uint8_t RESERVED4[192];
+  union {
+    __IO uint32_t ADE;
+    stc_gpio_ade_field_t ADE_f;
+  };
+        uint8_t RESERVED5[124];
+  union {
+    __IO uint32_t SPSR;
+    stc_gpio_spsr_field_t SPSR_f;
+  };
+        uint8_t RESERVED6[124];
+  union {
+    __IO uint32_t EPFR00;
+    stc_gpio_epfr00_field_t EPFR00_f;
+  };
+  union {
+    __IO uint32_t EPFR01;
+    stc_gpio_epfr01_field_t EPFR01_f;
+  };
+  union {
+    __IO uint32_t EPFR02;
+    stc_gpio_epfr02_field_t EPFR02_f;
+  };
+  union {
+    __IO uint32_t EPFR03;
+    stc_gpio_epfr03_field_t EPFR03_f;
+  };
+  union {
+    __IO uint32_t EPFR04;
+    stc_gpio_epfr04_field_t EPFR04_f;
+  };
+  union {
+    __IO uint32_t EPFR05;
+    stc_gpio_epfr05_field_t EPFR05_f;
+  };
+  union {
+    __IO uint32_t EPFR06;
+    stc_gpio_epfr06_field_t EPFR06_f;
+  };
+  union {
+    __IO uint32_t EPFR07;
+    stc_gpio_epfr07_field_t EPFR07_f;
+  };
+  union {
+    __IO uint32_t EPFR08;
+    stc_gpio_epfr08_field_t EPFR08_f;
+  };
+  union {
+    __IO uint32_t EPFR09;
+    stc_gpio_epfr09_field_t EPFR09_f;
+  };
+  union {
+    __IO uint32_t EPFR10;
+    stc_gpio_epfr10_field_t EPFR10_f;
+  };
+  union {
+    __IO uint32_t EPFR11;
+    stc_gpio_epfr11_field_t EPFR11_f;
+  };
+  union {
+    __IO uint32_t EPFR12;
+    stc_gpio_epfr12_field_t EPFR12_f;
+  };
+  union {
+    __IO uint32_t EPFR13;
+    stc_gpio_epfr13_field_t EPFR13_f;
+  };
+  union {
+    __IO uint32_t EPFR14;
+    stc_gpio_epfr14_field_t EPFR14_f;
+  };
+  union {
+    __IO uint32_t EPFR15;
+    stc_gpio_epfr15_field_t EPFR15_f;
+  };
+        uint8_t RESERVED7[192];
+  union {
+    __IO uint32_t PZR0;
+    stc_gpio_pzr0_field_t PZR0_f;
+  };
+  union {
+    __IO uint32_t PZR1;
+    stc_gpio_pzr1_field_t PZR1_f;
+  };
+  union {
+    __IO uint32_t PZR2;
+    stc_gpio_pzr2_field_t PZR2_f;
+  };
+  union {
+    __IO uint32_t PZR3;
+    stc_gpio_pzr3_field_t PZR3_f;
+  };
+  union {
+    __IO uint32_t PZR4;
+    stc_gpio_pzr4_field_t PZR4_f;
+  };
+  union {
+    __IO uint32_t PZR5;
+    stc_gpio_pzr5_field_t PZR5_f;
+  };
+  union {
+    __IO uint32_t PZR6;
+    stc_gpio_pzr6_field_t PZR6_f;
+  };
+  union {
+    __IO uint32_t PZR7;
+    stc_gpio_pzr7_field_t PZR7_f;
+  };
+  union {
+    __IO uint32_t PZR8;
+    stc_gpio_pzr8_field_t PZR8_f;
+  };
+  __IO uint32_t PZR9;
+  union {
+    __IO uint32_t PZRA;
+    stc_gpio_pzra_field_t PZRA_f;
+  };
+  __IO uint32_t PZRB;
+  union {
+    __IO uint32_t PZRC;
+    stc_gpio_pzrc_field_t PZRC_f;
+  };
+  union {
+    __IO uint32_t PZRD;
+    stc_gpio_pzrd_field_t PZRD_f;
+  };
+  union {
+    __IO uint32_t PZRE;
+    stc_gpio_pzre_field_t PZRE_f;
+  };
+  union {
+    __IO uint32_t PZRF;
+    stc_gpio_pzrf_field_t PZRF_f;
+  };
+}FM3_GPIO_TypeDef;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* Low voltage detection registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t LVD_CTL;
+    stc_lvd_lvd_ctl_field_t LVD_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t LVD_STR;
+    stc_lvd_lvd_str_field_t LVD_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t LVD_CLR;
+    stc_lvd_lvd_clr_field_t LVD_CLR_f;
+  };
+        uint8_t RESERVED2[3];
+  __IO uint32_t LVD_RLR;
+  union {
+    __IO  uint8_t LVD_STR2;
+    stc_lvd_lvd_str2_field_t LVD_STR2_f;
+  };
+}FM3_LVD_TypeDef;
+
+/******************************************************************************
+ * USBETHERNETCLK
+ ******************************************************************************/
+/* USB Ethernet clock registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t UCCR;
+    stc_usbethernetclk_uccr_field_t UCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t UPCR1;
+    stc_usbethernetclk_upcr1_field_t UPCR1_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t UPCR2;
+    stc_usbethernetclk_upcr2_field_t UPCR2_f;
+  };
+        uint8_t RESERVED2[3];
+  union {
+    __IO  uint8_t UPCR3;
+    stc_usbethernetclk_upcr3_field_t UPCR3_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t UPCR4;
+    stc_usbethernetclk_upcr4_field_t UPCR4_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t UP_STR;
+    stc_usbethernetclk_up_str_field_t UP_STR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t UPINT_ENR;
+    stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t UPINT_CLR;
+    stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO  uint8_t UPINT_STR;
+    stc_usbethernetclk_upint_str_field_t UPINT_STR_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t UPCR5;
+    stc_usbethernetclk_upcr5_field_t UPCR5_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t UPCR6;
+    stc_usbethernetclk_upcr6_field_t UPCR6_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t UPCR7;
+    stc_usbethernetclk_upcr7_field_t UPCR7_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t USBEN0;
+    stc_usbethernetclk_usben0_field_t USBEN0_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO  uint8_t USBEN1;
+    stc_usbethernetclk_usben1_field_t USBEN1_f;
+  };
+}FM3_USBETHERNETCLK_TypeDef;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs03_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs03_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_UART_TypeDef;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+}FM3_MFS03_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs03_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs03_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs03_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs03_i2c_ismk_field_t ISMK_f;
+  };
+}FM3_MFS03_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs47_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs47_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_uart_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_uart_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_uart_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_uart_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_uart_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_uart_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_UART_TypeDef;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_csio_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_csio_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_csio_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_csio_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_csio_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_csio_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_lin_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_lin_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_lin_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_lin_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_lin_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_lin_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs47_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs47_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs47_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs47_i2c_ismk_field_t ISMK_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_i2c_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_i2c_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_i2c_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_i2c_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct
+{
+  union {
+    __IO  uint16_t I2CDNF;
+    stc_mfs_nfc_i2cdnf_field_t I2CDNF_f;
+  };
+}FM3_MFS_NFC_TypeDef;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t CRCCR;
+    stc_crc_crccr_field_t CRCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t CRCINIT;
+  union {
+    __IO uint32_t CRCIN;
+    struct {
+      union {
+        __IO uint16_t CRCINL;
+        struct {
+          __IO  uint8_t CRCINLL;
+          __IO  uint8_t CRCINLH;
+        };
+      };
+      union {
+        __IO uint16_t CRCINH;
+        struct {
+          __IO  uint8_t CRCINHL;
+          __IO  uint8_t CRCINHH;
+        };
+      };
+    };
+  };
+  __IO uint32_t CRCR;
+}FM3_CRC_TypeDef;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* Watch counter registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t WCRD;
+    stc_wc_wcrd_field_t WCRD_f;
+  };
+  union {
+    __IO  uint8_t WCRL;
+    stc_wc_wcrl_field_t WCRL_f;
+  };
+  union {
+    __IO  uint8_t WCCR;
+    stc_wc_wccr_field_t WCCR_f;
+  };
+        uint8_t RESERVED0[13];
+  union {
+    __IO uint16_t CLK_SEL;
+    stc_wc_clk_sel_field_t CLK_SEL_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t CLK_EN;
+    stc_wc_clk_en_field_t CLK_EN_f;
+  };
+}FM3_WC_TypeDef;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* External bus interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MODE0;
+    stc_exbus_mode0_field_t MODE0_f;
+  };
+  union {
+    __IO uint32_t MODE1;
+    stc_exbus_mode1_field_t MODE1_f;
+  };
+  union {
+    __IO uint32_t MODE2;
+    stc_exbus_mode2_field_t MODE2_f;
+  };
+  union {
+    __IO uint32_t MODE3;
+    stc_exbus_mode3_field_t MODE3_f;
+  };
+  union {
+    __IO uint32_t MODE4;
+    stc_exbus_mode4_field_t MODE4_f;
+  };
+  union {
+    __IO uint32_t MODE5;
+    stc_exbus_mode5_field_t MODE5_f;
+  };
+  union {
+    __IO uint32_t MODE6;
+    stc_exbus_mode6_field_t MODE6_f;
+  };
+  union {
+    __IO uint32_t MODE7;
+    stc_exbus_mode7_field_t MODE7_f;
+  };
+  union {
+    __IO uint32_t TIM0;
+    stc_exbus_tim0_field_t TIM0_f;
+  };
+  union {
+    __IO uint32_t TIM1;
+    stc_exbus_tim1_field_t TIM1_f;
+  };
+  union {
+    __IO uint32_t TIM2;
+    stc_exbus_tim2_field_t TIM2_f;
+  };
+  union {
+    __IO uint32_t TIM3;
+    stc_exbus_tim3_field_t TIM3_f;
+  };
+  union {
+    __IO uint32_t TIM4;
+    stc_exbus_tim4_field_t TIM4_f;
+  };
+  union {
+    __IO uint32_t TIM5;
+    stc_exbus_tim5_field_t TIM5_f;
+  };
+  union {
+    __IO uint32_t TIM6;
+    stc_exbus_tim6_field_t TIM6_f;
+  };
+  union {
+    __IO uint32_t TIM7;
+    stc_exbus_tim7_field_t TIM7_f;
+  };
+  union {
+    __IO uint32_t AREA0;
+    stc_exbus_area0_field_t AREA0_f;
+  };
+  union {
+    __IO uint32_t AREA1;
+    stc_exbus_area1_field_t AREA1_f;
+  };
+  union {
+    __IO uint32_t AREA2;
+    stc_exbus_area2_field_t AREA2_f;
+  };
+  union {
+    __IO uint32_t AREA3;
+    stc_exbus_area3_field_t AREA3_f;
+  };
+  union {
+    __IO uint32_t AREA4;
+    stc_exbus_area4_field_t AREA4_f;
+  };
+  union {
+    __IO uint32_t AREA5;
+    stc_exbus_area5_field_t AREA5_f;
+  };
+  union {
+    __IO uint32_t AREA6;
+    stc_exbus_area6_field_t AREA6_f;
+  };
+  union {
+    __IO uint32_t AREA7;
+    stc_exbus_area7_field_t AREA7_f;
+  };
+  union {
+    __IO uint16_t ATIM0;
+    stc_exbus_atim0_field_t ATIM0_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO uint16_t ATIM1;
+    stc_exbus_atim1_field_t ATIM1_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t ATIM2;
+    stc_exbus_atim2_field_t ATIM2_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t ATIM3;
+    stc_exbus_atim3_field_t ATIM3_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t ATIM4;
+    stc_exbus_atim4_field_t ATIM4_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t ATIM5;
+    stc_exbus_atim5_field_t ATIM5_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t ATIM6;
+    stc_exbus_atim6_field_t ATIM6_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t ATIM7;
+    stc_exbus_atim7_field_t ATIM7_f;
+  };
+        uint8_t RESERVED7[642];
+  union {
+    __IO  uint8_t DCLKR;
+    stc_exbus_dclkr_field_t DCLKR_f;
+  };
+}FM3_EXBUS_TypeDef;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB channel 0 registers */
+typedef struct
+{
+  union {
+    union {
+      __IO uint16_t HCNT;
+      stc_usb_hcnt_field_t HCNT_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HCNT0;
+        stc_usb_hcnt0_field_t HCNT0_f;
+      };
+      union {
+        __IO  uint8_t HCNT1;
+        stc_usb_hcnt1_field_t HCNT1_f;
+      };
+    };
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t HIRQ;
+    stc_usb_hirq_field_t HIRQ_f;
+  };
+  union {
+    __IO  uint8_t HERR;
+    stc_usb_herr_field_t HERR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t HSTATE;
+    stc_usb_hstate_field_t HSTATE_f;
+  };
+  union {
+    __IO  uint8_t HFCOMP;
+    stc_usb_hfcomp_field_t HFCOMP_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t HRTIMER;
+      stc_usb_hrtimer_field_t HRTIMER_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HRTIMER0;
+        stc_usb_hrtimer0_field_t HRTIMER0_f;
+      };
+      union {
+        __IO  uint8_t HRTIMER1;
+        stc_usb_hrtimer1_field_t HRTIMER1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t HRTIMER2;
+    stc_usb_hrtimer2_field_t HRTIMER2_f;
+  };
+  union {
+    __IO  uint8_t HADR;
+    stc_usb_hadr_field_t HADR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t HEOF;
+      stc_usb_heof_field_t HEOF_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HEOF0;
+        stc_usb_heof0_field_t HEOF0_f;
+      };
+      union {
+        __IO  uint8_t HEOF1;
+        stc_usb_heof1_field_t HEOF1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t HFRAME;
+      stc_usb_hframe_field_t HFRAME_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HFRAME0;
+        stc_usb_hframe0_field_t HFRAME0_f;
+      };
+      union {
+        __IO  uint8_t HFRAME1;
+        stc_usb_hframe1_field_t HFRAME1_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t HTOKEN;
+    stc_usb_htoken_field_t HTOKEN_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t UDCC;
+    stc_usb_udcc_field_t UDCC_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t EP0C;
+    stc_usb_ep0c_field_t EP0C_f;
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO uint16_t EP1C;
+    stc_usb_ep1c_field_t EP1C_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t EP2C;
+    stc_usb_ep2c_field_t EP2C_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t EP3C;
+    stc_usb_ep3c_field_t EP3C_f;
+  };
+        uint8_t RESERVED12[2];
+  union {
+    __IO uint16_t EP4C;
+    stc_usb_ep4c_field_t EP4C_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO uint16_t EP5C;
+    stc_usb_ep5c_field_t EP5C_f;
+  };
+        uint8_t RESERVED14[2];
+  union {
+    __IO uint16_t TMSP;
+    stc_usb_tmsp_field_t TMSP_f;
+  };
+        uint8_t RESERVED15[2];
+  union {
+    __IO  uint8_t UDCS;
+    stc_usb_udcs_field_t UDCS_f;
+  };
+  union {
+    __IO  uint8_t UDCIE;
+    stc_usb_udcie_field_t UDCIE_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t EP0IS;
+    stc_usb_ep0is_field_t EP0IS_f;
+  };
+        uint8_t RESERVED17[2];
+  union {
+    __IO uint16_t EP0OS;
+    stc_usb_ep0os_field_t EP0OS_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t EP1S;
+    stc_usb_ep1s_field_t EP1S_f;
+  };
+        uint8_t RESERVED19[2];
+  union {
+    __IO uint16_t EP2S;
+    stc_usb_ep2s_field_t EP2S_f;
+  };
+        uint8_t RESERVED20[2];
+  __IO uint16_t EP3S;
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t EP4S;
+    stc_usb_ep4s_field_t EP4S_f;
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t EP5S;
+    stc_usb_ep5s_field_t EP5S_f;
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t EP0DT;
+    struct {
+      __IO  uint8_t EP0DTL;
+      __IO  uint8_t EP0DTH;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t EP1DT;
+    struct {
+      __IO  uint8_t EP1DTL;
+      __IO  uint8_t EP1DTH;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO uint16_t EP2DT;
+    struct {
+      __IO  uint8_t EP2DTL;
+      __IO  uint8_t EP2DTH;
+    };
+  };
+        uint8_t RESERVED26[2];
+  union {
+    __IO uint16_t EP3DT;
+    struct {
+      __IO  uint8_t EP3DTL;
+      __IO  uint8_t EP3DTH;
+    };
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO uint16_t EP4DT;
+    struct {
+      __IO  uint8_t EP4DTL;
+      __IO  uint8_t EP4DTH;
+    };
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t EP5DT;
+    struct {
+      __IO  uint8_t EP5DTL;
+      __IO  uint8_t EP5DTH;
+    };
+  };
+}FM3_USB_TypeDef;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMA controller */
+typedef struct
+{
+  union {
+    __IO uint32_t DMACR;
+    stc_dmac_dmacr_field_t DMACR_f;
+  };
+        uint8_t RESERVED0[12];
+  union {
+    __IO uint32_t DMACA0;
+    stc_dmac_dmaca0_field_t DMACA0_f;
+  };
+  union {
+    __IO uint32_t DMACB0;
+    stc_dmac_dmacb0_field_t DMACB0_f;
+  };
+  __IO uint32_t DMACSA0;
+  __IO uint32_t DMACDA0;
+  union {
+    __IO uint32_t DMACA1;
+    stc_dmac_dmaca1_field_t DMACA1_f;
+  };
+  union {
+    __IO uint32_t DMACB1;
+    stc_dmac_dmacb1_field_t DMACB1_f;
+  };
+  __IO uint32_t DMACSA1;
+  __IO uint32_t DMACDA1;
+  union {
+    __IO uint32_t DMACA2;
+    stc_dmac_dmaca2_field_t DMACA2_f;
+  };
+  union {
+    __IO uint32_t DMACB2;
+    stc_dmac_dmacb2_field_t DMACB2_f;
+  };
+  __IO uint32_t DMACSA2;
+  __IO uint32_t DMACDA2;
+  union {
+    __IO uint32_t DMACA3;
+    stc_dmac_dmaca3_field_t DMACA3_f;
+  };
+  union {
+    __IO uint32_t DMACB3;
+    stc_dmac_dmacb3_field_t DMACB3_f;
+  };
+  __IO uint32_t DMACSA3;
+  __IO uint32_t DMACDA3;
+  union {
+    __IO uint32_t DMACA4;
+    stc_dmac_dmaca4_field_t DMACA4_f;
+  };
+  union {
+    __IO uint32_t DMACB4;
+    stc_dmac_dmacb4_field_t DMACB4_f;
+  };
+  __IO uint32_t DMACSA4;
+  __IO uint32_t DMACDA4;
+  union {
+    __IO uint32_t DMACA5;
+    stc_dmac_dmaca5_field_t DMACA5_f;
+  };
+  union {
+    __IO uint32_t DMACB5;
+    stc_dmac_dmacb5_field_t DMACB5_f;
+  };
+  __IO uint32_t DMACSA5;
+  __IO uint32_t DMACDA5;
+  union {
+    __IO uint32_t DMACA6;
+    stc_dmac_dmaca6_field_t DMACA6_f;
+  };
+  union {
+    __IO uint32_t DMACB6;
+    stc_dmac_dmacb6_field_t DMACB6_f;
+  };
+  __IO uint32_t DMACSA6;
+  __IO uint32_t DMACDA6;
+  union {
+    __IO uint32_t DMACA7;
+    stc_dmac_dmaca7_field_t DMACA7_f;
+  };
+  union {
+    __IO uint32_t DMACB7;
+    stc_dmac_dmacb7_field_t DMACB7_f;
+  };
+  __IO uint32_t DMACSA7;
+  __IO uint32_t DMACDA7;
+}FM3_DMAC_TypeDef;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET-MAC registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MCR;
+    stc_ethernet_mac_mcr_field_t MCR_f;
+  };
+  union {
+    __IO uint32_t MFFR;
+    stc_ethernet_mac_mffr_field_t MFFR_f;
+  };
+  union {
+    __IO uint32_t MHTRH;
+    stc_ethernet_mac_mhtrh_field_t MHTRH_f;
+  };
+  union {
+    __IO uint32_t MHTRL;
+    stc_ethernet_mac_mhtrl_field_t MHTRL_f;
+  };
+  union {
+    __IO uint32_t GAR;
+    stc_ethernet_mac_gar_field_t GAR_f;
+  };
+  union {
+    __IO uint32_t GDR;
+    stc_ethernet_mac_gdr_field_t GDR_f;
+  };
+  union {
+    __IO uint32_t FCR;
+    stc_ethernet_mac_fcr_field_t FCR_f;
+  };
+  union {
+    __IO uint32_t VTR;
+    stc_ethernet_mac_vtr_field_t VTR_f;
+  };
+        uint8_t RESERVED0[8];
+  union {
+    __IO uint32_t RWFFR;
+    stc_ethernet_mac_rwffr_field_t RWFFR_f;
+  };
+  union {
+    __IO uint32_t PMTR;
+    stc_ethernet_mac_pmtr_field_t PMTR_f;
+  };
+  union {
+    __IO uint32_t LPICSR;
+    stc_ethernet_mac_lpicsr_field_t LPICSR_f;
+  };
+  union {
+    __IO uint32_t LPITCR;
+    stc_ethernet_mac_lpitcr_field_t LPITCR_f;
+  };
+  union {
+    __IO uint32_t ISR;
+    stc_ethernet_mac_isr_field_t ISR_f;
+  };
+  union {
+    __IO uint32_t IMR;
+    stc_ethernet_mac_imr_field_t IMR_f;
+  };
+  union {
+    __IO uint32_t MAR0H;
+    stc_ethernet_mac_mar0h_field_t MAR0H_f;
+  };
+  union {
+    __IO uint32_t MAR0L;
+    stc_ethernet_mac_mar0l_field_t MAR0L_f;
+  };
+  union {
+    __IO uint32_t MAR1H;
+    stc_ethernet_mac_mar1h_field_t MAR1H_f;
+  };
+  union {
+    __IO uint32_t MAR1L;
+    stc_ethernet_mac_mar1l_field_t MAR1L_f;
+  };
+  union {
+    __IO uint32_t MAR2H;
+    stc_ethernet_mac_mar2h_field_t MAR2H_f;
+  };
+  union {
+    __IO uint32_t MAR2L;
+    stc_ethernet_mac_mar2l_field_t MAR2L_f;
+  };
+  union {
+    __IO uint32_t MAR3H;
+    stc_ethernet_mac_mar3h_field_t MAR3H_f;
+  };
+  union {
+    __IO uint32_t MAR3L;
+    stc_ethernet_mac_mar3l_field_t MAR3L_f;
+  };
+  union {
+    __IO uint32_t MAR4H;
+    stc_ethernet_mac_mar4h_field_t MAR4H_f;
+  };
+  union {
+    __IO uint32_t MAR4L;
+    stc_ethernet_mac_mar4l_field_t MAR4L_f;
+  };
+  union {
+    __IO uint32_t MAR5H;
+    stc_ethernet_mac_mar5h_field_t MAR5H_f;
+  };
+  union {
+    __IO uint32_t MAR5L;
+    stc_ethernet_mac_mar5l_field_t MAR5L_f;
+  };
+  union {
+    __IO uint32_t MAR6H;
+    stc_ethernet_mac_mar6h_field_t MAR6H_f;
+  };
+  union {
+    __IO uint32_t MAR6L;
+    stc_ethernet_mac_mar6l_field_t MAR6L_f;
+  };
+  union {
+    __IO uint32_t MAR7H;
+    stc_ethernet_mac_mar7h_field_t MAR7H_f;
+  };
+  union {
+    __IO uint32_t MAR7L;
+    stc_ethernet_mac_mar7l_field_t MAR7L_f;
+  };
+  union {
+    __IO uint32_t MAR8H;
+    stc_ethernet_mac_mar8h_field_t MAR8H_f;
+  };
+  union {
+    __IO uint32_t MAR8L;
+    stc_ethernet_mac_mar8l_field_t MAR8L_f;
+  };
+  union {
+    __IO uint32_t MAR9H;
+    stc_ethernet_mac_mar9h_field_t MAR9H_f;
+  };
+  union {
+    __IO uint32_t MAR9L;
+    stc_ethernet_mac_mar9l_field_t MAR9L_f;
+  };
+  union {
+    __IO uint32_t MAR10H;
+    stc_ethernet_mac_mar10h_field_t MAR10H_f;
+  };
+  union {
+    __IO uint32_t MAR10L;
+    stc_ethernet_mac_mar10l_field_t MAR10L_f;
+  };
+  union {
+    __IO uint32_t MAR11H;
+    stc_ethernet_mac_mar11h_field_t MAR11H_f;
+  };
+  union {
+    __IO uint32_t MAR11L;
+    stc_ethernet_mac_mar11l_field_t MAR11L_f;
+  };
+  union {
+    __IO uint32_t MAR12H;
+    stc_ethernet_mac_mar12h_field_t MAR12H_f;
+  };
+  union {
+    __IO uint32_t MAR12L;
+    stc_ethernet_mac_mar12l_field_t MAR12L_f;
+  };
+  union {
+    __IO uint32_t MAR13H;
+    stc_ethernet_mac_mar13h_field_t MAR13H_f;
+  };
+  union {
+    __IO uint32_t MAR13L;
+    stc_ethernet_mac_mar13l_field_t MAR13L_f;
+  };
+  union {
+    __IO uint32_t MAR14H;
+    stc_ethernet_mac_mar14h_field_t MAR14H_f;
+  };
+  union {
+    __IO uint32_t MAR14L;
+    stc_ethernet_mac_mar14l_field_t MAR14L_f;
+  };
+  union {
+    __IO uint32_t MAR15H;
+    stc_ethernet_mac_mar15h_field_t MAR15H_f;
+  };
+  union {
+    __IO uint32_t MAR15L;
+    stc_ethernet_mac_mar15l_field_t MAR15L_f;
+  };
+        uint8_t RESERVED1[24];
+  union {
+    __IO uint32_t RGSR;
+    stc_ethernet_mac_rgsr_field_t RGSR_f;
+  };
+        uint8_t RESERVED2[36];
+  __IO uint32_t mmc_cntl;
+  __IO uint32_t mmc_intr_rx;
+  __IO uint32_t mmc_intr_tx;
+  __IO uint32_t mmc_intr_mask_rx;
+  __IO uint32_t mmc_intr_mask_tx;
+  __IO uint32_t txoctetcount_gb;
+  __IO uint32_t txframecount_gb;
+  __IO uint32_t txbroadcastframes_g;
+  __IO uint32_t txmulticastframes_g;
+  __IO uint32_t tx64octets_gb;
+  __IO uint32_t tx65to127octets_gb;
+  __IO uint32_t tx128to255octets_gb;
+  __IO uint32_t tx256to511octets_gb;
+  __IO uint32_t tx512to1023octets_gb;
+  __IO uint32_t tx1024tomaxoctets_gb;
+  __IO uint32_t txunicastframes_gb;
+  __IO uint32_t txmulticastframes_gb;
+  __IO uint32_t txbroadcastframes_gb;
+  __IO uint32_t txunderflowerror;
+  __IO uint32_t txsinglecol_g;
+  __IO uint32_t txmulticol_g;
+  __IO uint32_t txdeferred;
+  __IO uint32_t txlatecol;
+  __IO uint32_t txexesscol;
+  __IO uint32_t txcarriererror;
+  __IO uint32_t txoctetcount_g;
+  __IO uint32_t txframecount_g;
+  __IO uint32_t txexecessdef_g;
+  __IO uint32_t txpauseframes;
+  __IO uint32_t txvlanframes_g;
+        uint8_t RESERVED3[8];
+  __IO uint32_t rxframecount_gb;
+  __IO uint32_t rxoctetcount_gb;
+  __IO uint32_t rxoctetcount_g;
+  __IO uint32_t rxbroadcastframes_g;
+  __IO uint32_t rxmulticastframes_g;
+  __IO uint32_t rxcrcerror;
+  __IO uint32_t rxallignmenterror;
+  __IO uint32_t rxrunterror;
+  __IO uint32_t rxjabbererror;
+  __IO uint32_t rxundersize_g;
+  __IO uint32_t rxoversize_g;
+  __IO uint32_t rx64octets_gb;
+  __IO uint32_t rx65to127octets_gb;
+  __IO uint32_t rx128to255octets_gb;
+  __IO uint32_t rx256to511octets_gb;
+  __IO uint32_t rx512to1023octets_gb;
+  __IO uint32_t rx1024tomaxoctets_gb;
+  __IO uint32_t rxunicastframes_g;
+  __IO uint32_t rxlengtherror;
+  __IO uint32_t rxoutofrangetype;
+  __IO uint32_t rxpauseframes;
+  __IO uint32_t rxfifooverflow;
+  __IO uint32_t rxvlanframes_gb;
+  __IO uint32_t rxwatchdogerror;
+        uint8_t RESERVED4[32];
+  __IO uint32_t mmc_ipc_intr_mask_rx;
+        uint8_t RESERVED5[4];
+  __IO uint32_t mmc_ipc_intr_rx;
+        uint8_t RESERVED6[4];
+  __IO uint32_t rxipv4_gd_frms;
+  __IO uint32_t rxipv4_hdrerr_frms;
+  __IO uint32_t rxipv4_nopay_frms;
+  __IO uint32_t rxipv4_frag_frms;
+  __IO uint32_t rxipv4_udsbl_frms;
+  __IO uint32_t rxipv6_gd_frms;
+  __IO uint32_t rxipv6_hdrerr_frms;
+  __IO uint32_t rxipv6_nopay_frms;
+  __IO uint32_t rxudp_gd_frms;
+  __IO uint32_t rxudp_err_frms;
+  __IO uint32_t rxtcp_gd_frms;
+  __IO uint32_t rxtcp_err_frms;
+  __IO uint32_t rxicmp_gd_frms;
+  __IO uint32_t rxicmp_err_frms;
+        uint8_t RESERVED7[8];
+  __IO uint32_t rxipv4_gd_octets;
+  __IO uint32_t rxipv4_hdrerr_octets;
+  __IO uint32_t rxipv4_nopay_octets;
+  __IO uint32_t rxipv4_frag_octets;
+  __IO uint32_t rxipv4_udsbl_octets;
+  __IO uint32_t rxipv6_gd_octets;
+  __IO uint32_t rxipv6_hdrerr_octets;
+  __IO uint32_t rxipv6_nopay_octets;
+  __IO uint32_t rxudp_gd_octets;
+  __IO uint32_t rxudp_err_octets;
+  __IO uint32_t rxtcp_gd_octets;
+  __IO uint32_t rxtcp_err_octets;
+  __IO uint32_t rxicmp_gd_octets;
+  __IO uint32_t rxicmp_err_octets;
+        uint8_t RESERVED8[1144];
+  union {
+    __IO uint32_t TSCR;
+    stc_ethernet_mac_tscr_field_t TSCR_f;
+  };
+  union {
+    __IO uint32_t SSIR;
+    stc_ethernet_mac_ssir_field_t SSIR_f;
+  };
+  union {
+    __IO uint32_t STSR;
+    stc_ethernet_mac_stsr_field_t STSR_f;
+  };
+  union {
+    __IO uint32_t STNR;
+    stc_ethernet_mac_stnr_field_t STNR_f;
+  };
+  union {
+    __IO uint32_t STSUR;
+    stc_ethernet_mac_stsur_field_t STSUR_f;
+  };
+  union {
+    __IO uint32_t STNUR;
+    stc_ethernet_mac_stnur_field_t STNUR_f;
+  };
+  union {
+    __IO uint32_t TSAR;
+    stc_ethernet_mac_tsar_field_t TSAR_f;
+  };
+  union {
+    __IO uint32_t TTSR;
+    stc_ethernet_mac_ttsr_field_t TTSR_f;
+  };
+  union {
+    __IO uint32_t TTNR;
+    stc_ethernet_mac_ttnr_field_t TTNR_f;
+  };
+  union {
+    __IO uint32_t STHWSR;
+    stc_ethernet_mac_sthwsr_field_t STHWSR_f;
+  };
+  union {
+    __IO uint32_t TSR;
+    stc_ethernet_mac_tsr_field_t TSR_f;
+  };
+  union {
+    __IO uint32_t PPSCR;
+    stc_ethernet_mac_ppscr_field_t PPSCR_f;
+  };
+  union {
+    __IO uint32_t ATNR;
+    stc_ethernet_mac_atnr_field_t ATNR_f;
+  };
+  union {
+    __IO uint32_t ATSR;
+    stc_ethernet_mac_atsr_field_t ATSR_f;
+  };
+        uint8_t RESERVED9[200];
+  union {
+    __IO uint32_t MAR16H;
+    stc_ethernet_mac_mar16h_field_t MAR16H_f;
+  };
+  union {
+    __IO uint32_t MAR16L;
+    stc_ethernet_mac_mar16l_field_t MAR16L_f;
+  };
+  union {
+    __IO uint32_t MAR17H;
+    stc_ethernet_mac_mar17h_field_t MAR17H_f;
+  };
+  union {
+    __IO uint32_t MAR17L;
+    stc_ethernet_mac_mar17l_field_t MAR17L_f;
+  };
+  union {
+    __IO uint32_t MAR18H;
+    stc_ethernet_mac_mar18h_field_t MAR18H_f;
+  };
+  union {
+    __IO uint32_t MAR18L;
+    stc_ethernet_mac_mar18l_field_t MAR18L_f;
+  };
+  union {
+    __IO uint32_t MAR19H;
+    stc_ethernet_mac_mar19h_field_t MAR19H_f;
+  };
+  union {
+    __IO uint32_t MAR19L;
+    stc_ethernet_mac_mar19l_field_t MAR19L_f;
+  };
+  union {
+    __IO uint32_t MAR20H;
+    stc_ethernet_mac_mar20h_field_t MAR20H_f;
+  };
+  union {
+    __IO uint32_t MAR20L;
+    stc_ethernet_mac_mar20l_field_t MAR20L_f;
+  };
+  union {
+    __IO uint32_t MAR21H;
+    stc_ethernet_mac_mar21h_field_t MAR21H_f;
+  };
+  union {
+    __IO uint32_t MAR21L;
+    stc_ethernet_mac_mar21l_field_t MAR21L_f;
+  };
+  union {
+    __IO uint32_t MAR22H;
+    stc_ethernet_mac_mar22h_field_t MAR22H_f;
+  };
+  union {
+    __IO uint32_t MAR22L;
+    stc_ethernet_mac_mar22l_field_t MAR22L_f;
+  };
+  union {
+    __IO uint32_t MAR23H;
+    stc_ethernet_mac_mar23h_field_t MAR23H_f;
+  };
+  union {
+    __IO uint32_t MAR23L;
+    stc_ethernet_mac_mar23l_field_t MAR23L_f;
+  };
+  union {
+    __IO uint32_t MAR24H;
+    stc_ethernet_mac_mar24h_field_t MAR24H_f;
+  };
+  union {
+    __IO uint32_t MAR24L;
+    stc_ethernet_mac_mar24l_field_t MAR24L_f;
+  };
+  union {
+    __IO uint32_t MAR25H;
+    stc_ethernet_mac_mar25h_field_t MAR25H_f;
+  };
+  union {
+    __IO uint32_t MAR25L;
+    stc_ethernet_mac_mar25l_field_t MAR25L_f;
+  };
+  union {
+    __IO uint32_t MAR26H;
+    stc_ethernet_mac_mar26h_field_t MAR26H_f;
+  };
+  union {
+    __IO uint32_t MAR26L;
+    stc_ethernet_mac_mar26l_field_t MAR26L_f;
+  };
+  union {
+    __IO uint32_t MAR27H;
+    stc_ethernet_mac_mar27h_field_t MAR27H_f;
+  };
+  union {
+    __IO uint32_t MAR27L;
+    stc_ethernet_mac_mar27l_field_t MAR27L_f;
+  };
+  union {
+    __IO uint32_t MAR28H;
+    stc_ethernet_mac_mar28h_field_t MAR28H_f;
+  };
+  union {
+    __IO uint32_t MAR28L;
+    stc_ethernet_mac_mar28l_field_t MAR28L_f;
+  };
+  union {
+    __IO uint32_t MAR29H;
+    stc_ethernet_mac_mar29h_field_t MAR29H_f;
+  };
+  union {
+    __IO uint32_t MAR29L;
+    stc_ethernet_mac_mar29l_field_t MAR29L_f;
+  };
+  union {
+    __IO uint32_t MAR30H;
+    stc_ethernet_mac_mar30h_field_t MAR30H_f;
+  };
+  union {
+    __IO uint32_t MAR30L;
+    stc_ethernet_mac_mar30l_field_t MAR30L_f;
+  };
+  union {
+    __IO uint32_t MAR31H;
+    stc_ethernet_mac_mar31h_field_t MAR31H_f;
+  };
+  union {
+    __IO uint32_t MAR31L;
+    stc_ethernet_mac_mar31l_field_t MAR31L_f;
+  };
+        uint8_t RESERVED10[1920];
+  union {
+    __IO uint32_t BMR;
+    stc_ethernet_mac_bmr_field_t BMR_f;
+  };
+  union {
+    __IO uint32_t TPDR;
+    stc_ethernet_mac_tpdr_field_t TPDR_f;
+  };
+  union {
+    __IO uint32_t RPDR;
+    stc_ethernet_mac_rpdr_field_t RPDR_f;
+  };
+  union {
+    __IO uint32_t RDLAR;
+    stc_ethernet_mac_rdlar_field_t RDLAR_f;
+  };
+  union {
+    __IO uint32_t TDLAR;
+    stc_ethernet_mac_tdlar_field_t TDLAR_f;
+  };
+  union {
+    __IO uint32_t SR;
+    stc_ethernet_mac_sr_field_t SR_f;
+  };
+  union {
+    __IO uint32_t OMR;
+    stc_ethernet_mac_omr_field_t OMR_f;
+  };
+  union {
+    __IO uint32_t IER;
+    stc_ethernet_mac_ier_field_t IER_f;
+  };
+  union {
+    __IO uint32_t MFBOCR;
+    stc_ethernet_mac_mfbocr_field_t MFBOCR_f;
+  };
+  union {
+    __IO uint32_t RIWTR;
+    stc_ethernet_mac_riwtr_field_t RIWTR_f;
+  };
+        uint8_t RESERVED11[4];
+  union {
+    __IO uint32_t AHBSR;
+    stc_ethernet_mac_ahbsr_field_t AHBSR_f;
+  };
+        uint8_t RESERVED12[24];
+  union {
+    __IO uint32_t CHTDR;
+    stc_ethernet_mac_chtdr_field_t CHTDR_f;
+  };
+  union {
+    __IO uint32_t CHRDR;
+    stc_ethernet_mac_chrdr_field_t CHRDR_f;
+  };
+  union {
+    __IO uint32_t CHTBAR;
+    stc_ethernet_mac_chtbar_field_t CHTBAR_f;
+  };
+  union {
+    __IO uint32_t CHRBAR;
+    stc_ethernet_mac_chrbar_field_t CHRBAR_f;
+  };
+}FM3_ETHERNET_MAC_TypeDef;
+
+/* ETHERNET-CONTROL registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ETH_MODE;
+    stc_ethernet_control_eth_mode_field_t ETH_MODE_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t ETH_CLKG;
+    stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f;
+  };
+}FM3_ETHERNET_CONTROL_TypeDef;
+
+/******************************************************************************
+ * Peripheral memory map
+ ******************************************************************************/
+#define FM3_FLASH_BASE        (0x00000000UL)                 /* Flash Base                             */
+#define FM3_PERIPH_BASE       (0x40000000UL)                 /* Peripheral  Base                       */
+#define FM3_CM3_BASE          (0xE0100000UL)                 /* CM3 Private                            */
+
+#define FM3_FLASH_IF_BASE     (FM3_PERIPH_BASE + 0x00000UL)  /* Flash interface registers              */
+#define FM3_CRG_BASE          (FM3_PERIPH_BASE + 0x10000UL)  /* Clock and reset registers              */
+#define FM3_HWWDT_BASE        (FM3_PERIPH_BASE + 0x11000UL)  /* Hardware watchdog registers            */
+#define FM3_SWWDT_BASE        (FM3_PERIPH_BASE + 0x12000UL)  /* Software watchdog registers            */
+#define FM3_DTIM_BASE         (FM3_PERIPH_BASE + 0x15000UL)  /* Dual timer 1/2 registers               */
+#define FM3_MFT0_FRT_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Free Running Timer registers */
+#define FM3_MFT0_OCU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Output Compare Unit registers */
+#define FM3_MFT0_WFG_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT0_ICU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Input Capture Unit registers */
+#define FM3_MFT0_ADCMP_BASE   (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define FM3_MFT1_FRT_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Free Running Timer registers */
+#define FM3_MFT1_OCU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Output Compare Unit registers */
+#define FM3_MFT1_WFG_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT1_ICU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Input Capture Unit registers */
+#define FM3_MFT1_ADCMP_BASE   (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define FM3_MFT2_FRT_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Free Running Timer registers */
+#define FM3_MFT2_OCU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Output Compare Unit registers */
+#define FM3_MFT2_WFG_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT2_ICU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Input Capture Unit registers */
+#define FM3_MFT2_ADCMP_BASE   (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define FM3_MFT_PPG_BASE      (FM3_PERIPH_BASE + 0x24000UL)  /* Multifunction Timer PPG registers      */
+#define FM3_BT0_PPG_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PPG registers             */
+#define FM3_BT0_PWM_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWM registers             */
+#define FM3_BT0_RT_BASE       (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 RT registers              */
+#define FM3_BT0_PWC_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWC registers             */
+#define FM3_BT1_PPG_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PPG registers             */
+#define FM3_BT1_PWM_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWM registers             */
+#define FM3_BT1_RT_BASE       (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 RT registers              */
+#define FM3_BT1_PWC_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWC registers             */
+#define FM3_BT2_PPG_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PPG registers             */
+#define FM3_BT2_PWM_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWM registers             */
+#define FM3_BT2_RT_BASE       (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 RT registers              */
+#define FM3_BT2_PWC_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWC registers             */
+#define FM3_BT3_PPG_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PPG registers             */
+#define FM3_BT3_PWM_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWM registers             */
+#define FM3_BT3_RT_BASE       (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 RT registers              */
+#define FM3_BT3_PWC_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWC registers             */
+#define FM3_BT4_PPG_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PPG registers             */
+#define FM3_BT4_PWM_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWM registers             */
+#define FM3_BT4_RT_BASE       (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 RT registers              */
+#define FM3_BT4_PWC_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWC registers             */
+#define FM3_BT5_PPG_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PPG registers             */
+#define FM3_BT5_PWM_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWM registers             */
+#define FM3_BT5_RT_BASE       (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 RT registers              */
+#define FM3_BT5_PWC_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWC registers             */
+#define FM3_BT6_PPG_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PPG registers             */
+#define FM3_BT6_PWM_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWM registers             */
+#define FM3_BT6_RT_BASE       (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 RT registers              */
+#define FM3_BT6_PWC_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWC registers             */
+#define FM3_BT7_PPG_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PPG registers             */
+#define FM3_BT7_PWM_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWM registers             */
+#define FM3_BT7_RT_BASE       (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 RT registers              */
+#define FM3_BT7_PWC_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWC registers             */
+#define FM3_BTIOSEL03_BASE    (FM3_PERIPH_BASE + 0x25100UL)  /* Base Timer I/O selector channel 0 - channel 3 registers */
+#define FM3_BTIOSEL47_BASE    (FM3_PERIPH_BASE + 0x25300UL)  /* Base Timer I/O selector channel 4 - channel 7 registers */
+#define FM3_BT8_PPG_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT8_PWM_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT8_RT_BASE       (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT8_PWC_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT9_PPG_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT9_PWM_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT9_RT_BASE       (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT9_PWC_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT10_PPG_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT10_PWM_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT10_RT_BASE      (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT10_PWC_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT11_PPG_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT11_PWM_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT11_RT_BASE      (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT11_PWC_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BT12_PPG_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT12_PWM_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT12_RT_BASE      (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT12_PWC_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT13_PPG_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT13_PWM_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT13_RT_BASE      (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT13_PWC_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT14_PPG_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT14_PWM_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT14_RT_BASE      (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT14_PWC_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT15_PPG_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT15_PWM_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT15_RT_BASE      (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT15_PWC_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BTIOSEL8B_BASE    (FM3_PERIPH_BASE + 0x25500UL)  /* Base Timer I/O selector channel 8 - channel 11 registers */
+#define FM3_BTIOSELCF_BASE    (FM3_PERIPH_BASE + 0x25700UL)  /* Base Timer I/O selector channel 12 - channel 15 registers */
+#define FM3_SBSSR_BASE        (FM3_PERIPH_BASE + 0x25FFCUL)  /* Software based Simulation Startup (Base Timer) register */
+#define FM3_QPRC0_BASE        (FM3_PERIPH_BASE + 0x26000UL)  /* Quad position and revolution counter channel 0 registers */
+#define FM3_QPRC1_BASE        (FM3_PERIPH_BASE + 0x26040UL)  /* Quad position and revolution counter channel 1 registers */
+#define FM3_QPRC2_BASE        (FM3_PERIPH_BASE + 0x26080UL)  /* Quad position and revolution counter channel 2 registers */
+#define FM3_ADC0_BASE         (FM3_PERIPH_BASE + 0x27000UL)  /* 12-bit ADC unit 0 registers            */
+#define FM3_ADC1_BASE         (FM3_PERIPH_BASE + 0x27100UL)  /* 12-bit ADC unit 1 registers            */
+#define FM3_ADC2_BASE         (FM3_PERIPH_BASE + 0x27200UL)  /* 12-bit ADC unit 2 registers            */
+#define FM3_CRTRIM_BASE       (FM3_PERIPH_BASE + 0x2E000UL)  /* CR trimming registers                  */
+#define FM3_EXTI_BASE         (FM3_PERIPH_BASE + 0x30000UL)  /* External interrupt registers           */
+#define FM3_INTREQ_BASE       (FM3_PERIPH_BASE + 0x31000UL)  /* Interrupt request read registers       */
+#define FM3_GPIO_BASE         (FM3_PERIPH_BASE + 0x33000UL)  /* General purpose I/O registers          */
+#define FM3_LVD_BASE          (FM3_PERIPH_BASE + 0x35000UL)  /* Low voltage detection registers        */
+#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL)  /* USB clock registers                    */
+#define FM3_MFS0_UART_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART asynchronous channel 0 registers  */
+#define FM3_MFS0_CSIO_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART synchronous channel 0 registers   */
+#define FM3_MFS0_LIN_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* UART LIN channel 0 registers           */
+#define FM3_MFS0_I2C_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* I2C channel 0 registers                */
+#define FM3_MFS1_UART_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART asynchronous channel 1 registers  */
+#define FM3_MFS1_CSIO_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART synchronous channel 1 registers   */
+#define FM3_MFS1_LIN_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* UART LIN channel 1 registers           */
+#define FM3_MFS1_I2C_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* I2C channel 1 registers                */
+#define FM3_MFS2_UART_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART asynchronous channel 2 registers  */
+#define FM3_MFS2_CSIO_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART synchronous channel 2 registers   */
+#define FM3_MFS2_LIN_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* UART LIN channel 2 registers           */
+#define FM3_MFS2_I2C_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* I2C channel 2 registers                */
+#define FM3_MFS3_UART_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART asynchronous channel 3 registers  */
+#define FM3_MFS3_CSIO_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART synchronous channel 3 registers   */
+#define FM3_MFS3_LIN_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* UART LIN channel 3 registers           */
+#define FM3_MFS3_I2C_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* I2C channel 3 registers                */
+#define FM3_MFS4_UART_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART asynchronous channel 4 registers  */
+#define FM3_MFS4_CSIO_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART synchronous channel 4 registers   */
+#define FM3_MFS4_LIN_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* UART LIN channel 4 registers           */
+#define FM3_MFS4_I2C_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* I2C channel 4 registers                */
+#define FM3_MFS5_UART_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART asynchronous channel 5 registers  */
+#define FM3_MFS5_CSIO_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART synchronous channel 5 registers   */
+#define FM3_MFS5_LIN_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* UART LIN channel 5 registers           */
+#define FM3_MFS5_I2C_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* I2C channel 5 registers                */
+#define FM3_MFS6_UART_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART asynchronous channel 6 registers  */
+#define FM3_MFS6_CSIO_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART synchronous channel 6 registers   */
+#define FM3_MFS6_LIN_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* UART LIN channel 6 registers           */
+#define FM3_MFS6_I2C_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* I2C channel 6 registers                */
+#define FM3_MFS7_UART_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART asynchronous channel 7 registers  */
+#define FM3_MFS7_CSIO_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART synchronous channel 7 registers   */
+#define FM3_MFS7_LIN_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* UART LIN channel 7 registers           */
+#define FM3_MFS7_I2C_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* I2C channel 7 registers                */
+#define FM3_MFS_NFC_BASE      (FM3_PERIPH_BASE + 0x38800UL)  /* MFS Noise Filter Control register      */
+#define FM3_CRC_BASE          (FM3_PERIPH_BASE + 0x39000UL)  /* CRC registers                          */
+#define FM3_WC_BASE           (FM3_PERIPH_BASE + 0x3A000UL)  /* Watch counter registers                */
+#define FM3_EXBUS_BASE        (FM3_PERIPH_BASE + 0x3F000UL)  /* External bus interface registers       */
+#define FM3_USB0_BASE         (FM3_PERIPH_BASE + 0x42100UL)  /* USB channel 0 registers                */
+#define FM3_USB1_BASE         (FM3_PERIPH_BASE + 0x52100UL)  /* USB channel 1 registers                */
+#define FM3_DMAC_BASE         (FM3_PERIPH_BASE + 0x60000UL)  /* DMA controller                         */
+#define FM3_ETHERNET_MAC0_BASE    (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers            */
+#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers      */
+#define FM3_ETHERNET_MAC1_BASE    (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers            */
+
+/******************************************************************************
+ * Peripheral declaration
+ ******************************************************************************/
+#define FM3_FLASH_IF    ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)
+#define FM3_CRG         ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
+#define FM3_HWWDT       ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
+#define FM3_SWWDT       ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
+#define FM3_DTIM        ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)
+#define FM3_MFT0_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)
+#define FM3_MFT0_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)
+#define FM3_MFT0_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)
+#define FM3_MFT0_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)
+#define FM3_MFT0_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)
+#define FM3_MFT1_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)
+#define FM3_MFT1_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)
+#define FM3_MFT1_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)
+#define FM3_MFT1_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)
+#define FM3_MFT1_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)
+#define FM3_MFT2_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE)
+#define FM3_MFT2_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE)
+#define FM3_MFT2_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE)
+#define FM3_MFT2_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE)
+#define FM3_MFT2_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE)
+#define FM3_MFT_PPG     ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)
+#define FM3_BT0_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)
+#define FM3_BT0_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)
+#define FM3_BT0_RT      ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)
+#define FM3_BT0_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)
+#define FM3_BT1_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)
+#define FM3_BT1_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)
+#define FM3_BT1_RT      ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)
+#define FM3_BT1_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)
+#define FM3_BT2_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)
+#define FM3_BT2_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)
+#define FM3_BT2_RT      ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)
+#define FM3_BT2_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)
+#define FM3_BT3_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)
+#define FM3_BT3_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)
+#define FM3_BT3_RT      ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)
+#define FM3_BT3_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)
+#define FM3_BT4_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)
+#define FM3_BT4_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)
+#define FM3_BT4_RT      ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)
+#define FM3_BT4_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)
+#define FM3_BT5_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)
+#define FM3_BT5_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)
+#define FM3_BT5_RT      ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)
+#define FM3_BT5_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)
+#define FM3_BT6_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)
+#define FM3_BT6_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)
+#define FM3_BT6_RT      ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)
+#define FM3_BT6_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)
+#define FM3_BT7_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)
+#define FM3_BT7_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)
+#define FM3_BT7_RT      ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)
+#define FM3_BT7_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)
+#define FM3_BTIOSEL03   ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)
+#define FM3_BTIOSEL47   ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)
+#define FM3_BT8_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE)
+#define FM3_BT8_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE)
+#define FM3_BT8_RT      ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE)
+#define FM3_BT8_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE)
+#define FM3_BT9_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE)
+#define FM3_BT9_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE)
+#define FM3_BT9_RT      ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE)
+#define FM3_BT9_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE)
+#define FM3_BT10_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE)
+#define FM3_BT10_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE)
+#define FM3_BT10_RT     ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE)
+#define FM3_BT10_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE)
+#define FM3_BT11_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE)
+#define FM3_BT11_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE)
+#define FM3_BT11_RT     ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE)
+#define FM3_BT11_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE)
+#define FM3_BT12_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE)
+#define FM3_BT12_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE)
+#define FM3_BT12_RT     ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE)
+#define FM3_BT12_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE)
+#define FM3_BT13_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE)
+#define FM3_BT13_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE)
+#define FM3_BT13_RT     ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE)
+#define FM3_BT13_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE)
+#define FM3_BT14_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE)
+#define FM3_BT14_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE)
+#define FM3_BT14_RT     ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE)
+#define FM3_BT14_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE)
+#define FM3_BT15_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE)
+#define FM3_BT15_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE)
+#define FM3_BT15_RT     ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE)
+#define FM3_BT15_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE)
+#define FM3_BTIOSEL8B   ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE)
+#define FM3_BTIOSELCF   ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE)
+#define FM3_SBSSR       ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)
+#define FM3_QPRC0       ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)
+#define FM3_QPRC1       ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)
+#define FM3_QPRC3       ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE)
+#define FM3_ADC0        ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)
+#define FM3_ADC1        ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)
+#define FM3_ADC2        ((FM3_ADC_TypeDef *)FM3_ADC2_BASE)
+#define FM3_CRTRIM      ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)
+#define FM3_EXTI        ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)
+#define FM3_INTREQ      ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)
+#define FM3_GPIO        ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)
+#define FM3_LVD         ((FM3_LVD_TypeDef *)FM3_LVD_BASE)
+#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE)
+#define FM3_MFS0_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)
+#define FM3_MFS0_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)
+#define FM3_MFS0_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)
+#define FM3_MFS0_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)
+#define FM3_MFS1_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)
+#define FM3_MFS1_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)
+#define FM3_MFS1_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)
+#define FM3_MFS1_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)
+#define FM3_MFS2_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)
+#define FM3_MFS2_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)
+#define FM3_MFS2_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)
+#define FM3_MFS2_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)
+#define FM3_MFS3_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)
+#define FM3_MFS3_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)
+#define FM3_MFS3_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)
+#define FM3_MFS3_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)
+#define FM3_MFS4_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)
+#define FM3_MFS4_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)
+#define FM3_MFS4_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)
+#define FM3_MFS4_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)
+#define FM3_MFS5_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)
+#define FM3_MFS5_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)
+#define FM3_MFS5_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)
+#define FM3_MFS5_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)
+#define FM3_MFS6_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)
+#define FM3_MFS6_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)
+#define FM3_MFS6_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)
+#define FM3_MFS6_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)
+#define FM3_MFS7_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)
+#define FM3_MFS7_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)
+#define FM3_MFS7_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)
+#define FM3_MFS7_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)
+#define FM3_MFS_NFC     ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE)
+#define FM3_CRC         ((FM3_CRC_TypeDef *)FM3_CRC_BASE)
+#define FM3_WC          ((FM3_WC_TypeDef *)FM3_WC_BASE)
+#define FM3_EXBUS       ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE)
+#define FM3_USB0        ((FM3_USB_TypeDef *)FM3_USB0_BASE)
+#define FM3_USB1        ((FM3_USB_TypeDef *)FM3_USB1_BASE)
+#define FM3_DMAC        ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)
+#define FM3_ETHERNET_MAC0    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE)
+#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_CONTROL_TypeDef *)FM3_ETHERNET_CONTROL_BASE)
+#define FM3_ETHERNET_MAC1    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE)
+
+/******************************************************************************
+ * Peripheral Bit Band Alias declaration
+ ******************************************************************************/
+
+/* Flash interface registers */
+#define bFM3_FLASH_IF_FASZR_ASZ0               *((volatile unsigned int*)(0x42000000UL))
+#define bFM3_FLASH_IF_FASZR_ASZ1               *((volatile unsigned int*)(0x42000004UL))
+#define bFM3_FLASH_IF_FRWTR_RWT0               *((volatile unsigned int*)(0x42000080UL))
+#define bFM3_FLASH_IF_FRWTR_RWT1               *((volatile unsigned int*)(0x42000084UL))
+#define bFM3_FLASH_IF_FSTR_RDY                 *((volatile unsigned int*)(0x42000100UL))
+#define bFM3_FLASH_IF_FSTR_HNG                 *((volatile unsigned int*)(0x42000104UL))
+#define bFM3_FLASH_IF_FSTR_EER                 *((volatile unsigned int*)(0x42000108UL))
+#define bFM3_FLASH_IF_FSYNDN_SD0               *((volatile unsigned int*)(0x42000200UL))
+#define bFM3_FLASH_IF_FSYNDN_SD1               *((volatile unsigned int*)(0x42000204UL))
+#define bFM3_FLASH_IF_FSYNDN_SD2               *((volatile unsigned int*)(0x42000208UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM0             *((volatile unsigned int*)(0x42002000UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM1             *((volatile unsigned int*)(0x42002004UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM2             *((volatile unsigned int*)(0x42002008UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM3             *((volatile unsigned int*)(0x4200200CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM4             *((volatile unsigned int*)(0x42002010UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM5             *((volatile unsigned int*)(0x42002014UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM6             *((volatile unsigned int*)(0x42002018UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM7             *((volatile unsigned int*)(0x4200201CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM8             *((volatile unsigned int*)(0x42002020UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM9             *((volatile unsigned int*)(0x42002024UL))
+
+/* Clock and reset registers */
+#define bFM3_CRG_SCM_CTL_MOSCE                 *((volatile unsigned int*)(0x42200004UL))
+#define bFM3_CRG_SCM_CTL_SOSCE                 *((volatile unsigned int*)(0x4220000CUL))
+#define bFM3_CRG_SCM_CTL_PLLE                  *((volatile unsigned int*)(0x42200010UL))
+#define bFM3_CRG_SCM_CTL_RCS0                  *((volatile unsigned int*)(0x42200014UL))
+#define bFM3_CRG_SCM_CTL_RCS1                  *((volatile unsigned int*)(0x42200018UL))
+#define bFM3_CRG_SCM_CTL_RCS2                  *((volatile unsigned int*)(0x4220001CUL))
+#define bFM3_CRG_SCM_STR_MORDY                 *((volatile unsigned int*)(0x42200084UL))
+#define bFM3_CRG_SCM_STR_SORDY                 *((volatile unsigned int*)(0x4220008CUL))
+#define bFM3_CRG_SCM_STR_PLRDY                 *((volatile unsigned int*)(0x42200090UL))
+#define bFM3_CRG_SCM_STR_RCM0                  *((volatile unsigned int*)(0x42200094UL))
+#define bFM3_CRG_SCM_STR_RCM1                  *((volatile unsigned int*)(0x42200098UL))
+#define bFM3_CRG_SCM_STR_RCM2                  *((volatile unsigned int*)(0x4220009CUL))
+#define bFM3_CRG_RST_STR_PONR                  *((volatile unsigned int*)(0x42200180UL))
+#define bFM3_CRG_RST_STR_INITX                 *((volatile unsigned int*)(0x42200184UL))
+#define bFM3_CRG_RST_STR_SWDT                  *((volatile unsigned int*)(0x42200190UL))
+#define bFM3_CRG_RST_STR_HWDT                  *((volatile unsigned int*)(0x42200194UL))
+#define bFM3_CRG_RST_STR_CSVR                  *((volatile unsigned int*)(0x42200198UL))
+#define bFM3_CRG_RST_STR_FCSR                  *((volatile unsigned int*)(0x4220019CUL))
+#define bFM3_CRG_RST_STR_SRST                  *((volatile unsigned int*)(0x422001A0UL))
+#define bFM3_CRG_BSC_PSR_BSR0                  *((volatile unsigned int*)(0x42200200UL))
+#define bFM3_CRG_BSC_PSR_BSR1                  *((volatile unsigned int*)(0x42200204UL))
+#define bFM3_CRG_BSC_PSR_BSR2                  *((volatile unsigned int*)(0x42200208UL))
+#define bFM3_CRG_APBC0_PSR_APBC00              *((volatile unsigned int*)(0x42200280UL))
+#define bFM3_CRG_APBC0_PSR_APBC01              *((volatile unsigned int*)(0x42200284UL))
+#define bFM3_CRG_APBC1_PSR_APBC10              *((volatile unsigned int*)(0x42200300UL))
+#define bFM3_CRG_APBC1_PSR_APBC11              *((volatile unsigned int*)(0x42200304UL))
+#define bFM3_CRG_APBC1_PSR_APBC1RST            *((volatile unsigned int*)(0x42200310UL))
+#define bFM3_CRG_APBC1_PSR_APBC1EN             *((volatile unsigned int*)(0x4220031CUL))
+#define bFM3_CRG_APBC2_PSR_APBC20              *((volatile unsigned int*)(0x42200380UL))
+#define bFM3_CRG_APBC2_PSR_APBC21              *((volatile unsigned int*)(0x42200384UL))
+#define bFM3_CRG_APBC2_PSR_APBC2RST            *((volatile unsigned int*)(0x42200390UL))
+#define bFM3_CRG_APBC2_PSR_APBC2EN             *((volatile unsigned int*)(0x4220039CUL))
+#define bFM3_CRG_SWC_PSR_SWDS0                 *((volatile unsigned int*)(0x42200400UL))
+#define bFM3_CRG_SWC_PSR_SWDS1                 *((volatile unsigned int*)(0x42200404UL))
+#define bFM3_CRG_SWC_PSR_TESTB                 *((volatile unsigned int*)(0x4220041CUL))
+#define bFM3_CRG_TTC_PSR_TTC0                  *((volatile unsigned int*)(0x42200500UL))
+#define bFM3_CRG_TTC_PSR_TTC1                  *((volatile unsigned int*)(0x42200504UL))
+#define bFM3_CRG_CSW_TMR_MOWT0                 *((volatile unsigned int*)(0x42200600UL))
+#define bFM3_CRG_CSW_TMR_MOWT1                 *((volatile unsigned int*)(0x42200604UL))
+#define bFM3_CRG_CSW_TMR_MOWT2                 *((volatile unsigned int*)(0x42200608UL))
+#define bFM3_CRG_CSW_TMR_MOWT3                 *((volatile unsigned int*)(0x4220060CUL))
+#define bFM3_CRG_CSW_TMR_SOWT0                 *((volatile unsigned int*)(0x42200610UL))
+#define bFM3_CRG_CSW_TMR_SOWT1                 *((volatile unsigned int*)(0x42200614UL))
+#define bFM3_CRG_CSW_TMR_SOWT2                 *((volatile unsigned int*)(0x42200618UL))
+#define bFM3_CRG_PSW_TMR_POWT0                 *((volatile unsigned int*)(0x42200680UL))
+#define bFM3_CRG_PSW_TMR_POWT1                 *((volatile unsigned int*)(0x42200684UL))
+#define bFM3_CRG_PSW_TMR_POWT2                 *((volatile unsigned int*)(0x42200688UL))
+#define bFM3_CRG_PSW_TMR_PINC                  *((volatile unsigned int*)(0x42200690UL))
+#define bFM3_CRG_PLL_CTL1_PLLM0                *((volatile unsigned int*)(0x42200700UL))
+#define bFM3_CRG_PLL_CTL1_PLLM1                *((volatile unsigned int*)(0x42200704UL))
+#define bFM3_CRG_PLL_CTL1_PLLM2                *((volatile unsigned int*)(0x42200708UL))
+#define bFM3_CRG_PLL_CTL1_PLLM3                *((volatile unsigned int*)(0x4220070CUL))
+#define bFM3_CRG_PLL_CTL1_PLLK0                *((volatile unsigned int*)(0x42200710UL))
+#define bFM3_CRG_PLL_CTL1_PLLK1                *((volatile unsigned int*)(0x42200714UL))
+#define bFM3_CRG_PLL_CTL1_PLLK2                *((volatile unsigned int*)(0x42200718UL))
+#define bFM3_CRG_PLL_CTL1_PLLK3                *((volatile unsigned int*)(0x4220071CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN0                *((volatile unsigned int*)(0x42200780UL))
+#define bFM3_CRG_PLL_CTL2_PLLN1                *((volatile unsigned int*)(0x42200784UL))
+#define bFM3_CRG_PLL_CTL2_PLLN2                *((volatile unsigned int*)(0x42200788UL))
+#define bFM3_CRG_PLL_CTL2_PLLN3                *((volatile unsigned int*)(0x4220078CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN4                *((volatile unsigned int*)(0x42200790UL))
+#define bFM3_CRG_PLL_CTL2_PLLN5                *((volatile unsigned int*)(0x42200794UL))
+#define bFM3_CRG_CSV_CTL_MCSVE                 *((volatile unsigned int*)(0x42200800UL))
+#define bFM3_CRG_CSV_CTL_SCSVE                 *((volatile unsigned int*)(0x42200804UL))
+#define bFM3_CRG_CSV_CTL_FCSDE                 *((volatile unsigned int*)(0x42200820UL))
+#define bFM3_CRG_CSV_CTL_FCSRE                 *((volatile unsigned int*)(0x42200824UL))
+#define bFM3_CRG_CSV_CTL_FCD0                  *((volatile unsigned int*)(0x42200830UL))
+#define bFM3_CRG_CSV_CTL_FCD1                  *((volatile unsigned int*)(0x42200834UL))
+#define bFM3_CRG_CSV_CTL_FCD2                  *((volatile unsigned int*)(0x42200838UL))
+#define bFM3_CRG_CSV_STR_MCMF                  *((volatile unsigned int*)(0x42200880UL))
+#define bFM3_CRG_CSV_STR_SCMF                  *((volatile unsigned int*)(0x42200884UL))
+#define bFM3_CRG_DBWDT_CTL_DPSWBE              *((volatile unsigned int*)(0x42200A94UL))
+#define bFM3_CRG_DBWDT_CTL_DPHWBE              *((volatile unsigned int*)(0x42200A9CUL))
+#define bFM3_CRG_INT_ENR_MCSE                  *((volatile unsigned int*)(0x42200C00UL))
+#define bFM3_CRG_INT_ENR_SCSE                  *((volatile unsigned int*)(0x42200C04UL))
+#define bFM3_CRG_INT_ENR_PCSE                  *((volatile unsigned int*)(0x42200C08UL))
+#define bFM3_CRG_INT_ENR_FCSE                  *((volatile unsigned int*)(0x42200C14UL))
+#define bFM3_CRG_INT_STR_MCSI                  *((volatile unsigned int*)(0x42200C80UL))
+#define bFM3_CRG_INT_STR_SCSI                  *((volatile unsigned int*)(0x42200C84UL))
+#define bFM3_CRG_INT_STR_PCSI                  *((volatile unsigned int*)(0x42200C88UL))
+#define bFM3_CRG_INT_STR_FCSI                  *((volatile unsigned int*)(0x42200C94UL))
+#define bFM3_CRG_INT_CLR_MCSC                  *((volatile unsigned int*)(0x42200D00UL))
+#define bFM3_CRG_INT_CLR_SCSC                  *((volatile unsigned int*)(0x42200D04UL))
+#define bFM3_CRG_INT_CLR_PCSC                  *((volatile unsigned int*)(0x42200D08UL))
+#define bFM3_CRG_INT_CLR_FCSC                  *((volatile unsigned int*)(0x42200D14UL))
+
+/* Hardware watchdog registers */
+#define bFM3_HWWDT_WDG_CTL_INTEN               *((volatile unsigned int*)(0x42220100UL))
+#define bFM3_HWWDT_WDG_CTL_RESEN               *((volatile unsigned int*)(0x42220104UL))
+#define bFM3_HWWDT_WDG_RIS_RIS                 *((volatile unsigned int*)(0x42220200UL))
+
+/* Software watchdog registers */
+#define bFM3_SWWDT_WDOGCONTROL_INTEN           *((volatile unsigned int*)(0x42240100UL))
+#define bFM3_SWWDT_WDOGCONTROL_RESEN           *((volatile unsigned int*)(0x42240104UL))
+#define bFM3_SWWDT_WDOGRIS_RIS                 *((volatile unsigned int*)(0x42240200UL))
+
+/* Dual timer 1/2 registers */
+#define bFM3_DTIM_TIMER1CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0100UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0104UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0108UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A010CUL))
+#define bFM3_DTIM_TIMER1CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0114UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0118UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A011CUL))
+#define bFM3_DTIM_TIMER1RIS_TIMER1RIS          *((volatile unsigned int*)(0x422A0200UL))
+#define bFM3_DTIM_TIMER1MIS_TIMER1MIS          *((volatile unsigned int*)(0x422A0280UL))
+#define bFM3_DTIM_TIMER2CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0500UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0504UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0508UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A050CUL))
+#define bFM3_DTIM_TIMER2CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0514UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0518UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A051CUL))
+#define bFM3_DTIM_TIMER2RIS_TIMER2RIS          *((volatile unsigned int*)(0x422A0600UL))
+#define bFM3_DTIM_TIMER2MIS_TIMER2MIS          *((volatile unsigned int*)(0x422A0680UL))
+
+/* Multifunction Timer unit 0 Free Running Timer registers */
+#define bFM3_MFT0_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42400600UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42400604UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42400608UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4240060CUL))
+#define bFM3_MFT0_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42400610UL))
+#define bFM3_MFT0_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42400614UL))
+#define bFM3_MFT0_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42400618UL))
+#define bFM3_MFT0_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4240061CUL))
+#define bFM3_MFT0_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42400620UL))
+#define bFM3_MFT0_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42400624UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42400634UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42400638UL))
+#define bFM3_MFT0_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4240063CUL))
+#define bFM3_MFT0_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42400680UL))
+#define bFM3_MFT0_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42400684UL))
+#define bFM3_MFT0_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42400688UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42400800UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42400804UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42400808UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4240080CUL))
+#define bFM3_MFT0_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42400810UL))
+#define bFM3_MFT0_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42400814UL))
+#define bFM3_MFT0_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42400818UL))
+#define bFM3_MFT0_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4240081CUL))
+#define bFM3_MFT0_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42400820UL))
+#define bFM3_MFT0_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42400824UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42400834UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42400838UL))
+#define bFM3_MFT0_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4240083CUL))
+#define bFM3_MFT0_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42400880UL))
+#define bFM3_MFT0_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42400884UL))
+#define bFM3_MFT0_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42400888UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42400A00UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42400A04UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42400A08UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42400A0CUL))
+#define bFM3_MFT0_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42400A10UL))
+#define bFM3_MFT0_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42400A14UL))
+#define bFM3_MFT0_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42400A18UL))
+#define bFM3_MFT0_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42400A1CUL))
+#define bFM3_MFT0_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42400A20UL))
+#define bFM3_MFT0_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42400A24UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42400A34UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42400A38UL))
+#define bFM3_MFT0_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42400A3CUL))
+#define bFM3_MFT0_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42400A80UL))
+#define bFM3_MFT0_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42400A84UL))
+#define bFM3_MFT0_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42400A88UL))
+
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+#define bFM3_MFT0_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42400300UL))
+#define bFM3_MFT0_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42400304UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42400308UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4240030CUL))
+#define bFM3_MFT0_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42400310UL))
+#define bFM3_MFT0_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42400314UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42400318UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4240031CUL))
+#define bFM3_MFT0_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42400320UL))
+#define bFM3_MFT0_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42400324UL))
+#define bFM3_MFT0_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42400330UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42400334UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42400338UL))
+#define bFM3_MFT0_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42400380UL))
+#define bFM3_MFT0_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42400384UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42400388UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4240038CUL))
+#define bFM3_MFT0_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42400390UL))
+#define bFM3_MFT0_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42400394UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42400398UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4240039CUL))
+#define bFM3_MFT0_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424003A0UL))
+#define bFM3_MFT0_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424003A4UL))
+#define bFM3_MFT0_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424003B0UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424003B4UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424003B8UL))
+#define bFM3_MFT0_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42400400UL))
+#define bFM3_MFT0_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42400404UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42400408UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4240040CUL))
+#define bFM3_MFT0_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42400410UL))
+#define bFM3_MFT0_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42400414UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42400418UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4240041CUL))
+#define bFM3_MFT0_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42400420UL))
+#define bFM3_MFT0_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42400424UL))
+#define bFM3_MFT0_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42400430UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42400434UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42400438UL))
+#define bFM3_MFT0_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424004A0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424004A4UL))
+#define bFM3_MFT0_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424004A8UL))
+#define bFM3_MFT0_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424004ACUL))
+#define bFM3_MFT0_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424004B0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424004B4UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42400B00UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42400B04UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42400B08UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42400B0CUL))
+#define bFM3_MFT0_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42400B10UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42400B14UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42400B18UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42400B1CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42400B20UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42400B24UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42400B28UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42400B2CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42400B30UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42400B34UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42400B38UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42400B3CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42400B80UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42400B84UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42400B88UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42400B8CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42400B90UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42400B94UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42400B98UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42400B9CUL))
+
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT0_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42401180UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42401184UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42401188UL))
+#define bFM3_MFT0_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4240118CUL))
+#define bFM3_MFT0_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42401190UL))
+#define bFM3_MFT0_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42401194UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42401198UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4240119CUL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424011A0UL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424011A4UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424011A8UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424011ACUL))
+#define bFM3_MFT0_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424011B0UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42401200UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42401204UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42401208UL))
+#define bFM3_MFT0_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4240120CUL))
+#define bFM3_MFT0_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42401210UL))
+#define bFM3_MFT0_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42401214UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42401218UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4240121CUL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42401220UL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42401224UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42401228UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4240122CUL))
+#define bFM3_MFT0_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42401230UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42401280UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42401284UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42401288UL))
+#define bFM3_MFT0_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4240128CUL))
+#define bFM3_MFT0_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42401290UL))
+#define bFM3_MFT0_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42401294UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42401298UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4240129CUL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424012A0UL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424012A4UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424012A8UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424012ACUL))
+#define bFM3_MFT0_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424012B0UL))
+#define bFM3_MFT0_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42401300UL))
+#define bFM3_MFT0_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42401304UL))
+#define bFM3_MFT0_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42401310UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42401314UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42401318UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4240131CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42401320UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42401324UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42401328UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4240132CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42401330UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42401334UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42401338UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4240133CUL))
+#define bFM3_MFT0_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42401380UL))
+#define bFM3_MFT0_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42401384UL))
+#define bFM3_MFT0_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42401388UL))
+#define bFM3_MFT0_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4240138CUL))
+#define bFM3_MFT0_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42401390UL))
+
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+#define bFM3_MFT0_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42400C00UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42400C04UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42400C08UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42400C0CUL))
+#define bFM3_MFT0_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42400C10UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42400C14UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42400C18UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42400C1CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42400C20UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42400C24UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42400C28UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42400C2CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42400C30UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42400C34UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42400C38UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42400C3CUL))
+#define bFM3_MFT0_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42400F00UL))
+#define bFM3_MFT0_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42400F04UL))
+#define bFM3_MFT0_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42400F08UL))
+#define bFM3_MFT0_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42400F0CUL))
+#define bFM3_MFT0_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42400F10UL))
+#define bFM3_MFT0_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42400F14UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42400F18UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42400F1CUL))
+#define bFM3_MFT0_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42400F20UL))
+#define bFM3_MFT0_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42400F24UL))
+#define bFM3_MFT0_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42400F80UL))
+#define bFM3_MFT0_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42400F84UL))
+#define bFM3_MFT0_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42400F88UL))
+#define bFM3_MFT0_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42400F8CUL))
+#define bFM3_MFT0_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42400F90UL))
+#define bFM3_MFT0_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42400F94UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42400F98UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42400F9CUL))
+#define bFM3_MFT0_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42400FA0UL))
+#define bFM3_MFT0_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42400FA4UL))
+
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define bFM3_MFT0_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42401700UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42401704UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42401708UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42401710UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42401714UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42401718UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42401780UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42401784UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42401788UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4240178CUL))
+#define bFM3_MFT0_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42401790UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42401794UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424017A0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424017A4UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424017A8UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424017ACUL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424017B0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424017B4UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42401800UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42401804UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42401808UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4240180CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42401810UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42401814UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42401820UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42401824UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42401828UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4240182CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42401830UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42401834UL))
+
+/* Multifunction Timer unit 1 Free Running Timer registers */
+#define bFM3_MFT1_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42420600UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42420604UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42420608UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4242060CUL))
+#define bFM3_MFT1_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42420610UL))
+#define bFM3_MFT1_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42420614UL))
+#define bFM3_MFT1_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42420618UL))
+#define bFM3_MFT1_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4242061CUL))
+#define bFM3_MFT1_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42420620UL))
+#define bFM3_MFT1_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42420624UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42420634UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42420638UL))
+#define bFM3_MFT1_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4242063CUL))
+#define bFM3_MFT1_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42420680UL))
+#define bFM3_MFT1_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42420684UL))
+#define bFM3_MFT1_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42420688UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42420800UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42420804UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42420808UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4242080CUL))
+#define bFM3_MFT1_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42420810UL))
+#define bFM3_MFT1_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42420814UL))
+#define bFM3_MFT1_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42420818UL))
+#define bFM3_MFT1_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4242081CUL))
+#define bFM3_MFT1_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42420820UL))
+#define bFM3_MFT1_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42420824UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42420834UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42420838UL))
+#define bFM3_MFT1_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4242083CUL))
+#define bFM3_MFT1_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42420880UL))
+#define bFM3_MFT1_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42420884UL))
+#define bFM3_MFT1_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42420888UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42420A00UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42420A04UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42420A08UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42420A0CUL))
+#define bFM3_MFT1_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42420A10UL))
+#define bFM3_MFT1_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42420A14UL))
+#define bFM3_MFT1_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42420A18UL))
+#define bFM3_MFT1_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42420A1CUL))
+#define bFM3_MFT1_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42420A20UL))
+#define bFM3_MFT1_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42420A24UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42420A34UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42420A38UL))
+#define bFM3_MFT1_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42420A3CUL))
+#define bFM3_MFT1_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42420A80UL))
+#define bFM3_MFT1_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42420A84UL))
+#define bFM3_MFT1_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42420A88UL))
+
+/* Multifunction Timer unit 1 Output Compare Unit registers */
+#define bFM3_MFT1_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42420300UL))
+#define bFM3_MFT1_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42420304UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42420308UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4242030CUL))
+#define bFM3_MFT1_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42420310UL))
+#define bFM3_MFT1_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42420314UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42420318UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4242031CUL))
+#define bFM3_MFT1_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42420320UL))
+#define bFM3_MFT1_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42420324UL))
+#define bFM3_MFT1_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42420330UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42420334UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42420338UL))
+#define bFM3_MFT1_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42420380UL))
+#define bFM3_MFT1_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42420384UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42420388UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4242038CUL))
+#define bFM3_MFT1_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42420390UL))
+#define bFM3_MFT1_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42420394UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42420398UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4242039CUL))
+#define bFM3_MFT1_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424203A0UL))
+#define bFM3_MFT1_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424203A4UL))
+#define bFM3_MFT1_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424203B0UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424203B4UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424203B8UL))
+#define bFM3_MFT1_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42420400UL))
+#define bFM3_MFT1_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42420404UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42420408UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4242040CUL))
+#define bFM3_MFT1_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42420410UL))
+#define bFM3_MFT1_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42420414UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42420418UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4242041CUL))
+#define bFM3_MFT1_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42420420UL))
+#define bFM3_MFT1_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42420424UL))
+#define bFM3_MFT1_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42420430UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42420434UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42420438UL))
+#define bFM3_MFT1_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424204A0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424204A4UL))
+#define bFM3_MFT1_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424204A8UL))
+#define bFM3_MFT1_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424204ACUL))
+#define bFM3_MFT1_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424204B0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424204B4UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42420B00UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42420B04UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42420B08UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42420B0CUL))
+#define bFM3_MFT1_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42420B10UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42420B14UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42420B18UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42420B1CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42420B20UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42420B24UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42420B28UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42420B2CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42420B30UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42420B34UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42420B38UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42420B3CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42420B80UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42420B84UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42420B88UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42420B8CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42420B90UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42420B94UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42420B98UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42420B9CUL))
+
+/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT1_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42421180UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42421184UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42421188UL))
+#define bFM3_MFT1_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4242118CUL))
+#define bFM3_MFT1_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42421190UL))
+#define bFM3_MFT1_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42421194UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42421198UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4242119CUL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424211A0UL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424211A4UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424211A8UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424211ACUL))
+#define bFM3_MFT1_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424211B0UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42421200UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42421204UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42421208UL))
+#define bFM3_MFT1_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4242120CUL))
+#define bFM3_MFT1_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42421210UL))
+#define bFM3_MFT1_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42421214UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42421218UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4242121CUL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42421220UL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42421224UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42421228UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4242122CUL))
+#define bFM3_MFT1_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42421230UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42421280UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42421284UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42421288UL))
+#define bFM3_MFT1_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4242128CUL))
+#define bFM3_MFT1_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42421290UL))
+#define bFM3_MFT1_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42421294UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42421298UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4242129CUL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424212A0UL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424212A4UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424212A8UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424212ACUL))
+#define bFM3_MFT1_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424212B0UL))
+#define bFM3_MFT1_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42421300UL))
+#define bFM3_MFT1_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42421304UL))
+#define bFM3_MFT1_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42421310UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42421314UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42421318UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4242131CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42421320UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42421324UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42421328UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4242132CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42421330UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42421334UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42421338UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4242133CUL))
+#define bFM3_MFT1_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42421380UL))
+#define bFM3_MFT1_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42421384UL))
+#define bFM3_MFT1_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42421388UL))
+#define bFM3_MFT1_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4242138CUL))
+#define bFM3_MFT1_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42421390UL))
+
+/* Multifunction Timer unit 1 Input Capture Unit registers */
+#define bFM3_MFT1_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42420C00UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42420C04UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42420C08UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42420C0CUL))
+#define bFM3_MFT1_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42420C10UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42420C14UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42420C18UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42420C1CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42420C20UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42420C24UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42420C28UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42420C2CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42420C30UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42420C34UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42420C38UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42420C3CUL))
+#define bFM3_MFT1_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42420F00UL))
+#define bFM3_MFT1_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42420F04UL))
+#define bFM3_MFT1_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42420F08UL))
+#define bFM3_MFT1_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42420F0CUL))
+#define bFM3_MFT1_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42420F10UL))
+#define bFM3_MFT1_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42420F14UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42420F18UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42420F1CUL))
+#define bFM3_MFT1_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42420F20UL))
+#define bFM3_MFT1_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42420F24UL))
+#define bFM3_MFT1_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42420F80UL))
+#define bFM3_MFT1_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42420F84UL))
+#define bFM3_MFT1_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42420F88UL))
+#define bFM3_MFT1_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42420F8CUL))
+#define bFM3_MFT1_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42420F90UL))
+#define bFM3_MFT1_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42420F94UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42420F98UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42420F9CUL))
+#define bFM3_MFT1_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42420FA0UL))
+#define bFM3_MFT1_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42420FA4UL))
+
+/* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define bFM3_MFT1_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42421700UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42421704UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42421708UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42421710UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42421714UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42421718UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42421780UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42421784UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42421788UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4242178CUL))
+#define bFM3_MFT1_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42421790UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42421794UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424217A0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424217A4UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424217A8UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424217ACUL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424217B0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424217B4UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42421800UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42421804UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42421808UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4242180CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42421810UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42421814UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42421820UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42421824UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42421828UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4242182CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42421830UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42421834UL))
+
+/* Multifunction Timer unit 2 Free Running Timer registers */
+#define bFM3_MFT2_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42440600UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42440604UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42440608UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4244060CUL))
+#define bFM3_MFT2_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42440610UL))
+#define bFM3_MFT2_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42440614UL))
+#define bFM3_MFT2_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42440618UL))
+#define bFM3_MFT2_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4244061CUL))
+#define bFM3_MFT2_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42440620UL))
+#define bFM3_MFT2_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42440624UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42440634UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42440638UL))
+#define bFM3_MFT2_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4244063CUL))
+#define bFM3_MFT2_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42440680UL))
+#define bFM3_MFT2_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42440684UL))
+#define bFM3_MFT2_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42440688UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42440800UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42440804UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42440808UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4244080CUL))
+#define bFM3_MFT2_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42440810UL))
+#define bFM3_MFT2_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42440814UL))
+#define bFM3_MFT2_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42440818UL))
+#define bFM3_MFT2_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4244081CUL))
+#define bFM3_MFT2_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42440820UL))
+#define bFM3_MFT2_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42440824UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42440834UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42440838UL))
+#define bFM3_MFT2_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4244083CUL))
+#define bFM3_MFT2_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42440880UL))
+#define bFM3_MFT2_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42440884UL))
+#define bFM3_MFT2_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42440888UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42440A00UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42440A04UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42440A08UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42440A0CUL))
+#define bFM3_MFT2_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42440A10UL))
+#define bFM3_MFT2_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42440A14UL))
+#define bFM3_MFT2_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42440A18UL))
+#define bFM3_MFT2_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42440A1CUL))
+#define bFM3_MFT2_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42440A20UL))
+#define bFM3_MFT2_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42440A24UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42440A34UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42440A38UL))
+#define bFM3_MFT2_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42440A3CUL))
+#define bFM3_MFT2_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42440A80UL))
+#define bFM3_MFT2_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42440A84UL))
+#define bFM3_MFT2_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42440A88UL))
+
+/* Multifunction Timer unit 2 Output Compare Unit registers */
+#define bFM3_MFT2_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42440300UL))
+#define bFM3_MFT2_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42440304UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42440308UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4244030CUL))
+#define bFM3_MFT2_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42440310UL))
+#define bFM3_MFT2_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42440314UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42440318UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4244031CUL))
+#define bFM3_MFT2_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42440320UL))
+#define bFM3_MFT2_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42440324UL))
+#define bFM3_MFT2_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42440330UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42440334UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42440338UL))
+#define bFM3_MFT2_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42440380UL))
+#define bFM3_MFT2_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42440384UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42440388UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4244038CUL))
+#define bFM3_MFT2_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42440390UL))
+#define bFM3_MFT2_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42440394UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42440398UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4244039CUL))
+#define bFM3_MFT2_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424403A0UL))
+#define bFM3_MFT2_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424403A4UL))
+#define bFM3_MFT2_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424403B0UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424403B4UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424403B8UL))
+#define bFM3_MFT2_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42440400UL))
+#define bFM3_MFT2_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42440404UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42440408UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4244040CUL))
+#define bFM3_MFT2_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42440410UL))
+#define bFM3_MFT2_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42440414UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42440418UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4244041CUL))
+#define bFM3_MFT2_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42440420UL))
+#define bFM3_MFT2_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42440424UL))
+#define bFM3_MFT2_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42440430UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42440434UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42440438UL))
+#define bFM3_MFT2_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424404A0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424404A4UL))
+#define bFM3_MFT2_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424404A8UL))
+#define bFM3_MFT2_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424404ACUL))
+#define bFM3_MFT2_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424404B0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424404B4UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42440B00UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42440B04UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42440B08UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42440B0CUL))
+#define bFM3_MFT2_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42440B10UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42440B14UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42440B18UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42440B1CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42440B20UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42440B24UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42440B28UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42440B2CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42440B30UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42440B34UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42440B38UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42440B3CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42440B80UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42440B84UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42440B88UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42440B8CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42440B90UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42440B94UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42440B98UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42440B9CUL))
+
+/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT2_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42441180UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42441184UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42441188UL))
+#define bFM3_MFT2_WFG_WFSA10_TMD0              *((volatile unsigned int*)(0x4244118CUL))
+#define bFM3_MFT2_WFG_WFSA10_TMD1              *((volatile unsigned int*)(0x42441190UL))
+#define bFM3_MFT2_WFG_WFSA10_TMD2              *((volatile unsigned int*)(0x42441194UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42441198UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4244119CUL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424411A0UL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424411A4UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424411A8UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424411ACUL))
+#define bFM3_MFT2_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424411B0UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42441200UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42441204UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42441208UL))
+#define bFM3_MFT2_WFG_WFSA32_TMD0              *((volatile unsigned int*)(0x4244120CUL))
+#define bFM3_MFT2_WFG_WFSA32_TMD1              *((volatile unsigned int*)(0x42441210UL))
+#define bFM3_MFT2_WFG_WFSA32_TMD2              *((volatile unsigned int*)(0x42441214UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42441218UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4244121CUL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42441220UL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42441224UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42441228UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4244122CUL))
+#define bFM3_MFT2_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42441230UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42441280UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42441284UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42441288UL))
+#define bFM3_MFT2_WFG_WFSA54_TMD0              *((volatile unsigned int*)(0x4244128CUL))
+#define bFM3_MFT2_WFG_WFSA54_TMD1              *((volatile unsigned int*)(0x42441290UL))
+#define bFM3_MFT2_WFG_WFSA54_TMD2              *((volatile unsigned int*)(0x42441294UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42441298UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4244129CUL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424412A0UL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424412A4UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424412A8UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424412ACUL))
+#define bFM3_MFT2_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424412B0UL))
+#define bFM3_MFT2_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42441300UL))
+#define bFM3_MFT2_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42441304UL))
+#define bFM3_MFT2_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42441310UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42441314UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42441318UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4244131CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42441320UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42441324UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42441328UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4244132CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42441330UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42441334UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42441338UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4244133CUL))
+#define bFM3_MFT2_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42441380UL))
+#define bFM3_MFT2_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42441384UL))
+#define bFM3_MFT2_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42441388UL))
+#define bFM3_MFT2_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4244138CUL))
+#define bFM3_MFT2_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42441390UL))
+
+/* Multifunction Timer unit 2 Input Capture Unit registers */
+#define bFM3_MFT2_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42440C00UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42440C04UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42440C08UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42440C0CUL))
+#define bFM3_MFT2_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42440C10UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42440C14UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42440C18UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42440C1CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42440C20UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42440C24UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42440C28UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42440C2CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42440C30UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42440C34UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42440C38UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42440C3CUL))
+#define bFM3_MFT2_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42440F00UL))
+#define bFM3_MFT2_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42440F04UL))
+#define bFM3_MFT2_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42440F08UL))
+#define bFM3_MFT2_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42440F0CUL))
+#define bFM3_MFT2_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42440F10UL))
+#define bFM3_MFT2_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42440F14UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42440F18UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42440F1CUL))
+#define bFM3_MFT2_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42440F20UL))
+#define bFM3_MFT2_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42440F24UL))
+#define bFM3_MFT2_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42440F80UL))
+#define bFM3_MFT2_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42440F84UL))
+#define bFM3_MFT2_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42440F88UL))
+#define bFM3_MFT2_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42440F8CUL))
+#define bFM3_MFT2_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42440F90UL))
+#define bFM3_MFT2_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42440F94UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42440F98UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42440F9CUL))
+#define bFM3_MFT2_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42440FA0UL))
+#define bFM3_MFT2_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42440FA4UL))
+
+/* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define bFM3_MFT2_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42441700UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42441704UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42441708UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42441710UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42441714UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42441718UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42441780UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42441784UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42441788UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4244178CUL))
+#define bFM3_MFT2_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42441790UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42441794UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424417A0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424417A4UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424417A8UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424417ACUL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424417B0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424417B4UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42441800UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42441804UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42441808UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4244180CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42441810UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42441814UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42441820UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42441824UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42441828UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4244182CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42441830UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42441834UL))
+
+/* Multifunction Timer PPG registers */
+#define bFM3_MFT_PPG_TTCR0_STR0                *((volatile unsigned int*)(0x42480020UL))
+#define bFM3_MFT_PPG_TTCR0_MONI0               *((volatile unsigned int*)(0x42480024UL))
+#define bFM3_MFT_PPG_TTCR0_CS00                *((volatile unsigned int*)(0x42480028UL))
+#define bFM3_MFT_PPG_TTCR0_CS01                *((volatile unsigned int*)(0x4248002CUL))
+#define bFM3_MFT_PPG_TTCR0_TRG0O               *((volatile unsigned int*)(0x42480030UL))
+#define bFM3_MFT_PPG_TTCR0_TRG2O               *((volatile unsigned int*)(0x42480034UL))
+#define bFM3_MFT_PPG_TTCR0_TRG4O               *((volatile unsigned int*)(0x42480038UL))
+#define bFM3_MFT_PPG_TTCR0_TRG6O               *((volatile unsigned int*)(0x4248003CUL))
+#define bFM3_MFT_PPG_TTCR1_STR1                *((volatile unsigned int*)(0x42480420UL))
+#define bFM3_MFT_PPG_TTCR1_MONI1               *((volatile unsigned int*)(0x42480424UL))
+#define bFM3_MFT_PPG_TTCR1_CS10                *((volatile unsigned int*)(0x42480428UL))
+#define bFM3_MFT_PPG_TTCR1_CS11                *((volatile unsigned int*)(0x4248042CUL))
+#define bFM3_MFT_PPG_TTCR1_TRG1O               *((volatile unsigned int*)(0x42480430UL))
+#define bFM3_MFT_PPG_TTCR1_TRG3O               *((volatile unsigned int*)(0x42480434UL))
+#define bFM3_MFT_PPG_TTCR1_TRG5O               *((volatile unsigned int*)(0x42480438UL))
+#define bFM3_MFT_PPG_TTCR1_TRG7O               *((volatile unsigned int*)(0x4248043CUL))
+#define bFM3_MFT_PPG_TTCR2_STR2                *((volatile unsigned int*)(0x42480820UL))
+#define bFM3_MFT_PPG_TTCR2_MONI2               *((volatile unsigned int*)(0x42480824UL))
+#define bFM3_MFT_PPG_TTCR2_CS20                *((volatile unsigned int*)(0x42480828UL))
+#define bFM3_MFT_PPG_TTCR2_CS21                *((volatile unsigned int*)(0x4248082CUL))
+#define bFM3_MFT_PPG_TTCR2_TRG16O              *((volatile unsigned int*)(0x42480830UL))
+#define bFM3_MFT_PPG_TTCR2_TRG18O              *((volatile unsigned int*)(0x42480834UL))
+#define bFM3_MFT_PPG_TTCR2_TRG20O              *((volatile unsigned int*)(0x42480838UL))
+#define bFM3_MFT_PPG_TTCR2_TRG22O              *((volatile unsigned int*)(0x4248083CUL))
+#define bFM3_MFT_PPG_TRG_PEN00                 *((volatile unsigned int*)(0x42482000UL))
+#define bFM3_MFT_PPG_TRG_PEN01                 *((volatile unsigned int*)(0x42482004UL))
+#define bFM3_MFT_PPG_TRG_PEN02                 *((volatile unsigned int*)(0x42482008UL))
+#define bFM3_MFT_PPG_TRG_PEN03                 *((volatile unsigned int*)(0x4248200CUL))
+#define bFM3_MFT_PPG_TRG_PEN04                 *((volatile unsigned int*)(0x42482010UL))
+#define bFM3_MFT_PPG_TRG_PEN05                 *((volatile unsigned int*)(0x42482014UL))
+#define bFM3_MFT_PPG_TRG_PEN06                 *((volatile unsigned int*)(0x42482018UL))
+#define bFM3_MFT_PPG_TRG_PEN07                 *((volatile unsigned int*)(0x4248201CUL))
+#define bFM3_MFT_PPG_TRG_PEN08                 *((volatile unsigned int*)(0x42482020UL))
+#define bFM3_MFT_PPG_TRG_PEN09                 *((volatile unsigned int*)(0x42482024UL))
+#define bFM3_MFT_PPG_TRG_PEN10                 *((volatile unsigned int*)(0x42482028UL))
+#define bFM3_MFT_PPG_TRG_PEN11                 *((volatile unsigned int*)(0x4248202CUL))
+#define bFM3_MFT_PPG_TRG_PEN12                 *((volatile unsigned int*)(0x42482030UL))
+#define bFM3_MFT_PPG_TRG_PEN13                 *((volatile unsigned int*)(0x42482034UL))
+#define bFM3_MFT_PPG_TRG_PEN14                 *((volatile unsigned int*)(0x42482038UL))
+#define bFM3_MFT_PPG_TRG_PEN15                 *((volatile unsigned int*)(0x4248203CUL))
+#define bFM3_MFT_PPG_REVC_REV00                *((volatile unsigned int*)(0x42482080UL))
+#define bFM3_MFT_PPG_REVC_REV01                *((volatile unsigned int*)(0x42482084UL))
+#define bFM3_MFT_PPG_REVC_REV02                *((volatile unsigned int*)(0x42482088UL))
+#define bFM3_MFT_PPG_REVC_REV03                *((volatile unsigned int*)(0x4248208CUL))
+#define bFM3_MFT_PPG_REVC_REV04                *((volatile unsigned int*)(0x42482090UL))
+#define bFM3_MFT_PPG_REVC_REV05                *((volatile unsigned int*)(0x42482094UL))
+#define bFM3_MFT_PPG_REVC_REV06                *((volatile unsigned int*)(0x42482098UL))
+#define bFM3_MFT_PPG_REVC_REV07                *((volatile unsigned int*)(0x4248209CUL))
+#define bFM3_MFT_PPG_REVC_REV08                *((volatile unsigned int*)(0x424820A0UL))
+#define bFM3_MFT_PPG_REVC_REV09                *((volatile unsigned int*)(0x424820A4UL))
+#define bFM3_MFT_PPG_REVC_REV10                *((volatile unsigned int*)(0x424820A8UL))
+#define bFM3_MFT_PPG_REVC_REV11                *((volatile unsigned int*)(0x424820ACUL))
+#define bFM3_MFT_PPG_REVC_REV12                *((volatile unsigned int*)(0x424820B0UL))
+#define bFM3_MFT_PPG_REVC_REV13                *((volatile unsigned int*)(0x424820B4UL))
+#define bFM3_MFT_PPG_REVC_REV14                *((volatile unsigned int*)(0x424820B8UL))
+#define bFM3_MFT_PPG_REVC_REV15                *((volatile unsigned int*)(0x424820BCUL))
+#define bFM3_MFT_PPG_TRG1_PEN16                *((volatile unsigned int*)(0x42482800UL))
+#define bFM3_MFT_PPG_TRG1_PEN17                *((volatile unsigned int*)(0x42482804UL))
+#define bFM3_MFT_PPG_TRG1_PEN18                *((volatile unsigned int*)(0x42482808UL))
+#define bFM3_MFT_PPG_TRG1_PEN19                *((volatile unsigned int*)(0x4248280CUL))
+#define bFM3_MFT_PPG_TRG1_PEN20                *((volatile unsigned int*)(0x42482810UL))
+#define bFM3_MFT_PPG_TRG1_PEN21                *((volatile unsigned int*)(0x42482814UL))
+#define bFM3_MFT_PPG_TRG1_PEN22                *((volatile unsigned int*)(0x42482818UL))
+#define bFM3_MFT_PPG_TRG1_PEN23                *((volatile unsigned int*)(0x4248281CUL))
+#define bFM3_MFT_PPG_REVC1_REV16               *((volatile unsigned int*)(0x42482880UL))
+#define bFM3_MFT_PPG_REVC1_REV17               *((volatile unsigned int*)(0x42482884UL))
+#define bFM3_MFT_PPG_REVC1_REV18               *((volatile unsigned int*)(0x42482888UL))
+#define bFM3_MFT_PPG_REVC1_REV19               *((volatile unsigned int*)(0x4248288CUL))
+#define bFM3_MFT_PPG_REVC1_REV20               *((volatile unsigned int*)(0x42482890UL))
+#define bFM3_MFT_PPG_REVC1_REV21               *((volatile unsigned int*)(0x42482894UL))
+#define bFM3_MFT_PPG_REVC1_REV22               *((volatile unsigned int*)(0x42482898UL))
+#define bFM3_MFT_PPG_REVC1_REV23               *((volatile unsigned int*)(0x4248289CUL))
+#define bFM3_MFT_PPG_PPGC1_TTRG                *((volatile unsigned int*)(0x42484000UL))
+#define bFM3_MFT_PPG_PPGC1_MD0                 *((volatile unsigned int*)(0x42484004UL))
+#define bFM3_MFT_PPG_PPGC1_MD1                 *((volatile unsigned int*)(0x42484008UL))
+#define bFM3_MFT_PPG_PPGC1_PCS0                *((volatile unsigned int*)(0x4248400CUL))
+#define bFM3_MFT_PPG_PPGC1_PCS1                *((volatile unsigned int*)(0x42484010UL))
+#define bFM3_MFT_PPG_PPGC1_INTM                *((volatile unsigned int*)(0x42484014UL))
+#define bFM3_MFT_PPG_PPGC1_PUF                 *((volatile unsigned int*)(0x42484018UL))
+#define bFM3_MFT_PPG_PPGC1_PIE                 *((volatile unsigned int*)(0x4248401CUL))
+#define bFM3_MFT_PPG_PPGC0_TTRG                *((volatile unsigned int*)(0x42484020UL))
+#define bFM3_MFT_PPG_PPGC0_MD0                 *((volatile unsigned int*)(0x42484024UL))
+#define bFM3_MFT_PPG_PPGC0_MD1                 *((volatile unsigned int*)(0x42484028UL))
+#define bFM3_MFT_PPG_PPGC0_PCS0                *((volatile unsigned int*)(0x4248402CUL))
+#define bFM3_MFT_PPG_PPGC0_PCS1                *((volatile unsigned int*)(0x42484030UL))
+#define bFM3_MFT_PPG_PPGC0_INTM                *((volatile unsigned int*)(0x42484034UL))
+#define bFM3_MFT_PPG_PPGC0_PUF                 *((volatile unsigned int*)(0x42484038UL))
+#define bFM3_MFT_PPG_PPGC0_PIE                 *((volatile unsigned int*)(0x4248403CUL))
+#define bFM3_MFT_PPG_PPGC3_TTRG                *((volatile unsigned int*)(0x42484080UL))
+#define bFM3_MFT_PPG_PPGC3_MD0                 *((volatile unsigned int*)(0x42484084UL))
+#define bFM3_MFT_PPG_PPGC3_MD1                 *((volatile unsigned int*)(0x42484088UL))
+#define bFM3_MFT_PPG_PPGC3_PCS0                *((volatile unsigned int*)(0x4248408CUL))
+#define bFM3_MFT_PPG_PPGC3_PCS1                *((volatile unsigned int*)(0x42484090UL))
+#define bFM3_MFT_PPG_PPGC3_INTM                *((volatile unsigned int*)(0x42484094UL))
+#define bFM3_MFT_PPG_PPGC3_PUF                 *((volatile unsigned int*)(0x42484098UL))
+#define bFM3_MFT_PPG_PPGC3_PIE                 *((volatile unsigned int*)(0x4248409CUL))
+#define bFM3_MFT_PPG_PPGC2_TTRG                *((volatile unsigned int*)(0x424840A0UL))
+#define bFM3_MFT_PPG_PPGC2_MD0                 *((volatile unsigned int*)(0x424840A4UL))
+#define bFM3_MFT_PPG_PPGC2_MD1                 *((volatile unsigned int*)(0x424840A8UL))
+#define bFM3_MFT_PPG_PPGC2_PCS0                *((volatile unsigned int*)(0x424840ACUL))
+#define bFM3_MFT_PPG_PPGC2_PCS1                *((volatile unsigned int*)(0x424840B0UL))
+#define bFM3_MFT_PPG_PPGC2_INTM                *((volatile unsigned int*)(0x424840B4UL))
+#define bFM3_MFT_PPG_PPGC2_PUF                 *((volatile unsigned int*)(0x424840B8UL))
+#define bFM3_MFT_PPG_PPGC2_PIE                 *((volatile unsigned int*)(0x424840BCUL))
+#define bFM3_MFT_PPG_GATEC0_EDGE0              *((volatile unsigned int*)(0x42484300UL))
+#define bFM3_MFT_PPG_GATEC0_STRG0              *((volatile unsigned int*)(0x42484304UL))
+#define bFM3_MFT_PPG_GATEC0_EDGE2              *((volatile unsigned int*)(0x42484310UL))
+#define bFM3_MFT_PPG_GATEC0_STRG2              *((volatile unsigned int*)(0x42484314UL))
+#define bFM3_MFT_PPG_PPGC5_TTRG                *((volatile unsigned int*)(0x42484800UL))
+#define bFM3_MFT_PPG_PPGC5_MD0                 *((volatile unsigned int*)(0x42484804UL))
+#define bFM3_MFT_PPG_PPGC5_MD1                 *((volatile unsigned int*)(0x42484808UL))
+#define bFM3_MFT_PPG_PPGC5_PCS0                *((volatile unsigned int*)(0x4248480CUL))
+#define bFM3_MFT_PPG_PPGC5_PCS1                *((volatile unsigned int*)(0x42484810UL))
+#define bFM3_MFT_PPG_PPGC5_INTM                *((volatile unsigned int*)(0x42484814UL))
+#define bFM3_MFT_PPG_PPGC5_PUF                 *((volatile unsigned int*)(0x42484818UL))
+#define bFM3_MFT_PPG_PPGC5_PIE                 *((volatile unsigned int*)(0x4248481CUL))
+#define bFM3_MFT_PPG_PPGC4_TTRG                *((volatile unsigned int*)(0x42484820UL))
+#define bFM3_MFT_PPG_PPGC4_MD0                 *((volatile unsigned int*)(0x42484824UL))
+#define bFM3_MFT_PPG_PPGC4_MD1                 *((volatile unsigned int*)(0x42484828UL))
+#define bFM3_MFT_PPG_PPGC4_PCS0                *((volatile unsigned int*)(0x4248482CUL))
+#define bFM3_MFT_PPG_PPGC4_PCS1                *((volatile unsigned int*)(0x42484830UL))
+#define bFM3_MFT_PPG_PPGC4_INTM                *((volatile unsigned int*)(0x42484834UL))
+#define bFM3_MFT_PPG_PPGC4_PUF                 *((volatile unsigned int*)(0x42484838UL))
+#define bFM3_MFT_PPG_PPGC4_PIE                 *((volatile unsigned int*)(0x4248483CUL))
+#define bFM3_MFT_PPG_PPGC7_TTRG                *((volatile unsigned int*)(0x42484880UL))
+#define bFM3_MFT_PPG_PPGC7_MD0                 *((volatile unsigned int*)(0x42484884UL))
+#define bFM3_MFT_PPG_PPGC7_MD1                 *((volatile unsigned int*)(0x42484888UL))
+#define bFM3_MFT_PPG_PPGC7_PCS0                *((volatile unsigned int*)(0x4248488CUL))
+#define bFM3_MFT_PPG_PPGC7_PCS1                *((volatile unsigned int*)(0x42484890UL))
+#define bFM3_MFT_PPG_PPGC7_INTM                *((volatile unsigned int*)(0x42484894UL))
+#define bFM3_MFT_PPG_PPGC7_PUF                 *((volatile unsigned int*)(0x42484898UL))
+#define bFM3_MFT_PPG_PPGC7_PIE                 *((volatile unsigned int*)(0x4248489CUL))
+#define bFM3_MFT_PPG_PPGC6_TTRG                *((volatile unsigned int*)(0x424848A0UL))
+#define bFM3_MFT_PPG_PPGC6_MD0                 *((volatile unsigned int*)(0x424848A4UL))
+#define bFM3_MFT_PPG_PPGC6_MD1                 *((volatile unsigned int*)(0x424848A8UL))
+#define bFM3_MFT_PPG_PPGC6_PCS0                *((volatile unsigned int*)(0x424848ACUL))
+#define bFM3_MFT_PPG_PPGC6_PCS1                *((volatile unsigned int*)(0x424848B0UL))
+#define bFM3_MFT_PPG_PPGC6_INTM                *((volatile unsigned int*)(0x424848B4UL))
+#define bFM3_MFT_PPG_PPGC6_PUF                 *((volatile unsigned int*)(0x424848B8UL))
+#define bFM3_MFT_PPG_PPGC6_PIE                 *((volatile unsigned int*)(0x424848BCUL))
+#define bFM3_MFT_PPG_GATEC4_EDGE4              *((volatile unsigned int*)(0x42484B00UL))
+#define bFM3_MFT_PPG_GATEC4_STRG4              *((volatile unsigned int*)(0x42484B04UL))
+#define bFM3_MFT_PPG_GATEC4_EDGE6              *((volatile unsigned int*)(0x42484B10UL))
+#define bFM3_MFT_PPG_GATEC4_STRG6              *((volatile unsigned int*)(0x42484B14UL))
+#define bFM3_MFT_PPG_PPGC9_TTRG                *((volatile unsigned int*)(0x42485000UL))
+#define bFM3_MFT_PPG_PPGC9_MD0                 *((volatile unsigned int*)(0x42485004UL))
+#define bFM3_MFT_PPG_PPGC9_MD1                 *((volatile unsigned int*)(0x42485008UL))
+#define bFM3_MFT_PPG_PPGC9_PCS0                *((volatile unsigned int*)(0x4248500CUL))
+#define bFM3_MFT_PPG_PPGC9_PCS1                *((volatile unsigned int*)(0x42485010UL))
+#define bFM3_MFT_PPG_PPGC9_INTM                *((volatile unsigned int*)(0x42485014UL))
+#define bFM3_MFT_PPG_PPGC9_PUF                 *((volatile unsigned int*)(0x42485018UL))
+#define bFM3_MFT_PPG_PPGC9_PIE                 *((volatile unsigned int*)(0x4248501CUL))
+#define bFM3_MFT_PPG_PPGC8_TTRG                *((volatile unsigned int*)(0x42485020UL))
+#define bFM3_MFT_PPG_PPGC8_MD0                 *((volatile unsigned int*)(0x42485024UL))
+#define bFM3_MFT_PPG_PPGC8_MD1                 *((volatile unsigned int*)(0x42485028UL))
+#define bFM3_MFT_PPG_PPGC8_PCS0                *((volatile unsigned int*)(0x4248502CUL))
+#define bFM3_MFT_PPG_PPGC8_PCS1                *((volatile unsigned int*)(0x42485030UL))
+#define bFM3_MFT_PPG_PPGC8_INTM                *((volatile unsigned int*)(0x42485034UL))
+#define bFM3_MFT_PPG_PPGC8_PUF                 *((volatile unsigned int*)(0x42485038UL))
+#define bFM3_MFT_PPG_PPGC8_PIE                 *((volatile unsigned int*)(0x4248503CUL))
+#define bFM3_MFT_PPG_PPGC11_TTRG               *((volatile unsigned int*)(0x42485080UL))
+#define bFM3_MFT_PPG_PPGC11_MD0                *((volatile unsigned int*)(0x42485084UL))
+#define bFM3_MFT_PPG_PPGC11_MD1                *((volatile unsigned int*)(0x42485088UL))
+#define bFM3_MFT_PPG_PPGC11_PCS0               *((volatile unsigned int*)(0x4248508CUL))
+#define bFM3_MFT_PPG_PPGC11_PCS1               *((volatile unsigned int*)(0x42485090UL))
+#define bFM3_MFT_PPG_PPGC11_INTM               *((volatile unsigned int*)(0x42485094UL))
+#define bFM3_MFT_PPG_PPGC11_PUF                *((volatile unsigned int*)(0x42485098UL))
+#define bFM3_MFT_PPG_PPGC11_PIE                *((volatile unsigned int*)(0x4248509CUL))
+#define bFM3_MFT_PPG_PPGC10_TTRG               *((volatile unsigned int*)(0x424850A0UL))
+#define bFM3_MFT_PPG_PPGC10_MD0                *((volatile unsigned int*)(0x424850A4UL))
+#define bFM3_MFT_PPG_PPGC10_MD1                *((volatile unsigned int*)(0x424850A8UL))
+#define bFM3_MFT_PPG_PPGC10_PCS0               *((volatile unsigned int*)(0x424850ACUL))
+#define bFM3_MFT_PPG_PPGC10_PCS1               *((volatile unsigned int*)(0x424850B0UL))
+#define bFM3_MFT_PPG_PPGC10_INTM               *((volatile unsigned int*)(0x424850B4UL))
+#define bFM3_MFT_PPG_PPGC10_PUF                *((volatile unsigned int*)(0x424850B8UL))
+#define bFM3_MFT_PPG_PPGC10_PIE                *((volatile unsigned int*)(0x424850BCUL))
+#define bFM3_MFT_PPG_GATEC8_EDGE8              *((volatile unsigned int*)(0x42485300UL))
+#define bFM3_MFT_PPG_GATEC8_STRG8              *((volatile unsigned int*)(0x42485304UL))
+#define bFM3_MFT_PPG_GATEC8_EDGE10             *((volatile unsigned int*)(0x42485310UL))
+#define bFM3_MFT_PPG_GATEC8_STRG10             *((volatile unsigned int*)(0x42485314UL))
+#define bFM3_MFT_PPG_PPGC13_TTRG               *((volatile unsigned int*)(0x42485800UL))
+#define bFM3_MFT_PPG_PPGC13_MD0                *((volatile unsigned int*)(0x42485804UL))
+#define bFM3_MFT_PPG_PPGC13_MD1                *((volatile unsigned int*)(0x42485808UL))
+#define bFM3_MFT_PPG_PPGC13_PCS0               *((volatile unsigned int*)(0x4248580CUL))
+#define bFM3_MFT_PPG_PPGC13_PCS1               *((volatile unsigned int*)(0x42485810UL))
+#define bFM3_MFT_PPG_PPGC13_INTM               *((volatile unsigned int*)(0x42485814UL))
+#define bFM3_MFT_PPG_PPGC13_PUF                *((volatile unsigned int*)(0x42485818UL))
+#define bFM3_MFT_PPG_PPGC13_PIE                *((volatile unsigned int*)(0x4248581CUL))
+#define bFM3_MFT_PPG_PPGC12_TTRG               *((volatile unsigned int*)(0x42485820UL))
+#define bFM3_MFT_PPG_PPGC12_MD0                *((volatile unsigned int*)(0x42485824UL))
+#define bFM3_MFT_PPG_PPGC12_MD1                *((volatile unsigned int*)(0x42485828UL))
+#define bFM3_MFT_PPG_PPGC12_PCS0               *((volatile unsigned int*)(0x4248582CUL))
+#define bFM3_MFT_PPG_PPGC12_PCS1               *((volatile unsigned int*)(0x42485830UL))
+#define bFM3_MFT_PPG_PPGC12_INTM               *((volatile unsigned int*)(0x42485834UL))
+#define bFM3_MFT_PPG_PPGC12_PUF                *((volatile unsigned int*)(0x42485838UL))
+#define bFM3_MFT_PPG_PPGC12_PIE                *((volatile unsigned int*)(0x4248583CUL))
+#define bFM3_MFT_PPG_PPGC15_TTRG               *((volatile unsigned int*)(0x42485880UL))
+#define bFM3_MFT_PPG_PPGC15_MD0                *((volatile unsigned int*)(0x42485884UL))
+#define bFM3_MFT_PPG_PPGC15_MD1                *((volatile unsigned int*)(0x42485888UL))
+#define bFM3_MFT_PPG_PPGC15_PCS0               *((volatile unsigned int*)(0x4248588CUL))
+#define bFM3_MFT_PPG_PPGC15_PCS1               *((volatile unsigned int*)(0x42485890UL))
+#define bFM3_MFT_PPG_PPGC15_INTM               *((volatile unsigned int*)(0x42485894UL))
+#define bFM3_MFT_PPG_PPGC15_PUF                *((volatile unsigned int*)(0x42485898UL))
+#define bFM3_MFT_PPG_PPGC15_PIE                *((volatile unsigned int*)(0x4248589CUL))
+#define bFM3_MFT_PPG_PPGC14_TTRG               *((volatile unsigned int*)(0x424858A0UL))
+#define bFM3_MFT_PPG_PPGC14_MD0                *((volatile unsigned int*)(0x424858A4UL))
+#define bFM3_MFT_PPG_PPGC14_MD1                *((volatile unsigned int*)(0x424858A8UL))
+#define bFM3_MFT_PPG_PPGC14_PCS0               *((volatile unsigned int*)(0x424858ACUL))
+#define bFM3_MFT_PPG_PPGC14_PCS1               *((volatile unsigned int*)(0x424858B0UL))
+#define bFM3_MFT_PPG_PPGC14_INTM               *((volatile unsigned int*)(0x424858B4UL))
+#define bFM3_MFT_PPG_PPGC14_PUF                *((volatile unsigned int*)(0x424858B8UL))
+#define bFM3_MFT_PPG_PPGC14_PIE                *((volatile unsigned int*)(0x424858BCUL))
+#define bFM3_MFT_PPG_GATEC12_EDGE12            *((volatile unsigned int*)(0x42485B00UL))
+#define bFM3_MFT_PPG_GATEC12_STRG12            *((volatile unsigned int*)(0x42485B04UL))
+#define bFM3_MFT_PPG_GATEC12_EDGE14            *((volatile unsigned int*)(0x42485B10UL))
+#define bFM3_MFT_PPG_GATEC12_STRG14            *((volatile unsigned int*)(0x42485B14UL))
+#define bFM3_MFT_PPG_PPGC17_TTRG               *((volatile unsigned int*)(0x42486000UL))
+#define bFM3_MFT_PPG_PPGC17_MD0                *((volatile unsigned int*)(0x42486004UL))
+#define bFM3_MFT_PPG_PPGC17_MD1                *((volatile unsigned int*)(0x42486008UL))
+#define bFM3_MFT_PPG_PPGC17_PCS0               *((volatile unsigned int*)(0x4248600CUL))
+#define bFM3_MFT_PPG_PPGC17_PCS1               *((volatile unsigned int*)(0x42486010UL))
+#define bFM3_MFT_PPG_PPGC17_INTM               *((volatile unsigned int*)(0x42486014UL))
+#define bFM3_MFT_PPG_PPGC17_PUF                *((volatile unsigned int*)(0x42486018UL))
+#define bFM3_MFT_PPG_PPGC17_PIE                *((volatile unsigned int*)(0x4248601CUL))
+#define bFM3_MFT_PPG_PPGC16_TTRG               *((volatile unsigned int*)(0x42486020UL))
+#define bFM3_MFT_PPG_PPGC16_MD0                *((volatile unsigned int*)(0x42486024UL))
+#define bFM3_MFT_PPG_PPGC16_MD1                *((volatile unsigned int*)(0x42486028UL))
+#define bFM3_MFT_PPG_PPGC16_PCS0               *((volatile unsigned int*)(0x4248602CUL))
+#define bFM3_MFT_PPG_PPGC16_PCS1               *((volatile unsigned int*)(0x42486030UL))
+#define bFM3_MFT_PPG_PPGC16_INTM               *((volatile unsigned int*)(0x42486034UL))
+#define bFM3_MFT_PPG_PPGC16_PUF                *((volatile unsigned int*)(0x42486038UL))
+#define bFM3_MFT_PPG_PPGC16_PIE                *((volatile unsigned int*)(0x4248603CUL))
+#define bFM3_MFT_PPG_PPGC19_TTRG               *((volatile unsigned int*)(0x42486080UL))
+#define bFM3_MFT_PPG_PPGC19_MD0                *((volatile unsigned int*)(0x42486084UL))
+#define bFM3_MFT_PPG_PPGC19_MD1                *((volatile unsigned int*)(0x42486088UL))
+#define bFM3_MFT_PPG_PPGC19_PCS0               *((volatile unsigned int*)(0x4248608CUL))
+#define bFM3_MFT_PPG_PPGC19_PCS1               *((volatile unsigned int*)(0x42486090UL))
+#define bFM3_MFT_PPG_PPGC19_INTM               *((volatile unsigned int*)(0x42486094UL))
+#define bFM3_MFT_PPG_PPGC19_PUF                *((volatile unsigned int*)(0x42486098UL))
+#define bFM3_MFT_PPG_PPGC19_PIE                *((volatile unsigned int*)(0x4248609CUL))
+#define bFM3_MFT_PPG_PPGC18_TTRG               *((volatile unsigned int*)(0x424860A0UL))
+#define bFM3_MFT_PPG_PPGC18_MD0                *((volatile unsigned int*)(0x424860A4UL))
+#define bFM3_MFT_PPG_PPGC18_MD1                *((volatile unsigned int*)(0x424860A8UL))
+#define bFM3_MFT_PPG_PPGC18_PCS0               *((volatile unsigned int*)(0x424860ACUL))
+#define bFM3_MFT_PPG_PPGC18_PCS1               *((volatile unsigned int*)(0x424860B0UL))
+#define bFM3_MFT_PPG_PPGC18_INTM               *((volatile unsigned int*)(0x424860B4UL))
+#define bFM3_MFT_PPG_PPGC18_PUF                *((volatile unsigned int*)(0x424860B8UL))
+#define bFM3_MFT_PPG_PPGC18_PIE                *((volatile unsigned int*)(0x424860BCUL))
+#define bFM3_MFT_PPG_GATEC16_EDGE16            *((volatile unsigned int*)(0x42486300UL))
+#define bFM3_MFT_PPG_GATEC16_STRG16            *((volatile unsigned int*)(0x42486304UL))
+#define bFM3_MFT_PPG_GATEC16_EDGE18            *((volatile unsigned int*)(0x42486310UL))
+#define bFM3_MFT_PPG_GATEC16_STRG18            *((volatile unsigned int*)(0x42486314UL))
+#define bFM3_MFT_PPG_PPGC21_TTRG               *((volatile unsigned int*)(0x42486800UL))
+#define bFM3_MFT_PPG_PPGC21_MD0                *((volatile unsigned int*)(0x42486804UL))
+#define bFM3_MFT_PPG_PPGC21_MD1                *((volatile unsigned int*)(0x42486808UL))
+#define bFM3_MFT_PPG_PPGC21_PCS0               *((volatile unsigned int*)(0x4248680CUL))
+#define bFM3_MFT_PPG_PPGC21_PCS1               *((volatile unsigned int*)(0x42486810UL))
+#define bFM3_MFT_PPG_PPGC21_INTM               *((volatile unsigned int*)(0x42486814UL))
+#define bFM3_MFT_PPG_PPGC21_PUF                *((volatile unsigned int*)(0x42486818UL))
+#define bFM3_MFT_PPG_PPGC21_PIE                *((volatile unsigned int*)(0x4248681CUL))
+#define bFM3_MFT_PPG_PPGC20_TTRG               *((volatile unsigned int*)(0x42486820UL))
+#define bFM3_MFT_PPG_PPGC20_MD0                *((volatile unsigned int*)(0x42486824UL))
+#define bFM3_MFT_PPG_PPGC20_MD1                *((volatile unsigned int*)(0x42486828UL))
+#define bFM3_MFT_PPG_PPGC20_PCS0               *((volatile unsigned int*)(0x4248682CUL))
+#define bFM3_MFT_PPG_PPGC20_PCS1               *((volatile unsigned int*)(0x42486830UL))
+#define bFM3_MFT_PPG_PPGC20_INTM               *((volatile unsigned int*)(0x42486834UL))
+#define bFM3_MFT_PPG_PPGC20_PUF                *((volatile unsigned int*)(0x42486838UL))
+#define bFM3_MFT_PPG_PPGC20_PIE                *((volatile unsigned int*)(0x4248683CUL))
+#define bFM3_MFT_PPG_PPGC23_TTRG               *((volatile unsigned int*)(0x42486880UL))
+#define bFM3_MFT_PPG_PPGC23_MD0                *((volatile unsigned int*)(0x42486884UL))
+#define bFM3_MFT_PPG_PPGC23_MD1                *((volatile unsigned int*)(0x42486888UL))
+#define bFM3_MFT_PPG_PPGC23_PCS0               *((volatile unsigned int*)(0x4248688CUL))
+#define bFM3_MFT_PPG_PPGC23_PCS1               *((volatile unsigned int*)(0x42486890UL))
+#define bFM3_MFT_PPG_PPGC23_INTM               *((volatile unsigned int*)(0x42486894UL))
+#define bFM3_MFT_PPG_PPGC23_PUF                *((volatile unsigned int*)(0x42486898UL))
+#define bFM3_MFT_PPG_PPGC23_PIE                *((volatile unsigned int*)(0x4248689CUL))
+#define bFM3_MFT_PPG_PPGC22_TTRG               *((volatile unsigned int*)(0x424868A0UL))
+#define bFM3_MFT_PPG_PPGC22_MD0                *((volatile unsigned int*)(0x424868A4UL))
+#define bFM3_MFT_PPG_PPGC22_MD1                *((volatile unsigned int*)(0x424868A8UL))
+#define bFM3_MFT_PPG_PPGC22_PCS0               *((volatile unsigned int*)(0x424868ACUL))
+#define bFM3_MFT_PPG_PPGC22_PCS1               *((volatile unsigned int*)(0x424868B0UL))
+#define bFM3_MFT_PPG_PPGC22_INTM               *((volatile unsigned int*)(0x424868B4UL))
+#define bFM3_MFT_PPG_PPGC22_PUF                *((volatile unsigned int*)(0x424868B8UL))
+#define bFM3_MFT_PPG_PPGC22_PIE                *((volatile unsigned int*)(0x424868BCUL))
+#define bFM3_MFT_PPG_GATEC20_EDGE20            *((volatile unsigned int*)(0x42486B00UL))
+#define bFM3_MFT_PPG_GATEC20_STRG20            *((volatile unsigned int*)(0x42486B04UL))
+#define bFM3_MFT_PPG_GATEC20_EDGE22            *((volatile unsigned int*)(0x42486B10UL))
+#define bFM3_MFT_PPG_GATEC20_STRG22            *((volatile unsigned int*)(0x42486B14UL))
+
+/* Base Timer 0 PPG registers */
+#define bFM3_BT0_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWM registers */
+#define bFM3_BT0_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0204UL))
+#define bFM3_BT0_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0214UL))
+#define bFM3_BT0_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 RT registers */
+#define bFM3_BT0_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWC registers */
+#define bFM3_BT0_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0190UL))
+#define bFM3_BT0_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0194UL))
+#define bFM3_BT0_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0198UL))
+#define bFM3_BT0_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A021CUL))
+#define bFM3_BT0_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 1 PPG registers */
+#define bFM3_BT1_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWM registers */
+#define bFM3_BT1_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0A04UL))
+#define bFM3_BT1_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0A14UL))
+#define bFM3_BT1_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 RT registers */
+#define bFM3_BT1_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWC registers */
+#define bFM3_BT1_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A0990UL))
+#define bFM3_BT1_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A0994UL))
+#define bFM3_BT1_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A0998UL))
+#define bFM3_BT1_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A0A1CUL))
+#define bFM3_BT1_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 2 PPG registers */
+#define bFM3_BT2_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWM registers */
+#define bFM3_BT2_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1204UL))
+#define bFM3_BT2_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1214UL))
+#define bFM3_BT2_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 RT registers */
+#define bFM3_BT2_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWC registers */
+#define bFM3_BT2_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1190UL))
+#define bFM3_BT2_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1194UL))
+#define bFM3_BT2_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1198UL))
+#define bFM3_BT2_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A121CUL))
+#define bFM3_BT2_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 3 PPG registers */
+#define bFM3_BT3_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWM registers */
+#define bFM3_BT3_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1A04UL))
+#define bFM3_BT3_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1A14UL))
+#define bFM3_BT3_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 RT registers */
+#define bFM3_BT3_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWC registers */
+#define bFM3_BT3_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A1990UL))
+#define bFM3_BT3_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A1994UL))
+#define bFM3_BT3_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A1998UL))
+#define bFM3_BT3_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A1A1CUL))
+#define bFM3_BT3_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 4 PPG registers */
+#define bFM3_BT4_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWM registers */
+#define bFM3_BT4_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4204UL))
+#define bFM3_BT4_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4214UL))
+#define bFM3_BT4_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 RT registers */
+#define bFM3_BT4_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWC registers */
+#define bFM3_BT4_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4190UL))
+#define bFM3_BT4_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4194UL))
+#define bFM3_BT4_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4198UL))
+#define bFM3_BT4_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A421CUL))
+#define bFM3_BT4_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 5 PPG registers */
+#define bFM3_BT5_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWM registers */
+#define bFM3_BT5_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4A04UL))
+#define bFM3_BT5_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4A14UL))
+#define bFM3_BT5_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 RT registers */
+#define bFM3_BT5_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWC registers */
+#define bFM3_BT5_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A4990UL))
+#define bFM3_BT5_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A4994UL))
+#define bFM3_BT5_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A4998UL))
+#define bFM3_BT5_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A4A1CUL))
+#define bFM3_BT5_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 6 PPG registers */
+#define bFM3_BT6_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWM registers */
+#define bFM3_BT6_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5204UL))
+#define bFM3_BT6_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5214UL))
+#define bFM3_BT6_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 RT registers */
+#define bFM3_BT6_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWC registers */
+#define bFM3_BT6_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5190UL))
+#define bFM3_BT6_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5194UL))
+#define bFM3_BT6_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5198UL))
+#define bFM3_BT6_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A521CUL))
+#define bFM3_BT6_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 7 PPG registers */
+#define bFM3_BT7_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWM registers */
+#define bFM3_BT7_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5A04UL))
+#define bFM3_BT7_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5A14UL))
+#define bFM3_BT7_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 RT registers */
+#define bFM3_BT7_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWC registers */
+#define bFM3_BT7_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A5990UL))
+#define bFM3_BT7_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A5994UL))
+#define bFM3_BT7_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A5998UL))
+#define bFM3_BT7_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A5A1CUL))
+#define bFM3_BT7_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0       *((volatile unsigned int*)(0x424A2020UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1       *((volatile unsigned int*)(0x424A2024UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2       *((volatile unsigned int*)(0x424A2028UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3       *((volatile unsigned int*)(0x424A202CUL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0       *((volatile unsigned int*)(0x424A2030UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1       *((volatile unsigned int*)(0x424A2034UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2       *((volatile unsigned int*)(0x424A2038UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3       *((volatile unsigned int*)(0x424A203CUL))
+
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0       *((volatile unsigned int*)(0x424A6020UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1       *((volatile unsigned int*)(0x424A6024UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2       *((volatile unsigned int*)(0x424A6028UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3       *((volatile unsigned int*)(0x424A602CUL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0       *((volatile unsigned int*)(0x424A6030UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1       *((volatile unsigned int*)(0x424A6034UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2       *((volatile unsigned int*)(0x424A6038UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3       *((volatile unsigned int*)(0x424A603CUL))
+
+/* Base Timer 8 PPG registers */
+#define bFM3_BT8_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWM registers */
+#define bFM3_BT8_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8204UL))
+#define bFM3_BT8_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8214UL))
+#define bFM3_BT8_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 RT registers */
+#define bFM3_BT8_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWC registers */
+#define bFM3_BT8_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8190UL))
+#define bFM3_BT8_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8194UL))
+#define bFM3_BT8_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8198UL))
+#define bFM3_BT8_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A821CUL))
+#define bFM3_BT8_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 9 PPG registers */
+#define bFM3_BT9_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PPG_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_PPG_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_PPG_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWM registers */
+#define bFM3_BT9_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PWM_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_PWM_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_PWM_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8A04UL))
+#define bFM3_BT9_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8A14UL))
+#define bFM3_BT9_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 RT registers */
+#define bFM3_BT9_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_RT_TMCR_FMD0                  *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_RT_TMCR_FMD1                  *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_RT_TMCR_FMD2                  *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWC registers */
+#define bFM3_BT9_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWC_TMCR_FMD0                 *((volatile unsigned int*)(0x424A8990UL))
+#define bFM3_BT9_PWC_TMCR_FMD1                 *((volatile unsigned int*)(0x424A8994UL))
+#define bFM3_BT9_PWC_TMCR_FMD2                 *((volatile unsigned int*)(0x424A8998UL))
+#define bFM3_BT9_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A8A1CUL))
+#define bFM3_BT9_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 10 PPG registers */
+#define bFM3_BT10_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWM registers */
+#define bFM3_BT10_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9204UL))
+#define bFM3_BT10_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9214UL))
+#define bFM3_BT10_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 RT registers */
+#define bFM3_BT10_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWC registers */
+#define bFM3_BT10_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424A9190UL))
+#define bFM3_BT10_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424A9194UL))
+#define bFM3_BT10_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424A9198UL))
+#define bFM3_BT10_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A921CUL))
+#define bFM3_BT10_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 11 PPG registers */
+#define bFM3_BT11_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWM registers */
+#define bFM3_BT11_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9A04UL))
+#define bFM3_BT11_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9A14UL))
+#define bFM3_BT11_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 RT registers */
+#define bFM3_BT11_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWC registers */
+#define bFM3_BT11_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424A9990UL))
+#define bFM3_BT11_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424A9994UL))
+#define bFM3_BT11_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424A9998UL))
+#define bFM3_BT11_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A9A1CUL))
+#define bFM3_BT11_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 12 PPG registers */
+#define bFM3_BT12_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWM registers */
+#define bFM3_BT12_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AC204UL))
+#define bFM3_BT12_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AC214UL))
+#define bFM3_BT12_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 RT registers */
+#define bFM3_BT12_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWC registers */
+#define bFM3_BT12_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AC190UL))
+#define bFM3_BT12_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AC194UL))
+#define bFM3_BT12_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AC198UL))
+#define bFM3_BT12_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AC21CUL))
+#define bFM3_BT12_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 13 PPG registers */
+#define bFM3_BT13_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWM registers */
+#define bFM3_BT13_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ACA04UL))
+#define bFM3_BT13_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ACA14UL))
+#define bFM3_BT13_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 RT registers */
+#define bFM3_BT13_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWC registers */
+#define bFM3_BT13_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AC990UL))
+#define bFM3_BT13_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AC994UL))
+#define bFM3_BT13_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AC998UL))
+#define bFM3_BT13_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ACA1CUL))
+#define bFM3_BT13_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 14 PPG registers */
+#define bFM3_BT14_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWM registers */
+#define bFM3_BT14_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AD204UL))
+#define bFM3_BT14_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AD214UL))
+#define bFM3_BT14_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 RT registers */
+#define bFM3_BT14_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWC registers */
+#define bFM3_BT14_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AD190UL))
+#define bFM3_BT14_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AD194UL))
+#define bFM3_BT14_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AD198UL))
+#define bFM3_BT14_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AD21CUL))
+#define bFM3_BT14_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 15 PPG registers */
+#define bFM3_BT15_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PPG_TMCR_FMD0                *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_PPG_TMCR_FMD1                *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_PPG_TMCR_FMD2                *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWM registers */
+#define bFM3_BT15_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PWM_TMCR_FMD0                *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_PWM_TMCR_FMD1                *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_PWM_TMCR_FMD2                *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ADA04UL))
+#define bFM3_BT15_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ADA14UL))
+#define bFM3_BT15_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 RT registers */
+#define bFM3_BT15_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_RT_TMCR_FMD0                 *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_RT_TMCR_FMD1                 *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_RT_TMCR_FMD2                 *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWC registers */
+#define bFM3_BT15_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWC_TMCR_FMD0                *((volatile unsigned int*)(0x424AD990UL))
+#define bFM3_BT15_PWC_TMCR_FMD1                *((volatile unsigned int*)(0x424AD994UL))
+#define bFM3_BT15_PWC_TMCR_FMD2                *((volatile unsigned int*)(0x424AD998UL))
+#define bFM3_BT15_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ADA1CUL))
+#define bFM3_BT15_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0       *((volatile unsigned int*)(0x424AA020UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1       *((volatile unsigned int*)(0x424AA024UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2       *((volatile unsigned int*)(0x424AA028UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3       *((volatile unsigned int*)(0x424AA02CUL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0       *((volatile unsigned int*)(0x424AA030UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1       *((volatile unsigned int*)(0x424AA034UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2       *((volatile unsigned int*)(0x424AA038UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3       *((volatile unsigned int*)(0x424AA03CUL))
+
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0       *((volatile unsigned int*)(0x424AE020UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1       *((volatile unsigned int*)(0x424AE024UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2       *((volatile unsigned int*)(0x424AE028UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3       *((volatile unsigned int*)(0x424AE02CUL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0       *((volatile unsigned int*)(0x424AE030UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1       *((volatile unsigned int*)(0x424AE034UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2       *((volatile unsigned int*)(0x424AE038UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3       *((volatile unsigned int*)(0x424AE03CUL))
+
+/* Software based Simulation Startup (Base Timer) register */
+#define bFM3_SBSSR_BTSSSR_SSR0                 *((volatile unsigned int*)(0x424BFF80UL))
+#define bFM3_SBSSR_BTSSSR_SSR1                 *((volatile unsigned int*)(0x424BFF84UL))
+#define bFM3_SBSSR_BTSSSR_SSR2                 *((volatile unsigned int*)(0x424BFF88UL))
+#define bFM3_SBSSR_BTSSSR_SSR3                 *((volatile unsigned int*)(0x424BFF8CUL))
+#define bFM3_SBSSR_BTSSSR_SSR4                 *((volatile unsigned int*)(0x424BFF90UL))
+#define bFM3_SBSSR_BTSSSR_SSR5                 *((volatile unsigned int*)(0x424BFF94UL))
+#define bFM3_SBSSR_BTSSSR_SSR6                 *((volatile unsigned int*)(0x424BFF98UL))
+#define bFM3_SBSSR_BTSSSR_SSR7                 *((volatile unsigned int*)(0x424BFF9CUL))
+#define bFM3_SBSSR_BTSSSR_SSR8                 *((volatile unsigned int*)(0x424BFFA0UL))
+#define bFM3_SBSSR_BTSSSR_SSR9                 *((volatile unsigned int*)(0x424BFFA4UL))
+#define bFM3_SBSSR_BTSSSR_SSR10                *((volatile unsigned int*)(0x424BFFA8UL))
+#define bFM3_SBSSR_BTSSSR_SSR11                *((volatile unsigned int*)(0x424BFFACUL))
+#define bFM3_SBSSR_BTSSSR_SSR12                *((volatile unsigned int*)(0x424BFFB0UL))
+#define bFM3_SBSSR_BTSSSR_SSR13                *((volatile unsigned int*)(0x424BFFB4UL))
+#define bFM3_SBSSR_BTSSSR_SSR14                *((volatile unsigned int*)(0x424BFFB8UL))
+#define bFM3_SBSSR_BTSSSR_SSR15                *((volatile unsigned int*)(0x424BFFBCUL))
+
+/* Quad position and revolution counter channel 0 registers */
+#define bFM3_QPRC0_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICR_UFDF                   *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICR_OFDF                   *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICR_ZIIF                   *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICR_CDCIE                  *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICR_CDCF                   *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICR_DIRPC                  *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICR_DIROU                  *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICRH_CDCF                  *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICRH_DIROU                 *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QCR_PCM0                    *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCR_PCM1                    *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCR_RCM0                    *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCR_RCM1                    *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCR_PSTP                    *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCR_CGSC                    *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCR_RSEL                    *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCR_SWAP                    *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCR_AES0                    *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCR_AES1                    *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCR_BES0                    *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCR_BES1                    *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCR_CGE0                    *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCR_CGE1                    *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCRL_RCM1                   *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCRL_SWAP                   *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCRH_AES0                   *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCRH_AES1                   *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCRH_BES0                   *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCRH_BES1                   *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCRH_CGE1                   *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0380UL))
+#define bFM3_QPRC0_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0384UL))
+#define bFM3_QPRC0_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0388UL))
+
+/* Quad position and revolution counter channel 1 registers */
+#define bFM3_QPRC1_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICR_UFDF                   *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICR_OFDF                   *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICR_ZIIF                   *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICR_CDCIE                  *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICR_CDCF                   *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICR_DIRPC                  *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICR_DIROU                  *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICRH_CDCF                  *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICRH_DIROU                 *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QCR_PCM0                    *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCR_PCM1                    *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCR_RCM0                    *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCR_RCM1                    *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCR_PSTP                    *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCR_CGSC                    *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCR_RSEL                    *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCR_SWAP                    *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCR_AES0                    *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCR_AES1                    *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCR_BES0                    *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCR_BES1                    *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCR_CGE0                    *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCR_CGE1                    *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCRL_RCM1                   *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCRL_SWAP                   *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCRH_AES0                   *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCRH_AES1                   *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCRH_BES0                   *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCRH_BES1                   *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCRH_CGE1                   *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0B80UL))
+#define bFM3_QPRC1_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0B84UL))
+#define bFM3_QPRC1_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0B88UL))
+
+/* Quad position and revolution counter channel 2 registers */
+#define bFM3_QPRC2_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICR_QPCMF                  *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICR_OUZIE                  *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICR_UFDF                   *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICR_OFDF                   *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICR_ZIIF                   *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICR_CDCIE                  *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICR_CDCF                   *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICR_DIRPC                  *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICR_DIROU                  *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICRL_UFDF                  *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICRL_OFDF                  *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICRH_CDCF                  *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICRH_DIROU                 *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QCR_PCM0                    *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCR_PCM1                    *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCR_RCM0                    *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCR_RCM1                    *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCR_PSTP                    *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCR_CGSC                    *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCR_RSEL                    *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCR_SWAP                    *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCR_PCRM0                   *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCR_PCRM1                   *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCR_AES0                    *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCR_AES1                    *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCR_BES0                    *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCR_BES1                    *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCR_CGE0                    *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCR_CGE1                    *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QCRL_PCM0                   *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCRL_PCM1                   *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCRL_RCM0                   *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCRL_RCM1                   *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCRL_PSTP                   *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCRL_CGSC                   *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCRL_RSEL                   *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCRL_SWAP                   *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCRH_AES0                   *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCRH_AES1                   *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCRH_BES0                   *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCRH_BES1                   *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCRH_CGE0                   *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCRH_CGE1                   *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C1380UL))
+#define bFM3_QPRC2_QECR_ORNGF                  *((volatile unsigned int*)(0x424C1384UL))
+#define bFM3_QPRC2_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C1388UL))
+
+/* 12-bit ADC unit 0 registers */
+#define bFM3_ADC0_ADSR_SCS                     *((volatile unsigned int*)(0x424E0000UL))
+#define bFM3_ADC0_ADSR_PCS                     *((volatile unsigned int*)(0x424E0004UL))
+#define bFM3_ADC0_ADSR_PCNS                    *((volatile unsigned int*)(0x424E0008UL))
+#define bFM3_ADC0_ADSR_FDAS                    *((volatile unsigned int*)(0x424E0018UL))
+#define bFM3_ADC0_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E001CUL))
+#define bFM3_ADC0_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E0020UL))
+#define bFM3_ADC0_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E0024UL))
+#define bFM3_ADC0_ADCR_PCIE                    *((volatile unsigned int*)(0x424E0028UL))
+#define bFM3_ADC0_ADCR_SCIE                    *((volatile unsigned int*)(0x424E002CUL))
+#define bFM3_ADC0_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E0034UL))
+#define bFM3_ADC0_ADCR_PCIF                    *((volatile unsigned int*)(0x424E0038UL))
+#define bFM3_ADC0_ADCR_SCIF                    *((volatile unsigned int*)(0x424E003CUL))
+#define bFM3_ADC0_SFNS_SFS0                    *((volatile unsigned int*)(0x424E0100UL))
+#define bFM3_ADC0_SFNS_SFS1                    *((volatile unsigned int*)(0x424E0104UL))
+#define bFM3_ADC0_SFNS_SFS2                    *((volatile unsigned int*)(0x424E0108UL))
+#define bFM3_ADC0_SFNS_SFS3                    *((volatile unsigned int*)(0x424E010CUL))
+#define bFM3_ADC0_SCCR_SSTR                    *((volatile unsigned int*)(0x424E0120UL))
+#define bFM3_ADC0_SCCR_SHEN                    *((volatile unsigned int*)(0x424E0124UL))
+#define bFM3_ADC0_SCCR_RPT                     *((volatile unsigned int*)(0x424E0128UL))
+#define bFM3_ADC0_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E0130UL))
+#define bFM3_ADC0_SCCR_SOVR                    *((volatile unsigned int*)(0x424E0134UL))
+#define bFM3_ADC0_SCCR_SFUL                    *((volatile unsigned int*)(0x424E0138UL))
+#define bFM3_ADC0_SCCR_SEMP                    *((volatile unsigned int*)(0x424E013CUL))
+#define bFM3_ADC0_SCFD_SC0                     *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFD_SC1                     *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFD_SC2                     *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFD_SC3                     *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFD_SC4                     *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFD_RS0                     *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFD_RS1                     *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFD_INVL                    *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFD_SD0                     *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFD_SD1                     *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFD_SD2                     *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFD_SD3                     *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFD_SD4                     *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFD_SD5                     *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFD_SD6                     *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFD_SD7                     *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFD_SD8                     *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFD_SD9                     *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFD_SD10                    *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFD_SD11                    *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCFDL_SC0                    *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFDL_SC1                    *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFDL_SC2                    *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFDL_SC3                    *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFDL_SC4                    *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFDL_RS0                    *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFDL_RS1                    *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFDL_INVL                   *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFDH_SD0                    *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFDH_SD1                    *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFDH_SD2                    *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFDH_SD3                    *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFDH_SD4                    *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFDH_SD5                    *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFDH_SD6                    *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFDH_SD7                    *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFDH_SD8                    *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFDH_SD9                    *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFDH_SD10                   *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFDH_SD11                   *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCIS23_AN16                  *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS23_AN17                  *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS23_AN18                  *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS23_AN19                  *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS23_AN20                  *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS23_AN21                  *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS23_AN22                  *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS23_AN23                  *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS23_AN24                  *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS23_AN25                  *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS23_AN26                  *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS23_AN27                  *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS23_AN28                  *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS23_AN29                  *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS23_AN30                  *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS23_AN31                  *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS2_AN16                   *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS2_AN17                   *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS2_AN18                   *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS2_AN19                   *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS2_AN20                   *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS2_AN21                   *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS2_AN22                   *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS2_AN23                   *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS3_AN24                   *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS3_AN25                   *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS3_AN26                   *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS3_AN27                   *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS3_AN28                   *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS3_AN29                   *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS3_AN30                   *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS3_AN31                   *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS01_AN0                   *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS01_AN1                   *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS01_AN2                   *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS01_AN3                   *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS01_AN4                   *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS01_AN5                   *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS01_AN6                   *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS01_AN7                   *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS01_AN8                   *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS01_AN9                   *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS01_AN10                  *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS01_AN11                  *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS01_AN12                  *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS01_AN13                  *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS01_AN14                  *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS01_AN15                  *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_SCIS0_AN0                    *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS0_AN1                    *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS0_AN2                    *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS0_AN3                    *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS0_AN4                    *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS0_AN5                    *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS0_AN6                    *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS0_AN7                    *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS1_AN8                    *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS1_AN9                    *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS1_AN10                   *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS1_AN11                   *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS1_AN12                   *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS1_AN13                   *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS1_AN14                   *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS1_AN15                   *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_PFNS_PFS0                    *((volatile unsigned int*)(0x424E0300UL))
+#define bFM3_ADC0_PFNS_PFS1                    *((volatile unsigned int*)(0x424E0304UL))
+#define bFM3_ADC0_PFNS_TEST0                   *((volatile unsigned int*)(0x424E0310UL))
+#define bFM3_ADC0_PFNS_TEST1                   *((volatile unsigned int*)(0x424E0314UL))
+#define bFM3_ADC0_PCCR_PSTR                    *((volatile unsigned int*)(0x424E0320UL))
+#define bFM3_ADC0_PCCR_PHEN                    *((volatile unsigned int*)(0x424E0324UL))
+#define bFM3_ADC0_PCCR_PEEN                    *((volatile unsigned int*)(0x424E0328UL))
+#define bFM3_ADC0_PCCR_ESCE                    *((volatile unsigned int*)(0x424E032CUL))
+#define bFM3_ADC0_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E0330UL))
+#define bFM3_ADC0_PCCR_POVR                    *((volatile unsigned int*)(0x424E0334UL))
+#define bFM3_ADC0_PCCR_PFUL                    *((volatile unsigned int*)(0x424E0338UL))
+#define bFM3_ADC0_PCCR_PEMP                    *((volatile unsigned int*)(0x424E033CUL))
+#define bFM3_ADC0_PCFD_PC0                     *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFD_PC1                     *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFD_PC2                     *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFD_PC3                     *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFD_PC4                     *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFD_RS0                     *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFD_RS1                     *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFD_RS2                     *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFD_INVL                    *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFD_PD0                     *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFD_PD1                     *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFD_PD2                     *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFD_PD3                     *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFD_PD4                     *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFD_PD5                     *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFD_PD6                     *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFD_PD7                     *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFD_PD8                     *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFD_PD9                     *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFD_PD10                    *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFD_PD11                    *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCFDL_PC0                    *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFDL_PC1                    *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFDL_PC2                    *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFDL_PC3                    *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFDL_PC4                    *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFDL_RS0                    *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFDL_RS1                    *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFDL_RS2                    *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFDL_INVL                   *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFDH_PD0                    *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFDH_PD1                    *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFDH_PD2                    *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFDH_PD3                    *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFDH_PD4                    *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFDH_PD5                    *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFDH_PD6                    *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFDH_PD7                    *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFDH_PD8                    *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFDH_PD9                    *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFDH_PD10                   *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFDH_PD11                   *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCIS_P1A0                    *((volatile unsigned int*)(0x424E0400UL))
+#define bFM3_ADC0_PCIS_P1A1                    *((volatile unsigned int*)(0x424E0404UL))
+#define bFM3_ADC0_PCIS_P1A2                    *((volatile unsigned int*)(0x424E0408UL))
+#define bFM3_ADC0_PCIS_P2A0                    *((volatile unsigned int*)(0x424E040CUL))
+#define bFM3_ADC0_PCIS_P2A1                    *((volatile unsigned int*)(0x424E0410UL))
+#define bFM3_ADC0_PCIS_P2A2                    *((volatile unsigned int*)(0x424E0414UL))
+#define bFM3_ADC0_PCIS_P2A3                    *((volatile unsigned int*)(0x424E0418UL))
+#define bFM3_ADC0_PCIS_P2A4                    *((volatile unsigned int*)(0x424E041CUL))
+#define bFM3_ADC0_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E0480UL))
+#define bFM3_ADC0_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E0484UL))
+#define bFM3_ADC0_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E0488UL))
+#define bFM3_ADC0_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E048CUL))
+#define bFM3_ADC0_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E0490UL))
+#define bFM3_ADC0_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E0494UL))
+#define bFM3_ADC0_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E0498UL))
+#define bFM3_ADC0_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E049CUL))
+#define bFM3_ADC0_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E04D8UL))
+#define bFM3_ADC0_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E04DCUL))
+#define bFM3_ADC0_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E04E0UL))
+#define bFM3_ADC0_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E04E4UL))
+#define bFM3_ADC0_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E04E8UL))
+#define bFM3_ADC0_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E04ECUL))
+#define bFM3_ADC0_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E04F0UL))
+#define bFM3_ADC0_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E04F4UL))
+#define bFM3_ADC0_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E04F8UL))
+#define bFM3_ADC0_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E04FCUL))
+#define bFM3_ADC0_ADSS23_TS16                  *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS23_TS17                  *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS23_TS18                  *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS23_TS19                  *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS23_TS20                  *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS23_TS21                  *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS23_TS22                  *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS23_TS23                  *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS23_TS24                  *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS23_TS25                  *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS23_TS26                  *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS23_TS27                  *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS23_TS28                  *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS23_TS29                  *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS23_TS30                  *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS23_TS31                  *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS2_TS16                   *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS2_TS17                   *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS2_TS18                   *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS2_TS19                   *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS2_TS20                   *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS2_TS21                   *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS2_TS22                   *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS2_TS23                   *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS3_TS24                   *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS3_TS25                   *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS3_TS26                   *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS3_TS27                   *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS3_TS28                   *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS3_TS29                   *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS3_TS30                   *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS3_TS31                   *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS01_TS0                   *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS01_TS1                   *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS01_TS2                   *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS01_TS3                   *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS01_TS4                   *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS01_TS5                   *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS01_TS6                   *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS01_TS7                   *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS01_TS8                   *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS01_TS9                   *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS01_TS10                  *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS01_TS11                  *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS01_TS12                  *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS01_TS13                  *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS01_TS14                  *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS01_TS15                  *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADSS0_TS0                    *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS0_TS1                    *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS0_TS2                    *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS0_TS3                    *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS0_TS4                    *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS0_TS5                    *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS0_TS6                    *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS0_TS7                    *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS1_TS8                    *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS1_TS9                    *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS1_TS10                   *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS1_TS11                   *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS1_TS12                   *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS1_TS13                   *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS1_TS14                   *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS1_TS15                   *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADST01_ST10                  *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST01_ST11                  *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST01_ST12                  *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST01_ST13                  *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST01_ST14                  *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST01_STX10                 *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST01_STX11                 *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST01_STX12                 *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST01_ST00                  *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST01_ST01                  *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST01_ST02                  *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST01_ST03                  *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST01_ST04                  *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST01_STX00                 *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST01_STX01                 *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST01_STX02                 *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADST1_ST10                   *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST1_ST11                   *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST1_ST12                   *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST1_ST13                   *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST1_ST14                   *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST1_STX10                  *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST1_STX11                  *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST1_STX12                  *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST0_ST00                   *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST0_ST01                   *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST0_ST02                   *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST0_ST03                   *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST0_ST04                   *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST0_STX00                  *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST0_STX01                  *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST0_STX02                  *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADCT_CT0                     *((volatile unsigned int*)(0x424E0680UL))
+#define bFM3_ADC0_ADCT_CT1                     *((volatile unsigned int*)(0x424E0684UL))
+#define bFM3_ADC0_ADCT_CT2                     *((volatile unsigned int*)(0x424E0688UL))
+#define bFM3_ADC0_ADCT_CT3                     *((volatile unsigned int*)(0x424E068CUL))
+#define bFM3_ADC0_ADCT_CT4                     *((volatile unsigned int*)(0x424E0690UL))
+#define bFM3_ADC0_ADCT_CT5                     *((volatile unsigned int*)(0x424E0694UL))
+#define bFM3_ADC0_ADCT_CT6                     *((volatile unsigned int*)(0x424E0698UL))
+#define bFM3_ADC0_ADCT_CT7                     *((volatile unsigned int*)(0x424E069CUL))
+#define bFM3_ADC0_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E0700UL))
+#define bFM3_ADC0_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E0704UL))
+#define bFM3_ADC0_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E0708UL))
+#define bFM3_ADC0_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E070CUL))
+#define bFM3_ADC0_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E0720UL))
+#define bFM3_ADC0_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E0724UL))
+#define bFM3_ADC0_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E0728UL))
+#define bFM3_ADC0_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E072CUL))
+#define bFM3_ADC0_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E0780UL))
+#define bFM3_ADC0_ADCEN_READY                  *((volatile unsigned int*)(0x424E0784UL))
+#define bFM3_ADC0_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E0790UL))
+#define bFM3_ADC0_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E0794UL))
+
+/* 12-bit ADC unit 1 registers */
+#define bFM3_ADC1_ADSR_SCS                     *((volatile unsigned int*)(0x424E2000UL))
+#define bFM3_ADC1_ADSR_PCS                     *((volatile unsigned int*)(0x424E2004UL))
+#define bFM3_ADC1_ADSR_PCNS                    *((volatile unsigned int*)(0x424E2008UL))
+#define bFM3_ADC1_ADSR_FDAS                    *((volatile unsigned int*)(0x424E2018UL))
+#define bFM3_ADC1_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E201CUL))
+#define bFM3_ADC1_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E2020UL))
+#define bFM3_ADC1_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E2024UL))
+#define bFM3_ADC1_ADCR_PCIE                    *((volatile unsigned int*)(0x424E2028UL))
+#define bFM3_ADC1_ADCR_SCIE                    *((volatile unsigned int*)(0x424E202CUL))
+#define bFM3_ADC1_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E2034UL))
+#define bFM3_ADC1_ADCR_PCIF                    *((volatile unsigned int*)(0x424E2038UL))
+#define bFM3_ADC1_ADCR_SCIF                    *((volatile unsigned int*)(0x424E203CUL))
+#define bFM3_ADC1_SFNS_SFS0                    *((volatile unsigned int*)(0x424E2100UL))
+#define bFM3_ADC1_SFNS_SFS1                    *((volatile unsigned int*)(0x424E2104UL))
+#define bFM3_ADC1_SFNS_SFS2                    *((volatile unsigned int*)(0x424E2108UL))
+#define bFM3_ADC1_SFNS_SFS3                    *((volatile unsigned int*)(0x424E210CUL))
+#define bFM3_ADC1_SCCR_SSTR                    *((volatile unsigned int*)(0x424E2120UL))
+#define bFM3_ADC1_SCCR_SHEN                    *((volatile unsigned int*)(0x424E2124UL))
+#define bFM3_ADC1_SCCR_RPT                     *((volatile unsigned int*)(0x424E2128UL))
+#define bFM3_ADC1_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E2130UL))
+#define bFM3_ADC1_SCCR_SOVR                    *((volatile unsigned int*)(0x424E2134UL))
+#define bFM3_ADC1_SCCR_SFUL                    *((volatile unsigned int*)(0x424E2138UL))
+#define bFM3_ADC1_SCCR_SEMP                    *((volatile unsigned int*)(0x424E213CUL))
+#define bFM3_ADC1_SCFD_SC0                     *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFD_SC1                     *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFD_SC2                     *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFD_SC3                     *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFD_SC4                     *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFD_RS0                     *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFD_RS1                     *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFD_INVL                    *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFD_SD0                     *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFD_SD1                     *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFD_SD2                     *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFD_SD3                     *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFD_SD4                     *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFD_SD5                     *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFD_SD6                     *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFD_SD7                     *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFD_SD8                     *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFD_SD9                     *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFD_SD10                    *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFD_SD11                    *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCFDL_SC0                    *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFDL_SC1                    *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFDL_SC2                    *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFDL_SC3                    *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFDL_SC4                    *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFDL_RS0                    *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFDL_RS1                    *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFDL_INVL                   *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFDH_SD0                    *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFDH_SD1                    *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFDH_SD2                    *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFDH_SD3                    *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFDH_SD4                    *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFDH_SD5                    *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFDH_SD6                    *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFDH_SD7                    *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFDH_SD8                    *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFDH_SD9                    *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFDH_SD10                   *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFDH_SD11                   *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCIS23_AN16                  *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS23_AN17                  *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS23_AN18                  *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS23_AN19                  *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS23_AN20                  *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS23_AN21                  *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS23_AN22                  *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS23_AN23                  *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS23_AN24                  *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS23_AN25                  *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS23_AN26                  *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS23_AN27                  *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS23_AN28                  *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS23_AN29                  *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS23_AN30                  *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS23_AN31                  *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS2_AN16                   *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS2_AN17                   *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS2_AN18                   *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS2_AN19                   *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS2_AN20                   *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS2_AN21                   *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS2_AN22                   *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS2_AN23                   *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS3_AN24                   *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS3_AN25                   *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS3_AN26                   *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS3_AN27                   *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS3_AN28                   *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS3_AN29                   *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS3_AN30                   *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS3_AN31                   *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS01_AN0                   *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS01_AN1                   *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS01_AN2                   *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS01_AN3                   *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS01_AN4                   *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS01_AN5                   *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS01_AN6                   *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS01_AN7                   *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS01_AN8                   *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS01_AN9                   *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS01_AN10                  *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS01_AN11                  *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS01_AN12                  *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS01_AN13                  *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS01_AN14                  *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS01_AN15                  *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_SCIS0_AN0                    *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS0_AN1                    *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS0_AN2                    *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS0_AN3                    *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS0_AN4                    *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS0_AN5                    *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS0_AN6                    *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS0_AN7                    *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS1_AN8                    *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS1_AN9                    *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS1_AN10                   *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS1_AN11                   *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS1_AN12                   *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS1_AN13                   *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS1_AN14                   *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS1_AN15                   *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_PFNS_PFS0                    *((volatile unsigned int*)(0x424E2300UL))
+#define bFM3_ADC1_PFNS_PFS1                    *((volatile unsigned int*)(0x424E2304UL))
+#define bFM3_ADC1_PFNS_TEST0                   *((volatile unsigned int*)(0x424E2310UL))
+#define bFM3_ADC1_PFNS_TEST1                   *((volatile unsigned int*)(0x424E2314UL))
+#define bFM3_ADC1_PCCR_PSTR                    *((volatile unsigned int*)(0x424E2320UL))
+#define bFM3_ADC1_PCCR_PHEN                    *((volatile unsigned int*)(0x424E2324UL))
+#define bFM3_ADC1_PCCR_PEEN                    *((volatile unsigned int*)(0x424E2328UL))
+#define bFM3_ADC1_PCCR_ESCE                    *((volatile unsigned int*)(0x424E232CUL))
+#define bFM3_ADC1_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E2330UL))
+#define bFM3_ADC1_PCCR_POVR                    *((volatile unsigned int*)(0x424E2334UL))
+#define bFM3_ADC1_PCCR_PFUL                    *((volatile unsigned int*)(0x424E2338UL))
+#define bFM3_ADC1_PCCR_PEMP                    *((volatile unsigned int*)(0x424E233CUL))
+#define bFM3_ADC1_PCFD_PC0                     *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFD_PC1                     *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFD_PC2                     *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFD_PC3                     *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFD_PC4                     *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFD_RS0                     *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFD_RS1                     *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFD_RS2                     *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFD_INVL                    *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFD_PD0                     *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFD_PD1                     *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFD_PD2                     *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFD_PD3                     *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFD_PD4                     *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFD_PD5                     *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFD_PD6                     *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFD_PD7                     *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFD_PD8                     *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFD_PD9                     *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFD_PD10                    *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFD_PD11                    *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCFDL_PC0                    *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFDL_PC1                    *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFDL_PC2                    *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFDL_PC3                    *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFDL_PC4                    *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFDL_RS0                    *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFDL_RS1                    *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFDL_RS2                    *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFDL_INVL                   *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFDH_PD0                    *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFDH_PD1                    *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFDH_PD2                    *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFDH_PD3                    *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFDH_PD4                    *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFDH_PD5                    *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFDH_PD6                    *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFDH_PD7                    *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFDH_PD8                    *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFDH_PD9                    *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFDH_PD10                   *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFDH_PD11                   *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCIS_P1A0                    *((volatile unsigned int*)(0x424E2400UL))
+#define bFM3_ADC1_PCIS_P1A1                    *((volatile unsigned int*)(0x424E2404UL))
+#define bFM3_ADC1_PCIS_P1A2                    *((volatile unsigned int*)(0x424E2408UL))
+#define bFM3_ADC1_PCIS_P2A0                    *((volatile unsigned int*)(0x424E240CUL))
+#define bFM3_ADC1_PCIS_P2A1                    *((volatile unsigned int*)(0x424E2410UL))
+#define bFM3_ADC1_PCIS_P2A2                    *((volatile unsigned int*)(0x424E2414UL))
+#define bFM3_ADC1_PCIS_P2A3                    *((volatile unsigned int*)(0x424E2418UL))
+#define bFM3_ADC1_PCIS_P2A4                    *((volatile unsigned int*)(0x424E241CUL))
+#define bFM3_ADC1_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E2480UL))
+#define bFM3_ADC1_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E2484UL))
+#define bFM3_ADC1_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E2488UL))
+#define bFM3_ADC1_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E248CUL))
+#define bFM3_ADC1_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E2490UL))
+#define bFM3_ADC1_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E2494UL))
+#define bFM3_ADC1_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E2498UL))
+#define bFM3_ADC1_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E249CUL))
+#define bFM3_ADC1_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E24D8UL))
+#define bFM3_ADC1_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E24DCUL))
+#define bFM3_ADC1_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E24E0UL))
+#define bFM3_ADC1_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E24E4UL))
+#define bFM3_ADC1_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E24E8UL))
+#define bFM3_ADC1_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E24ECUL))
+#define bFM3_ADC1_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E24F0UL))
+#define bFM3_ADC1_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E24F4UL))
+#define bFM3_ADC1_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E24F8UL))
+#define bFM3_ADC1_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E24FCUL))
+#define bFM3_ADC1_ADSS23_TS16                  *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS23_TS17                  *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS23_TS18                  *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS23_TS19                  *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS23_TS20                  *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS23_TS21                  *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS23_TS22                  *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS23_TS23                  *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS23_TS24                  *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS23_TS25                  *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS23_TS26                  *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS23_TS27                  *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS23_TS28                  *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS23_TS29                  *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS23_TS30                  *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS23_TS31                  *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS2_TS16                   *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS2_TS17                   *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS2_TS18                   *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS2_TS19                   *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS2_TS20                   *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS2_TS21                   *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS2_TS22                   *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS2_TS23                   *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS3_TS24                   *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS3_TS25                   *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS3_TS26                   *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS3_TS27                   *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS3_TS28                   *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS3_TS29                   *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS3_TS30                   *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS3_TS31                   *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS01_TS0                   *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS01_TS1                   *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS01_TS2                   *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS01_TS3                   *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS01_TS4                   *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS01_TS5                   *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS01_TS6                   *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS01_TS7                   *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS01_TS8                   *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS01_TS9                   *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS01_TS10                  *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS01_TS11                  *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS01_TS12                  *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS01_TS13                  *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS01_TS14                  *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS01_TS15                  *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADSS0_TS0                    *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS0_TS1                    *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS0_TS2                    *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS0_TS3                    *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS0_TS4                    *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS0_TS5                    *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS0_TS6                    *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS0_TS7                    *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS1_TS8                    *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS1_TS9                    *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS1_TS10                   *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS1_TS11                   *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS1_TS12                   *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS1_TS13                   *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS1_TS14                   *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS1_TS15                   *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADST01_ST10                  *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST01_ST11                  *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST01_ST12                  *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST01_ST13                  *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST01_ST14                  *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST01_STX10                 *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST01_STX11                 *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST01_STX12                 *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST01_ST00                  *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST01_ST01                  *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST01_ST02                  *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST01_ST03                  *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST01_ST04                  *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST01_STX00                 *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST01_STX01                 *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST01_STX02                 *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADST1_ST10                   *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST1_ST11                   *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST1_ST12                   *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST1_ST13                   *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST1_ST14                   *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST1_STX10                  *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST1_STX11                  *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST1_STX12                  *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST0_ST00                   *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST0_ST01                   *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST0_ST02                   *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST0_ST03                   *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST0_ST04                   *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST0_STX00                  *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST0_STX01                  *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST0_STX02                  *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADCT_CT0                     *((volatile unsigned int*)(0x424E2680UL))
+#define bFM3_ADC1_ADCT_CT1                     *((volatile unsigned int*)(0x424E2684UL))
+#define bFM3_ADC1_ADCT_CT2                     *((volatile unsigned int*)(0x424E2688UL))
+#define bFM3_ADC1_ADCT_CT3                     *((volatile unsigned int*)(0x424E268CUL))
+#define bFM3_ADC1_ADCT_CT4                     *((volatile unsigned int*)(0x424E2690UL))
+#define bFM3_ADC1_ADCT_CT5                     *((volatile unsigned int*)(0x424E2694UL))
+#define bFM3_ADC1_ADCT_CT6                     *((volatile unsigned int*)(0x424E2698UL))
+#define bFM3_ADC1_ADCT_CT7                     *((volatile unsigned int*)(0x424E269CUL))
+#define bFM3_ADC1_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E2700UL))
+#define bFM3_ADC1_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E2704UL))
+#define bFM3_ADC1_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E2708UL))
+#define bFM3_ADC1_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E270CUL))
+#define bFM3_ADC1_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E2720UL))
+#define bFM3_ADC1_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E2724UL))
+#define bFM3_ADC1_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E2728UL))
+#define bFM3_ADC1_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E272CUL))
+#define bFM3_ADC1_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E2780UL))
+#define bFM3_ADC1_ADCEN_READY                  *((volatile unsigned int*)(0x424E2784UL))
+#define bFM3_ADC1_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E2790UL))
+#define bFM3_ADC1_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E2794UL))
+
+/* 12-bit ADC unit 2 registers */
+#define bFM3_ADC2_ADSR_SCS                     *((volatile unsigned int*)(0x424E4000UL))
+#define bFM3_ADC2_ADSR_PCS                     *((volatile unsigned int*)(0x424E4004UL))
+#define bFM3_ADC2_ADSR_PCNS                    *((volatile unsigned int*)(0x424E4008UL))
+#define bFM3_ADC2_ADSR_FDAS                    *((volatile unsigned int*)(0x424E4018UL))
+#define bFM3_ADC2_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E401CUL))
+#define bFM3_ADC2_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E4020UL))
+#define bFM3_ADC2_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E4024UL))
+#define bFM3_ADC2_ADCR_PCIE                    *((volatile unsigned int*)(0x424E4028UL))
+#define bFM3_ADC2_ADCR_SCIE                    *((volatile unsigned int*)(0x424E402CUL))
+#define bFM3_ADC2_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E4034UL))
+#define bFM3_ADC2_ADCR_PCIF                    *((volatile unsigned int*)(0x424E4038UL))
+#define bFM3_ADC2_ADCR_SCIF                    *((volatile unsigned int*)(0x424E403CUL))
+#define bFM3_ADC2_SFNS_SFS0                    *((volatile unsigned int*)(0x424E4100UL))
+#define bFM3_ADC2_SFNS_SFS1                    *((volatile unsigned int*)(0x424E4104UL))
+#define bFM3_ADC2_SFNS_SFS2                    *((volatile unsigned int*)(0x424E4108UL))
+#define bFM3_ADC2_SFNS_SFS3                    *((volatile unsigned int*)(0x424E410CUL))
+#define bFM3_ADC2_SCCR_SSTR                    *((volatile unsigned int*)(0x424E4120UL))
+#define bFM3_ADC2_SCCR_SHEN                    *((volatile unsigned int*)(0x424E4124UL))
+#define bFM3_ADC2_SCCR_RPT                     *((volatile unsigned int*)(0x424E4128UL))
+#define bFM3_ADC2_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E4130UL))
+#define bFM3_ADC2_SCCR_SOVR                    *((volatile unsigned int*)(0x424E4134UL))
+#define bFM3_ADC2_SCCR_SFUL                    *((volatile unsigned int*)(0x424E4138UL))
+#define bFM3_ADC2_SCCR_SEMP                    *((volatile unsigned int*)(0x424E413CUL))
+#define bFM3_ADC2_SCFD_SC0                     *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFD_SC1                     *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFD_SC2                     *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFD_SC3                     *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFD_SC4                     *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFD_RS0                     *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFD_RS1                     *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFD_INVL                    *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFD_SD0                     *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFD_SD1                     *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFD_SD2                     *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFD_SD3                     *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFD_SD4                     *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFD_SD5                     *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFD_SD6                     *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFD_SD7                     *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFD_SD8                     *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFD_SD9                     *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFD_SD10                    *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFD_SD11                    *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCFDL_SC0                    *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFDL_SC1                    *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFDL_SC2                    *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFDL_SC3                    *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFDL_SC4                    *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFDL_RS0                    *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFDL_RS1                    *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFDL_INVL                   *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFDH_SD0                    *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFDH_SD1                    *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFDH_SD2                    *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFDH_SD3                    *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFDH_SD4                    *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFDH_SD5                    *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFDH_SD6                    *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFDH_SD7                    *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFDH_SD8                    *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFDH_SD9                    *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFDH_SD10                   *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFDH_SD11                   *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCIS23_AN16                  *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS23_AN17                  *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS23_AN18                  *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS23_AN19                  *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS23_AN20                  *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS23_AN21                  *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS23_AN22                  *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS23_AN23                  *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS23_AN24                  *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS23_AN25                  *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS23_AN26                  *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS23_AN27                  *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS23_AN28                  *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS23_AN29                  *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS23_AN30                  *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS23_AN31                  *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS2_AN16                   *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS2_AN17                   *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS2_AN18                   *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS2_AN19                   *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS2_AN20                   *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS2_AN21                   *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS2_AN22                   *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS2_AN23                   *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS3_AN24                   *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS3_AN25                   *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS3_AN26                   *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS3_AN27                   *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS3_AN28                   *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS3_AN29                   *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS3_AN30                   *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS3_AN31                   *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS01_AN0                   *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS01_AN1                   *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS01_AN2                   *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS01_AN3                   *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS01_AN4                   *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS01_AN5                   *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS01_AN6                   *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS01_AN7                   *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS01_AN8                   *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS01_AN9                   *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS01_AN10                  *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS01_AN11                  *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS01_AN12                  *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS01_AN13                  *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS01_AN14                  *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS01_AN15                  *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_SCIS0_AN0                    *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS0_AN1                    *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS0_AN2                    *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS0_AN3                    *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS0_AN4                    *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS0_AN5                    *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS0_AN6                    *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS0_AN7                    *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS1_AN8                    *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS1_AN9                    *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS1_AN10                   *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS1_AN11                   *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS1_AN12                   *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS1_AN13                   *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS1_AN14                   *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS1_AN15                   *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_PFNS_PFS0                    *((volatile unsigned int*)(0x424E4300UL))
+#define bFM3_ADC2_PFNS_PFS1                    *((volatile unsigned int*)(0x424E4304UL))
+#define bFM3_ADC2_PFNS_TEST0                   *((volatile unsigned int*)(0x424E4310UL))
+#define bFM3_ADC2_PFNS_TEST1                   *((volatile unsigned int*)(0x424E4314UL))
+#define bFM3_ADC2_PCCR_PSTR                    *((volatile unsigned int*)(0x424E4320UL))
+#define bFM3_ADC2_PCCR_PHEN                    *((volatile unsigned int*)(0x424E4324UL))
+#define bFM3_ADC2_PCCR_PEEN                    *((volatile unsigned int*)(0x424E4328UL))
+#define bFM3_ADC2_PCCR_ESCE                    *((volatile unsigned int*)(0x424E432CUL))
+#define bFM3_ADC2_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E4330UL))
+#define bFM3_ADC2_PCCR_POVR                    *((volatile unsigned int*)(0x424E4334UL))
+#define bFM3_ADC2_PCCR_PFUL                    *((volatile unsigned int*)(0x424E4338UL))
+#define bFM3_ADC2_PCCR_PEMP                    *((volatile unsigned int*)(0x424E433CUL))
+#define bFM3_ADC2_PCFD_PC0                     *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFD_PC1                     *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFD_PC2                     *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFD_PC3                     *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFD_PC4                     *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFD_RS0                     *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFD_RS1                     *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFD_RS2                     *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFD_INVL                    *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFD_PD0                     *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFD_PD1                     *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFD_PD2                     *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFD_PD3                     *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFD_PD4                     *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFD_PD5                     *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFD_PD6                     *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFD_PD7                     *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFD_PD8                     *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFD_PD9                     *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFD_PD10                    *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFD_PD11                    *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCFDL_PC0                    *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFDL_PC1                    *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFDL_PC2                    *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFDL_PC3                    *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFDL_PC4                    *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFDL_RS0                    *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFDL_RS1                    *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFDL_RS2                    *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFDL_INVL                   *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFDH_PD0                    *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFDH_PD1                    *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFDH_PD2                    *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFDH_PD3                    *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFDH_PD4                    *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFDH_PD5                    *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFDH_PD6                    *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFDH_PD7                    *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFDH_PD8                    *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFDH_PD9                    *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFDH_PD10                   *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFDH_PD11                   *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCIS_P1A0                    *((volatile unsigned int*)(0x424E4400UL))
+#define bFM3_ADC2_PCIS_P1A1                    *((volatile unsigned int*)(0x424E4404UL))
+#define bFM3_ADC2_PCIS_P1A2                    *((volatile unsigned int*)(0x424E4408UL))
+#define bFM3_ADC2_PCIS_P2A0                    *((volatile unsigned int*)(0x424E440CUL))
+#define bFM3_ADC2_PCIS_P2A1                    *((volatile unsigned int*)(0x424E4410UL))
+#define bFM3_ADC2_PCIS_P2A2                    *((volatile unsigned int*)(0x424E4414UL))
+#define bFM3_ADC2_PCIS_P2A3                    *((volatile unsigned int*)(0x424E4418UL))
+#define bFM3_ADC2_PCIS_P2A4                    *((volatile unsigned int*)(0x424E441CUL))
+#define bFM3_ADC2_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E4480UL))
+#define bFM3_ADC2_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E4484UL))
+#define bFM3_ADC2_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E4488UL))
+#define bFM3_ADC2_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E448CUL))
+#define bFM3_ADC2_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E4490UL))
+#define bFM3_ADC2_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E4494UL))
+#define bFM3_ADC2_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E4498UL))
+#define bFM3_ADC2_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E449CUL))
+#define bFM3_ADC2_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E44D8UL))
+#define bFM3_ADC2_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E44DCUL))
+#define bFM3_ADC2_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E44E0UL))
+#define bFM3_ADC2_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E44E4UL))
+#define bFM3_ADC2_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E44E8UL))
+#define bFM3_ADC2_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E44ECUL))
+#define bFM3_ADC2_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E44F0UL))
+#define bFM3_ADC2_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E44F4UL))
+#define bFM3_ADC2_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E44F8UL))
+#define bFM3_ADC2_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E44FCUL))
+#define bFM3_ADC2_ADSS23_TS16                  *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS23_TS17                  *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS23_TS18                  *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS23_TS19                  *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS23_TS20                  *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS23_TS21                  *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS23_TS22                  *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS23_TS23                  *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS23_TS24                  *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS23_TS25                  *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS23_TS26                  *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS23_TS27                  *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS23_TS28                  *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS23_TS29                  *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS23_TS30                  *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS23_TS31                  *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS2_TS16                   *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS2_TS17                   *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS2_TS18                   *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS2_TS19                   *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS2_TS20                   *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS2_TS21                   *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS2_TS22                   *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS2_TS23                   *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS3_TS24                   *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS3_TS25                   *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS3_TS26                   *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS3_TS27                   *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS3_TS28                   *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS3_TS29                   *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS3_TS30                   *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS3_TS31                   *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS01_TS0                   *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS01_TS1                   *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS01_TS2                   *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS01_TS3                   *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS01_TS4                   *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS01_TS5                   *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS01_TS6                   *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS01_TS7                   *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS01_TS8                   *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS01_TS9                   *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS01_TS10                  *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS01_TS11                  *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS01_TS12                  *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS01_TS13                  *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS01_TS14                  *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS01_TS15                  *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADSS0_TS0                    *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS0_TS1                    *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS0_TS2                    *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS0_TS3                    *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS0_TS4                    *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS0_TS5                    *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS0_TS6                    *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS0_TS7                    *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS1_TS8                    *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS1_TS9                    *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS1_TS10                   *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS1_TS11                   *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS1_TS12                   *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS1_TS13                   *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS1_TS14                   *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS1_TS15                   *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADST01_ST10                  *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST01_ST11                  *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST01_ST12                  *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST01_ST13                  *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST01_ST14                  *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST01_STX10                 *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST01_STX11                 *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST01_STX12                 *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST01_ST00                  *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST01_ST01                  *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST01_ST02                  *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST01_ST03                  *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST01_ST04                  *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST01_STX00                 *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST01_STX01                 *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST01_STX02                 *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADST1_ST10                   *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST1_ST11                   *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST1_ST12                   *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST1_ST13                   *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST1_ST14                   *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST1_STX10                  *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST1_STX11                  *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST1_STX12                  *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST0_ST00                   *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST0_ST01                   *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST0_ST02                   *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST0_ST03                   *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST0_ST04                   *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST0_STX00                  *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST0_STX01                  *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST0_STX02                  *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADCT_CT0                     *((volatile unsigned int*)(0x424E4680UL))
+#define bFM3_ADC2_ADCT_CT1                     *((volatile unsigned int*)(0x424E4684UL))
+#define bFM3_ADC2_ADCT_CT2                     *((volatile unsigned int*)(0x424E4688UL))
+#define bFM3_ADC2_ADCT_CT3                     *((volatile unsigned int*)(0x424E468CUL))
+#define bFM3_ADC2_ADCT_CT4                     *((volatile unsigned int*)(0x424E4690UL))
+#define bFM3_ADC2_ADCT_CT5                     *((volatile unsigned int*)(0x424E4694UL))
+#define bFM3_ADC2_ADCT_CT6                     *((volatile unsigned int*)(0x424E4698UL))
+#define bFM3_ADC2_ADCT_CT7                     *((volatile unsigned int*)(0x424E469CUL))
+#define bFM3_ADC2_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E4700UL))
+#define bFM3_ADC2_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E4704UL))
+#define bFM3_ADC2_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E4708UL))
+#define bFM3_ADC2_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E470CUL))
+#define bFM3_ADC2_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E4720UL))
+#define bFM3_ADC2_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E4724UL))
+#define bFM3_ADC2_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E4728UL))
+#define bFM3_ADC2_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E472CUL))
+#define bFM3_ADC2_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E4780UL))
+#define bFM3_ADC2_ADCEN_READY                  *((volatile unsigned int*)(0x424E4784UL))
+#define bFM3_ADC2_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E4790UL))
+#define bFM3_ADC2_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E4794UL))
+
+/* CR trimming registers */
+#define bFM3_CRTRIM_MCR_PSR_CSR0               *((volatile unsigned int*)(0x425C0000UL))
+#define bFM3_CRTRIM_MCR_PSR_CSR1               *((volatile unsigned int*)(0x425C0004UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD0              *((volatile unsigned int*)(0x425C0080UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD1              *((volatile unsigned int*)(0x425C0084UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD2              *((volatile unsigned int*)(0x425C0088UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD3              *((volatile unsigned int*)(0x425C008CUL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD4              *((volatile unsigned int*)(0x425C0090UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD5              *((volatile unsigned int*)(0x425C0094UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD6              *((volatile unsigned int*)(0x425C0098UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD7              *((volatile unsigned int*)(0x425C009CUL))
+
+/* External interrupt registers */
+#define bFM3_EXTI_ENIR_EN0                     *((volatile unsigned int*)(0x42600000UL))
+#define bFM3_EXTI_ENIR_EN1                     *((volatile unsigned int*)(0x42600004UL))
+#define bFM3_EXTI_ENIR_EN2                     *((volatile unsigned int*)(0x42600008UL))
+#define bFM3_EXTI_ENIR_EN3                     *((volatile unsigned int*)(0x4260000CUL))
+#define bFM3_EXTI_ENIR_EN4                     *((volatile unsigned int*)(0x42600010UL))
+#define bFM3_EXTI_ENIR_EN5                     *((volatile unsigned int*)(0x42600014UL))
+#define bFM3_EXTI_ENIR_EN6                     *((volatile unsigned int*)(0x42600018UL))
+#define bFM3_EXTI_ENIR_EN7                     *((volatile unsigned int*)(0x4260001CUL))
+#define bFM3_EXTI_ENIR_EN8                     *((volatile unsigned int*)(0x42600020UL))
+#define bFM3_EXTI_ENIR_EN9                     *((volatile unsigned int*)(0x42600024UL))
+#define bFM3_EXTI_ENIR_EN10                    *((volatile unsigned int*)(0x42600028UL))
+#define bFM3_EXTI_ENIR_EN11                    *((volatile unsigned int*)(0x4260002CUL))
+#define bFM3_EXTI_ENIR_EN12                    *((volatile unsigned int*)(0x42600030UL))
+#define bFM3_EXTI_ENIR_EN13                    *((volatile unsigned int*)(0x42600034UL))
+#define bFM3_EXTI_ENIR_EN14                    *((volatile unsigned int*)(0x42600038UL))
+#define bFM3_EXTI_ENIR_EN15                    *((volatile unsigned int*)(0x4260003CUL))
+#define bFM3_EXTI_ENIR_EN16                    *((volatile unsigned int*)(0x42600040UL))
+#define bFM3_EXTI_ENIR_EN17                    *((volatile unsigned int*)(0x42600044UL))
+#define bFM3_EXTI_ENIR_EN18                    *((volatile unsigned int*)(0x42600048UL))
+#define bFM3_EXTI_ENIR_EN19                    *((volatile unsigned int*)(0x4260004CUL))
+#define bFM3_EXTI_ENIR_EN20                    *((volatile unsigned int*)(0x42600050UL))
+#define bFM3_EXTI_ENIR_EN21                    *((volatile unsigned int*)(0x42600054UL))
+#define bFM3_EXTI_ENIR_EN22                    *((volatile unsigned int*)(0x42600058UL))
+#define bFM3_EXTI_ENIR_EN23                    *((volatile unsigned int*)(0x4260005CUL))
+#define bFM3_EXTI_ENIR_EN24                    *((volatile unsigned int*)(0x42600060UL))
+#define bFM3_EXTI_ENIR_EN25                    *((volatile unsigned int*)(0x42600064UL))
+#define bFM3_EXTI_ENIR_EN26                    *((volatile unsigned int*)(0x42600068UL))
+#define bFM3_EXTI_ENIR_EN27                    *((volatile unsigned int*)(0x4260006CUL))
+#define bFM3_EXTI_ENIR_EN28                    *((volatile unsigned int*)(0x42600070UL))
+#define bFM3_EXTI_ENIR_EN29                    *((volatile unsigned int*)(0x42600074UL))
+#define bFM3_EXTI_ENIR_EN30                    *((volatile unsigned int*)(0x42600078UL))
+#define bFM3_EXTI_ENIR_EN31                    *((volatile unsigned int*)(0x4260007CUL))
+#define bFM3_EXTI_EIRR_ER0                     *((volatile unsigned int*)(0x42600080UL))
+#define bFM3_EXTI_EIRR_ER1                     *((volatile unsigned int*)(0x42600084UL))
+#define bFM3_EXTI_EIRR_ER2                     *((volatile unsigned int*)(0x42600088UL))
+#define bFM3_EXTI_EIRR_ER3                     *((volatile unsigned int*)(0x4260008CUL))
+#define bFM3_EXTI_EIRR_ER4                     *((volatile unsigned int*)(0x42600090UL))
+#define bFM3_EXTI_EIRR_ER5                     *((volatile unsigned int*)(0x42600094UL))
+#define bFM3_EXTI_EIRR_ER6                     *((volatile unsigned int*)(0x42600098UL))
+#define bFM3_EXTI_EIRR_ER7                     *((volatile unsigned int*)(0x4260009CUL))
+#define bFM3_EXTI_EIRR_ER8                     *((volatile unsigned int*)(0x426000A0UL))
+#define bFM3_EXTI_EIRR_ER9                     *((volatile unsigned int*)(0x426000A4UL))
+#define bFM3_EXTI_EIRR_ER10                    *((volatile unsigned int*)(0x426000A8UL))
+#define bFM3_EXTI_EIRR_ER11                    *((volatile unsigned int*)(0x426000ACUL))
+#define bFM3_EXTI_EIRR_ER12                    *((volatile unsigned int*)(0x426000B0UL))
+#define bFM3_EXTI_EIRR_ER13                    *((volatile unsigned int*)(0x426000B4UL))
+#define bFM3_EXTI_EIRR_ER14                    *((volatile unsigned int*)(0x426000B8UL))
+#define bFM3_EXTI_EIRR_ER15                    *((volatile unsigned int*)(0x426000BCUL))
+#define bFM3_EXTI_EIRR_ER16                    *((volatile unsigned int*)(0x426000C0UL))
+#define bFM3_EXTI_EIRR_ER17                    *((volatile unsigned int*)(0x426000C4UL))
+#define bFM3_EXTI_EIRR_ER18                    *((volatile unsigned int*)(0x426000C8UL))
+#define bFM3_EXTI_EIRR_ER19                    *((volatile unsigned int*)(0x426000CCUL))
+#define bFM3_EXTI_EIRR_ER20                    *((volatile unsigned int*)(0x426000D0UL))
+#define bFM3_EXTI_EIRR_ER21                    *((volatile unsigned int*)(0x426000D4UL))
+#define bFM3_EXTI_EIRR_ER22                    *((volatile unsigned int*)(0x426000D8UL))
+#define bFM3_EXTI_EIRR_ER23                    *((volatile unsigned int*)(0x426000DCUL))
+#define bFM3_EXTI_EIRR_ER24                    *((volatile unsigned int*)(0x426000E0UL))
+#define bFM3_EXTI_EIRR_ER25                    *((volatile unsigned int*)(0x426000E4UL))
+#define bFM3_EXTI_EIRR_ER26                    *((volatile unsigned int*)(0x426000E8UL))
+#define bFM3_EXTI_EIRR_ER27                    *((volatile unsigned int*)(0x426000ECUL))
+#define bFM3_EXTI_EIRR_ER28                    *((volatile unsigned int*)(0x426000F0UL))
+#define bFM3_EXTI_EIRR_ER29                    *((volatile unsigned int*)(0x426000F4UL))
+#define bFM3_EXTI_EIRR_ER30                    *((volatile unsigned int*)(0x426000F8UL))
+#define bFM3_EXTI_EIRR_ER31                    *((volatile unsigned int*)(0x426000FCUL))
+#define bFM3_EXTI_EICL_ECL0                    *((volatile unsigned int*)(0x42600100UL))
+#define bFM3_EXTI_EICL_ECL1                    *((volatile unsigned int*)(0x42600104UL))
+#define bFM3_EXTI_EICL_ECL2                    *((volatile unsigned int*)(0x42600108UL))
+#define bFM3_EXTI_EICL_ECL3                    *((volatile unsigned int*)(0x4260010CUL))
+#define bFM3_EXTI_EICL_ECL4                    *((volatile unsigned int*)(0x42600110UL))
+#define bFM3_EXTI_EICL_ECL5                    *((volatile unsigned int*)(0x42600114UL))
+#define bFM3_EXTI_EICL_ECL6                    *((volatile unsigned int*)(0x42600118UL))
+#define bFM3_EXTI_EICL_ECL7                    *((volatile unsigned int*)(0x4260011CUL))
+#define bFM3_EXTI_EICL_ECL8                    *((volatile unsigned int*)(0x42600120UL))
+#define bFM3_EXTI_EICL_ECL9                    *((volatile unsigned int*)(0x42600124UL))
+#define bFM3_EXTI_EICL_ECL10                   *((volatile unsigned int*)(0x42600128UL))
+#define bFM3_EXTI_EICL_ECL11                   *((volatile unsigned int*)(0x4260012CUL))
+#define bFM3_EXTI_EICL_ECL12                   *((volatile unsigned int*)(0x42600130UL))
+#define bFM3_EXTI_EICL_ECL13                   *((volatile unsigned int*)(0x42600134UL))
+#define bFM3_EXTI_EICL_ECL14                   *((volatile unsigned int*)(0x42600138UL))
+#define bFM3_EXTI_EICL_ECL15                   *((volatile unsigned int*)(0x4260013CUL))
+#define bFM3_EXTI_EICL_ECL16                   *((volatile unsigned int*)(0x42600140UL))
+#define bFM3_EXTI_EICL_ECL17                   *((volatile unsigned int*)(0x42600144UL))
+#define bFM3_EXTI_EICL_ECL18                   *((volatile unsigned int*)(0x42600148UL))
+#define bFM3_EXTI_EICL_ECL19                   *((volatile unsigned int*)(0x4260014CUL))
+#define bFM3_EXTI_EICL_ECL20                   *((volatile unsigned int*)(0x42600150UL))
+#define bFM3_EXTI_EICL_ECL21                   *((volatile unsigned int*)(0x42600154UL))
+#define bFM3_EXTI_EICL_ECL22                   *((volatile unsigned int*)(0x42600158UL))
+#define bFM3_EXTI_EICL_ECL23                   *((volatile unsigned int*)(0x4260015CUL))
+#define bFM3_EXTI_EICL_ECL24                   *((volatile unsigned int*)(0x42600160UL))
+#define bFM3_EXTI_EICL_ECL25                   *((volatile unsigned int*)(0x42600164UL))
+#define bFM3_EXTI_EICL_ECL26                   *((volatile unsigned int*)(0x42600168UL))
+#define bFM3_EXTI_EICL_ECL27                   *((volatile unsigned int*)(0x4260016CUL))
+#define bFM3_EXTI_EICL_ECL28                   *((volatile unsigned int*)(0x42600170UL))
+#define bFM3_EXTI_EICL_ECL29                   *((volatile unsigned int*)(0x42600174UL))
+#define bFM3_EXTI_EICL_ECL30                   *((volatile unsigned int*)(0x42600178UL))
+#define bFM3_EXTI_EICL_ECL31                   *((volatile unsigned int*)(0x4260017CUL))
+#define bFM3_EXTI_ELVR_LA0                     *((volatile unsigned int*)(0x42600180UL))
+#define bFM3_EXTI_ELVR_LB0                     *((volatile unsigned int*)(0x42600184UL))
+#define bFM3_EXTI_ELVR_LA1                     *((volatile unsigned int*)(0x42600188UL))
+#define bFM3_EXTI_ELVR_LB1                     *((volatile unsigned int*)(0x4260018CUL))
+#define bFM3_EXTI_ELVR_LA2                     *((volatile unsigned int*)(0x42600190UL))
+#define bFM3_EXTI_ELVR_LB2                     *((volatile unsigned int*)(0x42600194UL))
+#define bFM3_EXTI_ELVR_LA3                     *((volatile unsigned int*)(0x42600198UL))
+#define bFM3_EXTI_ELVR_LB3                     *((volatile unsigned int*)(0x4260019CUL))
+#define bFM3_EXTI_ELVR_LA4                     *((volatile unsigned int*)(0x426001A0UL))
+#define bFM3_EXTI_ELVR_LB4                     *((volatile unsigned int*)(0x426001A4UL))
+#define bFM3_EXTI_ELVR_LA5                     *((volatile unsigned int*)(0x426001A8UL))
+#define bFM3_EXTI_ELVR_LB5                     *((volatile unsigned int*)(0x426001ACUL))
+#define bFM3_EXTI_ELVR_LA6                     *((volatile unsigned int*)(0x426001B0UL))
+#define bFM3_EXTI_ELVR_LB6                     *((volatile unsigned int*)(0x426001B4UL))
+#define bFM3_EXTI_ELVR_LA7                     *((volatile unsigned int*)(0x426001B8UL))
+#define bFM3_EXTI_ELVR_LB7                     *((volatile unsigned int*)(0x426001BCUL))
+#define bFM3_EXTI_ELVR_LA8                     *((volatile unsigned int*)(0x426001C0UL))
+#define bFM3_EXTI_ELVR_LB8                     *((volatile unsigned int*)(0x426001C4UL))
+#define bFM3_EXTI_ELVR_LA9                     *((volatile unsigned int*)(0x426001C8UL))
+#define bFM3_EXTI_ELVR_LB9                     *((volatile unsigned int*)(0x426001CCUL))
+#define bFM3_EXTI_ELVR_LA10                    *((volatile unsigned int*)(0x426001D0UL))
+#define bFM3_EXTI_ELVR_LB10                    *((volatile unsigned int*)(0x426001D4UL))
+#define bFM3_EXTI_ELVR_LA11                    *((volatile unsigned int*)(0x426001D8UL))
+#define bFM3_EXTI_ELVR_LB11                    *((volatile unsigned int*)(0x426001DCUL))
+#define bFM3_EXTI_ELVR_LA12                    *((volatile unsigned int*)(0x426001E0UL))
+#define bFM3_EXTI_ELVR_LB12                    *((volatile unsigned int*)(0x426001E4UL))
+#define bFM3_EXTI_ELVR_LA13                    *((volatile unsigned int*)(0x426001E8UL))
+#define bFM3_EXTI_ELVR_LB13                    *((volatile unsigned int*)(0x426001ECUL))
+#define bFM3_EXTI_ELVR_LA14                    *((volatile unsigned int*)(0x426001F0UL))
+#define bFM3_EXTI_ELVR_LB14                    *((volatile unsigned int*)(0x426001F4UL))
+#define bFM3_EXTI_ELVR_LA15                    *((volatile unsigned int*)(0x426001F8UL))
+#define bFM3_EXTI_ELVR_LB15                    *((volatile unsigned int*)(0x426001FCUL))
+#define bFM3_EXTI_ELVR_LA16                    *((volatile unsigned int*)(0x42600200UL))
+#define bFM3_EXTI_ELVR_LB16                    *((volatile unsigned int*)(0x42600204UL))
+#define bFM3_EXTI_ELVR_LA17                    *((volatile unsigned int*)(0x42600208UL))
+#define bFM3_EXTI_ELVR_LB17                    *((volatile unsigned int*)(0x4260020CUL))
+#define bFM3_EXTI_ELVR_LA18                    *((volatile unsigned int*)(0x42600210UL))
+#define bFM3_EXTI_ELVR_LB18                    *((volatile unsigned int*)(0x42600214UL))
+#define bFM3_EXTI_ELVR_LA19                    *((volatile unsigned int*)(0x42600218UL))
+#define bFM3_EXTI_ELVR_LB19                    *((volatile unsigned int*)(0x4260021CUL))
+#define bFM3_EXTI_ELVR_LA20                    *((volatile unsigned int*)(0x42600220UL))
+#define bFM3_EXTI_ELVR_LB20                    *((volatile unsigned int*)(0x42600224UL))
+#define bFM3_EXTI_ELVR_LA21                    *((volatile unsigned int*)(0x42600228UL))
+#define bFM3_EXTI_ELVR_LB21                    *((volatile unsigned int*)(0x4260022CUL))
+#define bFM3_EXTI_ELVR_LA22                    *((volatile unsigned int*)(0x42600230UL))
+#define bFM3_EXTI_ELVR_LB22                    *((volatile unsigned int*)(0x42600234UL))
+#define bFM3_EXTI_ELVR_LA23                    *((volatile unsigned int*)(0x42600238UL))
+#define bFM3_EXTI_ELVR_LB23                    *((volatile unsigned int*)(0x4260023CUL))
+#define bFM3_EXTI_ELVR_LA24                    *((volatile unsigned int*)(0x42600240UL))
+#define bFM3_EXTI_ELVR_LB24                    *((volatile unsigned int*)(0x42600244UL))
+#define bFM3_EXTI_ELVR_LA25                    *((volatile unsigned int*)(0x42600248UL))
+#define bFM3_EXTI_ELVR_LB25                    *((volatile unsigned int*)(0x4260024CUL))
+#define bFM3_EXTI_ELVR_LA26                    *((volatile unsigned int*)(0x42600250UL))
+#define bFM3_EXTI_ELVR_LB26                    *((volatile unsigned int*)(0x42600254UL))
+#define bFM3_EXTI_ELVR_LA27                    *((volatile unsigned int*)(0x42600258UL))
+#define bFM3_EXTI_ELVR_LB27                    *((volatile unsigned int*)(0x4260025CUL))
+#define bFM3_EXTI_ELVR_LA28                    *((volatile unsigned int*)(0x42600260UL))
+#define bFM3_EXTI_ELVR_LB28                    *((volatile unsigned int*)(0x42600264UL))
+#define bFM3_EXTI_ELVR_LA29                    *((volatile unsigned int*)(0x42600268UL))
+#define bFM3_EXTI_ELVR_LB29                    *((volatile unsigned int*)(0x4260026CUL))
+#define bFM3_EXTI_ELVR_LA30                    *((volatile unsigned int*)(0x42600270UL))
+#define bFM3_EXTI_ELVR_LB30                    *((volatile unsigned int*)(0x42600274UL))
+#define bFM3_EXTI_ELVR_LA31                    *((volatile unsigned int*)(0x42600278UL))
+#define bFM3_EXTI_ELVR_LB31                    *((volatile unsigned int*)(0x4260027CUL))
+#define bFM3_EXTI_NMIRR_NR0                    *((volatile unsigned int*)(0x42600280UL))
+#define bFM3_EXTI_NMICL_NCL0                   *((volatile unsigned int*)(0x42600300UL))
+
+/* Interrupt request read registers */
+#define bFM3_INTREQ_DRQSEL_DRQSEL0             *((volatile unsigned int*)(0x42620000UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL1             *((volatile unsigned int*)(0x42620004UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL2             *((volatile unsigned int*)(0x42620008UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL3             *((volatile unsigned int*)(0x4262000CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL4             *((volatile unsigned int*)(0x42620010UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL5             *((volatile unsigned int*)(0x42620014UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL6             *((volatile unsigned int*)(0x42620018UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL7             *((volatile unsigned int*)(0x4262001CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL8             *((volatile unsigned int*)(0x42620020UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL9             *((volatile unsigned int*)(0x42620024UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL10            *((volatile unsigned int*)(0x42620028UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL11            *((volatile unsigned int*)(0x4262002CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL12            *((volatile unsigned int*)(0x42620030UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL13            *((volatile unsigned int*)(0x42620034UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL14            *((volatile unsigned int*)(0x42620038UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL15            *((volatile unsigned int*)(0x4262003CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL16            *((volatile unsigned int*)(0x42620040UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL17            *((volatile unsigned int*)(0x42620044UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL18            *((volatile unsigned int*)(0x42620048UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL19            *((volatile unsigned int*)(0x4262004CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL20            *((volatile unsigned int*)(0x42620050UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL21            *((volatile unsigned int*)(0x42620054UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL22            *((volatile unsigned int*)(0x42620058UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL23            *((volatile unsigned int*)(0x4262005CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL24            *((volatile unsigned int*)(0x42620060UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL25            *((volatile unsigned int*)(0x42620064UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL26            *((volatile unsigned int*)(0x42620068UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL27            *((volatile unsigned int*)(0x4262006CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL28            *((volatile unsigned int*)(0x42620070UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL29            *((volatile unsigned int*)(0x42620074UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL30            *((volatile unsigned int*)(0x42620078UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL31            *((volatile unsigned int*)(0x4262007CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS0             *((volatile unsigned char*)(0x42620160UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS1             *((volatile unsigned char*)(0x42620164UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS2             *((volatile unsigned char*)(0x42620168UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS3             *((volatile unsigned char*)(0x4262016CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS4             *((volatile unsigned char*)(0x42620170UL))
+#define bFM3_INTREQ_EXC02MON_NMI               *((volatile unsigned int*)(0x42620200UL))
+#define bFM3_INTREQ_EXC02MON_HWINT             *((volatile unsigned int*)(0x42620204UL))
+#define bFM3_INTREQ_IRQ00MON_FCSINT            *((volatile unsigned int*)(0x42620280UL))
+#define bFM3_INTREQ_IRQ01MON_SWWDTINT          *((volatile unsigned int*)(0x42620300UL))
+#define bFM3_INTREQ_IRQ02MON_LVDINT            *((volatile unsigned int*)(0x42620380UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT0         *((volatile unsigned int*)(0x42620400UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT1         *((volatile unsigned int*)(0x42620404UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT2         *((volatile unsigned int*)(0x42620408UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT3         *((volatile unsigned int*)(0x4262040CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT0         *((volatile unsigned int*)(0x42620410UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT1         *((volatile unsigned int*)(0x42620414UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT2         *((volatile unsigned int*)(0x42620418UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT3         *((volatile unsigned int*)(0x4262041CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT0         *((volatile unsigned int*)(0x42620420UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT1         *((volatile unsigned int*)(0x42620424UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT2         *((volatile unsigned int*)(0x42620428UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT3         *((volatile unsigned int*)(0x4262042CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT0           *((volatile unsigned int*)(0x42620480UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT1           *((volatile unsigned int*)(0x42620484UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT2           *((volatile unsigned int*)(0x42620488UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT3           *((volatile unsigned int*)(0x4262048CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT4           *((volatile unsigned int*)(0x42620490UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT5           *((volatile unsigned int*)(0x42620494UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT6           *((volatile unsigned int*)(0x42620498UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT7           *((volatile unsigned int*)(0x4262049CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT0           *((volatile unsigned int*)(0x42620500UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT1           *((volatile unsigned int*)(0x42620504UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT2           *((volatile unsigned int*)(0x42620508UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT3           *((volatile unsigned int*)(0x4262050CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT4           *((volatile unsigned int*)(0x42620510UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT5           *((volatile unsigned int*)(0x42620514UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT6           *((volatile unsigned int*)(0x42620518UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT7           *((volatile unsigned int*)(0x4262051CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT8           *((volatile unsigned int*)(0x42620520UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT9           *((volatile unsigned int*)(0x42620524UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT10          *((volatile unsigned int*)(0x42620528UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT11          *((volatile unsigned int*)(0x4262052CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT12          *((volatile unsigned int*)(0x42620530UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT13          *((volatile unsigned int*)(0x42620534UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT14          *((volatile unsigned int*)(0x42620538UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT15          *((volatile unsigned int*)(0x4262053CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT16          *((volatile unsigned int*)(0x42620540UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT17          *((volatile unsigned int*)(0x42620544UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT18          *((volatile unsigned int*)(0x42620548UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT19          *((volatile unsigned int*)(0x4262054CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT20          *((volatile unsigned int*)(0x42620550UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT21          *((volatile unsigned int*)(0x42620554UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT22          *((volatile unsigned int*)(0x42620558UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT23          *((volatile unsigned int*)(0x4262055CUL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT1           *((volatile unsigned int*)(0x42620580UL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT2           *((volatile unsigned int*)(0x42620584UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT0          *((volatile unsigned int*)(0x42620588UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT1          *((volatile unsigned int*)(0x4262058CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT2          *((volatile unsigned int*)(0x42620590UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT3          *((volatile unsigned int*)(0x42620594UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT4          *((volatile unsigned int*)(0x42620598UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT5          *((volatile unsigned int*)(0x4262059CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT0          *((volatile unsigned int*)(0x426205A0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT1          *((volatile unsigned int*)(0x426205A4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT2          *((volatile unsigned int*)(0x426205A8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT3          *((volatile unsigned int*)(0x426205ACUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT4          *((volatile unsigned int*)(0x426205B0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT5          *((volatile unsigned int*)(0x426205B4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT0          *((volatile unsigned int*)(0x426205B8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT1          *((volatile unsigned int*)(0x426205BCUL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT2          *((volatile unsigned int*)(0x426205C0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT3          *((volatile unsigned int*)(0x426205C4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT4          *((volatile unsigned int*)(0x426205C8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT5          *((volatile unsigned int*)(0x426205CCUL))
+#define bFM3_INTREQ_IRQ07MON_FMSINT            *((volatile unsigned int*)(0x42620600UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT0           *((volatile unsigned int*)(0x42620680UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT1           *((volatile unsigned int*)(0x42620684UL))
+#define bFM3_INTREQ_IRQ09MON_FMSINT            *((volatile unsigned int*)(0x42620700UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT0           *((volatile unsigned int*)(0x42620780UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT1           *((volatile unsigned int*)(0x42620784UL))
+#define bFM3_INTREQ_IRQ11MON_FMSINT            *((volatile unsigned int*)(0x42620800UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT0           *((volatile unsigned int*)(0x42620880UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT1           *((volatile unsigned int*)(0x42620884UL))
+#define bFM3_INTREQ_IRQ13MON_FMSINT            *((volatile unsigned int*)(0x42620900UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT0           *((volatile unsigned int*)(0x42620980UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT1           *((volatile unsigned int*)(0x42620984UL))
+#define bFM3_INTREQ_IRQ15MON_FMSINT            *((volatile unsigned int*)(0x42620A00UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT0           *((volatile unsigned int*)(0x42620A80UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT1           *((volatile unsigned int*)(0x42620A84UL))
+#define bFM3_INTREQ_IRQ17MON_FMSINT            *((volatile unsigned int*)(0x42620B00UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT0           *((volatile unsigned int*)(0x42620B80UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT1           *((volatile unsigned int*)(0x42620B84UL))
+#define bFM3_INTREQ_IRQ19MON_FMSINT            *((volatile unsigned int*)(0x42620C00UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT0           *((volatile unsigned int*)(0x42620C80UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT1           *((volatile unsigned int*)(0x42620C84UL))
+#define bFM3_INTREQ_IRQ21MON_FMSINT            *((volatile unsigned int*)(0x42620D00UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT0           *((volatile unsigned int*)(0x42620D80UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT1           *((volatile unsigned int*)(0x42620D84UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT0           *((volatile unsigned int*)(0x42620E00UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT1           *((volatile unsigned int*)(0x42620E04UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT2           *((volatile unsigned int*)(0x42620E08UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT3           *((volatile unsigned int*)(0x42620E0CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT4           *((volatile unsigned int*)(0x42620E10UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT5           *((volatile unsigned int*)(0x42620E14UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT6           *((volatile unsigned int*)(0x42620E18UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT7           *((volatile unsigned int*)(0x42620E1CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT8           *((volatile unsigned int*)(0x42620E20UL))
+#define bFM3_INTREQ_IRQ24MON_MOSCINT           *((volatile unsigned int*)(0x42620E80UL))
+#define bFM3_INTREQ_IRQ24MON_SOSCINT           *((volatile unsigned int*)(0x42620E84UL))
+#define bFM3_INTREQ_IRQ24MON_MPLLINT           *((volatile unsigned int*)(0x42620E88UL))
+#define bFM3_INTREQ_IRQ24MON_UPLLINT           *((volatile unsigned int*)(0x42620E8CUL))
+#define bFM3_INTREQ_IRQ24MON_WCINT             *((volatile unsigned int*)(0x42620E90UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT0           *((volatile unsigned int*)(0x42620F00UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT1           *((volatile unsigned int*)(0x42620F04UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT2           *((volatile unsigned int*)(0x42620F08UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT3           *((volatile unsigned int*)(0x42620F0CUL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT0           *((volatile unsigned int*)(0x42620F80UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT1           *((volatile unsigned int*)(0x42620F84UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT2           *((volatile unsigned int*)(0x42620F88UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT3           *((volatile unsigned int*)(0x42620F8CUL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT0           *((volatile unsigned int*)(0x42621000UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT1           *((volatile unsigned int*)(0x42621004UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT2           *((volatile unsigned int*)(0x42621008UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT3           *((volatile unsigned int*)(0x4262100CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT0          *((volatile unsigned int*)(0x42621080UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT1          *((volatile unsigned int*)(0x42621084UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT2          *((volatile unsigned int*)(0x42621088UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT3          *((volatile unsigned int*)(0x4262108CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT4          *((volatile unsigned int*)(0x42621090UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT5          *((volatile unsigned int*)(0x42621094UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT0          *((volatile unsigned int*)(0x42621098UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT1          *((volatile unsigned int*)(0x4262109CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT2          *((volatile unsigned int*)(0x426210A0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT3          *((volatile unsigned int*)(0x426210A4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT4          *((volatile unsigned int*)(0x426210A8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT5          *((volatile unsigned int*)(0x426210ACUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT0          *((volatile unsigned int*)(0x426210B0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT1          *((volatile unsigned int*)(0x426210B4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT2          *((volatile unsigned int*)(0x426210B8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT3          *((volatile unsigned int*)(0x426210BCUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT4          *((volatile unsigned int*)(0x426210C0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT5          *((volatile unsigned int*)(0x426210C4UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT0          *((volatile unsigned int*)(0x42621100UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT1          *((volatile unsigned int*)(0x42621104UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT2          *((volatile unsigned int*)(0x42621108UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT3          *((volatile unsigned int*)(0x4262110CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT0          *((volatile unsigned int*)(0x42621110UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT1          *((volatile unsigned int*)(0x42621114UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT2          *((volatile unsigned int*)(0x42621118UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT3          *((volatile unsigned int*)(0x4262111CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT0          *((volatile unsigned int*)(0x42621120UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT1          *((volatile unsigned int*)(0x42621124UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT2          *((volatile unsigned int*)(0x42621128UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT3          *((volatile unsigned int*)(0x4262112CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT0          *((volatile unsigned int*)(0x42621180UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT1          *((volatile unsigned int*)(0x42621184UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT2          *((volatile unsigned int*)(0x42621188UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT3          *((volatile unsigned int*)(0x4262118CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT4          *((volatile unsigned int*)(0x42621190UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT5          *((volatile unsigned int*)(0x42621194UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT0          *((volatile unsigned int*)(0x42621198UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT1          *((volatile unsigned int*)(0x4262119CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT2          *((volatile unsigned int*)(0x426211A0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT3          *((volatile unsigned int*)(0x426211A4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT4          *((volatile unsigned int*)(0x426211A8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT5          *((volatile unsigned int*)(0x426211ACUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT0          *((volatile unsigned int*)(0x426211B0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT1          *((volatile unsigned int*)(0x426211B4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT2          *((volatile unsigned int*)(0x426211B8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT3          *((volatile unsigned int*)(0x426211BCUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT4          *((volatile unsigned int*)(0x426211C0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT5          *((volatile unsigned int*)(0x426211C4UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT0            *((volatile unsigned int*)(0x42621200UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT1            *((volatile unsigned int*)(0x42621204UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT2            *((volatile unsigned int*)(0x42621208UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT3            *((volatile unsigned int*)(0x4262120CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT4            *((volatile unsigned int*)(0x42621210UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT5            *((volatile unsigned int*)(0x42621214UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT6            *((volatile unsigned int*)(0x42621218UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT7            *((volatile unsigned int*)(0x4262121CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT8            *((volatile unsigned int*)(0x42621220UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT9            *((volatile unsigned int*)(0x42621224UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT10           *((volatile unsigned int*)(0x42621228UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT11           *((volatile unsigned int*)(0x4262122CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT12           *((volatile unsigned int*)(0x42621230UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT13           *((volatile unsigned int*)(0x42621234UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT14           *((volatile unsigned int*)(0x42621238UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT15           *((volatile unsigned int*)(0x4262123CUL))
+#define bFM3_INTREQ_IRQ32MON_MAC0SBD           *((volatile unsigned int*)(0x42621284UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0PMI           *((volatile unsigned int*)(0x42621288UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0LPI           *((volatile unsigned int*)(0x4262128CUL))
+#define bFM3_INTREQ_IRQ33MON_MAC1SBD           *((volatile unsigned int*)(0x42621304UL))
+#define bFM3_INTREQ_IRQ33MON_MAC1PMI           *((volatile unsigned int*)(0x42621308UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT0          *((volatile unsigned int*)(0x42621380UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT1          *((volatile unsigned int*)(0x42621384UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT2          *((volatile unsigned int*)(0x42621388UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT3          *((volatile unsigned int*)(0x4262138CUL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT4          *((volatile unsigned int*)(0x42621390UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT0          *((volatile unsigned int*)(0x42621400UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT1          *((volatile unsigned int*)(0x42621404UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT2          *((volatile unsigned int*)(0x42621408UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT3          *((volatile unsigned int*)(0x4262140CUL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT4          *((volatile unsigned int*)(0x42621410UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT5          *((volatile unsigned int*)(0x42621414UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT0          *((volatile unsigned int*)(0x42621480UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT1          *((volatile unsigned int*)(0x42621484UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT2          *((volatile unsigned int*)(0x42621488UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT3          *((volatile unsigned int*)(0x4262148CUL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT4          *((volatile unsigned int*)(0x42621490UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT0          *((volatile unsigned int*)(0x42621500UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT1          *((volatile unsigned int*)(0x42621504UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT2          *((volatile unsigned int*)(0x42621508UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT3          *((volatile unsigned int*)(0x4262150CUL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT4          *((volatile unsigned int*)(0x42621510UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT5          *((volatile unsigned int*)(0x42621514UL))
+#define bFM3_INTREQ_IRQ38MON_DMAINT            *((volatile unsigned int*)(0x42621580UL))
+#define bFM3_INTREQ_IRQ39MON_DMAINT            *((volatile unsigned int*)(0x42621600UL))
+#define bFM3_INTREQ_IRQ40MON_DMAINT            *((volatile unsigned int*)(0x42621680UL))
+#define bFM3_INTREQ_IRQ41MON_DMAINT            *((volatile unsigned int*)(0x42621700UL))
+#define bFM3_INTREQ_IRQ42MON_DMAINT            *((volatile unsigned int*)(0x42621780UL))
+#define bFM3_INTREQ_IRQ43MON_DMAINT            *((volatile unsigned int*)(0x42621800UL))
+#define bFM3_INTREQ_IRQ44MON_DMAINT            *((volatile unsigned int*)(0x42621880UL))
+#define bFM3_INTREQ_IRQ45MON_DMAINT            *((volatile unsigned int*)(0x42621900UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT0            *((volatile unsigned int*)(0x42621980UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT1            *((volatile unsigned int*)(0x42621984UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT2            *((volatile unsigned int*)(0x42621988UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT3            *((volatile unsigned int*)(0x4262198CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT4            *((volatile unsigned int*)(0x42621990UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT5            *((volatile unsigned int*)(0x42621994UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT6            *((volatile unsigned int*)(0x42621998UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT7            *((volatile unsigned int*)(0x4262199CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT8            *((volatile unsigned int*)(0x426219A0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT9            *((volatile unsigned int*)(0x426219A4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT10           *((volatile unsigned int*)(0x426219A8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT11           *((volatile unsigned int*)(0x426219ACUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT12           *((volatile unsigned int*)(0x426219B0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT13           *((volatile unsigned int*)(0x426219B4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT14           *((volatile unsigned int*)(0x426219B8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT15           *((volatile unsigned int*)(0x426219BCUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL10           *((volatile unsigned int*)(0x42624000UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL11           *((volatile unsigned int*)(0x42624004UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL12           *((volatile unsigned int*)(0x42624008UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL13           *((volatile unsigned int*)(0x4262400CUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL14           *((volatile unsigned int*)(0x42624010UL))
+#define bFM3_INTREQ_DQESEL_ESEL100             *((volatile unsigned int*)(0x42624080UL))
+#define bFM3_INTREQ_DQESEL_ESEL101             *((volatile unsigned int*)(0x42624084UL))
+#define bFM3_INTREQ_DQESEL_ESEL102             *((volatile unsigned int*)(0x42624088UL))
+#define bFM3_INTREQ_DQESEL_ESEL103             *((volatile unsigned int*)(0x4262408CUL))
+#define bFM3_INTREQ_DQESEL_ESEL110             *((volatile unsigned int*)(0x42624090UL))
+#define bFM3_INTREQ_DQESEL_ESEL111             *((volatile unsigned int*)(0x42624094UL))
+#define bFM3_INTREQ_DQESEL_ESEL112             *((volatile unsigned int*)(0x42624098UL))
+#define bFM3_INTREQ_DQESEL_ESEL113             *((volatile unsigned int*)(0x4262409CUL))
+#define bFM3_INTREQ_DQESEL_ESEL240             *((volatile unsigned int*)(0x426240A0UL))
+#define bFM3_INTREQ_DQESEL_ESEL241             *((volatile unsigned int*)(0x426240A4UL))
+#define bFM3_INTREQ_DQESEL_ESEL242             *((volatile unsigned int*)(0x426240A8UL))
+#define bFM3_INTREQ_DQESEL_ESEL243             *((volatile unsigned int*)(0x426240ACUL))
+#define bFM3_INTREQ_DQESEL_ESEL250             *((volatile unsigned int*)(0x426240B0UL))
+#define bFM3_INTREQ_DQESEL_ESEL251             *((volatile unsigned int*)(0x426240B4UL))
+#define bFM3_INTREQ_DQESEL_ESEL252             *((volatile unsigned int*)(0x426240B8UL))
+#define bFM3_INTREQ_DQESEL_ESEL253             *((volatile unsigned int*)(0x426240BCUL))
+#define bFM3_INTREQ_DQESEL_ESEL260             *((volatile unsigned int*)(0x426240C0UL))
+#define bFM3_INTREQ_DQESEL_ESEL261             *((volatile unsigned int*)(0x426240C4UL))
+#define bFM3_INTREQ_DQESEL_ESEL262             *((volatile unsigned int*)(0x426240C8UL))
+#define bFM3_INTREQ_DQESEL_ESEL263             *((volatile unsigned int*)(0x426240CCUL))
+#define bFM3_INTREQ_DQESEL_ESEL270             *((volatile unsigned int*)(0x426240D0UL))
+#define bFM3_INTREQ_DQESEL_ESEL271             *((volatile unsigned int*)(0x426240D4UL))
+#define bFM3_INTREQ_DQESEL_ESEL272             *((volatile unsigned int*)(0x426240D8UL))
+#define bFM3_INTREQ_DQESEL_ESEL273             *((volatile unsigned int*)(0x426240DCUL))
+#define bFM3_INTREQ_DQESEL_ESEL300             *((volatile unsigned int*)(0x426240E0UL))
+#define bFM3_INTREQ_DQESEL_ESEL301             *((volatile unsigned int*)(0x426240E4UL))
+#define bFM3_INTREQ_DQESEL_ESEL302             *((volatile unsigned int*)(0x426240E8UL))
+#define bFM3_INTREQ_DQESEL_ESEL303             *((volatile unsigned int*)(0x426240ECUL))
+#define bFM3_INTREQ_DQESEL_ESEL310             *((volatile unsigned int*)(0x426240F0UL))
+#define bFM3_INTREQ_DQESEL_ESEL311             *((volatile unsigned int*)(0x426240F4UL))
+#define bFM3_INTREQ_DQESEL_ESEL312             *((volatile unsigned int*)(0x426240F8UL))
+#define bFM3_INTREQ_DQESEL_ESEL313             *((volatile unsigned int*)(0x426240FCUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS10           *((volatile unsigned char*)(0x426241E0UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS11           *((volatile unsigned char*)(0x426241E4UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS12           *((volatile unsigned char*)(0x426241E8UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS13           *((volatile unsigned char*)(0x426241ECUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS14           *((volatile unsigned char*)(0x426241F0UL))
+
+/* General purpose I/O registers */
+#define bFM3_GPIO_PFR0_P0                      *((volatile unsigned int*)(0x42660000UL))
+#define bFM3_GPIO_PFR0_P1                      *((volatile unsigned int*)(0x42660004UL))
+#define bFM3_GPIO_PFR0_P2                      *((volatile unsigned int*)(0x42660008UL))
+#define bFM3_GPIO_PFR0_P3                      *((volatile unsigned int*)(0x4266000CUL))
+#define bFM3_GPIO_PFR0_P4                      *((volatile unsigned int*)(0x42660010UL))
+#define bFM3_GPIO_PFR0_P5                      *((volatile unsigned int*)(0x42660014UL))
+#define bFM3_GPIO_PFR0_P6                      *((volatile unsigned int*)(0x42660018UL))
+#define bFM3_GPIO_PFR0_P7                      *((volatile unsigned int*)(0x4266001CUL))
+#define bFM3_GPIO_PFR0_P8                      *((volatile unsigned int*)(0x42660020UL))
+#define bFM3_GPIO_PFR0_P9                      *((volatile unsigned int*)(0x42660024UL))
+#define bFM3_GPIO_PFR1_P0                      *((volatile unsigned int*)(0x42660080UL))
+#define bFM3_GPIO_PFR1_P1                      *((volatile unsigned int*)(0x42660084UL))
+#define bFM3_GPIO_PFR1_P2                      *((volatile unsigned int*)(0x42660088UL))
+#define bFM3_GPIO_PFR1_P3                      *((volatile unsigned int*)(0x4266008CUL))
+#define bFM3_GPIO_PFR1_P4                      *((volatile unsigned int*)(0x42660090UL))
+#define bFM3_GPIO_PFR1_P5                      *((volatile unsigned int*)(0x42660094UL))
+#define bFM3_GPIO_PFR1_P6                      *((volatile unsigned int*)(0x42660098UL))
+#define bFM3_GPIO_PFR1_P7                      *((volatile unsigned int*)(0x4266009CUL))
+#define bFM3_GPIO_PFR1_P8                      *((volatile unsigned int*)(0x426600A0UL))
+#define bFM3_GPIO_PFR1_P9                      *((volatile unsigned int*)(0x426600A4UL))
+#define bFM3_GPIO_PFR1_PA                      *((volatile unsigned int*)(0x426600A8UL))
+#define bFM3_GPIO_PFR1_PB                      *((volatile unsigned int*)(0x426600ACUL))
+#define bFM3_GPIO_PFR1_PC                      *((volatile unsigned int*)(0x426600B0UL))
+#define bFM3_GPIO_PFR1_PD                      *((volatile unsigned int*)(0x426600B4UL))
+#define bFM3_GPIO_PFR1_PE                      *((volatile unsigned int*)(0x426600B8UL))
+#define bFM3_GPIO_PFR1_PF                      *((volatile unsigned int*)(0x426600BCUL))
+#define bFM3_GPIO_PFR2_P0                      *((volatile unsigned int*)(0x42660100UL))
+#define bFM3_GPIO_PFR2_P1                      *((volatile unsigned int*)(0x42660104UL))
+#define bFM3_GPIO_PFR2_P2                      *((volatile unsigned int*)(0x42660108UL))
+#define bFM3_GPIO_PFR2_P3                      *((volatile unsigned int*)(0x4266010CUL))
+#define bFM3_GPIO_PFR2_P4                      *((volatile unsigned int*)(0x42660110UL))
+#define bFM3_GPIO_PFR2_P5                      *((volatile unsigned int*)(0x42660114UL))
+#define bFM3_GPIO_PFR2_P6                      *((volatile unsigned int*)(0x42660118UL))
+#define bFM3_GPIO_PFR2_P7                      *((volatile unsigned int*)(0x4266011CUL))
+#define bFM3_GPIO_PFR2_P8                      *((volatile unsigned int*)(0x42660120UL))
+#define bFM3_GPIO_PFR2_P9                      *((volatile unsigned int*)(0x42660124UL))
+#define bFM3_GPIO_PFR3_P6                      *((volatile unsigned int*)(0x42660198UL))
+#define bFM3_GPIO_PFR3_P7                      *((volatile unsigned int*)(0x4266019CUL))
+#define bFM3_GPIO_PFR3_P8                      *((volatile unsigned int*)(0x426601A0UL))
+#define bFM3_GPIO_PFR3_P9                      *((volatile unsigned int*)(0x426601A4UL))
+#define bFM3_GPIO_PFR3_PA                      *((volatile unsigned int*)(0x426601A8UL))
+#define bFM3_GPIO_PFR3_PB                      *((volatile unsigned int*)(0x426601ACUL))
+#define bFM3_GPIO_PFR3_PC                      *((volatile unsigned int*)(0x426601B0UL))
+#define bFM3_GPIO_PFR3_PD                      *((volatile unsigned int*)(0x426601B4UL))
+#define bFM3_GPIO_PFR3_PE                      *((volatile unsigned int*)(0x426601B8UL))
+#define bFM3_GPIO_PFR3_PF                      *((volatile unsigned int*)(0x426601BCUL))
+#define bFM3_GPIO_PFR4_P0                      *((volatile unsigned int*)(0x42660200UL))
+#define bFM3_GPIO_PFR4_P1                      *((volatile unsigned int*)(0x42660204UL))
+#define bFM3_GPIO_PFR4_P2                      *((volatile unsigned int*)(0x42660208UL))
+#define bFM3_GPIO_PFR4_P3                      *((volatile unsigned int*)(0x4266020CUL))
+#define bFM3_GPIO_PFR4_P4                      *((volatile unsigned int*)(0x42660210UL))
+#define bFM3_GPIO_PFR4_P5                      *((volatile unsigned int*)(0x42660214UL))
+#define bFM3_GPIO_PFR4_P6                      *((volatile unsigned int*)(0x42660218UL))
+#define bFM3_GPIO_PFR4_P7                      *((volatile unsigned int*)(0x4266021CUL))
+#define bFM3_GPIO_PFR4_P8                      *((volatile unsigned int*)(0x42660220UL))
+#define bFM3_GPIO_PFR4_P9                      *((volatile unsigned int*)(0x42660224UL))
+#define bFM3_GPIO_PFR4_PA                      *((volatile unsigned int*)(0x42660228UL))
+#define bFM3_GPIO_PFR4_PB                      *((volatile unsigned int*)(0x4266022CUL))
+#define bFM3_GPIO_PFR4_PC                      *((volatile unsigned int*)(0x42660230UL))
+#define bFM3_GPIO_PFR4_PD                      *((volatile unsigned int*)(0x42660234UL))
+#define bFM3_GPIO_PFR4_PE                      *((volatile unsigned int*)(0x42660238UL))
+#define bFM3_GPIO_PFR5_P0                      *((volatile unsigned int*)(0x42660280UL))
+#define bFM3_GPIO_PFR5_P1                      *((volatile unsigned int*)(0x42660284UL))
+#define bFM3_GPIO_PFR5_P2                      *((volatile unsigned int*)(0x42660288UL))
+#define bFM3_GPIO_PFR5_P3                      *((volatile unsigned int*)(0x4266028CUL))
+#define bFM3_GPIO_PFR5_P4                      *((volatile unsigned int*)(0x42660290UL))
+#define bFM3_GPIO_PFR5_P5                      *((volatile unsigned int*)(0x42660294UL))
+#define bFM3_GPIO_PFR5_P6                      *((volatile unsigned int*)(0x42660298UL))
+#define bFM3_GPIO_PFR5_P7                      *((volatile unsigned int*)(0x4266029CUL))
+#define bFM3_GPIO_PFR5_P8                      *((volatile unsigned int*)(0x426602A0UL))
+#define bFM3_GPIO_PFR5_P9                      *((volatile unsigned int*)(0x426602A4UL))
+#define bFM3_GPIO_PFR5_PA                      *((volatile unsigned int*)(0x426602A8UL))
+#define bFM3_GPIO_PFR5_PB                      *((volatile unsigned int*)(0x426602ACUL))
+#define bFM3_GPIO_PFR6_P0                      *((volatile unsigned int*)(0x42660300UL))
+#define bFM3_GPIO_PFR6_P1                      *((volatile unsigned int*)(0x42660304UL))
+#define bFM3_GPIO_PFR6_P2                      *((volatile unsigned int*)(0x42660308UL))
+#define bFM3_GPIO_PFR7_P0                      *((volatile unsigned int*)(0x42660380UL))
+#define bFM3_GPIO_PFR7_P1                      *((volatile unsigned int*)(0x42660384UL))
+#define bFM3_GPIO_PFR7_P2                      *((volatile unsigned int*)(0x42660388UL))
+#define bFM3_GPIO_PFR7_P3                      *((volatile unsigned int*)(0x4266038CUL))
+#define bFM3_GPIO_PFR7_P4                      *((volatile unsigned int*)(0x42660390UL))
+#define bFM3_GPIO_PFR7_P5                      *((volatile unsigned int*)(0x42660394UL))
+#define bFM3_GPIO_PFR7_P6                      *((volatile unsigned int*)(0x42660398UL))
+#define bFM3_GPIO_PFR7_P7                      *((volatile unsigned int*)(0x4266039CUL))
+#define bFM3_GPIO_PFR7_P8                      *((volatile unsigned int*)(0x426603A0UL))
+#define bFM3_GPIO_PFR7_P9                      *((volatile unsigned int*)(0x426603A4UL))
+#define bFM3_GPIO_PFR7_PA                      *((volatile unsigned int*)(0x426603A8UL))
+#define bFM3_GPIO_PFR8_P0                      *((volatile unsigned int*)(0x42660400UL))
+#define bFM3_GPIO_PFR8_P1                      *((volatile unsigned int*)(0x42660404UL))
+#define bFM3_GPIO_PFR8_P2                      *((volatile unsigned int*)(0x42660408UL))
+#define bFM3_GPIO_PFR8_P3                      *((volatile unsigned int*)(0x4266040CUL))
+#define bFM3_GPIO_PFRA_P0                      *((volatile unsigned int*)(0x42660500UL))
+#define bFM3_GPIO_PFRA_P1                      *((volatile unsigned int*)(0x42660504UL))
+#define bFM3_GPIO_PFRA_P2                      *((volatile unsigned int*)(0x42660508UL))
+#define bFM3_GPIO_PFRA_P3                      *((volatile unsigned int*)(0x4266050CUL))
+#define bFM3_GPIO_PFRA_P4                      *((volatile unsigned int*)(0x42660510UL))
+#define bFM3_GPIO_PFRA_P5                      *((volatile unsigned int*)(0x42660514UL))
+#define bFM3_GPIO_PFRC_P0                      *((volatile unsigned int*)(0x42660600UL))
+#define bFM3_GPIO_PFRC_P1                      *((volatile unsigned int*)(0x42660604UL))
+#define bFM3_GPIO_PFRC_P2                      *((volatile unsigned int*)(0x42660608UL))
+#define bFM3_GPIO_PFRC_P3                      *((volatile unsigned int*)(0x4266060CUL))
+#define bFM3_GPIO_PFRC_P4                      *((volatile unsigned int*)(0x42660610UL))
+#define bFM3_GPIO_PFRC_P5                      *((volatile unsigned int*)(0x42660614UL))
+#define bFM3_GPIO_PFRC_P6                      *((volatile unsigned int*)(0x42660618UL))
+#define bFM3_GPIO_PFRC_P7                      *((volatile unsigned int*)(0x4266061CUL))
+#define bFM3_GPIO_PFRC_P8                      *((volatile unsigned int*)(0x42660620UL))
+#define bFM3_GPIO_PFRC_P9                      *((volatile unsigned int*)(0x42660624UL))
+#define bFM3_GPIO_PFRC_PA                      *((volatile unsigned int*)(0x42660628UL))
+#define bFM3_GPIO_PFRC_PB                      *((volatile unsigned int*)(0x4266062CUL))
+#define bFM3_GPIO_PFRC_PC                      *((volatile unsigned int*)(0x42660630UL))
+#define bFM3_GPIO_PFRC_PD                      *((volatile unsigned int*)(0x42660634UL))
+#define bFM3_GPIO_PFRC_PE                      *((volatile unsigned int*)(0x42660638UL))
+#define bFM3_GPIO_PFRC_PF                      *((volatile unsigned int*)(0x4266063CUL))
+#define bFM3_GPIO_PFRD_P0                      *((volatile unsigned int*)(0x42660680UL))
+#define bFM3_GPIO_PFRD_P1                      *((volatile unsigned int*)(0x42660684UL))
+#define bFM3_GPIO_PFRD_P2                      *((volatile unsigned int*)(0x42660688UL))
+#define bFM3_GPIO_PFRD_P3                      *((volatile unsigned int*)(0x4266068CUL))
+#define bFM3_GPIO_PFRE_P0                      *((volatile unsigned int*)(0x42660700UL))
+#define bFM3_GPIO_PFRE_P2                      *((volatile unsigned int*)(0x42660708UL))
+#define bFM3_GPIO_PFRE_P3                      *((volatile unsigned int*)(0x4266070CUL))
+#define bFM3_GPIO_PFRF_P5                      *((volatile unsigned int*)(0x42660794UL))
+#define bFM3_GPIO_PFRF_P6                      *((volatile unsigned int*)(0x42660798UL))
+#define bFM3_GPIO_PCR0_P0                      *((volatile unsigned int*)(0x42662000UL))
+#define bFM3_GPIO_PCR0_P1                      *((volatile unsigned int*)(0x42662004UL))
+#define bFM3_GPIO_PCR0_P2                      *((volatile unsigned int*)(0x42662008UL))
+#define bFM3_GPIO_PCR0_P3                      *((volatile unsigned int*)(0x4266200CUL))
+#define bFM3_GPIO_PCR0_P4                      *((volatile unsigned int*)(0x42662010UL))
+#define bFM3_GPIO_PCR0_P5                      *((volatile unsigned int*)(0x42662014UL))
+#define bFM3_GPIO_PCR0_P6                      *((volatile unsigned int*)(0x42662018UL))
+#define bFM3_GPIO_PCR0_P7                      *((volatile unsigned int*)(0x4266201CUL))
+#define bFM3_GPIO_PCR0_P8                      *((volatile unsigned int*)(0x42662020UL))
+#define bFM3_GPIO_PCR0_P9                      *((volatile unsigned int*)(0x42662024UL))
+#define bFM3_GPIO_PCR1_P0                      *((volatile unsigned int*)(0x42662080UL))
+#define bFM3_GPIO_PCR1_P1                      *((volatile unsigned int*)(0x42662084UL))
+#define bFM3_GPIO_PCR1_P2                      *((volatile unsigned int*)(0x42662088UL))
+#define bFM3_GPIO_PCR1_P3                      *((volatile unsigned int*)(0x4266208CUL))
+#define bFM3_GPIO_PCR1_P4                      *((volatile unsigned int*)(0x42662090UL))
+#define bFM3_GPIO_PCR1_P5                      *((volatile unsigned int*)(0x42662094UL))
+#define bFM3_GPIO_PCR1_P6                      *((volatile unsigned int*)(0x42662098UL))
+#define bFM3_GPIO_PCR1_P7                      *((volatile unsigned int*)(0x4266209CUL))
+#define bFM3_GPIO_PCR1_P8                      *((volatile unsigned int*)(0x426620A0UL))
+#define bFM3_GPIO_PCR1_P9                      *((volatile unsigned int*)(0x426620A4UL))
+#define bFM3_GPIO_PCR1_PA                      *((volatile unsigned int*)(0x426620A8UL))
+#define bFM3_GPIO_PCR1_PB                      *((volatile unsigned int*)(0x426620ACUL))
+#define bFM3_GPIO_PCR1_PC                      *((volatile unsigned int*)(0x426620B0UL))
+#define bFM3_GPIO_PCR1_PD                      *((volatile unsigned int*)(0x426620B4UL))
+#define bFM3_GPIO_PCR1_PE                      *((volatile unsigned int*)(0x426620B8UL))
+#define bFM3_GPIO_PCR1_PF                      *((volatile unsigned int*)(0x426620BCUL))
+#define bFM3_GPIO_PCR2_P0                      *((volatile unsigned int*)(0x42662100UL))
+#define bFM3_GPIO_PCR2_P1                      *((volatile unsigned int*)(0x42662104UL))
+#define bFM3_GPIO_PCR2_P2                      *((volatile unsigned int*)(0x42662108UL))
+#define bFM3_GPIO_PCR2_P3                      *((volatile unsigned int*)(0x4266210CUL))
+#define bFM3_GPIO_PCR2_P4                      *((volatile unsigned int*)(0x42662110UL))
+#define bFM3_GPIO_PCR2_P5                      *((volatile unsigned int*)(0x42662114UL))
+#define bFM3_GPIO_PCR2_P6                      *((volatile unsigned int*)(0x42662118UL))
+#define bFM3_GPIO_PCR2_P7                      *((volatile unsigned int*)(0x4266211CUL))
+#define bFM3_GPIO_PCR2_P8                      *((volatile unsigned int*)(0x42662120UL))
+#define bFM3_GPIO_PCR2_P9                      *((volatile unsigned int*)(0x42662124UL))
+#define bFM3_GPIO_PCR3_P6                      *((volatile unsigned int*)(0x42662198UL))
+#define bFM3_GPIO_PCR3_P7                      *((volatile unsigned int*)(0x4266219CUL))
+#define bFM3_GPIO_PCR3_P8                      *((volatile unsigned int*)(0x426621A0UL))
+#define bFM3_GPIO_PCR3_P9                      *((volatile unsigned int*)(0x426621A4UL))
+#define bFM3_GPIO_PCR3_PA                      *((volatile unsigned int*)(0x426621A8UL))
+#define bFM3_GPIO_PCR3_PB                      *((volatile unsigned int*)(0x426621ACUL))
+#define bFM3_GPIO_PCR3_PC                      *((volatile unsigned int*)(0x426621B0UL))
+#define bFM3_GPIO_PCR3_PD                      *((volatile unsigned int*)(0x426621B4UL))
+#define bFM3_GPIO_PCR3_PE                      *((volatile unsigned int*)(0x426621B8UL))
+#define bFM3_GPIO_PCR3_PF                      *((volatile unsigned int*)(0x426621BCUL))
+#define bFM3_GPIO_PCR4_P0                      *((volatile unsigned int*)(0x42662200UL))
+#define bFM3_GPIO_PCR4_P1                      *((volatile unsigned int*)(0x42662204UL))
+#define bFM3_GPIO_PCR4_P2                      *((volatile unsigned int*)(0x42662208UL))
+#define bFM3_GPIO_PCR4_P3                      *((volatile unsigned int*)(0x4266220CUL))
+#define bFM3_GPIO_PCR4_P4                      *((volatile unsigned int*)(0x42662210UL))
+#define bFM3_GPIO_PCR4_P5                      *((volatile unsigned int*)(0x42662214UL))
+#define bFM3_GPIO_PCR4_P6                      *((volatile unsigned int*)(0x42662218UL))
+#define bFM3_GPIO_PCR4_P7                      *((volatile unsigned int*)(0x4266221CUL))
+#define bFM3_GPIO_PCR4_P8                      *((volatile unsigned int*)(0x42662220UL))
+#define bFM3_GPIO_PCR4_P9                      *((volatile unsigned int*)(0x42662224UL))
+#define bFM3_GPIO_PCR4_PA                      *((volatile unsigned int*)(0x42662228UL))
+#define bFM3_GPIO_PCR4_PB                      *((volatile unsigned int*)(0x4266222CUL))
+#define bFM3_GPIO_PCR4_PC                      *((volatile unsigned int*)(0x42662230UL))
+#define bFM3_GPIO_PCR4_PD                      *((volatile unsigned int*)(0x42662234UL))
+#define bFM3_GPIO_PCR4_PE                      *((volatile unsigned int*)(0x42662238UL))
+#define bFM3_GPIO_PCR5_P0                      *((volatile unsigned int*)(0x42662280UL))
+#define bFM3_GPIO_PCR5_P1                      *((volatile unsigned int*)(0x42662284UL))
+#define bFM3_GPIO_PCR5_P2                      *((volatile unsigned int*)(0x42662288UL))
+#define bFM3_GPIO_PCR5_P3                      *((volatile unsigned int*)(0x4266228CUL))
+#define bFM3_GPIO_PCR5_P4                      *((volatile unsigned int*)(0x42662290UL))
+#define bFM3_GPIO_PCR5_P5                      *((volatile unsigned int*)(0x42662294UL))
+#define bFM3_GPIO_PCR5_P6                      *((volatile unsigned int*)(0x42662298UL))
+#define bFM3_GPIO_PCR5_P7                      *((volatile unsigned int*)(0x4266229CUL))
+#define bFM3_GPIO_PCR5_P8                      *((volatile unsigned int*)(0x426622A0UL))
+#define bFM3_GPIO_PCR5_P9                      *((volatile unsigned int*)(0x426622A4UL))
+#define bFM3_GPIO_PCR5_PA                      *((volatile unsigned int*)(0x426622A8UL))
+#define bFM3_GPIO_PCR5_PB                      *((volatile unsigned int*)(0x426622ACUL))
+#define bFM3_GPIO_PCR6_P0                      *((volatile unsigned int*)(0x42662300UL))
+#define bFM3_GPIO_PCR6_P1                      *((volatile unsigned int*)(0x42662304UL))
+#define bFM3_GPIO_PCR6_P2                      *((volatile unsigned int*)(0x42662308UL))
+#define bFM3_GPIO_PCR7_P0                      *((volatile unsigned int*)(0x42662380UL))
+#define bFM3_GPIO_PCR7_P1                      *((volatile unsigned int*)(0x42662384UL))
+#define bFM3_GPIO_PCR7_P2                      *((volatile unsigned int*)(0x42662388UL))
+#define bFM3_GPIO_PCR7_P3                      *((volatile unsigned int*)(0x4266238CUL))
+#define bFM3_GPIO_PCR7_P4                      *((volatile unsigned int*)(0x42662390UL))
+#define bFM3_GPIO_PCR7_P5                      *((volatile unsigned int*)(0x42662394UL))
+#define bFM3_GPIO_PCR7_P6                      *((volatile unsigned int*)(0x42662398UL))
+#define bFM3_GPIO_PCR7_P7                      *((volatile unsigned int*)(0x4266239CUL))
+#define bFM3_GPIO_PCR7_P8                      *((volatile unsigned int*)(0x426623A0UL))
+#define bFM3_GPIO_PCR7_P9                      *((volatile unsigned int*)(0x426623A4UL))
+#define bFM3_GPIO_PCR7_PA                      *((volatile unsigned int*)(0x426623A8UL))
+#define bFM3_GPIO_PCRA_P0                      *((volatile unsigned int*)(0x42662500UL))
+#define bFM3_GPIO_PCRA_P1                      *((volatile unsigned int*)(0x42662504UL))
+#define bFM3_GPIO_PCRA_P2                      *((volatile unsigned int*)(0x42662508UL))
+#define bFM3_GPIO_PCRA_P3                      *((volatile unsigned int*)(0x4266250CUL))
+#define bFM3_GPIO_PCRA_P4                      *((volatile unsigned int*)(0x42662510UL))
+#define bFM3_GPIO_PCRA_P5                      *((volatile unsigned int*)(0x42662514UL))
+#define bFM3_GPIO_PCRC_P0                      *((volatile unsigned int*)(0x42662600UL))
+#define bFM3_GPIO_PCRC_P1                      *((volatile unsigned int*)(0x42662604UL))
+#define bFM3_GPIO_PCRC_P2                      *((volatile unsigned int*)(0x42662608UL))
+#define bFM3_GPIO_PCRC_P3                      *((volatile unsigned int*)(0x4266260CUL))
+#define bFM3_GPIO_PCRC_P4                      *((volatile unsigned int*)(0x42662610UL))
+#define bFM3_GPIO_PCRC_P5                      *((volatile unsigned int*)(0x42662614UL))
+#define bFM3_GPIO_PCRC_P6                      *((volatile unsigned int*)(0x42662618UL))
+#define bFM3_GPIO_PCRC_P7                      *((volatile unsigned int*)(0x4266261CUL))
+#define bFM3_GPIO_PCRC_P8                      *((volatile unsigned int*)(0x42662620UL))
+#define bFM3_GPIO_PCRC_P9                      *((volatile unsigned int*)(0x42662624UL))
+#define bFM3_GPIO_PCRC_PA                      *((volatile unsigned int*)(0x42662628UL))
+#define bFM3_GPIO_PCRC_PB                      *((volatile unsigned int*)(0x4266262CUL))
+#define bFM3_GPIO_PCRC_PC                      *((volatile unsigned int*)(0x42662630UL))
+#define bFM3_GPIO_PCRC_PD                      *((volatile unsigned int*)(0x42662634UL))
+#define bFM3_GPIO_PCRC_PE                      *((volatile unsigned int*)(0x42662638UL))
+#define bFM3_GPIO_PCRC_PF                      *((volatile unsigned int*)(0x4266263CUL))
+#define bFM3_GPIO_PCRD_P0                      *((volatile unsigned int*)(0x42662680UL))
+#define bFM3_GPIO_PCRD_P1                      *((volatile unsigned int*)(0x42662684UL))
+#define bFM3_GPIO_PCRD_P2                      *((volatile unsigned int*)(0x42662688UL))
+#define bFM3_GPIO_PCRD_P3                      *((volatile unsigned int*)(0x4266268CUL))
+#define bFM3_GPIO_PCRE_P2                      *((volatile unsigned int*)(0x42662708UL))
+#define bFM3_GPIO_PCRE_P3                      *((volatile unsigned int*)(0x4266270CUL))
+#define bFM3_GPIO_DDR0_P0                      *((volatile unsigned int*)(0x42664000UL))
+#define bFM3_GPIO_DDR0_P1                      *((volatile unsigned int*)(0x42664004UL))
+#define bFM3_GPIO_DDR0_P2                      *((volatile unsigned int*)(0x42664008UL))
+#define bFM3_GPIO_DDR0_P3                      *((volatile unsigned int*)(0x4266400CUL))
+#define bFM3_GPIO_DDR0_P4                      *((volatile unsigned int*)(0x42664010UL))
+#define bFM3_GPIO_DDR0_P5                      *((volatile unsigned int*)(0x42664014UL))
+#define bFM3_GPIO_DDR0_P6                      *((volatile unsigned int*)(0x42664018UL))
+#define bFM3_GPIO_DDR0_P7                      *((volatile unsigned int*)(0x4266401CUL))
+#define bFM3_GPIO_DDR0_P8                      *((volatile unsigned int*)(0x42664020UL))
+#define bFM3_GPIO_DDR0_P9                      *((volatile unsigned int*)(0x42664024UL))
+#define bFM3_GPIO_DDR1_P0                      *((volatile unsigned int*)(0x42664080UL))
+#define bFM3_GPIO_DDR1_P1                      *((volatile unsigned int*)(0x42664084UL))
+#define bFM3_GPIO_DDR1_P2                      *((volatile unsigned int*)(0x42664088UL))
+#define bFM3_GPIO_DDR1_P3                      *((volatile unsigned int*)(0x4266408CUL))
+#define bFM3_GPIO_DDR1_P4                      *((volatile unsigned int*)(0x42664090UL))
+#define bFM3_GPIO_DDR1_P5                      *((volatile unsigned int*)(0x42664094UL))
+#define bFM3_GPIO_DDR1_P6                      *((volatile unsigned int*)(0x42664098UL))
+#define bFM3_GPIO_DDR1_P7                      *((volatile unsigned int*)(0x4266409CUL))
+#define bFM3_GPIO_DDR1_P8                      *((volatile unsigned int*)(0x426640A0UL))
+#define bFM3_GPIO_DDR1_P9                      *((volatile unsigned int*)(0x426640A4UL))
+#define bFM3_GPIO_DDR1_PA                      *((volatile unsigned int*)(0x426640A8UL))
+#define bFM3_GPIO_DDR1_PB                      *((volatile unsigned int*)(0x426640ACUL))
+#define bFM3_GPIO_DDR1_PC                      *((volatile unsigned int*)(0x426640B0UL))
+#define bFM3_GPIO_DDR1_PD                      *((volatile unsigned int*)(0x426640B4UL))
+#define bFM3_GPIO_DDR1_PE                      *((volatile unsigned int*)(0x426640B8UL))
+#define bFM3_GPIO_DDR1_PF                      *((volatile unsigned int*)(0x426640BCUL))
+#define bFM3_GPIO_DDR2_P0                      *((volatile unsigned int*)(0x42664100UL))
+#define bFM3_GPIO_DDR2_P1                      *((volatile unsigned int*)(0x42664104UL))
+#define bFM3_GPIO_DDR2_P2                      *((volatile unsigned int*)(0x42664108UL))
+#define bFM3_GPIO_DDR2_P3                      *((volatile unsigned int*)(0x4266410CUL))
+#define bFM3_GPIO_DDR2_P4                      *((volatile unsigned int*)(0x42664110UL))
+#define bFM3_GPIO_DDR2_P5                      *((volatile unsigned int*)(0x42664114UL))
+#define bFM3_GPIO_DDR2_P6                      *((volatile unsigned int*)(0x42664118UL))
+#define bFM3_GPIO_DDR2_P7                      *((volatile unsigned int*)(0x4266411CUL))
+#define bFM3_GPIO_DDR2_P8                      *((volatile unsigned int*)(0x42664120UL))
+#define bFM3_GPIO_DDR2_P9                      *((volatile unsigned int*)(0x42664124UL))
+#define bFM3_GPIO_DDR3_P6                      *((volatile unsigned int*)(0x42664198UL))
+#define bFM3_GPIO_DDR3_P7                      *((volatile unsigned int*)(0x4266419CUL))
+#define bFM3_GPIO_DDR3_P8                      *((volatile unsigned int*)(0x426641A0UL))
+#define bFM3_GPIO_DDR3_P9                      *((volatile unsigned int*)(0x426641A4UL))
+#define bFM3_GPIO_DDR3_PA                      *((volatile unsigned int*)(0x426641A8UL))
+#define bFM3_GPIO_DDR3_PB                      *((volatile unsigned int*)(0x426641ACUL))
+#define bFM3_GPIO_DDR3_PC                      *((volatile unsigned int*)(0x426641B0UL))
+#define bFM3_GPIO_DDR3_PD                      *((volatile unsigned int*)(0x426641B4UL))
+#define bFM3_GPIO_DDR3_PE                      *((volatile unsigned int*)(0x426641B8UL))
+#define bFM3_GPIO_DDR3_PF                      *((volatile unsigned int*)(0x426641BCUL))
+#define bFM3_GPIO_DDR4_P0                      *((volatile unsigned int*)(0x42664200UL))
+#define bFM3_GPIO_DDR4_P1                      *((volatile unsigned int*)(0x42664204UL))
+#define bFM3_GPIO_DDR4_P2                      *((volatile unsigned int*)(0x42664208UL))
+#define bFM3_GPIO_DDR4_P3                      *((volatile unsigned int*)(0x4266420CUL))
+#define bFM3_GPIO_DDR4_P4                      *((volatile unsigned int*)(0x42664210UL))
+#define bFM3_GPIO_DDR4_P5                      *((volatile unsigned int*)(0x42664214UL))
+#define bFM3_GPIO_DDR4_P6                      *((volatile unsigned int*)(0x42664218UL))
+#define bFM3_GPIO_DDR4_P7                      *((volatile unsigned int*)(0x4266421CUL))
+#define bFM3_GPIO_DDR4_P8                      *((volatile unsigned int*)(0x42664220UL))
+#define bFM3_GPIO_DDR4_P9                      *((volatile unsigned int*)(0x42664224UL))
+#define bFM3_GPIO_DDR4_PA                      *((volatile unsigned int*)(0x42664228UL))
+#define bFM3_GPIO_DDR4_PB                      *((volatile unsigned int*)(0x4266422CUL))
+#define bFM3_GPIO_DDR4_PC                      *((volatile unsigned int*)(0x42664230UL))
+#define bFM3_GPIO_DDR4_PD                      *((volatile unsigned int*)(0x42664234UL))
+#define bFM3_GPIO_DDR4_PE                      *((volatile unsigned int*)(0x42664238UL))
+#define bFM3_GPIO_DDR5_P0                      *((volatile unsigned int*)(0x42664280UL))
+#define bFM3_GPIO_DDR5_P1                      *((volatile unsigned int*)(0x42664284UL))
+#define bFM3_GPIO_DDR5_P2                      *((volatile unsigned int*)(0x42664288UL))
+#define bFM3_GPIO_DDR5_P3                      *((volatile unsigned int*)(0x4266428CUL))
+#define bFM3_GPIO_DDR5_P4                      *((volatile unsigned int*)(0x42664290UL))
+#define bFM3_GPIO_DDR5_P5                      *((volatile unsigned int*)(0x42664294UL))
+#define bFM3_GPIO_DDR5_P6                      *((volatile unsigned int*)(0x42664298UL))
+#define bFM3_GPIO_DDR5_P7                      *((volatile unsigned int*)(0x4266429CUL))
+#define bFM3_GPIO_DDR5_P8                      *((volatile unsigned int*)(0x426642A0UL))
+#define bFM3_GPIO_DDR5_P9                      *((volatile unsigned int*)(0x426642A4UL))
+#define bFM3_GPIO_DDR5_PA                      *((volatile unsigned int*)(0x426642A8UL))
+#define bFM3_GPIO_DDR5_PB                      *((volatile unsigned int*)(0x426642ACUL))
+#define bFM3_GPIO_DDR6_P0                      *((volatile unsigned int*)(0x42664300UL))
+#define bFM3_GPIO_DDR6_P1                      *((volatile unsigned int*)(0x42664304UL))
+#define bFM3_GPIO_DDR6_P2                      *((volatile unsigned int*)(0x42664308UL))
+#define bFM3_GPIO_DDR7_P0                      *((volatile unsigned int*)(0x42664380UL))
+#define bFM3_GPIO_DDR7_P1                      *((volatile unsigned int*)(0x42664384UL))
+#define bFM3_GPIO_DDR7_P2                      *((volatile unsigned int*)(0x42664388UL))
+#define bFM3_GPIO_DDR7_P3                      *((volatile unsigned int*)(0x4266438CUL))
+#define bFM3_GPIO_DDR7_P4                      *((volatile unsigned int*)(0x42664390UL))
+#define bFM3_GPIO_DDR7_P5                      *((volatile unsigned int*)(0x42664394UL))
+#define bFM3_GPIO_DDR7_P6                      *((volatile unsigned int*)(0x42664398UL))
+#define bFM3_GPIO_DDR7_P7                      *((volatile unsigned int*)(0x4266439CUL))
+#define bFM3_GPIO_DDR7_P8                      *((volatile unsigned int*)(0x426643A0UL))
+#define bFM3_GPIO_DDR7_P9                      *((volatile unsigned int*)(0x426643A4UL))
+#define bFM3_GPIO_DDR7_PA                      *((volatile unsigned int*)(0x426643A8UL))
+#define bFM3_GPIO_DDR8_P0                      *((volatile unsigned int*)(0x42664400UL))
+#define bFM3_GPIO_DDR8_P1                      *((volatile unsigned int*)(0x42664404UL))
+#define bFM3_GPIO_DDR8_P2                      *((volatile unsigned int*)(0x42664408UL))
+#define bFM3_GPIO_DDR8_P3                      *((volatile unsigned int*)(0x4266440CUL))
+#define bFM3_GPIO_DDRA_P0                      *((volatile unsigned int*)(0x42664500UL))
+#define bFM3_GPIO_DDRA_P1                      *((volatile unsigned int*)(0x42664504UL))
+#define bFM3_GPIO_DDRA_P2                      *((volatile unsigned int*)(0x42664508UL))
+#define bFM3_GPIO_DDRA_P3                      *((volatile unsigned int*)(0x4266450CUL))
+#define bFM3_GPIO_DDRA_P4                      *((volatile unsigned int*)(0x42664510UL))
+#define bFM3_GPIO_DDRA_P5                      *((volatile unsigned int*)(0x42664514UL))
+#define bFM3_GPIO_DDRC_P0                      *((volatile unsigned int*)(0x42664600UL))
+#define bFM3_GPIO_DDRC_P1                      *((volatile unsigned int*)(0x42664604UL))
+#define bFM3_GPIO_DDRC_P2                      *((volatile unsigned int*)(0x42664608UL))
+#define bFM3_GPIO_DDRC_P3                      *((volatile unsigned int*)(0x4266460CUL))
+#define bFM3_GPIO_DDRC_P4                      *((volatile unsigned int*)(0x42664610UL))
+#define bFM3_GPIO_DDRC_P5                      *((volatile unsigned int*)(0x42664614UL))
+#define bFM3_GPIO_DDRC_P6                      *((volatile unsigned int*)(0x42664618UL))
+#define bFM3_GPIO_DDRC_P7                      *((volatile unsigned int*)(0x4266461CUL))
+#define bFM3_GPIO_DDRC_P8                      *((volatile unsigned int*)(0x42664620UL))
+#define bFM3_GPIO_DDRC_P9                      *((volatile unsigned int*)(0x42664624UL))
+#define bFM3_GPIO_DDRC_PA                      *((volatile unsigned int*)(0x42664628UL))
+#define bFM3_GPIO_DDRC_PB                      *((volatile unsigned int*)(0x4266462CUL))
+#define bFM3_GPIO_DDRC_PC                      *((volatile unsigned int*)(0x42664630UL))
+#define bFM3_GPIO_DDRC_PD                      *((volatile unsigned int*)(0x42664634UL))
+#define bFM3_GPIO_DDRC_PE                      *((volatile unsigned int*)(0x42664638UL))
+#define bFM3_GPIO_DDRC_PF                      *((volatile unsigned int*)(0x4266463CUL))
+#define bFM3_GPIO_DDRD_P0                      *((volatile unsigned int*)(0x42664680UL))
+#define bFM3_GPIO_DDRD_P1                      *((volatile unsigned int*)(0x42664684UL))
+#define bFM3_GPIO_DDRD_P2                      *((volatile unsigned int*)(0x42664688UL))
+#define bFM3_GPIO_DDRD_P3                      *((volatile unsigned int*)(0x4266468CUL))
+#define bFM3_GPIO_DDRE_P0                      *((volatile unsigned int*)(0x42664700UL))
+#define bFM3_GPIO_DDRE_P2                      *((volatile unsigned int*)(0x42664708UL))
+#define bFM3_GPIO_DDRE_P3                      *((volatile unsigned int*)(0x4266470CUL))
+#define bFM3_GPIO_DDRF_P5                      *((volatile unsigned int*)(0x42664794UL))
+#define bFM3_GPIO_DDRF_P6                      *((volatile unsigned int*)(0x42664798UL))
+#define bFM3_GPIO_PDIR0_P0                     *((volatile unsigned int*)(0x42666000UL))
+#define bFM3_GPIO_PDIR0_P1                     *((volatile unsigned int*)(0x42666004UL))
+#define bFM3_GPIO_PDIR0_P2                     *((volatile unsigned int*)(0x42666008UL))
+#define bFM3_GPIO_PDIR0_P3                     *((volatile unsigned int*)(0x4266600CUL))
+#define bFM3_GPIO_PDIR0_P4                     *((volatile unsigned int*)(0x42666010UL))
+#define bFM3_GPIO_PDIR0_P5                     *((volatile unsigned int*)(0x42666014UL))
+#define bFM3_GPIO_PDIR0_P6                     *((volatile unsigned int*)(0x42666018UL))
+#define bFM3_GPIO_PDIR0_P7                     *((volatile unsigned int*)(0x4266601CUL))
+#define bFM3_GPIO_PDIR0_P8                     *((volatile unsigned int*)(0x42666020UL))
+#define bFM3_GPIO_PDIR0_P9                     *((volatile unsigned int*)(0x42666024UL))
+#define bFM3_GPIO_PDIR1_P0                     *((volatile unsigned int*)(0x42666080UL))
+#define bFM3_GPIO_PDIR1_P1                     *((volatile unsigned int*)(0x42666084UL))
+#define bFM3_GPIO_PDIR1_P2                     *((volatile unsigned int*)(0x42666088UL))
+#define bFM3_GPIO_PDIR1_P3                     *((volatile unsigned int*)(0x4266608CUL))
+#define bFM3_GPIO_PDIR1_P4                     *((volatile unsigned int*)(0x42666090UL))
+#define bFM3_GPIO_PDIR1_P5                     *((volatile unsigned int*)(0x42666094UL))
+#define bFM3_GPIO_PDIR1_P6                     *((volatile unsigned int*)(0x42666098UL))
+#define bFM3_GPIO_PDIR1_P7                     *((volatile unsigned int*)(0x4266609CUL))
+#define bFM3_GPIO_PDIR1_P8                     *((volatile unsigned int*)(0x426660A0UL))
+#define bFM3_GPIO_PDIR1_P9                     *((volatile unsigned int*)(0x426660A4UL))
+#define bFM3_GPIO_PDIR1_PA                     *((volatile unsigned int*)(0x426660A8UL))
+#define bFM3_GPIO_PDIR1_PB                     *((volatile unsigned int*)(0x426660ACUL))
+#define bFM3_GPIO_PDIR1_PC                     *((volatile unsigned int*)(0x426660B0UL))
+#define bFM3_GPIO_PDIR1_PD                     *((volatile unsigned int*)(0x426660B4UL))
+#define bFM3_GPIO_PDIR1_PE                     *((volatile unsigned int*)(0x426660B8UL))
+#define bFM3_GPIO_PDIR1_PF                     *((volatile unsigned int*)(0x426660BCUL))
+#define bFM3_GPIO_PDIR2_P0                     *((volatile unsigned int*)(0x42666100UL))
+#define bFM3_GPIO_PDIR2_P1                     *((volatile unsigned int*)(0x42666104UL))
+#define bFM3_GPIO_PDIR2_P2                     *((volatile unsigned int*)(0x42666108UL))
+#define bFM3_GPIO_PDIR2_P3                     *((volatile unsigned int*)(0x4266610CUL))
+#define bFM3_GPIO_PDIR2_P4                     *((volatile unsigned int*)(0x42666110UL))
+#define bFM3_GPIO_PDIR2_P5                     *((volatile unsigned int*)(0x42666114UL))
+#define bFM3_GPIO_PDIR2_P6                     *((volatile unsigned int*)(0x42666118UL))
+#define bFM3_GPIO_PDIR2_P7                     *((volatile unsigned int*)(0x4266611CUL))
+#define bFM3_GPIO_PDIR2_P8                     *((volatile unsigned int*)(0x42666120UL))
+#define bFM3_GPIO_PDIR2_P9                     *((volatile unsigned int*)(0x42666124UL))
+#define bFM3_GPIO_PDIR3_P6                     *((volatile unsigned int*)(0x42666198UL))
+#define bFM3_GPIO_PDIR3_P7                     *((volatile unsigned int*)(0x4266619CUL))
+#define bFM3_GPIO_PDIR3_P8                     *((volatile unsigned int*)(0x426661A0UL))
+#define bFM3_GPIO_PDIR3_P9                     *((volatile unsigned int*)(0x426661A4UL))
+#define bFM3_GPIO_PDIR3_PA                     *((volatile unsigned int*)(0x426661A8UL))
+#define bFM3_GPIO_PDIR3_PB                     *((volatile unsigned int*)(0x426661ACUL))
+#define bFM3_GPIO_PDIR3_PC                     *((volatile unsigned int*)(0x426661B0UL))
+#define bFM3_GPIO_PDIR3_PD                     *((volatile unsigned int*)(0x426661B4UL))
+#define bFM3_GPIO_PDIR3_PE                     *((volatile unsigned int*)(0x426661B8UL))
+#define bFM3_GPIO_PDIR3_PF                     *((volatile unsigned int*)(0x426661BCUL))
+#define bFM3_GPIO_PDIR4_P0                     *((volatile unsigned int*)(0x42666200UL))
+#define bFM3_GPIO_PDIR4_P1                     *((volatile unsigned int*)(0x42666204UL))
+#define bFM3_GPIO_PDIR4_P2                     *((volatile unsigned int*)(0x42666208UL))
+#define bFM3_GPIO_PDIR4_P3                     *((volatile unsigned int*)(0x4266620CUL))
+#define bFM3_GPIO_PDIR4_P4                     *((volatile unsigned int*)(0x42666210UL))
+#define bFM3_GPIO_PDIR4_P5                     *((volatile unsigned int*)(0x42666214UL))
+#define bFM3_GPIO_PDIR4_P6                     *((volatile unsigned int*)(0x42666218UL))
+#define bFM3_GPIO_PDIR4_P7                     *((volatile unsigned int*)(0x4266621CUL))
+#define bFM3_GPIO_PDIR4_P8                     *((volatile unsigned int*)(0x42666220UL))
+#define bFM3_GPIO_PDIR4_P9                     *((volatile unsigned int*)(0x42666224UL))
+#define bFM3_GPIO_PDIR4_PA                     *((volatile unsigned int*)(0x42666228UL))
+#define bFM3_GPIO_PDIR4_PB                     *((volatile unsigned int*)(0x4266622CUL))
+#define bFM3_GPIO_PDIR4_PC                     *((volatile unsigned int*)(0x42666230UL))
+#define bFM3_GPIO_PDIR4_PD                     *((volatile unsigned int*)(0x42666234UL))
+#define bFM3_GPIO_PDIR4_PE                     *((volatile unsigned int*)(0x42666238UL))
+#define bFM3_GPIO_PDIR5_P0                     *((volatile unsigned int*)(0x42666280UL))
+#define bFM3_GPIO_PDIR5_P1                     *((volatile unsigned int*)(0x42666284UL))
+#define bFM3_GPIO_PDIR5_P2                     *((volatile unsigned int*)(0x42666288UL))
+#define bFM3_GPIO_PDIR5_P3                     *((volatile unsigned int*)(0x4266628CUL))
+#define bFM3_GPIO_PDIR5_P4                     *((volatile unsigned int*)(0x42666290UL))
+#define bFM3_GPIO_PDIR5_P5                     *((volatile unsigned int*)(0x42666294UL))
+#define bFM3_GPIO_PDIR5_P6                     *((volatile unsigned int*)(0x42666298UL))
+#define bFM3_GPIO_PDIR5_P7                     *((volatile unsigned int*)(0x4266629CUL))
+#define bFM3_GPIO_PDIR5_P8                     *((volatile unsigned int*)(0x426662A0UL))
+#define bFM3_GPIO_PDIR5_P9                     *((volatile unsigned int*)(0x426662A4UL))
+#define bFM3_GPIO_PDIR5_PA                     *((volatile unsigned int*)(0x426662A8UL))
+#define bFM3_GPIO_PDIR5_PB                     *((volatile unsigned int*)(0x426662ACUL))
+#define bFM3_GPIO_PDIR6_P0                     *((volatile unsigned int*)(0x42666300UL))
+#define bFM3_GPIO_PDIR6_P1                     *((volatile unsigned int*)(0x42666304UL))
+#define bFM3_GPIO_PDIR6_P2                     *((volatile unsigned int*)(0x42666308UL))
+#define bFM3_GPIO_PDIR7_P0                     *((volatile unsigned int*)(0x42666380UL))
+#define bFM3_GPIO_PDIR7_P1                     *((volatile unsigned int*)(0x42666384UL))
+#define bFM3_GPIO_PDIR7_P2                     *((volatile unsigned int*)(0x42666388UL))
+#define bFM3_GPIO_PDIR7_P3                     *((volatile unsigned int*)(0x4266638CUL))
+#define bFM3_GPIO_PDIR7_P4                     *((volatile unsigned int*)(0x42666390UL))
+#define bFM3_GPIO_PDIR7_P5                     *((volatile unsigned int*)(0x42666394UL))
+#define bFM3_GPIO_PDIR7_P6                     *((volatile unsigned int*)(0x42666398UL))
+#define bFM3_GPIO_PDIR7_P7                     *((volatile unsigned int*)(0x4266639CUL))
+#define bFM3_GPIO_PDIR7_P8                     *((volatile unsigned int*)(0x426663A0UL))
+#define bFM3_GPIO_PDIR7_P9                     *((volatile unsigned int*)(0x426663A4UL))
+#define bFM3_GPIO_PDIR7_PA                     *((volatile unsigned int*)(0x426663A8UL))
+#define bFM3_GPIO_PDIR8_P0                     *((volatile unsigned int*)(0x42666400UL))
+#define bFM3_GPIO_PDIR8_P1                     *((volatile unsigned int*)(0x42666404UL))
+#define bFM3_GPIO_PDIR8_P2                     *((volatile unsigned int*)(0x42666408UL))
+#define bFM3_GPIO_PDIR8_P3                     *((volatile unsigned int*)(0x4266640CUL))
+#define bFM3_GPIO_PDIRA_P0                     *((volatile unsigned int*)(0x42666500UL))
+#define bFM3_GPIO_PDIRA_P1                     *((volatile unsigned int*)(0x42666504UL))
+#define bFM3_GPIO_PDIRA_P2                     *((volatile unsigned int*)(0x42666508UL))
+#define bFM3_GPIO_PDIRA_P3                     *((volatile unsigned int*)(0x4266650CUL))
+#define bFM3_GPIO_PDIRA_P4                     *((volatile unsigned int*)(0x42666510UL))
+#define bFM3_GPIO_PDIRA_P5                     *((volatile unsigned int*)(0x42666514UL))
+#define bFM3_GPIO_PDIRC_P0                     *((volatile unsigned int*)(0x42666600UL))
+#define bFM3_GPIO_PDIRC_P1                     *((volatile unsigned int*)(0x42666604UL))
+#define bFM3_GPIO_PDIRC_P2                     *((volatile unsigned int*)(0x42666608UL))
+#define bFM3_GPIO_PDIRC_P3                     *((volatile unsigned int*)(0x4266660CUL))
+#define bFM3_GPIO_PDIRC_P4                     *((volatile unsigned int*)(0x42666610UL))
+#define bFM3_GPIO_PDIRC_P5                     *((volatile unsigned int*)(0x42666614UL))
+#define bFM3_GPIO_PDIRC_P6                     *((volatile unsigned int*)(0x42666618UL))
+#define bFM3_GPIO_PDIRC_P7                     *((volatile unsigned int*)(0x4266661CUL))
+#define bFM3_GPIO_PDIRC_P8                     *((volatile unsigned int*)(0x42666620UL))
+#define bFM3_GPIO_PDIRC_P9                     *((volatile unsigned int*)(0x42666624UL))
+#define bFM3_GPIO_PDIRC_PA                     *((volatile unsigned int*)(0x42666628UL))
+#define bFM3_GPIO_PDIRC_PB                     *((volatile unsigned int*)(0x4266662CUL))
+#define bFM3_GPIO_PDIRC_PC                     *((volatile unsigned int*)(0x42666630UL))
+#define bFM3_GPIO_PDIRC_PD                     *((volatile unsigned int*)(0x42666634UL))
+#define bFM3_GPIO_PDIRC_PE                     *((volatile unsigned int*)(0x42666638UL))
+#define bFM3_GPIO_PDIRC_PF                     *((volatile unsigned int*)(0x4266663CUL))
+#define bFM3_GPIO_PDIRD_P0                     *((volatile unsigned int*)(0x42666680UL))
+#define bFM3_GPIO_PDIRD_P1                     *((volatile unsigned int*)(0x42666684UL))
+#define bFM3_GPIO_PDIRD_P2                     *((volatile unsigned int*)(0x42666688UL))
+#define bFM3_GPIO_PDIRD_P3                     *((volatile unsigned int*)(0x4266668CUL))
+#define bFM3_GPIO_PDIRE_P0                     *((volatile unsigned int*)(0x42666700UL))
+#define bFM3_GPIO_PDIRE_P2                     *((volatile unsigned int*)(0x42666708UL))
+#define bFM3_GPIO_PDIRE_P3                     *((volatile unsigned int*)(0x4266670CUL))
+#define bFM3_GPIO_PDIRF_P5                     *((volatile unsigned int*)(0x42666794UL))
+#define bFM3_GPIO_PDIRF_P6                     *((volatile unsigned int*)(0x42666798UL))
+#define bFM3_GPIO_PDOR0_P0                     *((volatile unsigned int*)(0x42668000UL))
+#define bFM3_GPIO_PDOR0_P1                     *((volatile unsigned int*)(0x42668004UL))
+#define bFM3_GPIO_PDOR0_P2                     *((volatile unsigned int*)(0x42668008UL))
+#define bFM3_GPIO_PDOR0_P3                     *((volatile unsigned int*)(0x4266800CUL))
+#define bFM3_GPIO_PDOR0_P4                     *((volatile unsigned int*)(0x42668010UL))
+#define bFM3_GPIO_PDOR0_P5                     *((volatile unsigned int*)(0x42668014UL))
+#define bFM3_GPIO_PDOR0_P6                     *((volatile unsigned int*)(0x42668018UL))
+#define bFM3_GPIO_PDOR0_P7                     *((volatile unsigned int*)(0x4266801CUL))
+#define bFM3_GPIO_PDOR0_P8                     *((volatile unsigned int*)(0x42668020UL))
+#define bFM3_GPIO_PDOR0_P9                     *((volatile unsigned int*)(0x42668024UL))
+#define bFM3_GPIO_PDOR1_P0                     *((volatile unsigned int*)(0x42668080UL))
+#define bFM3_GPIO_PDOR1_P1                     *((volatile unsigned int*)(0x42668084UL))
+#define bFM3_GPIO_PDOR1_P2                     *((volatile unsigned int*)(0x42668088UL))
+#define bFM3_GPIO_PDOR1_P3                     *((volatile unsigned int*)(0x4266808CUL))
+#define bFM3_GPIO_PDOR1_P4                     *((volatile unsigned int*)(0x42668090UL))
+#define bFM3_GPIO_PDOR1_P5                     *((volatile unsigned int*)(0x42668094UL))
+#define bFM3_GPIO_PDOR1_P6                     *((volatile unsigned int*)(0x42668098UL))
+#define bFM3_GPIO_PDOR1_P7                     *((volatile unsigned int*)(0x4266809CUL))
+#define bFM3_GPIO_PDOR1_P8                     *((volatile unsigned int*)(0x426680A0UL))
+#define bFM3_GPIO_PDOR1_P9                     *((volatile unsigned int*)(0x426680A4UL))
+#define bFM3_GPIO_PDOR1_PA                     *((volatile unsigned int*)(0x426680A8UL))
+#define bFM3_GPIO_PDOR1_PB                     *((volatile unsigned int*)(0x426680ACUL))
+#define bFM3_GPIO_PDOR1_PC                     *((volatile unsigned int*)(0x426680B0UL))
+#define bFM3_GPIO_PDOR1_PD                     *((volatile unsigned int*)(0x426680B4UL))
+#define bFM3_GPIO_PDOR1_PE                     *((volatile unsigned int*)(0x426680B8UL))
+#define bFM3_GPIO_PDOR1_PF                     *((volatile unsigned int*)(0x426680BCUL))
+#define bFM3_GPIO_PDOR2_P0                     *((volatile unsigned int*)(0x42668100UL))
+#define bFM3_GPIO_PDOR2_P1                     *((volatile unsigned int*)(0x42668104UL))
+#define bFM3_GPIO_PDOR2_P2                     *((volatile unsigned int*)(0x42668108UL))
+#define bFM3_GPIO_PDOR2_P3                     *((volatile unsigned int*)(0x4266810CUL))
+#define bFM3_GPIO_PDOR2_P4                     *((volatile unsigned int*)(0x42668110UL))
+#define bFM3_GPIO_PDOR2_P5                     *((volatile unsigned int*)(0x42668114UL))
+#define bFM3_GPIO_PDOR2_P6                     *((volatile unsigned int*)(0x42668118UL))
+#define bFM3_GPIO_PDOR2_P7                     *((volatile unsigned int*)(0x4266811CUL))
+#define bFM3_GPIO_PDOR2_P8                     *((volatile unsigned int*)(0x42668120UL))
+#define bFM3_GPIO_PDOR2_P9                     *((volatile unsigned int*)(0x42668124UL))
+#define bFM3_GPIO_PDOR3_P6                     *((volatile unsigned int*)(0x42668198UL))
+#define bFM3_GPIO_PDOR3_P7                     *((volatile unsigned int*)(0x4266819CUL))
+#define bFM3_GPIO_PDOR3_P8                     *((volatile unsigned int*)(0x426681A0UL))
+#define bFM3_GPIO_PDOR3_P9                     *((volatile unsigned int*)(0x426681A4UL))
+#define bFM3_GPIO_PDOR3_PA                     *((volatile unsigned int*)(0x426681A8UL))
+#define bFM3_GPIO_PDOR3_PB                     *((volatile unsigned int*)(0x426681ACUL))
+#define bFM3_GPIO_PDOR3_PC                     *((volatile unsigned int*)(0x426681B0UL))
+#define bFM3_GPIO_PDOR3_PD                     *((volatile unsigned int*)(0x426681B4UL))
+#define bFM3_GPIO_PDOR3_PE                     *((volatile unsigned int*)(0x426681B8UL))
+#define bFM3_GPIO_PDOR3_PF                     *((volatile unsigned int*)(0x426681BCUL))
+#define bFM3_GPIO_PDOR4_P0                     *((volatile unsigned int*)(0x42668200UL))
+#define bFM3_GPIO_PDOR4_P1                     *((volatile unsigned int*)(0x42668204UL))
+#define bFM3_GPIO_PDOR4_P2                     *((volatile unsigned int*)(0x42668208UL))
+#define bFM3_GPIO_PDOR4_P3                     *((volatile unsigned int*)(0x4266820CUL))
+#define bFM3_GPIO_PDOR4_P4                     *((volatile unsigned int*)(0x42668210UL))
+#define bFM3_GPIO_PDOR4_P5                     *((volatile unsigned int*)(0x42668214UL))
+#define bFM3_GPIO_PDOR4_P6                     *((volatile unsigned int*)(0x42668218UL))
+#define bFM3_GPIO_PDOR4_P7                     *((volatile unsigned int*)(0x4266821CUL))
+#define bFM3_GPIO_PDOR4_P8                     *((volatile unsigned int*)(0x42668220UL))
+#define bFM3_GPIO_PDOR4_P9                     *((volatile unsigned int*)(0x42668224UL))
+#define bFM3_GPIO_PDOR4_PA                     *((volatile unsigned int*)(0x42668228UL))
+#define bFM3_GPIO_PDOR4_PB                     *((volatile unsigned int*)(0x4266822CUL))
+#define bFM3_GPIO_PDOR4_PC                     *((volatile unsigned int*)(0x42668230UL))
+#define bFM3_GPIO_PDOR4_PD                     *((volatile unsigned int*)(0x42668234UL))
+#define bFM3_GPIO_PDOR4_PE                     *((volatile unsigned int*)(0x42668238UL))
+#define bFM3_GPIO_PDOR5_P0                     *((volatile unsigned int*)(0x42668280UL))
+#define bFM3_GPIO_PDOR5_P1                     *((volatile unsigned int*)(0x42668284UL))
+#define bFM3_GPIO_PDOR5_P2                     *((volatile unsigned int*)(0x42668288UL))
+#define bFM3_GPIO_PDOR5_P3                     *((volatile unsigned int*)(0x4266828CUL))
+#define bFM3_GPIO_PDOR5_P4                     *((volatile unsigned int*)(0x42668290UL))
+#define bFM3_GPIO_PDOR5_P5                     *((volatile unsigned int*)(0x42668294UL))
+#define bFM3_GPIO_PDOR5_P6                     *((volatile unsigned int*)(0x42668298UL))
+#define bFM3_GPIO_PDOR5_P7                     *((volatile unsigned int*)(0x4266829CUL))
+#define bFM3_GPIO_PDOR5_P8                     *((volatile unsigned int*)(0x426682A0UL))
+#define bFM3_GPIO_PDOR5_P9                     *((volatile unsigned int*)(0x426682A4UL))
+#define bFM3_GPIO_PDOR5_PA                     *((volatile unsigned int*)(0x426682A8UL))
+#define bFM3_GPIO_PDOR5_PB                     *((volatile unsigned int*)(0x426682ACUL))
+#define bFM3_GPIO_PDOR6_P0                     *((volatile unsigned int*)(0x42668300UL))
+#define bFM3_GPIO_PDOR6_P1                     *((volatile unsigned int*)(0x42668304UL))
+#define bFM3_GPIO_PDOR6_P2                     *((volatile unsigned int*)(0x42668308UL))
+#define bFM3_GPIO_PDOR7_P0                     *((volatile unsigned int*)(0x42668380UL))
+#define bFM3_GPIO_PDOR7_P1                     *((volatile unsigned int*)(0x42668384UL))
+#define bFM3_GPIO_PDOR7_P2                     *((volatile unsigned int*)(0x42668388UL))
+#define bFM3_GPIO_PDOR7_P3                     *((volatile unsigned int*)(0x4266838CUL))
+#define bFM3_GPIO_PDOR7_P4                     *((volatile unsigned int*)(0x42668390UL))
+#define bFM3_GPIO_PDOR7_P5                     *((volatile unsigned int*)(0x42668394UL))
+#define bFM3_GPIO_PDOR7_P6                     *((volatile unsigned int*)(0x42668398UL))
+#define bFM3_GPIO_PDOR7_P7                     *((volatile unsigned int*)(0x4266839CUL))
+#define bFM3_GPIO_PDOR7_P8                     *((volatile unsigned int*)(0x426683A0UL))
+#define bFM3_GPIO_PDOR7_P9                     *((volatile unsigned int*)(0x426683A4UL))
+#define bFM3_GPIO_PDOR7_PA                     *((volatile unsigned int*)(0x426683A8UL))
+#define bFM3_GPIO_PDOR8_P0                     *((volatile unsigned int*)(0x42668400UL))
+#define bFM3_GPIO_PDOR8_P1                     *((volatile unsigned int*)(0x42668404UL))
+#define bFM3_GPIO_PDOR8_P2                     *((volatile unsigned int*)(0x42668408UL))
+#define bFM3_GPIO_PDOR8_P3                     *((volatile unsigned int*)(0x4266840CUL))
+#define bFM3_GPIO_PDORA_P0                     *((volatile unsigned int*)(0x42668500UL))
+#define bFM3_GPIO_PDORA_P1                     *((volatile unsigned int*)(0x42668504UL))
+#define bFM3_GPIO_PDORA_P2                     *((volatile unsigned int*)(0x42668508UL))
+#define bFM3_GPIO_PDORA_P3                     *((volatile unsigned int*)(0x4266850CUL))
+#define bFM3_GPIO_PDORA_P4                     *((volatile unsigned int*)(0x42668510UL))
+#define bFM3_GPIO_PDORA_P5                     *((volatile unsigned int*)(0x42668514UL))
+#define bFM3_GPIO_PDORC_P0                     *((volatile unsigned int*)(0x42668600UL))
+#define bFM3_GPIO_PDORC_P1                     *((volatile unsigned int*)(0x42668604UL))
+#define bFM3_GPIO_PDORC_P2                     *((volatile unsigned int*)(0x42668608UL))
+#define bFM3_GPIO_PDORC_P3                     *((volatile unsigned int*)(0x4266860CUL))
+#define bFM3_GPIO_PDORC_P4                     *((volatile unsigned int*)(0x42668610UL))
+#define bFM3_GPIO_PDORC_P5                     *((volatile unsigned int*)(0x42668614UL))
+#define bFM3_GPIO_PDORC_P6                     *((volatile unsigned int*)(0x42668618UL))
+#define bFM3_GPIO_PDORC_P7                     *((volatile unsigned int*)(0x4266861CUL))
+#define bFM3_GPIO_PDORC_P8                     *((volatile unsigned int*)(0x42668620UL))
+#define bFM3_GPIO_PDORC_P9                     *((volatile unsigned int*)(0x42668624UL))
+#define bFM3_GPIO_PDORC_PA                     *((volatile unsigned int*)(0x42668628UL))
+#define bFM3_GPIO_PDORC_PB                     *((volatile unsigned int*)(0x4266862CUL))
+#define bFM3_GPIO_PDORC_PC                     *((volatile unsigned int*)(0x42668630UL))
+#define bFM3_GPIO_PDORC_PD                     *((volatile unsigned int*)(0x42668634UL))
+#define bFM3_GPIO_PDORC_PE                     *((volatile unsigned int*)(0x42668638UL))
+#define bFM3_GPIO_PDORC_PF                     *((volatile unsigned int*)(0x4266863CUL))
+#define bFM3_GPIO_PDORD_P0                     *((volatile unsigned int*)(0x42668680UL))
+#define bFM3_GPIO_PDORD_P1                     *((volatile unsigned int*)(0x42668684UL))
+#define bFM3_GPIO_PDORD_P2                     *((volatile unsigned int*)(0x42668688UL))
+#define bFM3_GPIO_PDORD_P3                     *((volatile unsigned int*)(0x4266868CUL))
+#define bFM3_GPIO_PDORE_P0                     *((volatile unsigned int*)(0x42668700UL))
+#define bFM3_GPIO_PDORE_P2                     *((volatile unsigned int*)(0x42668708UL))
+#define bFM3_GPIO_PDORE_P3                     *((volatile unsigned int*)(0x4266870CUL))
+#define bFM3_GPIO_PDORF_P5                     *((volatile unsigned int*)(0x42668794UL))
+#define bFM3_GPIO_PDORF_P6                     *((volatile unsigned int*)(0x42668798UL))
+#define bFM3_GPIO_ADE_AN0                      *((volatile unsigned int*)(0x4266A000UL))
+#define bFM3_GPIO_ADE_AN1                      *((volatile unsigned int*)(0x4266A004UL))
+#define bFM3_GPIO_ADE_AN2                      *((volatile unsigned int*)(0x4266A008UL))
+#define bFM3_GPIO_ADE_AN3                      *((volatile unsigned int*)(0x4266A00CUL))
+#define bFM3_GPIO_ADE_AN4                      *((volatile unsigned int*)(0x4266A010UL))
+#define bFM3_GPIO_ADE_AN5                      *((volatile unsigned int*)(0x4266A014UL))
+#define bFM3_GPIO_ADE_AN6                      *((volatile unsigned int*)(0x4266A018UL))
+#define bFM3_GPIO_ADE_AN7                      *((volatile unsigned int*)(0x4266A01CUL))
+#define bFM3_GPIO_ADE_AN8                      *((volatile unsigned int*)(0x4266A020UL))
+#define bFM3_GPIO_ADE_AN9                      *((volatile unsigned int*)(0x4266A024UL))
+#define bFM3_GPIO_ADE_AN10                     *((volatile unsigned int*)(0x4266A028UL))
+#define bFM3_GPIO_ADE_AN11                     *((volatile unsigned int*)(0x4266A02CUL))
+#define bFM3_GPIO_ADE_AN12                     *((volatile unsigned int*)(0x4266A030UL))
+#define bFM3_GPIO_ADE_AN13                     *((volatile unsigned int*)(0x4266A034UL))
+#define bFM3_GPIO_ADE_AN14                     *((volatile unsigned int*)(0x4266A038UL))
+#define bFM3_GPIO_ADE_AN15                     *((volatile unsigned int*)(0x4266A03CUL))
+#define bFM3_GPIO_ADE_AN24                     *((volatile unsigned int*)(0x4266A060UL))
+#define bFM3_GPIO_ADE_AN25                     *((volatile unsigned int*)(0x4266A064UL))
+#define bFM3_GPIO_ADE_AN26                     *((volatile unsigned int*)(0x4266A068UL))
+#define bFM3_GPIO_ADE_AN27                     *((volatile unsigned int*)(0x4266A06CUL))
+#define bFM3_GPIO_ADE_AN28                     *((volatile unsigned int*)(0x4266A070UL))
+#define bFM3_GPIO_ADE_AN29                     *((volatile unsigned int*)(0x4266A074UL))
+#define bFM3_GPIO_ADE_AN30                     *((volatile unsigned int*)(0x4266A078UL))
+#define bFM3_GPIO_ADE_AN31                     *((volatile unsigned int*)(0x4266A07CUL))
+#define bFM3_GPIO_SPSR_SUBXC                   *((volatile unsigned int*)(0x4266B000UL))
+#define bFM3_GPIO_SPSR_MAINXC                  *((volatile unsigned int*)(0x4266B008UL))
+#define bFM3_GPIO_SPSR_USB0C                   *((volatile unsigned int*)(0x4266B010UL))
+#define bFM3_GPIO_SPSR_USB1C                   *((volatile unsigned int*)(0x4266B014UL))
+#define bFM3_GPIO_EPFR00_NMIS                  *((volatile unsigned int*)(0x4266C000UL))
+#define bFM3_GPIO_EPFR00_CROUTE0               *((volatile unsigned int*)(0x4266C004UL))
+#define bFM3_GPIO_EPFR00_CROUTE1               *((volatile unsigned int*)(0x4266C008UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE0              *((volatile unsigned int*)(0x4266C018UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE1              *((volatile unsigned int*)(0x4266C01CUL))
+#define bFM3_GPIO_EPFR00_USBP0E                *((volatile unsigned int*)(0x4266C024UL))
+#define bFM3_GPIO_EPFR00_USBP1E                *((volatile unsigned int*)(0x4266C034UL))
+#define bFM3_GPIO_EPFR00_JTAGEN0B              *((volatile unsigned int*)(0x4266C040UL))
+#define bFM3_GPIO_EPFR00_JTAGEN1S              *((volatile unsigned int*)(0x4266C044UL))
+#define bFM3_GPIO_EPFR00_TRC0E                 *((volatile unsigned int*)(0x4266C060UL))
+#define bFM3_GPIO_EPFR00_TRC1E                 *((volatile unsigned int*)(0x4266C064UL))
+#define bFM3_GPIO_EPFR01_RTO00E0               *((volatile unsigned int*)(0x4266C080UL))
+#define bFM3_GPIO_EPFR01_RTO00E1               *((volatile unsigned int*)(0x4266C084UL))
+#define bFM3_GPIO_EPFR01_RTO01E0               *((volatile unsigned int*)(0x4266C088UL))
+#define bFM3_GPIO_EPFR01_RTO01E1               *((volatile unsigned int*)(0x4266C08CUL))
+#define bFM3_GPIO_EPFR01_RTO02E0               *((volatile unsigned int*)(0x4266C090UL))
+#define bFM3_GPIO_EPFR01_RTO02E1               *((volatile unsigned int*)(0x4266C094UL))
+#define bFM3_GPIO_EPFR01_RTO03E0               *((volatile unsigned int*)(0x4266C098UL))
+#define bFM3_GPIO_EPFR01_RTO03E1               *((volatile unsigned int*)(0x4266C09CUL))
+#define bFM3_GPIO_EPFR01_RTO04E0               *((volatile unsigned int*)(0x4266C0A0UL))
+#define bFM3_GPIO_EPFR01_RTO04E1               *((volatile unsigned int*)(0x4266C0A4UL))
+#define bFM3_GPIO_EPFR01_RTO05E0               *((volatile unsigned int*)(0x4266C0A8UL))
+#define bFM3_GPIO_EPFR01_RTO05E1               *((volatile unsigned int*)(0x4266C0ACUL))
+#define bFM3_GPIO_EPFR01_DTTI0C                *((volatile unsigned int*)(0x4266C0B0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S0               *((volatile unsigned int*)(0x4266C0C0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S1               *((volatile unsigned int*)(0x4266C0C4UL))
+#define bFM3_GPIO_EPFR01_FRCK0S0               *((volatile unsigned int*)(0x4266C0C8UL))
+#define bFM3_GPIO_EPFR01_FRCK0S1               *((volatile unsigned int*)(0x4266C0CCUL))
+#define bFM3_GPIO_EPFR01_IC00S0                *((volatile unsigned int*)(0x4266C0D0UL))
+#define bFM3_GPIO_EPFR01_IC00S1                *((volatile unsigned int*)(0x4266C0D4UL))
+#define bFM3_GPIO_EPFR01_IC00S2                *((volatile unsigned int*)(0x4266C0D8UL))
+#define bFM3_GPIO_EPFR01_IC01S0                *((volatile unsigned int*)(0x4266C0DCUL))
+#define bFM3_GPIO_EPFR01_IC01S1                *((volatile unsigned int*)(0x4266C0E0UL))
+#define bFM3_GPIO_EPFR01_IC01S2                *((volatile unsigned int*)(0x4266C0E4UL))
+#define bFM3_GPIO_EPFR01_IC02S0                *((volatile unsigned int*)(0x4266C0E8UL))
+#define bFM3_GPIO_EPFR01_IC02S1                *((volatile unsigned int*)(0x4266C0ECUL))
+#define bFM3_GPIO_EPFR01_IC02S2                *((volatile unsigned int*)(0x4266C0F0UL))
+#define bFM3_GPIO_EPFR01_IC03S0                *((volatile unsigned int*)(0x4266C0F4UL))
+#define bFM3_GPIO_EPFR01_IC03S1                *((volatile unsigned int*)(0x4266C0F8UL))
+#define bFM3_GPIO_EPFR01_IC03S2                *((volatile unsigned int*)(0x4266C0FCUL))
+#define bFM3_GPIO_EPFR02_RTO10E0               *((volatile unsigned int*)(0x4266C100UL))
+#define bFM3_GPIO_EPFR02_RTO10E1               *((volatile unsigned int*)(0x4266C104UL))
+#define bFM3_GPIO_EPFR02_RTO11E0               *((volatile unsigned int*)(0x4266C108UL))
+#define bFM3_GPIO_EPFR02_RTO11E1               *((volatile unsigned int*)(0x4266C10CUL))
+#define bFM3_GPIO_EPFR02_RTO12E0               *((volatile unsigned int*)(0x4266C110UL))
+#define bFM3_GPIO_EPFR02_RTO12E1               *((volatile unsigned int*)(0x4266C114UL))
+#define bFM3_GPIO_EPFR02_RTO13E0               *((volatile unsigned int*)(0x4266C118UL))
+#define bFM3_GPIO_EPFR02_RTO13E1               *((volatile unsigned int*)(0x4266C11CUL))
+#define bFM3_GPIO_EPFR02_RTO14E0               *((volatile unsigned int*)(0x4266C120UL))
+#define bFM3_GPIO_EPFR02_RTO14E1               *((volatile unsigned int*)(0x4266C124UL))
+#define bFM3_GPIO_EPFR02_RTO15E0               *((volatile unsigned int*)(0x4266C128UL))
+#define bFM3_GPIO_EPFR02_RTO15E1               *((volatile unsigned int*)(0x4266C12CUL))
+#define bFM3_GPIO_EPFR02_DTTI1C                *((volatile unsigned int*)(0x4266C130UL))
+#define bFM3_GPIO_EPFR02_DTTI1S0               *((volatile unsigned int*)(0x4266C140UL))
+#define bFM3_GPIO_EPFR02_DTTI1S1               *((volatile unsigned int*)(0x4266C144UL))
+#define bFM3_GPIO_EPFR02_FRCK1S0               *((volatile unsigned int*)(0x4266C148UL))
+#define bFM3_GPIO_EPFR02_FRCK1S1               *((volatile unsigned int*)(0x4266C14CUL))
+#define bFM3_GPIO_EPFR02_IC10S0                *((volatile unsigned int*)(0x4266C150UL))
+#define bFM3_GPIO_EPFR02_IC10S1                *((volatile unsigned int*)(0x4266C154UL))
+#define bFM3_GPIO_EPFR02_IC10S2                *((volatile unsigned int*)(0x4266C158UL))
+#define bFM3_GPIO_EPFR02_IC11S0                *((volatile unsigned int*)(0x4266C15CUL))
+#define bFM3_GPIO_EPFR02_IC11S1                *((volatile unsigned int*)(0x4266C160UL))
+#define bFM3_GPIO_EPFR02_IC11S2                *((volatile unsigned int*)(0x4266C164UL))
+#define bFM3_GPIO_EPFR02_IC12S0                *((volatile unsigned int*)(0x4266C168UL))
+#define bFM3_GPIO_EPFR02_IC12S1                *((volatile unsigned int*)(0x4266C16CUL))
+#define bFM3_GPIO_EPFR02_IC12S2                *((volatile unsigned int*)(0x4266C170UL))
+#define bFM3_GPIO_EPFR02_IC13S0                *((volatile unsigned int*)(0x4266C174UL))
+#define bFM3_GPIO_EPFR02_IC13S1                *((volatile unsigned int*)(0x4266C178UL))
+#define bFM3_GPIO_EPFR02_IC13S2                *((volatile unsigned int*)(0x4266C17CUL))
+#define bFM3_GPIO_EPFR03_RTO20E0               *((volatile unsigned int*)(0x4266C180UL))
+#define bFM3_GPIO_EPFR03_RTO20E1               *((volatile unsigned int*)(0x4266C184UL))
+#define bFM3_GPIO_EPFR03_RTO21E0               *((volatile unsigned int*)(0x4266C188UL))
+#define bFM3_GPIO_EPFR03_RTO21E1               *((volatile unsigned int*)(0x4266C18CUL))
+#define bFM3_GPIO_EPFR03_RTO22E0               *((volatile unsigned int*)(0x4266C190UL))
+#define bFM3_GPIO_EPFR03_RTO22E1               *((volatile unsigned int*)(0x4266C194UL))
+#define bFM3_GPIO_EPFR03_RTO23E0               *((volatile unsigned int*)(0x4266C198UL))
+#define bFM3_GPIO_EPFR03_RTO23E1               *((volatile unsigned int*)(0x4266C19CUL))
+#define bFM3_GPIO_EPFR03_RTO24E0               *((volatile unsigned int*)(0x4266C1A0UL))
+#define bFM3_GPIO_EPFR03_RTO24E1               *((volatile unsigned int*)(0x4266C1A4UL))
+#define bFM3_GPIO_EPFR03_RTO25E0               *((volatile unsigned int*)(0x4266C1A8UL))
+#define bFM3_GPIO_EPFR03_RTO25E1               *((volatile unsigned int*)(0x4266C1ACUL))
+#define bFM3_GPIO_EPFR03_DTTI2C                *((volatile unsigned int*)(0x4266C1B0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S0               *((volatile unsigned int*)(0x4266C1C0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S1               *((volatile unsigned int*)(0x4266C1C4UL))
+#define bFM3_GPIO_EPFR03_FRCK2S0               *((volatile unsigned int*)(0x4266C1C8UL))
+#define bFM3_GPIO_EPFR03_FRCK2S1               *((volatile unsigned int*)(0x4266C1CCUL))
+#define bFM3_GPIO_EPFR03_IC20S0                *((volatile unsigned int*)(0x4266C1D0UL))
+#define bFM3_GPIO_EPFR03_IC20S1                *((volatile unsigned int*)(0x4266C1D4UL))
+#define bFM3_GPIO_EPFR03_IC20S2                *((volatile unsigned int*)(0x4266C1D8UL))
+#define bFM3_GPIO_EPFR03_IC21S0                *((volatile unsigned int*)(0x4266C1DCUL))
+#define bFM3_GPIO_EPFR03_IC21S1                *((volatile unsigned int*)(0x4266C1E0UL))
+#define bFM3_GPIO_EPFR03_IC21S2                *((volatile unsigned int*)(0x4266C1E4UL))
+#define bFM3_GPIO_EPFR03_IC22S0                *((volatile unsigned int*)(0x4266C1E8UL))
+#define bFM3_GPIO_EPFR03_IC22S1                *((volatile unsigned int*)(0x4266C1ECUL))
+#define bFM3_GPIO_EPFR03_IC22S2                *((volatile unsigned int*)(0x4266C1F0UL))
+#define bFM3_GPIO_EPFR03_IC23S0                *((volatile unsigned int*)(0x4266C1F4UL))
+#define bFM3_GPIO_EPFR03_IC23S1                *((volatile unsigned int*)(0x4266C1F8UL))
+#define bFM3_GPIO_EPFR03_IC23S2                *((volatile unsigned int*)(0x4266C1FCUL))
+#define bFM3_GPIO_EPFR04_TIOA0E0               *((volatile unsigned int*)(0x4266C208UL))
+#define bFM3_GPIO_EPFR04_TIOA0E1               *((volatile unsigned int*)(0x4266C20CUL))
+#define bFM3_GPIO_EPFR04_TIOB0S0               *((volatile unsigned int*)(0x4266C210UL))
+#define bFM3_GPIO_EPFR04_TIOB0S1               *((volatile unsigned int*)(0x4266C214UL))
+#define bFM3_GPIO_EPFR04_TIOA1S0               *((volatile unsigned int*)(0x4266C220UL))
+#define bFM3_GPIO_EPFR04_TIOA1S1               *((volatile unsigned int*)(0x4266C224UL))
+#define bFM3_GPIO_EPFR04_TIOA1E0               *((volatile unsigned int*)(0x4266C228UL))
+#define bFM3_GPIO_EPFR04_TIOA1E1               *((volatile unsigned int*)(0x4266C22CUL))
+#define bFM3_GPIO_EPFR04_TIOB1S0               *((volatile unsigned int*)(0x4266C230UL))
+#define bFM3_GPIO_EPFR04_TIOB1S1               *((volatile unsigned int*)(0x4266C234UL))
+#define bFM3_GPIO_EPFR04_TIOA2E0               *((volatile unsigned int*)(0x4266C248UL))
+#define bFM3_GPIO_EPFR04_TIOA2E1               *((volatile unsigned int*)(0x4266C24CUL))
+#define bFM3_GPIO_EPFR04_TIOB2S0               *((volatile unsigned int*)(0x4266C250UL))
+#define bFM3_GPIO_EPFR04_TIOB2S1               *((volatile unsigned int*)(0x4266C254UL))
+#define bFM3_GPIO_EPFR04_TIOA3S0               *((volatile unsigned int*)(0x4266C260UL))
+#define bFM3_GPIO_EPFR04_TIOA3S1               *((volatile unsigned int*)(0x4266C264UL))
+#define bFM3_GPIO_EPFR04_TIOA3E0               *((volatile unsigned int*)(0x4266C268UL))
+#define bFM3_GPIO_EPFR04_TIOA3E1               *((volatile unsigned int*)(0x4266C26CUL))
+#define bFM3_GPIO_EPFR04_TIOB3S0               *((volatile unsigned int*)(0x4266C270UL))
+#define bFM3_GPIO_EPFR04_TIOB3S1               *((volatile unsigned int*)(0x4266C274UL))
+#define bFM3_GPIO_EPFR05_TIOA4E0               *((volatile unsigned int*)(0x4266C288UL))
+#define bFM3_GPIO_EPFR05_TIOA4E1               *((volatile unsigned int*)(0x4266C28CUL))
+#define bFM3_GPIO_EPFR05_TIOB4S0               *((volatile unsigned int*)(0x4266C290UL))
+#define bFM3_GPIO_EPFR05_TIOB4S1               *((volatile unsigned int*)(0x4266C294UL))
+#define bFM3_GPIO_EPFR05_TIOA5S0               *((volatile unsigned int*)(0x4266C2A0UL))
+#define bFM3_GPIO_EPFR05_TIOA5S1               *((volatile unsigned int*)(0x4266C2A4UL))
+#define bFM3_GPIO_EPFR05_TIOA5E0               *((volatile unsigned int*)(0x4266C2A8UL))
+#define bFM3_GPIO_EPFR05_TIOA5E1               *((volatile unsigned int*)(0x4266C2ACUL))
+#define bFM3_GPIO_EPFR05_TIOB5S0               *((volatile unsigned int*)(0x4266C2B0UL))
+#define bFM3_GPIO_EPFR05_TIOB5S1               *((volatile unsigned int*)(0x4266C2B4UL))
+#define bFM3_GPIO_EPFR05_TIOA6E0               *((volatile unsigned int*)(0x4266C2C8UL))
+#define bFM3_GPIO_EPFR05_TIOA6E1               *((volatile unsigned int*)(0x4266C2CCUL))
+#define bFM3_GPIO_EPFR05_TIOB6S0               *((volatile unsigned int*)(0x4266C2D0UL))
+#define bFM3_GPIO_EPFR05_TIOB6S1               *((volatile unsigned int*)(0x4266C2D4UL))
+#define bFM3_GPIO_EPFR05_TIOA7S0               *((volatile unsigned int*)(0x4266C2E0UL))
+#define bFM3_GPIO_EPFR05_TIOA7S1               *((volatile unsigned int*)(0x4266C2E4UL))
+#define bFM3_GPIO_EPFR05_TIOA7E0               *((volatile unsigned int*)(0x4266C2E8UL))
+#define bFM3_GPIO_EPFR05_TIOA7E1               *((volatile unsigned int*)(0x4266C2ECUL))
+#define bFM3_GPIO_EPFR05_TIOB7S0               *((volatile unsigned int*)(0x4266C2F0UL))
+#define bFM3_GPIO_EPFR05_TIOB7S1               *((volatile unsigned int*)(0x4266C2F4UL))
+#define bFM3_GPIO_EPFR06_EINT00S0              *((volatile unsigned int*)(0x4266C300UL))
+#define bFM3_GPIO_EPFR06_EINT00S1              *((volatile unsigned int*)(0x4266C304UL))
+#define bFM3_GPIO_EPFR06_EINT01S0              *((volatile unsigned int*)(0x4266C308UL))
+#define bFM3_GPIO_EPFR06_EINT01S1              *((volatile unsigned int*)(0x4266C30CUL))
+#define bFM3_GPIO_EPFR06_EINT02S0              *((volatile unsigned int*)(0x4266C310UL))
+#define bFM3_GPIO_EPFR06_EINT02S1              *((volatile unsigned int*)(0x4266C314UL))
+#define bFM3_GPIO_EPFR06_EINT03S0              *((volatile unsigned int*)(0x4266C318UL))
+#define bFM3_GPIO_EPFR06_EINT03S1              *((volatile unsigned int*)(0x4266C31CUL))
+#define bFM3_GPIO_EPFR06_EINT04S0              *((volatile unsigned int*)(0x4266C320UL))
+#define bFM3_GPIO_EPFR06_EINT04S1              *((volatile unsigned int*)(0x4266C324UL))
+#define bFM3_GPIO_EPFR06_EINT05S0              *((volatile unsigned int*)(0x4266C328UL))
+#define bFM3_GPIO_EPFR06_EINT05S1              *((volatile unsigned int*)(0x4266C32CUL))
+#define bFM3_GPIO_EPFR06_EINT06S0              *((volatile unsigned int*)(0x4266C330UL))
+#define bFM3_GPIO_EPFR06_EINT06S1              *((volatile unsigned int*)(0x4266C334UL))
+#define bFM3_GPIO_EPFR06_EINT07S0              *((volatile unsigned int*)(0x4266C338UL))
+#define bFM3_GPIO_EPFR06_EINT07S1              *((volatile unsigned int*)(0x4266C33CUL))
+#define bFM3_GPIO_EPFR06_EINT08S0              *((volatile unsigned int*)(0x4266C340UL))
+#define bFM3_GPIO_EPFR06_EINT08S1              *((volatile unsigned int*)(0x4266C344UL))
+#define bFM3_GPIO_EPFR06_EINT09S0              *((volatile unsigned int*)(0x4266C348UL))
+#define bFM3_GPIO_EPFR06_EINT09S1              *((volatile unsigned int*)(0x4266C34CUL))
+#define bFM3_GPIO_EPFR06_EINT10S0              *((volatile unsigned int*)(0x4266C350UL))
+#define bFM3_GPIO_EPFR06_EINT10S1              *((volatile unsigned int*)(0x4266C354UL))
+#define bFM3_GPIO_EPFR06_EINT11S0              *((volatile unsigned int*)(0x4266C358UL))
+#define bFM3_GPIO_EPFR06_EINT11S1              *((volatile unsigned int*)(0x4266C35CUL))
+#define bFM3_GPIO_EPFR06_EINT12S0              *((volatile unsigned int*)(0x4266C360UL))
+#define bFM3_GPIO_EPFR06_EINT12S1              *((volatile unsigned int*)(0x4266C364UL))
+#define bFM3_GPIO_EPFR06_EINT13S0              *((volatile unsigned int*)(0x4266C368UL))
+#define bFM3_GPIO_EPFR06_EINT13S1              *((volatile unsigned int*)(0x4266C36CUL))
+#define bFM3_GPIO_EPFR06_EINT14S0              *((volatile unsigned int*)(0x4266C370UL))
+#define bFM3_GPIO_EPFR06_EINT14S1              *((volatile unsigned int*)(0x4266C374UL))
+#define bFM3_GPIO_EPFR06_EINT15S0              *((volatile unsigned int*)(0x4266C378UL))
+#define bFM3_GPIO_EPFR06_EINT15S1              *((volatile unsigned int*)(0x4266C37CUL))
+#define bFM3_GPIO_EPFR07_SIN0S0                *((volatile unsigned int*)(0x4266C390UL))
+#define bFM3_GPIO_EPFR07_SIN0S1                *((volatile unsigned int*)(0x4266C394UL))
+#define bFM3_GPIO_EPFR07_SOT0B0                *((volatile unsigned int*)(0x4266C398UL))
+#define bFM3_GPIO_EPFR07_SOT0B1                *((volatile unsigned int*)(0x4266C39CUL))
+#define bFM3_GPIO_EPFR07_SCK0B0                *((volatile unsigned int*)(0x4266C3A0UL))
+#define bFM3_GPIO_EPFR07_SCK0B1                *((volatile unsigned int*)(0x4266C3A4UL))
+#define bFM3_GPIO_EPFR07_SIN1S0                *((volatile unsigned int*)(0x4266C3A8UL))
+#define bFM3_GPIO_EPFR07_SIN1S1                *((volatile unsigned int*)(0x4266C3ACUL))
+#define bFM3_GPIO_EPFR07_SOT1B0                *((volatile unsigned int*)(0x4266C3B0UL))
+#define bFM3_GPIO_EPFR07_SOT1B1                *((volatile unsigned int*)(0x4266C3B4UL))
+#define bFM3_GPIO_EPFR07_SCK1B0                *((volatile unsigned int*)(0x4266C3B8UL))
+#define bFM3_GPIO_EPFR07_SCK1B1                *((volatile unsigned int*)(0x4266C3BCUL))
+#define bFM3_GPIO_EPFR07_SIN2S0                *((volatile unsigned int*)(0x4266C3C0UL))
+#define bFM3_GPIO_EPFR07_SIN2S1                *((volatile unsigned int*)(0x4266C3C4UL))
+#define bFM3_GPIO_EPFR07_SOT2B0                *((volatile unsigned int*)(0x4266C3C8UL))
+#define bFM3_GPIO_EPFR07_SOT2B1                *((volatile unsigned int*)(0x4266C3CCUL))
+#define bFM3_GPIO_EPFR07_SCK2B0                *((volatile unsigned int*)(0x4266C3D0UL))
+#define bFM3_GPIO_EPFR07_SCK2B1                *((volatile unsigned int*)(0x4266C3D4UL))
+#define bFM3_GPIO_EPFR07_SIN3S0                *((volatile unsigned int*)(0x4266C3D8UL))
+#define bFM3_GPIO_EPFR07_SIN3S1                *((volatile unsigned int*)(0x4266C3DCUL))
+#define bFM3_GPIO_EPFR07_SOT3B0                *((volatile unsigned int*)(0x4266C3E0UL))
+#define bFM3_GPIO_EPFR07_SOT3B1                *((volatile unsigned int*)(0x4266C3E4UL))
+#define bFM3_GPIO_EPFR07_SCK3B0                *((volatile unsigned int*)(0x4266C3E8UL))
+#define bFM3_GPIO_EPFR07_SCK3B1                *((volatile unsigned int*)(0x4266C3ECUL))
+#define bFM3_GPIO_EPFR08_RTS4E0                *((volatile unsigned int*)(0x4266C400UL))
+#define bFM3_GPIO_EPFR08_RTS4E1                *((volatile unsigned int*)(0x4266C404UL))
+#define bFM3_GPIO_EPFR08_CTS4S0                *((volatile unsigned int*)(0x4266C408UL))
+#define bFM3_GPIO_EPFR08_CTS4S1                *((volatile unsigned int*)(0x4266C40CUL))
+#define bFM3_GPIO_EPFR08_SIN4S0                *((volatile unsigned int*)(0x4266C410UL))
+#define bFM3_GPIO_EPFR08_SIN4S1                *((volatile unsigned int*)(0x4266C414UL))
+#define bFM3_GPIO_EPFR08_SOT4B0                *((volatile unsigned int*)(0x4266C418UL))
+#define bFM3_GPIO_EPFR08_SOT4B1                *((volatile unsigned int*)(0x4266C41CUL))
+#define bFM3_GPIO_EPFR08_SCK4B0                *((volatile unsigned int*)(0x4266C420UL))
+#define bFM3_GPIO_EPFR08_SCK4B1                *((volatile unsigned int*)(0x4266C424UL))
+#define bFM3_GPIO_EPFR08_SIN5S0                *((volatile unsigned int*)(0x4266C428UL))
+#define bFM3_GPIO_EPFR08_SIN5S1                *((volatile unsigned int*)(0x4266C42CUL))
+#define bFM3_GPIO_EPFR08_SOT5B0                *((volatile unsigned int*)(0x4266C430UL))
+#define bFM3_GPIO_EPFR08_SOT5B1                *((volatile unsigned int*)(0x4266C434UL))
+#define bFM3_GPIO_EPFR08_SCK5B0                *((volatile unsigned int*)(0x4266C438UL))
+#define bFM3_GPIO_EPFR08_SCK5B1                *((volatile unsigned int*)(0x4266C43CUL))
+#define bFM3_GPIO_EPFR08_SIN6S0                *((volatile unsigned int*)(0x4266C440UL))
+#define bFM3_GPIO_EPFR08_SIN6S1                *((volatile unsigned int*)(0x4266C444UL))
+#define bFM3_GPIO_EPFR08_SOT6B0                *((volatile unsigned int*)(0x4266C448UL))
+#define bFM3_GPIO_EPFR08_SOT6B1                *((volatile unsigned int*)(0x4266C44CUL))
+#define bFM3_GPIO_EPFR08_SCK6B0                *((volatile unsigned int*)(0x4266C450UL))
+#define bFM3_GPIO_EPFR08_SCK6B1                *((volatile unsigned int*)(0x4266C454UL))
+#define bFM3_GPIO_EPFR08_SIN7S0                *((volatile unsigned int*)(0x4266C458UL))
+#define bFM3_GPIO_EPFR08_SIN7S1                *((volatile unsigned int*)(0x4266C45CUL))
+#define bFM3_GPIO_EPFR08_SOT7B0                *((volatile unsigned int*)(0x4266C460UL))
+#define bFM3_GPIO_EPFR08_SOT7B1                *((volatile unsigned int*)(0x4266C464UL))
+#define bFM3_GPIO_EPFR08_SCK7B0                *((volatile unsigned int*)(0x4266C468UL))
+#define bFM3_GPIO_EPFR08_SCK7B1                *((volatile unsigned int*)(0x4266C46CUL))
+#define bFM3_GPIO_EPFR09_QAIN0S0               *((volatile unsigned int*)(0x4266C480UL))
+#define bFM3_GPIO_EPFR09_QAIN0S1               *((volatile unsigned int*)(0x4266C484UL))
+#define bFM3_GPIO_EPFR09_QBIN0S0               *((volatile unsigned int*)(0x4266C488UL))
+#define bFM3_GPIO_EPFR09_QBIN0S1               *((volatile unsigned int*)(0x4266C48CUL))
+#define bFM3_GPIO_EPFR09_QZIN0S0               *((volatile unsigned int*)(0x4266C490UL))
+#define bFM3_GPIO_EPFR09_QZIN0S1               *((volatile unsigned int*)(0x4266C494UL))
+#define bFM3_GPIO_EPFR09_QAIN1S0               *((volatile unsigned int*)(0x4266C498UL))
+#define bFM3_GPIO_EPFR09_QAIN1S1               *((volatile unsigned int*)(0x4266C49CUL))
+#define bFM3_GPIO_EPFR09_QBIN1S0               *((volatile unsigned int*)(0x4266C4A0UL))
+#define bFM3_GPIO_EPFR09_QBIN1S1               *((volatile unsigned int*)(0x4266C4A4UL))
+#define bFM3_GPIO_EPFR09_QZIN1S0               *((volatile unsigned int*)(0x4266C4A8UL))
+#define bFM3_GPIO_EPFR09_QZIN1S1               *((volatile unsigned int*)(0x4266C4ACUL))
+#define bFM3_GPIO_EPFR09_ADTRG0S0              *((volatile unsigned int*)(0x4266C4B0UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S1              *((volatile unsigned int*)(0x4266C4B4UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S2              *((volatile unsigned int*)(0x4266C4B8UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S3              *((volatile unsigned int*)(0x4266C4BCUL))
+#define bFM3_GPIO_EPFR09_ADTRG1S0              *((volatile unsigned int*)(0x4266C4C0UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S1              *((volatile unsigned int*)(0x4266C4C4UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S2              *((volatile unsigned int*)(0x4266C4C8UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S3              *((volatile unsigned int*)(0x4266C4CCUL))
+#define bFM3_GPIO_EPFR09_ADTRG2S0              *((volatile unsigned int*)(0x4266C4D0UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S1              *((volatile unsigned int*)(0x4266C4D4UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S2              *((volatile unsigned int*)(0x4266C4D8UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S3              *((volatile unsigned int*)(0x4266C4DCUL))
+#define bFM3_GPIO_EPFR10_UEDEFB                *((volatile unsigned int*)(0x4266C500UL))
+#define bFM3_GPIO_EPFR10_UEDTHB                *((volatile unsigned int*)(0x4266C504UL))
+#define bFM3_GPIO_EPFR10_UECLKE                *((volatile unsigned int*)(0x4266C508UL))
+#define bFM3_GPIO_EPFR10_UEWEXE                *((volatile unsigned int*)(0x4266C50CUL))
+#define bFM3_GPIO_EPFR10_UEDQME                *((volatile unsigned int*)(0x4266C510UL))
+#define bFM3_GPIO_EPFR10_UEOEXE                *((volatile unsigned int*)(0x4266C514UL))
+#define bFM3_GPIO_EPFR10_UEFLSE                *((volatile unsigned int*)(0x4266C518UL))
+#define bFM3_GPIO_EPFR10_UECS1E                *((volatile unsigned int*)(0x4266C51CUL))
+#define bFM3_GPIO_EPFR10_UECS2E                *((volatile unsigned int*)(0x4266C520UL))
+#define bFM3_GPIO_EPFR10_UECS3E                *((volatile unsigned int*)(0x4266C524UL))
+#define bFM3_GPIO_EPFR10_UECS4E                *((volatile unsigned int*)(0x4266C528UL))
+#define bFM3_GPIO_EPFR10_UECS5E                *((volatile unsigned int*)(0x4266C52CUL))
+#define bFM3_GPIO_EPFR10_UECS6E                *((volatile unsigned int*)(0x4266C530UL))
+#define bFM3_GPIO_EPFR10_UECS7E                *((volatile unsigned int*)(0x4266C534UL))
+#define bFM3_GPIO_EPFR10_UEAOOE                *((volatile unsigned int*)(0x4266C538UL))
+#define bFM3_GPIO_EPFR10_UEA08E                *((volatile unsigned int*)(0x4266C53CUL))
+#define bFM3_GPIO_EPFR10_UEA09E                *((volatile unsigned int*)(0x4266C540UL))
+#define bFM3_GPIO_EPFR10_UEA10E                *((volatile unsigned int*)(0x4266C544UL))
+#define bFM3_GPIO_EPFR10_UEA11E                *((volatile unsigned int*)(0x4266C548UL))
+#define bFM3_GPIO_EPFR10_UEA12E                *((volatile unsigned int*)(0x4266C54CUL))
+#define bFM3_GPIO_EPFR10_UEA13E                *((volatile unsigned int*)(0x4266C550UL))
+#define bFM3_GPIO_EPFR10_UEA14E                *((volatile unsigned int*)(0x4266C554UL))
+#define bFM3_GPIO_EPFR10_UEA15E                *((volatile unsigned int*)(0x4266C558UL))
+#define bFM3_GPIO_EPFR10_UEA16E                *((volatile unsigned int*)(0x4266C55CUL))
+#define bFM3_GPIO_EPFR10_UEA17E                *((volatile unsigned int*)(0x4266C560UL))
+#define bFM3_GPIO_EPFR10_UEA18E                *((volatile unsigned int*)(0x4266C564UL))
+#define bFM3_GPIO_EPFR11_UEALEE                *((volatile unsigned int*)(0x4266C580UL))
+#define bFM3_GPIO_EPFR11_UECS0E                *((volatile unsigned int*)(0x4266C584UL))
+#define bFM3_GPIO_EPFR11_UEA01E                *((volatile unsigned int*)(0x4266C588UL))
+#define bFM3_GPIO_EPFR11_UEA02E                *((volatile unsigned int*)(0x4266C58CUL))
+#define bFM3_GPIO_EPFR11_UEA03E                *((volatile unsigned int*)(0x4266C590UL))
+#define bFM3_GPIO_EPFR11_UEA04E                *((volatile unsigned int*)(0x4266C594UL))
+#define bFM3_GPIO_EPFR11_UEA05E                *((volatile unsigned int*)(0x4266C598UL))
+#define bFM3_GPIO_EPFR11_UEA06E                *((volatile unsigned int*)(0x4266C59CUL))
+#define bFM3_GPIO_EPFR11_UEA07E                *((volatile unsigned int*)(0x4266C5A0UL))
+#define bFM3_GPIO_EPFR11_UED00B                *((volatile unsigned int*)(0x4266C5A4UL))
+#define bFM3_GPIO_EPFR11_UED01B                *((volatile unsigned int*)(0x4266C5A8UL))
+#define bFM3_GPIO_EPFR11_UED02B                *((volatile unsigned int*)(0x4266C5ACUL))
+#define bFM3_GPIO_EPFR11_UED03B                *((volatile unsigned int*)(0x4266C5B0UL))
+#define bFM3_GPIO_EPFR11_UED04B                *((volatile unsigned int*)(0x4266C5B4UL))
+#define bFM3_GPIO_EPFR11_UED05B                *((volatile unsigned int*)(0x4266C5B8UL))
+#define bFM3_GPIO_EPFR11_UED06B                *((volatile unsigned int*)(0x4266C5BCUL))
+#define bFM3_GPIO_EPFR11_UED07B                *((volatile unsigned int*)(0x4266C5C0UL))
+#define bFM3_GPIO_EPFR11_UED08B                *((volatile unsigned int*)(0x4266C5C4UL))
+#define bFM3_GPIO_EPFR11_UED09B                *((volatile unsigned int*)(0x4266C5C8UL))
+#define bFM3_GPIO_EPFR11_UED10B                *((volatile unsigned int*)(0x4266C5CCUL))
+#define bFM3_GPIO_EPFR11_UED11B                *((volatile unsigned int*)(0x4266C5D0UL))
+#define bFM3_GPIO_EPFR11_UED12B                *((volatile unsigned int*)(0x4266C5D4UL))
+#define bFM3_GPIO_EPFR11_UED13B                *((volatile unsigned int*)(0x4266C5D8UL))
+#define bFM3_GPIO_EPFR11_UED14B                *((volatile unsigned int*)(0x4266C5DCUL))
+#define bFM3_GPIO_EPFR11_UED15B                *((volatile unsigned int*)(0x4266C5E0UL))
+#define bFM3_GPIO_EPFR11_UERLC                 *((volatile unsigned int*)(0x4266C5E4UL))
+#define bFM3_GPIO_EPFR12_TIOA8E0               *((volatile unsigned int*)(0x4266C608UL))
+#define bFM3_GPIO_EPFR12_TIOA8E1               *((volatile unsigned int*)(0x4266C60CUL))
+#define bFM3_GPIO_EPFR12_TIOB8S0               *((volatile unsigned int*)(0x4266C610UL))
+#define bFM3_GPIO_EPFR12_TIOB8S1               *((volatile unsigned int*)(0x4266C614UL))
+#define bFM3_GPIO_EPFR12_TIOA9S0               *((volatile unsigned int*)(0x4266C620UL))
+#define bFM3_GPIO_EPFR12_TIOA9S1               *((volatile unsigned int*)(0x4266C624UL))
+#define bFM3_GPIO_EPFR12_TIOA9E0               *((volatile unsigned int*)(0x4266C628UL))
+#define bFM3_GPIO_EPFR12_TIOA9E1               *((volatile unsigned int*)(0x4266C62CUL))
+#define bFM3_GPIO_EPFR12_TIOB9S0               *((volatile unsigned int*)(0x4266C630UL))
+#define bFM3_GPIO_EPFR12_TIOB9S1               *((volatile unsigned int*)(0x4266C634UL))
+#define bFM3_GPIO_EPFR12_TIOA10E0              *((volatile unsigned int*)(0x4266C648UL))
+#define bFM3_GPIO_EPFR12_TIOA10E1              *((volatile unsigned int*)(0x4266C64CUL))
+#define bFM3_GPIO_EPFR12_TIOB10S0              *((volatile unsigned int*)(0x4266C650UL))
+#define bFM3_GPIO_EPFR12_TIOB10S1              *((volatile unsigned int*)(0x4266C654UL))
+#define bFM3_GPIO_EPFR12_TIOA11S0              *((volatile unsigned int*)(0x4266C660UL))
+#define bFM3_GPIO_EPFR12_TIOA11S1              *((volatile unsigned int*)(0x4266C664UL))
+#define bFM3_GPIO_EPFR12_TIOA11E0              *((volatile unsigned int*)(0x4266C668UL))
+#define bFM3_GPIO_EPFR12_TIOA11E1              *((volatile unsigned int*)(0x4266C66CUL))
+#define bFM3_GPIO_EPFR12_TIOB11S0              *((volatile unsigned int*)(0x4266C670UL))
+#define bFM3_GPIO_EPFR12_TIOB11S1              *((volatile unsigned int*)(0x4266C674UL))
+#define bFM3_GPIO_EPFR13_TIOA12E0              *((volatile unsigned int*)(0x4266C688UL))
+#define bFM3_GPIO_EPFR13_TIOA12E1              *((volatile unsigned int*)(0x4266C68CUL))
+#define bFM3_GPIO_EPFR13_TIOB12S0              *((volatile unsigned int*)(0x4266C690UL))
+#define bFM3_GPIO_EPFR13_TIOB12S1              *((volatile unsigned int*)(0x4266C694UL))
+#define bFM3_GPIO_EPFR13_TIOA13S0              *((volatile unsigned int*)(0x4266C6A0UL))
+#define bFM3_GPIO_EPFR13_TIOA13S1              *((volatile unsigned int*)(0x4266C6A4UL))
+#define bFM3_GPIO_EPFR13_TIOA13E0              *((volatile unsigned int*)(0x4266C6A8UL))
+#define bFM3_GPIO_EPFR13_TIOA13E1              *((volatile unsigned int*)(0x4266C6ACUL))
+#define bFM3_GPIO_EPFR13_TIOB13S0              *((volatile unsigned int*)(0x4266C6B0UL))
+#define bFM3_GPIO_EPFR13_TIOB13S1              *((volatile unsigned int*)(0x4266C6B4UL))
+#define bFM3_GPIO_EPFR13_TIOA14E0              *((volatile unsigned int*)(0x4266C6C8UL))
+#define bFM3_GPIO_EPFR13_TIOA14E1              *((volatile unsigned int*)(0x4266C6CCUL))
+#define bFM3_GPIO_EPFR13_TIOB14S0              *((volatile unsigned int*)(0x4266C6D0UL))
+#define bFM3_GPIO_EPFR13_TIOB14S1              *((volatile unsigned int*)(0x4266C6D4UL))
+#define bFM3_GPIO_EPFR13_TIOA15S0              *((volatile unsigned int*)(0x4266C6E0UL))
+#define bFM3_GPIO_EPFR13_TIOA15S1              *((volatile unsigned int*)(0x4266C6E4UL))
+#define bFM3_GPIO_EPFR13_TIOA15E0              *((volatile unsigned int*)(0x4266C6E8UL))
+#define bFM3_GPIO_EPFR13_TIOA15E1              *((volatile unsigned int*)(0x4266C6ECUL))
+#define bFM3_GPIO_EPFR13_TIOB15S0              *((volatile unsigned int*)(0x4266C6F0UL))
+#define bFM3_GPIO_EPFR13_TIOB15S1              *((volatile unsigned int*)(0x4266C6F4UL))
+#define bFM3_GPIO_EPFR14_QAIN2S0               *((volatile unsigned int*)(0x4266C700UL))
+#define bFM3_GPIO_EPFR14_QAIN2S1               *((volatile unsigned int*)(0x4266C704UL))
+#define bFM3_GPIO_EPFR14_QBIN2S0               *((volatile unsigned int*)(0x4266C708UL))
+#define bFM3_GPIO_EPFR14_QBIN2S1               *((volatile unsigned int*)(0x4266C70CUL))
+#define bFM3_GPIO_EPFR14_QZIN2S0               *((volatile unsigned int*)(0x4266C710UL))
+#define bFM3_GPIO_EPFR14_QZIN2S1               *((volatile unsigned int*)(0x4266C714UL))
+#define bFM3_GPIO_EPFR14_E_TD0E                *((volatile unsigned int*)(0x4266C748UL))
+#define bFM3_GPIO_EPFR14_E_TD1E                *((volatile unsigned int*)(0x4266C74CUL))
+#define bFM3_GPIO_EPFR14_E_TE0E                *((volatile unsigned int*)(0x4266C750UL))
+#define bFM3_GPIO_EPFR14_E_TE1E                *((volatile unsigned int*)(0x4266C754UL))
+#define bFM3_GPIO_EPFR14_E_MC0E                *((volatile unsigned int*)(0x4266C758UL))
+#define bFM3_GPIO_EPFR14_E_MC1B                *((volatile unsigned int*)(0x4266C75CUL))
+#define bFM3_GPIO_EPFR14_E_MD0B                *((volatile unsigned int*)(0x4266C760UL))
+#define bFM3_GPIO_EPFR14_E_MD1B                *((volatile unsigned int*)(0x4266C764UL))
+#define bFM3_GPIO_EPFR14_E_CKE                 *((volatile unsigned int*)(0x4266C768UL))
+#define bFM3_GPIO_EPFR14_E_PSE                 *((volatile unsigned int*)(0x4266C76CUL))
+#define bFM3_GPIO_EPFR14_E_SPLC0               *((volatile unsigned int*)(0x4266C770UL))
+#define bFM3_GPIO_EPFR14_E_SPLC1               *((volatile unsigned int*)(0x4266C774UL))
+#define bFM3_GPIO_EPFR15_EINT16S0              *((volatile unsigned int*)(0x4266C780UL))
+#define bFM3_GPIO_EPFR15_EINT16S1              *((volatile unsigned int*)(0x4266C784UL))
+#define bFM3_GPIO_EPFR15_EINT17S0              *((volatile unsigned int*)(0x4266C788UL))
+#define bFM3_GPIO_EPFR15_EINT17S1              *((volatile unsigned int*)(0x4266C78CUL))
+#define bFM3_GPIO_EPFR15_EINT18S0              *((volatile unsigned int*)(0x4266C790UL))
+#define bFM3_GPIO_EPFR15_EINT18S1              *((volatile unsigned int*)(0x4266C794UL))
+#define bFM3_GPIO_EPFR15_EINT19S0              *((volatile unsigned int*)(0x4266C798UL))
+#define bFM3_GPIO_EPFR15_EINT19S1              *((volatile unsigned int*)(0x4266C79CUL))
+#define bFM3_GPIO_EPFR15_EINT20S0              *((volatile unsigned int*)(0x4266C7A0UL))
+#define bFM3_GPIO_EPFR15_EINT20S1              *((volatile unsigned int*)(0x4266C7A4UL))
+#define bFM3_GPIO_EPFR15_EINT21S0              *((volatile unsigned int*)(0x4266C7A8UL))
+#define bFM3_GPIO_EPFR15_EINT21S1              *((volatile unsigned int*)(0x4266C7ACUL))
+#define bFM3_GPIO_EPFR15_EINT22S0              *((volatile unsigned int*)(0x4266C7B0UL))
+#define bFM3_GPIO_EPFR15_EINT22S1              *((volatile unsigned int*)(0x4266C7B4UL))
+#define bFM3_GPIO_EPFR15_EINT23S0              *((volatile unsigned int*)(0x4266C7B8UL))
+#define bFM3_GPIO_EPFR15_EINT23S1              *((volatile unsigned int*)(0x4266C7BCUL))
+#define bFM3_GPIO_EPFR15_EINT24S0              *((volatile unsigned int*)(0x4266C7C0UL))
+#define bFM3_GPIO_EPFR15_EINT24S1              *((volatile unsigned int*)(0x4266C7C4UL))
+#define bFM3_GPIO_EPFR15_EINT25S0              *((volatile unsigned int*)(0x4266C7C8UL))
+#define bFM3_GPIO_EPFR15_EINT25S1              *((volatile unsigned int*)(0x4266C7CCUL))
+#define bFM3_GPIO_EPFR15_EINT26S0              *((volatile unsigned int*)(0x4266C7D0UL))
+#define bFM3_GPIO_EPFR15_EINT26S1              *((volatile unsigned int*)(0x4266C7D4UL))
+#define bFM3_GPIO_EPFR15_EINT27S0              *((volatile unsigned int*)(0x4266C7D8UL))
+#define bFM3_GPIO_EPFR15_EINT27S1              *((volatile unsigned int*)(0x4266C7DCUL))
+#define bFM3_GPIO_EPFR15_EINT28S0              *((volatile unsigned int*)(0x4266C7E0UL))
+#define bFM3_GPIO_EPFR15_EINT28S1              *((volatile unsigned int*)(0x4266C7E4UL))
+#define bFM3_GPIO_EPFR15_EINT29S0              *((volatile unsigned int*)(0x4266C7E8UL))
+#define bFM3_GPIO_EPFR15_EINT29S1              *((volatile unsigned int*)(0x4266C7ECUL))
+#define bFM3_GPIO_EPFR15_EINT30S0              *((volatile unsigned int*)(0x4266C7F0UL))
+#define bFM3_GPIO_EPFR15_EINT30S1              *((volatile unsigned int*)(0x4266C7F4UL))
+#define bFM3_GPIO_EPFR15_EINT31S0              *((volatile unsigned int*)(0x4266C7F8UL))
+#define bFM3_GPIO_EPFR15_EINT31S1              *((volatile unsigned int*)(0x4266C7FCUL))
+#define bFM3_GPIO_PZR0_P0                      *((volatile unsigned int*)(0x4266E000UL))
+#define bFM3_GPIO_PZR0_P1                      *((volatile unsigned int*)(0x4266E004UL))
+#define bFM3_GPIO_PZR0_P2                      *((volatile unsigned int*)(0x4266E008UL))
+#define bFM3_GPIO_PZR0_P3                      *((volatile unsigned int*)(0x4266E00CUL))
+#define bFM3_GPIO_PZR0_P4                      *((volatile unsigned int*)(0x4266E010UL))
+#define bFM3_GPIO_PZR0_P5                      *((volatile unsigned int*)(0x4266E014UL))
+#define bFM3_GPIO_PZR0_P6                      *((volatile unsigned int*)(0x4266E018UL))
+#define bFM3_GPIO_PZR0_P7                      *((volatile unsigned int*)(0x4266E01CUL))
+#define bFM3_GPIO_PZR0_P8                      *((volatile unsigned int*)(0x4266E020UL))
+#define bFM3_GPIO_PZR0_P9                      *((volatile unsigned int*)(0x4266E024UL))
+#define bFM3_GPIO_PZR1_P0                      *((volatile unsigned int*)(0x4266E080UL))
+#define bFM3_GPIO_PZR1_P1                      *((volatile unsigned int*)(0x4266E084UL))
+#define bFM3_GPIO_PZR1_P2                      *((volatile unsigned int*)(0x4266E088UL))
+#define bFM3_GPIO_PZR1_P3                      *((volatile unsigned int*)(0x4266E08CUL))
+#define bFM3_GPIO_PZR1_P4                      *((volatile unsigned int*)(0x4266E090UL))
+#define bFM3_GPIO_PZR1_P5                      *((volatile unsigned int*)(0x4266E094UL))
+#define bFM3_GPIO_PZR1_P6                      *((volatile unsigned int*)(0x4266E098UL))
+#define bFM3_GPIO_PZR1_P7                      *((volatile unsigned int*)(0x4266E09CUL))
+#define bFM3_GPIO_PZR1_P8                      *((volatile unsigned int*)(0x4266E0A0UL))
+#define bFM3_GPIO_PZR1_P9                      *((volatile unsigned int*)(0x4266E0A4UL))
+#define bFM3_GPIO_PZR1_PA                      *((volatile unsigned int*)(0x4266E0A8UL))
+#define bFM3_GPIO_PZR1_PB                      *((volatile unsigned int*)(0x4266E0ACUL))
+#define bFM3_GPIO_PZR1_PC                      *((volatile unsigned int*)(0x4266E0B0UL))
+#define bFM3_GPIO_PZR1_PD                      *((volatile unsigned int*)(0x4266E0B4UL))
+#define bFM3_GPIO_PZR1_PE                      *((volatile unsigned int*)(0x4266E0B8UL))
+#define bFM3_GPIO_PZR1_PF                      *((volatile unsigned int*)(0x4266E0BCUL))
+#define bFM3_GPIO_PZR2_P0                      *((volatile unsigned int*)(0x4266E100UL))
+#define bFM3_GPIO_PZR2_P1                      *((volatile unsigned int*)(0x4266E104UL))
+#define bFM3_GPIO_PZR2_P2                      *((volatile unsigned int*)(0x4266E108UL))
+#define bFM3_GPIO_PZR2_P3                      *((volatile unsigned int*)(0x4266E10CUL))
+#define bFM3_GPIO_PZR2_P4                      *((volatile unsigned int*)(0x4266E110UL))
+#define bFM3_GPIO_PZR2_P5                      *((volatile unsigned int*)(0x4266E114UL))
+#define bFM3_GPIO_PZR2_P6                      *((volatile unsigned int*)(0x4266E118UL))
+#define bFM3_GPIO_PZR2_P7                      *((volatile unsigned int*)(0x4266E11CUL))
+#define bFM3_GPIO_PZR2_P8                      *((volatile unsigned int*)(0x4266E120UL))
+#define bFM3_GPIO_PZR2_P9                      *((volatile unsigned int*)(0x4266E124UL))
+#define bFM3_GPIO_PZR3_P6                      *((volatile unsigned int*)(0x4266E198UL))
+#define bFM3_GPIO_PZR3_P7                      *((volatile unsigned int*)(0x4266E19CUL))
+#define bFM3_GPIO_PZR3_P8                      *((volatile unsigned int*)(0x4266E1A0UL))
+#define bFM3_GPIO_PZR3_P9                      *((volatile unsigned int*)(0x4266E1A4UL))
+#define bFM3_GPIO_PZR3_PA                      *((volatile unsigned int*)(0x4266E1A8UL))
+#define bFM3_GPIO_PZR3_PB                      *((volatile unsigned int*)(0x4266E1ACUL))
+#define bFM3_GPIO_PZR3_PC                      *((volatile unsigned int*)(0x4266E1B0UL))
+#define bFM3_GPIO_PZR3_PD                      *((volatile unsigned int*)(0x4266E1B4UL))
+#define bFM3_GPIO_PZR3_PE                      *((volatile unsigned int*)(0x4266E1B8UL))
+#define bFM3_GPIO_PZR3_PF                      *((volatile unsigned int*)(0x4266E1BCUL))
+#define bFM3_GPIO_PZR4_P0                      *((volatile unsigned int*)(0x4266E200UL))
+#define bFM3_GPIO_PZR4_P1                      *((volatile unsigned int*)(0x4266E204UL))
+#define bFM3_GPIO_PZR4_P2                      *((volatile unsigned int*)(0x4266E208UL))
+#define bFM3_GPIO_PZR4_P3                      *((volatile unsigned int*)(0x4266E20CUL))
+#define bFM3_GPIO_PZR4_P4                      *((volatile unsigned int*)(0x4266E210UL))
+#define bFM3_GPIO_PZR4_P5                      *((volatile unsigned int*)(0x4266E214UL))
+#define bFM3_GPIO_PZR4_P6                      *((volatile unsigned int*)(0x4266E218UL))
+#define bFM3_GPIO_PZR4_P7                      *((volatile unsigned int*)(0x4266E21CUL))
+#define bFM3_GPIO_PZR4_P8                      *((volatile unsigned int*)(0x4266E220UL))
+#define bFM3_GPIO_PZR4_P9                      *((volatile unsigned int*)(0x4266E224UL))
+#define bFM3_GPIO_PZR4_PA                      *((volatile unsigned int*)(0x4266E228UL))
+#define bFM3_GPIO_PZR4_PB                      *((volatile unsigned int*)(0x4266E22CUL))
+#define bFM3_GPIO_PZR4_PC                      *((volatile unsigned int*)(0x4266E230UL))
+#define bFM3_GPIO_PZR4_PD                      *((volatile unsigned int*)(0x4266E234UL))
+#define bFM3_GPIO_PZR4_PE                      *((volatile unsigned int*)(0x4266E238UL))
+#define bFM3_GPIO_PZR5_P0                      *((volatile unsigned int*)(0x4266E280UL))
+#define bFM3_GPIO_PZR5_P1                      *((volatile unsigned int*)(0x4266E284UL))
+#define bFM3_GPIO_PZR5_P2                      *((volatile unsigned int*)(0x4266E288UL))
+#define bFM3_GPIO_PZR5_P3                      *((volatile unsigned int*)(0x4266E28CUL))
+#define bFM3_GPIO_PZR5_P4                      *((volatile unsigned int*)(0x4266E290UL))
+#define bFM3_GPIO_PZR5_P5                      *((volatile unsigned int*)(0x4266E294UL))
+#define bFM3_GPIO_PZR5_P6                      *((volatile unsigned int*)(0x4266E298UL))
+#define bFM3_GPIO_PZR5_P7                      *((volatile unsigned int*)(0x4266E29CUL))
+#define bFM3_GPIO_PZR5_P8                      *((volatile unsigned int*)(0x4266E2A0UL))
+#define bFM3_GPIO_PZR5_P9                      *((volatile unsigned int*)(0x4266E2A4UL))
+#define bFM3_GPIO_PZR5_PA                      *((volatile unsigned int*)(0x4266E2A8UL))
+#define bFM3_GPIO_PZR5_PB                      *((volatile unsigned int*)(0x4266E2ACUL))
+#define bFM3_GPIO_PZR6_P0                      *((volatile unsigned int*)(0x4266E300UL))
+#define bFM3_GPIO_PZR6_P1                      *((volatile unsigned int*)(0x4266E304UL))
+#define bFM3_GPIO_PZR6_P2                      *((volatile unsigned int*)(0x4266E308UL))
+#define bFM3_GPIO_PZR7_P0                      *((volatile unsigned int*)(0x4266E380UL))
+#define bFM3_GPIO_PZR7_P1                      *((volatile unsigned int*)(0x4266E384UL))
+#define bFM3_GPIO_PZR7_P2                      *((volatile unsigned int*)(0x4266E388UL))
+#define bFM3_GPIO_PZR7_P3                      *((volatile unsigned int*)(0x4266E38CUL))
+#define bFM3_GPIO_PZR7_P4                      *((volatile unsigned int*)(0x4266E390UL))
+#define bFM3_GPIO_PZR7_P5                      *((volatile unsigned int*)(0x4266E394UL))
+#define bFM3_GPIO_PZR7_P6                      *((volatile unsigned int*)(0x4266E398UL))
+#define bFM3_GPIO_PZR7_P7                      *((volatile unsigned int*)(0x4266E39CUL))
+#define bFM3_GPIO_PZR7_P8                      *((volatile unsigned int*)(0x4266E3A0UL))
+#define bFM3_GPIO_PZR7_P9                      *((volatile unsigned int*)(0x4266E3A4UL))
+#define bFM3_GPIO_PZR7_PA                      *((volatile unsigned int*)(0x4266E3A8UL))
+#define bFM3_GPIO_PZR8_P0                      *((volatile unsigned int*)(0x4266E400UL))
+#define bFM3_GPIO_PZR8_P1                      *((volatile unsigned int*)(0x4266E404UL))
+#define bFM3_GPIO_PZR8_P2                      *((volatile unsigned int*)(0x4266E408UL))
+#define bFM3_GPIO_PZR8_P3                      *((volatile unsigned int*)(0x4266E40CUL))
+#define bFM3_GPIO_PZRA_P0                      *((volatile unsigned int*)(0x4266E500UL))
+#define bFM3_GPIO_PZRA_P1                      *((volatile unsigned int*)(0x4266E504UL))
+#define bFM3_GPIO_PZRA_P2                      *((volatile unsigned int*)(0x4266E508UL))
+#define bFM3_GPIO_PZRA_P3                      *((volatile unsigned int*)(0x4266E50CUL))
+#define bFM3_GPIO_PZRA_P4                      *((volatile unsigned int*)(0x4266E510UL))
+#define bFM3_GPIO_PZRA_P5                      *((volatile unsigned int*)(0x4266E514UL))
+#define bFM3_GPIO_PZRC_P0                      *((volatile unsigned int*)(0x4266E600UL))
+#define bFM3_GPIO_PZRC_P1                      *((volatile unsigned int*)(0x4266E604UL))
+#define bFM3_GPIO_PZRC_P2                      *((volatile unsigned int*)(0x4266E608UL))
+#define bFM3_GPIO_PZRC_P3                      *((volatile unsigned int*)(0x4266E60CUL))
+#define bFM3_GPIO_PZRC_P4                      *((volatile unsigned int*)(0x4266E610UL))
+#define bFM3_GPIO_PZRC_P5                      *((volatile unsigned int*)(0x4266E614UL))
+#define bFM3_GPIO_PZRC_P6                      *((volatile unsigned int*)(0x4266E618UL))
+#define bFM3_GPIO_PZRC_P7                      *((volatile unsigned int*)(0x4266E61CUL))
+#define bFM3_GPIO_PZRC_P8                      *((volatile unsigned int*)(0x4266E620UL))
+#define bFM3_GPIO_PZRC_P9                      *((volatile unsigned int*)(0x4266E624UL))
+#define bFM3_GPIO_PZRC_PA                      *((volatile unsigned int*)(0x4266E628UL))
+#define bFM3_GPIO_PZRC_PB                      *((volatile unsigned int*)(0x4266E62CUL))
+#define bFM3_GPIO_PZRC_PC                      *((volatile unsigned int*)(0x4266E630UL))
+#define bFM3_GPIO_PZRC_PD                      *((volatile unsigned int*)(0x4266E634UL))
+#define bFM3_GPIO_PZRC_PE                      *((volatile unsigned int*)(0x4266E638UL))
+#define bFM3_GPIO_PZRC_PF                      *((volatile unsigned int*)(0x4266E63CUL))
+#define bFM3_GPIO_PZRD_P0                      *((volatile unsigned int*)(0x4266E680UL))
+#define bFM3_GPIO_PZRD_P1                      *((volatile unsigned int*)(0x4266E684UL))
+#define bFM3_GPIO_PZRD_P2                      *((volatile unsigned int*)(0x4266E688UL))
+#define bFM3_GPIO_PZRD_P3                      *((volatile unsigned int*)(0x4266E68CUL))
+#define bFM3_GPIO_PZRE_P0                      *((volatile unsigned int*)(0x4266E700UL))
+#define bFM3_GPIO_PZRE_P2                      *((volatile unsigned int*)(0x4266E708UL))
+#define bFM3_GPIO_PZRE_P3                      *((volatile unsigned int*)(0x4266E70CUL))
+#define bFM3_GPIO_PZRF_P5                      *((volatile unsigned int*)(0x4266E794UL))
+#define bFM3_GPIO_PZRF_P6                      *((volatile unsigned int*)(0x4266E798UL))
+
+/* Low voltage detection registers */
+#define bFM3_LVD_LVD_CTL_SVHI0                 *((volatile unsigned int*)(0x426A0008UL))
+#define bFM3_LVD_LVD_CTL_SVHI1                 *((volatile unsigned int*)(0x426A000CUL))
+#define bFM3_LVD_LVD_CTL_SVHI2                 *((volatile unsigned int*)(0x426A0010UL))
+#define bFM3_LVD_LVD_CTL_SVHI3                 *((volatile unsigned int*)(0x426A0014UL))
+#define bFM3_LVD_LVD_CTL_LVDIE                 *((volatile unsigned int*)(0x426A001CUL))
+#define bFM3_LVD_LVD_STR_LVDIR                 *((volatile unsigned int*)(0x426A009CUL))
+#define bFM3_LVD_LVD_CLR_LVDCL                 *((volatile unsigned int*)(0x426A011CUL))
+#define bFM3_LVD_LVD_STR2_LVDIRDY              *((volatile unsigned int*)(0x426A021CUL))
+
+/* USB clock registers */
+#define bFM3_USBETHERNETCLK_UCCR_UCEN0         *((volatile unsigned int*)(0x426C0000UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL0        *((volatile unsigned int*)(0x426C0004UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL1        *((volatile unsigned int*)(0x426C0008UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCEN1         *((volatile unsigned int*)(0x426C000CUL))
+#define bFM3_USBETHERNETCLK_UCCR_ECEN          *((volatile unsigned int*)(0x426C0010UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL0        *((volatile unsigned int*)(0x426C0014UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL1        *((volatile unsigned int*)(0x426C0018UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN       *((volatile unsigned int*)(0x426C0080UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPINC        *((volatile unsigned int*)(0x426C0084UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0       *((volatile unsigned int*)(0x426C0100UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1       *((volatile unsigned int*)(0x426C0104UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2       *((volatile unsigned int*)(0x426C0108UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0       *((volatile unsigned int*)(0x426C0180UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1       *((volatile unsigned int*)(0x426C0184UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2       *((volatile unsigned int*)(0x426C0188UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3       *((volatile unsigned int*)(0x426C018CUL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4       *((volatile unsigned int*)(0x426C0190UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0       *((volatile unsigned int*)(0x426C0200UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1       *((volatile unsigned int*)(0x426C0204UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2       *((volatile unsigned int*)(0x426C0208UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3       *((volatile unsigned int*)(0x426C020CUL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4       *((volatile unsigned int*)(0x426C0210UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5       *((volatile unsigned int*)(0x426C0214UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6       *((volatile unsigned int*)(0x426C0218UL))
+#define bFM3_USBETHERNETCLK_UP_STR_UPRDY       *((volatile unsigned int*)(0x426C0280UL))
+#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE    *((volatile unsigned int*)(0x426C0300UL))
+#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC    *((volatile unsigned int*)(0x426C0380UL))
+#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI    *((volatile unsigned int*)(0x426C0400UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0       *((volatile unsigned int*)(0x426C0480UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1       *((volatile unsigned int*)(0x426C0484UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2       *((volatile unsigned int*)(0x426C0488UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3       *((volatile unsigned int*)(0x426C048CUL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR0        *((volatile unsigned int*)(0x426C0500UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR1        *((volatile unsigned int*)(0x426C0504UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR2        *((volatile unsigned int*)(0x426C0508UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR3        *((volatile unsigned int*)(0x426C050CUL))
+#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN       *((volatile unsigned int*)(0x426C0580UL))
+#define bFM3_USBETHERNETCLK_USBEN0_USBEN0      *((volatile unsigned int*)(0x426C0600UL))
+#define bFM3_USBETHERNETCLK_USBEN1_USBEN1      *((volatile unsigned int*)(0x426C0680UL))
+
+/* UART asynchronous channel 0 registers */
+#define bFM3_MFS0_UART_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_UART_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_UART_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_UART_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_UART_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_UART_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_UART_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_UART_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_UART_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_UART_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_UART_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_UART_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_UART_ESCR_P                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_UART_ESCR_PEN                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_UART_ESCR_INV                *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_UART_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_UART_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_UART_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_UART_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_UART_SSR_FRE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_UART_SSR_PE                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_UART_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_UART_RDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_TDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_BGR_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_UART_BGR1_EXT                *((volatile unsigned int*)(0x427001BCUL))
+
+/* UART synchronous channel 0 registers */
+#define bFM3_MFS0_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42700004UL))
+#define bFM3_MFS0_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+
+/* UART LIN channel 0 registers */
+#define bFM3_MFS0_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_LIN_SCR_MS                   *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_LIN_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+
+/* I2C channel 0 registers */
+#define bFM3_MFS0_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42700004UL))
+#define bFM3_MFS0_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42700014UL))
+#define bFM3_MFS0_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42700018UL))
+#define bFM3_MFS0_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270001CUL))
+#define bFM3_MFS0_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427000B8UL))
+#define bFM3_MFS0_I2C_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42700200UL))
+#define bFM3_MFS0_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42700204UL))
+#define bFM3_MFS0_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42700208UL))
+#define bFM3_MFS0_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270020CUL))
+#define bFM3_MFS0_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42700210UL))
+#define bFM3_MFS0_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42700214UL))
+#define bFM3_MFS0_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42700218UL))
+#define bFM3_MFS0_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270021CUL))
+#define bFM3_MFS0_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42700220UL))
+#define bFM3_MFS0_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42700224UL))
+#define bFM3_MFS0_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42700228UL))
+#define bFM3_MFS0_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270022CUL))
+#define bFM3_MFS0_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42700230UL))
+#define bFM3_MFS0_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42700234UL))
+#define bFM3_MFS0_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42700238UL))
+#define bFM3_MFS0_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270023CUL))
+
+/* UART asynchronous channel 1 registers */
+#define bFM3_MFS1_UART_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_UART_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_UART_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_UART_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_UART_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_UART_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_UART_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_UART_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_UART_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_UART_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_UART_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_UART_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_UART_ESCR_P                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_UART_ESCR_PEN                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_UART_ESCR_INV                *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_UART_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_UART_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_UART_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_UART_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_UART_SSR_FRE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_UART_SSR_PE                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_UART_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_UART_RDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_TDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_BGR_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_UART_BGR1_EXT                *((volatile unsigned int*)(0x427021BCUL))
+
+/* UART synchronous channel 1 registers */
+#define bFM3_MFS1_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42702004UL))
+#define bFM3_MFS1_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+
+/* UART LIN channel 1 registers */
+#define bFM3_MFS1_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_LIN_SCR_MS                   *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_LIN_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+
+/* I2C channel 1 registers */
+#define bFM3_MFS1_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42702004UL))
+#define bFM3_MFS1_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42702014UL))
+#define bFM3_MFS1_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42702018UL))
+#define bFM3_MFS1_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270201CUL))
+#define bFM3_MFS1_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427020B8UL))
+#define bFM3_MFS1_I2C_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42702200UL))
+#define bFM3_MFS1_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42702204UL))
+#define bFM3_MFS1_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42702208UL))
+#define bFM3_MFS1_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270220CUL))
+#define bFM3_MFS1_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42702210UL))
+#define bFM3_MFS1_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42702214UL))
+#define bFM3_MFS1_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42702218UL))
+#define bFM3_MFS1_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270221CUL))
+#define bFM3_MFS1_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42702220UL))
+#define bFM3_MFS1_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42702224UL))
+#define bFM3_MFS1_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42702228UL))
+#define bFM3_MFS1_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270222CUL))
+#define bFM3_MFS1_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42702230UL))
+#define bFM3_MFS1_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42702234UL))
+#define bFM3_MFS1_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42702238UL))
+#define bFM3_MFS1_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270223CUL))
+
+/* UART asynchronous channel 2 registers */
+#define bFM3_MFS2_UART_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_UART_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_UART_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_UART_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_UART_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_UART_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_UART_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_UART_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_UART_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_UART_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_UART_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_UART_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_UART_ESCR_P                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_UART_ESCR_PEN                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_UART_ESCR_INV                *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_UART_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_UART_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_UART_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_UART_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_UART_SSR_FRE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_UART_SSR_PE                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_UART_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_UART_RDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_TDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_BGR_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_UART_BGR1_EXT                *((volatile unsigned int*)(0x427041BCUL))
+
+/* UART synchronous channel 2 registers */
+#define bFM3_MFS2_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42704004UL))
+#define bFM3_MFS2_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+
+/* UART LIN channel 2 registers */
+#define bFM3_MFS2_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_LIN_SCR_MS                   *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_LIN_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+
+/* I2C channel 2 registers */
+#define bFM3_MFS2_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42704004UL))
+#define bFM3_MFS2_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42704014UL))
+#define bFM3_MFS2_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42704018UL))
+#define bFM3_MFS2_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270401CUL))
+#define bFM3_MFS2_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427040B8UL))
+#define bFM3_MFS2_I2C_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42704200UL))
+#define bFM3_MFS2_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42704204UL))
+#define bFM3_MFS2_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42704208UL))
+#define bFM3_MFS2_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270420CUL))
+#define bFM3_MFS2_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42704210UL))
+#define bFM3_MFS2_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42704214UL))
+#define bFM3_MFS2_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42704218UL))
+#define bFM3_MFS2_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270421CUL))
+#define bFM3_MFS2_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42704220UL))
+#define bFM3_MFS2_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42704224UL))
+#define bFM3_MFS2_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42704228UL))
+#define bFM3_MFS2_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270422CUL))
+#define bFM3_MFS2_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42704230UL))
+#define bFM3_MFS2_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42704234UL))
+#define bFM3_MFS2_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42704238UL))
+#define bFM3_MFS2_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270423CUL))
+
+/* UART asynchronous channel 3 registers */
+#define bFM3_MFS3_UART_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_UART_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_UART_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_UART_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_UART_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_UART_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_UART_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_UART_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_UART_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_UART_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_UART_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_UART_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_UART_ESCR_P                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_UART_ESCR_PEN                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_UART_ESCR_INV                *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_UART_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_UART_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_UART_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_UART_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_UART_SSR_FRE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_UART_SSR_PE                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_UART_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_UART_RDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_TDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_BGR_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_UART_BGR1_EXT                *((volatile unsigned int*)(0x427061BCUL))
+
+/* UART synchronous channel 3 registers */
+#define bFM3_MFS3_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42706004UL))
+#define bFM3_MFS3_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+
+/* UART LIN channel 3 registers */
+#define bFM3_MFS3_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_LIN_SCR_MS                   *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_LIN_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+
+/* I2C channel 3 registers */
+#define bFM3_MFS3_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42706004UL))
+#define bFM3_MFS3_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42706014UL))
+#define bFM3_MFS3_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42706018UL))
+#define bFM3_MFS3_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270601CUL))
+#define bFM3_MFS3_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427060B8UL))
+#define bFM3_MFS3_I2C_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42706200UL))
+#define bFM3_MFS3_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42706204UL))
+#define bFM3_MFS3_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42706208UL))
+#define bFM3_MFS3_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270620CUL))
+#define bFM3_MFS3_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42706210UL))
+#define bFM3_MFS3_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42706214UL))
+#define bFM3_MFS3_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42706218UL))
+#define bFM3_MFS3_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270621CUL))
+#define bFM3_MFS3_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42706220UL))
+#define bFM3_MFS3_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42706224UL))
+#define bFM3_MFS3_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42706228UL))
+#define bFM3_MFS3_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270622CUL))
+#define bFM3_MFS3_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42706230UL))
+#define bFM3_MFS3_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42706234UL))
+#define bFM3_MFS3_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42706238UL))
+#define bFM3_MFS3_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270623CUL))
+
+/* UART asynchronous channel 4 registers */
+#define bFM3_MFS4_UART_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_UART_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_UART_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_UART_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_UART_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_UART_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_UART_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_UART_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_UART_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_UART_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_UART_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_UART_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_UART_ESCR_P                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_UART_ESCR_PEN                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_UART_ESCR_INV                *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_UART_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_UART_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_UART_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_UART_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_UART_SSR_FRE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_UART_SSR_PE                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_UART_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_UART_RDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_TDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_BGR_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_BGR1_EXT                *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART synchronous channel 4 registers */
+#define bFM3_MFS4_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42708004UL))
+#define bFM3_MFS4_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART LIN channel 4 registers */
+#define bFM3_MFS4_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_LIN_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_LIN_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_LIN_SCR_MS                   *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_LIN_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* I2C channel 4 registers */
+#define bFM3_MFS4_I2C_SMR_ITST0                *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_I2C_SMR_ITST1                *((volatile unsigned int*)(0x42708004UL))
+#define bFM3_MFS4_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_I2C_SMR_MD0                  *((volatile unsigned int*)(0x42708014UL))
+#define bFM3_MFS4_I2C_SMR_MD1                  *((volatile unsigned int*)(0x42708018UL))
+#define bFM3_MFS4_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270801CUL))
+#define bFM3_MFS4_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427080B8UL))
+#define bFM3_MFS4_I2C_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42708200UL))
+#define bFM3_MFS4_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42708204UL))
+#define bFM3_MFS4_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42708208UL))
+#define bFM3_MFS4_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270820CUL))
+#define bFM3_MFS4_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42708210UL))
+#define bFM3_MFS4_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42708214UL))
+#define bFM3_MFS4_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42708218UL))
+#define bFM3_MFS4_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270821CUL))
+#define bFM3_MFS4_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42708220UL))
+#define bFM3_MFS4_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42708224UL))
+#define bFM3_MFS4_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42708228UL))
+#define bFM3_MFS4_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270822CUL))
+#define bFM3_MFS4_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42708230UL))
+#define bFM3_MFS4_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42708234UL))
+#define bFM3_MFS4_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42708238UL))
+#define bFM3_MFS4_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270823CUL))
+#define bFM3_MFS4_I2C_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART asynchronous channel 5 registers */
+#define bFM3_MFS5_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_UART_ESCR_P                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_UART_ESCR_INV                *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_UART_SSR_PE                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_UART_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_UART_RDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_TDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART synchronous channel 5 registers */
+#define bFM3_MFS5_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270A004UL))
+#define bFM3_MFS5_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART LIN channel 5 registers */
+#define bFM3_MFS5_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* I2C channel 5 registers */
+#define bFM3_MFS5_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270A004UL))
+#define bFM3_MFS5_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270A014UL))
+#define bFM3_MFS5_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270A018UL))
+#define bFM3_MFS5_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270A01CUL))
+#define bFM3_MFS5_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270A0B8UL))
+#define bFM3_MFS5_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270A200UL))
+#define bFM3_MFS5_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270A204UL))
+#define bFM3_MFS5_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270A208UL))
+#define bFM3_MFS5_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270A20CUL))
+#define bFM3_MFS5_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270A210UL))
+#define bFM3_MFS5_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270A214UL))
+#define bFM3_MFS5_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270A218UL))
+#define bFM3_MFS5_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270A21CUL))
+#define bFM3_MFS5_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270A220UL))
+#define bFM3_MFS5_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270A224UL))
+#define bFM3_MFS5_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270A228UL))
+#define bFM3_MFS5_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270A22CUL))
+#define bFM3_MFS5_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270A230UL))
+#define bFM3_MFS5_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270A234UL))
+#define bFM3_MFS5_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270A238UL))
+#define bFM3_MFS5_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270A23CUL))
+#define bFM3_MFS5_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART asynchronous channel 6 registers */
+#define bFM3_MFS6_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_UART_ESCR_P                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_UART_ESCR_INV                *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_UART_SSR_PE                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_UART_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_UART_RDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_TDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART synchronous channel 6 registers */
+#define bFM3_MFS6_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270C004UL))
+#define bFM3_MFS6_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART LIN channel 6 registers */
+#define bFM3_MFS6_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* I2C channel 6 registers */
+#define bFM3_MFS6_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270C004UL))
+#define bFM3_MFS6_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270C014UL))
+#define bFM3_MFS6_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270C018UL))
+#define bFM3_MFS6_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270C01CUL))
+#define bFM3_MFS6_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270C0B8UL))
+#define bFM3_MFS6_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270C200UL))
+#define bFM3_MFS6_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270C204UL))
+#define bFM3_MFS6_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270C208UL))
+#define bFM3_MFS6_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270C20CUL))
+#define bFM3_MFS6_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270C210UL))
+#define bFM3_MFS6_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270C214UL))
+#define bFM3_MFS6_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270C218UL))
+#define bFM3_MFS6_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270C21CUL))
+#define bFM3_MFS6_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270C220UL))
+#define bFM3_MFS6_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270C224UL))
+#define bFM3_MFS6_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270C228UL))
+#define bFM3_MFS6_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270C22CUL))
+#define bFM3_MFS6_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270C230UL))
+#define bFM3_MFS6_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270C234UL))
+#define bFM3_MFS6_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270C238UL))
+#define bFM3_MFS6_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270C23CUL))
+#define bFM3_MFS6_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART asynchronous channel 7 registers */
+#define bFM3_MFS7_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_UART_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_UART_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_UART_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_UART_ESCR_P                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_UART_ESCR_INV                *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_UART_SSR_PE                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_UART_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_UART_RDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_TDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART synchronous channel 7 registers */
+#define bFM3_MFS7_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270E004UL))
+#define bFM3_MFS7_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_CSIO_SMR_MD0                 *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_CSIO_SMR_MD1                 *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_CSIO_SMR_MD2                 *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART LIN channel 7 registers */
+#define bFM3_MFS7_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_LIN_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_LIN_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_LIN_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* I2C channel 7 registers */
+#define bFM3_MFS7_I2C_SMR_ITST0                *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_I2C_SMR_ITST1                *((volatile unsigned int*)(0x4270E004UL))
+#define bFM3_MFS7_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_I2C_SMR_MD0                  *((volatile unsigned int*)(0x4270E014UL))
+#define bFM3_MFS7_I2C_SMR_MD1                  *((volatile unsigned int*)(0x4270E018UL))
+#define bFM3_MFS7_I2C_SMR_MD2                  *((volatile unsigned int*)(0x4270E01CUL))
+#define bFM3_MFS7_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270E0B8UL))
+#define bFM3_MFS7_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270E200UL))
+#define bFM3_MFS7_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270E204UL))
+#define bFM3_MFS7_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270E208UL))
+#define bFM3_MFS7_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270E20CUL))
+#define bFM3_MFS7_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270E210UL))
+#define bFM3_MFS7_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270E214UL))
+#define bFM3_MFS7_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270E218UL))
+#define bFM3_MFS7_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270E21CUL))
+#define bFM3_MFS7_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270E220UL))
+#define bFM3_MFS7_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270E224UL))
+#define bFM3_MFS7_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270E228UL))
+#define bFM3_MFS7_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270E22CUL))
+#define bFM3_MFS7_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270E230UL))
+#define bFM3_MFS7_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270E234UL))
+#define bFM3_MFS7_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270E238UL))
+#define bFM3_MFS7_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270E23CUL))
+#define bFM3_MFS7_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* MFS Noise Filter Control registers */
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF00           *((volatile unsigned int*)(0x42710000UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF01           *((volatile unsigned int*)(0x42710004UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF10           *((volatile unsigned int*)(0x42710008UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF11           *((volatile unsigned int*)(0x4271000CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF20           *((volatile unsigned int*)(0x42710010UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF21           *((volatile unsigned int*)(0x42710014UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF30           *((volatile unsigned int*)(0x42710018UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF31           *((volatile unsigned int*)(0x4271001CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF40           *((volatile unsigned int*)(0x42710020UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF41           *((volatile unsigned int*)(0x42710024UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF50           *((volatile unsigned int*)(0x42710028UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF51           *((volatile unsigned int*)(0x4271002CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF60           *((volatile unsigned int*)(0x42710030UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF61           *((volatile unsigned int*)(0x42710034UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF70           *((volatile unsigned int*)(0x42710038UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF71           *((volatile unsigned int*)(0x4271003CUL))
+
+/* CRC registers */
+#define bFM3_CRC_CRCCR_INIT                    *((volatile unsigned int*)(0x42720000UL))
+#define bFM3_CRC_CRCCR_CRC32                   *((volatile unsigned int*)(0x42720004UL))
+#define bFM3_CRC_CRCCR_LTLEND                  *((volatile unsigned int*)(0x42720008UL))
+#define bFM3_CRC_CRCCR_LSBFST                  *((volatile unsigned int*)(0x4272000CUL))
+#define bFM3_CRC_CRCCR_CRCLTE                  *((volatile unsigned int*)(0x42720010UL))
+#define bFM3_CRC_CRCCR_CRCLSF                  *((volatile unsigned int*)(0x42720014UL))
+#define bFM3_CRC_CRCCR_FXOR                    *((volatile unsigned int*)(0x42720018UL))
+
+/* Watch counter registers */
+#define bFM3_WC_WCRD_CTR0                      *((volatile unsigned int*)(0x42740000UL))
+#define bFM3_WC_WCRD_CTR1                      *((volatile unsigned int*)(0x42740004UL))
+#define bFM3_WC_WCRD_CTR2                      *((volatile unsigned int*)(0x42740008UL))
+#define bFM3_WC_WCRD_CTR3                      *((volatile unsigned int*)(0x4274000CUL))
+#define bFM3_WC_WCRD_CTR4                      *((volatile unsigned int*)(0x42740010UL))
+#define bFM3_WC_WCRD_CTR5                      *((volatile unsigned int*)(0x42740014UL))
+#define bFM3_WC_WCRL_RLC0                      *((volatile unsigned int*)(0x42740020UL))
+#define bFM3_WC_WCRL_RLC1                      *((volatile unsigned int*)(0x42740024UL))
+#define bFM3_WC_WCRL_RLC2                      *((volatile unsigned int*)(0x42740028UL))
+#define bFM3_WC_WCRL_RLC3                      *((volatile unsigned int*)(0x4274002CUL))
+#define bFM3_WC_WCRL_RLC4                      *((volatile unsigned int*)(0x42740030UL))
+#define bFM3_WC_WCRL_RLC5                      *((volatile unsigned int*)(0x42740034UL))
+#define bFM3_WC_WCCR_WCIF                      *((volatile unsigned int*)(0x42740040UL))
+#define bFM3_WC_WCCR_WCIE                      *((volatile unsigned int*)(0x42740044UL))
+#define bFM3_WC_WCCR_CS0                       *((volatile unsigned int*)(0x42740048UL))
+#define bFM3_WC_WCCR_CS1                       *((volatile unsigned int*)(0x4274004CUL))
+#define bFM3_WC_WCCR_WCOP                      *((volatile unsigned int*)(0x42740058UL))
+#define bFM3_WC_WCCR_WCEN                      *((volatile unsigned int*)(0x4274005CUL))
+#define bFM3_WC_CLK_SEL_SEL_IN                 *((volatile unsigned int*)(0x42740200UL))
+#define bFM3_WC_CLK_SEL_SEL_OUT                *((volatile unsigned int*)(0x42740220UL))
+#define bFM3_WC_CLK_EN_CLK_EN                  *((volatile unsigned int*)(0x42740280UL))
+#define bFM3_WC_CLK_EN_CLK_EN_R                *((volatile unsigned int*)(0x42740284UL))
+
+/* External bus interface registers */
+#define bFM3_EXBUS_MODE0_WDTH0                 *((volatile unsigned int*)(0x427E0000UL))
+#define bFM3_EXBUS_MODE0_WDTH1                 *((volatile unsigned int*)(0x427E0004UL))
+#define bFM3_EXBUS_MODE0_RBMON                 *((volatile unsigned int*)(0x427E0008UL))
+#define bFM3_EXBUS_MODE0_WEOFF                 *((volatile unsigned int*)(0x427E000CUL))
+#define bFM3_EXBUS_MODE0_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE0_PAGE                  *((volatile unsigned int*)(0x427E0014UL))
+#define bFM3_EXBUS_MODE0_RDY                   *((volatile unsigned int*)(0x427E0018UL))
+#define bFM3_EXBUS_MODE0_SHRTDOUT              *((volatile unsigned int*)(0x427E001CUL))
+#define bFM3_EXBUS_MODE0_MPXMODE               *((volatile unsigned int*)(0x427E0020UL))
+#define bFM3_EXBUS_MODE0_ALEINV                *((volatile unsigned int*)(0x427E0024UL))
+#define bFM3_EXBUS_MODE0_MPXDOFF               *((volatile unsigned int*)(0x427E002CUL))
+#define bFM3_EXBUS_MODE0_MPXCSOF               *((volatile unsigned int*)(0x427E0030UL))
+#define bFM3_EXBUS_MODE0_MOEXEUP               *((volatile unsigned int*)(0x427E0034UL))
+#define bFM3_EXBUS_MODE1_WDTH0                 *((volatile unsigned int*)(0x427E0080UL))
+#define bFM3_EXBUS_MODE1_WDTH1                 *((volatile unsigned int*)(0x427E0084UL))
+#define bFM3_EXBUS_MODE1_RBMON                 *((volatile unsigned int*)(0x427E0088UL))
+#define bFM3_EXBUS_MODE1_WEOFF                 *((volatile unsigned int*)(0x427E008CUL))
+#define bFM3_EXBUS_MODE1_NAND                  *((volatile unsigned int*)(0x427E0090UL))
+#define bFM3_EXBUS_MODE1_PAGE                  *((volatile unsigned int*)(0x427E0094UL))
+#define bFM3_EXBUS_MODE1_RDY                   *((volatile unsigned int*)(0x427E0098UL))
+#define bFM3_EXBUS_MODE1_SHRTDOUT              *((volatile unsigned int*)(0x427E009CUL))
+#define bFM3_EXBUS_MODE1_MPXMODE               *((volatile unsigned int*)(0x427E00A0UL))
+#define bFM3_EXBUS_MODE1_ALEINV                *((volatile unsigned int*)(0x427E00A4UL))
+#define bFM3_EXBUS_MODE1_MPXDOFF               *((volatile unsigned int*)(0x427E00ACUL))
+#define bFM3_EXBUS_MODE1_MPXCSOF               *((volatile unsigned int*)(0x427E00B0UL))
+#define bFM3_EXBUS_MODE1_MOEXEUP               *((volatile unsigned int*)(0x427E00B4UL))
+#define bFM3_EXBUS_MODE2_WDTH0                 *((volatile unsigned int*)(0x427E0100UL))
+#define bFM3_EXBUS_MODE2_WDTH1                 *((volatile unsigned int*)(0x427E0104UL))
+#define bFM3_EXBUS_MODE2_RBMON                 *((volatile unsigned int*)(0x427E0108UL))
+#define bFM3_EXBUS_MODE2_WEOFF                 *((volatile unsigned int*)(0x427E010CUL))
+#define bFM3_EXBUS_MODE2_NAND                  *((volatile unsigned int*)(0x427E0110UL))
+#define bFM3_EXBUS_MODE2_PAGE                  *((volatile unsigned int*)(0x427E0114UL))
+#define bFM3_EXBUS_MODE2_RDY                   *((volatile unsigned int*)(0x427E0118UL))
+#define bFM3_EXBUS_MODE2_SHRTDOUT              *((volatile unsigned int*)(0x427E011CUL))
+#define bFM3_EXBUS_MODE2_MPXMODE               *((volatile unsigned int*)(0x427E0120UL))
+#define bFM3_EXBUS_MODE2_ALEINV                *((volatile unsigned int*)(0x427E0124UL))
+#define bFM3_EXBUS_MODE2_MPXDOFF               *((volatile unsigned int*)(0x427E012CUL))
+#define bFM3_EXBUS_MODE2_MPXCSOF               *((volatile unsigned int*)(0x427E0130UL))
+#define bFM3_EXBUS_MODE2_MOEXEUP               *((volatile unsigned int*)(0x427E0134UL))
+#define bFM3_EXBUS_MODE3_WDTH0                 *((volatile unsigned int*)(0x427E0180UL))
+#define bFM3_EXBUS_MODE3_WDTH1                 *((volatile unsigned int*)(0x427E0184UL))
+#define bFM3_EXBUS_MODE3_RBMON                 *((volatile unsigned int*)(0x427E0188UL))
+#define bFM3_EXBUS_MODE3_WEOFF                 *((volatile unsigned int*)(0x427E018CUL))
+#define bFM3_EXBUS_MODE3_NAND                  *((volatile unsigned int*)(0x427E0190UL))
+#define bFM3_EXBUS_MODE3_PAGE                  *((volatile unsigned int*)(0x427E0194UL))
+#define bFM3_EXBUS_MODE3_RDY                   *((volatile unsigned int*)(0x427E0198UL))
+#define bFM3_EXBUS_MODE3_SHRTDOUT              *((volatile unsigned int*)(0x427E019CUL))
+#define bFM3_EXBUS_MODE3_MPXMODE               *((volatile unsigned int*)(0x427E01A0UL))
+#define bFM3_EXBUS_MODE3_ALEINV                *((volatile unsigned int*)(0x427E01A4UL))
+#define bFM3_EXBUS_MODE3_MPXDOFF               *((volatile unsigned int*)(0x427E01ACUL))
+#define bFM3_EXBUS_MODE3_MPXCSOF               *((volatile unsigned int*)(0x427E01B0UL))
+#define bFM3_EXBUS_MODE3_MOEXEUP               *((volatile unsigned int*)(0x427E01B4UL))
+#define bFM3_EXBUS_MODE4_WDTH0                 *((volatile unsigned int*)(0x427E0200UL))
+#define bFM3_EXBUS_MODE4_WDTH1                 *((volatile unsigned int*)(0x427E0204UL))
+#define bFM3_EXBUS_MODE4_RBMON                 *((volatile unsigned int*)(0x427E0208UL))
+#define bFM3_EXBUS_MODE4_WEOFF                 *((volatile unsigned int*)(0x427E020CUL))
+#define bFM3_EXBUS_MODE4_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE4_PAGE                  *((volatile unsigned int*)(0x427E0214UL))
+#define bFM3_EXBUS_MODE4_RDY                   *((volatile unsigned int*)(0x427E0218UL))
+#define bFM3_EXBUS_MODE4_SHRTDOUT              *((volatile unsigned int*)(0x427E021CUL))
+#define bFM3_EXBUS_MODE4_MPXMODE               *((volatile unsigned int*)(0x427E0220UL))
+#define bFM3_EXBUS_MODE4_ALEINV                *((volatile unsigned int*)(0x427E0224UL))
+#define bFM3_EXBUS_MODE4_MPXDOFF               *((volatile unsigned int*)(0x427E022CUL))
+#define bFM3_EXBUS_MODE4_MPXCSOF               *((volatile unsigned int*)(0x427E0230UL))
+#define bFM3_EXBUS_MODE4_MOEXEUP               *((volatile unsigned int*)(0x427E0234UL))
+#define bFM3_EXBUS_MODE5_WDTH0                 *((volatile unsigned int*)(0x427E0280UL))
+#define bFM3_EXBUS_MODE5_WDTH1                 *((volatile unsigned int*)(0x427E0284UL))
+#define bFM3_EXBUS_MODE5_RBMON                 *((volatile unsigned int*)(0x427E0288UL))
+#define bFM3_EXBUS_MODE5_WEOFF                 *((volatile unsigned int*)(0x427E028CUL))
+#define bFM3_EXBUS_MODE5_NAND                  *((volatile unsigned int*)(0x427E0290UL))
+#define bFM3_EXBUS_MODE5_PAGE                  *((volatile unsigned int*)(0x427E0294UL))
+#define bFM3_EXBUS_MODE5_RDY                   *((volatile unsigned int*)(0x427E0298UL))
+#define bFM3_EXBUS_MODE5_SHRTDOUT              *((volatile unsigned int*)(0x427E029CUL))
+#define bFM3_EXBUS_MODE5_MPXMODE               *((volatile unsigned int*)(0x427E02A0UL))
+#define bFM3_EXBUS_MODE5_ALEINV                *((volatile unsigned int*)(0x427E02A4UL))
+#define bFM3_EXBUS_MODE5_MPXDOFF               *((volatile unsigned int*)(0x427E02ACUL))
+#define bFM3_EXBUS_MODE5_MPXCSOF               *((volatile unsigned int*)(0x427E02B0UL))
+#define bFM3_EXBUS_MODE5_MOEXEUP               *((volatile unsigned int*)(0x427E02B4UL))
+#define bFM3_EXBUS_MODE6_WDTH0                 *((volatile unsigned int*)(0x427E0300UL))
+#define bFM3_EXBUS_MODE6_WDTH1                 *((volatile unsigned int*)(0x427E0304UL))
+#define bFM3_EXBUS_MODE6_RBMON                 *((volatile unsigned int*)(0x427E0308UL))
+#define bFM3_EXBUS_MODE6_WEOFF                 *((volatile unsigned int*)(0x427E030CUL))
+#define bFM3_EXBUS_MODE6_NAND                  *((volatile unsigned int*)(0x427E0310UL))
+#define bFM3_EXBUS_MODE6_PAGE                  *((volatile unsigned int*)(0x427E0314UL))
+#define bFM3_EXBUS_MODE6_RDY                   *((volatile unsigned int*)(0x427E0318UL))
+#define bFM3_EXBUS_MODE6_SHRTDOUT              *((volatile unsigned int*)(0x427E031CUL))
+#define bFM3_EXBUS_MODE6_MPXMODE               *((volatile unsigned int*)(0x427E0320UL))
+#define bFM3_EXBUS_MODE6_ALEINV                *((volatile unsigned int*)(0x427E0324UL))
+#define bFM3_EXBUS_MODE6_MPXDOFF               *((volatile unsigned int*)(0x427E032CUL))
+#define bFM3_EXBUS_MODE6_MPXCSOF               *((volatile unsigned int*)(0x427E0330UL))
+#define bFM3_EXBUS_MODE6_MOEXEUP               *((volatile unsigned int*)(0x427E0334UL))
+#define bFM3_EXBUS_MODE7_WDTH0                 *((volatile unsigned int*)(0x427E0380UL))
+#define bFM3_EXBUS_MODE7_WDTH1                 *((volatile unsigned int*)(0x427E0384UL))
+#define bFM3_EXBUS_MODE7_RBMON                 *((volatile unsigned int*)(0x427E0388UL))
+#define bFM3_EXBUS_MODE7_WEOFF                 *((volatile unsigned int*)(0x427E038CUL))
+#define bFM3_EXBUS_MODE7_NAND                  *((volatile unsigned int*)(0x427E0390UL))
+#define bFM3_EXBUS_MODE7_PAGE                  *((volatile unsigned int*)(0x427E0394UL))
+#define bFM3_EXBUS_MODE7_RDY                   *((volatile unsigned int*)(0x427E0398UL))
+#define bFM3_EXBUS_MODE7_SHRTDOUT              *((volatile unsigned int*)(0x427E039CUL))
+#define bFM3_EXBUS_MODE7_MPXMODE               *((volatile unsigned int*)(0x427E03A0UL))
+#define bFM3_EXBUS_MODE7_ALEINV                *((volatile unsigned int*)(0x427E03A4UL))
+#define bFM3_EXBUS_MODE7_MPXDOFF               *((volatile unsigned int*)(0x427E03ACUL))
+#define bFM3_EXBUS_MODE7_MPXCSOF               *((volatile unsigned int*)(0x427E03B0UL))
+#define bFM3_EXBUS_MODE7_MOEXEUP               *((volatile unsigned int*)(0x427E03B4UL))
+#define bFM3_EXBUS_TIM0_RACC0                  *((volatile unsigned int*)(0x427E0400UL))
+#define bFM3_EXBUS_TIM0_RACC1                  *((volatile unsigned int*)(0x427E0404UL))
+#define bFM3_EXBUS_TIM0_RACC2                  *((volatile unsigned int*)(0x427E0408UL))
+#define bFM3_EXBUS_TIM0_RACC3                  *((volatile unsigned int*)(0x427E040CUL))
+#define bFM3_EXBUS_TIM0_RADC0                  *((volatile unsigned int*)(0x427E0410UL))
+#define bFM3_EXBUS_TIM0_RADC1                  *((volatile unsigned int*)(0x427E0414UL))
+#define bFM3_EXBUS_TIM0_RADC2                  *((volatile unsigned int*)(0x427E0418UL))
+#define bFM3_EXBUS_TIM0_RADC3                  *((volatile unsigned int*)(0x427E041CUL))
+#define bFM3_EXBUS_TIM0_FRADC0                 *((volatile unsigned int*)(0x427E0420UL))
+#define bFM3_EXBUS_TIM0_FRADC1                 *((volatile unsigned int*)(0x427E0424UL))
+#define bFM3_EXBUS_TIM0_FRADC2                 *((volatile unsigned int*)(0x427E0428UL))
+#define bFM3_EXBUS_TIM0_FRADC3                 *((volatile unsigned int*)(0x427E042CUL))
+#define bFM3_EXBUS_TIM0_RIDLC0                 *((volatile unsigned int*)(0x427E0430UL))
+#define bFM3_EXBUS_TIM0_RIDLC1                 *((volatile unsigned int*)(0x427E0434UL))
+#define bFM3_EXBUS_TIM0_RIDLC2                 *((volatile unsigned int*)(0x427E0438UL))
+#define bFM3_EXBUS_TIM0_RIDLC3                 *((volatile unsigned int*)(0x427E043CUL))
+#define bFM3_EXBUS_TIM0_WACC0                  *((volatile unsigned int*)(0x427E0440UL))
+#define bFM3_EXBUS_TIM0_WACC1                  *((volatile unsigned int*)(0x427E0444UL))
+#define bFM3_EXBUS_TIM0_WACC2                  *((volatile unsigned int*)(0x427E0448UL))
+#define bFM3_EXBUS_TIM0_WACC3                  *((volatile unsigned int*)(0x427E044CUL))
+#define bFM3_EXBUS_TIM0_WADC0                  *((volatile unsigned int*)(0x427E0450UL))
+#define bFM3_EXBUS_TIM0_WADC1                  *((volatile unsigned int*)(0x427E0454UL))
+#define bFM3_EXBUS_TIM0_WADC2                  *((volatile unsigned int*)(0x427E0458UL))
+#define bFM3_EXBUS_TIM0_WADC3                  *((volatile unsigned int*)(0x427E045CUL))
+#define bFM3_EXBUS_TIM0_WWEC0                  *((volatile unsigned int*)(0x427E0460UL))
+#define bFM3_EXBUS_TIM0_WWEC1                  *((volatile unsigned int*)(0x427E0464UL))
+#define bFM3_EXBUS_TIM0_WWEC2                  *((volatile unsigned int*)(0x427E0468UL))
+#define bFM3_EXBUS_TIM0_WWEC3                  *((volatile unsigned int*)(0x427E046CUL))
+#define bFM3_EXBUS_TIM0_WIDLC0                 *((volatile unsigned int*)(0x427E0470UL))
+#define bFM3_EXBUS_TIM0_WIDLC1                 *((volatile unsigned int*)(0x427E0474UL))
+#define bFM3_EXBUS_TIM0_WIDLC2                 *((volatile unsigned int*)(0x427E0478UL))
+#define bFM3_EXBUS_TIM0_WIDLC3                 *((volatile unsigned int*)(0x427E047CUL))
+#define bFM3_EXBUS_TIM1_RACC0                  *((volatile unsigned int*)(0x427E0480UL))
+#define bFM3_EXBUS_TIM1_RACC1                  *((volatile unsigned int*)(0x427E0484UL))
+#define bFM3_EXBUS_TIM1_RACC2                  *((volatile unsigned int*)(0x427E0488UL))
+#define bFM3_EXBUS_TIM1_RACC3                  *((volatile unsigned int*)(0x427E048CUL))
+#define bFM3_EXBUS_TIM1_RADC0                  *((volatile unsigned int*)(0x427E0490UL))
+#define bFM3_EXBUS_TIM1_RADC1                  *((volatile unsigned int*)(0x427E0494UL))
+#define bFM3_EXBUS_TIM1_RADC2                  *((volatile unsigned int*)(0x427E0498UL))
+#define bFM3_EXBUS_TIM1_RADC3                  *((volatile unsigned int*)(0x427E049CUL))
+#define bFM3_EXBUS_TIM1_FRADC0                 *((volatile unsigned int*)(0x427E04A0UL))
+#define bFM3_EXBUS_TIM1_FRADC1                 *((volatile unsigned int*)(0x427E04A4UL))
+#define bFM3_EXBUS_TIM1_FRADC2                 *((volatile unsigned int*)(0x427E04A8UL))
+#define bFM3_EXBUS_TIM1_FRADC3                 *((volatile unsigned int*)(0x427E04ACUL))
+#define bFM3_EXBUS_TIM1_RIDLC0                 *((volatile unsigned int*)(0x427E04B0UL))
+#define bFM3_EXBUS_TIM1_RIDLC1                 *((volatile unsigned int*)(0x427E04B4UL))
+#define bFM3_EXBUS_TIM1_RIDLC2                 *((volatile unsigned int*)(0x427E04B8UL))
+#define bFM3_EXBUS_TIM1_RIDLC3                 *((volatile unsigned int*)(0x427E04BCUL))
+#define bFM3_EXBUS_TIM1_WACC0                  *((volatile unsigned int*)(0x427E04C0UL))
+#define bFM3_EXBUS_TIM1_WACC1                  *((volatile unsigned int*)(0x427E04C4UL))
+#define bFM3_EXBUS_TIM1_WACC2                  *((volatile unsigned int*)(0x427E04C8UL))
+#define bFM3_EXBUS_TIM1_WACC3                  *((volatile unsigned int*)(0x427E04CCUL))
+#define bFM3_EXBUS_TIM1_WADC0                  *((volatile unsigned int*)(0x427E04D0UL))
+#define bFM3_EXBUS_TIM1_WADC1                  *((volatile unsigned int*)(0x427E04D4UL))
+#define bFM3_EXBUS_TIM1_WADC2                  *((volatile unsigned int*)(0x427E04D8UL))
+#define bFM3_EXBUS_TIM1_WADC3                  *((volatile unsigned int*)(0x427E04DCUL))
+#define bFM3_EXBUS_TIM1_WWEC0                  *((volatile unsigned int*)(0x427E04E0UL))
+#define bFM3_EXBUS_TIM1_WWEC1                  *((volatile unsigned int*)(0x427E04E4UL))
+#define bFM3_EXBUS_TIM1_WWEC2                  *((volatile unsigned int*)(0x427E04E8UL))
+#define bFM3_EXBUS_TIM1_WWEC3                  *((volatile unsigned int*)(0x427E04ECUL))
+#define bFM3_EXBUS_TIM1_WIDLC0                 *((volatile unsigned int*)(0x427E04F0UL))
+#define bFM3_EXBUS_TIM1_WIDLC1                 *((volatile unsigned int*)(0x427E04F4UL))
+#define bFM3_EXBUS_TIM1_WIDLC2                 *((volatile unsigned int*)(0x427E04F8UL))
+#define bFM3_EXBUS_TIM1_WIDLC3                 *((volatile unsigned int*)(0x427E04FCUL))
+#define bFM3_EXBUS_TIM2_RACC0                  *((volatile unsigned int*)(0x427E0500UL))
+#define bFM3_EXBUS_TIM2_RACC1                  *((volatile unsigned int*)(0x427E0504UL))
+#define bFM3_EXBUS_TIM2_RACC2                  *((volatile unsigned int*)(0x427E0508UL))
+#define bFM3_EXBUS_TIM2_RACC3                  *((volatile unsigned int*)(0x427E050CUL))
+#define bFM3_EXBUS_TIM2_RADC0                  *((volatile unsigned int*)(0x427E0510UL))
+#define bFM3_EXBUS_TIM2_RADC1                  *((volatile unsigned int*)(0x427E0514UL))
+#define bFM3_EXBUS_TIM2_RADC2                  *((volatile unsigned int*)(0x427E0518UL))
+#define bFM3_EXBUS_TIM2_RADC3                  *((volatile unsigned int*)(0x427E051CUL))
+#define bFM3_EXBUS_TIM2_FRADC0                 *((volatile unsigned int*)(0x427E0520UL))
+#define bFM3_EXBUS_TIM2_FRADC1                 *((volatile unsigned int*)(0x427E0524UL))
+#define bFM3_EXBUS_TIM2_FRADC2                 *((volatile unsigned int*)(0x427E0528UL))
+#define bFM3_EXBUS_TIM2_FRADC3                 *((volatile unsigned int*)(0x427E052CUL))
+#define bFM3_EXBUS_TIM2_RIDLC0                 *((volatile unsigned int*)(0x427E0530UL))
+#define bFM3_EXBUS_TIM2_RIDLC1                 *((volatile unsigned int*)(0x427E0534UL))
+#define bFM3_EXBUS_TIM2_RIDLC2                 *((volatile unsigned int*)(0x427E0538UL))
+#define bFM3_EXBUS_TIM2_RIDLC3                 *((volatile unsigned int*)(0x427E053CUL))
+#define bFM3_EXBUS_TIM2_WACC0                  *((volatile unsigned int*)(0x427E0540UL))
+#define bFM3_EXBUS_TIM2_WACC1                  *((volatile unsigned int*)(0x427E0544UL))
+#define bFM3_EXBUS_TIM2_WACC2                  *((volatile unsigned int*)(0x427E0548UL))
+#define bFM3_EXBUS_TIM2_WACC3                  *((volatile unsigned int*)(0x427E054CUL))
+#define bFM3_EXBUS_TIM2_WADC0                  *((volatile unsigned int*)(0x427E0550UL))
+#define bFM3_EXBUS_TIM2_WADC1                  *((volatile unsigned int*)(0x427E0554UL))
+#define bFM3_EXBUS_TIM2_WADC2                  *((volatile unsigned int*)(0x427E0558UL))
+#define bFM3_EXBUS_TIM2_WADC3                  *((volatile unsigned int*)(0x427E055CUL))
+#define bFM3_EXBUS_TIM2_WWEC0                  *((volatile unsigned int*)(0x427E0560UL))
+#define bFM3_EXBUS_TIM2_WWEC1                  *((volatile unsigned int*)(0x427E0564UL))
+#define bFM3_EXBUS_TIM2_WWEC2                  *((volatile unsigned int*)(0x427E0568UL))
+#define bFM3_EXBUS_TIM2_WWEC3                  *((volatile unsigned int*)(0x427E056CUL))
+#define bFM3_EXBUS_TIM2_WIDLC0                 *((volatile unsigned int*)(0x427E0570UL))
+#define bFM3_EXBUS_TIM2_WIDLC1                 *((volatile unsigned int*)(0x427E0574UL))
+#define bFM3_EXBUS_TIM2_WIDLC2                 *((volatile unsigned int*)(0x427E0578UL))
+#define bFM3_EXBUS_TIM2_WIDLC3                 *((volatile unsigned int*)(0x427E057CUL))
+#define bFM3_EXBUS_TIM3_RACC0                  *((volatile unsigned int*)(0x427E0580UL))
+#define bFM3_EXBUS_TIM3_RACC1                  *((volatile unsigned int*)(0x427E0584UL))
+#define bFM3_EXBUS_TIM3_RACC2                  *((volatile unsigned int*)(0x427E0588UL))
+#define bFM3_EXBUS_TIM3_RACC3                  *((volatile unsigned int*)(0x427E058CUL))
+#define bFM3_EXBUS_TIM3_RADC0                  *((volatile unsigned int*)(0x427E0590UL))
+#define bFM3_EXBUS_TIM3_RADC1                  *((volatile unsigned int*)(0x427E0594UL))
+#define bFM3_EXBUS_TIM3_RADC2                  *((volatile unsigned int*)(0x427E0598UL))
+#define bFM3_EXBUS_TIM3_RADC3                  *((volatile unsigned int*)(0x427E059CUL))
+#define bFM3_EXBUS_TIM3_FRADC0                 *((volatile unsigned int*)(0x427E05A0UL))
+#define bFM3_EXBUS_TIM3_FRADC1                 *((volatile unsigned int*)(0x427E05A4UL))
+#define bFM3_EXBUS_TIM3_FRADC2                 *((volatile unsigned int*)(0x427E05A8UL))
+#define bFM3_EXBUS_TIM3_FRADC3                 *((volatile unsigned int*)(0x427E05ACUL))
+#define bFM3_EXBUS_TIM3_RIDLC0                 *((volatile unsigned int*)(0x427E05B0UL))
+#define bFM3_EXBUS_TIM3_RIDLC1                 *((volatile unsigned int*)(0x427E05B4UL))
+#define bFM3_EXBUS_TIM3_RIDLC2                 *((volatile unsigned int*)(0x427E05B8UL))
+#define bFM3_EXBUS_TIM3_RIDLC3                 *((volatile unsigned int*)(0x427E05BCUL))
+#define bFM3_EXBUS_TIM3_WACC0                  *((volatile unsigned int*)(0x427E05C0UL))
+#define bFM3_EXBUS_TIM3_WACC1                  *((volatile unsigned int*)(0x427E05C4UL))
+#define bFM3_EXBUS_TIM3_WACC2                  *((volatile unsigned int*)(0x427E05C8UL))
+#define bFM3_EXBUS_TIM3_WACC3                  *((volatile unsigned int*)(0x427E05CCUL))
+#define bFM3_EXBUS_TIM3_WADC0                  *((volatile unsigned int*)(0x427E05D0UL))
+#define bFM3_EXBUS_TIM3_WADC1                  *((volatile unsigned int*)(0x427E05D4UL))
+#define bFM3_EXBUS_TIM3_WADC2                  *((volatile unsigned int*)(0x427E05D8UL))
+#define bFM3_EXBUS_TIM3_WADC3                  *((volatile unsigned int*)(0x427E05DCUL))
+#define bFM3_EXBUS_TIM3_WWEC0                  *((volatile unsigned int*)(0x427E05E0UL))
+#define bFM3_EXBUS_TIM3_WWEC1                  *((volatile unsigned int*)(0x427E05E4UL))
+#define bFM3_EXBUS_TIM3_WWEC2                  *((volatile unsigned int*)(0x427E05E8UL))
+#define bFM3_EXBUS_TIM3_WWEC3                  *((volatile unsigned int*)(0x427E05ECUL))
+#define bFM3_EXBUS_TIM3_WIDLC0                 *((volatile unsigned int*)(0x427E05F0UL))
+#define bFM3_EXBUS_TIM3_WIDLC1                 *((volatile unsigned int*)(0x427E05F4UL))
+#define bFM3_EXBUS_TIM3_WIDLC2                 *((volatile unsigned int*)(0x427E05F8UL))
+#define bFM3_EXBUS_TIM3_WIDLC3                 *((volatile unsigned int*)(0x427E05FCUL))
+#define bFM3_EXBUS_TIM4_RACC0                  *((volatile unsigned int*)(0x427E0600UL))
+#define bFM3_EXBUS_TIM4_RACC1                  *((volatile unsigned int*)(0x427E0604UL))
+#define bFM3_EXBUS_TIM4_RACC2                  *((volatile unsigned int*)(0x427E0608UL))
+#define bFM3_EXBUS_TIM4_RACC3                  *((volatile unsigned int*)(0x427E060CUL))
+#define bFM3_EXBUS_TIM4_RADC0                  *((volatile unsigned int*)(0x427E0610UL))
+#define bFM3_EXBUS_TIM4_RADC1                  *((volatile unsigned int*)(0x427E0614UL))
+#define bFM3_EXBUS_TIM4_RADC2                  *((volatile unsigned int*)(0x427E0618UL))
+#define bFM3_EXBUS_TIM4_RADC3                  *((volatile unsigned int*)(0x427E061CUL))
+#define bFM3_EXBUS_TIM4_FRADC0                 *((volatile unsigned int*)(0x427E0620UL))
+#define bFM3_EXBUS_TIM4_FRADC1                 *((volatile unsigned int*)(0x427E0624UL))
+#define bFM3_EXBUS_TIM4_FRADC2                 *((volatile unsigned int*)(0x427E0628UL))
+#define bFM3_EXBUS_TIM4_FRADC3                 *((volatile unsigned int*)(0x427E062CUL))
+#define bFM3_EXBUS_TIM4_RIDLC0                 *((volatile unsigned int*)(0x427E0630UL))
+#define bFM3_EXBUS_TIM4_RIDLC1                 *((volatile unsigned int*)(0x427E0634UL))
+#define bFM3_EXBUS_TIM4_RIDLC2                 *((volatile unsigned int*)(0x427E0638UL))
+#define bFM3_EXBUS_TIM4_RIDLC3                 *((volatile unsigned int*)(0x427E063CUL))
+#define bFM3_EXBUS_TIM4_WACC0                  *((volatile unsigned int*)(0x427E0640UL))
+#define bFM3_EXBUS_TIM4_WACC1                  *((volatile unsigned int*)(0x427E0644UL))
+#define bFM3_EXBUS_TIM4_WACC2                  *((volatile unsigned int*)(0x427E0648UL))
+#define bFM3_EXBUS_TIM4_WACC3                  *((volatile unsigned int*)(0x427E064CUL))
+#define bFM3_EXBUS_TIM4_WADC0                  *((volatile unsigned int*)(0x427E0650UL))
+#define bFM3_EXBUS_TIM4_WADC1                  *((volatile unsigned int*)(0x427E0654UL))
+#define bFM3_EXBUS_TIM4_WADC2                  *((volatile unsigned int*)(0x427E0658UL))
+#define bFM3_EXBUS_TIM4_WADC3                  *((volatile unsigned int*)(0x427E065CUL))
+#define bFM3_EXBUS_TIM4_WWEC0                  *((volatile unsigned int*)(0x427E0660UL))
+#define bFM3_EXBUS_TIM4_WWEC1                  *((volatile unsigned int*)(0x427E0664UL))
+#define bFM3_EXBUS_TIM4_WWEC2                  *((volatile unsigned int*)(0x427E0668UL))
+#define bFM3_EXBUS_TIM4_WWEC3                  *((volatile unsigned int*)(0x427E066CUL))
+#define bFM3_EXBUS_TIM4_WIDLC0                 *((volatile unsigned int*)(0x427E0670UL))
+#define bFM3_EXBUS_TIM4_WIDLC1                 *((volatile unsigned int*)(0x427E0674UL))
+#define bFM3_EXBUS_TIM4_WIDLC2                 *((volatile unsigned int*)(0x427E0678UL))
+#define bFM3_EXBUS_TIM4_WIDLC3                 *((volatile unsigned int*)(0x427E067CUL))
+#define bFM3_EXBUS_TIM5_RACC0                  *((volatile unsigned int*)(0x427E0680UL))
+#define bFM3_EXBUS_TIM5_RACC1                  *((volatile unsigned int*)(0x427E0684UL))
+#define bFM3_EXBUS_TIM5_RACC2                  *((volatile unsigned int*)(0x427E0688UL))
+#define bFM3_EXBUS_TIM5_RACC3                  *((volatile unsigned int*)(0x427E068CUL))
+#define bFM3_EXBUS_TIM5_RADC0                  *((volatile unsigned int*)(0x427E0690UL))
+#define bFM3_EXBUS_TIM5_RADC1                  *((volatile unsigned int*)(0x427E0694UL))
+#define bFM3_EXBUS_TIM5_RADC2                  *((volatile unsigned int*)(0x427E0698UL))
+#define bFM3_EXBUS_TIM5_RADC3                  *((volatile unsigned int*)(0x427E069CUL))
+#define bFM3_EXBUS_TIM5_FRADC0                 *((volatile unsigned int*)(0x427E06A0UL))
+#define bFM3_EXBUS_TIM5_FRADC1                 *((volatile unsigned int*)(0x427E06A4UL))
+#define bFM3_EXBUS_TIM5_FRADC2                 *((volatile unsigned int*)(0x427E06A8UL))
+#define bFM3_EXBUS_TIM5_FRADC3                 *((volatile unsigned int*)(0x427E06ACUL))
+#define bFM3_EXBUS_TIM5_RIDLC0                 *((volatile unsigned int*)(0x427E06B0UL))
+#define bFM3_EXBUS_TIM5_RIDLC1                 *((volatile unsigned int*)(0x427E06B4UL))
+#define bFM3_EXBUS_TIM5_RIDLC2                 *((volatile unsigned int*)(0x427E06B8UL))
+#define bFM3_EXBUS_TIM5_RIDLC3                 *((volatile unsigned int*)(0x427E06BCUL))
+#define bFM3_EXBUS_TIM5_WACC0                  *((volatile unsigned int*)(0x427E06C0UL))
+#define bFM3_EXBUS_TIM5_WACC1                  *((volatile unsigned int*)(0x427E06C4UL))
+#define bFM3_EXBUS_TIM5_WACC2                  *((volatile unsigned int*)(0x427E06C8UL))
+#define bFM3_EXBUS_TIM5_WACC3                  *((volatile unsigned int*)(0x427E06CCUL))
+#define bFM3_EXBUS_TIM5_WADC0                  *((volatile unsigned int*)(0x427E06D0UL))
+#define bFM3_EXBUS_TIM5_WADC1                  *((volatile unsigned int*)(0x427E06D4UL))
+#define bFM3_EXBUS_TIM5_WADC2                  *((volatile unsigned int*)(0x427E06D8UL))
+#define bFM3_EXBUS_TIM5_WADC3                  *((volatile unsigned int*)(0x427E06DCUL))
+#define bFM3_EXBUS_TIM5_WWEC0                  *((volatile unsigned int*)(0x427E06E0UL))
+#define bFM3_EXBUS_TIM5_WWEC1                  *((volatile unsigned int*)(0x427E06E4UL))
+#define bFM3_EXBUS_TIM5_WWEC2                  *((volatile unsigned int*)(0x427E06E8UL))
+#define bFM3_EXBUS_TIM5_WWEC3                  *((volatile unsigned int*)(0x427E06ECUL))
+#define bFM3_EXBUS_TIM5_WIDLC0                 *((volatile unsigned int*)(0x427E06F0UL))
+#define bFM3_EXBUS_TIM5_WIDLC1                 *((volatile unsigned int*)(0x427E06F4UL))
+#define bFM3_EXBUS_TIM5_WIDLC2                 *((volatile unsigned int*)(0x427E06F8UL))
+#define bFM3_EXBUS_TIM5_WIDLC3                 *((volatile unsigned int*)(0x427E06FCUL))
+#define bFM3_EXBUS_TIM6_RACC0                  *((volatile unsigned int*)(0x427E0700UL))
+#define bFM3_EXBUS_TIM6_RACC1                  *((volatile unsigned int*)(0x427E0704UL))
+#define bFM3_EXBUS_TIM6_RACC2                  *((volatile unsigned int*)(0x427E0708UL))
+#define bFM3_EXBUS_TIM6_RACC3                  *((volatile unsigned int*)(0x427E070CUL))
+#define bFM3_EXBUS_TIM6_RADC0                  *((volatile unsigned int*)(0x427E0710UL))
+#define bFM3_EXBUS_TIM6_RADC1                  *((volatile unsigned int*)(0x427E0714UL))
+#define bFM3_EXBUS_TIM6_RADC2                  *((volatile unsigned int*)(0x427E0718UL))
+#define bFM3_EXBUS_TIM6_RADC3                  *((volatile unsigned int*)(0x427E071CUL))
+#define bFM3_EXBUS_TIM6_FRADC0                 *((volatile unsigned int*)(0x427E0720UL))
+#define bFM3_EXBUS_TIM6_FRADC1                 *((volatile unsigned int*)(0x427E0724UL))
+#define bFM3_EXBUS_TIM6_FRADC2                 *((volatile unsigned int*)(0x427E0728UL))
+#define bFM3_EXBUS_TIM6_FRADC3                 *((volatile unsigned int*)(0x427E072CUL))
+#define bFM3_EXBUS_TIM6_RIDLC0                 *((volatile unsigned int*)(0x427E0730UL))
+#define bFM3_EXBUS_TIM6_RIDLC1                 *((volatile unsigned int*)(0x427E0734UL))
+#define bFM3_EXBUS_TIM6_RIDLC2                 *((volatile unsigned int*)(0x427E0738UL))
+#define bFM3_EXBUS_TIM6_RIDLC3                 *((volatile unsigned int*)(0x427E073CUL))
+#define bFM3_EXBUS_TIM6_WACC0                  *((volatile unsigned int*)(0x427E0740UL))
+#define bFM3_EXBUS_TIM6_WACC1                  *((volatile unsigned int*)(0x427E0744UL))
+#define bFM3_EXBUS_TIM6_WACC2                  *((volatile unsigned int*)(0x427E0748UL))
+#define bFM3_EXBUS_TIM6_WACC3                  *((volatile unsigned int*)(0x427E074CUL))
+#define bFM3_EXBUS_TIM6_WADC0                  *((volatile unsigned int*)(0x427E0750UL))
+#define bFM3_EXBUS_TIM6_WADC1                  *((volatile unsigned int*)(0x427E0754UL))
+#define bFM3_EXBUS_TIM6_WADC2                  *((volatile unsigned int*)(0x427E0758UL))
+#define bFM3_EXBUS_TIM6_WADC3                  *((volatile unsigned int*)(0x427E075CUL))
+#define bFM3_EXBUS_TIM6_WWEC0                  *((volatile unsigned int*)(0x427E0760UL))
+#define bFM3_EXBUS_TIM6_WWEC1                  *((volatile unsigned int*)(0x427E0764UL))
+#define bFM3_EXBUS_TIM6_WWEC2                  *((volatile unsigned int*)(0x427E0768UL))
+#define bFM3_EXBUS_TIM6_WWEC3                  *((volatile unsigned int*)(0x427E076CUL))
+#define bFM3_EXBUS_TIM6_WIDLC0                 *((volatile unsigned int*)(0x427E0770UL))
+#define bFM3_EXBUS_TIM6_WIDLC1                 *((volatile unsigned int*)(0x427E0774UL))
+#define bFM3_EXBUS_TIM6_WIDLC2                 *((volatile unsigned int*)(0x427E0778UL))
+#define bFM3_EXBUS_TIM6_WIDLC3                 *((volatile unsigned int*)(0x427E077CUL))
+#define bFM3_EXBUS_TIM7_RACC0                  *((volatile unsigned int*)(0x427E0780UL))
+#define bFM3_EXBUS_TIM7_RACC1                  *((volatile unsigned int*)(0x427E0784UL))
+#define bFM3_EXBUS_TIM7_RACC2                  *((volatile unsigned int*)(0x427E0788UL))
+#define bFM3_EXBUS_TIM7_RACC3                  *((volatile unsigned int*)(0x427E078CUL))
+#define bFM3_EXBUS_TIM7_RADC0                  *((volatile unsigned int*)(0x427E0790UL))
+#define bFM3_EXBUS_TIM7_RADC1                  *((volatile unsigned int*)(0x427E0794UL))
+#define bFM3_EXBUS_TIM7_RADC2                  *((volatile unsigned int*)(0x427E0798UL))
+#define bFM3_EXBUS_TIM7_RADC3                  *((volatile unsigned int*)(0x427E079CUL))
+#define bFM3_EXBUS_TIM7_FRADC0                 *((volatile unsigned int*)(0x427E07A0UL))
+#define bFM3_EXBUS_TIM7_FRADC1                 *((volatile unsigned int*)(0x427E07A4UL))
+#define bFM3_EXBUS_TIM7_FRADC2                 *((volatile unsigned int*)(0x427E07A8UL))
+#define bFM3_EXBUS_TIM7_FRADC3                 *((volatile unsigned int*)(0x427E07ACUL))
+#define bFM3_EXBUS_TIM7_RIDLC0                 *((volatile unsigned int*)(0x427E07B0UL))
+#define bFM3_EXBUS_TIM7_RIDLC1                 *((volatile unsigned int*)(0x427E07B4UL))
+#define bFM3_EXBUS_TIM7_RIDLC2                 *((volatile unsigned int*)(0x427E07B8UL))
+#define bFM3_EXBUS_TIM7_RIDLC3                 *((volatile unsigned int*)(0x427E07BCUL))
+#define bFM3_EXBUS_TIM7_WACC0                  *((volatile unsigned int*)(0x427E07C0UL))
+#define bFM3_EXBUS_TIM7_WACC1                  *((volatile unsigned int*)(0x427E07C4UL))
+#define bFM3_EXBUS_TIM7_WACC2                  *((volatile unsigned int*)(0x427E07C8UL))
+#define bFM3_EXBUS_TIM7_WACC3                  *((volatile unsigned int*)(0x427E07CCUL))
+#define bFM3_EXBUS_TIM7_WADC0                  *((volatile unsigned int*)(0x427E07D0UL))
+#define bFM3_EXBUS_TIM7_WADC1                  *((volatile unsigned int*)(0x427E07D4UL))
+#define bFM3_EXBUS_TIM7_WADC2                  *((volatile unsigned int*)(0x427E07D8UL))
+#define bFM3_EXBUS_TIM7_WADC3                  *((volatile unsigned int*)(0x427E07DCUL))
+#define bFM3_EXBUS_TIM7_WWEC0                  *((volatile unsigned int*)(0x427E07E0UL))
+#define bFM3_EXBUS_TIM7_WWEC1                  *((volatile unsigned int*)(0x427E07E4UL))
+#define bFM3_EXBUS_TIM7_WWEC2                  *((volatile unsigned int*)(0x427E07E8UL))
+#define bFM3_EXBUS_TIM7_WWEC3                  *((volatile unsigned int*)(0x427E07ECUL))
+#define bFM3_EXBUS_TIM7_WIDLC0                 *((volatile unsigned int*)(0x427E07F0UL))
+#define bFM3_EXBUS_TIM7_WIDLC1                 *((volatile unsigned int*)(0x427E07F4UL))
+#define bFM3_EXBUS_TIM7_WIDLC2                 *((volatile unsigned int*)(0x427E07F8UL))
+#define bFM3_EXBUS_TIM7_WIDLC3                 *((volatile unsigned int*)(0x427E07FCUL))
+#define bFM3_EXBUS_AREA0_ADDR0                 *((volatile unsigned int*)(0x427E0800UL))
+#define bFM3_EXBUS_AREA0_ADDR1                 *((volatile unsigned int*)(0x427E0804UL))
+#define bFM3_EXBUS_AREA0_ADDR2                 *((volatile unsigned int*)(0x427E0808UL))
+#define bFM3_EXBUS_AREA0_ADDR3                 *((volatile unsigned int*)(0x427E080CUL))
+#define bFM3_EXBUS_AREA0_ADDR4                 *((volatile unsigned int*)(0x427E0810UL))
+#define bFM3_EXBUS_AREA0_ADDR5                 *((volatile unsigned int*)(0x427E0814UL))
+#define bFM3_EXBUS_AREA0_ADDR6                 *((volatile unsigned int*)(0x427E0818UL))
+#define bFM3_EXBUS_AREA0_ADDR7                 *((volatile unsigned int*)(0x427E081CUL))
+#define bFM3_EXBUS_AREA0_MASK0                 *((volatile unsigned int*)(0x427E0840UL))
+#define bFM3_EXBUS_AREA0_MASK1                 *((volatile unsigned int*)(0x427E0844UL))
+#define bFM3_EXBUS_AREA0_MASK2                 *((volatile unsigned int*)(0x427E0848UL))
+#define bFM3_EXBUS_AREA0_MASK3                 *((volatile unsigned int*)(0x427E084CUL))
+#define bFM3_EXBUS_AREA0_MASK4                 *((volatile unsigned int*)(0x427E0850UL))
+#define bFM3_EXBUS_AREA0_MASK5                 *((volatile unsigned int*)(0x427E0854UL))
+#define bFM3_EXBUS_AREA0_MASK6                 *((volatile unsigned int*)(0x427E0858UL))
+#define bFM3_EXBUS_AREA1_ADDR0                 *((volatile unsigned int*)(0x427E0880UL))
+#define bFM3_EXBUS_AREA1_ADDR1                 *((volatile unsigned int*)(0x427E0884UL))
+#define bFM3_EXBUS_AREA1_ADDR2                 *((volatile unsigned int*)(0x427E0888UL))
+#define bFM3_EXBUS_AREA1_ADDR3                 *((volatile unsigned int*)(0x427E088CUL))
+#define bFM3_EXBUS_AREA1_ADDR4                 *((volatile unsigned int*)(0x427E0890UL))
+#define bFM3_EXBUS_AREA1_ADDR5                 *((volatile unsigned int*)(0x427E0894UL))
+#define bFM3_EXBUS_AREA1_ADDR6                 *((volatile unsigned int*)(0x427E0898UL))
+#define bFM3_EXBUS_AREA1_ADDR7                 *((volatile unsigned int*)(0x427E089CUL))
+#define bFM3_EXBUS_AREA1_MASK0                 *((volatile unsigned int*)(0x427E08C0UL))
+#define bFM3_EXBUS_AREA1_MASK1                 *((volatile unsigned int*)(0x427E08C4UL))
+#define bFM3_EXBUS_AREA1_MASK2                 *((volatile unsigned int*)(0x427E08C8UL))
+#define bFM3_EXBUS_AREA1_MASK3                 *((volatile unsigned int*)(0x427E08CCUL))
+#define bFM3_EXBUS_AREA1_MASK4                 *((volatile unsigned int*)(0x427E08D0UL))
+#define bFM3_EXBUS_AREA1_MASK5                 *((volatile unsigned int*)(0x427E08D4UL))
+#define bFM3_EXBUS_AREA1_MASK6                 *((volatile unsigned int*)(0x427E08D8UL))
+#define bFM3_EXBUS_AREA2_ADDR0                 *((volatile unsigned int*)(0x427E0900UL))
+#define bFM3_EXBUS_AREA2_ADDR1                 *((volatile unsigned int*)(0x427E0904UL))
+#define bFM3_EXBUS_AREA2_ADDR2                 *((volatile unsigned int*)(0x427E0908UL))
+#define bFM3_EXBUS_AREA2_ADDR3                 *((volatile unsigned int*)(0x427E090CUL))
+#define bFM3_EXBUS_AREA2_ADDR4                 *((volatile unsigned int*)(0x427E0910UL))
+#define bFM3_EXBUS_AREA2_ADDR5                 *((volatile unsigned int*)(0x427E0914UL))
+#define bFM3_EXBUS_AREA2_ADDR6                 *((volatile unsigned int*)(0x427E0918UL))
+#define bFM3_EXBUS_AREA2_ADDR7                 *((volatile unsigned int*)(0x427E091CUL))
+#define bFM3_EXBUS_AREA2_MASK0                 *((volatile unsigned int*)(0x427E0940UL))
+#define bFM3_EXBUS_AREA2_MASK1                 *((volatile unsigned int*)(0x427E0944UL))
+#define bFM3_EXBUS_AREA2_MASK2                 *((volatile unsigned int*)(0x427E0948UL))
+#define bFM3_EXBUS_AREA2_MASK3                 *((volatile unsigned int*)(0x427E094CUL))
+#define bFM3_EXBUS_AREA2_MASK4                 *((volatile unsigned int*)(0x427E0950UL))
+#define bFM3_EXBUS_AREA2_MASK5                 *((volatile unsigned int*)(0x427E0954UL))
+#define bFM3_EXBUS_AREA2_MASK6                 *((volatile unsigned int*)(0x427E0958UL))
+#define bFM3_EXBUS_AREA3_ADDR0                 *((volatile unsigned int*)(0x427E0980UL))
+#define bFM3_EXBUS_AREA3_ADDR1                 *((volatile unsigned int*)(0x427E0984UL))
+#define bFM3_EXBUS_AREA3_ADDR2                 *((volatile unsigned int*)(0x427E0988UL))
+#define bFM3_EXBUS_AREA3_ADDR3                 *((volatile unsigned int*)(0x427E098CUL))
+#define bFM3_EXBUS_AREA3_ADDR4                 *((volatile unsigned int*)(0x427E0990UL))
+#define bFM3_EXBUS_AREA3_ADDR5                 *((volatile unsigned int*)(0x427E0994UL))
+#define bFM3_EXBUS_AREA3_ADDR6                 *((volatile unsigned int*)(0x427E0998UL))
+#define bFM3_EXBUS_AREA3_ADDR7                 *((volatile unsigned int*)(0x427E099CUL))
+#define bFM3_EXBUS_AREA3_MASK0                 *((volatile unsigned int*)(0x427E09C0UL))
+#define bFM3_EXBUS_AREA3_MASK1                 *((volatile unsigned int*)(0x427E09C4UL))
+#define bFM3_EXBUS_AREA3_MASK2                 *((volatile unsigned int*)(0x427E09C8UL))
+#define bFM3_EXBUS_AREA3_MASK3                 *((volatile unsigned int*)(0x427E09CCUL))
+#define bFM3_EXBUS_AREA3_MASK4                 *((volatile unsigned int*)(0x427E09D0UL))
+#define bFM3_EXBUS_AREA3_MASK5                 *((volatile unsigned int*)(0x427E09D4UL))
+#define bFM3_EXBUS_AREA3_MASK6                 *((volatile unsigned int*)(0x427E09D8UL))
+#define bFM3_EXBUS_AREA4_ADDR0                 *((volatile unsigned int*)(0x427E0A00UL))
+#define bFM3_EXBUS_AREA4_ADDR1                 *((volatile unsigned int*)(0x427E0A04UL))
+#define bFM3_EXBUS_AREA4_ADDR2                 *((volatile unsigned int*)(0x427E0A08UL))
+#define bFM3_EXBUS_AREA4_ADDR3                 *((volatile unsigned int*)(0x427E0A0CUL))
+#define bFM3_EXBUS_AREA4_ADDR4                 *((volatile unsigned int*)(0x427E0A10UL))
+#define bFM3_EXBUS_AREA4_ADDR5                 *((volatile unsigned int*)(0x427E0A14UL))
+#define bFM3_EXBUS_AREA4_ADDR6                 *((volatile unsigned int*)(0x427E0A18UL))
+#define bFM3_EXBUS_AREA4_ADDR7                 *((volatile unsigned int*)(0x427E0A1CUL))
+#define bFM3_EXBUS_AREA4_MASK0                 *((volatile unsigned int*)(0x427E0A40UL))
+#define bFM3_EXBUS_AREA4_MASK1                 *((volatile unsigned int*)(0x427E0A44UL))
+#define bFM3_EXBUS_AREA4_MASK2                 *((volatile unsigned int*)(0x427E0A48UL))
+#define bFM3_EXBUS_AREA4_MASK3                 *((volatile unsigned int*)(0x427E0A4CUL))
+#define bFM3_EXBUS_AREA4_MASK4                 *((volatile unsigned int*)(0x427E0A50UL))
+#define bFM3_EXBUS_AREA4_MASK5                 *((volatile unsigned int*)(0x427E0A54UL))
+#define bFM3_EXBUS_AREA4_MASK6                 *((volatile unsigned int*)(0x427E0A58UL))
+#define bFM3_EXBUS_AREA5_ADDR0                 *((volatile unsigned int*)(0x427E0A80UL))
+#define bFM3_EXBUS_AREA5_ADDR1                 *((volatile unsigned int*)(0x427E0A84UL))
+#define bFM3_EXBUS_AREA5_ADDR2                 *((volatile unsigned int*)(0x427E0A88UL))
+#define bFM3_EXBUS_AREA5_ADDR3                 *((volatile unsigned int*)(0x427E0A8CUL))
+#define bFM3_EXBUS_AREA5_ADDR4                 *((volatile unsigned int*)(0x427E0A90UL))
+#define bFM3_EXBUS_AREA5_ADDR5                 *((volatile unsigned int*)(0x427E0A94UL))
+#define bFM3_EXBUS_AREA5_ADDR6                 *((volatile unsigned int*)(0x427E0A98UL))
+#define bFM3_EXBUS_AREA5_ADDR7                 *((volatile unsigned int*)(0x427E0A9CUL))
+#define bFM3_EXBUS_AREA5_MASK0                 *((volatile unsigned int*)(0x427E0AC0UL))
+#define bFM3_EXBUS_AREA5_MASK1                 *((volatile unsigned int*)(0x427E0AC4UL))
+#define bFM3_EXBUS_AREA5_MASK2                 *((volatile unsigned int*)(0x427E0AC8UL))
+#define bFM3_EXBUS_AREA5_MASK3                 *((volatile unsigned int*)(0x427E0ACCUL))
+#define bFM3_EXBUS_AREA5_MASK4                 *((volatile unsigned int*)(0x427E0AD0UL))
+#define bFM3_EXBUS_AREA5_MASK5                 *((volatile unsigned int*)(0x427E0AD4UL))
+#define bFM3_EXBUS_AREA5_MASK6                 *((volatile unsigned int*)(0x427E0AD8UL))
+#define bFM3_EXBUS_AREA6_ADDR0                 *((volatile unsigned int*)(0x427E0B00UL))
+#define bFM3_EXBUS_AREA6_ADDR1                 *((volatile unsigned int*)(0x427E0B04UL))
+#define bFM3_EXBUS_AREA6_ADDR2                 *((volatile unsigned int*)(0x427E0B08UL))
+#define bFM3_EXBUS_AREA6_ADDR3                 *((volatile unsigned int*)(0x427E0B0CUL))
+#define bFM3_EXBUS_AREA6_ADDR4                 *((volatile unsigned int*)(0x427E0B10UL))
+#define bFM3_EXBUS_AREA6_ADDR5                 *((volatile unsigned int*)(0x427E0B14UL))
+#define bFM3_EXBUS_AREA6_ADDR6                 *((volatile unsigned int*)(0x427E0B18UL))
+#define bFM3_EXBUS_AREA6_ADDR7                 *((volatile unsigned int*)(0x427E0B1CUL))
+#define bFM3_EXBUS_AREA6_MASK0                 *((volatile unsigned int*)(0x427E0B40UL))
+#define bFM3_EXBUS_AREA6_MASK1                 *((volatile unsigned int*)(0x427E0B44UL))
+#define bFM3_EXBUS_AREA6_MASK2                 *((volatile unsigned int*)(0x427E0B48UL))
+#define bFM3_EXBUS_AREA6_MASK3                 *((volatile unsigned int*)(0x427E0B4CUL))
+#define bFM3_EXBUS_AREA6_MASK4                 *((volatile unsigned int*)(0x427E0B50UL))
+#define bFM3_EXBUS_AREA6_MASK5                 *((volatile unsigned int*)(0x427E0B54UL))
+#define bFM3_EXBUS_AREA6_MASK6                 *((volatile unsigned int*)(0x427E0B58UL))
+#define bFM3_EXBUS_AREA7_ADDR0                 *((volatile unsigned int*)(0x427E0B80UL))
+#define bFM3_EXBUS_AREA7_ADDR1                 *((volatile unsigned int*)(0x427E0B84UL))
+#define bFM3_EXBUS_AREA7_ADDR2                 *((volatile unsigned int*)(0x427E0B88UL))
+#define bFM3_EXBUS_AREA7_ADDR3                 *((volatile unsigned int*)(0x427E0B8CUL))
+#define bFM3_EXBUS_AREA7_ADDR4                 *((volatile unsigned int*)(0x427E0B90UL))
+#define bFM3_EXBUS_AREA7_ADDR5                 *((volatile unsigned int*)(0x427E0B94UL))
+#define bFM3_EXBUS_AREA7_ADDR6                 *((volatile unsigned int*)(0x427E0B98UL))
+#define bFM3_EXBUS_AREA7_ADDR7                 *((volatile unsigned int*)(0x427E0B9CUL))
+#define bFM3_EXBUS_AREA7_MASK0                 *((volatile unsigned int*)(0x427E0BC0UL))
+#define bFM3_EXBUS_AREA7_MASK1                 *((volatile unsigned int*)(0x427E0BC4UL))
+#define bFM3_EXBUS_AREA7_MASK2                 *((volatile unsigned int*)(0x427E0BC8UL))
+#define bFM3_EXBUS_AREA7_MASK3                 *((volatile unsigned int*)(0x427E0BCCUL))
+#define bFM3_EXBUS_AREA7_MASK4                 *((volatile unsigned int*)(0x427E0BD0UL))
+#define bFM3_EXBUS_AREA7_MASK5                 *((volatile unsigned int*)(0x427E0BD4UL))
+#define bFM3_EXBUS_AREA7_MASK6                 *((volatile unsigned int*)(0x427E0BD8UL))
+#define bFM3_EXBUS_ATIM0_ALC0                  *((volatile unsigned int*)(0x427E0C00UL))
+#define bFM3_EXBUS_ATIM0_ALC1                  *((volatile unsigned int*)(0x427E0C04UL))
+#define bFM3_EXBUS_ATIM0_ALC2                  *((volatile unsigned int*)(0x427E0C08UL))
+#define bFM3_EXBUS_ATIM0_ALC3                  *((volatile unsigned int*)(0x427E0C0CUL))
+#define bFM3_EXBUS_ATIM0_ALES0                 *((volatile unsigned int*)(0x427E0C10UL))
+#define bFM3_EXBUS_ATIM0_ALES1                 *((volatile unsigned int*)(0x427E0C14UL))
+#define bFM3_EXBUS_ATIM0_ALES2                 *((volatile unsigned int*)(0x427E0C18UL))
+#define bFM3_EXBUS_ATIM0_ALES3                 *((volatile unsigned int*)(0x427E0C1CUL))
+#define bFM3_EXBUS_ATIM0_ALEW0                 *((volatile unsigned int*)(0x427E0C20UL))
+#define bFM3_EXBUS_ATIM0_ALEW1                 *((volatile unsigned int*)(0x427E0C24UL))
+#define bFM3_EXBUS_ATIM0_ALEW2                 *((volatile unsigned int*)(0x427E0C28UL))
+#define bFM3_EXBUS_ATIM0_ALEW3                 *((volatile unsigned int*)(0x427E0C2CUL))
+#define bFM3_EXBUS_ATIM1_ALC0                  *((volatile unsigned int*)(0x427E0C80UL))
+#define bFM3_EXBUS_ATIM1_ALC1                  *((volatile unsigned int*)(0x427E0C84UL))
+#define bFM3_EXBUS_ATIM1_ALC2                  *((volatile unsigned int*)(0x427E0C88UL))
+#define bFM3_EXBUS_ATIM1_ALC3                  *((volatile unsigned int*)(0x427E0C8CUL))
+#define bFM3_EXBUS_ATIM1_ALES0                 *((volatile unsigned int*)(0x427E0C90UL))
+#define bFM3_EXBUS_ATIM1_ALES1                 *((volatile unsigned int*)(0x427E0C94UL))
+#define bFM3_EXBUS_ATIM1_ALES2                 *((volatile unsigned int*)(0x427E0C98UL))
+#define bFM3_EXBUS_ATIM1_ALES3                 *((volatile unsigned int*)(0x427E0C9CUL))
+#define bFM3_EXBUS_ATIM1_ALEW0                 *((volatile unsigned int*)(0x427E0CA0UL))
+#define bFM3_EXBUS_ATIM1_ALEW1                 *((volatile unsigned int*)(0x427E0CA4UL))
+#define bFM3_EXBUS_ATIM1_ALEW2                 *((volatile unsigned int*)(0x427E0CA8UL))
+#define bFM3_EXBUS_ATIM1_ALEW3                 *((volatile unsigned int*)(0x427E0CACUL))
+#define bFM3_EXBUS_ATIM2_ALC0                  *((volatile unsigned int*)(0x427E0D00UL))
+#define bFM3_EXBUS_ATIM2_ALC1                  *((volatile unsigned int*)(0x427E0D04UL))
+#define bFM3_EXBUS_ATIM2_ALC2                  *((volatile unsigned int*)(0x427E0D08UL))
+#define bFM3_EXBUS_ATIM2_ALC3                  *((volatile unsigned int*)(0x427E0D0CUL))
+#define bFM3_EXBUS_ATIM2_ALES0                 *((volatile unsigned int*)(0x427E0D10UL))
+#define bFM3_EXBUS_ATIM2_ALES1                 *((volatile unsigned int*)(0x427E0D14UL))
+#define bFM3_EXBUS_ATIM2_ALES2                 *((volatile unsigned int*)(0x427E0D18UL))
+#define bFM3_EXBUS_ATIM2_ALES3                 *((volatile unsigned int*)(0x427E0D1CUL))
+#define bFM3_EXBUS_ATIM2_ALEW0                 *((volatile unsigned int*)(0x427E0D20UL))
+#define bFM3_EXBUS_ATIM2_ALEW1                 *((volatile unsigned int*)(0x427E0D24UL))
+#define bFM3_EXBUS_ATIM2_ALEW2                 *((volatile unsigned int*)(0x427E0D28UL))
+#define bFM3_EXBUS_ATIM2_ALEW3                 *((volatile unsigned int*)(0x427E0D2CUL))
+#define bFM3_EXBUS_ATIM3_ALC0                  *((volatile unsigned int*)(0x427E0D80UL))
+#define bFM3_EXBUS_ATIM3_ALC1                  *((volatile unsigned int*)(0x427E0D84UL))
+#define bFM3_EXBUS_ATIM3_ALC2                  *((volatile unsigned int*)(0x427E0D88UL))
+#define bFM3_EXBUS_ATIM3_ALC3                  *((volatile unsigned int*)(0x427E0D8CUL))
+#define bFM3_EXBUS_ATIM3_ALES0                 *((volatile unsigned int*)(0x427E0D90UL))
+#define bFM3_EXBUS_ATIM3_ALES1                 *((volatile unsigned int*)(0x427E0D94UL))
+#define bFM3_EXBUS_ATIM3_ALES2                 *((volatile unsigned int*)(0x427E0D98UL))
+#define bFM3_EXBUS_ATIM3_ALES3                 *((volatile unsigned int*)(0x427E0D9CUL))
+#define bFM3_EXBUS_ATIM3_ALEW0                 *((volatile unsigned int*)(0x427E0DA0UL))
+#define bFM3_EXBUS_ATIM3_ALEW1                 *((volatile unsigned int*)(0x427E0DA4UL))
+#define bFM3_EXBUS_ATIM3_ALEW2                 *((volatile unsigned int*)(0x427E0DA8UL))
+#define bFM3_EXBUS_ATIM3_ALEW3                 *((volatile unsigned int*)(0x427E0DACUL))
+#define bFM3_EXBUS_ATIM4_ALC0                  *((volatile unsigned int*)(0x427E0E00UL))
+#define bFM3_EXBUS_ATIM4_ALC1                  *((volatile unsigned int*)(0x427E0E04UL))
+#define bFM3_EXBUS_ATIM4_ALC2                  *((volatile unsigned int*)(0x427E0E08UL))
+#define bFM3_EXBUS_ATIM4_ALC3                  *((volatile unsigned int*)(0x427E0E0CUL))
+#define bFM3_EXBUS_ATIM4_ALES0                 *((volatile unsigned int*)(0x427E0E10UL))
+#define bFM3_EXBUS_ATIM4_ALES1                 *((volatile unsigned int*)(0x427E0E14UL))
+#define bFM3_EXBUS_ATIM4_ALES2                 *((volatile unsigned int*)(0x427E0E18UL))
+#define bFM3_EXBUS_ATIM4_ALES3                 *((volatile unsigned int*)(0x427E0E1CUL))
+#define bFM3_EXBUS_ATIM4_ALEW0                 *((volatile unsigned int*)(0x427E0E20UL))
+#define bFM3_EXBUS_ATIM4_ALEW1                 *((volatile unsigned int*)(0x427E0E24UL))
+#define bFM3_EXBUS_ATIM4_ALEW2                 *((volatile unsigned int*)(0x427E0E28UL))
+#define bFM3_EXBUS_ATIM4_ALEW3                 *((volatile unsigned int*)(0x427E0E2CUL))
+#define bFM3_EXBUS_ATIM5_ALC0                  *((volatile unsigned int*)(0x427E0E80UL))
+#define bFM3_EXBUS_ATIM5_ALC1                  *((volatile unsigned int*)(0x427E0E84UL))
+#define bFM3_EXBUS_ATIM5_ALC2                  *((volatile unsigned int*)(0x427E0E88UL))
+#define bFM3_EXBUS_ATIM5_ALC3                  *((volatile unsigned int*)(0x427E0E8CUL))
+#define bFM3_EXBUS_ATIM5_ALES0                 *((volatile unsigned int*)(0x427E0E90UL))
+#define bFM3_EXBUS_ATIM5_ALES1                 *((volatile unsigned int*)(0x427E0E94UL))
+#define bFM3_EXBUS_ATIM5_ALES2                 *((volatile unsigned int*)(0x427E0E98UL))
+#define bFM3_EXBUS_ATIM5_ALES3                 *((volatile unsigned int*)(0x427E0E9CUL))
+#define bFM3_EXBUS_ATIM5_ALEW0                 *((volatile unsigned int*)(0x427E0EA0UL))
+#define bFM3_EXBUS_ATIM5_ALEW1                 *((volatile unsigned int*)(0x427E0EA4UL))
+#define bFM3_EXBUS_ATIM5_ALEW2                 *((volatile unsigned int*)(0x427E0EA8UL))
+#define bFM3_EXBUS_ATIM5_ALEW3                 *((volatile unsigned int*)(0x427E0EACUL))
+#define bFM3_EXBUS_ATIM6_ALC0                  *((volatile unsigned int*)(0x427E0F00UL))
+#define bFM3_EXBUS_ATIM6_ALC1                  *((volatile unsigned int*)(0x427E0F04UL))
+#define bFM3_EXBUS_ATIM6_ALC2                  *((volatile unsigned int*)(0x427E0F08UL))
+#define bFM3_EXBUS_ATIM6_ALC3                  *((volatile unsigned int*)(0x427E0F0CUL))
+#define bFM3_EXBUS_ATIM6_ALES0                 *((volatile unsigned int*)(0x427E0F10UL))
+#define bFM3_EXBUS_ATIM6_ALES1                 *((volatile unsigned int*)(0x427E0F14UL))
+#define bFM3_EXBUS_ATIM6_ALES2                 *((volatile unsigned int*)(0x427E0F18UL))
+#define bFM3_EXBUS_ATIM6_ALES3                 *((volatile unsigned int*)(0x427E0F1CUL))
+#define bFM3_EXBUS_ATIM6_ALEW0                 *((volatile unsigned int*)(0x427E0F20UL))
+#define bFM3_EXBUS_ATIM6_ALEW1                 *((volatile unsigned int*)(0x427E0F24UL))
+#define bFM3_EXBUS_ATIM6_ALEW2                 *((volatile unsigned int*)(0x427E0F28UL))
+#define bFM3_EXBUS_ATIM6_ALEW3                 *((volatile unsigned int*)(0x427E0F2CUL))
+#define bFM3_EXBUS_ATIM7_ALC0                  *((volatile unsigned int*)(0x427E0F80UL))
+#define bFM3_EXBUS_ATIM7_ALC1                  *((volatile unsigned int*)(0x427E0F84UL))
+#define bFM3_EXBUS_ATIM7_ALC2                  *((volatile unsigned int*)(0x427E0F88UL))
+#define bFM3_EXBUS_ATIM7_ALC3                  *((volatile unsigned int*)(0x427E0F8CUL))
+#define bFM3_EXBUS_ATIM7_ALES0                 *((volatile unsigned int*)(0x427E0F90UL))
+#define bFM3_EXBUS_ATIM7_ALES1                 *((volatile unsigned int*)(0x427E0F94UL))
+#define bFM3_EXBUS_ATIM7_ALES2                 *((volatile unsigned int*)(0x427E0F98UL))
+#define bFM3_EXBUS_ATIM7_ALES3                 *((volatile unsigned int*)(0x427E0F9CUL))
+#define bFM3_EXBUS_ATIM7_ALEW0                 *((volatile unsigned int*)(0x427E0FA0UL))
+#define bFM3_EXBUS_ATIM7_ALEW1                 *((volatile unsigned int*)(0x427E0FA4UL))
+#define bFM3_EXBUS_ATIM7_ALEW2                 *((volatile unsigned int*)(0x427E0FA8UL))
+#define bFM3_EXBUS_ATIM7_ALEW3                 *((volatile unsigned int*)(0x427E0FACUL))
+#define bFM3_EXBUS_DCLKR_MDIV0                 *((volatile unsigned int*)(0x427E6000UL))
+#define bFM3_EXBUS_DCLKR_MDIV1                 *((volatile unsigned int*)(0x427E6004UL))
+#define bFM3_EXBUS_DCLKR_MDIV2                 *((volatile unsigned int*)(0x427E6008UL))
+#define bFM3_EXBUS_DCLKR_MDIV3                 *((volatile unsigned int*)(0x427E600CUL))
+#define bFM3_EXBUS_DCLKR_MCLKON                *((volatile unsigned int*)(0x427E6010UL))
+
+/* USB channel 0 registers */
+#define bFM3_USB0_HCNT_HOST                    *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT_URST                    *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT_DIRE                    *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT_URIRE                   *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT_RWKIRE                  *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT_RETRY                   *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT_CANCEL                  *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HCNT0_HOST                   *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT0_URST                   *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT0_DIRE                   *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT0_URIRE                  *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT1_RETRY                  *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42842080UL))
+#define bFM3_USB0_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42842084UL))
+#define bFM3_USB0_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42842088UL))
+#define bFM3_USB0_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x4284208CUL))
+#define bFM3_USB0_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42842090UL))
+#define bFM3_USB0_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42842094UL))
+#define bFM3_USB0_HIRQ_TCAN                    *((volatile unsigned int*)(0x4284209CUL))
+#define bFM3_USB0_HERR_HS0                     *((volatile unsigned int*)(0x428420A0UL))
+#define bFM3_USB0_HERR_HS1                     *((volatile unsigned int*)(0x428420A4UL))
+#define bFM3_USB0_HERR_STUFF                   *((volatile unsigned int*)(0x428420A8UL))
+#define bFM3_USB0_HERR_TGERR                   *((volatile unsigned int*)(0x428420ACUL))
+#define bFM3_USB0_HERR_CRC                     *((volatile unsigned int*)(0x428420B0UL))
+#define bFM3_USB0_HERR_TOUT                    *((volatile unsigned int*)(0x428420B4UL))
+#define bFM3_USB0_HERR_RERR                    *((volatile unsigned int*)(0x428420B8UL))
+#define bFM3_USB0_HERR_LSTOF                   *((volatile unsigned int*)(0x428420BCUL))
+#define bFM3_USB0_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42842100UL))
+#define bFM3_USB0_HSTATE_TMODE                 *((volatile unsigned int*)(0x42842104UL))
+#define bFM3_USB0_HSTATE_SUSP                  *((volatile unsigned int*)(0x42842108UL))
+#define bFM3_USB0_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x4284210CUL))
+#define bFM3_USB0_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42842110UL))
+#define bFM3_USB0_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42842114UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42842120UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42842124UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42842128UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x4284212CUL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42842130UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42842134UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42842138UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x4284213CUL))
+#define bFM3_USB0_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42842200UL))
+#define bFM3_USB0_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42842204UL))
+#define bFM3_USB0_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42842208UL))
+#define bFM3_USB0_HADR_ADDRESS0                *((volatile unsigned int*)(0x42842220UL))
+#define bFM3_USB0_HADR_ADDRESS1                *((volatile unsigned int*)(0x42842224UL))
+#define bFM3_USB0_HADR_ADDRESS2                *((volatile unsigned int*)(0x42842228UL))
+#define bFM3_USB0_HADR_ADDRESS3                *((volatile unsigned int*)(0x4284222CUL))
+#define bFM3_USB0_HADR_ADDRESS4                *((volatile unsigned int*)(0x42842230UL))
+#define bFM3_USB0_HADR_ADDRESS5                *((volatile unsigned int*)(0x42842234UL))
+#define bFM3_USB0_HADR_ADDRESS6                *((volatile unsigned int*)(0x42842238UL))
+#define bFM3_USB0_HEOF_EOF0                    *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF_EOF1                    *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF_EOF2                    *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF_EOF3                    *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF_EOF4                    *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF_EOF5                    *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF_EOF6                    *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF_EOF7                    *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF_EOF8                    *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF_EOF9                    *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF_EOF10                   *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF_EOF11                   *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF_EOF12                   *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF_EOF13                   *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HEOF_EOF14                   *((volatile unsigned int*)(0x428422B8UL))
+#define bFM3_USB0_HEOF_EOF15                   *((volatile unsigned int*)(0x428422BCUL))
+#define bFM3_USB0_HEOF0_EOF00                  *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF0_EOF01                  *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF0_EOF02                  *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF0_EOF03                  *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF0_EOF04                  *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF0_EOF05                  *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF0_EOF06                  *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF0_EOF07                  *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF1_EOF10                  *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF1_EOF11                  *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF1_EOF12                  *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF1_EOF13                  *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF1_EOF14                  *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF1_EOF15                  *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HFRAME_FRAME0                *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME_FRAME1                *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME_FRAME2                *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME_FRAME3                *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME_FRAME4                *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME_FRAME5                *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME_FRAME6                *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME_FRAME7                *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME_FRAME8                *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME_FRAME9                *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME_FRAME10               *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME0_FRAME03              *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME0_FRAME07              *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME1_FRAME13              *((volatile unsigned int*)(0x4284232CUL))
+#define bFM3_USB0_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42842380UL))
+#define bFM3_USB0_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42842384UL))
+#define bFM3_USB0_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42842388UL))
+#define bFM3_USB0_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x4284238CUL))
+#define bFM3_USB0_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42842390UL))
+#define bFM3_USB0_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42842394UL))
+#define bFM3_USB0_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42842398UL))
+#define bFM3_USB0_HTOKEN_TGGL                  *((volatile unsigned int*)(0x4284239CUL))
+#define bFM3_USB0_UDCC_PWC                     *((volatile unsigned int*)(0x42842400UL))
+#define bFM3_USB0_UDCC_RFBK                    *((volatile unsigned int*)(0x42842404UL))
+#define bFM3_USB0_UDCC_STALCLREN               *((volatile unsigned int*)(0x4284240CUL))
+#define bFM3_USB0_UDCC_USTP                    *((volatile unsigned int*)(0x42842410UL))
+#define bFM3_USB0_UDCC_HCONX                   *((volatile unsigned int*)(0x42842414UL))
+#define bFM3_USB0_UDCC_RESUM                   *((volatile unsigned int*)(0x42842418UL))
+#define bFM3_USB0_UDCC_RST                     *((volatile unsigned int*)(0x4284241CUL))
+#define bFM3_USB0_EP0C_PKS00                   *((volatile unsigned int*)(0x42842480UL))
+#define bFM3_USB0_EP0C_PKS01                   *((volatile unsigned int*)(0x42842484UL))
+#define bFM3_USB0_EP0C_PKS02                   *((volatile unsigned int*)(0x42842488UL))
+#define bFM3_USB0_EP0C_PKS03                   *((volatile unsigned int*)(0x4284248CUL))
+#define bFM3_USB0_EP0C_PKS04                   *((volatile unsigned int*)(0x42842490UL))
+#define bFM3_USB0_EP0C_PKS05                   *((volatile unsigned int*)(0x42842494UL))
+#define bFM3_USB0_EP0C_PKS06                   *((volatile unsigned int*)(0x42842498UL))
+#define bFM3_USB0_EP0C_STAL                    *((volatile unsigned int*)(0x428424A4UL))
+#define bFM3_USB0_EP1C_PKS10                   *((volatile unsigned int*)(0x42842500UL))
+#define bFM3_USB0_EP1C_PKS11                   *((volatile unsigned int*)(0x42842504UL))
+#define bFM3_USB0_EP1C_PKS12                   *((volatile unsigned int*)(0x42842508UL))
+#define bFM3_USB0_EP1C_PKS13                   *((volatile unsigned int*)(0x4284250CUL))
+#define bFM3_USB0_EP1C_PKS14                   *((volatile unsigned int*)(0x42842510UL))
+#define bFM3_USB0_EP1C_PKS15                   *((volatile unsigned int*)(0x42842514UL))
+#define bFM3_USB0_EP1C_PKS16                   *((volatile unsigned int*)(0x42842518UL))
+#define bFM3_USB0_EP1C_PKS17                   *((volatile unsigned int*)(0x4284251CUL))
+#define bFM3_USB0_EP1C_PKS18                   *((volatile unsigned int*)(0x42842520UL))
+#define bFM3_USB0_EP1C_STAL                    *((volatile unsigned int*)(0x42842524UL))
+#define bFM3_USB0_EP1C_NULE                    *((volatile unsigned int*)(0x42842528UL))
+#define bFM3_USB0_EP1C_DMAE                    *((volatile unsigned int*)(0x4284252CUL))
+#define bFM3_USB0_EP1C_DIR                     *((volatile unsigned int*)(0x42842530UL))
+#define bFM3_USB0_EP1C_TYPE0                   *((volatile unsigned int*)(0x42842534UL))
+#define bFM3_USB0_EP1C_TYPE1                   *((volatile unsigned int*)(0x42842538UL))
+#define bFM3_USB0_EP1C_EPEN                    *((volatile unsigned int*)(0x4284253CUL))
+#define bFM3_USB0_EP2C_PKS20                   *((volatile unsigned int*)(0x42842580UL))
+#define bFM3_USB0_EP2C_PKS21                   *((volatile unsigned int*)(0x42842584UL))
+#define bFM3_USB0_EP2C_PKS22                   *((volatile unsigned int*)(0x42842588UL))
+#define bFM3_USB0_EP2C_PKS23                   *((volatile unsigned int*)(0x4284258CUL))
+#define bFM3_USB0_EP2C_PKS24                   *((volatile unsigned int*)(0x42842590UL))
+#define bFM3_USB0_EP2C_PKS25                   *((volatile unsigned int*)(0x42842594UL))
+#define bFM3_USB0_EP2C_PKS26                   *((volatile unsigned int*)(0x42842598UL))
+#define bFM3_USB0_EP2C_STAL                    *((volatile unsigned int*)(0x428425A4UL))
+#define bFM3_USB0_EP2C_NULE                    *((volatile unsigned int*)(0x428425A8UL))
+#define bFM3_USB0_EP2C_DMAE                    *((volatile unsigned int*)(0x428425ACUL))
+#define bFM3_USB0_EP2C_DIR                     *((volatile unsigned int*)(0x428425B0UL))
+#define bFM3_USB0_EP2C_TYPE0                   *((volatile unsigned int*)(0x428425B4UL))
+#define bFM3_USB0_EP2C_TYPE1                   *((volatile unsigned int*)(0x428425B8UL))
+#define bFM3_USB0_EP2C_EPEN                    *((volatile unsigned int*)(0x428425BCUL))
+#define bFM3_USB0_EP3C_PKS30                   *((volatile unsigned int*)(0x42842600UL))
+#define bFM3_USB0_EP3C_PKS31                   *((volatile unsigned int*)(0x42842604UL))
+#define bFM3_USB0_EP3C_PKS32                   *((volatile unsigned int*)(0x42842608UL))
+#define bFM3_USB0_EP3C_PKS33                   *((volatile unsigned int*)(0x4284260CUL))
+#define bFM3_USB0_EP3C_PKS34                   *((volatile unsigned int*)(0x42842610UL))
+#define bFM3_USB0_EP3C_PKS35                   *((volatile unsigned int*)(0x42842614UL))
+#define bFM3_USB0_EP3C_PKS36                   *((volatile unsigned int*)(0x42842618UL))
+#define bFM3_USB0_EP3C_STAL                    *((volatile unsigned int*)(0x42842624UL))
+#define bFM3_USB0_EP3C_NULE                    *((volatile unsigned int*)(0x42842628UL))
+#define bFM3_USB0_EP3C_DMAE                    *((volatile unsigned int*)(0x4284262CUL))
+#define bFM3_USB0_EP3C_DIR                     *((volatile unsigned int*)(0x42842630UL))
+#define bFM3_USB0_EP3C_TYPE0                   *((volatile unsigned int*)(0x42842634UL))
+#define bFM3_USB0_EP3C_TYPE1                   *((volatile unsigned int*)(0x42842638UL))
+#define bFM3_USB0_EP3C_EPEN                    *((volatile unsigned int*)(0x4284263CUL))
+#define bFM3_USB0_EP4C_PKS40                   *((volatile unsigned int*)(0x42842680UL))
+#define bFM3_USB0_EP4C_PKS41                   *((volatile unsigned int*)(0x42842684UL))
+#define bFM3_USB0_EP4C_PKS42                   *((volatile unsigned int*)(0x42842688UL))
+#define bFM3_USB0_EP4C_PKS43                   *((volatile unsigned int*)(0x4284268CUL))
+#define bFM3_USB0_EP4C_PKS44                   *((volatile unsigned int*)(0x42842690UL))
+#define bFM3_USB0_EP4C_PKS45                   *((volatile unsigned int*)(0x42842694UL))
+#define bFM3_USB0_EP4C_PKS46                   *((volatile unsigned int*)(0x42842698UL))
+#define bFM3_USB0_EP4C_STAL                    *((volatile unsigned int*)(0x428426A4UL))
+#define bFM3_USB0_EP4C_NULE                    *((volatile unsigned int*)(0x428426A8UL))
+#define bFM3_USB0_EP4C_DMAE                    *((volatile unsigned int*)(0x428426ACUL))
+#define bFM3_USB0_EP4C_DIR                     *((volatile unsigned int*)(0x428426B0UL))
+#define bFM3_USB0_EP4C_TYPE0                   *((volatile unsigned int*)(0x428426B4UL))
+#define bFM3_USB0_EP4C_TYPE1                   *((volatile unsigned int*)(0x428426B8UL))
+#define bFM3_USB0_EP4C_EPEN                    *((volatile unsigned int*)(0x428426BCUL))
+#define bFM3_USB0_EP5C_PKS50                   *((volatile unsigned int*)(0x42842700UL))
+#define bFM3_USB0_EP5C_PKS51                   *((volatile unsigned int*)(0x42842704UL))
+#define bFM3_USB0_EP5C_PKS52                   *((volatile unsigned int*)(0x42842708UL))
+#define bFM3_USB0_EP5C_PKS53                   *((volatile unsigned int*)(0x4284270CUL))
+#define bFM3_USB0_EP5C_PKS54                   *((volatile unsigned int*)(0x42842710UL))
+#define bFM3_USB0_EP5C_PKS55                   *((volatile unsigned int*)(0x42842714UL))
+#define bFM3_USB0_EP5C_PKS56                   *((volatile unsigned int*)(0x42842718UL))
+#define bFM3_USB0_EP5C_STAL                    *((volatile unsigned int*)(0x42842724UL))
+#define bFM3_USB0_EP5C_NULE                    *((volatile unsigned int*)(0x42842728UL))
+#define bFM3_USB0_EP5C_DMAE                    *((volatile unsigned int*)(0x4284272CUL))
+#define bFM3_USB0_EP5C_DIR                     *((volatile unsigned int*)(0x42842730UL))
+#define bFM3_USB0_EP5C_TYPE0                   *((volatile unsigned int*)(0x42842734UL))
+#define bFM3_USB0_EP5C_TYPE1                   *((volatile unsigned int*)(0x42842738UL))
+#define bFM3_USB0_EP5C_EPEN                    *((volatile unsigned int*)(0x4284273CUL))
+#define bFM3_USB0_TMSP_TMSP0                   *((volatile unsigned int*)(0x42842780UL))
+#define bFM3_USB0_TMSP_TMSP1                   *((volatile unsigned int*)(0x42842784UL))
+#define bFM3_USB0_TMSP_TMSP2                   *((volatile unsigned int*)(0x42842788UL))
+#define bFM3_USB0_TMSP_TMSP3                   *((volatile unsigned int*)(0x4284278CUL))
+#define bFM3_USB0_TMSP_TMSP4                   *((volatile unsigned int*)(0x42842790UL))
+#define bFM3_USB0_TMSP_TMSP5                   *((volatile unsigned int*)(0x42842794UL))
+#define bFM3_USB0_TMSP_TMSP6                   *((volatile unsigned int*)(0x42842798UL))
+#define bFM3_USB0_TMSP_TMSP7                   *((volatile unsigned int*)(0x4284279CUL))
+#define bFM3_USB0_TMSP_TMSP8                   *((volatile unsigned int*)(0x428427A0UL))
+#define bFM3_USB0_TMSP_TMSP9                   *((volatile unsigned int*)(0x428427A4UL))
+#define bFM3_USB0_TMSP_TMSP10                  *((volatile unsigned int*)(0x428427A8UL))
+#define bFM3_USB0_UDCS_CONF                    *((volatile unsigned int*)(0x42842800UL))
+#define bFM3_USB0_UDCS_SETP                    *((volatile unsigned int*)(0x42842804UL))
+#define bFM3_USB0_UDCS_WKUP                    *((volatile unsigned int*)(0x42842808UL))
+#define bFM3_USB0_UDCS_BRST                    *((volatile unsigned int*)(0x4284280CUL))
+#define bFM3_USB0_UDCS_SOF                     *((volatile unsigned int*)(0x42842810UL))
+#define bFM3_USB0_UDCS_SUSP                    *((volatile unsigned int*)(0x42842814UL))
+#define bFM3_USB0_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42842820UL))
+#define bFM3_USB0_UDCIE_CONFN                  *((volatile unsigned int*)(0x42842824UL))
+#define bFM3_USB0_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42842828UL))
+#define bFM3_USB0_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x4284282CUL))
+#define bFM3_USB0_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42842830UL))
+#define bFM3_USB0_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42842834UL))
+#define bFM3_USB0_EP0IS_DRQI                   *((volatile unsigned int*)(0x428428A8UL))
+#define bFM3_USB0_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x428428B8UL))
+#define bFM3_USB0_EP0IS_BFINI                  *((volatile unsigned int*)(0x428428BCUL))
+#define bFM3_USB0_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42842900UL))
+#define bFM3_USB0_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42842904UL))
+#define bFM3_USB0_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42842908UL))
+#define bFM3_USB0_EP0OS_SIZE3                  *((volatile unsigned int*)(0x4284290CUL))
+#define bFM3_USB0_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42842910UL))
+#define bFM3_USB0_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42842914UL))
+#define bFM3_USB0_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42842918UL))
+#define bFM3_USB0_EP0OS_SPK                    *((volatile unsigned int*)(0x42842924UL))
+#define bFM3_USB0_EP0OS_DRQO                   *((volatile unsigned int*)(0x42842928UL))
+#define bFM3_USB0_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42842934UL))
+#define bFM3_USB0_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42842938UL))
+#define bFM3_USB0_EP0OS_BFINI                  *((volatile unsigned int*)(0x4284293CUL))
+#define bFM3_USB0_EP1S_SIZE10                  *((volatile unsigned int*)(0x42842980UL))
+#define bFM3_USB0_EP1S_SIZE11                  *((volatile unsigned int*)(0x42842984UL))
+#define bFM3_USB0_EP1S_SIZE12                  *((volatile unsigned int*)(0x42842988UL))
+#define bFM3_USB0_EP1S_SIZE13                  *((volatile unsigned int*)(0x4284298CUL))
+#define bFM3_USB0_EP1S_SIZE14                  *((volatile unsigned int*)(0x42842990UL))
+#define bFM3_USB0_EP1S_SIZE15                  *((volatile unsigned int*)(0x42842994UL))
+#define bFM3_USB0_EP1S_SIZE16                  *((volatile unsigned int*)(0x42842998UL))
+#define bFM3_USB0_EP1S_SIZE17                  *((volatile unsigned int*)(0x4284299CUL))
+#define bFM3_USB0_EP1S_SIZE18                  *((volatile unsigned int*)(0x428429A0UL))
+#define bFM3_USB0_EP1S_SPK                     *((volatile unsigned int*)(0x428429A4UL))
+#define bFM3_USB0_EP1S_DRQ                     *((volatile unsigned int*)(0x428429A8UL))
+#define bFM3_USB0_EP1S_BUSY                    *((volatile unsigned int*)(0x428429ACUL))
+#define bFM3_USB0_EP1S_SPKIE                   *((volatile unsigned int*)(0x428429B4UL))
+#define bFM3_USB0_EP1S_DRQIE                   *((volatile unsigned int*)(0x428429B8UL))
+#define bFM3_USB0_EP1S_BFINI                   *((volatile unsigned int*)(0x428429BCUL))
+#define bFM3_USB0_EP2S_SIZE20                  *((volatile unsigned int*)(0x42842A00UL))
+#define bFM3_USB0_EP2S_SIZE21                  *((volatile unsigned int*)(0x42842A04UL))
+#define bFM3_USB0_EP2S_SIZE22                  *((volatile unsigned int*)(0x42842A08UL))
+#define bFM3_USB0_EP2S_SIZE23                  *((volatile unsigned int*)(0x42842A0CUL))
+#define bFM3_USB0_EP2S_SIZE24                  *((volatile unsigned int*)(0x42842A10UL))
+#define bFM3_USB0_EP2S_SIZE25                  *((volatile unsigned int*)(0x42842A14UL))
+#define bFM3_USB0_EP2S_SIZE26                  *((volatile unsigned int*)(0x42842A18UL))
+#define bFM3_USB0_EP2S_SPK                     *((volatile unsigned int*)(0x42842A24UL))
+#define bFM3_USB0_EP2S_DRQ                     *((volatile unsigned int*)(0x42842A28UL))
+#define bFM3_USB0_EP2S_BUSY                    *((volatile unsigned int*)(0x42842A2CUL))
+#define bFM3_USB0_EP2S_SPKIE                   *((volatile unsigned int*)(0x42842A34UL))
+#define bFM3_USB0_EP2S_DRQIE                   *((volatile unsigned int*)(0x42842A38UL))
+#define bFM3_USB0_EP2S_BFINI                   *((volatile unsigned int*)(0x42842A3CUL))
+#define bFM3_USB0_EP3S_SIZE30                  *((volatile unsigned int*)(0x42842A80UL))
+#define bFM3_USB0_EP3S_SIZE31                  *((volatile unsigned int*)(0x42842A84UL))
+#define bFM3_USB0_EP3S_SIZE32                  *((volatile unsigned int*)(0x42842A88UL))
+#define bFM3_USB0_EP3S_SIZE33                  *((volatile unsigned int*)(0x42842A8CUL))
+#define bFM3_USB0_EP3S_SIZE34                  *((volatile unsigned int*)(0x42842A90UL))
+#define bFM3_USB0_EP3S_SIZE35                  *((volatile unsigned int*)(0x42842A94UL))
+#define bFM3_USB0_EP3S_SIZE36                  *((volatile unsigned int*)(0x42842A98UL))
+#define bFM3_USB0_EP3S_SPK                     *((volatile unsigned int*)(0x42842AA4UL))
+#define bFM3_USB0_EP3S_DRQ                     *((volatile unsigned int*)(0x42842AA8UL))
+#define bFM3_USB0_EP3S_BUSY                    *((volatile unsigned int*)(0x42842AACUL))
+#define bFM3_USB0_EP3S_SPKIE                   *((volatile unsigned int*)(0x42842AB4UL))
+#define bFM3_USB0_EP3S_DRQIE                   *((volatile unsigned int*)(0x42842AB8UL))
+#define bFM3_USB0_EP3S_BFINI                   *((volatile unsigned int*)(0x42842ABCUL))
+#define bFM3_USB0_EP4S_SIZE40                  *((volatile unsigned int*)(0x42842B00UL))
+#define bFM3_USB0_EP4S_SIZE41                  *((volatile unsigned int*)(0x42842B04UL))
+#define bFM3_USB0_EP4S_SIZE42                  *((volatile unsigned int*)(0x42842B08UL))
+#define bFM3_USB0_EP4S_SIZE43                  *((volatile unsigned int*)(0x42842B0CUL))
+#define bFM3_USB0_EP4S_SIZE44                  *((volatile unsigned int*)(0x42842B10UL))
+#define bFM3_USB0_EP4S_SIZE45                  *((volatile unsigned int*)(0x42842B14UL))
+#define bFM3_USB0_EP4S_SIZE46                  *((volatile unsigned int*)(0x42842B18UL))
+#define bFM3_USB0_EP4S_SPK                     *((volatile unsigned int*)(0x42842B24UL))
+#define bFM3_USB0_EP4S_DRQ                     *((volatile unsigned int*)(0x42842B28UL))
+#define bFM3_USB0_EP4S_BUSY                    *((volatile unsigned int*)(0x42842B2CUL))
+#define bFM3_USB0_EP4S_SPKIE                   *((volatile unsigned int*)(0x42842B34UL))
+#define bFM3_USB0_EP4S_DRQIE                   *((volatile unsigned int*)(0x42842B38UL))
+#define bFM3_USB0_EP4S_BFINI                   *((volatile unsigned int*)(0x42842B3CUL))
+#define bFM3_USB0_EP5S_SIZE50                  *((volatile unsigned int*)(0x42842B80UL))
+#define bFM3_USB0_EP5S_SIZE51                  *((volatile unsigned int*)(0x42842B84UL))
+#define bFM3_USB0_EP5S_SIZE52                  *((volatile unsigned int*)(0x42842B88UL))
+#define bFM3_USB0_EP5S_SIZE53                  *((volatile unsigned int*)(0x42842B8CUL))
+#define bFM3_USB0_EP5S_SIZE54                  *((volatile unsigned int*)(0x42842B90UL))
+#define bFM3_USB0_EP5S_SIZE55                  *((volatile unsigned int*)(0x42842B94UL))
+#define bFM3_USB0_EP5S_SIZE56                  *((volatile unsigned int*)(0x42842B98UL))
+#define bFM3_USB0_EP5S_SPK                     *((volatile unsigned int*)(0x42842BA4UL))
+#define bFM3_USB0_EP5S_DRQ                     *((volatile unsigned int*)(0x42842BA8UL))
+#define bFM3_USB0_EP5S_BUSY                    *((volatile unsigned int*)(0x42842BACUL))
+#define bFM3_USB0_EP5S_SPKIE                   *((volatile unsigned int*)(0x42842BB4UL))
+#define bFM3_USB0_EP5S_DRQIE                   *((volatile unsigned int*)(0x42842BB8UL))
+#define bFM3_USB0_EP5S_BFINI                   *((volatile unsigned int*)(0x42842BBCUL))
+
+/* USB channel 1 registers */
+#define bFM3_USB1_HCNT_HOST                    *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT_URST                    *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT_DIRE                    *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT_URIRE                   *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT_RWKIRE                  *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT_RETRY                   *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT_CANCEL                  *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HCNT0_HOST                   *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT0_URST                   *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT0_DIRE                   *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT0_URIRE                  *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT1_RETRY                  *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42A42080UL))
+#define bFM3_USB1_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42A42084UL))
+#define bFM3_USB1_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42A42088UL))
+#define bFM3_USB1_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x42A4208CUL))
+#define bFM3_USB1_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42A42090UL))
+#define bFM3_USB1_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42A42094UL))
+#define bFM3_USB1_HIRQ_TCAN                    *((volatile unsigned int*)(0x42A4209CUL))
+#define bFM3_USB1_HERR_HS0                     *((volatile unsigned int*)(0x42A420A0UL))
+#define bFM3_USB1_HERR_HS1                     *((volatile unsigned int*)(0x42A420A4UL))
+#define bFM3_USB1_HERR_STUFF                   *((volatile unsigned int*)(0x42A420A8UL))
+#define bFM3_USB1_HERR_TGERR                   *((volatile unsigned int*)(0x42A420ACUL))
+#define bFM3_USB1_HERR_CRC                     *((volatile unsigned int*)(0x42A420B0UL))
+#define bFM3_USB1_HERR_TOUT                    *((volatile unsigned int*)(0x42A420B4UL))
+#define bFM3_USB1_HERR_RERR                    *((volatile unsigned int*)(0x42A420B8UL))
+#define bFM3_USB1_HERR_LSTOF                   *((volatile unsigned int*)(0x42A420BCUL))
+#define bFM3_USB1_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42A42100UL))
+#define bFM3_USB1_HSTATE_TMODE                 *((volatile unsigned int*)(0x42A42104UL))
+#define bFM3_USB1_HSTATE_SUSP                  *((volatile unsigned int*)(0x42A42108UL))
+#define bFM3_USB1_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x42A4210CUL))
+#define bFM3_USB1_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42A42110UL))
+#define bFM3_USB1_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42A42114UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42A42120UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42A42124UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42A42128UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x42A4212CUL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42A42130UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42A42134UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42A42138UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x42A4213CUL))
+#define bFM3_USB1_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42A42200UL))
+#define bFM3_USB1_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42A42204UL))
+#define bFM3_USB1_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42A42208UL))
+#define bFM3_USB1_HADR_ADDRESS0                *((volatile unsigned int*)(0x42A42220UL))
+#define bFM3_USB1_HADR_ADDRESS1                *((volatile unsigned int*)(0x42A42224UL))
+#define bFM3_USB1_HADR_ADDRESS2                *((volatile unsigned int*)(0x42A42228UL))
+#define bFM3_USB1_HADR_ADDRESS3                *((volatile unsigned int*)(0x42A4222CUL))
+#define bFM3_USB1_HADR_ADDRESS4                *((volatile unsigned int*)(0x42A42230UL))
+#define bFM3_USB1_HADR_ADDRESS5                *((volatile unsigned int*)(0x42A42234UL))
+#define bFM3_USB1_HADR_ADDRESS6                *((volatile unsigned int*)(0x42A42238UL))
+#define bFM3_USB1_HEOF_EOF0                    *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF_EOF1                    *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF_EOF2                    *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF_EOF3                    *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF_EOF4                    *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF_EOF5                    *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF_EOF6                    *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF_EOF7                    *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF_EOF8                    *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF_EOF9                    *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF_EOF10                   *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF_EOF11                   *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF_EOF12                   *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF_EOF13                   *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HEOF_EOF14                   *((volatile unsigned int*)(0x42A422B8UL))
+#define bFM3_USB1_HEOF_EOF15                   *((volatile unsigned int*)(0x42A422BCUL))
+#define bFM3_USB1_HEOF0_EOF00                  *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF0_EOF01                  *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF0_EOF02                  *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF0_EOF03                  *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF0_EOF04                  *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF0_EOF05                  *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF0_EOF06                  *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF0_EOF07                  *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF1_EOF10                  *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF1_EOF11                  *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF1_EOF12                  *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF1_EOF13                  *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF1_EOF14                  *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF1_EOF15                  *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HFRAME_FRAME0                *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME_FRAME1                *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME_FRAME2                *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME_FRAME3                *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME_FRAME4                *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME_FRAME5                *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME_FRAME6                *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME_FRAME7                *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME_FRAME8                *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME_FRAME9                *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME_FRAME10               *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME0_FRAME03              *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME0_FRAME07              *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME1_FRAME13              *((volatile unsigned int*)(0x42A4232CUL))
+#define bFM3_USB1_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42A42380UL))
+#define bFM3_USB1_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42A42384UL))
+#define bFM3_USB1_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42A42388UL))
+#define bFM3_USB1_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x42A4238CUL))
+#define bFM3_USB1_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42A42390UL))
+#define bFM3_USB1_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42A42394UL))
+#define bFM3_USB1_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42A42398UL))
+#define bFM3_USB1_HTOKEN_TGGL                  *((volatile unsigned int*)(0x42A4239CUL))
+#define bFM3_USB1_UDCC_PWC                     *((volatile unsigned int*)(0x42A42400UL))
+#define bFM3_USB1_UDCC_RFBK                    *((volatile unsigned int*)(0x42A42404UL))
+#define bFM3_USB1_UDCC_STALCLREN               *((volatile unsigned int*)(0x42A4240CUL))
+#define bFM3_USB1_UDCC_USTP                    *((volatile unsigned int*)(0x42A42410UL))
+#define bFM3_USB1_UDCC_HCONX                   *((volatile unsigned int*)(0x42A42414UL))
+#define bFM3_USB1_UDCC_RESUM                   *((volatile unsigned int*)(0x42A42418UL))
+#define bFM3_USB1_UDCC_RST                     *((volatile unsigned int*)(0x42A4241CUL))
+#define bFM3_USB1_EP0C_PKS00                   *((volatile unsigned int*)(0x42A42480UL))
+#define bFM3_USB1_EP0C_PKS01                   *((volatile unsigned int*)(0x42A42484UL))
+#define bFM3_USB1_EP0C_PKS02                   *((volatile unsigned int*)(0x42A42488UL))
+#define bFM3_USB1_EP0C_PKS03                   *((volatile unsigned int*)(0x42A4248CUL))
+#define bFM3_USB1_EP0C_PKS04                   *((volatile unsigned int*)(0x42A42490UL))
+#define bFM3_USB1_EP0C_PKS05                   *((volatile unsigned int*)(0x42A42494UL))
+#define bFM3_USB1_EP0C_PKS06                   *((volatile unsigned int*)(0x42A42498UL))
+#define bFM3_USB1_EP0C_STAL                    *((volatile unsigned int*)(0x42A424A4UL))
+#define bFM3_USB1_EP1C_PKS10                   *((volatile unsigned int*)(0x42A42500UL))
+#define bFM3_USB1_EP1C_PKS11                   *((volatile unsigned int*)(0x42A42504UL))
+#define bFM3_USB1_EP1C_PKS12                   *((volatile unsigned int*)(0x42A42508UL))
+#define bFM3_USB1_EP1C_PKS13                   *((volatile unsigned int*)(0x42A4250CUL))
+#define bFM3_USB1_EP1C_PKS14                   *((volatile unsigned int*)(0x42A42510UL))
+#define bFM3_USB1_EP1C_PKS15                   *((volatile unsigned int*)(0x42A42514UL))
+#define bFM3_USB1_EP1C_PKS16                   *((volatile unsigned int*)(0x42A42518UL))
+#define bFM3_USB1_EP1C_PKS17                   *((volatile unsigned int*)(0x42A4251CUL))
+#define bFM3_USB1_EP1C_PKS18                   *((volatile unsigned int*)(0x42A42520UL))
+#define bFM3_USB1_EP1C_STAL                    *((volatile unsigned int*)(0x42A42524UL))
+#define bFM3_USB1_EP1C_NULE                    *((volatile unsigned int*)(0x42A42528UL))
+#define bFM3_USB1_EP1C_DMAE                    *((volatile unsigned int*)(0x42A4252CUL))
+#define bFM3_USB1_EP1C_DIR                     *((volatile unsigned int*)(0x42A42530UL))
+#define bFM3_USB1_EP1C_TYPE0                   *((volatile unsigned int*)(0x42A42534UL))
+#define bFM3_USB1_EP1C_TYPE1                   *((volatile unsigned int*)(0x42A42538UL))
+#define bFM3_USB1_EP1C_EPEN                    *((volatile unsigned int*)(0x42A4253CUL))
+#define bFM3_USB1_EP2C_PKS20                   *((volatile unsigned int*)(0x42A42580UL))
+#define bFM3_USB1_EP2C_PKS21                   *((volatile unsigned int*)(0x42A42584UL))
+#define bFM3_USB1_EP2C_PKS22                   *((volatile unsigned int*)(0x42A42588UL))
+#define bFM3_USB1_EP2C_PKS23                   *((volatile unsigned int*)(0x42A4258CUL))
+#define bFM3_USB1_EP2C_PKS24                   *((volatile unsigned int*)(0x42A42590UL))
+#define bFM3_USB1_EP2C_PKS25                   *((volatile unsigned int*)(0x42A42594UL))
+#define bFM3_USB1_EP2C_PKS26                   *((volatile unsigned int*)(0x42A42598UL))
+#define bFM3_USB1_EP2C_STAL                    *((volatile unsigned int*)(0x42A425A4UL))
+#define bFM3_USB1_EP2C_NULE                    *((volatile unsigned int*)(0x42A425A8UL))
+#define bFM3_USB1_EP2C_DMAE                    *((volatile unsigned int*)(0x42A425ACUL))
+#define bFM3_USB1_EP2C_DIR                     *((volatile unsigned int*)(0x42A425B0UL))
+#define bFM3_USB1_EP2C_TYPE0                   *((volatile unsigned int*)(0x42A425B4UL))
+#define bFM3_USB1_EP2C_TYPE1                   *((volatile unsigned int*)(0x42A425B8UL))
+#define bFM3_USB1_EP2C_EPEN                    *((volatile unsigned int*)(0x42A425BCUL))
+#define bFM3_USB1_EP3C_PKS30                   *((volatile unsigned int*)(0x42A42600UL))
+#define bFM3_USB1_EP3C_PKS31                   *((volatile unsigned int*)(0x42A42604UL))
+#define bFM3_USB1_EP3C_PKS32                   *((volatile unsigned int*)(0x42A42608UL))
+#define bFM3_USB1_EP3C_PKS33                   *((volatile unsigned int*)(0x42A4260CUL))
+#define bFM3_USB1_EP3C_PKS34                   *((volatile unsigned int*)(0x42A42610UL))
+#define bFM3_USB1_EP3C_PKS35                   *((volatile unsigned int*)(0x42A42614UL))
+#define bFM3_USB1_EP3C_PKS36                   *((volatile unsigned int*)(0x42A42618UL))
+#define bFM3_USB1_EP3C_STAL                    *((volatile unsigned int*)(0x42A42624UL))
+#define bFM3_USB1_EP3C_NULE                    *((volatile unsigned int*)(0x42A42628UL))
+#define bFM3_USB1_EP3C_DMAE                    *((volatile unsigned int*)(0x42A4262CUL))
+#define bFM3_USB1_EP3C_DIR                     *((volatile unsigned int*)(0x42A42630UL))
+#define bFM3_USB1_EP3C_TYPE0                   *((volatile unsigned int*)(0x42A42634UL))
+#define bFM3_USB1_EP3C_TYPE1                   *((volatile unsigned int*)(0x42A42638UL))
+#define bFM3_USB1_EP3C_EPEN                    *((volatile unsigned int*)(0x42A4263CUL))
+#define bFM3_USB1_EP4C_PKS40                   *((volatile unsigned int*)(0x42A42680UL))
+#define bFM3_USB1_EP4C_PKS41                   *((volatile unsigned int*)(0x42A42684UL))
+#define bFM3_USB1_EP4C_PKS42                   *((volatile unsigned int*)(0x42A42688UL))
+#define bFM3_USB1_EP4C_PKS43                   *((volatile unsigned int*)(0x42A4268CUL))
+#define bFM3_USB1_EP4C_PKS44                   *((volatile unsigned int*)(0x42A42690UL))
+#define bFM3_USB1_EP4C_PKS45                   *((volatile unsigned int*)(0x42A42694UL))
+#define bFM3_USB1_EP4C_PKS46                   *((volatile unsigned int*)(0x42A42698UL))
+#define bFM3_USB1_EP4C_STAL                    *((volatile unsigned int*)(0x42A426A4UL))
+#define bFM3_USB1_EP4C_NULE                    *((volatile unsigned int*)(0x42A426A8UL))
+#define bFM3_USB1_EP4C_DMAE                    *((volatile unsigned int*)(0x42A426ACUL))
+#define bFM3_USB1_EP4C_DIR                     *((volatile unsigned int*)(0x42A426B0UL))
+#define bFM3_USB1_EP4C_TYPE0                   *((volatile unsigned int*)(0x42A426B4UL))
+#define bFM3_USB1_EP4C_TYPE1                   *((volatile unsigned int*)(0x42A426B8UL))
+#define bFM3_USB1_EP4C_EPEN                    *((volatile unsigned int*)(0x42A426BCUL))
+#define bFM3_USB1_EP5C_PKS50                   *((volatile unsigned int*)(0x42A42700UL))
+#define bFM3_USB1_EP5C_PKS51                   *((volatile unsigned int*)(0x42A42704UL))
+#define bFM3_USB1_EP5C_PKS52                   *((volatile unsigned int*)(0x42A42708UL))
+#define bFM3_USB1_EP5C_PKS53                   *((volatile unsigned int*)(0x42A4270CUL))
+#define bFM3_USB1_EP5C_PKS54                   *((volatile unsigned int*)(0x42A42710UL))
+#define bFM3_USB1_EP5C_PKS55                   *((volatile unsigned int*)(0x42A42714UL))
+#define bFM3_USB1_EP5C_PKS56                   *((volatile unsigned int*)(0x42A42718UL))
+#define bFM3_USB1_EP5C_STAL                    *((volatile unsigned int*)(0x42A42724UL))
+#define bFM3_USB1_EP5C_NULE                    *((volatile unsigned int*)(0x42A42728UL))
+#define bFM3_USB1_EP5C_DMAE                    *((volatile unsigned int*)(0x42A4272CUL))
+#define bFM3_USB1_EP5C_DIR                     *((volatile unsigned int*)(0x42A42730UL))
+#define bFM3_USB1_EP5C_TYPE0                   *((volatile unsigned int*)(0x42A42734UL))
+#define bFM3_USB1_EP5C_TYPE1                   *((volatile unsigned int*)(0x42A42738UL))
+#define bFM3_USB1_EP5C_EPEN                    *((volatile unsigned int*)(0x42A4273CUL))
+#define bFM3_USB1_TMSP_TMSP0                   *((volatile unsigned int*)(0x42A42780UL))
+#define bFM3_USB1_TMSP_TMSP1                   *((volatile unsigned int*)(0x42A42784UL))
+#define bFM3_USB1_TMSP_TMSP2                   *((volatile unsigned int*)(0x42A42788UL))
+#define bFM3_USB1_TMSP_TMSP3                   *((volatile unsigned int*)(0x42A4278CUL))
+#define bFM3_USB1_TMSP_TMSP4                   *((volatile unsigned int*)(0x42A42790UL))
+#define bFM3_USB1_TMSP_TMSP5                   *((volatile unsigned int*)(0x42A42794UL))
+#define bFM3_USB1_TMSP_TMSP6                   *((volatile unsigned int*)(0x42A42798UL))
+#define bFM3_USB1_TMSP_TMSP7                   *((volatile unsigned int*)(0x42A4279CUL))
+#define bFM3_USB1_TMSP_TMSP8                   *((volatile unsigned int*)(0x42A427A0UL))
+#define bFM3_USB1_TMSP_TMSP9                   *((volatile unsigned int*)(0x42A427A4UL))
+#define bFM3_USB1_TMSP_TMSP10                  *((volatile unsigned int*)(0x42A427A8UL))
+#define bFM3_USB1_UDCS_CONF                    *((volatile unsigned int*)(0x42A42800UL))
+#define bFM3_USB1_UDCS_SETP                    *((volatile unsigned int*)(0x42A42804UL))
+#define bFM3_USB1_UDCS_WKUP                    *((volatile unsigned int*)(0x42A42808UL))
+#define bFM3_USB1_UDCS_BRST                    *((volatile unsigned int*)(0x42A4280CUL))
+#define bFM3_USB1_UDCS_SOF                     *((volatile unsigned int*)(0x42A42810UL))
+#define bFM3_USB1_UDCS_SUSP                    *((volatile unsigned int*)(0x42A42814UL))
+#define bFM3_USB1_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42A42820UL))
+#define bFM3_USB1_UDCIE_CONFN                  *((volatile unsigned int*)(0x42A42824UL))
+#define bFM3_USB1_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42A42828UL))
+#define bFM3_USB1_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x42A4282CUL))
+#define bFM3_USB1_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42A42830UL))
+#define bFM3_USB1_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42A42834UL))
+#define bFM3_USB1_EP0IS_DRQI                   *((volatile unsigned int*)(0x42A428A8UL))
+#define bFM3_USB1_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x42A428B8UL))
+#define bFM3_USB1_EP0IS_BFINI                  *((volatile unsigned int*)(0x42A428BCUL))
+#define bFM3_USB1_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42A42900UL))
+#define bFM3_USB1_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42A42904UL))
+#define bFM3_USB1_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42A42908UL))
+#define bFM3_USB1_EP0OS_SIZE3                  *((volatile unsigned int*)(0x42A4290CUL))
+#define bFM3_USB1_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42A42910UL))
+#define bFM3_USB1_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42A42914UL))
+#define bFM3_USB1_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42A42918UL))
+#define bFM3_USB1_EP0OS_SPK                    *((volatile unsigned int*)(0x42A42924UL))
+#define bFM3_USB1_EP0OS_DRQO                   *((volatile unsigned int*)(0x42A42928UL))
+#define bFM3_USB1_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42A42934UL))
+#define bFM3_USB1_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42A42938UL))
+#define bFM3_USB1_EP0OS_BFINI                  *((volatile unsigned int*)(0x42A4293CUL))
+#define bFM3_USB1_EP1S_SIZE10                  *((volatile unsigned int*)(0x42A42980UL))
+#define bFM3_USB1_EP1S_SIZE11                  *((volatile unsigned int*)(0x42A42984UL))
+#define bFM3_USB1_EP1S_SIZE12                  *((volatile unsigned int*)(0x42A42988UL))
+#define bFM3_USB1_EP1S_SIZE13                  *((volatile unsigned int*)(0x42A4298CUL))
+#define bFM3_USB1_EP1S_SIZE14                  *((volatile unsigned int*)(0x42A42990UL))
+#define bFM3_USB1_EP1S_SIZE15                  *((volatile unsigned int*)(0x42A42994UL))
+#define bFM3_USB1_EP1S_SIZE16                  *((volatile unsigned int*)(0x42A42998UL))
+#define bFM3_USB1_EP1S_SIZE17                  *((volatile unsigned int*)(0x42A4299CUL))
+#define bFM3_USB1_EP1S_SIZE18                  *((volatile unsigned int*)(0x42A429A0UL))
+#define bFM3_USB1_EP1S_SPK                     *((volatile unsigned int*)(0x42A429A4UL))
+#define bFM3_USB1_EP1S_DRQ                     *((volatile unsigned int*)(0x42A429A8UL))
+#define bFM3_USB1_EP1S_BUSY                    *((volatile unsigned int*)(0x42A429ACUL))
+#define bFM3_USB1_EP1S_SPKIE                   *((volatile unsigned int*)(0x42A429B4UL))
+#define bFM3_USB1_EP1S_DRQIE                   *((volatile unsigned int*)(0x42A429B8UL))
+#define bFM3_USB1_EP1S_BFINI                   *((volatile unsigned int*)(0x42A429BCUL))
+#define bFM3_USB1_EP2S_SIZE20                  *((volatile unsigned int*)(0x42A42A00UL))
+#define bFM3_USB1_EP2S_SIZE21                  *((volatile unsigned int*)(0x42A42A04UL))
+#define bFM3_USB1_EP2S_SIZE22                  *((volatile unsigned int*)(0x42A42A08UL))
+#define bFM3_USB1_EP2S_SIZE23                  *((volatile unsigned int*)(0x42A42A0CUL))
+#define bFM3_USB1_EP2S_SIZE24                  *((volatile unsigned int*)(0x42A42A10UL))
+#define bFM3_USB1_EP2S_SIZE25                  *((volatile unsigned int*)(0x42A42A14UL))
+#define bFM3_USB1_EP2S_SIZE26                  *((volatile unsigned int*)(0x42A42A18UL))
+#define bFM3_USB1_EP2S_SPK                     *((volatile unsigned int*)(0x42A42A24UL))
+#define bFM3_USB1_EP2S_DRQ                     *((volatile unsigned int*)(0x42A42A28UL))
+#define bFM3_USB1_EP2S_BUSY                    *((volatile unsigned int*)(0x42A42A2CUL))
+#define bFM3_USB1_EP2S_SPKIE                   *((volatile unsigned int*)(0x42A42A34UL))
+#define bFM3_USB1_EP2S_DRQIE                   *((volatile unsigned int*)(0x42A42A38UL))
+#define bFM3_USB1_EP2S_BFINI                   *((volatile unsigned int*)(0x42A42A3CUL))
+#define bFM3_USB1_EP3S_SIZE30                  *((volatile unsigned int*)(0x42A42A80UL))
+#define bFM3_USB1_EP3S_SIZE31                  *((volatile unsigned int*)(0x42A42A84UL))
+#define bFM3_USB1_EP3S_SIZE32                  *((volatile unsigned int*)(0x42A42A88UL))
+#define bFM3_USB1_EP3S_SIZE33                  *((volatile unsigned int*)(0x42A42A8CUL))
+#define bFM3_USB1_EP3S_SIZE34                  *((volatile unsigned int*)(0x42A42A90UL))
+#define bFM3_USB1_EP3S_SIZE35                  *((volatile unsigned int*)(0x42A42A94UL))
+#define bFM3_USB1_EP3S_SIZE36                  *((volatile unsigned int*)(0x42A42A98UL))
+#define bFM3_USB1_EP3S_SPK                     *((volatile unsigned int*)(0x42A42AA4UL))
+#define bFM3_USB1_EP3S_DRQ                     *((volatile unsigned int*)(0x42A42AA8UL))
+#define bFM3_USB1_EP3S_BUSY                    *((volatile unsigned int*)(0x42A42AACUL))
+#define bFM3_USB1_EP3S_SPKIE                   *((volatile unsigned int*)(0x42A42AB4UL))
+#define bFM3_USB1_EP3S_DRQIE                   *((volatile unsigned int*)(0x42A42AB8UL))
+#define bFM3_USB1_EP3S_BFINI                   *((volatile unsigned int*)(0x42A42ABCUL))
+#define bFM3_USB1_EP4S_SIZE40                  *((volatile unsigned int*)(0x42A42B00UL))
+#define bFM3_USB1_EP4S_SIZE41                  *((volatile unsigned int*)(0x42A42B04UL))
+#define bFM3_USB1_EP4S_SIZE42                  *((volatile unsigned int*)(0x42A42B08UL))
+#define bFM3_USB1_EP4S_SIZE43                  *((volatile unsigned int*)(0x42A42B0CUL))
+#define bFM3_USB1_EP4S_SIZE44                  *((volatile unsigned int*)(0x42A42B10UL))
+#define bFM3_USB1_EP4S_SIZE45                  *((volatile unsigned int*)(0x42A42B14UL))
+#define bFM3_USB1_EP4S_SIZE46                  *((volatile unsigned int*)(0x42A42B18UL))
+#define bFM3_USB1_EP4S_SPK                     *((volatile unsigned int*)(0x42A42B24UL))
+#define bFM3_USB1_EP4S_DRQ                     *((volatile unsigned int*)(0x42A42B28UL))
+#define bFM3_USB1_EP4S_BUSY                    *((volatile unsigned int*)(0x42A42B2CUL))
+#define bFM3_USB1_EP4S_SPKIE                   *((volatile unsigned int*)(0x42A42B34UL))
+#define bFM3_USB1_EP4S_DRQIE                   *((volatile unsigned int*)(0x42A42B38UL))
+#define bFM3_USB1_EP4S_BFINI                   *((volatile unsigned int*)(0x42A42B3CUL))
+#define bFM3_USB1_EP5S_SIZE50                  *((volatile unsigned int*)(0x42A42B80UL))
+#define bFM3_USB1_EP5S_SIZE51                  *((volatile unsigned int*)(0x42A42B84UL))
+#define bFM3_USB1_EP5S_SIZE52                  *((volatile unsigned int*)(0x42A42B88UL))
+#define bFM3_USB1_EP5S_SIZE53                  *((volatile unsigned int*)(0x42A42B8CUL))
+#define bFM3_USB1_EP5S_SIZE54                  *((volatile unsigned int*)(0x42A42B90UL))
+#define bFM3_USB1_EP5S_SIZE55                  *((volatile unsigned int*)(0x42A42B94UL))
+#define bFM3_USB1_EP5S_SIZE56                  *((volatile unsigned int*)(0x42A42B98UL))
+#define bFM3_USB1_EP5S_SPK                     *((volatile unsigned int*)(0x42A42BA4UL))
+#define bFM3_USB1_EP5S_DRQ                     *((volatile unsigned int*)(0x42A42BA8UL))
+#define bFM3_USB1_EP5S_BUSY                    *((volatile unsigned int*)(0x42A42BACUL))
+#define bFM3_USB1_EP5S_SPKIE                   *((volatile unsigned int*)(0x42A42BB4UL))
+#define bFM3_USB1_EP5S_DRQIE                   *((volatile unsigned int*)(0x42A42BB8UL))
+#define bFM3_USB1_EP5S_BFINI                   *((volatile unsigned int*)(0x42A42BBCUL))
+
+/* DMA controller */
+#define bFM3_DMAC_DMACR_DH0                    *((volatile unsigned int*)(0x42C00060UL))
+#define bFM3_DMAC_DMACR_DH1                    *((volatile unsigned int*)(0x42C00064UL))
+#define bFM3_DMAC_DMACR_DH2                    *((volatile unsigned int*)(0x42C00068UL))
+#define bFM3_DMAC_DMACR_DH3                    *((volatile unsigned int*)(0x42C0006CUL))
+#define bFM3_DMAC_DMACR_PR                     *((volatile unsigned int*)(0x42C00070UL))
+#define bFM3_DMAC_DMACR_DS                     *((volatile unsigned int*)(0x42C00078UL))
+#define bFM3_DMAC_DMACR_DE                     *((volatile unsigned int*)(0x42C0007CUL))
+#define bFM3_DMAC_DMACA0_TC0                   *((volatile unsigned int*)(0x42C00200UL))
+#define bFM3_DMAC_DMACA0_TC1                   *((volatile unsigned int*)(0x42C00204UL))
+#define bFM3_DMAC_DMACA0_TC2                   *((volatile unsigned int*)(0x42C00208UL))
+#define bFM3_DMAC_DMACA0_TC3                   *((volatile unsigned int*)(0x42C0020CUL))
+#define bFM3_DMAC_DMACA0_TC4                   *((volatile unsigned int*)(0x42C00210UL))
+#define bFM3_DMAC_DMACA0_TC5                   *((volatile unsigned int*)(0x42C00214UL))
+#define bFM3_DMAC_DMACA0_TC6                   *((volatile unsigned int*)(0x42C00218UL))
+#define bFM3_DMAC_DMACA0_TC7                   *((volatile unsigned int*)(0x42C0021CUL))
+#define bFM3_DMAC_DMACA0_TC8                   *((volatile unsigned int*)(0x42C00220UL))
+#define bFM3_DMAC_DMACA0_TC9                   *((volatile unsigned int*)(0x42C00224UL))
+#define bFM3_DMAC_DMACA0_TC10                  *((volatile unsigned int*)(0x42C00228UL))
+#define bFM3_DMAC_DMACA0_TC11                  *((volatile unsigned int*)(0x42C0022CUL))
+#define bFM3_DMAC_DMACA0_TC12                  *((volatile unsigned int*)(0x42C00230UL))
+#define bFM3_DMAC_DMACA0_TC13                  *((volatile unsigned int*)(0x42C00234UL))
+#define bFM3_DMAC_DMACA0_TC14                  *((volatile unsigned int*)(0x42C00238UL))
+#define bFM3_DMAC_DMACA0_TC15                  *((volatile unsigned int*)(0x42C0023CUL))
+#define bFM3_DMAC_DMACA0_BC0                   *((volatile unsigned int*)(0x42C00240UL))
+#define bFM3_DMAC_DMACA0_BC1                   *((volatile unsigned int*)(0x42C00244UL))
+#define bFM3_DMAC_DMACA0_BC2                   *((volatile unsigned int*)(0x42C00248UL))
+#define bFM3_DMAC_DMACA0_BC3                   *((volatile unsigned int*)(0x42C0024CUL))
+#define bFM3_DMAC_DMACA0_IS0                   *((volatile unsigned int*)(0x42C0025CUL))
+#define bFM3_DMAC_DMACA0_IS1                   *((volatile unsigned int*)(0x42C00260UL))
+#define bFM3_DMAC_DMACA0_IS2                   *((volatile unsigned int*)(0x42C00264UL))
+#define bFM3_DMAC_DMACA0_IS3                   *((volatile unsigned int*)(0x42C00268UL))
+#define bFM3_DMAC_DMACA0_IS4                   *((volatile unsigned int*)(0x42C0026CUL))
+#define bFM3_DMAC_DMACA0_IS5                   *((volatile unsigned int*)(0x42C00270UL))
+#define bFM3_DMAC_DMACA0_ST                    *((volatile unsigned int*)(0x42C00274UL))
+#define bFM3_DMAC_DMACA0_PB                    *((volatile unsigned int*)(0x42C00278UL))
+#define bFM3_DMAC_DMACA0_EB                    *((volatile unsigned int*)(0x42C0027CUL))
+#define bFM3_DMAC_DMACB0_EM                    *((volatile unsigned int*)(0x42C00280UL))
+#define bFM3_DMAC_DMACB0_SS0                   *((volatile unsigned int*)(0x42C002C0UL))
+#define bFM3_DMAC_DMACB0_SS1                   *((volatile unsigned int*)(0x42C002C4UL))
+#define bFM3_DMAC_DMACB0_SS2                   *((volatile unsigned int*)(0x42C002C8UL))
+#define bFM3_DMAC_DMACB0_CI                    *((volatile unsigned int*)(0x42C002CCUL))
+#define bFM3_DMAC_DMACB0_EI                    *((volatile unsigned int*)(0x42C002D0UL))
+#define bFM3_DMAC_DMACB0_RD                    *((volatile unsigned int*)(0x42C002D4UL))
+#define bFM3_DMAC_DMACB0_RS                    *((volatile unsigned int*)(0x42C002D8UL))
+#define bFM3_DMAC_DMACB0_RC                    *((volatile unsigned int*)(0x42C002DCUL))
+#define bFM3_DMAC_DMACB0_FD                    *((volatile unsigned int*)(0x42C002E0UL))
+#define bFM3_DMAC_DMACB0_FS                    *((volatile unsigned int*)(0x42C002E4UL))
+#define bFM3_DMAC_DMACB0_TW0                   *((volatile unsigned int*)(0x42C002E8UL))
+#define bFM3_DMAC_DMACB0_TW1                   *((volatile unsigned int*)(0x42C002ECUL))
+#define bFM3_DMAC_DMACB0_MS0                   *((volatile unsigned int*)(0x42C002F0UL))
+#define bFM3_DMAC_DMACB0_MS1                   *((volatile unsigned int*)(0x42C002F4UL))
+#define bFM3_DMAC_DMACA1_TC0                   *((volatile unsigned int*)(0x42C00400UL))
+#define bFM3_DMAC_DMACA1_TC1                   *((volatile unsigned int*)(0x42C00404UL))
+#define bFM3_DMAC_DMACA1_TC2                   *((volatile unsigned int*)(0x42C00408UL))
+#define bFM3_DMAC_DMACA1_TC3                   *((volatile unsigned int*)(0x42C0040CUL))
+#define bFM3_DMAC_DMACA1_TC4                   *((volatile unsigned int*)(0x42C00410UL))
+#define bFM3_DMAC_DMACA1_TC5                   *((volatile unsigned int*)(0x42C00414UL))
+#define bFM3_DMAC_DMACA1_TC6                   *((volatile unsigned int*)(0x42C00418UL))
+#define bFM3_DMAC_DMACA1_TC7                   *((volatile unsigned int*)(0x42C0041CUL))
+#define bFM3_DMAC_DMACA1_TC8                   *((volatile unsigned int*)(0x42C00420UL))
+#define bFM3_DMAC_DMACA1_TC9                   *((volatile unsigned int*)(0x42C00424UL))
+#define bFM3_DMAC_DMACA1_TC10                  *((volatile unsigned int*)(0x42C00428UL))
+#define bFM3_DMAC_DMACA1_TC11                  *((volatile unsigned int*)(0x42C0042CUL))
+#define bFM3_DMAC_DMACA1_TC12                  *((volatile unsigned int*)(0x42C00430UL))
+#define bFM3_DMAC_DMACA1_TC13                  *((volatile unsigned int*)(0x42C00434UL))
+#define bFM3_DMAC_DMACA1_TC14                  *((volatile unsigned int*)(0x42C00438UL))
+#define bFM3_DMAC_DMACA1_TC15                  *((volatile unsigned int*)(0x42C0043CUL))
+#define bFM3_DMAC_DMACA1_BC0                   *((volatile unsigned int*)(0x42C00440UL))
+#define bFM3_DMAC_DMACA1_BC1                   *((volatile unsigned int*)(0x42C00444UL))
+#define bFM3_DMAC_DMACA1_BC2                   *((volatile unsigned int*)(0x42C00448UL))
+#define bFM3_DMAC_DMACA1_BC3                   *((volatile unsigned int*)(0x42C0044CUL))
+#define bFM3_DMAC_DMACA1_IS0                   *((volatile unsigned int*)(0x42C0045CUL))
+#define bFM3_DMAC_DMACA1_IS1                   *((volatile unsigned int*)(0x42C00460UL))
+#define bFM3_DMAC_DMACA1_IS2                   *((volatile unsigned int*)(0x42C00464UL))
+#define bFM3_DMAC_DMACA1_IS3                   *((volatile unsigned int*)(0x42C00468UL))
+#define bFM3_DMAC_DMACA1_IS4                   *((volatile unsigned int*)(0x42C0046CUL))
+#define bFM3_DMAC_DMACA1_IS5                   *((volatile unsigned int*)(0x42C00470UL))
+#define bFM3_DMAC_DMACA1_ST                    *((volatile unsigned int*)(0x42C00474UL))
+#define bFM3_DMAC_DMACA1_PB                    *((volatile unsigned int*)(0x42C00478UL))
+#define bFM3_DMAC_DMACA1_EB                    *((volatile unsigned int*)(0x42C0047CUL))
+#define bFM3_DMAC_DMACB1_EM                    *((volatile unsigned int*)(0x42C00480UL))
+#define bFM3_DMAC_DMACB1_SS0                   *((volatile unsigned int*)(0x42C004C0UL))
+#define bFM3_DMAC_DMACB1_SS1                   *((volatile unsigned int*)(0x42C004C4UL))
+#define bFM3_DMAC_DMACB1_SS2                   *((volatile unsigned int*)(0x42C004C8UL))
+#define bFM3_DMAC_DMACB1_CI                    *((volatile unsigned int*)(0x42C004CCUL))
+#define bFM3_DMAC_DMACB1_EI                    *((volatile unsigned int*)(0x42C004D0UL))
+#define bFM3_DMAC_DMACB1_RD                    *((volatile unsigned int*)(0x42C004D4UL))
+#define bFM3_DMAC_DMACB1_RS                    *((volatile unsigned int*)(0x42C004D8UL))
+#define bFM3_DMAC_DMACB1_RC                    *((volatile unsigned int*)(0x42C004DCUL))
+#define bFM3_DMAC_DMACB1_FD                    *((volatile unsigned int*)(0x42C004E0UL))
+#define bFM3_DMAC_DMACB1_FS                    *((volatile unsigned int*)(0x42C004E4UL))
+#define bFM3_DMAC_DMACB1_TW0                   *((volatile unsigned int*)(0x42C004E8UL))
+#define bFM3_DMAC_DMACB1_TW1                   *((volatile unsigned int*)(0x42C004ECUL))
+#define bFM3_DMAC_DMACB1_MS0                   *((volatile unsigned int*)(0x42C004F0UL))
+#define bFM3_DMAC_DMACB1_MS1                   *((volatile unsigned int*)(0x42C004F4UL))
+#define bFM3_DMAC_DMACA2_TC0                   *((volatile unsigned int*)(0x42C00600UL))
+#define bFM3_DMAC_DMACA2_TC1                   *((volatile unsigned int*)(0x42C00604UL))
+#define bFM3_DMAC_DMACA2_TC2                   *((volatile unsigned int*)(0x42C00608UL))
+#define bFM3_DMAC_DMACA2_TC3                   *((volatile unsigned int*)(0x42C0060CUL))
+#define bFM3_DMAC_DMACA2_TC4                   *((volatile unsigned int*)(0x42C00610UL))
+#define bFM3_DMAC_DMACA2_TC5                   *((volatile unsigned int*)(0x42C00614UL))
+#define bFM3_DMAC_DMACA2_TC6                   *((volatile unsigned int*)(0x42C00618UL))
+#define bFM3_DMAC_DMACA2_TC7                   *((volatile unsigned int*)(0x42C0061CUL))
+#define bFM3_DMAC_DMACA2_TC8                   *((volatile unsigned int*)(0x42C00620UL))
+#define bFM3_DMAC_DMACA2_TC9                   *((volatile unsigned int*)(0x42C00624UL))
+#define bFM3_DMAC_DMACA2_TC10                  *((volatile unsigned int*)(0x42C00628UL))
+#define bFM3_DMAC_DMACA2_TC11                  *((volatile unsigned int*)(0x42C0062CUL))
+#define bFM3_DMAC_DMACA2_TC12                  *((volatile unsigned int*)(0x42C00630UL))
+#define bFM3_DMAC_DMACA2_TC13                  *((volatile unsigned int*)(0x42C00634UL))
+#define bFM3_DMAC_DMACA2_TC14                  *((volatile unsigned int*)(0x42C00638UL))
+#define bFM3_DMAC_DMACA2_TC15                  *((volatile unsigned int*)(0x42C0063CUL))
+#define bFM3_DMAC_DMACA2_BC0                   *((volatile unsigned int*)(0x42C00640UL))
+#define bFM3_DMAC_DMACA2_BC1                   *((volatile unsigned int*)(0x42C00644UL))
+#define bFM3_DMAC_DMACA2_BC2                   *((volatile unsigned int*)(0x42C00648UL))
+#define bFM3_DMAC_DMACA2_BC3                   *((volatile unsigned int*)(0x42C0064CUL))
+#define bFM3_DMAC_DMACA2_IS0                   *((volatile unsigned int*)(0x42C0065CUL))
+#define bFM3_DMAC_DMACA2_IS1                   *((volatile unsigned int*)(0x42C00660UL))
+#define bFM3_DMAC_DMACA2_IS2                   *((volatile unsigned int*)(0x42C00664UL))
+#define bFM3_DMAC_DMACA2_IS3                   *((volatile unsigned int*)(0x42C00668UL))
+#define bFM3_DMAC_DMACA2_IS4                   *((volatile unsigned int*)(0x42C0066CUL))
+#define bFM3_DMAC_DMACA2_IS5                   *((volatile unsigned int*)(0x42C00670UL))
+#define bFM3_DMAC_DMACA2_ST                    *((volatile unsigned int*)(0x42C00674UL))
+#define bFM3_DMAC_DMACA2_PB                    *((volatile unsigned int*)(0x42C00678UL))
+#define bFM3_DMAC_DMACA2_EB                    *((volatile unsigned int*)(0x42C0067CUL))
+#define bFM3_DMAC_DMACB2_EM                    *((volatile unsigned int*)(0x42C00680UL))
+#define bFM3_DMAC_DMACB2_SS0                   *((volatile unsigned int*)(0x42C006C0UL))
+#define bFM3_DMAC_DMACB2_SS1                   *((volatile unsigned int*)(0x42C006C4UL))
+#define bFM3_DMAC_DMACB2_SS2                   *((volatile unsigned int*)(0x42C006C8UL))
+#define bFM3_DMAC_DMACB2_CI                    *((volatile unsigned int*)(0x42C006CCUL))
+#define bFM3_DMAC_DMACB2_EI                    *((volatile unsigned int*)(0x42C006D0UL))
+#define bFM3_DMAC_DMACB2_RD                    *((volatile unsigned int*)(0x42C006D4UL))
+#define bFM3_DMAC_DMACB2_RS                    *((volatile unsigned int*)(0x42C006D8UL))
+#define bFM3_DMAC_DMACB2_RC                    *((volatile unsigned int*)(0x42C006DCUL))
+#define bFM3_DMAC_DMACB2_FD                    *((volatile unsigned int*)(0x42C006E0UL))
+#define bFM3_DMAC_DMACB2_FS                    *((volatile unsigned int*)(0x42C006E4UL))
+#define bFM3_DMAC_DMACB2_TW0                   *((volatile unsigned int*)(0x42C006E8UL))
+#define bFM3_DMAC_DMACB2_TW1                   *((volatile unsigned int*)(0x42C006ECUL))
+#define bFM3_DMAC_DMACB2_MS0                   *((volatile unsigned int*)(0x42C006F0UL))
+#define bFM3_DMAC_DMACB2_MS1                   *((volatile unsigned int*)(0x42C006F4UL))
+#define bFM3_DMAC_DMACA3_TC0                   *((volatile unsigned int*)(0x42C00800UL))
+#define bFM3_DMAC_DMACA3_TC1                   *((volatile unsigned int*)(0x42C00804UL))
+#define bFM3_DMAC_DMACA3_TC2                   *((volatile unsigned int*)(0x42C00808UL))
+#define bFM3_DMAC_DMACA3_TC3                   *((volatile unsigned int*)(0x42C0080CUL))
+#define bFM3_DMAC_DMACA3_TC4                   *((volatile unsigned int*)(0x42C00810UL))
+#define bFM3_DMAC_DMACA3_TC5                   *((volatile unsigned int*)(0x42C00814UL))
+#define bFM3_DMAC_DMACA3_TC6                   *((volatile unsigned int*)(0x42C00818UL))
+#define bFM3_DMAC_DMACA3_TC7                   *((volatile unsigned int*)(0x42C0081CUL))
+#define bFM3_DMAC_DMACA3_TC8                   *((volatile unsigned int*)(0x42C00820UL))
+#define bFM3_DMAC_DMACA3_TC9                   *((volatile unsigned int*)(0x42C00824UL))
+#define bFM3_DMAC_DMACA3_TC10                  *((volatile unsigned int*)(0x42C00828UL))
+#define bFM3_DMAC_DMACA3_TC11                  *((volatile unsigned int*)(0x42C0082CUL))
+#define bFM3_DMAC_DMACA3_TC12                  *((volatile unsigned int*)(0x42C00830UL))
+#define bFM3_DMAC_DMACA3_TC13                  *((volatile unsigned int*)(0x42C00834UL))
+#define bFM3_DMAC_DMACA3_TC14                  *((volatile unsigned int*)(0x42C00838UL))
+#define bFM3_DMAC_DMACA3_TC15                  *((volatile unsigned int*)(0x42C0083CUL))
+#define bFM3_DMAC_DMACA3_BC0                   *((volatile unsigned int*)(0x42C00840UL))
+#define bFM3_DMAC_DMACA3_BC1                   *((volatile unsigned int*)(0x42C00844UL))
+#define bFM3_DMAC_DMACA3_BC2                   *((volatile unsigned int*)(0x42C00848UL))
+#define bFM3_DMAC_DMACA3_BC3                   *((volatile unsigned int*)(0x42C0084CUL))
+#define bFM3_DMAC_DMACA3_IS0                   *((volatile unsigned int*)(0x42C0085CUL))
+#define bFM3_DMAC_DMACA3_IS1                   *((volatile unsigned int*)(0x42C00860UL))
+#define bFM3_DMAC_DMACA3_IS2                   *((volatile unsigned int*)(0x42C00864UL))
+#define bFM3_DMAC_DMACA3_IS3                   *((volatile unsigned int*)(0x42C00868UL))
+#define bFM3_DMAC_DMACA3_IS4                   *((volatile unsigned int*)(0x42C0086CUL))
+#define bFM3_DMAC_DMACA3_IS5                   *((volatile unsigned int*)(0x42C00870UL))
+#define bFM3_DMAC_DMACA3_ST                    *((volatile unsigned int*)(0x42C00874UL))
+#define bFM3_DMAC_DMACA3_PB                    *((volatile unsigned int*)(0x42C00878UL))
+#define bFM3_DMAC_DMACA3_EB                    *((volatile unsigned int*)(0x42C0087CUL))
+#define bFM3_DMAC_DMACB3_EM                    *((volatile unsigned int*)(0x42C00880UL))
+#define bFM3_DMAC_DMACB3_SS0                   *((volatile unsigned int*)(0x42C008C0UL))
+#define bFM3_DMAC_DMACB3_SS1                   *((volatile unsigned int*)(0x42C008C4UL))
+#define bFM3_DMAC_DMACB3_SS2                   *((volatile unsigned int*)(0x42C008C8UL))
+#define bFM3_DMAC_DMACB3_CI                    *((volatile unsigned int*)(0x42C008CCUL))
+#define bFM3_DMAC_DMACB3_EI                    *((volatile unsigned int*)(0x42C008D0UL))
+#define bFM3_DMAC_DMACB3_RD                    *((volatile unsigned int*)(0x42C008D4UL))
+#define bFM3_DMAC_DMACB3_RS                    *((volatile unsigned int*)(0x42C008D8UL))
+#define bFM3_DMAC_DMACB3_RC                    *((volatile unsigned int*)(0x42C008DCUL))
+#define bFM3_DMAC_DMACB3_FD                    *((volatile unsigned int*)(0x42C008E0UL))
+#define bFM3_DMAC_DMACB3_FS                    *((volatile unsigned int*)(0x42C008E4UL))
+#define bFM3_DMAC_DMACB3_TW0                   *((volatile unsigned int*)(0x42C008E8UL))
+#define bFM3_DMAC_DMACB3_TW1                   *((volatile unsigned int*)(0x42C008ECUL))
+#define bFM3_DMAC_DMACB3_MS0                   *((volatile unsigned int*)(0x42C008F0UL))
+#define bFM3_DMAC_DMACB3_MS1                   *((volatile unsigned int*)(0x42C008F4UL))
+#define bFM3_DMAC_DMACA4_TC0                   *((volatile unsigned int*)(0x42C00A00UL))
+#define bFM3_DMAC_DMACA4_TC1                   *((volatile unsigned int*)(0x42C00A04UL))
+#define bFM3_DMAC_DMACA4_TC2                   *((volatile unsigned int*)(0x42C00A08UL))
+#define bFM3_DMAC_DMACA4_TC3                   *((volatile unsigned int*)(0x42C00A0CUL))
+#define bFM3_DMAC_DMACA4_TC4                   *((volatile unsigned int*)(0x42C00A10UL))
+#define bFM3_DMAC_DMACA4_TC5                   *((volatile unsigned int*)(0x42C00A14UL))
+#define bFM3_DMAC_DMACA4_TC6                   *((volatile unsigned int*)(0x42C00A18UL))
+#define bFM3_DMAC_DMACA4_TC7                   *((volatile unsigned int*)(0x42C00A1CUL))
+#define bFM3_DMAC_DMACA4_TC8                   *((volatile unsigned int*)(0x42C00A20UL))
+#define bFM3_DMAC_DMACA4_TC9                   *((volatile unsigned int*)(0x42C00A24UL))
+#define bFM3_DMAC_DMACA4_TC10                  *((volatile unsigned int*)(0x42C00A28UL))
+#define bFM3_DMAC_DMACA4_TC11                  *((volatile unsigned int*)(0x42C00A2CUL))
+#define bFM3_DMAC_DMACA4_TC12                  *((volatile unsigned int*)(0x42C00A30UL))
+#define bFM3_DMAC_DMACA4_TC13                  *((volatile unsigned int*)(0x42C00A34UL))
+#define bFM3_DMAC_DMACA4_TC14                  *((volatile unsigned int*)(0x42C00A38UL))
+#define bFM3_DMAC_DMACA4_TC15                  *((volatile unsigned int*)(0x42C00A3CUL))
+#define bFM3_DMAC_DMACA4_BC0                   *((volatile unsigned int*)(0x42C00A40UL))
+#define bFM3_DMAC_DMACA4_BC1                   *((volatile unsigned int*)(0x42C00A44UL))
+#define bFM3_DMAC_DMACA4_BC2                   *((volatile unsigned int*)(0x42C00A48UL))
+#define bFM3_DMAC_DMACA4_BC3                   *((volatile unsigned int*)(0x42C00A4CUL))
+#define bFM3_DMAC_DMACA4_IS0                   *((volatile unsigned int*)(0x42C00A5CUL))
+#define bFM3_DMAC_DMACA4_IS1                   *((volatile unsigned int*)(0x42C00A60UL))
+#define bFM3_DMAC_DMACA4_IS2                   *((volatile unsigned int*)(0x42C00A64UL))
+#define bFM3_DMAC_DMACA4_IS3                   *((volatile unsigned int*)(0x42C00A68UL))
+#define bFM3_DMAC_DMACA4_IS4                   *((volatile unsigned int*)(0x42C00A6CUL))
+#define bFM3_DMAC_DMACA4_IS5                   *((volatile unsigned int*)(0x42C00A70UL))
+#define bFM3_DMAC_DMACA4_ST                    *((volatile unsigned int*)(0x42C00A74UL))
+#define bFM3_DMAC_DMACA4_PB                    *((volatile unsigned int*)(0x42C00A78UL))
+#define bFM3_DMAC_DMACA4_EB                    *((volatile unsigned int*)(0x42C00A7CUL))
+#define bFM3_DMAC_DMACB4_EM                    *((volatile unsigned int*)(0x42C00A80UL))
+#define bFM3_DMAC_DMACB4_SS0                   *((volatile unsigned int*)(0x42C00AC0UL))
+#define bFM3_DMAC_DMACB4_SS1                   *((volatile unsigned int*)(0x42C00AC4UL))
+#define bFM3_DMAC_DMACB4_SS2                   *((volatile unsigned int*)(0x42C00AC8UL))
+#define bFM3_DMAC_DMACB4_CI                    *((volatile unsigned int*)(0x42C00ACCUL))
+#define bFM3_DMAC_DMACB4_EI                    *((volatile unsigned int*)(0x42C00AD0UL))
+#define bFM3_DMAC_DMACB4_RD                    *((volatile unsigned int*)(0x42C00AD4UL))
+#define bFM3_DMAC_DMACB4_RS                    *((volatile unsigned int*)(0x42C00AD8UL))
+#define bFM3_DMAC_DMACB4_RC                    *((volatile unsigned int*)(0x42C00ADCUL))
+#define bFM3_DMAC_DMACB4_FD                    *((volatile unsigned int*)(0x42C00AE0UL))
+#define bFM3_DMAC_DMACB4_FS                    *((volatile unsigned int*)(0x42C00AE4UL))
+#define bFM3_DMAC_DMACB4_TW0                   *((volatile unsigned int*)(0x42C00AE8UL))
+#define bFM3_DMAC_DMACB4_TW1                   *((volatile unsigned int*)(0x42C00AECUL))
+#define bFM3_DMAC_DMACB4_MS0                   *((volatile unsigned int*)(0x42C00AF0UL))
+#define bFM3_DMAC_DMACB4_MS1                   *((volatile unsigned int*)(0x42C00AF4UL))
+#define bFM3_DMAC_DMACA5_TC0                   *((volatile unsigned int*)(0x42C00C00UL))
+#define bFM3_DMAC_DMACA5_TC1                   *((volatile unsigned int*)(0x42C00C04UL))
+#define bFM3_DMAC_DMACA5_TC2                   *((volatile unsigned int*)(0x42C00C08UL))
+#define bFM3_DMAC_DMACA5_TC3                   *((volatile unsigned int*)(0x42C00C0CUL))
+#define bFM3_DMAC_DMACA5_TC4                   *((volatile unsigned int*)(0x42C00C10UL))
+#define bFM3_DMAC_DMACA5_TC5                   *((volatile unsigned int*)(0x42C00C14UL))
+#define bFM3_DMAC_DMACA5_TC6                   *((volatile unsigned int*)(0x42C00C18UL))
+#define bFM3_DMAC_DMACA5_TC7                   *((volatile unsigned int*)(0x42C00C1CUL))
+#define bFM3_DMAC_DMACA5_TC8                   *((volatile unsigned int*)(0x42C00C20UL))
+#define bFM3_DMAC_DMACA5_TC9                   *((volatile unsigned int*)(0x42C00C24UL))
+#define bFM3_DMAC_DMACA5_TC10                  *((volatile unsigned int*)(0x42C00C28UL))
+#define bFM3_DMAC_DMACA5_TC11                  *((volatile unsigned int*)(0x42C00C2CUL))
+#define bFM3_DMAC_DMACA5_TC12                  *((volatile unsigned int*)(0x42C00C30UL))
+#define bFM3_DMAC_DMACA5_TC13                  *((volatile unsigned int*)(0x42C00C34UL))
+#define bFM3_DMAC_DMACA5_TC14                  *((volatile unsigned int*)(0x42C00C38UL))
+#define bFM3_DMAC_DMACA5_TC15                  *((volatile unsigned int*)(0x42C00C3CUL))
+#define bFM3_DMAC_DMACA5_BC0                   *((volatile unsigned int*)(0x42C00C40UL))
+#define bFM3_DMAC_DMACA5_BC1                   *((volatile unsigned int*)(0x42C00C44UL))
+#define bFM3_DMAC_DMACA5_BC2                   *((volatile unsigned int*)(0x42C00C48UL))
+#define bFM3_DMAC_DMACA5_BC3                   *((volatile unsigned int*)(0x42C00C4CUL))
+#define bFM3_DMAC_DMACA5_IS0                   *((volatile unsigned int*)(0x42C00C5CUL))
+#define bFM3_DMAC_DMACA5_IS1                   *((volatile unsigned int*)(0x42C00C60UL))
+#define bFM3_DMAC_DMACA5_IS2                   *((volatile unsigned int*)(0x42C00C64UL))
+#define bFM3_DMAC_DMACA5_IS3                   *((volatile unsigned int*)(0x42C00C68UL))
+#define bFM3_DMAC_DMACA5_IS4                   *((volatile unsigned int*)(0x42C00C6CUL))
+#define bFM3_DMAC_DMACA5_IS5                   *((volatile unsigned int*)(0x42C00C70UL))
+#define bFM3_DMAC_DMACA5_ST                    *((volatile unsigned int*)(0x42C00C74UL))
+#define bFM3_DMAC_DMACA5_PB                    *((volatile unsigned int*)(0x42C00C78UL))
+#define bFM3_DMAC_DMACA5_EB                    *((volatile unsigned int*)(0x42C00C7CUL))
+#define bFM3_DMAC_DMACB5_EM                    *((volatile unsigned int*)(0x42C00C80UL))
+#define bFM3_DMAC_DMACB5_SS0                   *((volatile unsigned int*)(0x42C00CC0UL))
+#define bFM3_DMAC_DMACB5_SS1                   *((volatile unsigned int*)(0x42C00CC4UL))
+#define bFM3_DMAC_DMACB5_SS2                   *((volatile unsigned int*)(0x42C00CC8UL))
+#define bFM3_DMAC_DMACB5_CI                    *((volatile unsigned int*)(0x42C00CCCUL))
+#define bFM3_DMAC_DMACB5_EI                    *((volatile unsigned int*)(0x42C00CD0UL))
+#define bFM3_DMAC_DMACB5_RD                    *((volatile unsigned int*)(0x42C00CD4UL))
+#define bFM3_DMAC_DMACB5_RS                    *((volatile unsigned int*)(0x42C00CD8UL))
+#define bFM3_DMAC_DMACB5_RC                    *((volatile unsigned int*)(0x42C00CDCUL))
+#define bFM3_DMAC_DMACB5_FD                    *((volatile unsigned int*)(0x42C00CE0UL))
+#define bFM3_DMAC_DMACB5_FS                    *((volatile unsigned int*)(0x42C00CE4UL))
+#define bFM3_DMAC_DMACB5_TW0                   *((volatile unsigned int*)(0x42C00CE8UL))
+#define bFM3_DMAC_DMACB5_TW1                   *((volatile unsigned int*)(0x42C00CECUL))
+#define bFM3_DMAC_DMACB5_MS0                   *((volatile unsigned int*)(0x42C00CF0UL))
+#define bFM3_DMAC_DMACB5_MS1                   *((volatile unsigned int*)(0x42C00CF4UL))
+#define bFM3_DMAC_DMACA6_TC0                   *((volatile unsigned int*)(0x42C00E00UL))
+#define bFM3_DMAC_DMACA6_TC1                   *((volatile unsigned int*)(0x42C00E04UL))
+#define bFM3_DMAC_DMACA6_TC2                   *((volatile unsigned int*)(0x42C00E08UL))
+#define bFM3_DMAC_DMACA6_TC3                   *((volatile unsigned int*)(0x42C00E0CUL))
+#define bFM3_DMAC_DMACA6_TC4                   *((volatile unsigned int*)(0x42C00E10UL))
+#define bFM3_DMAC_DMACA6_TC5                   *((volatile unsigned int*)(0x42C00E14UL))
+#define bFM3_DMAC_DMACA6_TC6                   *((volatile unsigned int*)(0x42C00E18UL))
+#define bFM3_DMAC_DMACA6_TC7                   *((volatile unsigned int*)(0x42C00E1CUL))
+#define bFM3_DMAC_DMACA6_TC8                   *((volatile unsigned int*)(0x42C00E20UL))
+#define bFM3_DMAC_DMACA6_TC9                   *((volatile unsigned int*)(0x42C00E24UL))
+#define bFM3_DMAC_DMACA6_TC10                  *((volatile unsigned int*)(0x42C00E28UL))
+#define bFM3_DMAC_DMACA6_TC11                  *((volatile unsigned int*)(0x42C00E2CUL))
+#define bFM3_DMAC_DMACA6_TC12                  *((volatile unsigned int*)(0x42C00E30UL))
+#define bFM3_DMAC_DMACA6_TC13                  *((volatile unsigned int*)(0x42C00E34UL))
+#define bFM3_DMAC_DMACA6_TC14                  *((volatile unsigned int*)(0x42C00E38UL))
+#define bFM3_DMAC_DMACA6_TC15                  *((volatile unsigned int*)(0x42C00E3CUL))
+#define bFM3_DMAC_DMACA6_BC0                   *((volatile unsigned int*)(0x42C00E40UL))
+#define bFM3_DMAC_DMACA6_BC1                   *((volatile unsigned int*)(0x42C00E44UL))
+#define bFM3_DMAC_DMACA6_BC2                   *((volatile unsigned int*)(0x42C00E48UL))
+#define bFM3_DMAC_DMACA6_BC3                   *((volatile unsigned int*)(0x42C00E4CUL))
+#define bFM3_DMAC_DMACA6_IS0                   *((volatile unsigned int*)(0x42C00E5CUL))
+#define bFM3_DMAC_DMACA6_IS1                   *((volatile unsigned int*)(0x42C00E60UL))
+#define bFM3_DMAC_DMACA6_IS2                   *((volatile unsigned int*)(0x42C00E64UL))
+#define bFM3_DMAC_DMACA6_IS3                   *((volatile unsigned int*)(0x42C00E68UL))
+#define bFM3_DMAC_DMACA6_IS4                   *((volatile unsigned int*)(0x42C00E6CUL))
+#define bFM3_DMAC_DMACA6_IS5                   *((volatile unsigned int*)(0x42C00E70UL))
+#define bFM3_DMAC_DMACA6_ST                    *((volatile unsigned int*)(0x42C00E74UL))
+#define bFM3_DMAC_DMACA6_PB                    *((volatile unsigned int*)(0x42C00E78UL))
+#define bFM3_DMAC_DMACA6_EB                    *((volatile unsigned int*)(0x42C00E7CUL))
+#define bFM3_DMAC_DMACB6_EM                    *((volatile unsigned int*)(0x42C00E80UL))
+#define bFM3_DMAC_DMACB6_SS0                   *((volatile unsigned int*)(0x42C00EC0UL))
+#define bFM3_DMAC_DMACB6_SS1                   *((volatile unsigned int*)(0x42C00EC4UL))
+#define bFM3_DMAC_DMACB6_SS2                   *((volatile unsigned int*)(0x42C00EC8UL))
+#define bFM3_DMAC_DMACB6_CI                    *((volatile unsigned int*)(0x42C00ECCUL))
+#define bFM3_DMAC_DMACB6_EI                    *((volatile unsigned int*)(0x42C00ED0UL))
+#define bFM3_DMAC_DMACB6_RD                    *((volatile unsigned int*)(0x42C00ED4UL))
+#define bFM3_DMAC_DMACB6_RS                    *((volatile unsigned int*)(0x42C00ED8UL))
+#define bFM3_DMAC_DMACB6_RC                    *((volatile unsigned int*)(0x42C00EDCUL))
+#define bFM3_DMAC_DMACB6_FD                    *((volatile unsigned int*)(0x42C00EE0UL))
+#define bFM3_DMAC_DMACB6_FS                    *((volatile unsigned int*)(0x42C00EE4UL))
+#define bFM3_DMAC_DMACB6_TW0                   *((volatile unsigned int*)(0x42C00EE8UL))
+#define bFM3_DMAC_DMACB6_TW1                   *((volatile unsigned int*)(0x42C00EECUL))
+#define bFM3_DMAC_DMACB6_MS0                   *((volatile unsigned int*)(0x42C00EF0UL))
+#define bFM3_DMAC_DMACB6_MS1                   *((volatile unsigned int*)(0x42C00EF4UL))
+#define bFM3_DMAC_DMACA7_TC0                   *((volatile unsigned int*)(0x42C01000UL))
+#define bFM3_DMAC_DMACA7_TC1                   *((volatile unsigned int*)(0x42C01004UL))
+#define bFM3_DMAC_DMACA7_TC2                   *((volatile unsigned int*)(0x42C01008UL))
+#define bFM3_DMAC_DMACA7_TC3                   *((volatile unsigned int*)(0x42C0100CUL))
+#define bFM3_DMAC_DMACA7_TC4                   *((volatile unsigned int*)(0x42C01010UL))
+#define bFM3_DMAC_DMACA7_TC5                   *((volatile unsigned int*)(0x42C01014UL))
+#define bFM3_DMAC_DMACA7_TC6                   *((volatile unsigned int*)(0x42C01018UL))
+#define bFM3_DMAC_DMACA7_TC7                   *((volatile unsigned int*)(0x42C0101CUL))
+#define bFM3_DMAC_DMACA7_TC8                   *((volatile unsigned int*)(0x42C01020UL))
+#define bFM3_DMAC_DMACA7_TC9                   *((volatile unsigned int*)(0x42C01024UL))
+#define bFM3_DMAC_DMACA7_TC10                  *((volatile unsigned int*)(0x42C01028UL))
+#define bFM3_DMAC_DMACA7_TC11                  *((volatile unsigned int*)(0x42C0102CUL))
+#define bFM3_DMAC_DMACA7_TC12                  *((volatile unsigned int*)(0x42C01030UL))
+#define bFM3_DMAC_DMACA7_TC13                  *((volatile unsigned int*)(0x42C01034UL))
+#define bFM3_DMAC_DMACA7_TC14                  *((volatile unsigned int*)(0x42C01038UL))
+#define bFM3_DMAC_DMACA7_TC15                  *((volatile unsigned int*)(0x42C0103CUL))
+#define bFM3_DMAC_DMACA7_BC0                   *((volatile unsigned int*)(0x42C01040UL))
+#define bFM3_DMAC_DMACA7_BC1                   *((volatile unsigned int*)(0x42C01044UL))
+#define bFM3_DMAC_DMACA7_BC2                   *((volatile unsigned int*)(0x42C01048UL))
+#define bFM3_DMAC_DMACA7_BC3                   *((volatile unsigned int*)(0x42C0104CUL))
+#define bFM3_DMAC_DMACA7_IS0                   *((volatile unsigned int*)(0x42C0105CUL))
+#define bFM3_DMAC_DMACA7_IS1                   *((volatile unsigned int*)(0x42C01060UL))
+#define bFM3_DMAC_DMACA7_IS2                   *((volatile unsigned int*)(0x42C01064UL))
+#define bFM3_DMAC_DMACA7_IS3                   *((volatile unsigned int*)(0x42C01068UL))
+#define bFM3_DMAC_DMACA7_IS4                   *((volatile unsigned int*)(0x42C0106CUL))
+#define bFM3_DMAC_DMACA7_IS5                   *((volatile unsigned int*)(0x42C01070UL))
+#define bFM3_DMAC_DMACA7_ST                    *((volatile unsigned int*)(0x42C01074UL))
+#define bFM3_DMAC_DMACA7_PB                    *((volatile unsigned int*)(0x42C01078UL))
+#define bFM3_DMAC_DMACA7_EB                    *((volatile unsigned int*)(0x42C0107CUL))
+#define bFM3_DMAC_DMACB7_EM                    *((volatile unsigned int*)(0x42C01080UL))
+#define bFM3_DMAC_DMACB7_SS0                   *((volatile unsigned int*)(0x42C010C0UL))
+#define bFM3_DMAC_DMACB7_SS1                   *((volatile unsigned int*)(0x42C010C4UL))
+#define bFM3_DMAC_DMACB7_SS2                   *((volatile unsigned int*)(0x42C010C8UL))
+#define bFM3_DMAC_DMACB7_CI                    *((volatile unsigned int*)(0x42C010CCUL))
+#define bFM3_DMAC_DMACB7_EI                    *((volatile unsigned int*)(0x42C010D0UL))
+#define bFM3_DMAC_DMACB7_RD                    *((volatile unsigned int*)(0x42C010D4UL))
+#define bFM3_DMAC_DMACB7_RS                    *((volatile unsigned int*)(0x42C010D8UL))
+#define bFM3_DMAC_DMACB7_RC                    *((volatile unsigned int*)(0x42C010DCUL))
+#define bFM3_DMAC_DMACB7_FD                    *((volatile unsigned int*)(0x42C010E0UL))
+#define bFM3_DMAC_DMACB7_FS                    *((volatile unsigned int*)(0x42C010E4UL))
+#define bFM3_DMAC_DMACB7_TW0                   *((volatile unsigned int*)(0x42C010E8UL))
+#define bFM3_DMAC_DMACB7_TW1                   *((volatile unsigned int*)(0x42C010ECUL))
+#define bFM3_DMAC_DMACB7_MS0                   *((volatile unsigned int*)(0x42C010F0UL))
+#define bFM3_DMAC_DMACB7_MS1                   *((volatile unsigned int*)(0x42C010F4UL))
+
+/* ETHERNET-MAC0 registers*/
+#define bFM3_ETHERNET_MAC0_MCR_RE              *((volatile unsigned int*)(0x42C80008UL))
+#define bFM3_ETHERNET_MAC0_MCR_TE              *((volatile unsigned int*)(0x42C8000CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DC              *((volatile unsigned int*)(0x42C80010UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL0             *((volatile unsigned int*)(0x42C80014UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL1             *((volatile unsigned int*)(0x42C80018UL))
+#define bFM3_ETHERNET_MAC0_MCR_ACS             *((volatile unsigned int*)(0x42C8001CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LUD             *((volatile unsigned int*)(0x42C80020UL))
+#define bFM3_ETHERNET_MAC0_MCR_DR              *((volatile unsigned int*)(0x42C80024UL))
+#define bFM3_ETHERNET_MAC0_MCR_IPC             *((volatile unsigned int*)(0x42C80028UL))
+#define bFM3_ETHERNET_MAC0_MCR_DM              *((volatile unsigned int*)(0x42C8002CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LM              *((volatile unsigned int*)(0x42C80030UL))
+#define bFM3_ETHERNET_MAC0_MCR_DO              *((volatile unsigned int*)(0x42C80034UL))
+#define bFM3_ETHERNET_MAC0_MCR_FES             *((volatile unsigned int*)(0x42C80038UL))
+#define bFM3_ETHERNET_MAC0_MCR_PS              *((volatile unsigned int*)(0x42C8003CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DCRS            *((volatile unsigned int*)(0x42C80040UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG0            *((volatile unsigned int*)(0x42C80044UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG1            *((volatile unsigned int*)(0x42C80048UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG2            *((volatile unsigned int*)(0x42C8004CUL))
+#define bFM3_ETHERNET_MAC0_MCR_JE              *((volatile unsigned int*)(0x42C80050UL))
+#define bFM3_ETHERNET_MAC0_MCR_BE              *((volatile unsigned int*)(0x42C80054UL))
+#define bFM3_ETHERNET_MAC0_MCR_JD              *((volatile unsigned int*)(0x42C80058UL))
+#define bFM3_ETHERNET_MAC0_MCR_WD              *((volatile unsigned int*)(0x42C8005CUL))
+#define bFM3_ETHERNET_MAC0_MCR_TC              *((volatile unsigned int*)(0x42C80060UL))
+#define bFM3_ETHERNET_MAC0_MCR_CST             *((volatile unsigned int*)(0x42C80064UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PR             *((volatile unsigned int*)(0x42C80080UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HUC            *((volatile unsigned int*)(0x42C80084UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HMC            *((volatile unsigned int*)(0x42C80088UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DAIF           *((volatile unsigned int*)(0x42C8008CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_PM             *((volatile unsigned int*)(0x42C80090UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DB             *((volatile unsigned int*)(0x42C80094UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF0           *((volatile unsigned int*)(0x42C80098UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF1           *((volatile unsigned int*)(0x42C8009CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAIF           *((volatile unsigned int*)(0x42C800A0UL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAF            *((volatile unsigned int*)(0x42C800A4UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HPF            *((volatile unsigned int*)(0x42C800A8UL))
+#define bFM3_ETHERNET_MAC0_MFFR_RA             *((volatile unsigned int*)(0x42C800FCUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH0          *((volatile unsigned int*)(0x42C80100UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH1          *((volatile unsigned int*)(0x42C80104UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH2          *((volatile unsigned int*)(0x42C80108UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH3          *((volatile unsigned int*)(0x42C8010CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH4          *((volatile unsigned int*)(0x42C80110UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH5          *((volatile unsigned int*)(0x42C80114UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH6          *((volatile unsigned int*)(0x42C80118UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH7          *((volatile unsigned int*)(0x42C8011CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH8          *((volatile unsigned int*)(0x42C80120UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH9          *((volatile unsigned int*)(0x42C80124UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH10         *((volatile unsigned int*)(0x42C80128UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH11         *((volatile unsigned int*)(0x42C8012CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH12         *((volatile unsigned int*)(0x42C80130UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH13         *((volatile unsigned int*)(0x42C80134UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH14         *((volatile unsigned int*)(0x42C80138UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH15         *((volatile unsigned int*)(0x42C8013CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH16         *((volatile unsigned int*)(0x42C80140UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH17         *((volatile unsigned int*)(0x42C80144UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH18         *((volatile unsigned int*)(0x42C80148UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH19         *((volatile unsigned int*)(0x42C8014CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH20         *((volatile unsigned int*)(0x42C80150UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH21         *((volatile unsigned int*)(0x42C80154UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH22         *((volatile unsigned int*)(0x42C80158UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH23         *((volatile unsigned int*)(0x42C8015CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH24         *((volatile unsigned int*)(0x42C80160UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH25         *((volatile unsigned int*)(0x42C80164UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH26         *((volatile unsigned int*)(0x42C80168UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH27         *((volatile unsigned int*)(0x42C8016CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH28         *((volatile unsigned int*)(0x42C80170UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH29         *((volatile unsigned int*)(0x42C80174UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH30         *((volatile unsigned int*)(0x42C80178UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH31         *((volatile unsigned int*)(0x42C8017CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL0          *((volatile unsigned int*)(0x42C80180UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL1          *((volatile unsigned int*)(0x42C80184UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL2          *((volatile unsigned int*)(0x42C80188UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL3          *((volatile unsigned int*)(0x42C8018CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL4          *((volatile unsigned int*)(0x42C80190UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL5          *((volatile unsigned int*)(0x42C80194UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL6          *((volatile unsigned int*)(0x42C80198UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL7          *((volatile unsigned int*)(0x42C8019CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL8          *((volatile unsigned int*)(0x42C801A0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL9          *((volatile unsigned int*)(0x42C801A4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL10         *((volatile unsigned int*)(0x42C801A8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL11         *((volatile unsigned int*)(0x42C801ACUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL12         *((volatile unsigned int*)(0x42C801B0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL13         *((volatile unsigned int*)(0x42C801B4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL14         *((volatile unsigned int*)(0x42C801B8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL15         *((volatile unsigned int*)(0x42C801BCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL16         *((volatile unsigned int*)(0x42C801C0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL17         *((volatile unsigned int*)(0x42C801C4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL18         *((volatile unsigned int*)(0x42C801C8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL19         *((volatile unsigned int*)(0x42C801CCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL20         *((volatile unsigned int*)(0x42C801D0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL21         *((volatile unsigned int*)(0x42C801D4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL22         *((volatile unsigned int*)(0x42C801D8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL23         *((volatile unsigned int*)(0x42C801DCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL24         *((volatile unsigned int*)(0x42C801E0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL25         *((volatile unsigned int*)(0x42C801E4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL26         *((volatile unsigned int*)(0x42C801E8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL27         *((volatile unsigned int*)(0x42C801ECUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL28         *((volatile unsigned int*)(0x42C801F0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL29         *((volatile unsigned int*)(0x42C801F4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL30         *((volatile unsigned int*)(0x42C801F8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL31         *((volatile unsigned int*)(0x42C801FCUL))
+#define bFM3_ETHERNET_MAC0_GAR_GB              *((volatile unsigned int*)(0x42C80200UL))
+#define bFM3_ETHERNET_MAC0_GAR_GW              *((volatile unsigned int*)(0x42C80204UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR0             *((volatile unsigned int*)(0x42C80208UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR1             *((volatile unsigned int*)(0x42C8020CUL))
+#define bFM3_ETHERNET_MAC0_GAR_CR2             *((volatile unsigned int*)(0x42C80210UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR3             *((volatile unsigned int*)(0x42C80214UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR0             *((volatile unsigned int*)(0x42C80218UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR1             *((volatile unsigned int*)(0x42C8021CUL))
+#define bFM3_ETHERNET_MAC0_GAR_GR2             *((volatile unsigned int*)(0x42C80220UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR3             *((volatile unsigned int*)(0x42C80224UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR4             *((volatile unsigned int*)(0x42C80228UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA0             *((volatile unsigned int*)(0x42C8022CUL))
+#define bFM3_ETHERNET_MAC0_GAR_PA1             *((volatile unsigned int*)(0x42C80230UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA2             *((volatile unsigned int*)(0x42C80234UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA3             *((volatile unsigned int*)(0x42C80238UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA4             *((volatile unsigned int*)(0x42C8023CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD0             *((volatile unsigned int*)(0x42C80280UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD1             *((volatile unsigned int*)(0x42C80284UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD2             *((volatile unsigned int*)(0x42C80288UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD3             *((volatile unsigned int*)(0x42C8028CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD4             *((volatile unsigned int*)(0x42C80290UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD5             *((volatile unsigned int*)(0x42C80294UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD6             *((volatile unsigned int*)(0x42C80298UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD7             *((volatile unsigned int*)(0x42C8029CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD8             *((volatile unsigned int*)(0x42C802A0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD9             *((volatile unsigned int*)(0x42C802A4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD10            *((volatile unsigned int*)(0x42C802A8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD11            *((volatile unsigned int*)(0x42C802ACUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD12            *((volatile unsigned int*)(0x42C802B0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD13            *((volatile unsigned int*)(0x42C802B4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD14            *((volatile unsigned int*)(0x42C802B8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD15            *((volatile unsigned int*)(0x42C802BCUL))
+#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA         *((volatile unsigned int*)(0x42C80300UL))
+#define bFM3_ETHERNET_MAC0_FCR_TFE             *((volatile unsigned int*)(0x42C80304UL))
+#define bFM3_ETHERNET_MAC0_FCR_RFE             *((volatile unsigned int*)(0x42C80308UL))
+#define bFM3_ETHERNET_MAC0_FCR_UP              *((volatile unsigned int*)(0x42C8030CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT0            *((volatile unsigned int*)(0x42C80310UL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT1            *((volatile unsigned int*)(0x42C80314UL))
+#define bFM3_ETHERNET_MAC0_FCR_DZPQ            *((volatile unsigned int*)(0x42C8031CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT0             *((volatile unsigned int*)(0x42C80340UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT1             *((volatile unsigned int*)(0x42C80344UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT2             *((volatile unsigned int*)(0x42C80348UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT3             *((volatile unsigned int*)(0x42C8034CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT4             *((volatile unsigned int*)(0x42C80350UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT5             *((volatile unsigned int*)(0x42C80354UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT6             *((volatile unsigned int*)(0x42C80358UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT7             *((volatile unsigned int*)(0x42C8035CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT8             *((volatile unsigned int*)(0x42C80360UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT9             *((volatile unsigned int*)(0x42C80364UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT10            *((volatile unsigned int*)(0x42C80368UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT11            *((volatile unsigned int*)(0x42C8036CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT12            *((volatile unsigned int*)(0x42C80370UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT13            *((volatile unsigned int*)(0x42C80374UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT14            *((volatile unsigned int*)(0x42C80378UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT15            *((volatile unsigned int*)(0x42C8037CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL0             *((volatile unsigned int*)(0x42C80380UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL1             *((volatile unsigned int*)(0x42C80384UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL2             *((volatile unsigned int*)(0x42C80388UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL3             *((volatile unsigned int*)(0x42C8038CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL4             *((volatile unsigned int*)(0x42C80390UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL5             *((volatile unsigned int*)(0x42C80394UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL6             *((volatile unsigned int*)(0x42C80398UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL7             *((volatile unsigned int*)(0x42C8039CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL8             *((volatile unsigned int*)(0x42C803A0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL9             *((volatile unsigned int*)(0x42C803A4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL10            *((volatile unsigned int*)(0x42C803A8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL11            *((volatile unsigned int*)(0x42C803ACUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL12            *((volatile unsigned int*)(0x42C803B0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL13            *((volatile unsigned int*)(0x42C803B4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL14            *((volatile unsigned int*)(0x42C803B8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL15            *((volatile unsigned int*)(0x42C803BCUL))
+#define bFM3_ETHERNET_MAC0_VTR_ETV             *((volatile unsigned int*)(0x42C803C0UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42C80500UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42C80504UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42C80508UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42C8050CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42C80510UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42C80514UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42C80518UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42C8051CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42C80520UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42C80524UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42C80528UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42C8052CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42C80530UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42C80534UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42C80538UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42C8053CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42C80540UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42C80544UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42C80548UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42C8054CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42C80550UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42C80554UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42C80558UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42C8055CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42C80560UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42C80564UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42C80568UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42C8056CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42C80570UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42C80574UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42C80578UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42C8057CUL))
+#define bFM3_ETHERNET_MAC0_PMTR_PD             *((volatile unsigned int*)(0x42C80580UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPE            *((volatile unsigned int*)(0x42C80584UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WFE            *((volatile unsigned int*)(0x42C80588UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPR            *((volatile unsigned int*)(0x42C80594UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WPR            *((volatile unsigned int*)(0x42C80598UL))
+#define bFM3_ETHERNET_MAC0_PMTR_GU             *((volatile unsigned int*)(0x42C805A4UL))
+#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42C805FCUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42C80600UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42C80604UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42C80608UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42C8060CUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST       *((volatile unsigned int*)(0x42C80620UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST       *((volatile unsigned int*)(0x42C80624UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN        *((volatile unsigned int*)(0x42C80640UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLS          *((volatile unsigned int*)(0x42C80644UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN        *((volatile unsigned int*)(0x42C80648UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA       *((volatile unsigned int*)(0x42C8064CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT0         *((volatile unsigned int*)(0x42C80680UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT1         *((volatile unsigned int*)(0x42C80684UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT2         *((volatile unsigned int*)(0x42C80688UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT3         *((volatile unsigned int*)(0x42C8068CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT4         *((volatile unsigned int*)(0x42C80690UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT5         *((volatile unsigned int*)(0x42C80694UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT6         *((volatile unsigned int*)(0x42C80698UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT7         *((volatile unsigned int*)(0x42C8069CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT8         *((volatile unsigned int*)(0x42C806A0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT9         *((volatile unsigned int*)(0x42C806A4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT10        *((volatile unsigned int*)(0x42C806A8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT11        *((volatile unsigned int*)(0x42C806ACUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT12        *((volatile unsigned int*)(0x42C806B0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT13        *((volatile unsigned int*)(0x42C806B4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT14        *((volatile unsigned int*)(0x42C806B8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT15        *((volatile unsigned int*)(0x42C806BCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT0         *((volatile unsigned int*)(0x42C806C0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT1         *((volatile unsigned int*)(0x42C806C4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT2         *((volatile unsigned int*)(0x42C806C8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT3         *((volatile unsigned int*)(0x42C806CCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT4         *((volatile unsigned int*)(0x42C806D0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT5         *((volatile unsigned int*)(0x42C806D4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT6         *((volatile unsigned int*)(0x42C806D8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT7         *((volatile unsigned int*)(0x42C806DCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT8         *((volatile unsigned int*)(0x42C806E0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT9         *((volatile unsigned int*)(0x42C806E4UL))
+#define bFM3_ETHERNET_MAC0_ISR_RGIS            *((volatile unsigned int*)(0x42C80700UL))
+#define bFM3_ETHERNET_MAC0_ISR_PIS             *((volatile unsigned int*)(0x42C8070CUL))
+#define bFM3_ETHERNET_MAC0_ISR_MIS             *((volatile unsigned int*)(0x42C80710UL))
+#define bFM3_ETHERNET_MAC0_ISR_RIS             *((volatile unsigned int*)(0x42C80714UL))
+#define bFM3_ETHERNET_MAC0_ISR_TIS             *((volatile unsigned int*)(0x42C80718UL))
+#define bFM3_ETHERNET_MAC0_ISR_COIS            *((volatile unsigned int*)(0x42C8071CUL))
+#define bFM3_ETHERNET_MAC0_ISR_TSIS            *((volatile unsigned int*)(0x42C80724UL))
+#define bFM3_ETHERNET_MAC0_ISR_LPIIS           *((volatile unsigned int*)(0x42C80728UL))
+#define bFM3_ETHERNET_MAC0_IMR_RGIM            *((volatile unsigned int*)(0x42C80780UL))
+#define bFM3_ETHERNET_MAC0_IMR_PIM             *((volatile unsigned int*)(0x42C8078CUL))
+#define bFM3_ETHERNET_MAC0_IMR_TSIM            *((volatile unsigned int*)(0x42C80794UL))
+#define bFM3_ETHERNET_MAC0_IMR_LPIIM           *((volatile unsigned int*)(0x42C80798UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A32           *((volatile unsigned int*)(0x42C80800UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A33           *((volatile unsigned int*)(0x42C80804UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A34           *((volatile unsigned int*)(0x42C80808UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A35           *((volatile unsigned int*)(0x42C8080CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A36           *((volatile unsigned int*)(0x42C80810UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A37           *((volatile unsigned int*)(0x42C80814UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A38           *((volatile unsigned int*)(0x42C80818UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A39           *((volatile unsigned int*)(0x42C8081CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A40           *((volatile unsigned int*)(0x42C80820UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A41           *((volatile unsigned int*)(0x42C80824UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A42           *((volatile unsigned int*)(0x42C80828UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A43           *((volatile unsigned int*)(0x42C8082CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A44           *((volatile unsigned int*)(0x42C80830UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A45           *((volatile unsigned int*)(0x42C80834UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A46           *((volatile unsigned int*)(0x42C80838UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A47           *((volatile unsigned int*)(0x42C8083CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_MO            *((volatile unsigned int*)(0x42C8087CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A0            *((volatile unsigned int*)(0x42C80880UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A1            *((volatile unsigned int*)(0x42C80884UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A2            *((volatile unsigned int*)(0x42C80888UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A3            *((volatile unsigned int*)(0x42C8088CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A4            *((volatile unsigned int*)(0x42C80890UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A5            *((volatile unsigned int*)(0x42C80894UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A6            *((volatile unsigned int*)(0x42C80898UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A7            *((volatile unsigned int*)(0x42C8089CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A8            *((volatile unsigned int*)(0x42C808A0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A9            *((volatile unsigned int*)(0x42C808A4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A10           *((volatile unsigned int*)(0x42C808A8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A11           *((volatile unsigned int*)(0x42C808ACUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A12           *((volatile unsigned int*)(0x42C808B0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A13           *((volatile unsigned int*)(0x42C808B4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A14           *((volatile unsigned int*)(0x42C808B8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A15           *((volatile unsigned int*)(0x42C808BCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A16           *((volatile unsigned int*)(0x42C808C0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A17           *((volatile unsigned int*)(0x42C808C4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A18           *((volatile unsigned int*)(0x42C808C8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A19           *((volatile unsigned int*)(0x42C808CCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A20           *((volatile unsigned int*)(0x42C808D0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A21           *((volatile unsigned int*)(0x42C808D4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A22           *((volatile unsigned int*)(0x42C808D8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A23           *((volatile unsigned int*)(0x42C808DCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A24           *((volatile unsigned int*)(0x42C808E0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A25           *((volatile unsigned int*)(0x42C808E4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A26           *((volatile unsigned int*)(0x42C808E8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A27           *((volatile unsigned int*)(0x42C808ECUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A28           *((volatile unsigned int*)(0x42C808F0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A29           *((volatile unsigned int*)(0x42C808F4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A30           *((volatile unsigned int*)(0x42C808F8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A31           *((volatile unsigned int*)(0x42C808FCUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A32           *((volatile unsigned int*)(0x42C80900UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A33           *((volatile unsigned int*)(0x42C80904UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A34           *((volatile unsigned int*)(0x42C80908UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A35           *((volatile unsigned int*)(0x42C8090CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A36           *((volatile unsigned int*)(0x42C80910UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A37           *((volatile unsigned int*)(0x42C80914UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A38           *((volatile unsigned int*)(0x42C80918UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A39           *((volatile unsigned int*)(0x42C8091CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A40           *((volatile unsigned int*)(0x42C80920UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A41           *((volatile unsigned int*)(0x42C80924UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A42           *((volatile unsigned int*)(0x42C80928UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A43           *((volatile unsigned int*)(0x42C8092CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A44           *((volatile unsigned int*)(0x42C80930UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A45           *((volatile unsigned int*)(0x42C80934UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A46           *((volatile unsigned int*)(0x42C80938UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A47           *((volatile unsigned int*)(0x42C8093CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC0          *((volatile unsigned int*)(0x42C80960UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC1          *((volatile unsigned int*)(0x42C80964UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC2          *((volatile unsigned int*)(0x42C80968UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC3          *((volatile unsigned int*)(0x42C8096CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC4          *((volatile unsigned int*)(0x42C80970UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC5          *((volatile unsigned int*)(0x42C80974UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_SA            *((volatile unsigned int*)(0x42C80978UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_AE            *((volatile unsigned int*)(0x42C8097CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A0            *((volatile unsigned int*)(0x42C80980UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A1            *((volatile unsigned int*)(0x42C80984UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A2            *((volatile unsigned int*)(0x42C80988UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A3            *((volatile unsigned int*)(0x42C8098CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A4            *((volatile unsigned int*)(0x42C80990UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A5            *((volatile unsigned int*)(0x42C80994UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A6            *((volatile unsigned int*)(0x42C80998UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A7            *((volatile unsigned int*)(0x42C8099CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A8            *((volatile unsigned int*)(0x42C809A0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A9            *((volatile unsigned int*)(0x42C809A4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A10           *((volatile unsigned int*)(0x42C809A8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A11           *((volatile unsigned int*)(0x42C809ACUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A12           *((volatile unsigned int*)(0x42C809B0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A13           *((volatile unsigned int*)(0x42C809B4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A14           *((volatile unsigned int*)(0x42C809B8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A15           *((volatile unsigned int*)(0x42C809BCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A16           *((volatile unsigned int*)(0x42C809C0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A17           *((volatile unsigned int*)(0x42C809C4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A18           *((volatile unsigned int*)(0x42C809C8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A19           *((volatile unsigned int*)(0x42C809CCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A20           *((volatile unsigned int*)(0x42C809D0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A21           *((volatile unsigned int*)(0x42C809D4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A22           *((volatile unsigned int*)(0x42C809D8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A23           *((volatile unsigned int*)(0x42C809DCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A24           *((volatile unsigned int*)(0x42C809E0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A25           *((volatile unsigned int*)(0x42C809E4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A26           *((volatile unsigned int*)(0x42C809E8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A27           *((volatile unsigned int*)(0x42C809ECUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A28           *((volatile unsigned int*)(0x42C809F0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A29           *((volatile unsigned int*)(0x42C809F4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A30           *((volatile unsigned int*)(0x42C809F8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A31           *((volatile unsigned int*)(0x42C809FCUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A32           *((volatile unsigned int*)(0x42C80A00UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A33           *((volatile unsigned int*)(0x42C80A04UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A34           *((volatile unsigned int*)(0x42C80A08UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A35           *((volatile unsigned int*)(0x42C80A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A36           *((volatile unsigned int*)(0x42C80A10UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A37           *((volatile unsigned int*)(0x42C80A14UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A38           *((volatile unsigned int*)(0x42C80A18UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A39           *((volatile unsigned int*)(0x42C80A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A40           *((volatile unsigned int*)(0x42C80A20UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A41           *((volatile unsigned int*)(0x42C80A24UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A42           *((volatile unsigned int*)(0x42C80A28UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A43           *((volatile unsigned int*)(0x42C80A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A44           *((volatile unsigned int*)(0x42C80A30UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A45           *((volatile unsigned int*)(0x42C80A34UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A46           *((volatile unsigned int*)(0x42C80A38UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A47           *((volatile unsigned int*)(0x42C80A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC0          *((volatile unsigned int*)(0x42C80A60UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC1          *((volatile unsigned int*)(0x42C80A64UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC2          *((volatile unsigned int*)(0x42C80A68UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC3          *((volatile unsigned int*)(0x42C80A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC4          *((volatile unsigned int*)(0x42C80A70UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC5          *((volatile unsigned int*)(0x42C80A74UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_SA            *((volatile unsigned int*)(0x42C80A78UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_AE            *((volatile unsigned int*)(0x42C80A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A0            *((volatile unsigned int*)(0x42C80A80UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A1            *((volatile unsigned int*)(0x42C80A84UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A2            *((volatile unsigned int*)(0x42C80A88UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A3            *((volatile unsigned int*)(0x42C80A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A4            *((volatile unsigned int*)(0x42C80A90UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A5            *((volatile unsigned int*)(0x42C80A94UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A6            *((volatile unsigned int*)(0x42C80A98UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A7            *((volatile unsigned int*)(0x42C80A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A8            *((volatile unsigned int*)(0x42C80AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A9            *((volatile unsigned int*)(0x42C80AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A10           *((volatile unsigned int*)(0x42C80AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A11           *((volatile unsigned int*)(0x42C80AACUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A12           *((volatile unsigned int*)(0x42C80AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A13           *((volatile unsigned int*)(0x42C80AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A14           *((volatile unsigned int*)(0x42C80AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A15           *((volatile unsigned int*)(0x42C80ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A16           *((volatile unsigned int*)(0x42C80AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A17           *((volatile unsigned int*)(0x42C80AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A18           *((volatile unsigned int*)(0x42C80AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A19           *((volatile unsigned int*)(0x42C80ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A20           *((volatile unsigned int*)(0x42C80AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A21           *((volatile unsigned int*)(0x42C80AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A22           *((volatile unsigned int*)(0x42C80AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A23           *((volatile unsigned int*)(0x42C80ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A24           *((volatile unsigned int*)(0x42C80AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A25           *((volatile unsigned int*)(0x42C80AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A26           *((volatile unsigned int*)(0x42C80AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A27           *((volatile unsigned int*)(0x42C80AECUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A28           *((volatile unsigned int*)(0x42C80AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A29           *((volatile unsigned int*)(0x42C80AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A30           *((volatile unsigned int*)(0x42C80AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A31           *((volatile unsigned int*)(0x42C80AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A32           *((volatile unsigned int*)(0x42C80B00UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A33           *((volatile unsigned int*)(0x42C80B04UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A34           *((volatile unsigned int*)(0x42C80B08UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A35           *((volatile unsigned int*)(0x42C80B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A36           *((volatile unsigned int*)(0x42C80B10UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A37           *((volatile unsigned int*)(0x42C80B14UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A38           *((volatile unsigned int*)(0x42C80B18UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A39           *((volatile unsigned int*)(0x42C80B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A40           *((volatile unsigned int*)(0x42C80B20UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A41           *((volatile unsigned int*)(0x42C80B24UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A42           *((volatile unsigned int*)(0x42C80B28UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A43           *((volatile unsigned int*)(0x42C80B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A44           *((volatile unsigned int*)(0x42C80B30UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A45           *((volatile unsigned int*)(0x42C80B34UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A46           *((volatile unsigned int*)(0x42C80B38UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A47           *((volatile unsigned int*)(0x42C80B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC0          *((volatile unsigned int*)(0x42C80B60UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC1          *((volatile unsigned int*)(0x42C80B64UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC2          *((volatile unsigned int*)(0x42C80B68UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC3          *((volatile unsigned int*)(0x42C80B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC4          *((volatile unsigned int*)(0x42C80B70UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC5          *((volatile unsigned int*)(0x42C80B74UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_SA            *((volatile unsigned int*)(0x42C80B78UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_AE            *((volatile unsigned int*)(0x42C80B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A0            *((volatile unsigned int*)(0x42C80B80UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A1            *((volatile unsigned int*)(0x42C80B84UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A2            *((volatile unsigned int*)(0x42C80B88UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A3            *((volatile unsigned int*)(0x42C80B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A4            *((volatile unsigned int*)(0x42C80B90UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A5            *((volatile unsigned int*)(0x42C80B94UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A6            *((volatile unsigned int*)(0x42C80B98UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A7            *((volatile unsigned int*)(0x42C80B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A8            *((volatile unsigned int*)(0x42C80BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A9            *((volatile unsigned int*)(0x42C80BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A10           *((volatile unsigned int*)(0x42C80BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A11           *((volatile unsigned int*)(0x42C80BACUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A12           *((volatile unsigned int*)(0x42C80BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A13           *((volatile unsigned int*)(0x42C80BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A14           *((volatile unsigned int*)(0x42C80BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A15           *((volatile unsigned int*)(0x42C80BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A16           *((volatile unsigned int*)(0x42C80BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A17           *((volatile unsigned int*)(0x42C80BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A18           *((volatile unsigned int*)(0x42C80BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A19           *((volatile unsigned int*)(0x42C80BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A20           *((volatile unsigned int*)(0x42C80BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A21           *((volatile unsigned int*)(0x42C80BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A22           *((volatile unsigned int*)(0x42C80BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A23           *((volatile unsigned int*)(0x42C80BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A24           *((volatile unsigned int*)(0x42C80BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A25           *((volatile unsigned int*)(0x42C80BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A26           *((volatile unsigned int*)(0x42C80BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A27           *((volatile unsigned int*)(0x42C80BECUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A28           *((volatile unsigned int*)(0x42C80BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A29           *((volatile unsigned int*)(0x42C80BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A30           *((volatile unsigned int*)(0x42C80BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A31           *((volatile unsigned int*)(0x42C80BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A32           *((volatile unsigned int*)(0x42C80C00UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A33           *((volatile unsigned int*)(0x42C80C04UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A34           *((volatile unsigned int*)(0x42C80C08UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A35           *((volatile unsigned int*)(0x42C80C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A36           *((volatile unsigned int*)(0x42C80C10UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A37           *((volatile unsigned int*)(0x42C80C14UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A38           *((volatile unsigned int*)(0x42C80C18UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A39           *((volatile unsigned int*)(0x42C80C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A40           *((volatile unsigned int*)(0x42C80C20UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A41           *((volatile unsigned int*)(0x42C80C24UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A42           *((volatile unsigned int*)(0x42C80C28UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A43           *((volatile unsigned int*)(0x42C80C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A44           *((volatile unsigned int*)(0x42C80C30UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A45           *((volatile unsigned int*)(0x42C80C34UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A46           *((volatile unsigned int*)(0x42C80C38UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A47           *((volatile unsigned int*)(0x42C80C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC0          *((volatile unsigned int*)(0x42C80C60UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC1          *((volatile unsigned int*)(0x42C80C64UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC2          *((volatile unsigned int*)(0x42C80C68UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC3          *((volatile unsigned int*)(0x42C80C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC4          *((volatile unsigned int*)(0x42C80C70UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC5          *((volatile unsigned int*)(0x42C80C74UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_SA            *((volatile unsigned int*)(0x42C80C78UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_AE            *((volatile unsigned int*)(0x42C80C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A0            *((volatile unsigned int*)(0x42C80C80UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A1            *((volatile unsigned int*)(0x42C80C84UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A2            *((volatile unsigned int*)(0x42C80C88UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A3            *((volatile unsigned int*)(0x42C80C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A4            *((volatile unsigned int*)(0x42C80C90UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A5            *((volatile unsigned int*)(0x42C80C94UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A6            *((volatile unsigned int*)(0x42C80C98UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A7            *((volatile unsigned int*)(0x42C80C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A8            *((volatile unsigned int*)(0x42C80CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A9            *((volatile unsigned int*)(0x42C80CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A10           *((volatile unsigned int*)(0x42C80CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A11           *((volatile unsigned int*)(0x42C80CACUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A12           *((volatile unsigned int*)(0x42C80CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A13           *((volatile unsigned int*)(0x42C80CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A14           *((volatile unsigned int*)(0x42C80CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A15           *((volatile unsigned int*)(0x42C80CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A16           *((volatile unsigned int*)(0x42C80CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A17           *((volatile unsigned int*)(0x42C80CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A18           *((volatile unsigned int*)(0x42C80CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A19           *((volatile unsigned int*)(0x42C80CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A20           *((volatile unsigned int*)(0x42C80CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A21           *((volatile unsigned int*)(0x42C80CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A22           *((volatile unsigned int*)(0x42C80CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A23           *((volatile unsigned int*)(0x42C80CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A24           *((volatile unsigned int*)(0x42C80CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A25           *((volatile unsigned int*)(0x42C80CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A26           *((volatile unsigned int*)(0x42C80CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A27           *((volatile unsigned int*)(0x42C80CECUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A28           *((volatile unsigned int*)(0x42C80CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A29           *((volatile unsigned int*)(0x42C80CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A30           *((volatile unsigned int*)(0x42C80CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A31           *((volatile unsigned int*)(0x42C80CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A32           *((volatile unsigned int*)(0x42C80D00UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A33           *((volatile unsigned int*)(0x42C80D04UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A34           *((volatile unsigned int*)(0x42C80D08UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A35           *((volatile unsigned int*)(0x42C80D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A36           *((volatile unsigned int*)(0x42C80D10UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A37           *((volatile unsigned int*)(0x42C80D14UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A38           *((volatile unsigned int*)(0x42C80D18UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A39           *((volatile unsigned int*)(0x42C80D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A40           *((volatile unsigned int*)(0x42C80D20UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A41           *((volatile unsigned int*)(0x42C80D24UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A42           *((volatile unsigned int*)(0x42C80D28UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A43           *((volatile unsigned int*)(0x42C80D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A44           *((volatile unsigned int*)(0x42C80D30UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A45           *((volatile unsigned int*)(0x42C80D34UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A46           *((volatile unsigned int*)(0x42C80D38UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A47           *((volatile unsigned int*)(0x42C80D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC0          *((volatile unsigned int*)(0x42C80D60UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC1          *((volatile unsigned int*)(0x42C80D64UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC2          *((volatile unsigned int*)(0x42C80D68UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC3          *((volatile unsigned int*)(0x42C80D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC4          *((volatile unsigned int*)(0x42C80D70UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC5          *((volatile unsigned int*)(0x42C80D74UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_SA            *((volatile unsigned int*)(0x42C80D78UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_AE            *((volatile unsigned int*)(0x42C80D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A0            *((volatile unsigned int*)(0x42C80D80UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A1            *((volatile unsigned int*)(0x42C80D84UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A2            *((volatile unsigned int*)(0x42C80D88UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A3            *((volatile unsigned int*)(0x42C80D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A4            *((volatile unsigned int*)(0x42C80D90UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A5            *((volatile unsigned int*)(0x42C80D94UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A6            *((volatile unsigned int*)(0x42C80D98UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A7            *((volatile unsigned int*)(0x42C80D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A8            *((volatile unsigned int*)(0x42C80DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A9            *((volatile unsigned int*)(0x42C80DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A10           *((volatile unsigned int*)(0x42C80DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A11           *((volatile unsigned int*)(0x42C80DACUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A12           *((volatile unsigned int*)(0x42C80DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A13           *((volatile unsigned int*)(0x42C80DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A14           *((volatile unsigned int*)(0x42C80DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A15           *((volatile unsigned int*)(0x42C80DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A16           *((volatile unsigned int*)(0x42C80DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A17           *((volatile unsigned int*)(0x42C80DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A18           *((volatile unsigned int*)(0x42C80DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A19           *((volatile unsigned int*)(0x42C80DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A20           *((volatile unsigned int*)(0x42C80DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A21           *((volatile unsigned int*)(0x42C80DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A22           *((volatile unsigned int*)(0x42C80DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A23           *((volatile unsigned int*)(0x42C80DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A24           *((volatile unsigned int*)(0x42C80DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A25           *((volatile unsigned int*)(0x42C80DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A26           *((volatile unsigned int*)(0x42C80DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A27           *((volatile unsigned int*)(0x42C80DECUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A28           *((volatile unsigned int*)(0x42C80DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A29           *((volatile unsigned int*)(0x42C80DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A30           *((volatile unsigned int*)(0x42C80DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A31           *((volatile unsigned int*)(0x42C80DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A32           *((volatile unsigned int*)(0x42C80E00UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A33           *((volatile unsigned int*)(0x42C80E04UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A34           *((volatile unsigned int*)(0x42C80E08UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A35           *((volatile unsigned int*)(0x42C80E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A36           *((volatile unsigned int*)(0x42C80E10UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A37           *((volatile unsigned int*)(0x42C80E14UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A38           *((volatile unsigned int*)(0x42C80E18UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A39           *((volatile unsigned int*)(0x42C80E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A40           *((volatile unsigned int*)(0x42C80E20UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A41           *((volatile unsigned int*)(0x42C80E24UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A42           *((volatile unsigned int*)(0x42C80E28UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A43           *((volatile unsigned int*)(0x42C80E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A44           *((volatile unsigned int*)(0x42C80E30UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A45           *((volatile unsigned int*)(0x42C80E34UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A46           *((volatile unsigned int*)(0x42C80E38UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A47           *((volatile unsigned int*)(0x42C80E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC0          *((volatile unsigned int*)(0x42C80E60UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC1          *((volatile unsigned int*)(0x42C80E64UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC2          *((volatile unsigned int*)(0x42C80E68UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC3          *((volatile unsigned int*)(0x42C80E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC4          *((volatile unsigned int*)(0x42C80E70UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC5          *((volatile unsigned int*)(0x42C80E74UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_SA            *((volatile unsigned int*)(0x42C80E78UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_AE            *((volatile unsigned int*)(0x42C80E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A0            *((volatile unsigned int*)(0x42C80E80UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A1            *((volatile unsigned int*)(0x42C80E84UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A2            *((volatile unsigned int*)(0x42C80E88UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A3            *((volatile unsigned int*)(0x42C80E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A4            *((volatile unsigned int*)(0x42C80E90UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A5            *((volatile unsigned int*)(0x42C80E94UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A6            *((volatile unsigned int*)(0x42C80E98UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A7            *((volatile unsigned int*)(0x42C80E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A8            *((volatile unsigned int*)(0x42C80EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A9            *((volatile unsigned int*)(0x42C80EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A10           *((volatile unsigned int*)(0x42C80EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A11           *((volatile unsigned int*)(0x42C80EACUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A12           *((volatile unsigned int*)(0x42C80EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A13           *((volatile unsigned int*)(0x42C80EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A14           *((volatile unsigned int*)(0x42C80EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A15           *((volatile unsigned int*)(0x42C80EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A16           *((volatile unsigned int*)(0x42C80EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A17           *((volatile unsigned int*)(0x42C80EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A18           *((volatile unsigned int*)(0x42C80EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A19           *((volatile unsigned int*)(0x42C80ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A20           *((volatile unsigned int*)(0x42C80ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A21           *((volatile unsigned int*)(0x42C80ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A22           *((volatile unsigned int*)(0x42C80ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A23           *((volatile unsigned int*)(0x42C80EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A24           *((volatile unsigned int*)(0x42C80EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A25           *((volatile unsigned int*)(0x42C80EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A26           *((volatile unsigned int*)(0x42C80EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A27           *((volatile unsigned int*)(0x42C80EECUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A28           *((volatile unsigned int*)(0x42C80EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A29           *((volatile unsigned int*)(0x42C80EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A30           *((volatile unsigned int*)(0x42C80EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A31           *((volatile unsigned int*)(0x42C80EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A32           *((volatile unsigned int*)(0x42C80F00UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A33           *((volatile unsigned int*)(0x42C80F04UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A34           *((volatile unsigned int*)(0x42C80F08UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A35           *((volatile unsigned int*)(0x42C80F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A36           *((volatile unsigned int*)(0x42C80F10UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A37           *((volatile unsigned int*)(0x42C80F14UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A38           *((volatile unsigned int*)(0x42C80F18UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A39           *((volatile unsigned int*)(0x42C80F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A40           *((volatile unsigned int*)(0x42C80F20UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A41           *((volatile unsigned int*)(0x42C80F24UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A42           *((volatile unsigned int*)(0x42C80F28UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A43           *((volatile unsigned int*)(0x42C80F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A44           *((volatile unsigned int*)(0x42C80F30UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A45           *((volatile unsigned int*)(0x42C80F34UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A46           *((volatile unsigned int*)(0x42C80F38UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A47           *((volatile unsigned int*)(0x42C80F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC0          *((volatile unsigned int*)(0x42C80F60UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC1          *((volatile unsigned int*)(0x42C80F64UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC2          *((volatile unsigned int*)(0x42C80F68UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC3          *((volatile unsigned int*)(0x42C80F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC4          *((volatile unsigned int*)(0x42C80F70UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC5          *((volatile unsigned int*)(0x42C80F74UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_SA            *((volatile unsigned int*)(0x42C80F78UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_AE            *((volatile unsigned int*)(0x42C80F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A0            *((volatile unsigned int*)(0x42C80F80UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A1            *((volatile unsigned int*)(0x42C80F84UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A2            *((volatile unsigned int*)(0x42C80F88UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A3            *((volatile unsigned int*)(0x42C80F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A4            *((volatile unsigned int*)(0x42C80F90UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A5            *((volatile unsigned int*)(0x42C80F94UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A6            *((volatile unsigned int*)(0x42C80F98UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A7            *((volatile unsigned int*)(0x42C80F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A8            *((volatile unsigned int*)(0x42C80FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A9            *((volatile unsigned int*)(0x42C80FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A10           *((volatile unsigned int*)(0x42C80FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A11           *((volatile unsigned int*)(0x42C80FACUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A12           *((volatile unsigned int*)(0x42C80FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A13           *((volatile unsigned int*)(0x42C80FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A14           *((volatile unsigned int*)(0x42C80FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A15           *((volatile unsigned int*)(0x42C80FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A16           *((volatile unsigned int*)(0x42C80FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A17           *((volatile unsigned int*)(0x42C80FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A18           *((volatile unsigned int*)(0x42C80FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A19           *((volatile unsigned int*)(0x42C80FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A20           *((volatile unsigned int*)(0x42C80FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A21           *((volatile unsigned int*)(0x42C80FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A22           *((volatile unsigned int*)(0x42C80FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A23           *((volatile unsigned int*)(0x42C80FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A24           *((volatile unsigned int*)(0x42C80FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A25           *((volatile unsigned int*)(0x42C80FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A26           *((volatile unsigned int*)(0x42C80FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A27           *((volatile unsigned int*)(0x42C80FECUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A28           *((volatile unsigned int*)(0x42C80FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A29           *((volatile unsigned int*)(0x42C80FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A30           *((volatile unsigned int*)(0x42C80FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A31           *((volatile unsigned int*)(0x42C80FFCUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A32           *((volatile unsigned int*)(0x42C81000UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A33           *((volatile unsigned int*)(0x42C81004UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A34           *((volatile unsigned int*)(0x42C81008UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A35           *((volatile unsigned int*)(0x42C8100CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A36           *((volatile unsigned int*)(0x42C81010UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A37           *((volatile unsigned int*)(0x42C81014UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A38           *((volatile unsigned int*)(0x42C81018UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A39           *((volatile unsigned int*)(0x42C8101CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A40           *((volatile unsigned int*)(0x42C81020UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A41           *((volatile unsigned int*)(0x42C81024UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A42           *((volatile unsigned int*)(0x42C81028UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A43           *((volatile unsigned int*)(0x42C8102CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A44           *((volatile unsigned int*)(0x42C81030UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A45           *((volatile unsigned int*)(0x42C81034UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A46           *((volatile unsigned int*)(0x42C81038UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A47           *((volatile unsigned int*)(0x42C8103CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC0          *((volatile unsigned int*)(0x42C81060UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC1          *((volatile unsigned int*)(0x42C81064UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC2          *((volatile unsigned int*)(0x42C81068UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC3          *((volatile unsigned int*)(0x42C8106CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC4          *((volatile unsigned int*)(0x42C81070UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC5          *((volatile unsigned int*)(0x42C81074UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_SA            *((volatile unsigned int*)(0x42C81078UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_AE            *((volatile unsigned int*)(0x42C8107CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A0            *((volatile unsigned int*)(0x42C81080UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A1            *((volatile unsigned int*)(0x42C81084UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A2            *((volatile unsigned int*)(0x42C81088UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A3            *((volatile unsigned int*)(0x42C8108CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A4            *((volatile unsigned int*)(0x42C81090UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A5            *((volatile unsigned int*)(0x42C81094UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A6            *((volatile unsigned int*)(0x42C81098UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A7            *((volatile unsigned int*)(0x42C8109CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A8            *((volatile unsigned int*)(0x42C810A0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A9            *((volatile unsigned int*)(0x42C810A4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A10           *((volatile unsigned int*)(0x42C810A8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A11           *((volatile unsigned int*)(0x42C810ACUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A12           *((volatile unsigned int*)(0x42C810B0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A13           *((volatile unsigned int*)(0x42C810B4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A14           *((volatile unsigned int*)(0x42C810B8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A15           *((volatile unsigned int*)(0x42C810BCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A16           *((volatile unsigned int*)(0x42C810C0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A17           *((volatile unsigned int*)(0x42C810C4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A18           *((volatile unsigned int*)(0x42C810C8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A19           *((volatile unsigned int*)(0x42C810CCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A20           *((volatile unsigned int*)(0x42C810D0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A21           *((volatile unsigned int*)(0x42C810D4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A22           *((volatile unsigned int*)(0x42C810D8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A23           *((volatile unsigned int*)(0x42C810DCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A24           *((volatile unsigned int*)(0x42C810E0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A25           *((volatile unsigned int*)(0x42C810E4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A26           *((volatile unsigned int*)(0x42C810E8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A27           *((volatile unsigned int*)(0x42C810ECUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A28           *((volatile unsigned int*)(0x42C810F0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A29           *((volatile unsigned int*)(0x42C810F4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A30           *((volatile unsigned int*)(0x42C810F8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A31           *((volatile unsigned int*)(0x42C810FCUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A32           *((volatile unsigned int*)(0x42C81100UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A33           *((volatile unsigned int*)(0x42C81104UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A34           *((volatile unsigned int*)(0x42C81108UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A35           *((volatile unsigned int*)(0x42C8110CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A36           *((volatile unsigned int*)(0x42C81110UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A37           *((volatile unsigned int*)(0x42C81114UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A38           *((volatile unsigned int*)(0x42C81118UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A39           *((volatile unsigned int*)(0x42C8111CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A40           *((volatile unsigned int*)(0x42C81120UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A41           *((volatile unsigned int*)(0x42C81124UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A42           *((volatile unsigned int*)(0x42C81128UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A43           *((volatile unsigned int*)(0x42C8112CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A44           *((volatile unsigned int*)(0x42C81130UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A45           *((volatile unsigned int*)(0x42C81134UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A46           *((volatile unsigned int*)(0x42C81138UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A47           *((volatile unsigned int*)(0x42C8113CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC0          *((volatile unsigned int*)(0x42C81160UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC1          *((volatile unsigned int*)(0x42C81164UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC2          *((volatile unsigned int*)(0x42C81168UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC3          *((volatile unsigned int*)(0x42C8116CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC4          *((volatile unsigned int*)(0x42C81170UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC5          *((volatile unsigned int*)(0x42C81174UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_SA            *((volatile unsigned int*)(0x42C81178UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_AE            *((volatile unsigned int*)(0x42C8117CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A0            *((volatile unsigned int*)(0x42C81180UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A1            *((volatile unsigned int*)(0x42C81184UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A2            *((volatile unsigned int*)(0x42C81188UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A3            *((volatile unsigned int*)(0x42C8118CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A4            *((volatile unsigned int*)(0x42C81190UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A5            *((volatile unsigned int*)(0x42C81194UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A6            *((volatile unsigned int*)(0x42C81198UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A7            *((volatile unsigned int*)(0x42C8119CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A8            *((volatile unsigned int*)(0x42C811A0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A9            *((volatile unsigned int*)(0x42C811A4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A10           *((volatile unsigned int*)(0x42C811A8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A11           *((volatile unsigned int*)(0x42C811ACUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A12           *((volatile unsigned int*)(0x42C811B0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A13           *((volatile unsigned int*)(0x42C811B4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A14           *((volatile unsigned int*)(0x42C811B8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A15           *((volatile unsigned int*)(0x42C811BCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A16           *((volatile unsigned int*)(0x42C811C0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A17           *((volatile unsigned int*)(0x42C811C4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A18           *((volatile unsigned int*)(0x42C811C8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A19           *((volatile unsigned int*)(0x42C811CCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A20           *((volatile unsigned int*)(0x42C811D0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A21           *((volatile unsigned int*)(0x42C811D4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A22           *((volatile unsigned int*)(0x42C811D8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A23           *((volatile unsigned int*)(0x42C811DCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A24           *((volatile unsigned int*)(0x42C811E0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A25           *((volatile unsigned int*)(0x42C811E4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A26           *((volatile unsigned int*)(0x42C811E8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A27           *((volatile unsigned int*)(0x42C811ECUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A28           *((volatile unsigned int*)(0x42C811F0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A29           *((volatile unsigned int*)(0x42C811F4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A30           *((volatile unsigned int*)(0x42C811F8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A31           *((volatile unsigned int*)(0x42C811FCUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A32          *((volatile unsigned int*)(0x42C81200UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A33          *((volatile unsigned int*)(0x42C81204UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A34          *((volatile unsigned int*)(0x42C81208UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A35          *((volatile unsigned int*)(0x42C8120CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A36          *((volatile unsigned int*)(0x42C81210UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A37          *((volatile unsigned int*)(0x42C81214UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A38          *((volatile unsigned int*)(0x42C81218UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A39          *((volatile unsigned int*)(0x42C8121CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A40          *((volatile unsigned int*)(0x42C81220UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A41          *((volatile unsigned int*)(0x42C81224UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A42          *((volatile unsigned int*)(0x42C81228UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A43          *((volatile unsigned int*)(0x42C8122CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A44          *((volatile unsigned int*)(0x42C81230UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A45          *((volatile unsigned int*)(0x42C81234UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A46          *((volatile unsigned int*)(0x42C81238UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A47          *((volatile unsigned int*)(0x42C8123CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC0         *((volatile unsigned int*)(0x42C81260UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC1         *((volatile unsigned int*)(0x42C81264UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC2         *((volatile unsigned int*)(0x42C81268UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC3         *((volatile unsigned int*)(0x42C8126CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC4         *((volatile unsigned int*)(0x42C81270UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC5         *((volatile unsigned int*)(0x42C81274UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_SA           *((volatile unsigned int*)(0x42C81278UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_AE           *((volatile unsigned int*)(0x42C8127CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A0           *((volatile unsigned int*)(0x42C81280UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A1           *((volatile unsigned int*)(0x42C81284UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A2           *((volatile unsigned int*)(0x42C81288UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A3           *((volatile unsigned int*)(0x42C8128CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A4           *((volatile unsigned int*)(0x42C81290UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A5           *((volatile unsigned int*)(0x42C81294UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A6           *((volatile unsigned int*)(0x42C81298UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A7           *((volatile unsigned int*)(0x42C8129CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A8           *((volatile unsigned int*)(0x42C812A0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A9           *((volatile unsigned int*)(0x42C812A4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A10          *((volatile unsigned int*)(0x42C812A8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A11          *((volatile unsigned int*)(0x42C812ACUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A12          *((volatile unsigned int*)(0x42C812B0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A13          *((volatile unsigned int*)(0x42C812B4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A14          *((volatile unsigned int*)(0x42C812B8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A15          *((volatile unsigned int*)(0x42C812BCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A16          *((volatile unsigned int*)(0x42C812C0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A17          *((volatile unsigned int*)(0x42C812C4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A18          *((volatile unsigned int*)(0x42C812C8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A19          *((volatile unsigned int*)(0x42C812CCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A20          *((volatile unsigned int*)(0x42C812D0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A21          *((volatile unsigned int*)(0x42C812D4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A22          *((volatile unsigned int*)(0x42C812D8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A23          *((volatile unsigned int*)(0x42C812DCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A24          *((volatile unsigned int*)(0x42C812E0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A25          *((volatile unsigned int*)(0x42C812E4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A26          *((volatile unsigned int*)(0x42C812E8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A27          *((volatile unsigned int*)(0x42C812ECUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A28          *((volatile unsigned int*)(0x42C812F0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A29          *((volatile unsigned int*)(0x42C812F4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A30          *((volatile unsigned int*)(0x42C812F8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A31          *((volatile unsigned int*)(0x42C812FCUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A32          *((volatile unsigned int*)(0x42C81300UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A33          *((volatile unsigned int*)(0x42C81304UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A34          *((volatile unsigned int*)(0x42C81308UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A35          *((volatile unsigned int*)(0x42C8130CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A36          *((volatile unsigned int*)(0x42C81310UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A37          *((volatile unsigned int*)(0x42C81314UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A38          *((volatile unsigned int*)(0x42C81318UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A39          *((volatile unsigned int*)(0x42C8131CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A40          *((volatile unsigned int*)(0x42C81320UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A41          *((volatile unsigned int*)(0x42C81324UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A42          *((volatile unsigned int*)(0x42C81328UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A43          *((volatile unsigned int*)(0x42C8132CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A44          *((volatile unsigned int*)(0x42C81330UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A45          *((volatile unsigned int*)(0x42C81334UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A46          *((volatile unsigned int*)(0x42C81338UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A47          *((volatile unsigned int*)(0x42C8133CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC0         *((volatile unsigned int*)(0x42C81360UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC1         *((volatile unsigned int*)(0x42C81364UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC2         *((volatile unsigned int*)(0x42C81368UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC3         *((volatile unsigned int*)(0x42C8136CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC4         *((volatile unsigned int*)(0x42C81370UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC5         *((volatile unsigned int*)(0x42C81374UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_SA           *((volatile unsigned int*)(0x42C81378UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_AE           *((volatile unsigned int*)(0x42C8137CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A0           *((volatile unsigned int*)(0x42C81380UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A1           *((volatile unsigned int*)(0x42C81384UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A2           *((volatile unsigned int*)(0x42C81388UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A3           *((volatile unsigned int*)(0x42C8138CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A4           *((volatile unsigned int*)(0x42C81390UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A5           *((volatile unsigned int*)(0x42C81394UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A6           *((volatile unsigned int*)(0x42C81398UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A7           *((volatile unsigned int*)(0x42C8139CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A8           *((volatile unsigned int*)(0x42C813A0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A9           *((volatile unsigned int*)(0x42C813A4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A10          *((volatile unsigned int*)(0x42C813A8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A11          *((volatile unsigned int*)(0x42C813ACUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A12          *((volatile unsigned int*)(0x42C813B0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A13          *((volatile unsigned int*)(0x42C813B4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A14          *((volatile unsigned int*)(0x42C813B8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A15          *((volatile unsigned int*)(0x42C813BCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A16          *((volatile unsigned int*)(0x42C813C0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A17          *((volatile unsigned int*)(0x42C813C4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A18          *((volatile unsigned int*)(0x42C813C8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A19          *((volatile unsigned int*)(0x42C813CCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A20          *((volatile unsigned int*)(0x42C813D0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A21          *((volatile unsigned int*)(0x42C813D4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A22          *((volatile unsigned int*)(0x42C813D8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A23          *((volatile unsigned int*)(0x42C813DCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A24          *((volatile unsigned int*)(0x42C813E0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A25          *((volatile unsigned int*)(0x42C813E4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A26          *((volatile unsigned int*)(0x42C813E8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A27          *((volatile unsigned int*)(0x42C813ECUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A28          *((volatile unsigned int*)(0x42C813F0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A29          *((volatile unsigned int*)(0x42C813F4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A30          *((volatile unsigned int*)(0x42C813F8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A31          *((volatile unsigned int*)(0x42C813FCUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A32          *((volatile unsigned int*)(0x42C81400UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A33          *((volatile unsigned int*)(0x42C81404UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A34          *((volatile unsigned int*)(0x42C81408UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A35          *((volatile unsigned int*)(0x42C8140CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A36          *((volatile unsigned int*)(0x42C81410UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A37          *((volatile unsigned int*)(0x42C81414UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A38          *((volatile unsigned int*)(0x42C81418UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A39          *((volatile unsigned int*)(0x42C8141CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A40          *((volatile unsigned int*)(0x42C81420UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A41          *((volatile unsigned int*)(0x42C81424UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A42          *((volatile unsigned int*)(0x42C81428UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A43          *((volatile unsigned int*)(0x42C8142CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A44          *((volatile unsigned int*)(0x42C81430UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A45          *((volatile unsigned int*)(0x42C81434UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A46          *((volatile unsigned int*)(0x42C81438UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A47          *((volatile unsigned int*)(0x42C8143CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC0         *((volatile unsigned int*)(0x42C81460UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC1         *((volatile unsigned int*)(0x42C81464UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC2         *((volatile unsigned int*)(0x42C81468UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC3         *((volatile unsigned int*)(0x42C8146CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC4         *((volatile unsigned int*)(0x42C81470UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC5         *((volatile unsigned int*)(0x42C81474UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_SA           *((volatile unsigned int*)(0x42C81478UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_AE           *((volatile unsigned int*)(0x42C8147CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A0           *((volatile unsigned int*)(0x42C81480UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A1           *((volatile unsigned int*)(0x42C81484UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A2           *((volatile unsigned int*)(0x42C81488UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A3           *((volatile unsigned int*)(0x42C8148CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A4           *((volatile unsigned int*)(0x42C81490UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A5           *((volatile unsigned int*)(0x42C81494UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A6           *((volatile unsigned int*)(0x42C81498UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A7           *((volatile unsigned int*)(0x42C8149CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A8           *((volatile unsigned int*)(0x42C814A0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A9           *((volatile unsigned int*)(0x42C814A4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A10          *((volatile unsigned int*)(0x42C814A8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A11          *((volatile unsigned int*)(0x42C814ACUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A12          *((volatile unsigned int*)(0x42C814B0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A13          *((volatile unsigned int*)(0x42C814B4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A14          *((volatile unsigned int*)(0x42C814B8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A15          *((volatile unsigned int*)(0x42C814BCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A16          *((volatile unsigned int*)(0x42C814C0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A17          *((volatile unsigned int*)(0x42C814C4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A18          *((volatile unsigned int*)(0x42C814C8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A19          *((volatile unsigned int*)(0x42C814CCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A20          *((volatile unsigned int*)(0x42C814D0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A21          *((volatile unsigned int*)(0x42C814D4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A22          *((volatile unsigned int*)(0x42C814D8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A23          *((volatile unsigned int*)(0x42C814DCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A24          *((volatile unsigned int*)(0x42C814E0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A25          *((volatile unsigned int*)(0x42C814E4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A26          *((volatile unsigned int*)(0x42C814E8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A27          *((volatile unsigned int*)(0x42C814ECUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A28          *((volatile unsigned int*)(0x42C814F0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A29          *((volatile unsigned int*)(0x42C814F4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A30          *((volatile unsigned int*)(0x42C814F8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A31          *((volatile unsigned int*)(0x42C814FCUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A32          *((volatile unsigned int*)(0x42C81500UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A33          *((volatile unsigned int*)(0x42C81504UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A34          *((volatile unsigned int*)(0x42C81508UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A35          *((volatile unsigned int*)(0x42C8150CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A36          *((volatile unsigned int*)(0x42C81510UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A37          *((volatile unsigned int*)(0x42C81514UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A38          *((volatile unsigned int*)(0x42C81518UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A39          *((volatile unsigned int*)(0x42C8151CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A40          *((volatile unsigned int*)(0x42C81520UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A41          *((volatile unsigned int*)(0x42C81524UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A42          *((volatile unsigned int*)(0x42C81528UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A43          *((volatile unsigned int*)(0x42C8152CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A44          *((volatile unsigned int*)(0x42C81530UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A45          *((volatile unsigned int*)(0x42C81534UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A46          *((volatile unsigned int*)(0x42C81538UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A47          *((volatile unsigned int*)(0x42C8153CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC0         *((volatile unsigned int*)(0x42C81560UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC1         *((volatile unsigned int*)(0x42C81564UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC2         *((volatile unsigned int*)(0x42C81568UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC3         *((volatile unsigned int*)(0x42C8156CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC4         *((volatile unsigned int*)(0x42C81570UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC5         *((volatile unsigned int*)(0x42C81574UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_SA           *((volatile unsigned int*)(0x42C81578UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_AE           *((volatile unsigned int*)(0x42C8157CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A0           *((volatile unsigned int*)(0x42C81580UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A1           *((volatile unsigned int*)(0x42C81584UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A2           *((volatile unsigned int*)(0x42C81588UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A3           *((volatile unsigned int*)(0x42C8158CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A4           *((volatile unsigned int*)(0x42C81590UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A5           *((volatile unsigned int*)(0x42C81594UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A6           *((volatile unsigned int*)(0x42C81598UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A7           *((volatile unsigned int*)(0x42C8159CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A8           *((volatile unsigned int*)(0x42C815A0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A9           *((volatile unsigned int*)(0x42C815A4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A10          *((volatile unsigned int*)(0x42C815A8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A11          *((volatile unsigned int*)(0x42C815ACUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A12          *((volatile unsigned int*)(0x42C815B0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A13          *((volatile unsigned int*)(0x42C815B4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A14          *((volatile unsigned int*)(0x42C815B8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A15          *((volatile unsigned int*)(0x42C815BCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A16          *((volatile unsigned int*)(0x42C815C0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A17          *((volatile unsigned int*)(0x42C815C4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A18          *((volatile unsigned int*)(0x42C815C8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A19          *((volatile unsigned int*)(0x42C815CCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A20          *((volatile unsigned int*)(0x42C815D0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A21          *((volatile unsigned int*)(0x42C815D4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A22          *((volatile unsigned int*)(0x42C815D8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A23          *((volatile unsigned int*)(0x42C815DCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A24          *((volatile unsigned int*)(0x42C815E0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A25          *((volatile unsigned int*)(0x42C815E4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A26          *((volatile unsigned int*)(0x42C815E8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A27          *((volatile unsigned int*)(0x42C815ECUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A28          *((volatile unsigned int*)(0x42C815F0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A29          *((volatile unsigned int*)(0x42C815F4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A30          *((volatile unsigned int*)(0x42C815F8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A31          *((volatile unsigned int*)(0x42C815FCUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A32          *((volatile unsigned int*)(0x42C81600UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A33          *((volatile unsigned int*)(0x42C81604UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A34          *((volatile unsigned int*)(0x42C81608UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A35          *((volatile unsigned int*)(0x42C8160CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A36          *((volatile unsigned int*)(0x42C81610UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A37          *((volatile unsigned int*)(0x42C81614UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A38          *((volatile unsigned int*)(0x42C81618UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A39          *((volatile unsigned int*)(0x42C8161CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A40          *((volatile unsigned int*)(0x42C81620UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A41          *((volatile unsigned int*)(0x42C81624UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A42          *((volatile unsigned int*)(0x42C81628UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A43          *((volatile unsigned int*)(0x42C8162CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A44          *((volatile unsigned int*)(0x42C81630UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A45          *((volatile unsigned int*)(0x42C81634UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A46          *((volatile unsigned int*)(0x42C81638UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A47          *((volatile unsigned int*)(0x42C8163CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC0         *((volatile unsigned int*)(0x42C81660UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC1         *((volatile unsigned int*)(0x42C81664UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC2         *((volatile unsigned int*)(0x42C81668UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC3         *((volatile unsigned int*)(0x42C8166CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC4         *((volatile unsigned int*)(0x42C81670UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC5         *((volatile unsigned int*)(0x42C81674UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_SA           *((volatile unsigned int*)(0x42C81678UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_AE           *((volatile unsigned int*)(0x42C8167CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A0           *((volatile unsigned int*)(0x42C81680UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A1           *((volatile unsigned int*)(0x42C81684UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A2           *((volatile unsigned int*)(0x42C81688UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A3           *((volatile unsigned int*)(0x42C8168CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A4           *((volatile unsigned int*)(0x42C81690UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A5           *((volatile unsigned int*)(0x42C81694UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A6           *((volatile unsigned int*)(0x42C81698UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A7           *((volatile unsigned int*)(0x42C8169CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A8           *((volatile unsigned int*)(0x42C816A0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A9           *((volatile unsigned int*)(0x42C816A4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A10          *((volatile unsigned int*)(0x42C816A8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A11          *((volatile unsigned int*)(0x42C816ACUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A12          *((volatile unsigned int*)(0x42C816B0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A13          *((volatile unsigned int*)(0x42C816B4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A14          *((volatile unsigned int*)(0x42C816B8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A15          *((volatile unsigned int*)(0x42C816BCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A16          *((volatile unsigned int*)(0x42C816C0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A17          *((volatile unsigned int*)(0x42C816C4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A18          *((volatile unsigned int*)(0x42C816C8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A19          *((volatile unsigned int*)(0x42C816CCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A20          *((volatile unsigned int*)(0x42C816D0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A21          *((volatile unsigned int*)(0x42C816D4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A22          *((volatile unsigned int*)(0x42C816D8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A23          *((volatile unsigned int*)(0x42C816DCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A24          *((volatile unsigned int*)(0x42C816E0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A25          *((volatile unsigned int*)(0x42C816E4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A26          *((volatile unsigned int*)(0x42C816E8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A27          *((volatile unsigned int*)(0x42C816ECUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A28          *((volatile unsigned int*)(0x42C816F0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A29          *((volatile unsigned int*)(0x42C816F4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A30          *((volatile unsigned int*)(0x42C816F8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A31          *((volatile unsigned int*)(0x42C816FCUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A32          *((volatile unsigned int*)(0x42C81700UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A33          *((volatile unsigned int*)(0x42C81704UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A34          *((volatile unsigned int*)(0x42C81708UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A35          *((volatile unsigned int*)(0x42C8170CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A36          *((volatile unsigned int*)(0x42C81710UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A37          *((volatile unsigned int*)(0x42C81714UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A38          *((volatile unsigned int*)(0x42C81718UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A39          *((volatile unsigned int*)(0x42C8171CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A40          *((volatile unsigned int*)(0x42C81720UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A41          *((volatile unsigned int*)(0x42C81724UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A42          *((volatile unsigned int*)(0x42C81728UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A43          *((volatile unsigned int*)(0x42C8172CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A44          *((volatile unsigned int*)(0x42C81730UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A45          *((volatile unsigned int*)(0x42C81734UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A46          *((volatile unsigned int*)(0x42C81738UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A47          *((volatile unsigned int*)(0x42C8173CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC0         *((volatile unsigned int*)(0x42C81760UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC1         *((volatile unsigned int*)(0x42C81764UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC2         *((volatile unsigned int*)(0x42C81768UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC3         *((volatile unsigned int*)(0x42C8176CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC4         *((volatile unsigned int*)(0x42C81770UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC5         *((volatile unsigned int*)(0x42C81774UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_SA           *((volatile unsigned int*)(0x42C81778UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_AE           *((volatile unsigned int*)(0x42C8177CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A0           *((volatile unsigned int*)(0x42C81780UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A1           *((volatile unsigned int*)(0x42C81784UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A2           *((volatile unsigned int*)(0x42C81788UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A3           *((volatile unsigned int*)(0x42C8178CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A4           *((volatile unsigned int*)(0x42C81790UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A5           *((volatile unsigned int*)(0x42C81794UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A6           *((volatile unsigned int*)(0x42C81798UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A7           *((volatile unsigned int*)(0x42C8179CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A8           *((volatile unsigned int*)(0x42C817A0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A9           *((volatile unsigned int*)(0x42C817A4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A10          *((volatile unsigned int*)(0x42C817A8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A11          *((volatile unsigned int*)(0x42C817ACUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A12          *((volatile unsigned int*)(0x42C817B0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A13          *((volatile unsigned int*)(0x42C817B4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A14          *((volatile unsigned int*)(0x42C817B8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A15          *((volatile unsigned int*)(0x42C817BCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A16          *((volatile unsigned int*)(0x42C817C0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A17          *((volatile unsigned int*)(0x42C817C4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A18          *((volatile unsigned int*)(0x42C817C8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A19          *((volatile unsigned int*)(0x42C817CCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A20          *((volatile unsigned int*)(0x42C817D0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A21          *((volatile unsigned int*)(0x42C817D4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A22          *((volatile unsigned int*)(0x42C817D8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A23          *((volatile unsigned int*)(0x42C817DCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A24          *((volatile unsigned int*)(0x42C817E0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A25          *((volatile unsigned int*)(0x42C817E4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A26          *((volatile unsigned int*)(0x42C817E8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A27          *((volatile unsigned int*)(0x42C817ECUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A28          *((volatile unsigned int*)(0x42C817F0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A29          *((volatile unsigned int*)(0x42C817F4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A30          *((volatile unsigned int*)(0x42C817F8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A31          *((volatile unsigned int*)(0x42C817FCUL))
+#define bFM3_ETHERNET_MAC0_RGSR_LM             *((volatile unsigned int*)(0x42C81B00UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP0           *((volatile unsigned int*)(0x42C81B04UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP1           *((volatile unsigned int*)(0x42C81B08UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LS             *((volatile unsigned int*)(0x42C81B0CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSE            *((volatile unsigned int*)(0x42C8E000UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TFCU           *((volatile unsigned int*)(0x42C8E004UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSI            *((volatile unsigned int*)(0x42C8E008UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSU            *((volatile unsigned int*)(0x42C8E00CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TITE           *((volatile unsigned int*)(0x42C8E010UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TARU           *((volatile unsigned int*)(0x42C8E014UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSEA           *((volatile unsigned int*)(0x42C8E020UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSDB           *((volatile unsigned int*)(0x42C8E024UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSV2E          *((volatile unsigned int*)(0x42C8E028UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSP          *((volatile unsigned int*)(0x42C8E02CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E         *((volatile unsigned int*)(0x42C8E030UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E         *((volatile unsigned int*)(0x42C8E034UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSEM         *((volatile unsigned int*)(0x42C8E038UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSMRM          *((volatile unsigned int*)(0x42C8E03CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS0          *((volatile unsigned int*)(0x42C8E040UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS1          *((volatile unsigned int*)(0x42C8E044UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSENMF         *((volatile unsigned int*)(0x42C8E048UL))
+#define bFM3_ETHERNET_MAC0_TSCR_ATSFC          *((volatile unsigned int*)(0x42C8E060UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC0         *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC1         *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC2         *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC3         *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC4         *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC5         *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC6         *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC7         *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS0           *((volatile unsigned int*)(0x42C8E100UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS1           *((volatile unsigned int*)(0x42C8E104UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS2           *((volatile unsigned int*)(0x42C8E108UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS3           *((volatile unsigned int*)(0x42C8E10CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS4           *((volatile unsigned int*)(0x42C8E110UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS5           *((volatile unsigned int*)(0x42C8E114UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS6           *((volatile unsigned int*)(0x42C8E118UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS7           *((volatile unsigned int*)(0x42C8E11CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS8           *((volatile unsigned int*)(0x42C8E120UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS9           *((volatile unsigned int*)(0x42C8E124UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS10          *((volatile unsigned int*)(0x42C8E128UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS11          *((volatile unsigned int*)(0x42C8E12CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS12          *((volatile unsigned int*)(0x42C8E130UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS13          *((volatile unsigned int*)(0x42C8E134UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS14          *((volatile unsigned int*)(0x42C8E138UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS15          *((volatile unsigned int*)(0x42C8E13CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS16          *((volatile unsigned int*)(0x42C8E140UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS17          *((volatile unsigned int*)(0x42C8E144UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS18          *((volatile unsigned int*)(0x42C8E148UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS19          *((volatile unsigned int*)(0x42C8E14CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS20          *((volatile unsigned int*)(0x42C8E150UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS21          *((volatile unsigned int*)(0x42C8E154UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS22          *((volatile unsigned int*)(0x42C8E158UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS23          *((volatile unsigned int*)(0x42C8E15CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS24          *((volatile unsigned int*)(0x42C8E160UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS25          *((volatile unsigned int*)(0x42C8E164UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS26          *((volatile unsigned int*)(0x42C8E168UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS27          *((volatile unsigned int*)(0x42C8E16CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS28          *((volatile unsigned int*)(0x42C8E170UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS29          *((volatile unsigned int*)(0x42C8E174UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS30          *((volatile unsigned int*)(0x42C8E178UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS31          *((volatile unsigned int*)(0x42C8E17CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS0          *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS1          *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS2          *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS3          *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS4          *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS5          *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS6          *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS7          *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS8          *((volatile unsigned int*)(0x42C8E0A0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS9          *((volatile unsigned int*)(0x42C8E0A4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS10         *((volatile unsigned int*)(0x42C8E0A8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS11         *((volatile unsigned int*)(0x42C8E0ACUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS12         *((volatile unsigned int*)(0x42C8E0B0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS13         *((volatile unsigned int*)(0x42C8E0B4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS14         *((volatile unsigned int*)(0x42C8E0B8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS15         *((volatile unsigned int*)(0x42C8E0BCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS16         *((volatile unsigned int*)(0x42C8E0C0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS17         *((volatile unsigned int*)(0x42C8E0C4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS18         *((volatile unsigned int*)(0x42C8E0C8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS19         *((volatile unsigned int*)(0x42C8E0CCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS20         *((volatile unsigned int*)(0x42C8E0D0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS21         *((volatile unsigned int*)(0x42C8E0D4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS22         *((volatile unsigned int*)(0x42C8E0D8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS23         *((volatile unsigned int*)(0x42C8E0DCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS24         *((volatile unsigned int*)(0x42C8E0E0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS25         *((volatile unsigned int*)(0x42C8E0E4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS26         *((volatile unsigned int*)(0x42C8E0E8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS27         *((volatile unsigned int*)(0x42C8E0ECUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS28         *((volatile unsigned int*)(0x42C8E0F0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS29         *((volatile unsigned int*)(0x42C8E0F4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS30         *((volatile unsigned int*)(0x42C8E0F8UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS0          *((volatile unsigned int*)(0x42C8E200UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS1          *((volatile unsigned int*)(0x42C8E204UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS2          *((volatile unsigned int*)(0x42C8E208UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS3          *((volatile unsigned int*)(0x42C8E20CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS4          *((volatile unsigned int*)(0x42C8E210UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS5          *((volatile unsigned int*)(0x42C8E214UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS6          *((volatile unsigned int*)(0x42C8E218UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS7          *((volatile unsigned int*)(0x42C8E21CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS8          *((volatile unsigned int*)(0x42C8E220UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS9          *((volatile unsigned int*)(0x42C8E224UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS10         *((volatile unsigned int*)(0x42C8E228UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS11         *((volatile unsigned int*)(0x42C8E22CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS12         *((volatile unsigned int*)(0x42C8E230UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS13         *((volatile unsigned int*)(0x42C8E234UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS14         *((volatile unsigned int*)(0x42C8E238UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS15         *((volatile unsigned int*)(0x42C8E23CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS16         *((volatile unsigned int*)(0x42C8E240UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS17         *((volatile unsigned int*)(0x42C8E244UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS18         *((volatile unsigned int*)(0x42C8E248UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS19         *((volatile unsigned int*)(0x42C8E24CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS20         *((volatile unsigned int*)(0x42C8E250UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS21         *((volatile unsigned int*)(0x42C8E254UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS22         *((volatile unsigned int*)(0x42C8E258UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS23         *((volatile unsigned int*)(0x42C8E25CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS24         *((volatile unsigned int*)(0x42C8E260UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS25         *((volatile unsigned int*)(0x42C8E264UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS26         *((volatile unsigned int*)(0x42C8E268UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS27         *((volatile unsigned int*)(0x42C8E26CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS28         *((volatile unsigned int*)(0x42C8E270UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS29         *((volatile unsigned int*)(0x42C8E274UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS30         *((volatile unsigned int*)(0x42C8E278UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS31         *((volatile unsigned int*)(0x42C8E27CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS0         *((volatile unsigned int*)(0x42C8E280UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS1         *((volatile unsigned int*)(0x42C8E284UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS2         *((volatile unsigned int*)(0x42C8E288UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS3         *((volatile unsigned int*)(0x42C8E28CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS4         *((volatile unsigned int*)(0x42C8E290UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS5         *((volatile unsigned int*)(0x42C8E294UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS6         *((volatile unsigned int*)(0x42C8E298UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS7         *((volatile unsigned int*)(0x42C8E29CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS8         *((volatile unsigned int*)(0x42C8E2A0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS9         *((volatile unsigned int*)(0x42C8E2A4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS10        *((volatile unsigned int*)(0x42C8E2A8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS11        *((volatile unsigned int*)(0x42C8E2ACUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS12        *((volatile unsigned int*)(0x42C8E2B0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS13        *((volatile unsigned int*)(0x42C8E2B4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS14        *((volatile unsigned int*)(0x42C8E2B8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS15        *((volatile unsigned int*)(0x42C8E2BCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS16        *((volatile unsigned int*)(0x42C8E2C0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS17        *((volatile unsigned int*)(0x42C8E2C4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS18        *((volatile unsigned int*)(0x42C8E2C8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS19        *((volatile unsigned int*)(0x42C8E2CCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS20        *((volatile unsigned int*)(0x42C8E2D0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS21        *((volatile unsigned int*)(0x42C8E2D4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS22        *((volatile unsigned int*)(0x42C8E2D8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS23        *((volatile unsigned int*)(0x42C8E2DCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS24        *((volatile unsigned int*)(0x42C8E2E0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS25        *((volatile unsigned int*)(0x42C8E2E4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS26        *((volatile unsigned int*)(0x42C8E2E8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS27        *((volatile unsigned int*)(0x42C8E2ECUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS28        *((volatile unsigned int*)(0x42C8E2F0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS29        *((volatile unsigned int*)(0x42C8E2F4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS30        *((volatile unsigned int*)(0x42C8E2F8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB        *((volatile unsigned int*)(0x42C8E2FCUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR0          *((volatile unsigned int*)(0x42C8E300UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR1          *((volatile unsigned int*)(0x42C8E304UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR2          *((volatile unsigned int*)(0x42C8E308UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR3          *((volatile unsigned int*)(0x42C8E30CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR4          *((volatile unsigned int*)(0x42C8E310UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR5          *((volatile unsigned int*)(0x42C8E314UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR6          *((volatile unsigned int*)(0x42C8E318UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR7          *((volatile unsigned int*)(0x42C8E31CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR8          *((volatile unsigned int*)(0x42C8E320UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR9          *((volatile unsigned int*)(0x42C8E324UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR10         *((volatile unsigned int*)(0x42C8E328UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR11         *((volatile unsigned int*)(0x42C8E32CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR12         *((volatile unsigned int*)(0x42C8E330UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR13         *((volatile unsigned int*)(0x42C8E334UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR14         *((volatile unsigned int*)(0x42C8E338UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR15         *((volatile unsigned int*)(0x42C8E33CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR16         *((volatile unsigned int*)(0x42C8E340UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR17         *((volatile unsigned int*)(0x42C8E344UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR18         *((volatile unsigned int*)(0x42C8E348UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR19         *((volatile unsigned int*)(0x42C8E34CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR20         *((volatile unsigned int*)(0x42C8E350UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR21         *((volatile unsigned int*)(0x42C8E354UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR22         *((volatile unsigned int*)(0x42C8E358UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR23         *((volatile unsigned int*)(0x42C8E35CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR24         *((volatile unsigned int*)(0x42C8E360UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR25         *((volatile unsigned int*)(0x42C8E364UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR26         *((volatile unsigned int*)(0x42C8E368UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR27         *((volatile unsigned int*)(0x42C8E36CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR28         *((volatile unsigned int*)(0x42C8E370UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR29         *((volatile unsigned int*)(0x42C8E374UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR30         *((volatile unsigned int*)(0x42C8E378UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR31         *((volatile unsigned int*)(0x42C8E37CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR0          *((volatile unsigned int*)(0x42C8E380UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR1          *((volatile unsigned int*)(0x42C8E384UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR2          *((volatile unsigned int*)(0x42C8E388UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR3          *((volatile unsigned int*)(0x42C8E38CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR4          *((volatile unsigned int*)(0x42C8E390UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR5          *((volatile unsigned int*)(0x42C8E394UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR6          *((volatile unsigned int*)(0x42C8E398UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR7          *((volatile unsigned int*)(0x42C8E39CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR8          *((volatile unsigned int*)(0x42C8E3A0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR9          *((volatile unsigned int*)(0x42C8E3A4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR10         *((volatile unsigned int*)(0x42C8E3A8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR11         *((volatile unsigned int*)(0x42C8E3ACUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR12         *((volatile unsigned int*)(0x42C8E3B0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR13         *((volatile unsigned int*)(0x42C8E3B4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR14         *((volatile unsigned int*)(0x42C8E3B8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR15         *((volatile unsigned int*)(0x42C8E3BCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR16         *((volatile unsigned int*)(0x42C8E3C0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR17         *((volatile unsigned int*)(0x42C8E3C4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR18         *((volatile unsigned int*)(0x42C8E3C8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR19         *((volatile unsigned int*)(0x42C8E3CCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR20         *((volatile unsigned int*)(0x42C8E3D0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR21         *((volatile unsigned int*)(0x42C8E3D4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR22         *((volatile unsigned int*)(0x42C8E3D8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR23         *((volatile unsigned int*)(0x42C8E3DCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR24         *((volatile unsigned int*)(0x42C8E3E0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR25         *((volatile unsigned int*)(0x42C8E3E4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR26         *((volatile unsigned int*)(0x42C8E3E8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR27         *((volatile unsigned int*)(0x42C8E3ECUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR28         *((volatile unsigned int*)(0x42C8E3F0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR29         *((volatile unsigned int*)(0x42C8E3F4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR30         *((volatile unsigned int*)(0x42C8E3F8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR31         *((volatile unsigned int*)(0x42C8E3FCUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR0          *((volatile unsigned int*)(0x42C8E400UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR1          *((volatile unsigned int*)(0x42C8E404UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR2          *((volatile unsigned int*)(0x42C8E408UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR3          *((volatile unsigned int*)(0x42C8E40CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR4          *((volatile unsigned int*)(0x42C8E410UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR5          *((volatile unsigned int*)(0x42C8E414UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR6          *((volatile unsigned int*)(0x42C8E418UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR7          *((volatile unsigned int*)(0x42C8E41CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR8          *((volatile unsigned int*)(0x42C8E420UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR9          *((volatile unsigned int*)(0x42C8E424UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR10         *((volatile unsigned int*)(0x42C8E428UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR11         *((volatile unsigned int*)(0x42C8E42CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR12         *((volatile unsigned int*)(0x42C8E430UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR13         *((volatile unsigned int*)(0x42C8E434UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR14         *((volatile unsigned int*)(0x42C8E438UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR15         *((volatile unsigned int*)(0x42C8E43CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR16         *((volatile unsigned int*)(0x42C8E440UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR17         *((volatile unsigned int*)(0x42C8E444UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR18         *((volatile unsigned int*)(0x42C8E448UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR19         *((volatile unsigned int*)(0x42C8E44CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR20         *((volatile unsigned int*)(0x42C8E450UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR21         *((volatile unsigned int*)(0x42C8E454UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR22         *((volatile unsigned int*)(0x42C8E458UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR23         *((volatile unsigned int*)(0x42C8E45CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR24         *((volatile unsigned int*)(0x42C8E460UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR25         *((volatile unsigned int*)(0x42C8E464UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR26         *((volatile unsigned int*)(0x42C8E468UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR27         *((volatile unsigned int*)(0x42C8E46CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR28         *((volatile unsigned int*)(0x42C8E470UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR29         *((volatile unsigned int*)(0x42C8E474UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR30         *((volatile unsigned int*)(0x42C8E478UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42C8E480UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42C8E484UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42C8E488UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42C8E48CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42C8E490UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42C8E494UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42C8E498UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42C8E49CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42C8E4A0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42C8E4A4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42C8E4A8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42C8E4ACUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42C8E4B0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42C8E4B4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42C8E4B8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42C8E4BCUL))
+#define bFM3_ETHERNET_MAC0_TSR_TSSOVF          *((volatile unsigned int*)(0x42C8E500UL))
+#define bFM3_ETHERNET_MAC0_TSR_TSTART          *((volatile unsigned int*)(0x42C8E504UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSTS           *((volatile unsigned int*)(0x42C8E508UL))
+#define bFM3_ETHERNET_MAC0_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSSTM          *((volatile unsigned int*)(0x42C8E560UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS0          *((volatile unsigned int*)(0x42C8E564UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS1          *((volatile unsigned int*)(0x42C8E568UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS2          *((volatile unsigned int*)(0x42C8E56CUL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42C8E580UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42C8E584UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42C8E588UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42C8E58CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN0           *((volatile unsigned int*)(0x42C8E600UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN1           *((volatile unsigned int*)(0x42C8E604UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN2           *((volatile unsigned int*)(0x42C8E608UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN3           *((volatile unsigned int*)(0x42C8E60CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN4           *((volatile unsigned int*)(0x42C8E610UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN5           *((volatile unsigned int*)(0x42C8E614UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN6           *((volatile unsigned int*)(0x42C8E618UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN7           *((volatile unsigned int*)(0x42C8E61CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN8           *((volatile unsigned int*)(0x42C8E620UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN9           *((volatile unsigned int*)(0x42C8E624UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN10          *((volatile unsigned int*)(0x42C8E628UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN11          *((volatile unsigned int*)(0x42C8E62CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN12          *((volatile unsigned int*)(0x42C8E630UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN13          *((volatile unsigned int*)(0x42C8E634UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN14          *((volatile unsigned int*)(0x42C8E638UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN15          *((volatile unsigned int*)(0x42C8E63CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN16          *((volatile unsigned int*)(0x42C8E640UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN17          *((volatile unsigned int*)(0x42C8E644UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN18          *((volatile unsigned int*)(0x42C8E648UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN19          *((volatile unsigned int*)(0x42C8E64CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN20          *((volatile unsigned int*)(0x42C8E650UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN21          *((volatile unsigned int*)(0x42C8E654UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN22          *((volatile unsigned int*)(0x42C8E658UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN23          *((volatile unsigned int*)(0x42C8E65CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN24          *((volatile unsigned int*)(0x42C8E660UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN25          *((volatile unsigned int*)(0x42C8E664UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN26          *((volatile unsigned int*)(0x42C8E668UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN27          *((volatile unsigned int*)(0x42C8E66CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN28          *((volatile unsigned int*)(0x42C8E670UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN29          *((volatile unsigned int*)(0x42C8E674UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN30          *((volatile unsigned int*)(0x42C8E678UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS0           *((volatile unsigned int*)(0x42C8E680UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS1           *((volatile unsigned int*)(0x42C8E684UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS2           *((volatile unsigned int*)(0x42C8E688UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS3           *((volatile unsigned int*)(0x42C8E68CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS4           *((volatile unsigned int*)(0x42C8E690UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS5           *((volatile unsigned int*)(0x42C8E694UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS6           *((volatile unsigned int*)(0x42C8E698UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS7           *((volatile unsigned int*)(0x42C8E69CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS8           *((volatile unsigned int*)(0x42C8E6A0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS9           *((volatile unsigned int*)(0x42C8E6A4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS10          *((volatile unsigned int*)(0x42C8E6A8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS11          *((volatile unsigned int*)(0x42C8E6ACUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS12          *((volatile unsigned int*)(0x42C8E6B0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS13          *((volatile unsigned int*)(0x42C8E6B4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS14          *((volatile unsigned int*)(0x42C8E6B8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS15          *((volatile unsigned int*)(0x42C8E6BCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS16          *((volatile unsigned int*)(0x42C8E6C0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS17          *((volatile unsigned int*)(0x42C8E6C4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS18          *((volatile unsigned int*)(0x42C8E6C8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS19          *((volatile unsigned int*)(0x42C8E6CCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS20          *((volatile unsigned int*)(0x42C8E6D0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS21          *((volatile unsigned int*)(0x42C8E6D4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS22          *((volatile unsigned int*)(0x42C8E6D8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS23          *((volatile unsigned int*)(0x42C8E6DCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS24          *((volatile unsigned int*)(0x42C8E6E0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS25          *((volatile unsigned int*)(0x42C8E6E4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS26          *((volatile unsigned int*)(0x42C8E6E8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS27          *((volatile unsigned int*)(0x42C8E6ECUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS28          *((volatile unsigned int*)(0x42C8E6F0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS29          *((volatile unsigned int*)(0x42C8E6F4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS30          *((volatile unsigned int*)(0x42C8E6F8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS31          *((volatile unsigned int*)(0x42C8E6FCUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A32          *((volatile unsigned int*)(0x42C90000UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A33          *((volatile unsigned int*)(0x42C90004UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A34          *((volatile unsigned int*)(0x42C90008UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A35          *((volatile unsigned int*)(0x42C9000CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A36          *((volatile unsigned int*)(0x42C90010UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A37          *((volatile unsigned int*)(0x42C90014UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A38          *((volatile unsigned int*)(0x42C90018UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A39          *((volatile unsigned int*)(0x42C9001CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A40          *((volatile unsigned int*)(0x42C90020UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A41          *((volatile unsigned int*)(0x42C90024UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A42          *((volatile unsigned int*)(0x42C90028UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A43          *((volatile unsigned int*)(0x42C9002CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A44          *((volatile unsigned int*)(0x42C90030UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A45          *((volatile unsigned int*)(0x42C90034UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A46          *((volatile unsigned int*)(0x42C90038UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A47          *((volatile unsigned int*)(0x42C9003CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC0         *((volatile unsigned int*)(0x42C90060UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC1         *((volatile unsigned int*)(0x42C90064UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC2         *((volatile unsigned int*)(0x42C90068UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC3         *((volatile unsigned int*)(0x42C9006CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC4         *((volatile unsigned int*)(0x42C90070UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC5         *((volatile unsigned int*)(0x42C90074UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_SA           *((volatile unsigned int*)(0x42C90078UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_AE           *((volatile unsigned int*)(0x42C9007CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A0           *((volatile unsigned int*)(0x42C90080UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A1           *((volatile unsigned int*)(0x42C90084UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A2           *((volatile unsigned int*)(0x42C90088UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A3           *((volatile unsigned int*)(0x42C9008CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A4           *((volatile unsigned int*)(0x42C90090UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A5           *((volatile unsigned int*)(0x42C90094UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A6           *((volatile unsigned int*)(0x42C90098UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A7           *((volatile unsigned int*)(0x42C9009CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A8           *((volatile unsigned int*)(0x42C900A0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A9           *((volatile unsigned int*)(0x42C900A4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A10          *((volatile unsigned int*)(0x42C900A8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A11          *((volatile unsigned int*)(0x42C900ACUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A12          *((volatile unsigned int*)(0x42C900B0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A13          *((volatile unsigned int*)(0x42C900B4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A14          *((volatile unsigned int*)(0x42C900B8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A15          *((volatile unsigned int*)(0x42C900BCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A16          *((volatile unsigned int*)(0x42C900C0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A17          *((volatile unsigned int*)(0x42C900C4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A18          *((volatile unsigned int*)(0x42C900C8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A19          *((volatile unsigned int*)(0x42C900CCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A20          *((volatile unsigned int*)(0x42C900D0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A21          *((volatile unsigned int*)(0x42C900D4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A22          *((volatile unsigned int*)(0x42C900D8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A23          *((volatile unsigned int*)(0x42C900DCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A24          *((volatile unsigned int*)(0x42C900E0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A25          *((volatile unsigned int*)(0x42C900E4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A26          *((volatile unsigned int*)(0x42C900E8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A27          *((volatile unsigned int*)(0x42C900ECUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A28          *((volatile unsigned int*)(0x42C900F0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A29          *((volatile unsigned int*)(0x42C900F4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A30          *((volatile unsigned int*)(0x42C900F8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A31          *((volatile unsigned int*)(0x42C900FCUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A32          *((volatile unsigned int*)(0x42C90100UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A33          *((volatile unsigned int*)(0x42C90104UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A34          *((volatile unsigned int*)(0x42C90108UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A35          *((volatile unsigned int*)(0x42C9010CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A36          *((volatile unsigned int*)(0x42C90110UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A37          *((volatile unsigned int*)(0x42C90114UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A38          *((volatile unsigned int*)(0x42C90118UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A39          *((volatile unsigned int*)(0x42C9011CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A40          *((volatile unsigned int*)(0x42C90120UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A41          *((volatile unsigned int*)(0x42C90124UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A42          *((volatile unsigned int*)(0x42C90128UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A43          *((volatile unsigned int*)(0x42C9012CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A44          *((volatile unsigned int*)(0x42C90130UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A45          *((volatile unsigned int*)(0x42C90134UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A46          *((volatile unsigned int*)(0x42C90138UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A47          *((volatile unsigned int*)(0x42C9013CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC0         *((volatile unsigned int*)(0x42C90160UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC1         *((volatile unsigned int*)(0x42C90164UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC2         *((volatile unsigned int*)(0x42C90168UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC3         *((volatile unsigned int*)(0x42C9016CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC4         *((volatile unsigned int*)(0x42C90170UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC5         *((volatile unsigned int*)(0x42C90174UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_SA           *((volatile unsigned int*)(0x42C90178UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_AE           *((volatile unsigned int*)(0x42C9017CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A0           *((volatile unsigned int*)(0x42C90180UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A1           *((volatile unsigned int*)(0x42C90184UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A2           *((volatile unsigned int*)(0x42C90188UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A3           *((volatile unsigned int*)(0x42C9018CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A4           *((volatile unsigned int*)(0x42C90190UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A5           *((volatile unsigned int*)(0x42C90194UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A6           *((volatile unsigned int*)(0x42C90198UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A7           *((volatile unsigned int*)(0x42C9019CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A8           *((volatile unsigned int*)(0x42C901A0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A9           *((volatile unsigned int*)(0x42C901A4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A10          *((volatile unsigned int*)(0x42C901A8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A11          *((volatile unsigned int*)(0x42C901ACUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A12          *((volatile unsigned int*)(0x42C901B0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A13          *((volatile unsigned int*)(0x42C901B4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A14          *((volatile unsigned int*)(0x42C901B8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A15          *((volatile unsigned int*)(0x42C901BCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A16          *((volatile unsigned int*)(0x42C901C0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A17          *((volatile unsigned int*)(0x42C901C4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A18          *((volatile unsigned int*)(0x42C901C8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A19          *((volatile unsigned int*)(0x42C901CCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A20          *((volatile unsigned int*)(0x42C901D0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A21          *((volatile unsigned int*)(0x42C901D4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A22          *((volatile unsigned int*)(0x42C901D8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A23          *((volatile unsigned int*)(0x42C901DCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A24          *((volatile unsigned int*)(0x42C901E0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A25          *((volatile unsigned int*)(0x42C901E4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A26          *((volatile unsigned int*)(0x42C901E8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A27          *((volatile unsigned int*)(0x42C901ECUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A28          *((volatile unsigned int*)(0x42C901F0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A29          *((volatile unsigned int*)(0x42C901F4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A30          *((volatile unsigned int*)(0x42C901F8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A31          *((volatile unsigned int*)(0x42C901FCUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A32          *((volatile unsigned int*)(0x42C90200UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A33          *((volatile unsigned int*)(0x42C90204UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A34          *((volatile unsigned int*)(0x42C90208UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A35          *((volatile unsigned int*)(0x42C9020CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A36          *((volatile unsigned int*)(0x42C90210UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A37          *((volatile unsigned int*)(0x42C90214UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A38          *((volatile unsigned int*)(0x42C90218UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A39          *((volatile unsigned int*)(0x42C9021CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A40          *((volatile unsigned int*)(0x42C90220UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A41          *((volatile unsigned int*)(0x42C90224UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A42          *((volatile unsigned int*)(0x42C90228UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A43          *((volatile unsigned int*)(0x42C9022CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A44          *((volatile unsigned int*)(0x42C90230UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A45          *((volatile unsigned int*)(0x42C90234UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A46          *((volatile unsigned int*)(0x42C90238UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A47          *((volatile unsigned int*)(0x42C9023CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC0         *((volatile unsigned int*)(0x42C90260UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC1         *((volatile unsigned int*)(0x42C90264UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC2         *((volatile unsigned int*)(0x42C90268UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC3         *((volatile unsigned int*)(0x42C9026CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC4         *((volatile unsigned int*)(0x42C90270UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC5         *((volatile unsigned int*)(0x42C90274UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_SA           *((volatile unsigned int*)(0x42C90278UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_AE           *((volatile unsigned int*)(0x42C9027CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A0           *((volatile unsigned int*)(0x42C90280UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A1           *((volatile unsigned int*)(0x42C90284UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A2           *((volatile unsigned int*)(0x42C90288UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A3           *((volatile unsigned int*)(0x42C9028CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A4           *((volatile unsigned int*)(0x42C90290UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A5           *((volatile unsigned int*)(0x42C90294UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A6           *((volatile unsigned int*)(0x42C90298UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A7           *((volatile unsigned int*)(0x42C9029CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A8           *((volatile unsigned int*)(0x42C902A0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A9           *((volatile unsigned int*)(0x42C902A4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A10          *((volatile unsigned int*)(0x42C902A8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A11          *((volatile unsigned int*)(0x42C902ACUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A12          *((volatile unsigned int*)(0x42C902B0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A13          *((volatile unsigned int*)(0x42C902B4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A14          *((volatile unsigned int*)(0x42C902B8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A15          *((volatile unsigned int*)(0x42C902BCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A16          *((volatile unsigned int*)(0x42C902C0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A17          *((volatile unsigned int*)(0x42C902C4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A18          *((volatile unsigned int*)(0x42C902C8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A19          *((volatile unsigned int*)(0x42C902CCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A20          *((volatile unsigned int*)(0x42C902D0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A21          *((volatile unsigned int*)(0x42C902D4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A22          *((volatile unsigned int*)(0x42C902D8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A23          *((volatile unsigned int*)(0x42C902DCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A24          *((volatile unsigned int*)(0x42C902E0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A25          *((volatile unsigned int*)(0x42C902E4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A26          *((volatile unsigned int*)(0x42C902E8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A27          *((volatile unsigned int*)(0x42C902ECUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A28          *((volatile unsigned int*)(0x42C902F0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A29          *((volatile unsigned int*)(0x42C902F4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A30          *((volatile unsigned int*)(0x42C902F8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A31          *((volatile unsigned int*)(0x42C902FCUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A32          *((volatile unsigned int*)(0x42C90300UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A33          *((volatile unsigned int*)(0x42C90304UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A34          *((volatile unsigned int*)(0x42C90308UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A35          *((volatile unsigned int*)(0x42C9030CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A36          *((volatile unsigned int*)(0x42C90310UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A37          *((volatile unsigned int*)(0x42C90314UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A38          *((volatile unsigned int*)(0x42C90318UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A39          *((volatile unsigned int*)(0x42C9031CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A40          *((volatile unsigned int*)(0x42C90320UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A41          *((volatile unsigned int*)(0x42C90324UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A42          *((volatile unsigned int*)(0x42C90328UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A43          *((volatile unsigned int*)(0x42C9032CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A44          *((volatile unsigned int*)(0x42C90330UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A45          *((volatile unsigned int*)(0x42C90334UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A46          *((volatile unsigned int*)(0x42C90338UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A47          *((volatile unsigned int*)(0x42C9033CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC0         *((volatile unsigned int*)(0x42C90360UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC1         *((volatile unsigned int*)(0x42C90364UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC2         *((volatile unsigned int*)(0x42C90368UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC3         *((volatile unsigned int*)(0x42C9036CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC4         *((volatile unsigned int*)(0x42C90370UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC5         *((volatile unsigned int*)(0x42C90374UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_SA           *((volatile unsigned int*)(0x42C90378UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_AE           *((volatile unsigned int*)(0x42C9037CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A0           *((volatile unsigned int*)(0x42C90380UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A1           *((volatile unsigned int*)(0x42C90384UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A2           *((volatile unsigned int*)(0x42C90388UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A3           *((volatile unsigned int*)(0x42C9038CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A4           *((volatile unsigned int*)(0x42C90390UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A5           *((volatile unsigned int*)(0x42C90394UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A6           *((volatile unsigned int*)(0x42C90398UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A7           *((volatile unsigned int*)(0x42C9039CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A8           *((volatile unsigned int*)(0x42C903A0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A9           *((volatile unsigned int*)(0x42C903A4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A10          *((volatile unsigned int*)(0x42C903A8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A11          *((volatile unsigned int*)(0x42C903ACUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A12          *((volatile unsigned int*)(0x42C903B0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A13          *((volatile unsigned int*)(0x42C903B4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A14          *((volatile unsigned int*)(0x42C903B8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A15          *((volatile unsigned int*)(0x42C903BCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A16          *((volatile unsigned int*)(0x42C903C0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A17          *((volatile unsigned int*)(0x42C903C4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A18          *((volatile unsigned int*)(0x42C903C8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A19          *((volatile unsigned int*)(0x42C903CCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A20          *((volatile unsigned int*)(0x42C903D0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A21          *((volatile unsigned int*)(0x42C903D4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A22          *((volatile unsigned int*)(0x42C903D8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A23          *((volatile unsigned int*)(0x42C903DCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A24          *((volatile unsigned int*)(0x42C903E0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A25          *((volatile unsigned int*)(0x42C903E4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A26          *((volatile unsigned int*)(0x42C903E8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A27          *((volatile unsigned int*)(0x42C903ECUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A28          *((volatile unsigned int*)(0x42C903F0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A29          *((volatile unsigned int*)(0x42C903F4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A30          *((volatile unsigned int*)(0x42C903F8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A31          *((volatile unsigned int*)(0x42C903FCUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A32          *((volatile unsigned int*)(0x42C90400UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A33          *((volatile unsigned int*)(0x42C90404UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A34          *((volatile unsigned int*)(0x42C90408UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A35          *((volatile unsigned int*)(0x42C9040CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A36          *((volatile unsigned int*)(0x42C90410UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A37          *((volatile unsigned int*)(0x42C90414UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A38          *((volatile unsigned int*)(0x42C90418UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A39          *((volatile unsigned int*)(0x42C9041CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A40          *((volatile unsigned int*)(0x42C90420UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A41          *((volatile unsigned int*)(0x42C90424UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A42          *((volatile unsigned int*)(0x42C90428UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A43          *((volatile unsigned int*)(0x42C9042CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A44          *((volatile unsigned int*)(0x42C90430UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A45          *((volatile unsigned int*)(0x42C90434UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A46          *((volatile unsigned int*)(0x42C90438UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A47          *((volatile unsigned int*)(0x42C9043CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC0         *((volatile unsigned int*)(0x42C90460UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC1         *((volatile unsigned int*)(0x42C90464UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC2         *((volatile unsigned int*)(0x42C90468UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC3         *((volatile unsigned int*)(0x42C9046CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC4         *((volatile unsigned int*)(0x42C90470UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC5         *((volatile unsigned int*)(0x42C90474UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_SA           *((volatile unsigned int*)(0x42C90478UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_AE           *((volatile unsigned int*)(0x42C9047CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A0           *((volatile unsigned int*)(0x42C90480UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A1           *((volatile unsigned int*)(0x42C90484UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A2           *((volatile unsigned int*)(0x42C90488UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A3           *((volatile unsigned int*)(0x42C9048CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A4           *((volatile unsigned int*)(0x42C90490UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A5           *((volatile unsigned int*)(0x42C90494UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A6           *((volatile unsigned int*)(0x42C90498UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A7           *((volatile unsigned int*)(0x42C9049CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A8           *((volatile unsigned int*)(0x42C904A0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A9           *((volatile unsigned int*)(0x42C904A4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A10          *((volatile unsigned int*)(0x42C904A8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A11          *((volatile unsigned int*)(0x42C904ACUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A12          *((volatile unsigned int*)(0x42C904B0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A13          *((volatile unsigned int*)(0x42C904B4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A14          *((volatile unsigned int*)(0x42C904B8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A15          *((volatile unsigned int*)(0x42C904BCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A16          *((volatile unsigned int*)(0x42C904C0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A17          *((volatile unsigned int*)(0x42C904C4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A18          *((volatile unsigned int*)(0x42C904C8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A19          *((volatile unsigned int*)(0x42C904CCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A20          *((volatile unsigned int*)(0x42C904D0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A21          *((volatile unsigned int*)(0x42C904D4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A22          *((volatile unsigned int*)(0x42C904D8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A23          *((volatile unsigned int*)(0x42C904DCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A24          *((volatile unsigned int*)(0x42C904E0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A25          *((volatile unsigned int*)(0x42C904E4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A26          *((volatile unsigned int*)(0x42C904E8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A27          *((volatile unsigned int*)(0x42C904ECUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A28          *((volatile unsigned int*)(0x42C904F0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A29          *((volatile unsigned int*)(0x42C904F4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A30          *((volatile unsigned int*)(0x42C904F8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A31          *((volatile unsigned int*)(0x42C904FCUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A32          *((volatile unsigned int*)(0x42C90500UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A33          *((volatile unsigned int*)(0x42C90504UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A34          *((volatile unsigned int*)(0x42C90508UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A35          *((volatile unsigned int*)(0x42C9050CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A36          *((volatile unsigned int*)(0x42C90510UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A37          *((volatile unsigned int*)(0x42C90514UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A38          *((volatile unsigned int*)(0x42C90518UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A39          *((volatile unsigned int*)(0x42C9051CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A40          *((volatile unsigned int*)(0x42C90520UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A41          *((volatile unsigned int*)(0x42C90524UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A42          *((volatile unsigned int*)(0x42C90528UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A43          *((volatile unsigned int*)(0x42C9052CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A44          *((volatile unsigned int*)(0x42C90530UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A45          *((volatile unsigned int*)(0x42C90534UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A46          *((volatile unsigned int*)(0x42C90538UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A47          *((volatile unsigned int*)(0x42C9053CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC0         *((volatile unsigned int*)(0x42C90560UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC1         *((volatile unsigned int*)(0x42C90564UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC2         *((volatile unsigned int*)(0x42C90568UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC3         *((volatile unsigned int*)(0x42C9056CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC4         *((volatile unsigned int*)(0x42C90570UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC5         *((volatile unsigned int*)(0x42C90574UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_SA           *((volatile unsigned int*)(0x42C90578UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_AE           *((volatile unsigned int*)(0x42C9057CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A0           *((volatile unsigned int*)(0x42C90580UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A1           *((volatile unsigned int*)(0x42C90584UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A2           *((volatile unsigned int*)(0x42C90588UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A3           *((volatile unsigned int*)(0x42C9058CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A4           *((volatile unsigned int*)(0x42C90590UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A5           *((volatile unsigned int*)(0x42C90594UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A6           *((volatile unsigned int*)(0x42C90598UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A7           *((volatile unsigned int*)(0x42C9059CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A8           *((volatile unsigned int*)(0x42C905A0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A9           *((volatile unsigned int*)(0x42C905A4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A10          *((volatile unsigned int*)(0x42C905A8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A11          *((volatile unsigned int*)(0x42C905ACUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A12          *((volatile unsigned int*)(0x42C905B0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A13          *((volatile unsigned int*)(0x42C905B4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A14          *((volatile unsigned int*)(0x42C905B8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A15          *((volatile unsigned int*)(0x42C905BCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A16          *((volatile unsigned int*)(0x42C905C0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A17          *((volatile unsigned int*)(0x42C905C4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A18          *((volatile unsigned int*)(0x42C905C8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A19          *((volatile unsigned int*)(0x42C905CCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A20          *((volatile unsigned int*)(0x42C905D0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A21          *((volatile unsigned int*)(0x42C905D4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A22          *((volatile unsigned int*)(0x42C905D8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A23          *((volatile unsigned int*)(0x42C905DCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A24          *((volatile unsigned int*)(0x42C905E0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A25          *((volatile unsigned int*)(0x42C905E4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A26          *((volatile unsigned int*)(0x42C905E8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A27          *((volatile unsigned int*)(0x42C905ECUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A28          *((volatile unsigned int*)(0x42C905F0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A29          *((volatile unsigned int*)(0x42C905F4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A30          *((volatile unsigned int*)(0x42C905F8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A31          *((volatile unsigned int*)(0x42C905FCUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A32          *((volatile unsigned int*)(0x42C90600UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A33          *((volatile unsigned int*)(0x42C90604UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A34          *((volatile unsigned int*)(0x42C90608UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A35          *((volatile unsigned int*)(0x42C9060CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A36          *((volatile unsigned int*)(0x42C90610UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A37          *((volatile unsigned int*)(0x42C90614UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A38          *((volatile unsigned int*)(0x42C90618UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A39          *((volatile unsigned int*)(0x42C9061CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A40          *((volatile unsigned int*)(0x42C90620UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A41          *((volatile unsigned int*)(0x42C90624UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A42          *((volatile unsigned int*)(0x42C90628UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A43          *((volatile unsigned int*)(0x42C9062CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A44          *((volatile unsigned int*)(0x42C90630UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A45          *((volatile unsigned int*)(0x42C90634UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A46          *((volatile unsigned int*)(0x42C90638UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A47          *((volatile unsigned int*)(0x42C9063CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC0         *((volatile unsigned int*)(0x42C90660UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC1         *((volatile unsigned int*)(0x42C90664UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC2         *((volatile unsigned int*)(0x42C90668UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC3         *((volatile unsigned int*)(0x42C9066CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC4         *((volatile unsigned int*)(0x42C90670UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC5         *((volatile unsigned int*)(0x42C90674UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_SA           *((volatile unsigned int*)(0x42C90678UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_AE           *((volatile unsigned int*)(0x42C9067CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A0           *((volatile unsigned int*)(0x42C90680UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A1           *((volatile unsigned int*)(0x42C90684UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A2           *((volatile unsigned int*)(0x42C90688UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A3           *((volatile unsigned int*)(0x42C9068CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A4           *((volatile unsigned int*)(0x42C90690UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A5           *((volatile unsigned int*)(0x42C90694UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A6           *((volatile unsigned int*)(0x42C90698UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A7           *((volatile unsigned int*)(0x42C9069CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A8           *((volatile unsigned int*)(0x42C906A0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A9           *((volatile unsigned int*)(0x42C906A4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A10          *((volatile unsigned int*)(0x42C906A8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A11          *((volatile unsigned int*)(0x42C906ACUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A12          *((volatile unsigned int*)(0x42C906B0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A13          *((volatile unsigned int*)(0x42C906B4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A14          *((volatile unsigned int*)(0x42C906B8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A15          *((volatile unsigned int*)(0x42C906BCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A16          *((volatile unsigned int*)(0x42C906C0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A17          *((volatile unsigned int*)(0x42C906C4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A18          *((volatile unsigned int*)(0x42C906C8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A19          *((volatile unsigned int*)(0x42C906CCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A20          *((volatile unsigned int*)(0x42C906D0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A21          *((volatile unsigned int*)(0x42C906D4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A22          *((volatile unsigned int*)(0x42C906D8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A23          *((volatile unsigned int*)(0x42C906DCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A24          *((volatile unsigned int*)(0x42C906E0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A25          *((volatile unsigned int*)(0x42C906E4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A26          *((volatile unsigned int*)(0x42C906E8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A27          *((volatile unsigned int*)(0x42C906ECUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A28          *((volatile unsigned int*)(0x42C906F0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A29          *((volatile unsigned int*)(0x42C906F4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A30          *((volatile unsigned int*)(0x42C906F8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A31          *((volatile unsigned int*)(0x42C906FCUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A32          *((volatile unsigned int*)(0x42C90700UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A33          *((volatile unsigned int*)(0x42C90704UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A34          *((volatile unsigned int*)(0x42C90708UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A35          *((volatile unsigned int*)(0x42C9070CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A36          *((volatile unsigned int*)(0x42C90710UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A37          *((volatile unsigned int*)(0x42C90714UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A38          *((volatile unsigned int*)(0x42C90718UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A39          *((volatile unsigned int*)(0x42C9071CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A40          *((volatile unsigned int*)(0x42C90720UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A41          *((volatile unsigned int*)(0x42C90724UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A42          *((volatile unsigned int*)(0x42C90728UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A43          *((volatile unsigned int*)(0x42C9072CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A44          *((volatile unsigned int*)(0x42C90730UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A45          *((volatile unsigned int*)(0x42C90734UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A46          *((volatile unsigned int*)(0x42C90738UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A47          *((volatile unsigned int*)(0x42C9073CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC0         *((volatile unsigned int*)(0x42C90760UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC1         *((volatile unsigned int*)(0x42C90764UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC2         *((volatile unsigned int*)(0x42C90768UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC3         *((volatile unsigned int*)(0x42C9076CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC4         *((volatile unsigned int*)(0x42C90770UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC5         *((volatile unsigned int*)(0x42C90774UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_SA           *((volatile unsigned int*)(0x42C90778UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_AE           *((volatile unsigned int*)(0x42C9077CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A0           *((volatile unsigned int*)(0x42C90780UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A1           *((volatile unsigned int*)(0x42C90784UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A2           *((volatile unsigned int*)(0x42C90788UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A3           *((volatile unsigned int*)(0x42C9078CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A4           *((volatile unsigned int*)(0x42C90790UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A5           *((volatile unsigned int*)(0x42C90794UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A6           *((volatile unsigned int*)(0x42C90798UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A7           *((volatile unsigned int*)(0x42C9079CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A8           *((volatile unsigned int*)(0x42C907A0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A9           *((volatile unsigned int*)(0x42C907A4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A10          *((volatile unsigned int*)(0x42C907A8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A11          *((volatile unsigned int*)(0x42C907ACUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A12          *((volatile unsigned int*)(0x42C907B0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A13          *((volatile unsigned int*)(0x42C907B4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A14          *((volatile unsigned int*)(0x42C907B8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A15          *((volatile unsigned int*)(0x42C907BCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A16          *((volatile unsigned int*)(0x42C907C0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A17          *((volatile unsigned int*)(0x42C907C4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A18          *((volatile unsigned int*)(0x42C907C8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A19          *((volatile unsigned int*)(0x42C907CCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A20          *((volatile unsigned int*)(0x42C907D0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A21          *((volatile unsigned int*)(0x42C907D4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A22          *((volatile unsigned int*)(0x42C907D8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A23          *((volatile unsigned int*)(0x42C907DCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A24          *((volatile unsigned int*)(0x42C907E0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A25          *((volatile unsigned int*)(0x42C907E4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A26          *((volatile unsigned int*)(0x42C907E8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A27          *((volatile unsigned int*)(0x42C907ECUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A28          *((volatile unsigned int*)(0x42C907F0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A29          *((volatile unsigned int*)(0x42C907F4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A30          *((volatile unsigned int*)(0x42C907F8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A31          *((volatile unsigned int*)(0x42C907FCUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A32          *((volatile unsigned int*)(0x42C90800UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A33          *((volatile unsigned int*)(0x42C90804UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A34          *((volatile unsigned int*)(0x42C90808UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A35          *((volatile unsigned int*)(0x42C9080CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A36          *((volatile unsigned int*)(0x42C90810UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A37          *((volatile unsigned int*)(0x42C90814UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A38          *((volatile unsigned int*)(0x42C90818UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A39          *((volatile unsigned int*)(0x42C9081CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A40          *((volatile unsigned int*)(0x42C90820UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A41          *((volatile unsigned int*)(0x42C90824UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A42          *((volatile unsigned int*)(0x42C90828UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A43          *((volatile unsigned int*)(0x42C9082CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A44          *((volatile unsigned int*)(0x42C90830UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A45          *((volatile unsigned int*)(0x42C90834UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A46          *((volatile unsigned int*)(0x42C90838UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A47          *((volatile unsigned int*)(0x42C9083CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC0         *((volatile unsigned int*)(0x42C90860UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC1         *((volatile unsigned int*)(0x42C90864UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC2         *((volatile unsigned int*)(0x42C90868UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC3         *((volatile unsigned int*)(0x42C9086CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC4         *((volatile unsigned int*)(0x42C90870UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC5         *((volatile unsigned int*)(0x42C90874UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_SA           *((volatile unsigned int*)(0x42C90878UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_AE           *((volatile unsigned int*)(0x42C9087CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A0           *((volatile unsigned int*)(0x42C90880UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A1           *((volatile unsigned int*)(0x42C90884UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A2           *((volatile unsigned int*)(0x42C90888UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A3           *((volatile unsigned int*)(0x42C9088CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A4           *((volatile unsigned int*)(0x42C90890UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A5           *((volatile unsigned int*)(0x42C90894UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A6           *((volatile unsigned int*)(0x42C90898UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A7           *((volatile unsigned int*)(0x42C9089CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A8           *((volatile unsigned int*)(0x42C908A0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A9           *((volatile unsigned int*)(0x42C908A4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A10          *((volatile unsigned int*)(0x42C908A8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A11          *((volatile unsigned int*)(0x42C908ACUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A12          *((volatile unsigned int*)(0x42C908B0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A13          *((volatile unsigned int*)(0x42C908B4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A14          *((volatile unsigned int*)(0x42C908B8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A15          *((volatile unsigned int*)(0x42C908BCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A16          *((volatile unsigned int*)(0x42C908C0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A17          *((volatile unsigned int*)(0x42C908C4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A18          *((volatile unsigned int*)(0x42C908C8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A19          *((volatile unsigned int*)(0x42C908CCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A20          *((volatile unsigned int*)(0x42C908D0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A21          *((volatile unsigned int*)(0x42C908D4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A22          *((volatile unsigned int*)(0x42C908D8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A23          *((volatile unsigned int*)(0x42C908DCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A24          *((volatile unsigned int*)(0x42C908E0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A25          *((volatile unsigned int*)(0x42C908E4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A26          *((volatile unsigned int*)(0x42C908E8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A27          *((volatile unsigned int*)(0x42C908ECUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A28          *((volatile unsigned int*)(0x42C908F0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A29          *((volatile unsigned int*)(0x42C908F4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A30          *((volatile unsigned int*)(0x42C908F8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A31          *((volatile unsigned int*)(0x42C908FCUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A32          *((volatile unsigned int*)(0x42C90900UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A33          *((volatile unsigned int*)(0x42C90904UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A34          *((volatile unsigned int*)(0x42C90908UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A35          *((volatile unsigned int*)(0x42C9090CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A36          *((volatile unsigned int*)(0x42C90910UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A37          *((volatile unsigned int*)(0x42C90914UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A38          *((volatile unsigned int*)(0x42C90918UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A39          *((volatile unsigned int*)(0x42C9091CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A40          *((volatile unsigned int*)(0x42C90920UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A41          *((volatile unsigned int*)(0x42C90924UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A42          *((volatile unsigned int*)(0x42C90928UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A43          *((volatile unsigned int*)(0x42C9092CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A44          *((volatile unsigned int*)(0x42C90930UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A45          *((volatile unsigned int*)(0x42C90934UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A46          *((volatile unsigned int*)(0x42C90938UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A47          *((volatile unsigned int*)(0x42C9093CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC0         *((volatile unsigned int*)(0x42C90960UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC1         *((volatile unsigned int*)(0x42C90964UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC2         *((volatile unsigned int*)(0x42C90968UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC3         *((volatile unsigned int*)(0x42C9096CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC4         *((volatile unsigned int*)(0x42C90970UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC5         *((volatile unsigned int*)(0x42C90974UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_SA           *((volatile unsigned int*)(0x42C90978UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_AE           *((volatile unsigned int*)(0x42C9097CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A0           *((volatile unsigned int*)(0x42C90980UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A1           *((volatile unsigned int*)(0x42C90984UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A2           *((volatile unsigned int*)(0x42C90988UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A3           *((volatile unsigned int*)(0x42C9098CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A4           *((volatile unsigned int*)(0x42C90990UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A5           *((volatile unsigned int*)(0x42C90994UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A6           *((volatile unsigned int*)(0x42C90998UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A7           *((volatile unsigned int*)(0x42C9099CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A8           *((volatile unsigned int*)(0x42C909A0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A9           *((volatile unsigned int*)(0x42C909A4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A10          *((volatile unsigned int*)(0x42C909A8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A11          *((volatile unsigned int*)(0x42C909ACUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A12          *((volatile unsigned int*)(0x42C909B0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A13          *((volatile unsigned int*)(0x42C909B4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A14          *((volatile unsigned int*)(0x42C909B8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A15          *((volatile unsigned int*)(0x42C909BCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A16          *((volatile unsigned int*)(0x42C909C0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A17          *((volatile unsigned int*)(0x42C909C4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A18          *((volatile unsigned int*)(0x42C909C8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A19          *((volatile unsigned int*)(0x42C909CCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A20          *((volatile unsigned int*)(0x42C909D0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A21          *((volatile unsigned int*)(0x42C909D4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A22          *((volatile unsigned int*)(0x42C909D8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A23          *((volatile unsigned int*)(0x42C909DCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A24          *((volatile unsigned int*)(0x42C909E0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A25          *((volatile unsigned int*)(0x42C909E4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A26          *((volatile unsigned int*)(0x42C909E8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A27          *((volatile unsigned int*)(0x42C909ECUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A28          *((volatile unsigned int*)(0x42C909F0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A29          *((volatile unsigned int*)(0x42C909F4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A30          *((volatile unsigned int*)(0x42C909F8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A31          *((volatile unsigned int*)(0x42C909FCUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A32          *((volatile unsigned int*)(0x42C90A00UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A33          *((volatile unsigned int*)(0x42C90A04UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A34          *((volatile unsigned int*)(0x42C90A08UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A35          *((volatile unsigned int*)(0x42C90A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A36          *((volatile unsigned int*)(0x42C90A10UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A37          *((volatile unsigned int*)(0x42C90A14UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A38          *((volatile unsigned int*)(0x42C90A18UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A39          *((volatile unsigned int*)(0x42C90A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A40          *((volatile unsigned int*)(0x42C90A20UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A41          *((volatile unsigned int*)(0x42C90A24UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A42          *((volatile unsigned int*)(0x42C90A28UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A43          *((volatile unsigned int*)(0x42C90A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A44          *((volatile unsigned int*)(0x42C90A30UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A45          *((volatile unsigned int*)(0x42C90A34UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A46          *((volatile unsigned int*)(0x42C90A38UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A47          *((volatile unsigned int*)(0x42C90A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC0         *((volatile unsigned int*)(0x42C90A60UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC1         *((volatile unsigned int*)(0x42C90A64UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC2         *((volatile unsigned int*)(0x42C90A68UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC3         *((volatile unsigned int*)(0x42C90A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC4         *((volatile unsigned int*)(0x42C90A70UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC5         *((volatile unsigned int*)(0x42C90A74UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_SA           *((volatile unsigned int*)(0x42C90A78UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_AE           *((volatile unsigned int*)(0x42C90A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A0           *((volatile unsigned int*)(0x42C90A80UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A1           *((volatile unsigned int*)(0x42C90A84UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A2           *((volatile unsigned int*)(0x42C90A88UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A3           *((volatile unsigned int*)(0x42C90A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A4           *((volatile unsigned int*)(0x42C90A90UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A5           *((volatile unsigned int*)(0x42C90A94UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A6           *((volatile unsigned int*)(0x42C90A98UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A7           *((volatile unsigned int*)(0x42C90A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A8           *((volatile unsigned int*)(0x42C90AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A9           *((volatile unsigned int*)(0x42C90AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A10          *((volatile unsigned int*)(0x42C90AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A11          *((volatile unsigned int*)(0x42C90AACUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A12          *((volatile unsigned int*)(0x42C90AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A13          *((volatile unsigned int*)(0x42C90AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A14          *((volatile unsigned int*)(0x42C90AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A15          *((volatile unsigned int*)(0x42C90ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A16          *((volatile unsigned int*)(0x42C90AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A17          *((volatile unsigned int*)(0x42C90AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A18          *((volatile unsigned int*)(0x42C90AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A19          *((volatile unsigned int*)(0x42C90ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A20          *((volatile unsigned int*)(0x42C90AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A21          *((volatile unsigned int*)(0x42C90AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A22          *((volatile unsigned int*)(0x42C90AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A23          *((volatile unsigned int*)(0x42C90ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A24          *((volatile unsigned int*)(0x42C90AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A25          *((volatile unsigned int*)(0x42C90AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A26          *((volatile unsigned int*)(0x42C90AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A27          *((volatile unsigned int*)(0x42C90AECUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A28          *((volatile unsigned int*)(0x42C90AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A29          *((volatile unsigned int*)(0x42C90AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A30          *((volatile unsigned int*)(0x42C90AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A31          *((volatile unsigned int*)(0x42C90AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A32          *((volatile unsigned int*)(0x42C90B00UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A33          *((volatile unsigned int*)(0x42C90B04UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A34          *((volatile unsigned int*)(0x42C90B08UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A35          *((volatile unsigned int*)(0x42C90B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A36          *((volatile unsigned int*)(0x42C90B10UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A37          *((volatile unsigned int*)(0x42C90B14UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A38          *((volatile unsigned int*)(0x42C90B18UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A39          *((volatile unsigned int*)(0x42C90B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A40          *((volatile unsigned int*)(0x42C90B20UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A41          *((volatile unsigned int*)(0x42C90B24UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A42          *((volatile unsigned int*)(0x42C90B28UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A43          *((volatile unsigned int*)(0x42C90B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A44          *((volatile unsigned int*)(0x42C90B30UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A45          *((volatile unsigned int*)(0x42C90B34UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A46          *((volatile unsigned int*)(0x42C90B38UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A47          *((volatile unsigned int*)(0x42C90B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC0         *((volatile unsigned int*)(0x42C90B60UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC1         *((volatile unsigned int*)(0x42C90B64UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC2         *((volatile unsigned int*)(0x42C90B68UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC3         *((volatile unsigned int*)(0x42C90B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC4         *((volatile unsigned int*)(0x42C90B70UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC5         *((volatile unsigned int*)(0x42C90B74UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_SA           *((volatile unsigned int*)(0x42C90B78UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_AE           *((volatile unsigned int*)(0x42C90B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A0           *((volatile unsigned int*)(0x42C90B80UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A1           *((volatile unsigned int*)(0x42C90B84UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A2           *((volatile unsigned int*)(0x42C90B88UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A3           *((volatile unsigned int*)(0x42C90B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A4           *((volatile unsigned int*)(0x42C90B90UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A5           *((volatile unsigned int*)(0x42C90B94UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A6           *((volatile unsigned int*)(0x42C90B98UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A7           *((volatile unsigned int*)(0x42C90B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A8           *((volatile unsigned int*)(0x42C90BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A9           *((volatile unsigned int*)(0x42C90BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A10          *((volatile unsigned int*)(0x42C90BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A11          *((volatile unsigned int*)(0x42C90BACUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A12          *((volatile unsigned int*)(0x42C90BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A13          *((volatile unsigned int*)(0x42C90BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A14          *((volatile unsigned int*)(0x42C90BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A15          *((volatile unsigned int*)(0x42C90BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A16          *((volatile unsigned int*)(0x42C90BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A17          *((volatile unsigned int*)(0x42C90BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A18          *((volatile unsigned int*)(0x42C90BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A19          *((volatile unsigned int*)(0x42C90BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A20          *((volatile unsigned int*)(0x42C90BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A21          *((volatile unsigned int*)(0x42C90BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A22          *((volatile unsigned int*)(0x42C90BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A23          *((volatile unsigned int*)(0x42C90BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A24          *((volatile unsigned int*)(0x42C90BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A25          *((volatile unsigned int*)(0x42C90BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A26          *((volatile unsigned int*)(0x42C90BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A27          *((volatile unsigned int*)(0x42C90BECUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A28          *((volatile unsigned int*)(0x42C90BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A29          *((volatile unsigned int*)(0x42C90BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A30          *((volatile unsigned int*)(0x42C90BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A31          *((volatile unsigned int*)(0x42C90BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A32          *((volatile unsigned int*)(0x42C90C00UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A33          *((volatile unsigned int*)(0x42C90C04UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A34          *((volatile unsigned int*)(0x42C90C08UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A35          *((volatile unsigned int*)(0x42C90C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A36          *((volatile unsigned int*)(0x42C90C10UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A37          *((volatile unsigned int*)(0x42C90C14UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A38          *((volatile unsigned int*)(0x42C90C18UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A39          *((volatile unsigned int*)(0x42C90C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A40          *((volatile unsigned int*)(0x42C90C20UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A41          *((volatile unsigned int*)(0x42C90C24UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A42          *((volatile unsigned int*)(0x42C90C28UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A43          *((volatile unsigned int*)(0x42C90C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A44          *((volatile unsigned int*)(0x42C90C30UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A45          *((volatile unsigned int*)(0x42C90C34UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A46          *((volatile unsigned int*)(0x42C90C38UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A47          *((volatile unsigned int*)(0x42C90C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC0         *((volatile unsigned int*)(0x42C90C60UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC1         *((volatile unsigned int*)(0x42C90C64UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC2         *((volatile unsigned int*)(0x42C90C68UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC3         *((volatile unsigned int*)(0x42C90C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC4         *((volatile unsigned int*)(0x42C90C70UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC5         *((volatile unsigned int*)(0x42C90C74UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_SA           *((volatile unsigned int*)(0x42C90C78UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_AE           *((volatile unsigned int*)(0x42C90C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A0           *((volatile unsigned int*)(0x42C90C80UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A1           *((volatile unsigned int*)(0x42C90C84UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A2           *((volatile unsigned int*)(0x42C90C88UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A3           *((volatile unsigned int*)(0x42C90C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A4           *((volatile unsigned int*)(0x42C90C90UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A5           *((volatile unsigned int*)(0x42C90C94UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A6           *((volatile unsigned int*)(0x42C90C98UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A7           *((volatile unsigned int*)(0x42C90C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A8           *((volatile unsigned int*)(0x42C90CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A9           *((volatile unsigned int*)(0x42C90CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A10          *((volatile unsigned int*)(0x42C90CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A11          *((volatile unsigned int*)(0x42C90CACUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A12          *((volatile unsigned int*)(0x42C90CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A13          *((volatile unsigned int*)(0x42C90CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A14          *((volatile unsigned int*)(0x42C90CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A15          *((volatile unsigned int*)(0x42C90CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A16          *((volatile unsigned int*)(0x42C90CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A17          *((volatile unsigned int*)(0x42C90CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A18          *((volatile unsigned int*)(0x42C90CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A19          *((volatile unsigned int*)(0x42C90CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A20          *((volatile unsigned int*)(0x42C90CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A21          *((volatile unsigned int*)(0x42C90CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A22          *((volatile unsigned int*)(0x42C90CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A23          *((volatile unsigned int*)(0x42C90CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A24          *((volatile unsigned int*)(0x42C90CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A25          *((volatile unsigned int*)(0x42C90CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A26          *((volatile unsigned int*)(0x42C90CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A27          *((volatile unsigned int*)(0x42C90CECUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A28          *((volatile unsigned int*)(0x42C90CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A29          *((volatile unsigned int*)(0x42C90CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A30          *((volatile unsigned int*)(0x42C90CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A31          *((volatile unsigned int*)(0x42C90CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A32          *((volatile unsigned int*)(0x42C90D00UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A33          *((volatile unsigned int*)(0x42C90D04UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A34          *((volatile unsigned int*)(0x42C90D08UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A35          *((volatile unsigned int*)(0x42C90D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A36          *((volatile unsigned int*)(0x42C90D10UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A37          *((volatile unsigned int*)(0x42C90D14UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A38          *((volatile unsigned int*)(0x42C90D18UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A39          *((volatile unsigned int*)(0x42C90D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A40          *((volatile unsigned int*)(0x42C90D20UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A41          *((volatile unsigned int*)(0x42C90D24UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A42          *((volatile unsigned int*)(0x42C90D28UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A43          *((volatile unsigned int*)(0x42C90D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A44          *((volatile unsigned int*)(0x42C90D30UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A45          *((volatile unsigned int*)(0x42C90D34UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A46          *((volatile unsigned int*)(0x42C90D38UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A47          *((volatile unsigned int*)(0x42C90D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC0         *((volatile unsigned int*)(0x42C90D60UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC1         *((volatile unsigned int*)(0x42C90D64UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC2         *((volatile unsigned int*)(0x42C90D68UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC3         *((volatile unsigned int*)(0x42C90D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC4         *((volatile unsigned int*)(0x42C90D70UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC5         *((volatile unsigned int*)(0x42C90D74UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_SA           *((volatile unsigned int*)(0x42C90D78UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_AE           *((volatile unsigned int*)(0x42C90D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A0           *((volatile unsigned int*)(0x42C90D80UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A1           *((volatile unsigned int*)(0x42C90D84UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A2           *((volatile unsigned int*)(0x42C90D88UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A3           *((volatile unsigned int*)(0x42C90D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A4           *((volatile unsigned int*)(0x42C90D90UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A5           *((volatile unsigned int*)(0x42C90D94UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A6           *((volatile unsigned int*)(0x42C90D98UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A7           *((volatile unsigned int*)(0x42C90D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A8           *((volatile unsigned int*)(0x42C90DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A9           *((volatile unsigned int*)(0x42C90DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A10          *((volatile unsigned int*)(0x42C90DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A11          *((volatile unsigned int*)(0x42C90DACUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A12          *((volatile unsigned int*)(0x42C90DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A13          *((volatile unsigned int*)(0x42C90DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A14          *((volatile unsigned int*)(0x42C90DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A15          *((volatile unsigned int*)(0x42C90DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A16          *((volatile unsigned int*)(0x42C90DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A17          *((volatile unsigned int*)(0x42C90DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A18          *((volatile unsigned int*)(0x42C90DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A19          *((volatile unsigned int*)(0x42C90DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A20          *((volatile unsigned int*)(0x42C90DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A21          *((volatile unsigned int*)(0x42C90DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A22          *((volatile unsigned int*)(0x42C90DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A23          *((volatile unsigned int*)(0x42C90DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A24          *((volatile unsigned int*)(0x42C90DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A25          *((volatile unsigned int*)(0x42C90DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A26          *((volatile unsigned int*)(0x42C90DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A27          *((volatile unsigned int*)(0x42C90DECUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A28          *((volatile unsigned int*)(0x42C90DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A29          *((volatile unsigned int*)(0x42C90DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A30          *((volatile unsigned int*)(0x42C90DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A31          *((volatile unsigned int*)(0x42C90DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A32          *((volatile unsigned int*)(0x42C90E00UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A33          *((volatile unsigned int*)(0x42C90E04UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A34          *((volatile unsigned int*)(0x42C90E08UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A35          *((volatile unsigned int*)(0x42C90E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A36          *((volatile unsigned int*)(0x42C90E10UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A37          *((volatile unsigned int*)(0x42C90E14UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A38          *((volatile unsigned int*)(0x42C90E18UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A39          *((volatile unsigned int*)(0x42C90E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A40          *((volatile unsigned int*)(0x42C90E20UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A41          *((volatile unsigned int*)(0x42C90E24UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A42          *((volatile unsigned int*)(0x42C90E28UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A43          *((volatile unsigned int*)(0x42C90E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A44          *((volatile unsigned int*)(0x42C90E30UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A45          *((volatile unsigned int*)(0x42C90E34UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A46          *((volatile unsigned int*)(0x42C90E38UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A47          *((volatile unsigned int*)(0x42C90E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC0         *((volatile unsigned int*)(0x42C90E60UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC1         *((volatile unsigned int*)(0x42C90E64UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC2         *((volatile unsigned int*)(0x42C90E68UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC3         *((volatile unsigned int*)(0x42C90E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC4         *((volatile unsigned int*)(0x42C90E70UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC5         *((volatile unsigned int*)(0x42C90E74UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_SA           *((volatile unsigned int*)(0x42C90E78UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_AE           *((volatile unsigned int*)(0x42C90E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A0           *((volatile unsigned int*)(0x42C90E80UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A1           *((volatile unsigned int*)(0x42C90E84UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A2           *((volatile unsigned int*)(0x42C90E88UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A3           *((volatile unsigned int*)(0x42C90E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A4           *((volatile unsigned int*)(0x42C90E90UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A5           *((volatile unsigned int*)(0x42C90E94UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A6           *((volatile unsigned int*)(0x42C90E98UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A7           *((volatile unsigned int*)(0x42C90E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A8           *((volatile unsigned int*)(0x42C90EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A9           *((volatile unsigned int*)(0x42C90EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A10          *((volatile unsigned int*)(0x42C90EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A11          *((volatile unsigned int*)(0x42C90EACUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A12          *((volatile unsigned int*)(0x42C90EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A13          *((volatile unsigned int*)(0x42C90EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A14          *((volatile unsigned int*)(0x42C90EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A15          *((volatile unsigned int*)(0x42C90EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A16          *((volatile unsigned int*)(0x42C90EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A17          *((volatile unsigned int*)(0x42C90EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A18          *((volatile unsigned int*)(0x42C90EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A19          *((volatile unsigned int*)(0x42C90ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A20          *((volatile unsigned int*)(0x42C90ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A21          *((volatile unsigned int*)(0x42C90ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A22          *((volatile unsigned int*)(0x42C90ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A23          *((volatile unsigned int*)(0x42C90EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A24          *((volatile unsigned int*)(0x42C90EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A25          *((volatile unsigned int*)(0x42C90EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A26          *((volatile unsigned int*)(0x42C90EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A27          *((volatile unsigned int*)(0x42C90EECUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A28          *((volatile unsigned int*)(0x42C90EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A29          *((volatile unsigned int*)(0x42C90EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A30          *((volatile unsigned int*)(0x42C90EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A31          *((volatile unsigned int*)(0x42C90EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A32          *((volatile unsigned int*)(0x42C90F00UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A33          *((volatile unsigned int*)(0x42C90F04UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A34          *((volatile unsigned int*)(0x42C90F08UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A35          *((volatile unsigned int*)(0x42C90F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A36          *((volatile unsigned int*)(0x42C90F10UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A37          *((volatile unsigned int*)(0x42C90F14UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A38          *((volatile unsigned int*)(0x42C90F18UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A39          *((volatile unsigned int*)(0x42C90F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A40          *((volatile unsigned int*)(0x42C90F20UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A41          *((volatile unsigned int*)(0x42C90F24UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A42          *((volatile unsigned int*)(0x42C90F28UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A43          *((volatile unsigned int*)(0x42C90F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A44          *((volatile unsigned int*)(0x42C90F30UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A45          *((volatile unsigned int*)(0x42C90F34UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A46          *((volatile unsigned int*)(0x42C90F38UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A47          *((volatile unsigned int*)(0x42C90F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC0         *((volatile unsigned int*)(0x42C90F60UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC1         *((volatile unsigned int*)(0x42C90F64UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC2         *((volatile unsigned int*)(0x42C90F68UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC3         *((volatile unsigned int*)(0x42C90F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC4         *((volatile unsigned int*)(0x42C90F70UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC5         *((volatile unsigned int*)(0x42C90F74UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_SA           *((volatile unsigned int*)(0x42C90F78UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_AE           *((volatile unsigned int*)(0x42C90F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A0           *((volatile unsigned int*)(0x42C90F80UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A1           *((volatile unsigned int*)(0x42C90F84UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A2           *((volatile unsigned int*)(0x42C90F88UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A3           *((volatile unsigned int*)(0x42C90F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A4           *((volatile unsigned int*)(0x42C90F90UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A5           *((volatile unsigned int*)(0x42C90F94UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A6           *((volatile unsigned int*)(0x42C90F98UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A7           *((volatile unsigned int*)(0x42C90F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A8           *((volatile unsigned int*)(0x42C90FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A9           *((volatile unsigned int*)(0x42C90FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A10          *((volatile unsigned int*)(0x42C90FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A11          *((volatile unsigned int*)(0x42C90FACUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A12          *((volatile unsigned int*)(0x42C90FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A13          *((volatile unsigned int*)(0x42C90FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A14          *((volatile unsigned int*)(0x42C90FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A15          *((volatile unsigned int*)(0x42C90FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A16          *((volatile unsigned int*)(0x42C90FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A17          *((volatile unsigned int*)(0x42C90FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A18          *((volatile unsigned int*)(0x42C90FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A19          *((volatile unsigned int*)(0x42C90FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A20          *((volatile unsigned int*)(0x42C90FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A21          *((volatile unsigned int*)(0x42C90FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A22          *((volatile unsigned int*)(0x42C90FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A23          *((volatile unsigned int*)(0x42C90FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A24          *((volatile unsigned int*)(0x42C90FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A25          *((volatile unsigned int*)(0x42C90FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A26          *((volatile unsigned int*)(0x42C90FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A27          *((volatile unsigned int*)(0x42C90FECUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A28          *((volatile unsigned int*)(0x42C90FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A29          *((volatile unsigned int*)(0x42C90FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A30          *((volatile unsigned int*)(0x42C90FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A31          *((volatile unsigned int*)(0x42C90FFCUL))
+#define bFM3_ETHERNET_MAC0_BMR_SWR             *((volatile unsigned int*)(0x42CA0000UL))
+#define bFM3_ETHERNET_MAC0_BMR_DA              *((volatile unsigned int*)(0x42CA0004UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL0            *((volatile unsigned int*)(0x42CA0008UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL1            *((volatile unsigned int*)(0x42CA000CUL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL2            *((volatile unsigned int*)(0x42CA0010UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL3            *((volatile unsigned int*)(0x42CA0014UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL4            *((volatile unsigned int*)(0x42CA0018UL))
+#define bFM3_ETHERNET_MAC0_BMR_ATDS            *((volatile unsigned int*)(0x42CA001CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL0            *((volatile unsigned int*)(0x42CA0020UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL1            *((volatile unsigned int*)(0x42CA0024UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL2            *((volatile unsigned int*)(0x42CA0028UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL3            *((volatile unsigned int*)(0x42CA002CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL4            *((volatile unsigned int*)(0x42CA0030UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL5            *((volatile unsigned int*)(0x42CA0034UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR0             *((volatile unsigned int*)(0x42CA0038UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR1             *((volatile unsigned int*)(0x42CA003CUL))
+#define bFM3_ETHERNET_MAC0_BMR_FB              *((volatile unsigned int*)(0x42CA0040UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL0           *((volatile unsigned int*)(0x42CA0044UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL1           *((volatile unsigned int*)(0x42CA0048UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL2           *((volatile unsigned int*)(0x42CA004CUL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL3           *((volatile unsigned int*)(0x42CA0050UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL4           *((volatile unsigned int*)(0x42CA0054UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL5           *((volatile unsigned int*)(0x42CA0058UL))
+#define bFM3_ETHERNET_MAC0_BMR_USP             *((volatile unsigned int*)(0x42CA005CUL))
+#define bFM3_ETHERNET_MAC0_BMR_8XPBL           *((volatile unsigned int*)(0x42CA0060UL))
+#define bFM3_ETHERNET_MAC0_BMR_AAL             *((volatile unsigned int*)(0x42CA0064UL))
+#define bFM3_ETHERNET_MAC0_BMR_MB              *((volatile unsigned int*)(0x42CA0068UL))
+#define bFM3_ETHERNET_MAC0_BMR_TXPR            *((volatile unsigned int*)(0x42CA006CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD0           *((volatile unsigned int*)(0x42CA0080UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD1           *((volatile unsigned int*)(0x42CA0084UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD2           *((volatile unsigned int*)(0x42CA0088UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD3           *((volatile unsigned int*)(0x42CA008CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD4           *((volatile unsigned int*)(0x42CA0090UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD5           *((volatile unsigned int*)(0x42CA0094UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD6           *((volatile unsigned int*)(0x42CA0098UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD7           *((volatile unsigned int*)(0x42CA009CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD8           *((volatile unsigned int*)(0x42CA00A0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD9           *((volatile unsigned int*)(0x42CA00A4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD10          *((volatile unsigned int*)(0x42CA00A8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD11          *((volatile unsigned int*)(0x42CA00ACUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD12          *((volatile unsigned int*)(0x42CA00B0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD13          *((volatile unsigned int*)(0x42CA00B4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD14          *((volatile unsigned int*)(0x42CA00B8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD15          *((volatile unsigned int*)(0x42CA00BCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD16          *((volatile unsigned int*)(0x42CA00C0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD17          *((volatile unsigned int*)(0x42CA00C4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD18          *((volatile unsigned int*)(0x42CA00C8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD19          *((volatile unsigned int*)(0x42CA00CCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD20          *((volatile unsigned int*)(0x42CA00D0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD21          *((volatile unsigned int*)(0x42CA00D4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD22          *((volatile unsigned int*)(0x42CA00D8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD23          *((volatile unsigned int*)(0x42CA00DCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD24          *((volatile unsigned int*)(0x42CA00E0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD25          *((volatile unsigned int*)(0x42CA00E4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD26          *((volatile unsigned int*)(0x42CA00E8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD27          *((volatile unsigned int*)(0x42CA00ECUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD28          *((volatile unsigned int*)(0x42CA00F0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD29          *((volatile unsigned int*)(0x42CA00F4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD30          *((volatile unsigned int*)(0x42CA00F8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD31          *((volatile unsigned int*)(0x42CA00FCUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD0           *((volatile unsigned int*)(0x42CA0100UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD1           *((volatile unsigned int*)(0x42CA0104UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD2           *((volatile unsigned int*)(0x42CA0108UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD3           *((volatile unsigned int*)(0x42CA010CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD4           *((volatile unsigned int*)(0x42CA0110UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD5           *((volatile unsigned int*)(0x42CA0114UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD6           *((volatile unsigned int*)(0x42CA0118UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD7           *((volatile unsigned int*)(0x42CA011CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD8           *((volatile unsigned int*)(0x42CA0120UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD9           *((volatile unsigned int*)(0x42CA0124UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD10          *((volatile unsigned int*)(0x42CA0128UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD11          *((volatile unsigned int*)(0x42CA012CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD12          *((volatile unsigned int*)(0x42CA0130UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD13          *((volatile unsigned int*)(0x42CA0134UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD14          *((volatile unsigned int*)(0x42CA0138UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD15          *((volatile unsigned int*)(0x42CA013CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD16          *((volatile unsigned int*)(0x42CA0140UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD17          *((volatile unsigned int*)(0x42CA0144UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD18          *((volatile unsigned int*)(0x42CA0148UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD19          *((volatile unsigned int*)(0x42CA014CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD20          *((volatile unsigned int*)(0x42CA0150UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD21          *((volatile unsigned int*)(0x42CA0154UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD22          *((volatile unsigned int*)(0x42CA0158UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD23          *((volatile unsigned int*)(0x42CA015CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD24          *((volatile unsigned int*)(0x42CA0160UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD25          *((volatile unsigned int*)(0x42CA0164UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD26          *((volatile unsigned int*)(0x42CA0168UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD27          *((volatile unsigned int*)(0x42CA016CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD28          *((volatile unsigned int*)(0x42CA0170UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD29          *((volatile unsigned int*)(0x42CA0174UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD30          *((volatile unsigned int*)(0x42CA0178UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD31          *((volatile unsigned int*)(0x42CA017CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL2          *((volatile unsigned int*)(0x42CA0188UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL3          *((volatile unsigned int*)(0x42CA018CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL4          *((volatile unsigned int*)(0x42CA0190UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL5          *((volatile unsigned int*)(0x42CA0194UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL6          *((volatile unsigned int*)(0x42CA0198UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL7          *((volatile unsigned int*)(0x42CA019CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL8          *((volatile unsigned int*)(0x42CA01A0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL9          *((volatile unsigned int*)(0x42CA01A4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL10         *((volatile unsigned int*)(0x42CA01A8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL11         *((volatile unsigned int*)(0x42CA01ACUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL12         *((volatile unsigned int*)(0x42CA01B0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL13         *((volatile unsigned int*)(0x42CA01B4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL14         *((volatile unsigned int*)(0x42CA01B8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL15         *((volatile unsigned int*)(0x42CA01BCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL16         *((volatile unsigned int*)(0x42CA01C0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL17         *((volatile unsigned int*)(0x42CA01C4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL18         *((volatile unsigned int*)(0x42CA01C8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL19         *((volatile unsigned int*)(0x42CA01CCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL20         *((volatile unsigned int*)(0x42CA01D0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL21         *((volatile unsigned int*)(0x42CA01D4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL22         *((volatile unsigned int*)(0x42CA01D8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL23         *((volatile unsigned int*)(0x42CA01DCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL24         *((volatile unsigned int*)(0x42CA01E0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL25         *((volatile unsigned int*)(0x42CA01E4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL26         *((volatile unsigned int*)(0x42CA01E8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL27         *((volatile unsigned int*)(0x42CA01ECUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL28         *((volatile unsigned int*)(0x42CA01F0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL29         *((volatile unsigned int*)(0x42CA01F4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL30         *((volatile unsigned int*)(0x42CA01F8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL31         *((volatile unsigned int*)(0x42CA01FCUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL2          *((volatile unsigned int*)(0x42CA0208UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL3          *((volatile unsigned int*)(0x42CA020CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL4          *((volatile unsigned int*)(0x42CA0210UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL5          *((volatile unsigned int*)(0x42CA0214UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL6          *((volatile unsigned int*)(0x42CA0218UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL7          *((volatile unsigned int*)(0x42CA021CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL8          *((volatile unsigned int*)(0x42CA0220UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL9          *((volatile unsigned int*)(0x42CA0224UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL10         *((volatile unsigned int*)(0x42CA0228UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL11         *((volatile unsigned int*)(0x42CA022CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL12         *((volatile unsigned int*)(0x42CA0230UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL13         *((volatile unsigned int*)(0x42CA0234UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL14         *((volatile unsigned int*)(0x42CA0238UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL15         *((volatile unsigned int*)(0x42CA023CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL16         *((volatile unsigned int*)(0x42CA0240UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL17         *((volatile unsigned int*)(0x42CA0244UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL18         *((volatile unsigned int*)(0x42CA0248UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL19         *((volatile unsigned int*)(0x42CA024CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL20         *((volatile unsigned int*)(0x42CA0250UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL21         *((volatile unsigned int*)(0x42CA0254UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL22         *((volatile unsigned int*)(0x42CA0258UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL23         *((volatile unsigned int*)(0x42CA025CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL24         *((volatile unsigned int*)(0x42CA0260UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL25         *((volatile unsigned int*)(0x42CA0264UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL26         *((volatile unsigned int*)(0x42CA0268UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL27         *((volatile unsigned int*)(0x42CA026CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL28         *((volatile unsigned int*)(0x42CA0270UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL29         *((volatile unsigned int*)(0x42CA0274UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL30         *((volatile unsigned int*)(0x42CA0278UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL31         *((volatile unsigned int*)(0x42CA027CUL))
+#define bFM3_ETHERNET_MAC0_SR_TI               *((volatile unsigned int*)(0x42CA0280UL))
+#define bFM3_ETHERNET_MAC0_SR_TPS              *((volatile unsigned int*)(0x42CA0284UL))
+#define bFM3_ETHERNET_MAC0_SR_TU               *((volatile unsigned int*)(0x42CA0288UL))
+#define bFM3_ETHERNET_MAC0_SR_TJT              *((volatile unsigned int*)(0x42CA028CUL))
+#define bFM3_ETHERNET_MAC0_SR_OVF              *((volatile unsigned int*)(0x42CA0290UL))
+#define bFM3_ETHERNET_MAC0_SR_UNF              *((volatile unsigned int*)(0x42CA0294UL))
+#define bFM3_ETHERNET_MAC0_SR_RI               *((volatile unsigned int*)(0x42CA0298UL))
+#define bFM3_ETHERNET_MAC0_SR_RU               *((volatile unsigned int*)(0x42CA029CUL))
+#define bFM3_ETHERNET_MAC0_SR_RPS              *((volatile unsigned int*)(0x42CA02A0UL))
+#define bFM3_ETHERNET_MAC0_SR_RWT              *((volatile unsigned int*)(0x42CA02A4UL))
+#define bFM3_ETHERNET_MAC0_SR_ETI              *((volatile unsigned int*)(0x42CA02A8UL))
+#define bFM3_ETHERNET_MAC0_SR_FBI              *((volatile unsigned int*)(0x42CA02B4UL))
+#define bFM3_ETHERNET_MAC0_SR_ERI              *((volatile unsigned int*)(0x42CA02B8UL))
+#define bFM3_ETHERNET_MAC0_SR_AIS              *((volatile unsigned int*)(0x42CA02BCUL))
+#define bFM3_ETHERNET_MAC0_SR_NIS              *((volatile unsigned int*)(0x42CA02C0UL))
+#define bFM3_ETHERNET_MAC0_SR_RS0              *((volatile unsigned int*)(0x42CA02C4UL))
+#define bFM3_ETHERNET_MAC0_SR_RS1              *((volatile unsigned int*)(0x42CA02C8UL))
+#define bFM3_ETHERNET_MAC0_SR_RS2              *((volatile unsigned int*)(0x42CA02CCUL))
+#define bFM3_ETHERNET_MAC0_SR_TS0              *((volatile unsigned int*)(0x42CA02D0UL))
+#define bFM3_ETHERNET_MAC0_SR_TS1              *((volatile unsigned int*)(0x42CA02D4UL))
+#define bFM3_ETHERNET_MAC0_SR_TS2              *((volatile unsigned int*)(0x42CA02D8UL))
+#define bFM3_ETHERNET_MAC0_SR_EB0              *((volatile unsigned int*)(0x42CA02DCUL))
+#define bFM3_ETHERNET_MAC0_SR_EB1              *((volatile unsigned int*)(0x42CA02E0UL))
+#define bFM3_ETHERNET_MAC0_SR_EB2              *((volatile unsigned int*)(0x42CA02E4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLI              *((volatile unsigned int*)(0x42CA02E8UL))
+#define bFM3_ETHERNET_MAC0_SR_GMI              *((volatile unsigned int*)(0x42CA02ECUL))
+#define bFM3_ETHERNET_MAC0_SR_GPI              *((volatile unsigned int*)(0x42CA02F0UL))
+#define bFM3_ETHERNET_MAC0_SR_TTI              *((volatile unsigned int*)(0x42CA02F4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLPII            *((volatile unsigned int*)(0x42CA02F8UL))
+#define bFM3_ETHERNET_MAC0_OMR_SR              *((volatile unsigned int*)(0x42CA0304UL))
+#define bFM3_ETHERNET_MAC0_OMR_OSF             *((volatile unsigned int*)(0x42CA0308UL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC0            *((volatile unsigned int*)(0x42CA030CUL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC1            *((volatile unsigned int*)(0x42CA0310UL))
+#define bFM3_ETHERNET_MAC0_OMR_FUF             *((volatile unsigned int*)(0x42CA0318UL))
+#define bFM3_ETHERNET_MAC0_OMR_FEF             *((volatile unsigned int*)(0x42CA031CUL))
+#define bFM3_ETHERNET_MAC0_OMR_ST              *((volatile unsigned int*)(0x42CA0334UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC0            *((volatile unsigned int*)(0x42CA0338UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC1            *((volatile unsigned int*)(0x42CA033CUL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC2            *((volatile unsigned int*)(0x42CA0340UL))
+#define bFM3_ETHERNET_MAC0_OMR_FTF             *((volatile unsigned int*)(0x42CA0350UL))
+#define bFM3_ETHERNET_MAC0_OMR_TSF             *((volatile unsigned int*)(0x42CA0354UL))
+#define bFM3_ETHERNET_MAC0_OMR_DFF             *((volatile unsigned int*)(0x42CA0360UL))
+#define bFM3_ETHERNET_MAC0_OMR_RSF             *((volatile unsigned int*)(0x42CA0364UL))
+#define bFM3_ETHERNET_MAC0_OMR_DT              *((volatile unsigned int*)(0x42CA0368UL))
+#define bFM3_ETHERNET_MAC0_IER_TIE             *((volatile unsigned int*)(0x42CA0380UL))
+#define bFM3_ETHERNET_MAC0_IER_TSE             *((volatile unsigned int*)(0x42CA0384UL))
+#define bFM3_ETHERNET_MAC0_IER_TUE             *((volatile unsigned int*)(0x42CA0388UL))
+#define bFM3_ETHERNET_MAC0_IER_TJE             *((volatile unsigned int*)(0x42CA038CUL))
+#define bFM3_ETHERNET_MAC0_IER_OVE             *((volatile unsigned int*)(0x42CA0390UL))
+#define bFM3_ETHERNET_MAC0_IER_UNE             *((volatile unsigned int*)(0x42CA0394UL))
+#define bFM3_ETHERNET_MAC0_IER_RIE             *((volatile unsigned int*)(0x42CA0398UL))
+#define bFM3_ETHERNET_MAC0_IER_RUE             *((volatile unsigned int*)(0x42CA039CUL))
+#define bFM3_ETHERNET_MAC0_IER_RSE             *((volatile unsigned int*)(0x42CA03A0UL))
+#define bFM3_ETHERNET_MAC0_IER_RWE             *((volatile unsigned int*)(0x42CA03A4UL))
+#define bFM3_ETHERNET_MAC0_IER_ETE             *((volatile unsigned int*)(0x42CA03A8UL))
+#define bFM3_ETHERNET_MAC0_IER_FBE             *((volatile unsigned int*)(0x42CA03B4UL))
+#define bFM3_ETHERNET_MAC0_IER_ERE             *((volatile unsigned int*)(0x42CA03B8UL))
+#define bFM3_ETHERNET_MAC0_IER_AIE             *((volatile unsigned int*)(0x42CA03BCUL))
+#define bFM3_ETHERNET_MAC0_IER_NIE             *((volatile unsigned int*)(0x42CA03C0UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42CA0400UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42CA0404UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42CA0408UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42CA040CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42CA0410UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42CA0414UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42CA0418UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42CA041CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42CA0420UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42CA0424UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42CA0428UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42CA042CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42CA0430UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42CA0434UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42CA0438UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42CA043CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42CA0440UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42CA0444UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42CA0448UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42CA044CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42CA0450UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42CA0454UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42CA0458UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42CA045CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42CA0460UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42CA0464UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42CA0468UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42CA046CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42CA0470UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0         *((volatile unsigned int*)(0x42CA0480UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1         *((volatile unsigned int*)(0x42CA0484UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2         *((volatile unsigned int*)(0x42CA0488UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3         *((volatile unsigned int*)(0x42CA048CUL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4         *((volatile unsigned int*)(0x42CA0490UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5         *((volatile unsigned int*)(0x42CA0494UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6         *((volatile unsigned int*)(0x42CA0498UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7         *((volatile unsigned int*)(0x42CA049CUL))
+#define bFM3_ETHERNET_MAC0_AHBSR_AHBS          *((volatile unsigned int*)(0x42CA0580UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42CA0900UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42CA0904UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42CA0908UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42CA090CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42CA0910UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42CA0914UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42CA0918UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42CA091CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42CA0920UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42CA0924UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42CA0928UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42CA092CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42CA0930UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42CA0934UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42CA0938UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42CA093CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42CA0940UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42CA0944UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42CA0948UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42CA094CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42CA0950UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42CA0954UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42CA0958UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42CA095CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42CA0960UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42CA0964UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42CA0968UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42CA096CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42CA0970UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42CA0974UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42CA0978UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42CA097CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42CA0980UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42CA0984UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42CA0988UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42CA098CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42CA0990UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42CA0994UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42CA0998UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42CA099CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42CA09A0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42CA09A4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42CA09A8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42CA09ACUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42CA09B0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42CA09B4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42CA09B8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42CA09BCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42CA09C0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42CA09C4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42CA09C8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42CA09CCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42CA09D0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42CA09D4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42CA09D8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42CA09DCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42CA09E0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42CA09E4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42CA09E8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42CA09ECUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42CA09F0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42CA09F4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42CA09F8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42CA09FCUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42CA0A00UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42CA0A04UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42CA0A08UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42CA0A0CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42CA0A10UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42CA0A14UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42CA0A18UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42CA0A1CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42CA0A20UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42CA0A24UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42CA0A28UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42CA0A2CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42CA0A30UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42CA0A34UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42CA0A38UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42CA0A3CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42CA0A40UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42CA0A44UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42CA0A48UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42CA0A4CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42CA0A50UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42CA0A54UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42CA0A58UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42CA0A5CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42CA0A60UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42CA0A64UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42CA0A68UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42CA0A6CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42CA0A70UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42CA0A74UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42CA0A78UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42CA0A7CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42CA0A80UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42CA0A84UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42CA0A88UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42CA0A8CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42CA0A90UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42CA0A94UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42CA0A98UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42CA0A9CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42CA0AA0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42CA0AA4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42CA0AA8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42CA0AACUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42CA0AB0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42CA0AB4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42CA0AB8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42CA0ABCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42CA0AC0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42CA0AC4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42CA0AC8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42CA0ACCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42CA0AD0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42CA0AD4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42CA0AD8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42CA0ADCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42CA0AE0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42CA0AE4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42CA0AE8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42CA0AECUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42CA0AF0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42CA0AF4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42CA0AF8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42CA0AFCUL))
+
+/* ETHERNET-MAC-CONTROL registers */
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE  *((volatile unsigned int*)(0x42CC0000UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0    *((volatile unsigned int*)(0x42CC0020UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1    *((volatile unsigned int*)(0x42CC0024UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL  *((volatile unsigned int*)(0x42CC0070UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0  *((volatile unsigned int*)(0x42CC0100UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1  *((volatile unsigned int*)(0x42CC0104UL))
+
+/* ETHERNET-MAC1 registers*/
+#define bFM3_ETHERNET_MAC1_MCR_RE              *((volatile unsigned int*)(0x42CE0008UL))
+#define bFM3_ETHERNET_MAC1_MCR_TE              *((volatile unsigned int*)(0x42CE000CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DC              *((volatile unsigned int*)(0x42CE0010UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL0             *((volatile unsigned int*)(0x42CE0014UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL1             *((volatile unsigned int*)(0x42CE0018UL))
+#define bFM3_ETHERNET_MAC1_MCR_ACS             *((volatile unsigned int*)(0x42CE001CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LUD             *((volatile unsigned int*)(0x42CE0020UL))
+#define bFM3_ETHERNET_MAC1_MCR_DR              *((volatile unsigned int*)(0x42CE0024UL))
+#define bFM3_ETHERNET_MAC1_MCR_IPC             *((volatile unsigned int*)(0x42CE0028UL))
+#define bFM3_ETHERNET_MAC1_MCR_DM              *((volatile unsigned int*)(0x42CE002CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LM              *((volatile unsigned int*)(0x42CE0030UL))
+#define bFM3_ETHERNET_MAC1_MCR_DO              *((volatile unsigned int*)(0x42CE0034UL))
+#define bFM3_ETHERNET_MAC1_MCR_FES             *((volatile unsigned int*)(0x42CE0038UL))
+#define bFM3_ETHERNET_MAC1_MCR_PS              *((volatile unsigned int*)(0x42CE003CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DCRS            *((volatile unsigned int*)(0x42CE0040UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG0            *((volatile unsigned int*)(0x42CE0044UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG1            *((volatile unsigned int*)(0x42CE0048UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG2            *((volatile unsigned int*)(0x42CE004CUL))
+#define bFM3_ETHERNET_MAC1_MCR_JE              *((volatile unsigned int*)(0x42CE0050UL))
+#define bFM3_ETHERNET_MAC1_MCR_BE              *((volatile unsigned int*)(0x42CE0054UL))
+#define bFM3_ETHERNET_MAC1_MCR_JD              *((volatile unsigned int*)(0x42CE0058UL))
+#define bFM3_ETHERNET_MAC1_MCR_WD              *((volatile unsigned int*)(0x42CE005CUL))
+#define bFM3_ETHERNET_MAC1_MCR_TC              *((volatile unsigned int*)(0x42CE0060UL))
+#define bFM3_ETHERNET_MAC1_MCR_CST             *((volatile unsigned int*)(0x42CE0064UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PR             *((volatile unsigned int*)(0x42CE0080UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HUC            *((volatile unsigned int*)(0x42CE0084UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HMC            *((volatile unsigned int*)(0x42CE0088UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DAIF           *((volatile unsigned int*)(0x42CE008CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_PM             *((volatile unsigned int*)(0x42CE0090UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DB             *((volatile unsigned int*)(0x42CE0094UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF0           *((volatile unsigned int*)(0x42CE0098UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF1           *((volatile unsigned int*)(0x42CE009CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAIF           *((volatile unsigned int*)(0x42CE00A0UL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAF            *((volatile unsigned int*)(0x42CE00A4UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HPF            *((volatile unsigned int*)(0x42CE00A8UL))
+#define bFM3_ETHERNET_MAC1_MFFR_RA             *((volatile unsigned int*)(0x42CE00FCUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH0          *((volatile unsigned int*)(0x42CE0100UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH1          *((volatile unsigned int*)(0x42CE0104UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH2          *((volatile unsigned int*)(0x42CE0108UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH3          *((volatile unsigned int*)(0x42CE010CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH4          *((volatile unsigned int*)(0x42CE0110UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH5          *((volatile unsigned int*)(0x42CE0114UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH6          *((volatile unsigned int*)(0x42CE0118UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH7          *((volatile unsigned int*)(0x42CE011CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH8          *((volatile unsigned int*)(0x42CE0120UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH9          *((volatile unsigned int*)(0x42CE0124UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH10         *((volatile unsigned int*)(0x42CE0128UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH11         *((volatile unsigned int*)(0x42CE012CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH12         *((volatile unsigned int*)(0x42CE0130UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH13         *((volatile unsigned int*)(0x42CE0134UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH14         *((volatile unsigned int*)(0x42CE0138UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH15         *((volatile unsigned int*)(0x42CE013CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH16         *((volatile unsigned int*)(0x42CE0140UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH17         *((volatile unsigned int*)(0x42CE0144UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH18         *((volatile unsigned int*)(0x42CE0148UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH19         *((volatile unsigned int*)(0x42CE014CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH20         *((volatile unsigned int*)(0x42CE0150UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH21         *((volatile unsigned int*)(0x42CE0154UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH22         *((volatile unsigned int*)(0x42CE0158UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH23         *((volatile unsigned int*)(0x42CE015CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH24         *((volatile unsigned int*)(0x42CE0160UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH25         *((volatile unsigned int*)(0x42CE0164UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH26         *((volatile unsigned int*)(0x42CE0168UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH27         *((volatile unsigned int*)(0x42CE016CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH28         *((volatile unsigned int*)(0x42CE0170UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH29         *((volatile unsigned int*)(0x42CE0174UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH30         *((volatile unsigned int*)(0x42CE0178UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH31         *((volatile unsigned int*)(0x42CE017CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL0          *((volatile unsigned int*)(0x42CE0180UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL1          *((volatile unsigned int*)(0x42CE0184UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL2          *((volatile unsigned int*)(0x42CE0188UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL3          *((volatile unsigned int*)(0x42CE018CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL4          *((volatile unsigned int*)(0x42CE0190UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL5          *((volatile unsigned int*)(0x42CE0194UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL6          *((volatile unsigned int*)(0x42CE0198UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL7          *((volatile unsigned int*)(0x42CE019CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL8          *((volatile unsigned int*)(0x42CE01A0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL9          *((volatile unsigned int*)(0x42CE01A4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL10         *((volatile unsigned int*)(0x42CE01A8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL11         *((volatile unsigned int*)(0x42CE01ACUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL12         *((volatile unsigned int*)(0x42CE01B0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL13         *((volatile unsigned int*)(0x42CE01B4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL14         *((volatile unsigned int*)(0x42CE01B8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL15         *((volatile unsigned int*)(0x42CE01BCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL16         *((volatile unsigned int*)(0x42CE01C0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL17         *((volatile unsigned int*)(0x42CE01C4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL18         *((volatile unsigned int*)(0x42CE01C8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL19         *((volatile unsigned int*)(0x42CE01CCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL20         *((volatile unsigned int*)(0x42CE01D0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL21         *((volatile unsigned int*)(0x42CE01D4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL22         *((volatile unsigned int*)(0x42CE01D8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL23         *((volatile unsigned int*)(0x42CE01DCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL24         *((volatile unsigned int*)(0x42CE01E0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL25         *((volatile unsigned int*)(0x42CE01E4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL26         *((volatile unsigned int*)(0x42CE01E8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL27         *((volatile unsigned int*)(0x42CE01ECUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL28         *((volatile unsigned int*)(0x42CE01F0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL29         *((volatile unsigned int*)(0x42CE01F4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL30         *((volatile unsigned int*)(0x42CE01F8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL31         *((volatile unsigned int*)(0x42CE01FCUL))
+#define bFM3_ETHERNET_MAC1_GAR_GB              *((volatile unsigned int*)(0x42CE0200UL))
+#define bFM3_ETHERNET_MAC1_GAR_GW              *((volatile unsigned int*)(0x42CE0204UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR0             *((volatile unsigned int*)(0x42CE0208UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR1             *((volatile unsigned int*)(0x42CE020CUL))
+#define bFM3_ETHERNET_MAC1_GAR_CR2             *((volatile unsigned int*)(0x42CE0210UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR3             *((volatile unsigned int*)(0x42CE0214UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR0             *((volatile unsigned int*)(0x42CE0218UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR1             *((volatile unsigned int*)(0x42CE021CUL))
+#define bFM3_ETHERNET_MAC1_GAR_GR2             *((volatile unsigned int*)(0x42CE0220UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR3             *((volatile unsigned int*)(0x42CE0224UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR4             *((volatile unsigned int*)(0x42CE0228UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA0             *((volatile unsigned int*)(0x42CE022CUL))
+#define bFM3_ETHERNET_MAC1_GAR_PA1             *((volatile unsigned int*)(0x42CE0230UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA2             *((volatile unsigned int*)(0x42CE0234UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA3             *((volatile unsigned int*)(0x42CE0238UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA4             *((volatile unsigned int*)(0x42CE023CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD0             *((volatile unsigned int*)(0x42CE0280UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD1             *((volatile unsigned int*)(0x42CE0284UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD2             *((volatile unsigned int*)(0x42CE0288UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD3             *((volatile unsigned int*)(0x42CE028CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD4             *((volatile unsigned int*)(0x42CE0290UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD5             *((volatile unsigned int*)(0x42CE0294UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD6             *((volatile unsigned int*)(0x42CE0298UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD7             *((volatile unsigned int*)(0x42CE029CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD8             *((volatile unsigned int*)(0x42CE02A0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD9             *((volatile unsigned int*)(0x42CE02A4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD10            *((volatile unsigned int*)(0x42CE02A8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD11            *((volatile unsigned int*)(0x42CE02ACUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD12            *((volatile unsigned int*)(0x42CE02B0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD13            *((volatile unsigned int*)(0x42CE02B4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD14            *((volatile unsigned int*)(0x42CE02B8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD15            *((volatile unsigned int*)(0x42CE02BCUL))
+#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA         *((volatile unsigned int*)(0x42CE0300UL))
+#define bFM3_ETHERNET_MAC1_FCR_TFE             *((volatile unsigned int*)(0x42CE0304UL))
+#define bFM3_ETHERNET_MAC1_FCR_RFE             *((volatile unsigned int*)(0x42CE0308UL))
+#define bFM3_ETHERNET_MAC1_FCR_UP              *((volatile unsigned int*)(0x42CE030CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT0            *((volatile unsigned int*)(0x42CE0310UL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT1            *((volatile unsigned int*)(0x42CE0314UL))
+#define bFM3_ETHERNET_MAC1_FCR_DZPQ            *((volatile unsigned int*)(0x42CE031CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT0             *((volatile unsigned int*)(0x42CE0340UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT1             *((volatile unsigned int*)(0x42CE0344UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT2             *((volatile unsigned int*)(0x42CE0348UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT3             *((volatile unsigned int*)(0x42CE034CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT4             *((volatile unsigned int*)(0x42CE0350UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT5             *((volatile unsigned int*)(0x42CE0354UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT6             *((volatile unsigned int*)(0x42CE0358UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT7             *((volatile unsigned int*)(0x42CE035CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT8             *((volatile unsigned int*)(0x42CE0360UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT9             *((volatile unsigned int*)(0x42CE0364UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT10            *((volatile unsigned int*)(0x42CE0368UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT11            *((volatile unsigned int*)(0x42CE036CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT12            *((volatile unsigned int*)(0x42CE0370UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT13            *((volatile unsigned int*)(0x42CE0374UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT14            *((volatile unsigned int*)(0x42CE0378UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT15            *((volatile unsigned int*)(0x42CE037CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL0             *((volatile unsigned int*)(0x42CE0380UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL1             *((volatile unsigned int*)(0x42CE0384UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL2             *((volatile unsigned int*)(0x42CE0388UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL3             *((volatile unsigned int*)(0x42CE038CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL4             *((volatile unsigned int*)(0x42CE0390UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL5             *((volatile unsigned int*)(0x42CE0394UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL6             *((volatile unsigned int*)(0x42CE0398UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL7             *((volatile unsigned int*)(0x42CE039CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL8             *((volatile unsigned int*)(0x42CE03A0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL9             *((volatile unsigned int*)(0x42CE03A4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL10            *((volatile unsigned int*)(0x42CE03A8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL11            *((volatile unsigned int*)(0x42CE03ACUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL12            *((volatile unsigned int*)(0x42CE03B0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL13            *((volatile unsigned int*)(0x42CE03B4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL14            *((volatile unsigned int*)(0x42CE03B8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL15            *((volatile unsigned int*)(0x42CE03BCUL))
+#define bFM3_ETHERNET_MAC1_VTR_ETV             *((volatile unsigned int*)(0x42CE03C0UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42CE0500UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42CE0504UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42CE0508UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42CE050CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42CE0510UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42CE0514UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42CE0518UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42CE051CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42CE0520UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42CE0524UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42CE0528UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42CE052CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42CE0530UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42CE0534UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42CE0538UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42CE053CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42CE0540UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42CE0544UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42CE0548UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42CE054CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42CE0550UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42CE0554UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42CE0558UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42CE055CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42CE0560UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42CE0564UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42CE0568UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42CE056CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42CE0570UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42CE0574UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42CE0578UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42CE057CUL))
+#define bFM3_ETHERNET_MAC1_PMTR_PD             *((volatile unsigned int*)(0x42CE0580UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPE            *((volatile unsigned int*)(0x42CE0584UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WFE            *((volatile unsigned int*)(0x42CE0588UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPR            *((volatile unsigned int*)(0x42CE0594UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WPR            *((volatile unsigned int*)(0x42CE0598UL))
+#define bFM3_ETHERNET_MAC1_PMTR_GU             *((volatile unsigned int*)(0x42CE05A4UL))
+#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42CE05FCUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42CE0600UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42CE0604UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42CE0608UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42CE060CUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST       *((volatile unsigned int*)(0x42CE0620UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST       *((volatile unsigned int*)(0x42CE0624UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN        *((volatile unsigned int*)(0x42CE0640UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLS          *((volatile unsigned int*)(0x42CE0644UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN        *((volatile unsigned int*)(0x42CE0648UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA       *((volatile unsigned int*)(0x42CE064CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT0         *((volatile unsigned int*)(0x42CE0680UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT1         *((volatile unsigned int*)(0x42CE0684UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT2         *((volatile unsigned int*)(0x42CE0688UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT3         *((volatile unsigned int*)(0x42CE068CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT4         *((volatile unsigned int*)(0x42CE0690UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT5         *((volatile unsigned int*)(0x42CE0694UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT6         *((volatile unsigned int*)(0x42CE0698UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT7         *((volatile unsigned int*)(0x42CE069CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT8         *((volatile unsigned int*)(0x42CE06A0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT9         *((volatile unsigned int*)(0x42CE06A4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT10        *((volatile unsigned int*)(0x42CE06A8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT11        *((volatile unsigned int*)(0x42CE06ACUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT12        *((volatile unsigned int*)(0x42CE06B0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT13        *((volatile unsigned int*)(0x42CE06B4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT14        *((volatile unsigned int*)(0x42CE06B8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT15        *((volatile unsigned int*)(0x42CE06BCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT0         *((volatile unsigned int*)(0x42CE06C0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT1         *((volatile unsigned int*)(0x42CE06C4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT2         *((volatile unsigned int*)(0x42CE06C8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT3         *((volatile unsigned int*)(0x42CE06CCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT4         *((volatile unsigned int*)(0x42CE06D0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT5         *((volatile unsigned int*)(0x42CE06D4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT6         *((volatile unsigned int*)(0x42CE06D8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT7         *((volatile unsigned int*)(0x42CE06DCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT8         *((volatile unsigned int*)(0x42CE06E0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT9         *((volatile unsigned int*)(0x42CE06E4UL))
+#define bFM3_ETHERNET_MAC1_ISR_RGIS            *((volatile unsigned int*)(0x42CE0700UL))
+#define bFM3_ETHERNET_MAC1_ISR_PIS             *((volatile unsigned int*)(0x42CE070CUL))
+#define bFM3_ETHERNET_MAC1_ISR_MIS             *((volatile unsigned int*)(0x42CE0710UL))
+#define bFM3_ETHERNET_MAC1_ISR_RIS             *((volatile unsigned int*)(0x42CE0714UL))
+#define bFM3_ETHERNET_MAC1_ISR_TIS             *((volatile unsigned int*)(0x42CE0718UL))
+#define bFM3_ETHERNET_MAC1_ISR_COIS            *((volatile unsigned int*)(0x42CE071CUL))
+#define bFM3_ETHERNET_MAC1_ISR_TSIS            *((volatile unsigned int*)(0x42CE0724UL))
+#define bFM3_ETHERNET_MAC1_ISR_LPIIS           *((volatile unsigned int*)(0x42CE0728UL))
+#define bFM3_ETHERNET_MAC1_IMR_RGIM            *((volatile unsigned int*)(0x42CE0780UL))
+#define bFM3_ETHERNET_MAC1_IMR_PIM             *((volatile unsigned int*)(0x42CE078CUL))
+#define bFM3_ETHERNET_MAC1_IMR_TSIM            *((volatile unsigned int*)(0x42CE0794UL))
+#define bFM3_ETHERNET_MAC1_IMR_LPIIM           *((volatile unsigned int*)(0x42CE0798UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A32           *((volatile unsigned int*)(0x42CE0800UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A33           *((volatile unsigned int*)(0x42CE0804UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A34           *((volatile unsigned int*)(0x42CE0808UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A35           *((volatile unsigned int*)(0x42CE080CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A36           *((volatile unsigned int*)(0x42CE0810UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A37           *((volatile unsigned int*)(0x42CE0814UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A38           *((volatile unsigned int*)(0x42CE0818UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A39           *((volatile unsigned int*)(0x42CE081CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A40           *((volatile unsigned int*)(0x42CE0820UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A41           *((volatile unsigned int*)(0x42CE0824UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A42           *((volatile unsigned int*)(0x42CE0828UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A43           *((volatile unsigned int*)(0x42CE082CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A44           *((volatile unsigned int*)(0x42CE0830UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A45           *((volatile unsigned int*)(0x42CE0834UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A46           *((volatile unsigned int*)(0x42CE0838UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A47           *((volatile unsigned int*)(0x42CE083CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_MO            *((volatile unsigned int*)(0x42CE087CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A0            *((volatile unsigned int*)(0x42CE0880UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A1            *((volatile unsigned int*)(0x42CE0884UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A2            *((volatile unsigned int*)(0x42CE0888UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A3            *((volatile unsigned int*)(0x42CE088CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A4            *((volatile unsigned int*)(0x42CE0890UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A5            *((volatile unsigned int*)(0x42CE0894UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A6            *((volatile unsigned int*)(0x42CE0898UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A7            *((volatile unsigned int*)(0x42CE089CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A8            *((volatile unsigned int*)(0x42CE08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A9            *((volatile unsigned int*)(0x42CE08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A10           *((volatile unsigned int*)(0x42CE08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A11           *((volatile unsigned int*)(0x42CE08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A12           *((volatile unsigned int*)(0x42CE08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A13           *((volatile unsigned int*)(0x42CE08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A14           *((volatile unsigned int*)(0x42CE08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A15           *((volatile unsigned int*)(0x42CE08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A16           *((volatile unsigned int*)(0x42CE08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A17           *((volatile unsigned int*)(0x42CE08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A18           *((volatile unsigned int*)(0x42CE08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A19           *((volatile unsigned int*)(0x42CE08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A20           *((volatile unsigned int*)(0x42CE08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A21           *((volatile unsigned int*)(0x42CE08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A22           *((volatile unsigned int*)(0x42CE08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A23           *((volatile unsigned int*)(0x42CE08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A24           *((volatile unsigned int*)(0x42CE08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A25           *((volatile unsigned int*)(0x42CE08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A26           *((volatile unsigned int*)(0x42CE08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A27           *((volatile unsigned int*)(0x42CE08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A28           *((volatile unsigned int*)(0x42CE08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A29           *((volatile unsigned int*)(0x42CE08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A30           *((volatile unsigned int*)(0x42CE08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A31           *((volatile unsigned int*)(0x42CE08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A32           *((volatile unsigned int*)(0x42CE0900UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A33           *((volatile unsigned int*)(0x42CE0904UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A34           *((volatile unsigned int*)(0x42CE0908UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A35           *((volatile unsigned int*)(0x42CE090CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A36           *((volatile unsigned int*)(0x42CE0910UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A37           *((volatile unsigned int*)(0x42CE0914UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A38           *((volatile unsigned int*)(0x42CE0918UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A39           *((volatile unsigned int*)(0x42CE091CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A40           *((volatile unsigned int*)(0x42CE0920UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A41           *((volatile unsigned int*)(0x42CE0924UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A42           *((volatile unsigned int*)(0x42CE0928UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A43           *((volatile unsigned int*)(0x42CE092CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A44           *((volatile unsigned int*)(0x42CE0930UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A45           *((volatile unsigned int*)(0x42CE0934UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A46           *((volatile unsigned int*)(0x42CE0938UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A47           *((volatile unsigned int*)(0x42CE093CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC0          *((volatile unsigned int*)(0x42CE0960UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC1          *((volatile unsigned int*)(0x42CE0964UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC2          *((volatile unsigned int*)(0x42CE0968UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC3          *((volatile unsigned int*)(0x42CE096CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC4          *((volatile unsigned int*)(0x42CE0970UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC5          *((volatile unsigned int*)(0x42CE0974UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_SA            *((volatile unsigned int*)(0x42CE0978UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_AE            *((volatile unsigned int*)(0x42CE097CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A0            *((volatile unsigned int*)(0x42CE0980UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A1            *((volatile unsigned int*)(0x42CE0984UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A2            *((volatile unsigned int*)(0x42CE0988UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A3            *((volatile unsigned int*)(0x42CE098CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A4            *((volatile unsigned int*)(0x42CE0990UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A5            *((volatile unsigned int*)(0x42CE0994UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A6            *((volatile unsigned int*)(0x42CE0998UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A7            *((volatile unsigned int*)(0x42CE099CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A8            *((volatile unsigned int*)(0x42CE09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A9            *((volatile unsigned int*)(0x42CE09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A10           *((volatile unsigned int*)(0x42CE09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A11           *((volatile unsigned int*)(0x42CE09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A12           *((volatile unsigned int*)(0x42CE09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A13           *((volatile unsigned int*)(0x42CE09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A14           *((volatile unsigned int*)(0x42CE09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A15           *((volatile unsigned int*)(0x42CE09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A16           *((volatile unsigned int*)(0x42CE09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A17           *((volatile unsigned int*)(0x42CE09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A18           *((volatile unsigned int*)(0x42CE09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A19           *((volatile unsigned int*)(0x42CE09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A20           *((volatile unsigned int*)(0x42CE09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A21           *((volatile unsigned int*)(0x42CE09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A22           *((volatile unsigned int*)(0x42CE09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A23           *((volatile unsigned int*)(0x42CE09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A24           *((volatile unsigned int*)(0x42CE09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A25           *((volatile unsigned int*)(0x42CE09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A26           *((volatile unsigned int*)(0x42CE09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A27           *((volatile unsigned int*)(0x42CE09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A28           *((volatile unsigned int*)(0x42CE09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A29           *((volatile unsigned int*)(0x42CE09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A30           *((volatile unsigned int*)(0x42CE09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A31           *((volatile unsigned int*)(0x42CE09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A32           *((volatile unsigned int*)(0x42CE0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A33           *((volatile unsigned int*)(0x42CE0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A34           *((volatile unsigned int*)(0x42CE0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A35           *((volatile unsigned int*)(0x42CE0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A36           *((volatile unsigned int*)(0x42CE0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A37           *((volatile unsigned int*)(0x42CE0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A38           *((volatile unsigned int*)(0x42CE0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A39           *((volatile unsigned int*)(0x42CE0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A40           *((volatile unsigned int*)(0x42CE0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A41           *((volatile unsigned int*)(0x42CE0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A42           *((volatile unsigned int*)(0x42CE0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A43           *((volatile unsigned int*)(0x42CE0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A44           *((volatile unsigned int*)(0x42CE0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A45           *((volatile unsigned int*)(0x42CE0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A46           *((volatile unsigned int*)(0x42CE0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A47           *((volatile unsigned int*)(0x42CE0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC0          *((volatile unsigned int*)(0x42CE0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC1          *((volatile unsigned int*)(0x42CE0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC2          *((volatile unsigned int*)(0x42CE0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC3          *((volatile unsigned int*)(0x42CE0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC4          *((volatile unsigned int*)(0x42CE0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC5          *((volatile unsigned int*)(0x42CE0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_SA            *((volatile unsigned int*)(0x42CE0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_AE            *((volatile unsigned int*)(0x42CE0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A0            *((volatile unsigned int*)(0x42CE0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A1            *((volatile unsigned int*)(0x42CE0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A2            *((volatile unsigned int*)(0x42CE0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A3            *((volatile unsigned int*)(0x42CE0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A4            *((volatile unsigned int*)(0x42CE0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A5            *((volatile unsigned int*)(0x42CE0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A6            *((volatile unsigned int*)(0x42CE0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A7            *((volatile unsigned int*)(0x42CE0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A8            *((volatile unsigned int*)(0x42CE0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A9            *((volatile unsigned int*)(0x42CE0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A10           *((volatile unsigned int*)(0x42CE0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A11           *((volatile unsigned int*)(0x42CE0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A12           *((volatile unsigned int*)(0x42CE0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A13           *((volatile unsigned int*)(0x42CE0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A14           *((volatile unsigned int*)(0x42CE0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A15           *((volatile unsigned int*)(0x42CE0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A16           *((volatile unsigned int*)(0x42CE0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A17           *((volatile unsigned int*)(0x42CE0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A18           *((volatile unsigned int*)(0x42CE0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A19           *((volatile unsigned int*)(0x42CE0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A20           *((volatile unsigned int*)(0x42CE0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A21           *((volatile unsigned int*)(0x42CE0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A22           *((volatile unsigned int*)(0x42CE0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A23           *((volatile unsigned int*)(0x42CE0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A24           *((volatile unsigned int*)(0x42CE0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A25           *((volatile unsigned int*)(0x42CE0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A26           *((volatile unsigned int*)(0x42CE0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A27           *((volatile unsigned int*)(0x42CE0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A28           *((volatile unsigned int*)(0x42CE0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A29           *((volatile unsigned int*)(0x42CE0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A30           *((volatile unsigned int*)(0x42CE0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A31           *((volatile unsigned int*)(0x42CE0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A32           *((volatile unsigned int*)(0x42CE0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A33           *((volatile unsigned int*)(0x42CE0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A34           *((volatile unsigned int*)(0x42CE0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A35           *((volatile unsigned int*)(0x42CE0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A36           *((volatile unsigned int*)(0x42CE0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A37           *((volatile unsigned int*)(0x42CE0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A38           *((volatile unsigned int*)(0x42CE0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A39           *((volatile unsigned int*)(0x42CE0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A40           *((volatile unsigned int*)(0x42CE0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A41           *((volatile unsigned int*)(0x42CE0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A42           *((volatile unsigned int*)(0x42CE0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A43           *((volatile unsigned int*)(0x42CE0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A44           *((volatile unsigned int*)(0x42CE0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A45           *((volatile unsigned int*)(0x42CE0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A46           *((volatile unsigned int*)(0x42CE0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A47           *((volatile unsigned int*)(0x42CE0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC0          *((volatile unsigned int*)(0x42CE0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC1          *((volatile unsigned int*)(0x42CE0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC2          *((volatile unsigned int*)(0x42CE0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC3          *((volatile unsigned int*)(0x42CE0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC4          *((volatile unsigned int*)(0x42CE0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC5          *((volatile unsigned int*)(0x42CE0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_SA            *((volatile unsigned int*)(0x42CE0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_AE            *((volatile unsigned int*)(0x42CE0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A0            *((volatile unsigned int*)(0x42CE0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A1            *((volatile unsigned int*)(0x42CE0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A2            *((volatile unsigned int*)(0x42CE0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A3            *((volatile unsigned int*)(0x42CE0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A4            *((volatile unsigned int*)(0x42CE0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A5            *((volatile unsigned int*)(0x42CE0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A6            *((volatile unsigned int*)(0x42CE0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A7            *((volatile unsigned int*)(0x42CE0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A8            *((volatile unsigned int*)(0x42CE0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A9            *((volatile unsigned int*)(0x42CE0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A10           *((volatile unsigned int*)(0x42CE0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A11           *((volatile unsigned int*)(0x42CE0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A12           *((volatile unsigned int*)(0x42CE0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A13           *((volatile unsigned int*)(0x42CE0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A14           *((volatile unsigned int*)(0x42CE0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A15           *((volatile unsigned int*)(0x42CE0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A16           *((volatile unsigned int*)(0x42CE0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A17           *((volatile unsigned int*)(0x42CE0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A18           *((volatile unsigned int*)(0x42CE0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A19           *((volatile unsigned int*)(0x42CE0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A20           *((volatile unsigned int*)(0x42CE0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A21           *((volatile unsigned int*)(0x42CE0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A22           *((volatile unsigned int*)(0x42CE0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A23           *((volatile unsigned int*)(0x42CE0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A24           *((volatile unsigned int*)(0x42CE0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A25           *((volatile unsigned int*)(0x42CE0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A26           *((volatile unsigned int*)(0x42CE0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A27           *((volatile unsigned int*)(0x42CE0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A28           *((volatile unsigned int*)(0x42CE0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A29           *((volatile unsigned int*)(0x42CE0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A30           *((volatile unsigned int*)(0x42CE0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A31           *((volatile unsigned int*)(0x42CE0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A32           *((volatile unsigned int*)(0x42CE0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A33           *((volatile unsigned int*)(0x42CE0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A34           *((volatile unsigned int*)(0x42CE0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A35           *((volatile unsigned int*)(0x42CE0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A36           *((volatile unsigned int*)(0x42CE0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A37           *((volatile unsigned int*)(0x42CE0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A38           *((volatile unsigned int*)(0x42CE0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A39           *((volatile unsigned int*)(0x42CE0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A40           *((volatile unsigned int*)(0x42CE0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A41           *((volatile unsigned int*)(0x42CE0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A42           *((volatile unsigned int*)(0x42CE0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A43           *((volatile unsigned int*)(0x42CE0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A44           *((volatile unsigned int*)(0x42CE0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A45           *((volatile unsigned int*)(0x42CE0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A46           *((volatile unsigned int*)(0x42CE0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A47           *((volatile unsigned int*)(0x42CE0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC0          *((volatile unsigned int*)(0x42CE0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC1          *((volatile unsigned int*)(0x42CE0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC2          *((volatile unsigned int*)(0x42CE0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC3          *((volatile unsigned int*)(0x42CE0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC4          *((volatile unsigned int*)(0x42CE0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC5          *((volatile unsigned int*)(0x42CE0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_SA            *((volatile unsigned int*)(0x42CE0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_AE            *((volatile unsigned int*)(0x42CE0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A0            *((volatile unsigned int*)(0x42CE0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A1            *((volatile unsigned int*)(0x42CE0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A2            *((volatile unsigned int*)(0x42CE0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A3            *((volatile unsigned int*)(0x42CE0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A4            *((volatile unsigned int*)(0x42CE0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A5            *((volatile unsigned int*)(0x42CE0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A6            *((volatile unsigned int*)(0x42CE0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A7            *((volatile unsigned int*)(0x42CE0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A8            *((volatile unsigned int*)(0x42CE0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A9            *((volatile unsigned int*)(0x42CE0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A10           *((volatile unsigned int*)(0x42CE0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A11           *((volatile unsigned int*)(0x42CE0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A12           *((volatile unsigned int*)(0x42CE0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A13           *((volatile unsigned int*)(0x42CE0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A14           *((volatile unsigned int*)(0x42CE0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A15           *((volatile unsigned int*)(0x42CE0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A16           *((volatile unsigned int*)(0x42CE0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A17           *((volatile unsigned int*)(0x42CE0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A18           *((volatile unsigned int*)(0x42CE0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A19           *((volatile unsigned int*)(0x42CE0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A20           *((volatile unsigned int*)(0x42CE0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A21           *((volatile unsigned int*)(0x42CE0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A22           *((volatile unsigned int*)(0x42CE0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A23           *((volatile unsigned int*)(0x42CE0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A24           *((volatile unsigned int*)(0x42CE0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A25           *((volatile unsigned int*)(0x42CE0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A26           *((volatile unsigned int*)(0x42CE0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A27           *((volatile unsigned int*)(0x42CE0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A28           *((volatile unsigned int*)(0x42CE0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A29           *((volatile unsigned int*)(0x42CE0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A30           *((volatile unsigned int*)(0x42CE0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A31           *((volatile unsigned int*)(0x42CE0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A32           *((volatile unsigned int*)(0x42CE0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A33           *((volatile unsigned int*)(0x42CE0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A34           *((volatile unsigned int*)(0x42CE0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A35           *((volatile unsigned int*)(0x42CE0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A36           *((volatile unsigned int*)(0x42CE0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A37           *((volatile unsigned int*)(0x42CE0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A38           *((volatile unsigned int*)(0x42CE0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A39           *((volatile unsigned int*)(0x42CE0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A40           *((volatile unsigned int*)(0x42CE0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A41           *((volatile unsigned int*)(0x42CE0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A42           *((volatile unsigned int*)(0x42CE0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A43           *((volatile unsigned int*)(0x42CE0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A44           *((volatile unsigned int*)(0x42CE0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A45           *((volatile unsigned int*)(0x42CE0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A46           *((volatile unsigned int*)(0x42CE0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A47           *((volatile unsigned int*)(0x42CE0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC0          *((volatile unsigned int*)(0x42CE0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC1          *((volatile unsigned int*)(0x42CE0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC2          *((volatile unsigned int*)(0x42CE0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC3          *((volatile unsigned int*)(0x42CE0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC4          *((volatile unsigned int*)(0x42CE0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC5          *((volatile unsigned int*)(0x42CE0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_SA            *((volatile unsigned int*)(0x42CE0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_AE            *((volatile unsigned int*)(0x42CE0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A0            *((volatile unsigned int*)(0x42CE0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A1            *((volatile unsigned int*)(0x42CE0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A2            *((volatile unsigned int*)(0x42CE0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A3            *((volatile unsigned int*)(0x42CE0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A4            *((volatile unsigned int*)(0x42CE0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A5            *((volatile unsigned int*)(0x42CE0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A6            *((volatile unsigned int*)(0x42CE0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A7            *((volatile unsigned int*)(0x42CE0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A8            *((volatile unsigned int*)(0x42CE0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A9            *((volatile unsigned int*)(0x42CE0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A10           *((volatile unsigned int*)(0x42CE0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A11           *((volatile unsigned int*)(0x42CE0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A12           *((volatile unsigned int*)(0x42CE0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A13           *((volatile unsigned int*)(0x42CE0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A14           *((volatile unsigned int*)(0x42CE0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A15           *((volatile unsigned int*)(0x42CE0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A16           *((volatile unsigned int*)(0x42CE0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A17           *((volatile unsigned int*)(0x42CE0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A18           *((volatile unsigned int*)(0x42CE0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A19           *((volatile unsigned int*)(0x42CE0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A20           *((volatile unsigned int*)(0x42CE0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A21           *((volatile unsigned int*)(0x42CE0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A22           *((volatile unsigned int*)(0x42CE0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A23           *((volatile unsigned int*)(0x42CE0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A24           *((volatile unsigned int*)(0x42CE0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A25           *((volatile unsigned int*)(0x42CE0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A26           *((volatile unsigned int*)(0x42CE0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A27           *((volatile unsigned int*)(0x42CE0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A28           *((volatile unsigned int*)(0x42CE0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A29           *((volatile unsigned int*)(0x42CE0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A30           *((volatile unsigned int*)(0x42CE0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A31           *((volatile unsigned int*)(0x42CE0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A32           *((volatile unsigned int*)(0x42CE0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A33           *((volatile unsigned int*)(0x42CE0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A34           *((volatile unsigned int*)(0x42CE0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A35           *((volatile unsigned int*)(0x42CE0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A36           *((volatile unsigned int*)(0x42CE0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A37           *((volatile unsigned int*)(0x42CE0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A38           *((volatile unsigned int*)(0x42CE0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A39           *((volatile unsigned int*)(0x42CE0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A40           *((volatile unsigned int*)(0x42CE0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A41           *((volatile unsigned int*)(0x42CE0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A42           *((volatile unsigned int*)(0x42CE0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A43           *((volatile unsigned int*)(0x42CE0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A44           *((volatile unsigned int*)(0x42CE0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A45           *((volatile unsigned int*)(0x42CE0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A46           *((volatile unsigned int*)(0x42CE0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A47           *((volatile unsigned int*)(0x42CE0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC0          *((volatile unsigned int*)(0x42CE0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC1          *((volatile unsigned int*)(0x42CE0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC2          *((volatile unsigned int*)(0x42CE0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC3          *((volatile unsigned int*)(0x42CE0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC4          *((volatile unsigned int*)(0x42CE0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC5          *((volatile unsigned int*)(0x42CE0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_SA            *((volatile unsigned int*)(0x42CE0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_AE            *((volatile unsigned int*)(0x42CE0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A0            *((volatile unsigned int*)(0x42CE0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A1            *((volatile unsigned int*)(0x42CE0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A2            *((volatile unsigned int*)(0x42CE0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A3            *((volatile unsigned int*)(0x42CE0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A4            *((volatile unsigned int*)(0x42CE0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A5            *((volatile unsigned int*)(0x42CE0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A6            *((volatile unsigned int*)(0x42CE0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A7            *((volatile unsigned int*)(0x42CE0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A8            *((volatile unsigned int*)(0x42CE0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A9            *((volatile unsigned int*)(0x42CE0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A10           *((volatile unsigned int*)(0x42CE0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A11           *((volatile unsigned int*)(0x42CE0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A12           *((volatile unsigned int*)(0x42CE0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A13           *((volatile unsigned int*)(0x42CE0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A14           *((volatile unsigned int*)(0x42CE0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A15           *((volatile unsigned int*)(0x42CE0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A16           *((volatile unsigned int*)(0x42CE0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A17           *((volatile unsigned int*)(0x42CE0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A18           *((volatile unsigned int*)(0x42CE0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A19           *((volatile unsigned int*)(0x42CE0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A20           *((volatile unsigned int*)(0x42CE0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A21           *((volatile unsigned int*)(0x42CE0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A22           *((volatile unsigned int*)(0x42CE0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A23           *((volatile unsigned int*)(0x42CE0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A24           *((volatile unsigned int*)(0x42CE0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A25           *((volatile unsigned int*)(0x42CE0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A26           *((volatile unsigned int*)(0x42CE0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A27           *((volatile unsigned int*)(0x42CE0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A28           *((volatile unsigned int*)(0x42CE0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A29           *((volatile unsigned int*)(0x42CE0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A30           *((volatile unsigned int*)(0x42CE0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A31           *((volatile unsigned int*)(0x42CE0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A32           *((volatile unsigned int*)(0x42CE0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A33           *((volatile unsigned int*)(0x42CE0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A34           *((volatile unsigned int*)(0x42CE0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A35           *((volatile unsigned int*)(0x42CE0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A36           *((volatile unsigned int*)(0x42CE0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A37           *((volatile unsigned int*)(0x42CE0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A38           *((volatile unsigned int*)(0x42CE0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A39           *((volatile unsigned int*)(0x42CE0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A40           *((volatile unsigned int*)(0x42CE0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A41           *((volatile unsigned int*)(0x42CE0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A42           *((volatile unsigned int*)(0x42CE0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A43           *((volatile unsigned int*)(0x42CE0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A44           *((volatile unsigned int*)(0x42CE0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A45           *((volatile unsigned int*)(0x42CE0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A46           *((volatile unsigned int*)(0x42CE0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A47           *((volatile unsigned int*)(0x42CE0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC0          *((volatile unsigned int*)(0x42CE0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC1          *((volatile unsigned int*)(0x42CE0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC2          *((volatile unsigned int*)(0x42CE0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC3          *((volatile unsigned int*)(0x42CE0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC4          *((volatile unsigned int*)(0x42CE0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC5          *((volatile unsigned int*)(0x42CE0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_SA            *((volatile unsigned int*)(0x42CE0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_AE            *((volatile unsigned int*)(0x42CE0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A0            *((volatile unsigned int*)(0x42CE0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A1            *((volatile unsigned int*)(0x42CE0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A2            *((volatile unsigned int*)(0x42CE0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A3            *((volatile unsigned int*)(0x42CE0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A4            *((volatile unsigned int*)(0x42CE0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A5            *((volatile unsigned int*)(0x42CE0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A6            *((volatile unsigned int*)(0x42CE0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A7            *((volatile unsigned int*)(0x42CE0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A8            *((volatile unsigned int*)(0x42CE0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A9            *((volatile unsigned int*)(0x42CE0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A10           *((volatile unsigned int*)(0x42CE0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A11           *((volatile unsigned int*)(0x42CE0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A12           *((volatile unsigned int*)(0x42CE0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A13           *((volatile unsigned int*)(0x42CE0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A14           *((volatile unsigned int*)(0x42CE0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A15           *((volatile unsigned int*)(0x42CE0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A16           *((volatile unsigned int*)(0x42CE0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A17           *((volatile unsigned int*)(0x42CE0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A18           *((volatile unsigned int*)(0x42CE0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A19           *((volatile unsigned int*)(0x42CE0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A20           *((volatile unsigned int*)(0x42CE0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A21           *((volatile unsigned int*)(0x42CE0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A22           *((volatile unsigned int*)(0x42CE0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A23           *((volatile unsigned int*)(0x42CE0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A24           *((volatile unsigned int*)(0x42CE0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A25           *((volatile unsigned int*)(0x42CE0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A26           *((volatile unsigned int*)(0x42CE0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A27           *((volatile unsigned int*)(0x42CE0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A28           *((volatile unsigned int*)(0x42CE0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A29           *((volatile unsigned int*)(0x42CE0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A30           *((volatile unsigned int*)(0x42CE0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A31           *((volatile unsigned int*)(0x42CE0FFCUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A32           *((volatile unsigned int*)(0x42CE1000UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A33           *((volatile unsigned int*)(0x42CE1004UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A34           *((volatile unsigned int*)(0x42CE1008UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A35           *((volatile unsigned int*)(0x42CE100CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A36           *((volatile unsigned int*)(0x42CE1010UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A37           *((volatile unsigned int*)(0x42CE1014UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A38           *((volatile unsigned int*)(0x42CE1018UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A39           *((volatile unsigned int*)(0x42CE101CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A40           *((volatile unsigned int*)(0x42CE1020UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A41           *((volatile unsigned int*)(0x42CE1024UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A42           *((volatile unsigned int*)(0x42CE1028UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A43           *((volatile unsigned int*)(0x42CE102CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A44           *((volatile unsigned int*)(0x42CE1030UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A45           *((volatile unsigned int*)(0x42CE1034UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A46           *((volatile unsigned int*)(0x42CE1038UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A47           *((volatile unsigned int*)(0x42CE103CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC0          *((volatile unsigned int*)(0x42CE1060UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC1          *((volatile unsigned int*)(0x42CE1064UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC2          *((volatile unsigned int*)(0x42CE1068UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC3          *((volatile unsigned int*)(0x42CE106CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC4          *((volatile unsigned int*)(0x42CE1070UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC5          *((volatile unsigned int*)(0x42CE1074UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_SA            *((volatile unsigned int*)(0x42CE1078UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_AE            *((volatile unsigned int*)(0x42CE107CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A0            *((volatile unsigned int*)(0x42CE1080UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A1            *((volatile unsigned int*)(0x42CE1084UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A2            *((volatile unsigned int*)(0x42CE1088UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A3            *((volatile unsigned int*)(0x42CE108CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A4            *((volatile unsigned int*)(0x42CE1090UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A5            *((volatile unsigned int*)(0x42CE1094UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A6            *((volatile unsigned int*)(0x42CE1098UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A7            *((volatile unsigned int*)(0x42CE109CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A8            *((volatile unsigned int*)(0x42CE10A0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A9            *((volatile unsigned int*)(0x42CE10A4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A10           *((volatile unsigned int*)(0x42CE10A8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A11           *((volatile unsigned int*)(0x42CE10ACUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A12           *((volatile unsigned int*)(0x42CE10B0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A13           *((volatile unsigned int*)(0x42CE10B4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A14           *((volatile unsigned int*)(0x42CE10B8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A15           *((volatile unsigned int*)(0x42CE10BCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A16           *((volatile unsigned int*)(0x42CE10C0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A17           *((volatile unsigned int*)(0x42CE10C4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A18           *((volatile unsigned int*)(0x42CE10C8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A19           *((volatile unsigned int*)(0x42CE10CCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A20           *((volatile unsigned int*)(0x42CE10D0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A21           *((volatile unsigned int*)(0x42CE10D4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A22           *((volatile unsigned int*)(0x42CE10D8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A23           *((volatile unsigned int*)(0x42CE10DCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A24           *((volatile unsigned int*)(0x42CE10E0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A25           *((volatile unsigned int*)(0x42CE10E4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A26           *((volatile unsigned int*)(0x42CE10E8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A27           *((volatile unsigned int*)(0x42CE10ECUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A28           *((volatile unsigned int*)(0x42CE10F0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A29           *((volatile unsigned int*)(0x42CE10F4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A30           *((volatile unsigned int*)(0x42CE10F8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A31           *((volatile unsigned int*)(0x42CE10FCUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A32           *((volatile unsigned int*)(0x42CE1100UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A33           *((volatile unsigned int*)(0x42CE1104UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A34           *((volatile unsigned int*)(0x42CE1108UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A35           *((volatile unsigned int*)(0x42CE110CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A36           *((volatile unsigned int*)(0x42CE1110UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A37           *((volatile unsigned int*)(0x42CE1114UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A38           *((volatile unsigned int*)(0x42CE1118UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A39           *((volatile unsigned int*)(0x42CE111CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A40           *((volatile unsigned int*)(0x42CE1120UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A41           *((volatile unsigned int*)(0x42CE1124UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A42           *((volatile unsigned int*)(0x42CE1128UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A43           *((volatile unsigned int*)(0x42CE112CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A44           *((volatile unsigned int*)(0x42CE1130UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A45           *((volatile unsigned int*)(0x42CE1134UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A46           *((volatile unsigned int*)(0x42CE1138UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A47           *((volatile unsigned int*)(0x42CE113CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC0          *((volatile unsigned int*)(0x42CE1160UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC1          *((volatile unsigned int*)(0x42CE1164UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC2          *((volatile unsigned int*)(0x42CE1168UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC3          *((volatile unsigned int*)(0x42CE116CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC4          *((volatile unsigned int*)(0x42CE1170UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC5          *((volatile unsigned int*)(0x42CE1174UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_SA            *((volatile unsigned int*)(0x42CE1178UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_AE            *((volatile unsigned int*)(0x42CE117CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A0            *((volatile unsigned int*)(0x42CE1180UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A1            *((volatile unsigned int*)(0x42CE1184UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A2            *((volatile unsigned int*)(0x42CE1188UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A3            *((volatile unsigned int*)(0x42CE118CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A4            *((volatile unsigned int*)(0x42CE1190UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A5            *((volatile unsigned int*)(0x42CE1194UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A6            *((volatile unsigned int*)(0x42CE1198UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A7            *((volatile unsigned int*)(0x42CE119CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A8            *((volatile unsigned int*)(0x42CE11A0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A9            *((volatile unsigned int*)(0x42CE11A4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A10           *((volatile unsigned int*)(0x42CE11A8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A11           *((volatile unsigned int*)(0x42CE11ACUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A12           *((volatile unsigned int*)(0x42CE11B0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A13           *((volatile unsigned int*)(0x42CE11B4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A14           *((volatile unsigned int*)(0x42CE11B8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A15           *((volatile unsigned int*)(0x42CE11BCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A16           *((volatile unsigned int*)(0x42CE11C0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A17           *((volatile unsigned int*)(0x42CE11C4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A18           *((volatile unsigned int*)(0x42CE11C8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A19           *((volatile unsigned int*)(0x42CE11CCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A20           *((volatile unsigned int*)(0x42CE11D0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A21           *((volatile unsigned int*)(0x42CE11D4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A22           *((volatile unsigned int*)(0x42CE11D8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A23           *((volatile unsigned int*)(0x42CE11DCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A24           *((volatile unsigned int*)(0x42CE11E0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A25           *((volatile unsigned int*)(0x42CE11E4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A26           *((volatile unsigned int*)(0x42CE11E8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A27           *((volatile unsigned int*)(0x42CE11ECUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A28           *((volatile unsigned int*)(0x42CE11F0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A29           *((volatile unsigned int*)(0x42CE11F4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A30           *((volatile unsigned int*)(0x42CE11F8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A31           *((volatile unsigned int*)(0x42CE11FCUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A32          *((volatile unsigned int*)(0x42CE1200UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A33          *((volatile unsigned int*)(0x42CE1204UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A34          *((volatile unsigned int*)(0x42CE1208UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A35          *((volatile unsigned int*)(0x42CE120CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A36          *((volatile unsigned int*)(0x42CE1210UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A37          *((volatile unsigned int*)(0x42CE1214UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A38          *((volatile unsigned int*)(0x42CE1218UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A39          *((volatile unsigned int*)(0x42CE121CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A40          *((volatile unsigned int*)(0x42CE1220UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A41          *((volatile unsigned int*)(0x42CE1224UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A42          *((volatile unsigned int*)(0x42CE1228UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A43          *((volatile unsigned int*)(0x42CE122CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A44          *((volatile unsigned int*)(0x42CE1230UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A45          *((volatile unsigned int*)(0x42CE1234UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A46          *((volatile unsigned int*)(0x42CE1238UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A47          *((volatile unsigned int*)(0x42CE123CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC0         *((volatile unsigned int*)(0x42CE1260UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC1         *((volatile unsigned int*)(0x42CE1264UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC2         *((volatile unsigned int*)(0x42CE1268UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC3         *((volatile unsigned int*)(0x42CE126CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC4         *((volatile unsigned int*)(0x42CE1270UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC5         *((volatile unsigned int*)(0x42CE1274UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_SA           *((volatile unsigned int*)(0x42CE1278UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_AE           *((volatile unsigned int*)(0x42CE127CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A0           *((volatile unsigned int*)(0x42CE1280UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A1           *((volatile unsigned int*)(0x42CE1284UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A2           *((volatile unsigned int*)(0x42CE1288UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A3           *((volatile unsigned int*)(0x42CE128CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A4           *((volatile unsigned int*)(0x42CE1290UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A5           *((volatile unsigned int*)(0x42CE1294UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A6           *((volatile unsigned int*)(0x42CE1298UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A7           *((volatile unsigned int*)(0x42CE129CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A8           *((volatile unsigned int*)(0x42CE12A0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A9           *((volatile unsigned int*)(0x42CE12A4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A10          *((volatile unsigned int*)(0x42CE12A8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A11          *((volatile unsigned int*)(0x42CE12ACUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A12          *((volatile unsigned int*)(0x42CE12B0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A13          *((volatile unsigned int*)(0x42CE12B4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A14          *((volatile unsigned int*)(0x42CE12B8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A15          *((volatile unsigned int*)(0x42CE12BCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A16          *((volatile unsigned int*)(0x42CE12C0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A17          *((volatile unsigned int*)(0x42CE12C4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A18          *((volatile unsigned int*)(0x42CE12C8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A19          *((volatile unsigned int*)(0x42CE12CCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A20          *((volatile unsigned int*)(0x42CE12D0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A21          *((volatile unsigned int*)(0x42CE12D4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A22          *((volatile unsigned int*)(0x42CE12D8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A23          *((volatile unsigned int*)(0x42CE12DCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A24          *((volatile unsigned int*)(0x42CE12E0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A25          *((volatile unsigned int*)(0x42CE12E4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A26          *((volatile unsigned int*)(0x42CE12E8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A27          *((volatile unsigned int*)(0x42CE12ECUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A28          *((volatile unsigned int*)(0x42CE12F0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A29          *((volatile unsigned int*)(0x42CE12F4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A30          *((volatile unsigned int*)(0x42CE12F8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A31          *((volatile unsigned int*)(0x42CE12FCUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A32          *((volatile unsigned int*)(0x42CE1300UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A33          *((volatile unsigned int*)(0x42CE1304UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A34          *((volatile unsigned int*)(0x42CE1308UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A35          *((volatile unsigned int*)(0x42CE130CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A36          *((volatile unsigned int*)(0x42CE1310UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A37          *((volatile unsigned int*)(0x42CE1314UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A38          *((volatile unsigned int*)(0x42CE1318UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A39          *((volatile unsigned int*)(0x42CE131CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A40          *((volatile unsigned int*)(0x42CE1320UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A41          *((volatile unsigned int*)(0x42CE1324UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A42          *((volatile unsigned int*)(0x42CE1328UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A43          *((volatile unsigned int*)(0x42CE132CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A44          *((volatile unsigned int*)(0x42CE1330UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A45          *((volatile unsigned int*)(0x42CE1334UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A46          *((volatile unsigned int*)(0x42CE1338UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A47          *((volatile unsigned int*)(0x42CE133CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC0         *((volatile unsigned int*)(0x42CE1360UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC1         *((volatile unsigned int*)(0x42CE1364UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC2         *((volatile unsigned int*)(0x42CE1368UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC3         *((volatile unsigned int*)(0x42CE136CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC4         *((volatile unsigned int*)(0x42CE1370UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC5         *((volatile unsigned int*)(0x42CE1374UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_SA           *((volatile unsigned int*)(0x42CE1378UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_AE           *((volatile unsigned int*)(0x42CE137CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A0           *((volatile unsigned int*)(0x42CE1380UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A1           *((volatile unsigned int*)(0x42CE1384UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A2           *((volatile unsigned int*)(0x42CE1388UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A3           *((volatile unsigned int*)(0x42CE138CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A4           *((volatile unsigned int*)(0x42CE1390UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A5           *((volatile unsigned int*)(0x42CE1394UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A6           *((volatile unsigned int*)(0x42CE1398UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A7           *((volatile unsigned int*)(0x42CE139CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A8           *((volatile unsigned int*)(0x42CE13A0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A9           *((volatile unsigned int*)(0x42CE13A4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A10          *((volatile unsigned int*)(0x42CE13A8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A11          *((volatile unsigned int*)(0x42CE13ACUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A12          *((volatile unsigned int*)(0x42CE13B0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A13          *((volatile unsigned int*)(0x42CE13B4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A14          *((volatile unsigned int*)(0x42CE13B8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A15          *((volatile unsigned int*)(0x42CE13BCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A16          *((volatile unsigned int*)(0x42CE13C0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A17          *((volatile unsigned int*)(0x42CE13C4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A18          *((volatile unsigned int*)(0x42CE13C8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A19          *((volatile unsigned int*)(0x42CE13CCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A20          *((volatile unsigned int*)(0x42CE13D0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A21          *((volatile unsigned int*)(0x42CE13D4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A22          *((volatile unsigned int*)(0x42CE13D8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A23          *((volatile unsigned int*)(0x42CE13DCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A24          *((volatile unsigned int*)(0x42CE13E0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A25          *((volatile unsigned int*)(0x42CE13E4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A26          *((volatile unsigned int*)(0x42CE13E8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A27          *((volatile unsigned int*)(0x42CE13ECUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A28          *((volatile unsigned int*)(0x42CE13F0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A29          *((volatile unsigned int*)(0x42CE13F4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A30          *((volatile unsigned int*)(0x42CE13F8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A31          *((volatile unsigned int*)(0x42CE13FCUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A32          *((volatile unsigned int*)(0x42CE1400UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A33          *((volatile unsigned int*)(0x42CE1404UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A34          *((volatile unsigned int*)(0x42CE1408UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A35          *((volatile unsigned int*)(0x42CE140CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A36          *((volatile unsigned int*)(0x42CE1410UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A37          *((volatile unsigned int*)(0x42CE1414UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A38          *((volatile unsigned int*)(0x42CE1418UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A39          *((volatile unsigned int*)(0x42CE141CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A40          *((volatile unsigned int*)(0x42CE1420UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A41          *((volatile unsigned int*)(0x42CE1424UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A42          *((volatile unsigned int*)(0x42CE1428UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A43          *((volatile unsigned int*)(0x42CE142CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A44          *((volatile unsigned int*)(0x42CE1430UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A45          *((volatile unsigned int*)(0x42CE1434UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A46          *((volatile unsigned int*)(0x42CE1438UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A47          *((volatile unsigned int*)(0x42CE143CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC0         *((volatile unsigned int*)(0x42CE1460UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC1         *((volatile unsigned int*)(0x42CE1464UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC2         *((volatile unsigned int*)(0x42CE1468UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC3         *((volatile unsigned int*)(0x42CE146CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC4         *((volatile unsigned int*)(0x42CE1470UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC5         *((volatile unsigned int*)(0x42CE1474UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_SA           *((volatile unsigned int*)(0x42CE1478UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_AE           *((volatile unsigned int*)(0x42CE147CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A0           *((volatile unsigned int*)(0x42CE1480UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A1           *((volatile unsigned int*)(0x42CE1484UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A2           *((volatile unsigned int*)(0x42CE1488UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A3           *((volatile unsigned int*)(0x42CE148CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A4           *((volatile unsigned int*)(0x42CE1490UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A5           *((volatile unsigned int*)(0x42CE1494UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A6           *((volatile unsigned int*)(0x42CE1498UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A7           *((volatile unsigned int*)(0x42CE149CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A8           *((volatile unsigned int*)(0x42CE14A0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A9           *((volatile unsigned int*)(0x42CE14A4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A10          *((volatile unsigned int*)(0x42CE14A8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A11          *((volatile unsigned int*)(0x42CE14ACUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A12          *((volatile unsigned int*)(0x42CE14B0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A13          *((volatile unsigned int*)(0x42CE14B4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A14          *((volatile unsigned int*)(0x42CE14B8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A15          *((volatile unsigned int*)(0x42CE14BCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A16          *((volatile unsigned int*)(0x42CE14C0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A17          *((volatile unsigned int*)(0x42CE14C4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A18          *((volatile unsigned int*)(0x42CE14C8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A19          *((volatile unsigned int*)(0x42CE14CCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A20          *((volatile unsigned int*)(0x42CE14D0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A21          *((volatile unsigned int*)(0x42CE14D4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A22          *((volatile unsigned int*)(0x42CE14D8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A23          *((volatile unsigned int*)(0x42CE14DCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A24          *((volatile unsigned int*)(0x42CE14E0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A25          *((volatile unsigned int*)(0x42CE14E4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A26          *((volatile unsigned int*)(0x42CE14E8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A27          *((volatile unsigned int*)(0x42CE14ECUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A28          *((volatile unsigned int*)(0x42CE14F0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A29          *((volatile unsigned int*)(0x42CE14F4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A30          *((volatile unsigned int*)(0x42CE14F8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A31          *((volatile unsigned int*)(0x42CE14FCUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A32          *((volatile unsigned int*)(0x42CE1500UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A33          *((volatile unsigned int*)(0x42CE1504UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A34          *((volatile unsigned int*)(0x42CE1508UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A35          *((volatile unsigned int*)(0x42CE150CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A36          *((volatile unsigned int*)(0x42CE1510UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A37          *((volatile unsigned int*)(0x42CE1514UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A38          *((volatile unsigned int*)(0x42CE1518UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A39          *((volatile unsigned int*)(0x42CE151CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A40          *((volatile unsigned int*)(0x42CE1520UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A41          *((volatile unsigned int*)(0x42CE1524UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A42          *((volatile unsigned int*)(0x42CE1528UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A43          *((volatile unsigned int*)(0x42CE152CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A44          *((volatile unsigned int*)(0x42CE1530UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A45          *((volatile unsigned int*)(0x42CE1534UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A46          *((volatile unsigned int*)(0x42CE1538UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A47          *((volatile unsigned int*)(0x42CE153CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC0         *((volatile unsigned int*)(0x42CE1560UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC1         *((volatile unsigned int*)(0x42CE1564UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC2         *((volatile unsigned int*)(0x42CE1568UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC3         *((volatile unsigned int*)(0x42CE156CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC4         *((volatile unsigned int*)(0x42CE1570UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC5         *((volatile unsigned int*)(0x42CE1574UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_SA           *((volatile unsigned int*)(0x42CE1578UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_AE           *((volatile unsigned int*)(0x42CE157CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A0           *((volatile unsigned int*)(0x42CE1580UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A1           *((volatile unsigned int*)(0x42CE1584UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A2           *((volatile unsigned int*)(0x42CE1588UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A3           *((volatile unsigned int*)(0x42CE158CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A4           *((volatile unsigned int*)(0x42CE1590UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A5           *((volatile unsigned int*)(0x42CE1594UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A6           *((volatile unsigned int*)(0x42CE1598UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A7           *((volatile unsigned int*)(0x42CE159CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A8           *((volatile unsigned int*)(0x42CE15A0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A9           *((volatile unsigned int*)(0x42CE15A4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A10          *((volatile unsigned int*)(0x42CE15A8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A11          *((volatile unsigned int*)(0x42CE15ACUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A12          *((volatile unsigned int*)(0x42CE15B0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A13          *((volatile unsigned int*)(0x42CE15B4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A14          *((volatile unsigned int*)(0x42CE15B8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A15          *((volatile unsigned int*)(0x42CE15BCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A16          *((volatile unsigned int*)(0x42CE15C0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A17          *((volatile unsigned int*)(0x42CE15C4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A18          *((volatile unsigned int*)(0x42CE15C8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A19          *((volatile unsigned int*)(0x42CE15CCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A20          *((volatile unsigned int*)(0x42CE15D0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A21          *((volatile unsigned int*)(0x42CE15D4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A22          *((volatile unsigned int*)(0x42CE15D8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A23          *((volatile unsigned int*)(0x42CE15DCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A24          *((volatile unsigned int*)(0x42CE15E0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A25          *((volatile unsigned int*)(0x42CE15E4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A26          *((volatile unsigned int*)(0x42CE15E8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A27          *((volatile unsigned int*)(0x42CE15ECUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A28          *((volatile unsigned int*)(0x42CE15F0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A29          *((volatile unsigned int*)(0x42CE15F4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A30          *((volatile unsigned int*)(0x42CE15F8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A31          *((volatile unsigned int*)(0x42CE15FCUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A32          *((volatile unsigned int*)(0x42CE1600UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A33          *((volatile unsigned int*)(0x42CE1604UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A34          *((volatile unsigned int*)(0x42CE1608UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A35          *((volatile unsigned int*)(0x42CE160CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A36          *((volatile unsigned int*)(0x42CE1610UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A37          *((volatile unsigned int*)(0x42CE1614UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A38          *((volatile unsigned int*)(0x42CE1618UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A39          *((volatile unsigned int*)(0x42CE161CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A40          *((volatile unsigned int*)(0x42CE1620UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A41          *((volatile unsigned int*)(0x42CE1624UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A42          *((volatile unsigned int*)(0x42CE1628UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A43          *((volatile unsigned int*)(0x42CE162CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A44          *((volatile unsigned int*)(0x42CE1630UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A45          *((volatile unsigned int*)(0x42CE1634UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A46          *((volatile unsigned int*)(0x42CE1638UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A47          *((volatile unsigned int*)(0x42CE163CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC0         *((volatile unsigned int*)(0x42CE1660UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC1         *((volatile unsigned int*)(0x42CE1664UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC2         *((volatile unsigned int*)(0x42CE1668UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC3         *((volatile unsigned int*)(0x42CE166CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC4         *((volatile unsigned int*)(0x42CE1670UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC5         *((volatile unsigned int*)(0x42CE1674UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_SA           *((volatile unsigned int*)(0x42CE1678UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_AE           *((volatile unsigned int*)(0x42CE167CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A0           *((volatile unsigned int*)(0x42CE1680UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A1           *((volatile unsigned int*)(0x42CE1684UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A2           *((volatile unsigned int*)(0x42CE1688UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A3           *((volatile unsigned int*)(0x42CE168CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A4           *((volatile unsigned int*)(0x42CE1690UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A5           *((volatile unsigned int*)(0x42CE1694UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A6           *((volatile unsigned int*)(0x42CE1698UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A7           *((volatile unsigned int*)(0x42CE169CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A8           *((volatile unsigned int*)(0x42CE16A0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A9           *((volatile unsigned int*)(0x42CE16A4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A10          *((volatile unsigned int*)(0x42CE16A8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A11          *((volatile unsigned int*)(0x42CE16ACUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A12          *((volatile unsigned int*)(0x42CE16B0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A13          *((volatile unsigned int*)(0x42CE16B4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A14          *((volatile unsigned int*)(0x42CE16B8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A15          *((volatile unsigned int*)(0x42CE16BCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A16          *((volatile unsigned int*)(0x42CE16C0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A17          *((volatile unsigned int*)(0x42CE16C4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A18          *((volatile unsigned int*)(0x42CE16C8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A19          *((volatile unsigned int*)(0x42CE16CCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A20          *((volatile unsigned int*)(0x42CE16D0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A21          *((volatile unsigned int*)(0x42CE16D4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A22          *((volatile unsigned int*)(0x42CE16D8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A23          *((volatile unsigned int*)(0x42CE16DCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A24          *((volatile unsigned int*)(0x42CE16E0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A25          *((volatile unsigned int*)(0x42CE16E4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A26          *((volatile unsigned int*)(0x42CE16E8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A27          *((volatile unsigned int*)(0x42CE16ECUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A28          *((volatile unsigned int*)(0x42CE16F0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A29          *((volatile unsigned int*)(0x42CE16F4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A30          *((volatile unsigned int*)(0x42CE16F8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A31          *((volatile unsigned int*)(0x42CE16FCUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A32          *((volatile unsigned int*)(0x42CE1700UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A33          *((volatile unsigned int*)(0x42CE1704UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A34          *((volatile unsigned int*)(0x42CE1708UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A35          *((volatile unsigned int*)(0x42CE170CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A36          *((volatile unsigned int*)(0x42CE1710UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A37          *((volatile unsigned int*)(0x42CE1714UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A38          *((volatile unsigned int*)(0x42CE1718UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A39          *((volatile unsigned int*)(0x42CE171CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A40          *((volatile unsigned int*)(0x42CE1720UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A41          *((volatile unsigned int*)(0x42CE1724UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A42          *((volatile unsigned int*)(0x42CE1728UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A43          *((volatile unsigned int*)(0x42CE172CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A44          *((volatile unsigned int*)(0x42CE1730UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A45          *((volatile unsigned int*)(0x42CE1734UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A46          *((volatile unsigned int*)(0x42CE1738UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A47          *((volatile unsigned int*)(0x42CE173CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC0         *((volatile unsigned int*)(0x42CE1760UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC1         *((volatile unsigned int*)(0x42CE1764UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC2         *((volatile unsigned int*)(0x42CE1768UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC3         *((volatile unsigned int*)(0x42CE176CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC4         *((volatile unsigned int*)(0x42CE1770UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC5         *((volatile unsigned int*)(0x42CE1774UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_SA           *((volatile unsigned int*)(0x42CE1778UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_AE           *((volatile unsigned int*)(0x42CE177CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A0           *((volatile unsigned int*)(0x42CE1780UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A1           *((volatile unsigned int*)(0x42CE1784UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A2           *((volatile unsigned int*)(0x42CE1788UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A3           *((volatile unsigned int*)(0x42CE178CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A4           *((volatile unsigned int*)(0x42CE1790UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A5           *((volatile unsigned int*)(0x42CE1794UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A6           *((volatile unsigned int*)(0x42CE1798UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A7           *((volatile unsigned int*)(0x42CE179CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A8           *((volatile unsigned int*)(0x42CE17A0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A9           *((volatile unsigned int*)(0x42CE17A4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A10          *((volatile unsigned int*)(0x42CE17A8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A11          *((volatile unsigned int*)(0x42CE17ACUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A12          *((volatile unsigned int*)(0x42CE17B0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A13          *((volatile unsigned int*)(0x42CE17B4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A14          *((volatile unsigned int*)(0x42CE17B8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A15          *((volatile unsigned int*)(0x42CE17BCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A16          *((volatile unsigned int*)(0x42CE17C0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A17          *((volatile unsigned int*)(0x42CE17C4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A18          *((volatile unsigned int*)(0x42CE17C8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A19          *((volatile unsigned int*)(0x42CE17CCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A20          *((volatile unsigned int*)(0x42CE17D0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A21          *((volatile unsigned int*)(0x42CE17D4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A22          *((volatile unsigned int*)(0x42CE17D8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A23          *((volatile unsigned int*)(0x42CE17DCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A24          *((volatile unsigned int*)(0x42CE17E0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A25          *((volatile unsigned int*)(0x42CE17E4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A26          *((volatile unsigned int*)(0x42CE17E8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A27          *((volatile unsigned int*)(0x42CE17ECUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A28          *((volatile unsigned int*)(0x42CE17F0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A29          *((volatile unsigned int*)(0x42CE17F4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A30          *((volatile unsigned int*)(0x42CE17F8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A31          *((volatile unsigned int*)(0x42CE17FCUL))
+#define bFM3_ETHERNET_MAC1_RGSR_LM             *((volatile unsigned int*)(0x42CE1B00UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP0           *((volatile unsigned int*)(0x42CE1B04UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP1           *((volatile unsigned int*)(0x42CE1B08UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LS             *((volatile unsigned int*)(0x42CE1B0CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSE            *((volatile unsigned int*)(0x42CEE000UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TFCU           *((volatile unsigned int*)(0x42CEE004UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSI            *((volatile unsigned int*)(0x42CEE008UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSU            *((volatile unsigned int*)(0x42CEE00CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TITE           *((volatile unsigned int*)(0x42CEE010UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TARU           *((volatile unsigned int*)(0x42CEE014UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSEA           *((volatile unsigned int*)(0x42CEE020UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSDB           *((volatile unsigned int*)(0x42CEE024UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSV2E          *((volatile unsigned int*)(0x42CEE028UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSP          *((volatile unsigned int*)(0x42CEE02CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E         *((volatile unsigned int*)(0x42CEE030UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E         *((volatile unsigned int*)(0x42CEE034UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSEM         *((volatile unsigned int*)(0x42CEE038UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSMRM          *((volatile unsigned int*)(0x42CEE03CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS0          *((volatile unsigned int*)(0x42CEE040UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS1          *((volatile unsigned int*)(0x42CEE044UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSENMF         *((volatile unsigned int*)(0x42CEE048UL))
+#define bFM3_ETHERNET_MAC1_TSCR_ATSFC          *((volatile unsigned int*)(0x42CEE060UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC0         *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC1         *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC2         *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC3         *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC4         *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC5         *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC6         *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC7         *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS0           *((volatile unsigned int*)(0x42CEE100UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS1           *((volatile unsigned int*)(0x42CEE104UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS2           *((volatile unsigned int*)(0x42CEE108UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS3           *((volatile unsigned int*)(0x42CEE10CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS4           *((volatile unsigned int*)(0x42CEE110UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS5           *((volatile unsigned int*)(0x42CEE114UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS6           *((volatile unsigned int*)(0x42CEE118UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS7           *((volatile unsigned int*)(0x42CEE11CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS8           *((volatile unsigned int*)(0x42CEE120UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS9           *((volatile unsigned int*)(0x42CEE124UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS10          *((volatile unsigned int*)(0x42CEE128UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS11          *((volatile unsigned int*)(0x42CEE12CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS12          *((volatile unsigned int*)(0x42CEE130UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS13          *((volatile unsigned int*)(0x42CEE134UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS14          *((volatile unsigned int*)(0x42CEE138UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS15          *((volatile unsigned int*)(0x42CEE13CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS16          *((volatile unsigned int*)(0x42CEE140UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS17          *((volatile unsigned int*)(0x42CEE144UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS18          *((volatile unsigned int*)(0x42CEE148UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS19          *((volatile unsigned int*)(0x42CEE14CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS20          *((volatile unsigned int*)(0x42CEE150UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS21          *((volatile unsigned int*)(0x42CEE154UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS22          *((volatile unsigned int*)(0x42CEE158UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS23          *((volatile unsigned int*)(0x42CEE15CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS24          *((volatile unsigned int*)(0x42CEE160UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS25          *((volatile unsigned int*)(0x42CEE164UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS26          *((volatile unsigned int*)(0x42CEE168UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS27          *((volatile unsigned int*)(0x42CEE16CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS28          *((volatile unsigned int*)(0x42CEE170UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS29          *((volatile unsigned int*)(0x42CEE174UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS30          *((volatile unsigned int*)(0x42CEE178UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS31          *((volatile unsigned int*)(0x42CEE17CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS0          *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS1          *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS2          *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS3          *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS4          *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS5          *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS6          *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS7          *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS8          *((volatile unsigned int*)(0x42CEE0A0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS9          *((volatile unsigned int*)(0x42CEE0A4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS10         *((volatile unsigned int*)(0x42CEE0A8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS11         *((volatile unsigned int*)(0x42CEE0ACUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS12         *((volatile unsigned int*)(0x42CEE0B0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS13         *((volatile unsigned int*)(0x42CEE0B4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS14         *((volatile unsigned int*)(0x42CEE0B8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS15         *((volatile unsigned int*)(0x42CEE0BCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS16         *((volatile unsigned int*)(0x42CEE0C0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS17         *((volatile unsigned int*)(0x42CEE0C4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS18         *((volatile unsigned int*)(0x42CEE0C8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS19         *((volatile unsigned int*)(0x42CEE0CCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS20         *((volatile unsigned int*)(0x42CEE0D0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS21         *((volatile unsigned int*)(0x42CEE0D4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS22         *((volatile unsigned int*)(0x42CEE0D8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS23         *((volatile unsigned int*)(0x42CEE0DCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS24         *((volatile unsigned int*)(0x42CEE0E0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS25         *((volatile unsigned int*)(0x42CEE0E4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS26         *((volatile unsigned int*)(0x42CEE0E8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS27         *((volatile unsigned int*)(0x42CEE0ECUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS28         *((volatile unsigned int*)(0x42CEE0F0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS29         *((volatile unsigned int*)(0x42CEE0F4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS30         *((volatile unsigned int*)(0x42CEE0F8UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS0          *((volatile unsigned int*)(0x42CEE200UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS1          *((volatile unsigned int*)(0x42CEE204UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS2          *((volatile unsigned int*)(0x42CEE208UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS3          *((volatile unsigned int*)(0x42CEE20CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS4          *((volatile unsigned int*)(0x42CEE210UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS5          *((volatile unsigned int*)(0x42CEE214UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS6          *((volatile unsigned int*)(0x42CEE218UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS7          *((volatile unsigned int*)(0x42CEE21CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS8          *((volatile unsigned int*)(0x42CEE220UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS9          *((volatile unsigned int*)(0x42CEE224UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS10         *((volatile unsigned int*)(0x42CEE228UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS11         *((volatile unsigned int*)(0x42CEE22CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS12         *((volatile unsigned int*)(0x42CEE230UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS13         *((volatile unsigned int*)(0x42CEE234UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS14         *((volatile unsigned int*)(0x42CEE238UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS15         *((volatile unsigned int*)(0x42CEE23CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS16         *((volatile unsigned int*)(0x42CEE240UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS17         *((volatile unsigned int*)(0x42CEE244UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS18         *((volatile unsigned int*)(0x42CEE248UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS19         *((volatile unsigned int*)(0x42CEE24CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS20         *((volatile unsigned int*)(0x42CEE250UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS21         *((volatile unsigned int*)(0x42CEE254UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS22         *((volatile unsigned int*)(0x42CEE258UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS23         *((volatile unsigned int*)(0x42CEE25CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS24         *((volatile unsigned int*)(0x42CEE260UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS25         *((volatile unsigned int*)(0x42CEE264UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS26         *((volatile unsigned int*)(0x42CEE268UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS27         *((volatile unsigned int*)(0x42CEE26CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS28         *((volatile unsigned int*)(0x42CEE270UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS29         *((volatile unsigned int*)(0x42CEE274UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS30         *((volatile unsigned int*)(0x42CEE278UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS31         *((volatile unsigned int*)(0x42CEE27CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS0         *((volatile unsigned int*)(0x42CEE280UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS1         *((volatile unsigned int*)(0x42CEE284UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS2         *((volatile unsigned int*)(0x42CEE288UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS3         *((volatile unsigned int*)(0x42CEE28CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS4         *((volatile unsigned int*)(0x42CEE290UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS5         *((volatile unsigned int*)(0x42CEE294UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS6         *((volatile unsigned int*)(0x42CEE298UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS7         *((volatile unsigned int*)(0x42CEE29CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS8         *((volatile unsigned int*)(0x42CEE2A0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS9         *((volatile unsigned int*)(0x42CEE2A4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS10        *((volatile unsigned int*)(0x42CEE2A8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS11        *((volatile unsigned int*)(0x42CEE2ACUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS12        *((volatile unsigned int*)(0x42CEE2B0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS13        *((volatile unsigned int*)(0x42CEE2B4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS14        *((volatile unsigned int*)(0x42CEE2B8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS15        *((volatile unsigned int*)(0x42CEE2BCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS16        *((volatile unsigned int*)(0x42CEE2C0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS17        *((volatile unsigned int*)(0x42CEE2C4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS18        *((volatile unsigned int*)(0x42CEE2C8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS19        *((volatile unsigned int*)(0x42CEE2CCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS20        *((volatile unsigned int*)(0x42CEE2D0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS21        *((volatile unsigned int*)(0x42CEE2D4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS22        *((volatile unsigned int*)(0x42CEE2D8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS23        *((volatile unsigned int*)(0x42CEE2DCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS24        *((volatile unsigned int*)(0x42CEE2E0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS25        *((volatile unsigned int*)(0x42CEE2E4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS26        *((volatile unsigned int*)(0x42CEE2E8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS27        *((volatile unsigned int*)(0x42CEE2ECUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS28        *((volatile unsigned int*)(0x42CEE2F0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS29        *((volatile unsigned int*)(0x42CEE2F4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS30        *((volatile unsigned int*)(0x42CEE2F8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB        *((volatile unsigned int*)(0x42CEE2FCUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR0          *((volatile unsigned int*)(0x42CEE300UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR1          *((volatile unsigned int*)(0x42CEE304UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR2          *((volatile unsigned int*)(0x42CEE308UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR3          *((volatile unsigned int*)(0x42CEE30CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR4          *((volatile unsigned int*)(0x42CEE310UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR5          *((volatile unsigned int*)(0x42CEE314UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR6          *((volatile unsigned int*)(0x42CEE318UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR7          *((volatile unsigned int*)(0x42CEE31CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR8          *((volatile unsigned int*)(0x42CEE320UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR9          *((volatile unsigned int*)(0x42CEE324UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR10         *((volatile unsigned int*)(0x42CEE328UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR11         *((volatile unsigned int*)(0x42CEE32CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR12         *((volatile unsigned int*)(0x42CEE330UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR13         *((volatile unsigned int*)(0x42CEE334UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR14         *((volatile unsigned int*)(0x42CEE338UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR15         *((volatile unsigned int*)(0x42CEE33CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR16         *((volatile unsigned int*)(0x42CEE340UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR17         *((volatile unsigned int*)(0x42CEE344UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR18         *((volatile unsigned int*)(0x42CEE348UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR19         *((volatile unsigned int*)(0x42CEE34CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR20         *((volatile unsigned int*)(0x42CEE350UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR21         *((volatile unsigned int*)(0x42CEE354UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR22         *((volatile unsigned int*)(0x42CEE358UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR23         *((volatile unsigned int*)(0x42CEE35CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR24         *((volatile unsigned int*)(0x42CEE360UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR25         *((volatile unsigned int*)(0x42CEE364UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR26         *((volatile unsigned int*)(0x42CEE368UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR27         *((volatile unsigned int*)(0x42CEE36CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR28         *((volatile unsigned int*)(0x42CEE370UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR29         *((volatile unsigned int*)(0x42CEE374UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR30         *((volatile unsigned int*)(0x42CEE378UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR31         *((volatile unsigned int*)(0x42CEE37CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR0          *((volatile unsigned int*)(0x42CEE380UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR1          *((volatile unsigned int*)(0x42CEE384UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR2          *((volatile unsigned int*)(0x42CEE388UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR3          *((volatile unsigned int*)(0x42CEE38CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR4          *((volatile unsigned int*)(0x42CEE390UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR5          *((volatile unsigned int*)(0x42CEE394UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR6          *((volatile unsigned int*)(0x42CEE398UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR7          *((volatile unsigned int*)(0x42CEE39CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR8          *((volatile unsigned int*)(0x42CEE3A0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR9          *((volatile unsigned int*)(0x42CEE3A4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR10         *((volatile unsigned int*)(0x42CEE3A8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR11         *((volatile unsigned int*)(0x42CEE3ACUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR12         *((volatile unsigned int*)(0x42CEE3B0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR13         *((volatile unsigned int*)(0x42CEE3B4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR14         *((volatile unsigned int*)(0x42CEE3B8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR15         *((volatile unsigned int*)(0x42CEE3BCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR16         *((volatile unsigned int*)(0x42CEE3C0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR17         *((volatile unsigned int*)(0x42CEE3C4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR18         *((volatile unsigned int*)(0x42CEE3C8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR19         *((volatile unsigned int*)(0x42CEE3CCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR20         *((volatile unsigned int*)(0x42CEE3D0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR21         *((volatile unsigned int*)(0x42CEE3D4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR22         *((volatile unsigned int*)(0x42CEE3D8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR23         *((volatile unsigned int*)(0x42CEE3DCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR24         *((volatile unsigned int*)(0x42CEE3E0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR25         *((volatile unsigned int*)(0x42CEE3E4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR26         *((volatile unsigned int*)(0x42CEE3E8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR27         *((volatile unsigned int*)(0x42CEE3ECUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR28         *((volatile unsigned int*)(0x42CEE3F0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR29         *((volatile unsigned int*)(0x42CEE3F4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR30         *((volatile unsigned int*)(0x42CEE3F8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR31         *((volatile unsigned int*)(0x42CEE3FCUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR0          *((volatile unsigned int*)(0x42CEE400UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR1          *((volatile unsigned int*)(0x42CEE404UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR2          *((volatile unsigned int*)(0x42CEE408UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR3          *((volatile unsigned int*)(0x42CEE40CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR4          *((volatile unsigned int*)(0x42CEE410UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR5          *((volatile unsigned int*)(0x42CEE414UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR6          *((volatile unsigned int*)(0x42CEE418UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR7          *((volatile unsigned int*)(0x42CEE41CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR8          *((volatile unsigned int*)(0x42CEE420UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR9          *((volatile unsigned int*)(0x42CEE424UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR10         *((volatile unsigned int*)(0x42CEE428UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR11         *((volatile unsigned int*)(0x42CEE42CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR12         *((volatile unsigned int*)(0x42CEE430UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR13         *((volatile unsigned int*)(0x42CEE434UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR14         *((volatile unsigned int*)(0x42CEE438UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR15         *((volatile unsigned int*)(0x42CEE43CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR16         *((volatile unsigned int*)(0x42CEE440UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR17         *((volatile unsigned int*)(0x42CEE444UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR18         *((volatile unsigned int*)(0x42CEE448UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR19         *((volatile unsigned int*)(0x42CEE44CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR20         *((volatile unsigned int*)(0x42CEE450UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR21         *((volatile unsigned int*)(0x42CEE454UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR22         *((volatile unsigned int*)(0x42CEE458UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR23         *((volatile unsigned int*)(0x42CEE45CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR24         *((volatile unsigned int*)(0x42CEE460UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR25         *((volatile unsigned int*)(0x42CEE464UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR26         *((volatile unsigned int*)(0x42CEE468UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR27         *((volatile unsigned int*)(0x42CEE46CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR28         *((volatile unsigned int*)(0x42CEE470UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR29         *((volatile unsigned int*)(0x42CEE474UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR30         *((volatile unsigned int*)(0x42CEE478UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42CEE480UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42CEE484UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42CEE488UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42CEE48CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42CEE490UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42CEE494UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42CEE498UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42CEE49CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42CEE4A0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42CEE4A4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42CEE4A8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42CEE4ACUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42CEE4B0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42CEE4B4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42CEE4B8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42CEE4BCUL))
+#define bFM3_ETHERNET_MAC1_TSR_TSSOVF          *((volatile unsigned int*)(0x42CEE500UL))
+#define bFM3_ETHERNET_MAC1_TSR_TSTART          *((volatile unsigned int*)(0x42CEE504UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSTS           *((volatile unsigned int*)(0x42CEE508UL))
+#define bFM3_ETHERNET_MAC1_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSSTM          *((volatile unsigned int*)(0x42CEE560UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS0          *((volatile unsigned int*)(0x42CEE564UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS1          *((volatile unsigned int*)(0x42CEE568UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS2          *((volatile unsigned int*)(0x42CEE56CUL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42CEE580UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42CEE584UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42CEE588UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42CEE58CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN0           *((volatile unsigned int*)(0x42CEE600UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN1           *((volatile unsigned int*)(0x42CEE604UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN2           *((volatile unsigned int*)(0x42CEE608UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN3           *((volatile unsigned int*)(0x42CEE60CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN4           *((volatile unsigned int*)(0x42CEE610UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN5           *((volatile unsigned int*)(0x42CEE614UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN6           *((volatile unsigned int*)(0x42CEE618UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN7           *((volatile unsigned int*)(0x42CEE61CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN8           *((volatile unsigned int*)(0x42CEE620UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN9           *((volatile unsigned int*)(0x42CEE624UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN10          *((volatile unsigned int*)(0x42CEE628UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN11          *((volatile unsigned int*)(0x42CEE62CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN12          *((volatile unsigned int*)(0x42CEE630UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN13          *((volatile unsigned int*)(0x42CEE634UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN14          *((volatile unsigned int*)(0x42CEE638UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN15          *((volatile unsigned int*)(0x42CEE63CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN16          *((volatile unsigned int*)(0x42CEE640UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN17          *((volatile unsigned int*)(0x42CEE644UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN18          *((volatile unsigned int*)(0x42CEE648UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN19          *((volatile unsigned int*)(0x42CEE64CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN20          *((volatile unsigned int*)(0x42CEE650UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN21          *((volatile unsigned int*)(0x42CEE654UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN22          *((volatile unsigned int*)(0x42CEE658UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN23          *((volatile unsigned int*)(0x42CEE65CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN24          *((volatile unsigned int*)(0x42CEE660UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN25          *((volatile unsigned int*)(0x42CEE664UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN26          *((volatile unsigned int*)(0x42CEE668UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN27          *((volatile unsigned int*)(0x42CEE66CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN28          *((volatile unsigned int*)(0x42CEE670UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN29          *((volatile unsigned int*)(0x42CEE674UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN30          *((volatile unsigned int*)(0x42CEE678UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS0           *((volatile unsigned int*)(0x42CEE680UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS1           *((volatile unsigned int*)(0x42CEE684UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS2           *((volatile unsigned int*)(0x42CEE688UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS3           *((volatile unsigned int*)(0x42CEE68CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS4           *((volatile unsigned int*)(0x42CEE690UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS5           *((volatile unsigned int*)(0x42CEE694UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS6           *((volatile unsigned int*)(0x42CEE698UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS7           *((volatile unsigned int*)(0x42CEE69CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS8           *((volatile unsigned int*)(0x42CEE6A0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS9           *((volatile unsigned int*)(0x42CEE6A4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS10          *((volatile unsigned int*)(0x42CEE6A8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS11          *((volatile unsigned int*)(0x42CEE6ACUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS12          *((volatile unsigned int*)(0x42CEE6B0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS13          *((volatile unsigned int*)(0x42CEE6B4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS14          *((volatile unsigned int*)(0x42CEE6B8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS15          *((volatile unsigned int*)(0x42CEE6BCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS16          *((volatile unsigned int*)(0x42CEE6C0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS17          *((volatile unsigned int*)(0x42CEE6C4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS18          *((volatile unsigned int*)(0x42CEE6C8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS19          *((volatile unsigned int*)(0x42CEE6CCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS20          *((volatile unsigned int*)(0x42CEE6D0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS21          *((volatile unsigned int*)(0x42CEE6D4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS22          *((volatile unsigned int*)(0x42CEE6D8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS23          *((volatile unsigned int*)(0x42CEE6DCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS24          *((volatile unsigned int*)(0x42CEE6E0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS25          *((volatile unsigned int*)(0x42CEE6E4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS26          *((volatile unsigned int*)(0x42CEE6E8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS27          *((volatile unsigned int*)(0x42CEE6ECUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS28          *((volatile unsigned int*)(0x42CEE6F0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS29          *((volatile unsigned int*)(0x42CEE6F4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS30          *((volatile unsigned int*)(0x42CEE6F8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS31          *((volatile unsigned int*)(0x42CEE6FCUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A32          *((volatile unsigned int*)(0x42CF0000UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A33          *((volatile unsigned int*)(0x42CF0004UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A34          *((volatile unsigned int*)(0x42CF0008UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A35          *((volatile unsigned int*)(0x42CF000CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A36          *((volatile unsigned int*)(0x42CF0010UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A37          *((volatile unsigned int*)(0x42CF0014UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A38          *((volatile unsigned int*)(0x42CF0018UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A39          *((volatile unsigned int*)(0x42CF001CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A40          *((volatile unsigned int*)(0x42CF0020UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A41          *((volatile unsigned int*)(0x42CF0024UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A42          *((volatile unsigned int*)(0x42CF0028UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A43          *((volatile unsigned int*)(0x42CF002CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A44          *((volatile unsigned int*)(0x42CF0030UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A45          *((volatile unsigned int*)(0x42CF0034UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A46          *((volatile unsigned int*)(0x42CF0038UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A47          *((volatile unsigned int*)(0x42CF003CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC0         *((volatile unsigned int*)(0x42CF0060UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC1         *((volatile unsigned int*)(0x42CF0064UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC2         *((volatile unsigned int*)(0x42CF0068UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC3         *((volatile unsigned int*)(0x42CF006CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC4         *((volatile unsigned int*)(0x42CF0070UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC5         *((volatile unsigned int*)(0x42CF0074UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_SA           *((volatile unsigned int*)(0x42CF0078UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_AE           *((volatile unsigned int*)(0x42CF007CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A0           *((volatile unsigned int*)(0x42CF0080UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A1           *((volatile unsigned int*)(0x42CF0084UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A2           *((volatile unsigned int*)(0x42CF0088UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A3           *((volatile unsigned int*)(0x42CF008CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A4           *((volatile unsigned int*)(0x42CF0090UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A5           *((volatile unsigned int*)(0x42CF0094UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A6           *((volatile unsigned int*)(0x42CF0098UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A7           *((volatile unsigned int*)(0x42CF009CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A8           *((volatile unsigned int*)(0x42CF00A0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A9           *((volatile unsigned int*)(0x42CF00A4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A10          *((volatile unsigned int*)(0x42CF00A8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A11          *((volatile unsigned int*)(0x42CF00ACUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A12          *((volatile unsigned int*)(0x42CF00B0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A13          *((volatile unsigned int*)(0x42CF00B4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A14          *((volatile unsigned int*)(0x42CF00B8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A15          *((volatile unsigned int*)(0x42CF00BCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A16          *((volatile unsigned int*)(0x42CF00C0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A17          *((volatile unsigned int*)(0x42CF00C4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A18          *((volatile unsigned int*)(0x42CF00C8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A19          *((volatile unsigned int*)(0x42CF00CCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A20          *((volatile unsigned int*)(0x42CF00D0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A21          *((volatile unsigned int*)(0x42CF00D4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A22          *((volatile unsigned int*)(0x42CF00D8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A23          *((volatile unsigned int*)(0x42CF00DCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A24          *((volatile unsigned int*)(0x42CF00E0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A25          *((volatile unsigned int*)(0x42CF00E4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A26          *((volatile unsigned int*)(0x42CF00E8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A27          *((volatile unsigned int*)(0x42CF00ECUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A28          *((volatile unsigned int*)(0x42CF00F0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A29          *((volatile unsigned int*)(0x42CF00F4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A30          *((volatile unsigned int*)(0x42CF00F8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A31          *((volatile unsigned int*)(0x42CF00FCUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A32          *((volatile unsigned int*)(0x42CF0100UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A33          *((volatile unsigned int*)(0x42CF0104UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A34          *((volatile unsigned int*)(0x42CF0108UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A35          *((volatile unsigned int*)(0x42CF010CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A36          *((volatile unsigned int*)(0x42CF0110UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A37          *((volatile unsigned int*)(0x42CF0114UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A38          *((volatile unsigned int*)(0x42CF0118UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A39          *((volatile unsigned int*)(0x42CF011CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A40          *((volatile unsigned int*)(0x42CF0120UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A41          *((volatile unsigned int*)(0x42CF0124UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A42          *((volatile unsigned int*)(0x42CF0128UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A43          *((volatile unsigned int*)(0x42CF012CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A44          *((volatile unsigned int*)(0x42CF0130UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A45          *((volatile unsigned int*)(0x42CF0134UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A46          *((volatile unsigned int*)(0x42CF0138UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A47          *((volatile unsigned int*)(0x42CF013CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC0         *((volatile unsigned int*)(0x42CF0160UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC1         *((volatile unsigned int*)(0x42CF0164UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC2         *((volatile unsigned int*)(0x42CF0168UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC3         *((volatile unsigned int*)(0x42CF016CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC4         *((volatile unsigned int*)(0x42CF0170UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC5         *((volatile unsigned int*)(0x42CF0174UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_SA           *((volatile unsigned int*)(0x42CF0178UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_AE           *((volatile unsigned int*)(0x42CF017CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A0           *((volatile unsigned int*)(0x42CF0180UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A1           *((volatile unsigned int*)(0x42CF0184UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A2           *((volatile unsigned int*)(0x42CF0188UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A3           *((volatile unsigned int*)(0x42CF018CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A4           *((volatile unsigned int*)(0x42CF0190UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A5           *((volatile unsigned int*)(0x42CF0194UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A6           *((volatile unsigned int*)(0x42CF0198UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A7           *((volatile unsigned int*)(0x42CF019CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A8           *((volatile unsigned int*)(0x42CF01A0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A9           *((volatile unsigned int*)(0x42CF01A4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A10          *((volatile unsigned int*)(0x42CF01A8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A11          *((volatile unsigned int*)(0x42CF01ACUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A12          *((volatile unsigned int*)(0x42CF01B0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A13          *((volatile unsigned int*)(0x42CF01B4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A14          *((volatile unsigned int*)(0x42CF01B8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A15          *((volatile unsigned int*)(0x42CF01BCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A16          *((volatile unsigned int*)(0x42CF01C0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A17          *((volatile unsigned int*)(0x42CF01C4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A18          *((volatile unsigned int*)(0x42CF01C8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A19          *((volatile unsigned int*)(0x42CF01CCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A20          *((volatile unsigned int*)(0x42CF01D0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A21          *((volatile unsigned int*)(0x42CF01D4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A22          *((volatile unsigned int*)(0x42CF01D8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A23          *((volatile unsigned int*)(0x42CF01DCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A24          *((volatile unsigned int*)(0x42CF01E0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A25          *((volatile unsigned int*)(0x42CF01E4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A26          *((volatile unsigned int*)(0x42CF01E8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A27          *((volatile unsigned int*)(0x42CF01ECUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A28          *((volatile unsigned int*)(0x42CF01F0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A29          *((volatile unsigned int*)(0x42CF01F4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A30          *((volatile unsigned int*)(0x42CF01F8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A31          *((volatile unsigned int*)(0x42CF01FCUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A32          *((volatile unsigned int*)(0x42CF0200UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A33          *((volatile unsigned int*)(0x42CF0204UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A34          *((volatile unsigned int*)(0x42CF0208UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A35          *((volatile unsigned int*)(0x42CF020CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A36          *((volatile unsigned int*)(0x42CF0210UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A37          *((volatile unsigned int*)(0x42CF0214UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A38          *((volatile unsigned int*)(0x42CF0218UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A39          *((volatile unsigned int*)(0x42CF021CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A40          *((volatile unsigned int*)(0x42CF0220UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A41          *((volatile unsigned int*)(0x42CF0224UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A42          *((volatile unsigned int*)(0x42CF0228UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A43          *((volatile unsigned int*)(0x42CF022CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A44          *((volatile unsigned int*)(0x42CF0230UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A45          *((volatile unsigned int*)(0x42CF0234UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A46          *((volatile unsigned int*)(0x42CF0238UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A47          *((volatile unsigned int*)(0x42CF023CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC0         *((volatile unsigned int*)(0x42CF0260UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC1         *((volatile unsigned int*)(0x42CF0264UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC2         *((volatile unsigned int*)(0x42CF0268UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC3         *((volatile unsigned int*)(0x42CF026CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC4         *((volatile unsigned int*)(0x42CF0270UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC5         *((volatile unsigned int*)(0x42CF0274UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_SA           *((volatile unsigned int*)(0x42CF0278UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_AE           *((volatile unsigned int*)(0x42CF027CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A0           *((volatile unsigned int*)(0x42CF0280UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A1           *((volatile unsigned int*)(0x42CF0284UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A2           *((volatile unsigned int*)(0x42CF0288UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A3           *((volatile unsigned int*)(0x42CF028CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A4           *((volatile unsigned int*)(0x42CF0290UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A5           *((volatile unsigned int*)(0x42CF0294UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A6           *((volatile unsigned int*)(0x42CF0298UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A7           *((volatile unsigned int*)(0x42CF029CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A8           *((volatile unsigned int*)(0x42CF02A0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A9           *((volatile unsigned int*)(0x42CF02A4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A10          *((volatile unsigned int*)(0x42CF02A8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A11          *((volatile unsigned int*)(0x42CF02ACUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A12          *((volatile unsigned int*)(0x42CF02B0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A13          *((volatile unsigned int*)(0x42CF02B4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A14          *((volatile unsigned int*)(0x42CF02B8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A15          *((volatile unsigned int*)(0x42CF02BCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A16          *((volatile unsigned int*)(0x42CF02C0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A17          *((volatile unsigned int*)(0x42CF02C4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A18          *((volatile unsigned int*)(0x42CF02C8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A19          *((volatile unsigned int*)(0x42CF02CCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A20          *((volatile unsigned int*)(0x42CF02D0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A21          *((volatile unsigned int*)(0x42CF02D4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A22          *((volatile unsigned int*)(0x42CF02D8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A23          *((volatile unsigned int*)(0x42CF02DCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A24          *((volatile unsigned int*)(0x42CF02E0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A25          *((volatile unsigned int*)(0x42CF02E4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A26          *((volatile unsigned int*)(0x42CF02E8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A27          *((volatile unsigned int*)(0x42CF02ECUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A28          *((volatile unsigned int*)(0x42CF02F0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A29          *((volatile unsigned int*)(0x42CF02F4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A30          *((volatile unsigned int*)(0x42CF02F8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A31          *((volatile unsigned int*)(0x42CF02FCUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A32          *((volatile unsigned int*)(0x42CF0300UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A33          *((volatile unsigned int*)(0x42CF0304UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A34          *((volatile unsigned int*)(0x42CF0308UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A35          *((volatile unsigned int*)(0x42CF030CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A36          *((volatile unsigned int*)(0x42CF0310UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A37          *((volatile unsigned int*)(0x42CF0314UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A38          *((volatile unsigned int*)(0x42CF0318UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A39          *((volatile unsigned int*)(0x42CF031CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A40          *((volatile unsigned int*)(0x42CF0320UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A41          *((volatile unsigned int*)(0x42CF0324UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A42          *((volatile unsigned int*)(0x42CF0328UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A43          *((volatile unsigned int*)(0x42CF032CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A44          *((volatile unsigned int*)(0x42CF0330UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A45          *((volatile unsigned int*)(0x42CF0334UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A46          *((volatile unsigned int*)(0x42CF0338UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A47          *((volatile unsigned int*)(0x42CF033CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC0         *((volatile unsigned int*)(0x42CF0360UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC1         *((volatile unsigned int*)(0x42CF0364UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC2         *((volatile unsigned int*)(0x42CF0368UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC3         *((volatile unsigned int*)(0x42CF036CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC4         *((volatile unsigned int*)(0x42CF0370UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC5         *((volatile unsigned int*)(0x42CF0374UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_SA           *((volatile unsigned int*)(0x42CF0378UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_AE           *((volatile unsigned int*)(0x42CF037CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A0           *((volatile unsigned int*)(0x42CF0380UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A1           *((volatile unsigned int*)(0x42CF0384UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A2           *((volatile unsigned int*)(0x42CF0388UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A3           *((volatile unsigned int*)(0x42CF038CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A4           *((volatile unsigned int*)(0x42CF0390UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A5           *((volatile unsigned int*)(0x42CF0394UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A6           *((volatile unsigned int*)(0x42CF0398UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A7           *((volatile unsigned int*)(0x42CF039CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A8           *((volatile unsigned int*)(0x42CF03A0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A9           *((volatile unsigned int*)(0x42CF03A4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A10          *((volatile unsigned int*)(0x42CF03A8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A11          *((volatile unsigned int*)(0x42CF03ACUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A12          *((volatile unsigned int*)(0x42CF03B0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A13          *((volatile unsigned int*)(0x42CF03B4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A14          *((volatile unsigned int*)(0x42CF03B8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A15          *((volatile unsigned int*)(0x42CF03BCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A16          *((volatile unsigned int*)(0x42CF03C0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A17          *((volatile unsigned int*)(0x42CF03C4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A18          *((volatile unsigned int*)(0x42CF03C8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A19          *((volatile unsigned int*)(0x42CF03CCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A20          *((volatile unsigned int*)(0x42CF03D0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A21          *((volatile unsigned int*)(0x42CF03D4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A22          *((volatile unsigned int*)(0x42CF03D8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A23          *((volatile unsigned int*)(0x42CF03DCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A24          *((volatile unsigned int*)(0x42CF03E0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A25          *((volatile unsigned int*)(0x42CF03E4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A26          *((volatile unsigned int*)(0x42CF03E8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A27          *((volatile unsigned int*)(0x42CF03ECUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A28          *((volatile unsigned int*)(0x42CF03F0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A29          *((volatile unsigned int*)(0x42CF03F4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A30          *((volatile unsigned int*)(0x42CF03F8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A31          *((volatile unsigned int*)(0x42CF03FCUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A32          *((volatile unsigned int*)(0x42CF0400UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A33          *((volatile unsigned int*)(0x42CF0404UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A34          *((volatile unsigned int*)(0x42CF0408UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A35          *((volatile unsigned int*)(0x42CF040CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A36          *((volatile unsigned int*)(0x42CF0410UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A37          *((volatile unsigned int*)(0x42CF0414UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A38          *((volatile unsigned int*)(0x42CF0418UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A39          *((volatile unsigned int*)(0x42CF041CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A40          *((volatile unsigned int*)(0x42CF0420UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A41          *((volatile unsigned int*)(0x42CF0424UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A42          *((volatile unsigned int*)(0x42CF0428UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A43          *((volatile unsigned int*)(0x42CF042CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A44          *((volatile unsigned int*)(0x42CF0430UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A45          *((volatile unsigned int*)(0x42CF0434UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A46          *((volatile unsigned int*)(0x42CF0438UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A47          *((volatile unsigned int*)(0x42CF043CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC0         *((volatile unsigned int*)(0x42CF0460UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC1         *((volatile unsigned int*)(0x42CF0464UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC2         *((volatile unsigned int*)(0x42CF0468UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC3         *((volatile unsigned int*)(0x42CF046CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC4         *((volatile unsigned int*)(0x42CF0470UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC5         *((volatile unsigned int*)(0x42CF0474UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_SA           *((volatile unsigned int*)(0x42CF0478UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_AE           *((volatile unsigned int*)(0x42CF047CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A0           *((volatile unsigned int*)(0x42CF0480UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A1           *((volatile unsigned int*)(0x42CF0484UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A2           *((volatile unsigned int*)(0x42CF0488UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A3           *((volatile unsigned int*)(0x42CF048CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A4           *((volatile unsigned int*)(0x42CF0490UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A5           *((volatile unsigned int*)(0x42CF0494UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A6           *((volatile unsigned int*)(0x42CF0498UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A7           *((volatile unsigned int*)(0x42CF049CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A8           *((volatile unsigned int*)(0x42CF04A0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A9           *((volatile unsigned int*)(0x42CF04A4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A10          *((volatile unsigned int*)(0x42CF04A8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A11          *((volatile unsigned int*)(0x42CF04ACUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A12          *((volatile unsigned int*)(0x42CF04B0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A13          *((volatile unsigned int*)(0x42CF04B4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A14          *((volatile unsigned int*)(0x42CF04B8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A15          *((volatile unsigned int*)(0x42CF04BCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A16          *((volatile unsigned int*)(0x42CF04C0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A17          *((volatile unsigned int*)(0x42CF04C4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A18          *((volatile unsigned int*)(0x42CF04C8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A19          *((volatile unsigned int*)(0x42CF04CCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A20          *((volatile unsigned int*)(0x42CF04D0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A21          *((volatile unsigned int*)(0x42CF04D4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A22          *((volatile unsigned int*)(0x42CF04D8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A23          *((volatile unsigned int*)(0x42CF04DCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A24          *((volatile unsigned int*)(0x42CF04E0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A25          *((volatile unsigned int*)(0x42CF04E4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A26          *((volatile unsigned int*)(0x42CF04E8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A27          *((volatile unsigned int*)(0x42CF04ECUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A28          *((volatile unsigned int*)(0x42CF04F0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A29          *((volatile unsigned int*)(0x42CF04F4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A30          *((volatile unsigned int*)(0x42CF04F8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A31          *((volatile unsigned int*)(0x42CF04FCUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A32          *((volatile unsigned int*)(0x42CF0500UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A33          *((volatile unsigned int*)(0x42CF0504UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A34          *((volatile unsigned int*)(0x42CF0508UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A35          *((volatile unsigned int*)(0x42CF050CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A36          *((volatile unsigned int*)(0x42CF0510UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A37          *((volatile unsigned int*)(0x42CF0514UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A38          *((volatile unsigned int*)(0x42CF0518UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A39          *((volatile unsigned int*)(0x42CF051CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A40          *((volatile unsigned int*)(0x42CF0520UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A41          *((volatile unsigned int*)(0x42CF0524UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A42          *((volatile unsigned int*)(0x42CF0528UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A43          *((volatile unsigned int*)(0x42CF052CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A44          *((volatile unsigned int*)(0x42CF0530UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A45          *((volatile unsigned int*)(0x42CF0534UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A46          *((volatile unsigned int*)(0x42CF0538UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A47          *((volatile unsigned int*)(0x42CF053CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC0         *((volatile unsigned int*)(0x42CF0560UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC1         *((volatile unsigned int*)(0x42CF0564UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC2         *((volatile unsigned int*)(0x42CF0568UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC3         *((volatile unsigned int*)(0x42CF056CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC4         *((volatile unsigned int*)(0x42CF0570UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC5         *((volatile unsigned int*)(0x42CF0574UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_SA           *((volatile unsigned int*)(0x42CF0578UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_AE           *((volatile unsigned int*)(0x42CF057CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A0           *((volatile unsigned int*)(0x42CF0580UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A1           *((volatile unsigned int*)(0x42CF0584UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A2           *((volatile unsigned int*)(0x42CF0588UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A3           *((volatile unsigned int*)(0x42CF058CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A4           *((volatile unsigned int*)(0x42CF0590UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A5           *((volatile unsigned int*)(0x42CF0594UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A6           *((volatile unsigned int*)(0x42CF0598UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A7           *((volatile unsigned int*)(0x42CF059CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A8           *((volatile unsigned int*)(0x42CF05A0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A9           *((volatile unsigned int*)(0x42CF05A4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A10          *((volatile unsigned int*)(0x42CF05A8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A11          *((volatile unsigned int*)(0x42CF05ACUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A12          *((volatile unsigned int*)(0x42CF05B0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A13          *((volatile unsigned int*)(0x42CF05B4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A14          *((volatile unsigned int*)(0x42CF05B8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A15          *((volatile unsigned int*)(0x42CF05BCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A16          *((volatile unsigned int*)(0x42CF05C0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A17          *((volatile unsigned int*)(0x42CF05C4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A18          *((volatile unsigned int*)(0x42CF05C8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A19          *((volatile unsigned int*)(0x42CF05CCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A20          *((volatile unsigned int*)(0x42CF05D0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A21          *((volatile unsigned int*)(0x42CF05D4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A22          *((volatile unsigned int*)(0x42CF05D8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A23          *((volatile unsigned int*)(0x42CF05DCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A24          *((volatile unsigned int*)(0x42CF05E0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A25          *((volatile unsigned int*)(0x42CF05E4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A26          *((volatile unsigned int*)(0x42CF05E8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A27          *((volatile unsigned int*)(0x42CF05ECUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A28          *((volatile unsigned int*)(0x42CF05F0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A29          *((volatile unsigned int*)(0x42CF05F4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A30          *((volatile unsigned int*)(0x42CF05F8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A31          *((volatile unsigned int*)(0x42CF05FCUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A32          *((volatile unsigned int*)(0x42CF0600UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A33          *((volatile unsigned int*)(0x42CF0604UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A34          *((volatile unsigned int*)(0x42CF0608UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A35          *((volatile unsigned int*)(0x42CF060CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A36          *((volatile unsigned int*)(0x42CF0610UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A37          *((volatile unsigned int*)(0x42CF0614UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A38          *((volatile unsigned int*)(0x42CF0618UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A39          *((volatile unsigned int*)(0x42CF061CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A40          *((volatile unsigned int*)(0x42CF0620UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A41          *((volatile unsigned int*)(0x42CF0624UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A42          *((volatile unsigned int*)(0x42CF0628UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A43          *((volatile unsigned int*)(0x42CF062CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A44          *((volatile unsigned int*)(0x42CF0630UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A45          *((volatile unsigned int*)(0x42CF0634UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A46          *((volatile unsigned int*)(0x42CF0638UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A47          *((volatile unsigned int*)(0x42CF063CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC0         *((volatile unsigned int*)(0x42CF0660UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC1         *((volatile unsigned int*)(0x42CF0664UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC2         *((volatile unsigned int*)(0x42CF0668UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC3         *((volatile unsigned int*)(0x42CF066CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC4         *((volatile unsigned int*)(0x42CF0670UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC5         *((volatile unsigned int*)(0x42CF0674UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_SA           *((volatile unsigned int*)(0x42CF0678UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_AE           *((volatile unsigned int*)(0x42CF067CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A0           *((volatile unsigned int*)(0x42CF0680UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A1           *((volatile unsigned int*)(0x42CF0684UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A2           *((volatile unsigned int*)(0x42CF0688UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A3           *((volatile unsigned int*)(0x42CF068CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A4           *((volatile unsigned int*)(0x42CF0690UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A5           *((volatile unsigned int*)(0x42CF0694UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A6           *((volatile unsigned int*)(0x42CF0698UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A7           *((volatile unsigned int*)(0x42CF069CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A8           *((volatile unsigned int*)(0x42CF06A0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A9           *((volatile unsigned int*)(0x42CF06A4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A10          *((volatile unsigned int*)(0x42CF06A8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A11          *((volatile unsigned int*)(0x42CF06ACUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A12          *((volatile unsigned int*)(0x42CF06B0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A13          *((volatile unsigned int*)(0x42CF06B4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A14          *((volatile unsigned int*)(0x42CF06B8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A15          *((volatile unsigned int*)(0x42CF06BCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A16          *((volatile unsigned int*)(0x42CF06C0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A17          *((volatile unsigned int*)(0x42CF06C4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A18          *((volatile unsigned int*)(0x42CF06C8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A19          *((volatile unsigned int*)(0x42CF06CCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A20          *((volatile unsigned int*)(0x42CF06D0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A21          *((volatile unsigned int*)(0x42CF06D4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A22          *((volatile unsigned int*)(0x42CF06D8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A23          *((volatile unsigned int*)(0x42CF06DCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A24          *((volatile unsigned int*)(0x42CF06E0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A25          *((volatile unsigned int*)(0x42CF06E4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A26          *((volatile unsigned int*)(0x42CF06E8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A27          *((volatile unsigned int*)(0x42CF06ECUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A28          *((volatile unsigned int*)(0x42CF06F0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A29          *((volatile unsigned int*)(0x42CF06F4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A30          *((volatile unsigned int*)(0x42CF06F8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A31          *((volatile unsigned int*)(0x42CF06FCUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A32          *((volatile unsigned int*)(0x42CF0700UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A33          *((volatile unsigned int*)(0x42CF0704UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A34          *((volatile unsigned int*)(0x42CF0708UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A35          *((volatile unsigned int*)(0x42CF070CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A36          *((volatile unsigned int*)(0x42CF0710UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A37          *((volatile unsigned int*)(0x42CF0714UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A38          *((volatile unsigned int*)(0x42CF0718UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A39          *((volatile unsigned int*)(0x42CF071CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A40          *((volatile unsigned int*)(0x42CF0720UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A41          *((volatile unsigned int*)(0x42CF0724UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A42          *((volatile unsigned int*)(0x42CF0728UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A43          *((volatile unsigned int*)(0x42CF072CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A44          *((volatile unsigned int*)(0x42CF0730UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A45          *((volatile unsigned int*)(0x42CF0734UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A46          *((volatile unsigned int*)(0x42CF0738UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A47          *((volatile unsigned int*)(0x42CF073CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC0         *((volatile unsigned int*)(0x42CF0760UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC1         *((volatile unsigned int*)(0x42CF0764UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC2         *((volatile unsigned int*)(0x42CF0768UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC3         *((volatile unsigned int*)(0x42CF076CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC4         *((volatile unsigned int*)(0x42CF0770UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC5         *((volatile unsigned int*)(0x42CF0774UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_SA           *((volatile unsigned int*)(0x42CF0778UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_AE           *((volatile unsigned int*)(0x42CF077CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A0           *((volatile unsigned int*)(0x42CF0780UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A1           *((volatile unsigned int*)(0x42CF0784UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A2           *((volatile unsigned int*)(0x42CF0788UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A3           *((volatile unsigned int*)(0x42CF078CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A4           *((volatile unsigned int*)(0x42CF0790UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A5           *((volatile unsigned int*)(0x42CF0794UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A6           *((volatile unsigned int*)(0x42CF0798UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A7           *((volatile unsigned int*)(0x42CF079CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A8           *((volatile unsigned int*)(0x42CF07A0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A9           *((volatile unsigned int*)(0x42CF07A4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A10          *((volatile unsigned int*)(0x42CF07A8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A11          *((volatile unsigned int*)(0x42CF07ACUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A12          *((volatile unsigned int*)(0x42CF07B0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A13          *((volatile unsigned int*)(0x42CF07B4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A14          *((volatile unsigned int*)(0x42CF07B8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A15          *((volatile unsigned int*)(0x42CF07BCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A16          *((volatile unsigned int*)(0x42CF07C0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A17          *((volatile unsigned int*)(0x42CF07C4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A18          *((volatile unsigned int*)(0x42CF07C8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A19          *((volatile unsigned int*)(0x42CF07CCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A20          *((volatile unsigned int*)(0x42CF07D0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A21          *((volatile unsigned int*)(0x42CF07D4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A22          *((volatile unsigned int*)(0x42CF07D8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A23          *((volatile unsigned int*)(0x42CF07DCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A24          *((volatile unsigned int*)(0x42CF07E0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A25          *((volatile unsigned int*)(0x42CF07E4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A26          *((volatile unsigned int*)(0x42CF07E8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A27          *((volatile unsigned int*)(0x42CF07ECUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A28          *((volatile unsigned int*)(0x42CF07F0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A29          *((volatile unsigned int*)(0x42CF07F4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A30          *((volatile unsigned int*)(0x42CF07F8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A31          *((volatile unsigned int*)(0x42CF07FCUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A32          *((volatile unsigned int*)(0x42CF0800UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A33          *((volatile unsigned int*)(0x42CF0804UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A34          *((volatile unsigned int*)(0x42CF0808UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A35          *((volatile unsigned int*)(0x42CF080CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A36          *((volatile unsigned int*)(0x42CF0810UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A37          *((volatile unsigned int*)(0x42CF0814UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A38          *((volatile unsigned int*)(0x42CF0818UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A39          *((volatile unsigned int*)(0x42CF081CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A40          *((volatile unsigned int*)(0x42CF0820UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A41          *((volatile unsigned int*)(0x42CF0824UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A42          *((volatile unsigned int*)(0x42CF0828UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A43          *((volatile unsigned int*)(0x42CF082CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A44          *((volatile unsigned int*)(0x42CF0830UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A45          *((volatile unsigned int*)(0x42CF0834UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A46          *((volatile unsigned int*)(0x42CF0838UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A47          *((volatile unsigned int*)(0x42CF083CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC0         *((volatile unsigned int*)(0x42CF0860UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC1         *((volatile unsigned int*)(0x42CF0864UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC2         *((volatile unsigned int*)(0x42CF0868UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC3         *((volatile unsigned int*)(0x42CF086CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC4         *((volatile unsigned int*)(0x42CF0870UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC5         *((volatile unsigned int*)(0x42CF0874UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_SA           *((volatile unsigned int*)(0x42CF0878UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_AE           *((volatile unsigned int*)(0x42CF087CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A0           *((volatile unsigned int*)(0x42CF0880UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A1           *((volatile unsigned int*)(0x42CF0884UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A2           *((volatile unsigned int*)(0x42CF0888UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A3           *((volatile unsigned int*)(0x42CF088CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A4           *((volatile unsigned int*)(0x42CF0890UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A5           *((volatile unsigned int*)(0x42CF0894UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A6           *((volatile unsigned int*)(0x42CF0898UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A7           *((volatile unsigned int*)(0x42CF089CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A8           *((volatile unsigned int*)(0x42CF08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A9           *((volatile unsigned int*)(0x42CF08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A10          *((volatile unsigned int*)(0x42CF08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A11          *((volatile unsigned int*)(0x42CF08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A12          *((volatile unsigned int*)(0x42CF08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A13          *((volatile unsigned int*)(0x42CF08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A14          *((volatile unsigned int*)(0x42CF08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A15          *((volatile unsigned int*)(0x42CF08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A16          *((volatile unsigned int*)(0x42CF08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A17          *((volatile unsigned int*)(0x42CF08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A18          *((volatile unsigned int*)(0x42CF08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A19          *((volatile unsigned int*)(0x42CF08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A20          *((volatile unsigned int*)(0x42CF08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A21          *((volatile unsigned int*)(0x42CF08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A22          *((volatile unsigned int*)(0x42CF08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A23          *((volatile unsigned int*)(0x42CF08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A24          *((volatile unsigned int*)(0x42CF08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A25          *((volatile unsigned int*)(0x42CF08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A26          *((volatile unsigned int*)(0x42CF08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A27          *((volatile unsigned int*)(0x42CF08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A28          *((volatile unsigned int*)(0x42CF08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A29          *((volatile unsigned int*)(0x42CF08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A30          *((volatile unsigned int*)(0x42CF08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A31          *((volatile unsigned int*)(0x42CF08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A32          *((volatile unsigned int*)(0x42CF0900UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A33          *((volatile unsigned int*)(0x42CF0904UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A34          *((volatile unsigned int*)(0x42CF0908UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A35          *((volatile unsigned int*)(0x42CF090CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A36          *((volatile unsigned int*)(0x42CF0910UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A37          *((volatile unsigned int*)(0x42CF0914UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A38          *((volatile unsigned int*)(0x42CF0918UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A39          *((volatile unsigned int*)(0x42CF091CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A40          *((volatile unsigned int*)(0x42CF0920UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A41          *((volatile unsigned int*)(0x42CF0924UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A42          *((volatile unsigned int*)(0x42CF0928UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A43          *((volatile unsigned int*)(0x42CF092CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A44          *((volatile unsigned int*)(0x42CF0930UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A45          *((volatile unsigned int*)(0x42CF0934UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A46          *((volatile unsigned int*)(0x42CF0938UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A47          *((volatile unsigned int*)(0x42CF093CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC0         *((volatile unsigned int*)(0x42CF0960UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC1         *((volatile unsigned int*)(0x42CF0964UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC2         *((volatile unsigned int*)(0x42CF0968UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC3         *((volatile unsigned int*)(0x42CF096CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC4         *((volatile unsigned int*)(0x42CF0970UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC5         *((volatile unsigned int*)(0x42CF0974UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_SA           *((volatile unsigned int*)(0x42CF0978UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_AE           *((volatile unsigned int*)(0x42CF097CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A0           *((volatile unsigned int*)(0x42CF0980UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A1           *((volatile unsigned int*)(0x42CF0984UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A2           *((volatile unsigned int*)(0x42CF0988UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A3           *((volatile unsigned int*)(0x42CF098CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A4           *((volatile unsigned int*)(0x42CF0990UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A5           *((volatile unsigned int*)(0x42CF0994UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A6           *((volatile unsigned int*)(0x42CF0998UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A7           *((volatile unsigned int*)(0x42CF099CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A8           *((volatile unsigned int*)(0x42CF09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A9           *((volatile unsigned int*)(0x42CF09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A10          *((volatile unsigned int*)(0x42CF09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A11          *((volatile unsigned int*)(0x42CF09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A12          *((volatile unsigned int*)(0x42CF09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A13          *((volatile unsigned int*)(0x42CF09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A14          *((volatile unsigned int*)(0x42CF09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A15          *((volatile unsigned int*)(0x42CF09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A16          *((volatile unsigned int*)(0x42CF09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A17          *((volatile unsigned int*)(0x42CF09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A18          *((volatile unsigned int*)(0x42CF09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A19          *((volatile unsigned int*)(0x42CF09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A20          *((volatile unsigned int*)(0x42CF09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A21          *((volatile unsigned int*)(0x42CF09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A22          *((volatile unsigned int*)(0x42CF09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A23          *((volatile unsigned int*)(0x42CF09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A24          *((volatile unsigned int*)(0x42CF09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A25          *((volatile unsigned int*)(0x42CF09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A26          *((volatile unsigned int*)(0x42CF09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A27          *((volatile unsigned int*)(0x42CF09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A28          *((volatile unsigned int*)(0x42CF09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A29          *((volatile unsigned int*)(0x42CF09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A30          *((volatile unsigned int*)(0x42CF09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A31          *((volatile unsigned int*)(0x42CF09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A32          *((volatile unsigned int*)(0x42CF0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A33          *((volatile unsigned int*)(0x42CF0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A34          *((volatile unsigned int*)(0x42CF0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A35          *((volatile unsigned int*)(0x42CF0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A36          *((volatile unsigned int*)(0x42CF0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A37          *((volatile unsigned int*)(0x42CF0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A38          *((volatile unsigned int*)(0x42CF0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A39          *((volatile unsigned int*)(0x42CF0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A40          *((volatile unsigned int*)(0x42CF0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A41          *((volatile unsigned int*)(0x42CF0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A42          *((volatile unsigned int*)(0x42CF0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A43          *((volatile unsigned int*)(0x42CF0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A44          *((volatile unsigned int*)(0x42CF0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A45          *((volatile unsigned int*)(0x42CF0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A46          *((volatile unsigned int*)(0x42CF0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A47          *((volatile unsigned int*)(0x42CF0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC0         *((volatile unsigned int*)(0x42CF0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC1         *((volatile unsigned int*)(0x42CF0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC2         *((volatile unsigned int*)(0x42CF0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC3         *((volatile unsigned int*)(0x42CF0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC4         *((volatile unsigned int*)(0x42CF0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC5         *((volatile unsigned int*)(0x42CF0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_SA           *((volatile unsigned int*)(0x42CF0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_AE           *((volatile unsigned int*)(0x42CF0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A0           *((volatile unsigned int*)(0x42CF0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A1           *((volatile unsigned int*)(0x42CF0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A2           *((volatile unsigned int*)(0x42CF0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A3           *((volatile unsigned int*)(0x42CF0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A4           *((volatile unsigned int*)(0x42CF0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A5           *((volatile unsigned int*)(0x42CF0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A6           *((volatile unsigned int*)(0x42CF0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A7           *((volatile unsigned int*)(0x42CF0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A8           *((volatile unsigned int*)(0x42CF0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A9           *((volatile unsigned int*)(0x42CF0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A10          *((volatile unsigned int*)(0x42CF0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A11          *((volatile unsigned int*)(0x42CF0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A12          *((volatile unsigned int*)(0x42CF0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A13          *((volatile unsigned int*)(0x42CF0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A14          *((volatile unsigned int*)(0x42CF0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A15          *((volatile unsigned int*)(0x42CF0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A16          *((volatile unsigned int*)(0x42CF0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A17          *((volatile unsigned int*)(0x42CF0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A18          *((volatile unsigned int*)(0x42CF0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A19          *((volatile unsigned int*)(0x42CF0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A20          *((volatile unsigned int*)(0x42CF0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A21          *((volatile unsigned int*)(0x42CF0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A22          *((volatile unsigned int*)(0x42CF0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A23          *((volatile unsigned int*)(0x42CF0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A24          *((volatile unsigned int*)(0x42CF0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A25          *((volatile unsigned int*)(0x42CF0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A26          *((volatile unsigned int*)(0x42CF0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A27          *((volatile unsigned int*)(0x42CF0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A28          *((volatile unsigned int*)(0x42CF0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A29          *((volatile unsigned int*)(0x42CF0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A30          *((volatile unsigned int*)(0x42CF0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A31          *((volatile unsigned int*)(0x42CF0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A32          *((volatile unsigned int*)(0x42CF0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A33          *((volatile unsigned int*)(0x42CF0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A34          *((volatile unsigned int*)(0x42CF0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A35          *((volatile unsigned int*)(0x42CF0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A36          *((volatile unsigned int*)(0x42CF0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A37          *((volatile unsigned int*)(0x42CF0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A38          *((volatile unsigned int*)(0x42CF0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A39          *((volatile unsigned int*)(0x42CF0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A40          *((volatile unsigned int*)(0x42CF0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A41          *((volatile unsigned int*)(0x42CF0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A42          *((volatile unsigned int*)(0x42CF0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A43          *((volatile unsigned int*)(0x42CF0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A44          *((volatile unsigned int*)(0x42CF0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A45          *((volatile unsigned int*)(0x42CF0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A46          *((volatile unsigned int*)(0x42CF0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A47          *((volatile unsigned int*)(0x42CF0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC0         *((volatile unsigned int*)(0x42CF0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC1         *((volatile unsigned int*)(0x42CF0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC2         *((volatile unsigned int*)(0x42CF0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC3         *((volatile unsigned int*)(0x42CF0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC4         *((volatile unsigned int*)(0x42CF0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC5         *((volatile unsigned int*)(0x42CF0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_SA           *((volatile unsigned int*)(0x42CF0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_AE           *((volatile unsigned int*)(0x42CF0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A0           *((volatile unsigned int*)(0x42CF0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A1           *((volatile unsigned int*)(0x42CF0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A2           *((volatile unsigned int*)(0x42CF0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A3           *((volatile unsigned int*)(0x42CF0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A4           *((volatile unsigned int*)(0x42CF0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A5           *((volatile unsigned int*)(0x42CF0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A6           *((volatile unsigned int*)(0x42CF0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A7           *((volatile unsigned int*)(0x42CF0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A8           *((volatile unsigned int*)(0x42CF0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A9           *((volatile unsigned int*)(0x42CF0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A10          *((volatile unsigned int*)(0x42CF0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A11          *((volatile unsigned int*)(0x42CF0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A12          *((volatile unsigned int*)(0x42CF0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A13          *((volatile unsigned int*)(0x42CF0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A14          *((volatile unsigned int*)(0x42CF0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A15          *((volatile unsigned int*)(0x42CF0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A16          *((volatile unsigned int*)(0x42CF0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A17          *((volatile unsigned int*)(0x42CF0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A18          *((volatile unsigned int*)(0x42CF0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A19          *((volatile unsigned int*)(0x42CF0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A20          *((volatile unsigned int*)(0x42CF0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A21          *((volatile unsigned int*)(0x42CF0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A22          *((volatile unsigned int*)(0x42CF0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A23          *((volatile unsigned int*)(0x42CF0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A24          *((volatile unsigned int*)(0x42CF0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A25          *((volatile unsigned int*)(0x42CF0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A26          *((volatile unsigned int*)(0x42CF0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A27          *((volatile unsigned int*)(0x42CF0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A28          *((volatile unsigned int*)(0x42CF0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A29          *((volatile unsigned int*)(0x42CF0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A30          *((volatile unsigned int*)(0x42CF0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A31          *((volatile unsigned int*)(0x42CF0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A32          *((volatile unsigned int*)(0x42CF0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A33          *((volatile unsigned int*)(0x42CF0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A34          *((volatile unsigned int*)(0x42CF0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A35          *((volatile unsigned int*)(0x42CF0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A36          *((volatile unsigned int*)(0x42CF0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A37          *((volatile unsigned int*)(0x42CF0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A38          *((volatile unsigned int*)(0x42CF0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A39          *((volatile unsigned int*)(0x42CF0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A40          *((volatile unsigned int*)(0x42CF0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A41          *((volatile unsigned int*)(0x42CF0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A42          *((volatile unsigned int*)(0x42CF0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A43          *((volatile unsigned int*)(0x42CF0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A44          *((volatile unsigned int*)(0x42CF0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A45          *((volatile unsigned int*)(0x42CF0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A46          *((volatile unsigned int*)(0x42CF0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A47          *((volatile unsigned int*)(0x42CF0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC0         *((volatile unsigned int*)(0x42CF0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC1         *((volatile unsigned int*)(0x42CF0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC2         *((volatile unsigned int*)(0x42CF0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC3         *((volatile unsigned int*)(0x42CF0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC4         *((volatile unsigned int*)(0x42CF0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC5         *((volatile unsigned int*)(0x42CF0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_SA           *((volatile unsigned int*)(0x42CF0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_AE           *((volatile unsigned int*)(0x42CF0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A0           *((volatile unsigned int*)(0x42CF0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A1           *((volatile unsigned int*)(0x42CF0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A2           *((volatile unsigned int*)(0x42CF0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A3           *((volatile unsigned int*)(0x42CF0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A4           *((volatile unsigned int*)(0x42CF0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A5           *((volatile unsigned int*)(0x42CF0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A6           *((volatile unsigned int*)(0x42CF0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A7           *((volatile unsigned int*)(0x42CF0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A8           *((volatile unsigned int*)(0x42CF0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A9           *((volatile unsigned int*)(0x42CF0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A10          *((volatile unsigned int*)(0x42CF0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A11          *((volatile unsigned int*)(0x42CF0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A12          *((volatile unsigned int*)(0x42CF0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A13          *((volatile unsigned int*)(0x42CF0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A14          *((volatile unsigned int*)(0x42CF0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A15          *((volatile unsigned int*)(0x42CF0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A16          *((volatile unsigned int*)(0x42CF0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A17          *((volatile unsigned int*)(0x42CF0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A18          *((volatile unsigned int*)(0x42CF0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A19          *((volatile unsigned int*)(0x42CF0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A20          *((volatile unsigned int*)(0x42CF0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A21          *((volatile unsigned int*)(0x42CF0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A22          *((volatile unsigned int*)(0x42CF0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A23          *((volatile unsigned int*)(0x42CF0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A24          *((volatile unsigned int*)(0x42CF0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A25          *((volatile unsigned int*)(0x42CF0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A26          *((volatile unsigned int*)(0x42CF0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A27          *((volatile unsigned int*)(0x42CF0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A28          *((volatile unsigned int*)(0x42CF0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A29          *((volatile unsigned int*)(0x42CF0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A30          *((volatile unsigned int*)(0x42CF0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A31          *((volatile unsigned int*)(0x42CF0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A32          *((volatile unsigned int*)(0x42CF0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A33          *((volatile unsigned int*)(0x42CF0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A34          *((volatile unsigned int*)(0x42CF0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A35          *((volatile unsigned int*)(0x42CF0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A36          *((volatile unsigned int*)(0x42CF0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A37          *((volatile unsigned int*)(0x42CF0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A38          *((volatile unsigned int*)(0x42CF0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A39          *((volatile unsigned int*)(0x42CF0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A40          *((volatile unsigned int*)(0x42CF0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A41          *((volatile unsigned int*)(0x42CF0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A42          *((volatile unsigned int*)(0x42CF0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A43          *((volatile unsigned int*)(0x42CF0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A44          *((volatile unsigned int*)(0x42CF0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A45          *((volatile unsigned int*)(0x42CF0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A46          *((volatile unsigned int*)(0x42CF0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A47          *((volatile unsigned int*)(0x42CF0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC0         *((volatile unsigned int*)(0x42CF0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC1         *((volatile unsigned int*)(0x42CF0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC2         *((volatile unsigned int*)(0x42CF0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC3         *((volatile unsigned int*)(0x42CF0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC4         *((volatile unsigned int*)(0x42CF0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC5         *((volatile unsigned int*)(0x42CF0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_SA           *((volatile unsigned int*)(0x42CF0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_AE           *((volatile unsigned int*)(0x42CF0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A0           *((volatile unsigned int*)(0x42CF0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A1           *((volatile unsigned int*)(0x42CF0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A2           *((volatile unsigned int*)(0x42CF0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A3           *((volatile unsigned int*)(0x42CF0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A4           *((volatile unsigned int*)(0x42CF0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A5           *((volatile unsigned int*)(0x42CF0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A6           *((volatile unsigned int*)(0x42CF0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A7           *((volatile unsigned int*)(0x42CF0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A8           *((volatile unsigned int*)(0x42CF0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A9           *((volatile unsigned int*)(0x42CF0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A10          *((volatile unsigned int*)(0x42CF0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A11          *((volatile unsigned int*)(0x42CF0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A12          *((volatile unsigned int*)(0x42CF0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A13          *((volatile unsigned int*)(0x42CF0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A14          *((volatile unsigned int*)(0x42CF0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A15          *((volatile unsigned int*)(0x42CF0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A16          *((volatile unsigned int*)(0x42CF0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A17          *((volatile unsigned int*)(0x42CF0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A18          *((volatile unsigned int*)(0x42CF0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A19          *((volatile unsigned int*)(0x42CF0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A20          *((volatile unsigned int*)(0x42CF0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A21          *((volatile unsigned int*)(0x42CF0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A22          *((volatile unsigned int*)(0x42CF0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A23          *((volatile unsigned int*)(0x42CF0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A24          *((volatile unsigned int*)(0x42CF0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A25          *((volatile unsigned int*)(0x42CF0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A26          *((volatile unsigned int*)(0x42CF0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A27          *((volatile unsigned int*)(0x42CF0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A28          *((volatile unsigned int*)(0x42CF0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A29          *((volatile unsigned int*)(0x42CF0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A30          *((volatile unsigned int*)(0x42CF0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A31          *((volatile unsigned int*)(0x42CF0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A32          *((volatile unsigned int*)(0x42CF0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A33          *((volatile unsigned int*)(0x42CF0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A34          *((volatile unsigned int*)(0x42CF0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A35          *((volatile unsigned int*)(0x42CF0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A36          *((volatile unsigned int*)(0x42CF0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A37          *((volatile unsigned int*)(0x42CF0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A38          *((volatile unsigned int*)(0x42CF0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A39          *((volatile unsigned int*)(0x42CF0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A40          *((volatile unsigned int*)(0x42CF0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A41          *((volatile unsigned int*)(0x42CF0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A42          *((volatile unsigned int*)(0x42CF0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A43          *((volatile unsigned int*)(0x42CF0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A44          *((volatile unsigned int*)(0x42CF0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A45          *((volatile unsigned int*)(0x42CF0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A46          *((volatile unsigned int*)(0x42CF0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A47          *((volatile unsigned int*)(0x42CF0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC0         *((volatile unsigned int*)(0x42CF0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC1         *((volatile unsigned int*)(0x42CF0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC2         *((volatile unsigned int*)(0x42CF0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC3         *((volatile unsigned int*)(0x42CF0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC4         *((volatile unsigned int*)(0x42CF0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC5         *((volatile unsigned int*)(0x42CF0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_SA           *((volatile unsigned int*)(0x42CF0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_AE           *((volatile unsigned int*)(0x42CF0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A0           *((volatile unsigned int*)(0x42CF0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A1           *((volatile unsigned int*)(0x42CF0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A2           *((volatile unsigned int*)(0x42CF0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A3           *((volatile unsigned int*)(0x42CF0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A4           *((volatile unsigned int*)(0x42CF0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A5           *((volatile unsigned int*)(0x42CF0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A6           *((volatile unsigned int*)(0x42CF0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A7           *((volatile unsigned int*)(0x42CF0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A8           *((volatile unsigned int*)(0x42CF0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A9           *((volatile unsigned int*)(0x42CF0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A10          *((volatile unsigned int*)(0x42CF0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A11          *((volatile unsigned int*)(0x42CF0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A12          *((volatile unsigned int*)(0x42CF0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A13          *((volatile unsigned int*)(0x42CF0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A14          *((volatile unsigned int*)(0x42CF0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A15          *((volatile unsigned int*)(0x42CF0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A16          *((volatile unsigned int*)(0x42CF0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A17          *((volatile unsigned int*)(0x42CF0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A18          *((volatile unsigned int*)(0x42CF0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A19          *((volatile unsigned int*)(0x42CF0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A20          *((volatile unsigned int*)(0x42CF0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A21          *((volatile unsigned int*)(0x42CF0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A22          *((volatile unsigned int*)(0x42CF0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A23          *((volatile unsigned int*)(0x42CF0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A24          *((volatile unsigned int*)(0x42CF0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A25          *((volatile unsigned int*)(0x42CF0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A26          *((volatile unsigned int*)(0x42CF0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A27          *((volatile unsigned int*)(0x42CF0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A28          *((volatile unsigned int*)(0x42CF0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A29          *((volatile unsigned int*)(0x42CF0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A30          *((volatile unsigned int*)(0x42CF0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A31          *((volatile unsigned int*)(0x42CF0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A32          *((volatile unsigned int*)(0x42CF0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A33          *((volatile unsigned int*)(0x42CF0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A34          *((volatile unsigned int*)(0x42CF0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A35          *((volatile unsigned int*)(0x42CF0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A36          *((volatile unsigned int*)(0x42CF0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A37          *((volatile unsigned int*)(0x42CF0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A38          *((volatile unsigned int*)(0x42CF0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A39          *((volatile unsigned int*)(0x42CF0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A40          *((volatile unsigned int*)(0x42CF0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A41          *((volatile unsigned int*)(0x42CF0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A42          *((volatile unsigned int*)(0x42CF0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A43          *((volatile unsigned int*)(0x42CF0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A44          *((volatile unsigned int*)(0x42CF0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A45          *((volatile unsigned int*)(0x42CF0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A46          *((volatile unsigned int*)(0x42CF0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A47          *((volatile unsigned int*)(0x42CF0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC0         *((volatile unsigned int*)(0x42CF0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC1         *((volatile unsigned int*)(0x42CF0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC2         *((volatile unsigned int*)(0x42CF0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC3         *((volatile unsigned int*)(0x42CF0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC4         *((volatile unsigned int*)(0x42CF0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC5         *((volatile unsigned int*)(0x42CF0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_SA           *((volatile unsigned int*)(0x42CF0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_AE           *((volatile unsigned int*)(0x42CF0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A0           *((volatile unsigned int*)(0x42CF0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A1           *((volatile unsigned int*)(0x42CF0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A2           *((volatile unsigned int*)(0x42CF0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A3           *((volatile unsigned int*)(0x42CF0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A4           *((volatile unsigned int*)(0x42CF0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A5           *((volatile unsigned int*)(0x42CF0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A6           *((volatile unsigned int*)(0x42CF0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A7           *((volatile unsigned int*)(0x42CF0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A8           *((volatile unsigned int*)(0x42CF0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A9           *((volatile unsigned int*)(0x42CF0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A10          *((volatile unsigned int*)(0x42CF0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A11          *((volatile unsigned int*)(0x42CF0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A12          *((volatile unsigned int*)(0x42CF0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A13          *((volatile unsigned int*)(0x42CF0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A14          *((volatile unsigned int*)(0x42CF0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A15          *((volatile unsigned int*)(0x42CF0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A16          *((volatile unsigned int*)(0x42CF0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A17          *((volatile unsigned int*)(0x42CF0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A18          *((volatile unsigned int*)(0x42CF0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A19          *((volatile unsigned int*)(0x42CF0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A20          *((volatile unsigned int*)(0x42CF0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A21          *((volatile unsigned int*)(0x42CF0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A22          *((volatile unsigned int*)(0x42CF0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A23          *((volatile unsigned int*)(0x42CF0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A24          *((volatile unsigned int*)(0x42CF0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A25          *((volatile unsigned int*)(0x42CF0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A26          *((volatile unsigned int*)(0x42CF0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A27          *((volatile unsigned int*)(0x42CF0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A28          *((volatile unsigned int*)(0x42CF0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A29          *((volatile unsigned int*)(0x42CF0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A30          *((volatile unsigned int*)(0x42CF0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A31          *((volatile unsigned int*)(0x42CF0FFCUL))
+#define bFM3_ETHERNET_MAC1_BMR_SWR             *((volatile unsigned int*)(0x42D00000UL))
+#define bFM3_ETHERNET_MAC1_BMR_DA              *((volatile unsigned int*)(0x42D00004UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL0            *((volatile unsigned int*)(0x42D00008UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL1            *((volatile unsigned int*)(0x42D0000CUL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL2            *((volatile unsigned int*)(0x42D00010UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL3            *((volatile unsigned int*)(0x42D00014UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL4            *((volatile unsigned int*)(0x42D00018UL))
+#define bFM3_ETHERNET_MAC1_BMR_ATDS            *((volatile unsigned int*)(0x42D0001CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL0            *((volatile unsigned int*)(0x42D00020UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL1            *((volatile unsigned int*)(0x42D00024UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL2            *((volatile unsigned int*)(0x42D00028UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL3            *((volatile unsigned int*)(0x42D0002CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL4            *((volatile unsigned int*)(0x42D00030UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL5            *((volatile unsigned int*)(0x42D00034UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR0             *((volatile unsigned int*)(0x42D00038UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR1             *((volatile unsigned int*)(0x42D0003CUL))
+#define bFM3_ETHERNET_MAC1_BMR_FB              *((volatile unsigned int*)(0x42D00040UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL0           *((volatile unsigned int*)(0x42D00044UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL1           *((volatile unsigned int*)(0x42D00048UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL2           *((volatile unsigned int*)(0x42D0004CUL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL3           *((volatile unsigned int*)(0x42D00050UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL4           *((volatile unsigned int*)(0x42D00054UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL5           *((volatile unsigned int*)(0x42D00058UL))
+#define bFM3_ETHERNET_MAC1_BMR_USP             *((volatile unsigned int*)(0x42D0005CUL))
+#define bFM3_ETHERNET_MAC1_BMR_8XPBL           *((volatile unsigned int*)(0x42D00060UL))
+#define bFM3_ETHERNET_MAC1_BMR_AAL             *((volatile unsigned int*)(0x42D00064UL))
+#define bFM3_ETHERNET_MAC1_BMR_MB              *((volatile unsigned int*)(0x42D00068UL))
+#define bFM3_ETHERNET_MAC1_BMR_TXPR            *((volatile unsigned int*)(0x42D0006CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD0           *((volatile unsigned int*)(0x42D00080UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD1           *((volatile unsigned int*)(0x42D00084UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD2           *((volatile unsigned int*)(0x42D00088UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD3           *((volatile unsigned int*)(0x42D0008CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD4           *((volatile unsigned int*)(0x42D00090UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD5           *((volatile unsigned int*)(0x42D00094UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD6           *((volatile unsigned int*)(0x42D00098UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD7           *((volatile unsigned int*)(0x42D0009CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD8           *((volatile unsigned int*)(0x42D000A0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD9           *((volatile unsigned int*)(0x42D000A4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD10          *((volatile unsigned int*)(0x42D000A8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD11          *((volatile unsigned int*)(0x42D000ACUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD12          *((volatile unsigned int*)(0x42D000B0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD13          *((volatile unsigned int*)(0x42D000B4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD14          *((volatile unsigned int*)(0x42D000B8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD15          *((volatile unsigned int*)(0x42D000BCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD16          *((volatile unsigned int*)(0x42D000C0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD17          *((volatile unsigned int*)(0x42D000C4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD18          *((volatile unsigned int*)(0x42D000C8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD19          *((volatile unsigned int*)(0x42D000CCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD20          *((volatile unsigned int*)(0x42D000D0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD21          *((volatile unsigned int*)(0x42D000D4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD22          *((volatile unsigned int*)(0x42D000D8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD23          *((volatile unsigned int*)(0x42D000DCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD24          *((volatile unsigned int*)(0x42D000E0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD25          *((volatile unsigned int*)(0x42D000E4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD26          *((volatile unsigned int*)(0x42D000E8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD27          *((volatile unsigned int*)(0x42D000ECUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD28          *((volatile unsigned int*)(0x42D000F0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD29          *((volatile unsigned int*)(0x42D000F4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD30          *((volatile unsigned int*)(0x42D000F8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD31          *((volatile unsigned int*)(0x42D000FCUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD0           *((volatile unsigned int*)(0x42D00100UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD1           *((volatile unsigned int*)(0x42D00104UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD2           *((volatile unsigned int*)(0x42D00108UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD3           *((volatile unsigned int*)(0x42D0010CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD4           *((volatile unsigned int*)(0x42D00110UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD5           *((volatile unsigned int*)(0x42D00114UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD6           *((volatile unsigned int*)(0x42D00118UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD7           *((volatile unsigned int*)(0x42D0011CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD8           *((volatile unsigned int*)(0x42D00120UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD9           *((volatile unsigned int*)(0x42D00124UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD10          *((volatile unsigned int*)(0x42D00128UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD11          *((volatile unsigned int*)(0x42D0012CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD12          *((volatile unsigned int*)(0x42D00130UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD13          *((volatile unsigned int*)(0x42D00134UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD14          *((volatile unsigned int*)(0x42D00138UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD15          *((volatile unsigned int*)(0x42D0013CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD16          *((volatile unsigned int*)(0x42D00140UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD17          *((volatile unsigned int*)(0x42D00144UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD18          *((volatile unsigned int*)(0x42D00148UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD19          *((volatile unsigned int*)(0x42D0014CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD20          *((volatile unsigned int*)(0x42D00150UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD21          *((volatile unsigned int*)(0x42D00154UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD22          *((volatile unsigned int*)(0x42D00158UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD23          *((volatile unsigned int*)(0x42D0015CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD24          *((volatile unsigned int*)(0x42D00160UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD25          *((volatile unsigned int*)(0x42D00164UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD26          *((volatile unsigned int*)(0x42D00168UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD27          *((volatile unsigned int*)(0x42D0016CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD28          *((volatile unsigned int*)(0x42D00170UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD29          *((volatile unsigned int*)(0x42D00174UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD30          *((volatile unsigned int*)(0x42D00178UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD31          *((volatile unsigned int*)(0x42D0017CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL2          *((volatile unsigned int*)(0x42D00188UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL3          *((volatile unsigned int*)(0x42D0018CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL4          *((volatile unsigned int*)(0x42D00190UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL5          *((volatile unsigned int*)(0x42D00194UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL6          *((volatile unsigned int*)(0x42D00198UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL7          *((volatile unsigned int*)(0x42D0019CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL8          *((volatile unsigned int*)(0x42D001A0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL9          *((volatile unsigned int*)(0x42D001A4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL10         *((volatile unsigned int*)(0x42D001A8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL11         *((volatile unsigned int*)(0x42D001ACUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL12         *((volatile unsigned int*)(0x42D001B0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL13         *((volatile unsigned int*)(0x42D001B4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL14         *((volatile unsigned int*)(0x42D001B8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL15         *((volatile unsigned int*)(0x42D001BCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL16         *((volatile unsigned int*)(0x42D001C0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL17         *((volatile unsigned int*)(0x42D001C4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL18         *((volatile unsigned int*)(0x42D001C8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL19         *((volatile unsigned int*)(0x42D001CCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL20         *((volatile unsigned int*)(0x42D001D0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL21         *((volatile unsigned int*)(0x42D001D4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL22         *((volatile unsigned int*)(0x42D001D8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL23         *((volatile unsigned int*)(0x42D001DCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL24         *((volatile unsigned int*)(0x42D001E0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL25         *((volatile unsigned int*)(0x42D001E4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL26         *((volatile unsigned int*)(0x42D001E8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL27         *((volatile unsigned int*)(0x42D001ECUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL28         *((volatile unsigned int*)(0x42D001F0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL29         *((volatile unsigned int*)(0x42D001F4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL30         *((volatile unsigned int*)(0x42D001F8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL31         *((volatile unsigned int*)(0x42D001FCUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL2          *((volatile unsigned int*)(0x42D00208UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL3          *((volatile unsigned int*)(0x42D0020CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL4          *((volatile unsigned int*)(0x42D00210UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL5          *((volatile unsigned int*)(0x42D00214UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL6          *((volatile unsigned int*)(0x42D00218UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL7          *((volatile unsigned int*)(0x42D0021CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL8          *((volatile unsigned int*)(0x42D00220UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL9          *((volatile unsigned int*)(0x42D00224UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL10         *((volatile unsigned int*)(0x42D00228UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL11         *((volatile unsigned int*)(0x42D0022CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL12         *((volatile unsigned int*)(0x42D00230UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL13         *((volatile unsigned int*)(0x42D00234UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL14         *((volatile unsigned int*)(0x42D00238UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL15         *((volatile unsigned int*)(0x42D0023CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL16         *((volatile unsigned int*)(0x42D00240UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL17         *((volatile unsigned int*)(0x42D00244UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL18         *((volatile unsigned int*)(0x42D00248UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL19         *((volatile unsigned int*)(0x42D0024CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL20         *((volatile unsigned int*)(0x42D00250UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL21         *((volatile unsigned int*)(0x42D00254UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL22         *((volatile unsigned int*)(0x42D00258UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL23         *((volatile unsigned int*)(0x42D0025CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL24         *((volatile unsigned int*)(0x42D00260UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL25         *((volatile unsigned int*)(0x42D00264UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL26         *((volatile unsigned int*)(0x42D00268UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL27         *((volatile unsigned int*)(0x42D0026CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL28         *((volatile unsigned int*)(0x42D00270UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL29         *((volatile unsigned int*)(0x42D00274UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL30         *((volatile unsigned int*)(0x42D00278UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL31         *((volatile unsigned int*)(0x42D0027CUL))
+#define bFM3_ETHERNET_MAC1_SR_TI               *((volatile unsigned int*)(0x42D00280UL))
+#define bFM3_ETHERNET_MAC1_SR_TPS              *((volatile unsigned int*)(0x42D00284UL))
+#define bFM3_ETHERNET_MAC1_SR_TU               *((volatile unsigned int*)(0x42D00288UL))
+#define bFM3_ETHERNET_MAC1_SR_TJT              *((volatile unsigned int*)(0x42D0028CUL))
+#define bFM3_ETHERNET_MAC1_SR_OVF              *((volatile unsigned int*)(0x42D00290UL))
+#define bFM3_ETHERNET_MAC1_SR_UNF              *((volatile unsigned int*)(0x42D00294UL))
+#define bFM3_ETHERNET_MAC1_SR_RI               *((volatile unsigned int*)(0x42D00298UL))
+#define bFM3_ETHERNET_MAC1_SR_RU               *((volatile unsigned int*)(0x42D0029CUL))
+#define bFM3_ETHERNET_MAC1_SR_RPS              *((volatile unsigned int*)(0x42D002A0UL))
+#define bFM3_ETHERNET_MAC1_SR_RWT              *((volatile unsigned int*)(0x42D002A4UL))
+#define bFM3_ETHERNET_MAC1_SR_ETI              *((volatile unsigned int*)(0x42D002A8UL))
+#define bFM3_ETHERNET_MAC1_SR_FBI              *((volatile unsigned int*)(0x42D002B4UL))
+#define bFM3_ETHERNET_MAC1_SR_ERI              *((volatile unsigned int*)(0x42D002B8UL))
+#define bFM3_ETHERNET_MAC1_SR_AIS              *((volatile unsigned int*)(0x42D002BCUL))
+#define bFM3_ETHERNET_MAC1_SR_NIS              *((volatile unsigned int*)(0x42D002C0UL))
+#define bFM3_ETHERNET_MAC1_SR_RS0              *((volatile unsigned int*)(0x42D002C4UL))
+#define bFM3_ETHERNET_MAC1_SR_RS1              *((volatile unsigned int*)(0x42D002C8UL))
+#define bFM3_ETHERNET_MAC1_SR_RS2              *((volatile unsigned int*)(0x42D002CCUL))
+#define bFM3_ETHERNET_MAC1_SR_TS0              *((volatile unsigned int*)(0x42D002D0UL))
+#define bFM3_ETHERNET_MAC1_SR_TS1              *((volatile unsigned int*)(0x42D002D4UL))
+#define bFM3_ETHERNET_MAC1_SR_TS2              *((volatile unsigned int*)(0x42D002D8UL))
+#define bFM3_ETHERNET_MAC1_SR_EB0              *((volatile unsigned int*)(0x42D002DCUL))
+#define bFM3_ETHERNET_MAC1_SR_EB1              *((volatile unsigned int*)(0x42D002E0UL))
+#define bFM3_ETHERNET_MAC1_SR_EB2              *((volatile unsigned int*)(0x42D002E4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLI              *((volatile unsigned int*)(0x42D002E8UL))
+#define bFM3_ETHERNET_MAC1_SR_GMI              *((volatile unsigned int*)(0x42D002ECUL))
+#define bFM3_ETHERNET_MAC1_SR_GPI              *((volatile unsigned int*)(0x42D002F0UL))
+#define bFM3_ETHERNET_MAC1_SR_TTI              *((volatile unsigned int*)(0x42D002F4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLPII            *((volatile unsigned int*)(0x42D002F8UL))
+#define bFM3_ETHERNET_MAC1_OMR_SR              *((volatile unsigned int*)(0x42D00304UL))
+#define bFM3_ETHERNET_MAC1_OMR_OSF             *((volatile unsigned int*)(0x42D00308UL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC0            *((volatile unsigned int*)(0x42D0030CUL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC1            *((volatile unsigned int*)(0x42D00310UL))
+#define bFM3_ETHERNET_MAC1_OMR_FUF             *((volatile unsigned int*)(0x42D00318UL))
+#define bFM3_ETHERNET_MAC1_OMR_FEF             *((volatile unsigned int*)(0x42D0031CUL))
+#define bFM3_ETHERNET_MAC1_OMR_ST              *((volatile unsigned int*)(0x42D00334UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC0            *((volatile unsigned int*)(0x42D00338UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC1            *((volatile unsigned int*)(0x42D0033CUL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC2            *((volatile unsigned int*)(0x42D00340UL))
+#define bFM3_ETHERNET_MAC1_OMR_FTF             *((volatile unsigned int*)(0x42D00350UL))
+#define bFM3_ETHERNET_MAC1_OMR_TSF             *((volatile unsigned int*)(0x42D00354UL))
+#define bFM3_ETHERNET_MAC1_OMR_DFF             *((volatile unsigned int*)(0x42D00360UL))
+#define bFM3_ETHERNET_MAC1_OMR_RSF             *((volatile unsigned int*)(0x42D00364UL))
+#define bFM3_ETHERNET_MAC1_OMR_DT              *((volatile unsigned int*)(0x42D00368UL))
+#define bFM3_ETHERNET_MAC1_IER_TIE             *((volatile unsigned int*)(0x42D00380UL))
+#define bFM3_ETHERNET_MAC1_IER_TSE             *((volatile unsigned int*)(0x42D00384UL))
+#define bFM3_ETHERNET_MAC1_IER_TUE             *((volatile unsigned int*)(0x42D00388UL))
+#define bFM3_ETHERNET_MAC1_IER_TJE             *((volatile unsigned int*)(0x42D0038CUL))
+#define bFM3_ETHERNET_MAC1_IER_OVE             *((volatile unsigned int*)(0x42D00390UL))
+#define bFM3_ETHERNET_MAC1_IER_UNE             *((volatile unsigned int*)(0x42D00394UL))
+#define bFM3_ETHERNET_MAC1_IER_RIE             *((volatile unsigned int*)(0x42D00398UL))
+#define bFM3_ETHERNET_MAC1_IER_RUE             *((volatile unsigned int*)(0x42D0039CUL))
+#define bFM3_ETHERNET_MAC1_IER_RSE             *((volatile unsigned int*)(0x42D003A0UL))
+#define bFM3_ETHERNET_MAC1_IER_RWE             *((volatile unsigned int*)(0x42D003A4UL))
+#define bFM3_ETHERNET_MAC1_IER_ETE             *((volatile unsigned int*)(0x42D003A8UL))
+#define bFM3_ETHERNET_MAC1_IER_FBE             *((volatile unsigned int*)(0x42D003B4UL))
+#define bFM3_ETHERNET_MAC1_IER_ERE             *((volatile unsigned int*)(0x42D003B8UL))
+#define bFM3_ETHERNET_MAC1_IER_AIE             *((volatile unsigned int*)(0x42D003BCUL))
+#define bFM3_ETHERNET_MAC1_IER_NIE             *((volatile unsigned int*)(0x42D003C0UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42D00400UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42D00404UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42D00408UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42D0040CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42D00410UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42D00414UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42D00418UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42D0041CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42D00420UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42D00424UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42D00428UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42D0042CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42D00430UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42D00434UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42D00438UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42D0043CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42D00440UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42D00444UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42D00448UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42D0044CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42D00450UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42D00454UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42D00458UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42D0045CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42D00460UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42D00464UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42D00468UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42D0046CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42D00470UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0         *((volatile unsigned int*)(0x42D00480UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1         *((volatile unsigned int*)(0x42D00484UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2         *((volatile unsigned int*)(0x42D00488UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3         *((volatile unsigned int*)(0x42D0048CUL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4         *((volatile unsigned int*)(0x42D00490UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5         *((volatile unsigned int*)(0x42D00494UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6         *((volatile unsigned int*)(0x42D00498UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7         *((volatile unsigned int*)(0x42D0049CUL))
+#define bFM3_ETHERNET_MAC1_AHBSR_AHBS          *((volatile unsigned int*)(0x42D00580UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42D00900UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42D00904UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42D00908UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42D0090CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42D00910UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42D00914UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42D00918UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42D0091CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42D00920UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42D00924UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42D00928UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42D0092CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42D00930UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42D00934UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42D00938UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42D0093CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42D00940UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42D00944UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42D00948UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42D0094CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42D00950UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42D00954UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42D00958UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42D0095CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42D00960UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42D00964UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42D00968UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42D0096CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42D00970UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42D00974UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42D00978UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42D0097CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42D00980UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42D00984UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42D00988UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42D0098CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42D00990UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42D00994UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42D00998UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42D0099CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42D009A0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42D009A4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42D009A8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42D009ACUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42D009B0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42D009B4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42D009B8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42D009BCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42D009C0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42D009C4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42D009C8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42D009CCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42D009D0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42D009D4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42D009D8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42D009DCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42D009E0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42D009E4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42D009E8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42D009ECUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42D009F0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42D009F4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42D009F8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42D009FCUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42D00A00UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42D00A04UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42D00A08UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42D00A0CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42D00A10UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42D00A14UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42D00A18UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42D00A1CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42D00A20UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42D00A24UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42D00A28UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42D00A2CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42D00A30UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42D00A34UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42D00A38UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42D00A3CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42D00A40UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42D00A44UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42D00A48UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42D00A4CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42D00A50UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42D00A54UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42D00A58UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42D00A5CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42D00A60UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42D00A64UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42D00A68UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42D00A6CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42D00A70UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42D00A74UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42D00A78UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42D00A7CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42D00A80UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42D00A84UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42D00A88UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42D00A8CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42D00A90UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42D00A94UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42D00A98UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42D00A9CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42D00AA0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42D00AA4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42D00AA8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42D00AACUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42D00AB0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42D00AB4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42D00AB8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42D00ABCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42D00AC0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42D00AC4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42D00AC8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42D00ACCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42D00AD0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42D00AD4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42D00AD8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42D00ADCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42D00AE0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42D00AE4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42D00AE8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42D00AECUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42D00AF0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42D00AF4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42D00AF8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42D00AFCUL))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MB9BF618S_H_ */
+

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/mb9b610t.h

@@ -0,0 +1,29338 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/*                                                                      */
+/*  Header File for Device MB9B610T                                     */
+/*  Version V1.2                                                        */
+/*  Date    2012-02-23                                                  */
+/*                                                                      */
+/************************************************************************/
+
+/******************************************************************************
+ * History
+ * Date       Ver Description
+ * 2011-08-04 1.0 Initial
+ * 2011-10-04 1.1 Added FBFCR register
+ *                Removed the following bits from the bit fields
+ *                - TMD bits of WFSAxx register in MFT
+ *                - MD bits of PPGCx register in PPG
+ *                - FMD bits of TMCR register in BT
+ *                - MD bits of SMR register in MFS
+ * 2012-02-23 1.2 Added the following bits to the bit fields
+ *                - TMD bits of WFSAxx register in MFT
+ *                - MD bits of PPGCx register in PPG
+ *                - FMD bits of TMCR register in BT
+ *                - MD bits of SMR register in MFS
+ *
+ ******************************************************************************/
+
+#ifndef _MB9B610T_H_
+#define _MB9B610T_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+
+/******************************************************************************
+ * Configuration of the Cortex-M3 Processor and Core Peripherals
+ ******************************************************************************/
+#define __MPU_PRESENT           1 /* FM3 provide an MPU                           */
+#define __NVIC_PRIO_BITS        4 /* FM3 uses 4 Bits for the Priority Levels      */
+#define __Vendor_SysTickConfig  0 /* Set to 1 if different SysTick Config is used */
+
+
+/******************************************************************************
+ * Interrupt Number Definition
+ ******************************************************************************/
+typedef enum IRQn
+{
+    NMI_IRQn          = -14, /*  2 Non Maskable      */
+    HardFault_IRQn    = -13, /*  3 Hard Fault        */
+    MemManage_IRQn    = -12, /*  4 Memory Management */
+    BusFault_IRQn     = -11, /*  5 Bus Fault         */
+    UsageFault_IRQn   = -10, /*  6 Usage Fault       */
+    SVC_IRQn          = -5,  /* 11 SV Call           */
+    DebugMonitor_IRQn = -4,  /* 12 Debug Monitor     */
+    PendSV_IRQn       = -2,  /* 14 Pend SV           */
+    SysTick_IRQn      = -1,  /* 15 System Tick       */
+
+    CSV_IRQn          =  0, /* Clock Super Visor                             */
+    SWDT_IRQn         =  1, /* Software Watchdog Timer                       */
+    LVD_IRQn          =  2, /* Low Voltage Detector                          */
+    WFG_IRQn          =  3, /* Wave Form Generator                           */
+    EXINT0_7_IRQn     =  4, /* External Interrupt Request ch.0 to ch.7       */
+    EXINT8_31_IRQn    =  5, /* External Interrupt Request ch.8 to ch.31      */
+    DTIM_QDU_IRQn     =  6, /* Dual Timer / Quad Decoder                     */
+    MFS0RX_IRQn       =  7, /* MultiFunction Serial Reception ch.0           */
+    MFS0TX_IRQn       =  8, /* MultiFunction Serial Transmission ch.0        */
+    MFS1RX_IRQn       =  9, /* MultiFunction Serial Reception ch.1           */
+    MFS1TX_IRQn       = 10, /* MultiFunction Serial Transmission ch.1        */
+    MFS2RX_IRQn       = 11, /* MultiFunction Serial Reception ch.2           */
+    MFS2TX_IRQn       = 12, /* MultiFunction Serial Transmission ch.2        */
+    MFS3RX_IRQn       = 13, /* MultiFunction Serial Reception ch.3           */
+    MFS3TX_IRQn       = 14, /* MultiFunction Serial Transmission ch.3        */
+    MFS4RX_IRQn       = 15, /* MultiFunction Serial Reception ch.4           */
+    MFS4TX_IRQn       = 16, /* MultiFunction Serial Transmission ch.4        */
+    MFS5RX_IRQn       = 17, /* MultiFunction Serial Reception ch.5           */
+    MFS5TX_IRQn       = 18, /* MultiFunction Serial Transmission ch.5        */
+    MFS6RX_IRQn       = 19, /* MultiFunction Serial Reception ch.6           */
+    MFS6TX_IRQn       = 20, /* MultiFunction Serial Transmission ch.6        */
+    MFS7RX_IRQn       = 21, /* MultiFunction Serial Reception ch.7           */
+    MFS7TX_IRQn       = 22, /* MultiFunction Serial Transmission ch.7        */
+    PPG_IRQn          = 23, /* PPG                                           */
+    OSC_PLL_WC_IRQn   = 24, /* OSC / PLL / Watch Counter                     */
+    ADC0_IRQn         = 25, /* ADC0                                          */
+    ADC1_IRQn         = 26, /* ADC1                                          */
+    ADC2_IRQn         = 27, /* ADC2                                          */
+    FRTIM_IRQn        = 28, /* Free-run Timer                                */
+    INCAP_IRQn        = 29, /* Input Capture                                 */
+    OUTCOMP_IRQn      = 30, /* Output Compare                                */
+    BTIM0_7_IRQn      = 31, /* Base Timer ch.0 to ch.7                       */
+    ETHER_MAC0_IRQn   = 32, /* Ethernet MAC ch.0                             */
+    ETHER_MAC1_IRQn   = 33, /* Ethernet MAC ch.1                             */
+    USB0F_IRQn        = 34, /* USB Function ch.0                             */
+    USB0F_USB0H_IRQn  = 35, /* USB Function ch.0 / USB Host ch.0             */
+    USB1F_IRQn        = 36, /* USB Function ch.1                             */
+    USB1F_USB1H_IRQn  = 37, /* USB Function ch.1 / USB Host ch.1             */
+    DMAC0_IRQn        = 38, /* DMAC ch.0                                     */
+    DMAC1_IRQn        = 39, /* DMAC ch.1                                     */
+    DMAC2_IRQn        = 40, /* DMAC ch.2                                     */
+    DMAC3_IRQn        = 41, /* DMAC ch.3                                     */
+    DMAC4_IRQn        = 42, /* DMAC ch.4                                     */
+    DMAC5_IRQn        = 43, /* DMAC ch.5                                     */
+    DMAC6_IRQn        = 44, /* DMAC ch.6                                     */
+    DMAC7_IRQn        = 45, /* DMAC ch.7                                     */
+    BTIM8_15_IRQn     = 46  /* Base Timer ch.8 to ch.15                      */
+    /* Reserved       = 47                                                   */
+} IRQn_Type;
+
+
+#include <core_cm3.h>
+#include "system_mb9bf61x.h"
+#include <stdint.h>
+
+#define SUCCESS  0
+#define ERROR    -1
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+
+/******************************************************************************/
+/*                Device Specific Peripheral Registers structures             */
+/******************************************************************************/
+
+#if defined ( __CC_ARM   )
+#pragma anon_unions
+#endif
+
+/******************************************************************************
+ * Peripheral register bit fields
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash_IF_MODULE register bit fields */
+typedef struct stc_flash_if_faszr_field
+{
+  __IO uint32_t ASZ0       : 1;
+  __IO uint32_t ASZ1       : 1;
+} stc_flash_if_faszr_field_t;
+
+typedef struct stc_flash_if_frwtr_field
+{
+  __IO uint32_t RWT0       : 1;
+  __IO uint32_t RWT1       : 1;
+} stc_flash_if_frwtr_field_t;
+
+typedef struct stc_flash_if_fstr_field
+{
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t HNG        : 1;
+  __IO uint32_t EER        : 1;
+} stc_flash_if_fstr_field_t;
+
+typedef struct stc_flash_if_fsyndn_field
+{
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+} stc_flash_if_fsyndn_field_t;
+
+typedef struct stc_flash_if_fbfcr_field
+{
+  __IO uint32_t BE         : 1;
+  __IO uint32_t BS         : 1;
+} stc_flash_if_fbfcr_field_t;
+
+typedef struct stc_flash_if_crtrmm_field
+{
+  __IO uint32_t TRMM0      : 1;
+  __IO uint32_t TRMM1      : 1;
+  __IO uint32_t TRMM2      : 1;
+  __IO uint32_t TRMM3      : 1;
+  __IO uint32_t TRMM4      : 1;
+  __IO uint32_t TRMM5      : 1;
+  __IO uint32_t TRMM6      : 1;
+  __IO uint32_t TRMM7      : 1;
+  __IO uint32_t TRMM8      : 1;
+  __IO uint32_t TRMM9      : 1;
+} stc_flash_if_crtrmm_field_t;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock_Reset_MODULE register bit fields */
+typedef struct stc_crg_scm_ctl_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MOSCE      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SOSCE      : 1;
+  __IO  uint8_t PLLE       : 1;
+  __IO  uint8_t RCS0       : 1;
+  __IO  uint8_t RCS1       : 1;
+  __IO  uint8_t RCS2       : 1;
+} stc_crg_scm_ctl_field_t;
+
+typedef struct stc_crg_scm_str_field
+{
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t MORDY      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t SORDY      : 1;
+  __IO  uint8_t PLRDY      : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t RCM2       : 1;
+} stc_crg_scm_str_field_t;
+
+typedef struct stc_crg_rst_str_field
+{
+  __IO uint16_t PONR       : 1;
+  __IO uint16_t INITX      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SWDT       : 1;
+  __IO uint16_t HWDT       : 1;
+  __IO uint16_t CSVR       : 1;
+  __IO uint16_t FCSR       : 1;
+  __IO uint16_t SRST       : 1;
+} stc_crg_rst_str_field_t;
+
+typedef struct stc_crg_bsc_psr_field
+{
+  __IO  uint8_t BSR0       : 1;
+  __IO  uint8_t BSR1       : 1;
+  __IO  uint8_t BSR2       : 1;
+} stc_crg_bsc_psr_field_t;
+
+typedef struct stc_crg_apbc0_psr_field
+{
+  __IO  uint8_t APBC00     : 1;
+  __IO  uint8_t APBC01     : 1;
+} stc_crg_apbc0_psr_field_t;
+
+typedef struct stc_crg_apbc1_psr_field
+{
+  __IO  uint8_t APBC10     : 1;
+  __IO  uint8_t APBC11     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC1RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC1EN    : 1;
+} stc_crg_apbc1_psr_field_t;
+
+typedef struct stc_crg_apbc2_psr_field
+{
+  __IO  uint8_t APBC20     : 1;
+  __IO  uint8_t APBC21     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t APBC2RST   : 1;
+        uint8_t RESERVED2  : 2;
+  __IO  uint8_t APBC2EN    : 1;
+} stc_crg_apbc2_psr_field_t;
+
+typedef struct stc_crg_swc_psr_field
+{
+  __IO  uint8_t SWDS0      : 1;
+  __IO  uint8_t SWDS1      : 1;
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t TESTB      : 1;
+} stc_crg_swc_psr_field_t;
+
+typedef struct stc_crg_ttc_psr_field
+{
+  __IO  uint8_t TTC0       : 1;
+  __IO  uint8_t TTC1       : 1;
+} stc_crg_ttc_psr_field_t;
+
+typedef struct stc_crg_csw_tmr_field
+{
+  __IO  uint8_t MOWT0      : 1;
+  __IO  uint8_t MOWT1      : 1;
+  __IO  uint8_t MOWT2      : 1;
+  __IO  uint8_t MOWT3      : 1;
+  __IO  uint8_t SOWT0      : 1;
+  __IO  uint8_t SOWT1      : 1;
+  __IO  uint8_t SOWT2      : 1;
+} stc_crg_csw_tmr_field_t;
+
+typedef struct stc_crg_psw_tmr_field
+{
+  __IO  uint8_t POWT0      : 1;
+  __IO  uint8_t POWT1      : 1;
+  __IO  uint8_t POWT2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t PINC       : 1;
+} stc_crg_psw_tmr_field_t;
+
+typedef struct stc_crg_pll_ctl1_field
+{
+  __IO  uint8_t PLLM0      : 1;
+  __IO  uint8_t PLLM1      : 1;
+  __IO  uint8_t PLLM2      : 1;
+  __IO  uint8_t PLLM3      : 1;
+  __IO  uint8_t PLLK0      : 1;
+  __IO  uint8_t PLLK1      : 1;
+  __IO  uint8_t PLLK2      : 1;
+  __IO  uint8_t PLLK3      : 1;
+} stc_crg_pll_ctl1_field_t;
+
+typedef struct stc_crg_pll_ctl2_field
+{
+  __IO  uint8_t PLLN0      : 1;
+  __IO  uint8_t PLLN1      : 1;
+  __IO  uint8_t PLLN2      : 1;
+  __IO  uint8_t PLLN3      : 1;
+  __IO  uint8_t PLLN4      : 1;
+  __IO  uint8_t PLLN5      : 1;
+} stc_crg_pll_ctl2_field_t;
+
+typedef struct stc_crg_csv_ctl_field
+{
+  __IO uint16_t MCSVE      : 1;
+  __IO uint16_t SCSVE      : 1;
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t FCSDE      : 1;
+  __IO uint16_t FCSRE      : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t FCD0       : 1;
+  __IO uint16_t FCD1       : 1;
+  __IO uint16_t FCD2       : 1;
+} stc_crg_csv_ctl_field_t;
+
+typedef struct stc_crg_csv_str_field
+{
+  __IO  uint8_t MCMF       : 1;
+  __IO  uint8_t SCMF       : 1;
+} stc_crg_csv_str_field_t;
+
+typedef struct stc_crg_dbwdt_ctl_field
+{
+        uint8_t RESERVED1  : 5;
+  __IO  uint8_t DPSWBE     : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t DPHWBE     : 1;
+} stc_crg_dbwdt_ctl_field_t;
+
+typedef struct stc_crg_int_enr_field
+{
+  __IO  uint8_t MCSE       : 1;
+  __IO  uint8_t SCSE       : 1;
+  __IO  uint8_t PCSE       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSE       : 1;
+} stc_crg_int_enr_field_t;
+
+typedef struct stc_crg_int_str_field
+{
+  __IO  uint8_t MCSI       : 1;
+  __IO  uint8_t SCSI       : 1;
+  __IO  uint8_t PCSI       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSI       : 1;
+} stc_crg_int_str_field_t;
+
+typedef struct stc_crg_int_clr_field
+{
+  __IO  uint8_t MCSC       : 1;
+  __IO  uint8_t SCSC       : 1;
+  __IO  uint8_t PCSC       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t FCSC       : 1;
+} stc_crg_int_clr_field_t;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* HWWDT_MODULE register bit fields */
+typedef struct stc_hwwdt_wdg_ctl_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_hwwdt_wdg_ctl_field_t;
+
+typedef struct stc_hwwdt_wdg_ris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_hwwdt_wdg_ris_field_t;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* SWWDT_MODULE register bit fields */
+typedef struct stc_swwdt_wdogcontrol_field
+{
+  __IO  uint8_t INTEN      : 1;
+  __IO  uint8_t RESEN      : 1;
+} stc_swwdt_wdogcontrol_field_t;
+
+typedef struct stc_swwdt_wdogris_field
+{
+  __IO  uint8_t RIS        : 1;
+} stc_swwdt_wdogris_field_t;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* DTIM_MODULE register bit fields */
+typedef struct stc_dtim_timer1control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer1control_field_t;
+
+typedef struct stc_dtim_timer1ris_field
+{
+  __IO uint32_t TIMER1RIS  : 1;
+} stc_dtim_timer1ris_field_t;
+
+typedef struct stc_dtim_timer1mis_field
+{
+  __IO uint32_t TIMER1MIS  : 1;
+} stc_dtim_timer1mis_field_t;
+
+typedef struct stc_dtim_timer2control_field
+{
+  __IO uint32_t ONESHOT    : 1;
+  __IO uint32_t TIMERSIZE  : 1;
+  __IO uint32_t TIMERPRE0  : 1;
+  __IO uint32_t TIMERPRE1  : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t INTENABLE  : 1;
+  __IO uint32_t TIMERMODE  : 1;
+  __IO uint32_t TIMEREN    : 1;
+} stc_dtim_timer2control_field_t;
+
+typedef struct stc_dtim_timer2ris_field
+{
+  __IO uint32_t TIMER2RIS  : 1;
+} stc_dtim_timer2ris_field_t;
+
+typedef struct stc_dtim_timer2mis_field
+{
+  __IO uint32_t TIMER2MIS  : 1;
+} stc_dtim_timer2mis_field_t;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* MFT_FRT_MODULE register bit fields */
+typedef struct stc_mft_frt_tcsa0_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa0_field_t;
+
+typedef struct stc_mft_frt_tcsb0_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb0_field_t;
+
+typedef struct stc_mft_frt_tcsa1_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa1_field_t;
+
+typedef struct stc_mft_frt_tcsb1_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb1_field_t;
+
+typedef struct stc_mft_frt_tcsa2_field
+{
+  __IO uint16_t CLK0       : 1;
+  __IO uint16_t CLK1       : 1;
+  __IO uint16_t CLK2       : 1;
+  __IO uint16_t CLK3       : 1;
+  __IO uint16_t SCLR       : 1;
+  __IO uint16_t MODE       : 1;
+  __IO uint16_t STOP       : 1;
+  __IO uint16_t BFE        : 1;
+  __IO uint16_t ICRE       : 1;
+  __IO uint16_t ICLR       : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t IRQZE      : 1;
+  __IO uint16_t IRQZF      : 1;
+  __IO uint16_t ECKE       : 1;
+} stc_mft_frt_tcsa2_field_t;
+
+typedef struct stc_mft_frt_tcsb2_field
+{
+  __IO uint16_t AD0E       : 1;
+  __IO uint16_t AD1E       : 1;
+  __IO uint16_t AD2E       : 1;
+} stc_mft_frt_tcsb2_field_t;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* MFT_OCU_MODULE register bit fields */
+typedef struct stc_mft_ocu_ocsa10_field
+{
+  __IO  uint8_t CST0       : 1;
+  __IO  uint8_t CST1       : 1;
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t IOE0       : 1;
+  __IO  uint8_t IOE1       : 1;
+  __IO  uint8_t IOP0       : 1;
+  __IO  uint8_t IOP1       : 1;
+} stc_mft_ocu_ocsa10_field_t;
+
+typedef struct stc_mft_ocu_ocsb10_field
+{
+  __IO  uint8_t OTD0       : 1;
+  __IO  uint8_t OTD1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+} stc_mft_ocu_ocsb10_field_t;
+
+typedef struct stc_mft_ocu_ocsa32_field
+{
+  __IO  uint8_t CST2       : 1;
+  __IO  uint8_t CST3       : 1;
+  __IO  uint8_t BDIS2      : 1;
+  __IO  uint8_t BDIS3      : 1;
+  __IO  uint8_t IOE2       : 1;
+  __IO  uint8_t IOE3       : 1;
+  __IO  uint8_t IOP2       : 1;
+  __IO  uint8_t IOP3       : 1;
+} stc_mft_ocu_ocsa32_field_t;
+
+typedef struct stc_mft_ocu_ocsb32_field
+{
+  __IO  uint8_t OTD2       : 1;
+  __IO  uint8_t OTD3       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS2       : 1;
+  __IO  uint8_t BTS3       : 1;
+} stc_mft_ocu_ocsb32_field_t;
+
+typedef struct stc_mft_ocu_ocsa54_field
+{
+  __IO  uint8_t CST4       : 1;
+  __IO  uint8_t CST5       : 1;
+  __IO  uint8_t BDIS4      : 1;
+  __IO  uint8_t BDIS5      : 1;
+  __IO  uint8_t IOE4       : 1;
+  __IO  uint8_t IOE5       : 1;
+  __IO  uint8_t IOP4       : 1;
+  __IO  uint8_t IOP5       : 1;
+} stc_mft_ocu_ocsa54_field_t;
+
+typedef struct stc_mft_ocu_ocsb54_field
+{
+  __IO  uint8_t OTD4       : 1;
+  __IO  uint8_t OTD5       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CMOD       : 1;
+  __IO  uint8_t BTS4       : 1;
+  __IO  uint8_t BTS5       : 1;
+} stc_mft_ocu_ocsb54_field_t;
+
+typedef struct stc_mft_ocu_ocsc_field
+{
+  __IO  uint8_t MOD0       : 1;
+  __IO  uint8_t MOD1       : 1;
+  __IO  uint8_t MOD2       : 1;
+  __IO  uint8_t MOD3       : 1;
+  __IO  uint8_t MOD4       : 1;
+  __IO  uint8_t MOD5       : 1;
+} stc_mft_ocu_ocsc_field_t;
+
+typedef struct stc_mft_ocu_ocfs10_field
+{
+  __IO  uint8_t FSO00      : 1;
+  __IO  uint8_t FSO01      : 1;
+  __IO  uint8_t FSO02      : 1;
+  __IO  uint8_t FSO03      : 1;
+  __IO  uint8_t FSO10      : 1;
+  __IO  uint8_t FSO11      : 1;
+  __IO  uint8_t FSO12      : 1;
+  __IO  uint8_t FSO13      : 1;
+} stc_mft_ocu_ocfs10_field_t;
+
+typedef struct stc_mft_ocu_ocfs32_field
+{
+  __IO  uint8_t FSO20      : 1;
+  __IO  uint8_t FSO21      : 1;
+  __IO  uint8_t FSO22      : 1;
+  __IO  uint8_t FSO23      : 1;
+  __IO  uint8_t FSO30      : 1;
+  __IO  uint8_t FSO31      : 1;
+  __IO  uint8_t FSO32      : 1;
+  __IO  uint8_t FSO33      : 1;
+} stc_mft_ocu_ocfs32_field_t;
+
+typedef struct stc_mft_ocu_ocfs54_field
+{
+  __IO  uint8_t FSO40      : 1;
+  __IO  uint8_t FSO41      : 1;
+  __IO  uint8_t FSO42      : 1;
+  __IO  uint8_t FSO43      : 1;
+  __IO  uint8_t FSO50      : 1;
+  __IO  uint8_t FSO51      : 1;
+  __IO  uint8_t FSO52      : 1;
+  __IO  uint8_t FSO53      : 1;
+} stc_mft_ocu_ocfs54_field_t;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* MFT_WFG_MODULE register bit fields */
+typedef struct stc_mft_wfg_wfsa10_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD        : 3;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa10_field_t;
+
+typedef struct stc_mft_wfg_wfsa32_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD        : 3;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa32_field_t;
+
+typedef struct stc_mft_wfg_wfsa54_field
+{
+  __IO uint16_t DCK0       : 1;
+  __IO uint16_t DCK1       : 1;
+  __IO uint16_t DCK2       : 1;
+  __IO uint16_t TMD        : 3;
+  __IO uint16_t GTEN0      : 1;
+  __IO uint16_t GTEN1      : 1;
+  __IO uint16_t PSEL0      : 1;
+  __IO uint16_t PSEL1      : 1;
+  __IO uint16_t PGEN0      : 1;
+  __IO uint16_t PGEN1      : 1;
+  __IO uint16_t DMOD       : 1;
+} stc_mft_wfg_wfsa54_field_t;
+
+typedef struct stc_mft_wfg_wfir_field
+{
+  __IO uint16_t DTIF       : 1;
+  __IO uint16_t DTIC       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t TMIF10     : 1;
+  __IO uint16_t TMIC10     : 1;
+  __IO uint16_t TMIE10     : 1;
+  __IO uint16_t TMIS10     : 1;
+  __IO uint16_t TMIF32     : 1;
+  __IO uint16_t TMIC32     : 1;
+  __IO uint16_t TMIE32     : 1;
+  __IO uint16_t TMIS32     : 1;
+  __IO uint16_t TMIF54     : 1;
+  __IO uint16_t TMIC54     : 1;
+  __IO uint16_t TMIE54     : 1;
+  __IO uint16_t TMIS54     : 1;
+} stc_mft_wfg_wfir_field_t;
+
+typedef struct stc_mft_wfg_nzcl_field
+{
+  __IO uint16_t DTIE       : 1;
+  __IO uint16_t NWS0       : 1;
+  __IO uint16_t NWS1       : 1;
+  __IO uint16_t NWS2       : 1;
+  __IO uint16_t SDTI       : 1;
+} stc_mft_wfg_nzcl_field_t;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* MFT_ICU_MODULE register bit fields */
+typedef struct stc_mft_icu_icfs10_field
+{
+  __IO  uint8_t FSI00      : 1;
+  __IO  uint8_t FSI01      : 1;
+  __IO  uint8_t FSI02      : 1;
+  __IO  uint8_t FSI03      : 1;
+  __IO  uint8_t FSI10      : 1;
+  __IO  uint8_t FSI11      : 1;
+  __IO  uint8_t FSI12      : 1;
+  __IO  uint8_t FSI13      : 1;
+} stc_mft_icu_icfs10_field_t;
+
+typedef struct stc_mft_icu_icfs32_field
+{
+  __IO  uint8_t FSI20      : 1;
+  __IO  uint8_t FSI21      : 1;
+  __IO  uint8_t FSI22      : 1;
+  __IO  uint8_t FSI23      : 1;
+  __IO  uint8_t FSI30      : 1;
+  __IO  uint8_t FSI31      : 1;
+  __IO  uint8_t FSI32      : 1;
+  __IO  uint8_t FSI33      : 1;
+} stc_mft_icu_icfs32_field_t;
+
+typedef struct stc_mft_icu_icsa10_field
+{
+  __IO  uint8_t EG00       : 1;
+  __IO  uint8_t EG01       : 1;
+  __IO  uint8_t EG10       : 1;
+  __IO  uint8_t EG11       : 1;
+  __IO  uint8_t ICE0       : 1;
+  __IO  uint8_t ICE1       : 1;
+  __IO  uint8_t ICP0       : 1;
+  __IO  uint8_t ICP1       : 1;
+} stc_mft_icu_icsa10_field_t;
+
+typedef struct stc_mft_icu_icsb10_field
+{
+  __IO  uint8_t IEI0       : 1;
+  __IO  uint8_t IEI1       : 1;
+} stc_mft_icu_icsb10_field_t;
+
+typedef struct stc_mft_icu_icsa32_field
+{
+  __IO  uint8_t EG20       : 1;
+  __IO  uint8_t EG21       : 1;
+  __IO  uint8_t EG30       : 1;
+  __IO  uint8_t EG31       : 1;
+  __IO  uint8_t ICE2       : 1;
+  __IO  uint8_t ICE3       : 1;
+  __IO  uint8_t ICP2       : 1;
+  __IO  uint8_t ICP3       : 1;
+} stc_mft_icu_icsa32_field_t;
+
+typedef struct stc_mft_icu_icsb32_field
+{
+  __IO  uint8_t IEI2       : 1;
+  __IO  uint8_t IEI3       : 1;
+} stc_mft_icu_icsb32_field_t;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* MFT_ADCMP_MODULE register bit fields */
+typedef struct stc_mft_adcmp_acsb_field
+{
+  __IO  uint8_t BDIS0      : 1;
+  __IO  uint8_t BDIS1      : 1;
+  __IO  uint8_t BDIS2      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BTS0       : 1;
+  __IO  uint8_t BTS1       : 1;
+  __IO  uint8_t BTS2       : 1;
+} stc_mft_adcmp_acsb_field_t;
+
+typedef struct stc_mft_adcmp_acsa_field
+{
+  __IO uint16_t CE00       : 1;
+  __IO uint16_t CE01       : 1;
+  __IO uint16_t CE10       : 1;
+  __IO uint16_t CE11       : 1;
+  __IO uint16_t CE20       : 1;
+  __IO uint16_t CE21       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SEL00      : 1;
+  __IO uint16_t SEL01      : 1;
+  __IO uint16_t SEL10      : 1;
+  __IO uint16_t SEL11      : 1;
+  __IO uint16_t SEL20      : 1;
+  __IO uint16_t SEL21      : 1;
+} stc_mft_adcmp_acsa_field_t;
+
+typedef struct stc_mft_adcmp_atsa_field
+{
+  __IO uint16_t AD0S0      : 1;
+  __IO uint16_t AD0S1      : 1;
+  __IO uint16_t AD1S0      : 1;
+  __IO uint16_t AD1S1      : 1;
+  __IO uint16_t AD2S0      : 1;
+  __IO uint16_t AD2S1      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t AD0P0      : 1;
+  __IO uint16_t AD0P1      : 1;
+  __IO uint16_t AD1P0      : 1;
+  __IO uint16_t AD1P1      : 1;
+  __IO uint16_t AD2P0      : 1;
+  __IO uint16_t AD2P1      : 1;
+} stc_mft_adcmp_atsa_field_t;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* MFT_PPG_MODULE register bit fields */
+typedef struct stc_mft_ppg_ttcr0_field
+{
+  __IO  uint8_t STR0       : 1;
+  __IO  uint8_t MONI0      : 1;
+  __IO  uint8_t CS00       : 1;
+  __IO  uint8_t CS01       : 1;
+  __IO  uint8_t TRG0O      : 1;
+  __IO  uint8_t TRG2O      : 1;
+  __IO  uint8_t TRG4O      : 1;
+  __IO  uint8_t TRG6O      : 1;
+} stc_mft_ppg_ttcr0_field_t;
+
+typedef struct stc_mft_ppg_ttcr1_field
+{
+  __IO  uint8_t STR1       : 1;
+  __IO  uint8_t MONI1      : 1;
+  __IO  uint8_t CS10       : 1;
+  __IO  uint8_t CS11       : 1;
+  __IO  uint8_t TRG1O      : 1;
+  __IO  uint8_t TRG3O      : 1;
+  __IO  uint8_t TRG5O      : 1;
+  __IO  uint8_t TRG7O      : 1;
+} stc_mft_ppg_ttcr1_field_t;
+
+typedef struct stc_mft_ppg_ttcr2_field
+{
+  __IO  uint8_t STR2       : 1;
+  __IO  uint8_t MONI2      : 1;
+  __IO  uint8_t CS20       : 1;
+  __IO  uint8_t CS21       : 1;
+  __IO  uint8_t TRG16O     : 1;
+  __IO  uint8_t TRG18O     : 1;
+  __IO  uint8_t TRG20O     : 1;
+  __IO  uint8_t TRG22O     : 1;
+} stc_mft_ppg_ttcr2_field_t;
+
+typedef struct stc_mft_ppg_trg_field
+{
+  __IO uint16_t PEN00      : 1;
+  __IO uint16_t PEN01      : 1;
+  __IO uint16_t PEN02      : 1;
+  __IO uint16_t PEN03      : 1;
+  __IO uint16_t PEN04      : 1;
+  __IO uint16_t PEN05      : 1;
+  __IO uint16_t PEN06      : 1;
+  __IO uint16_t PEN07      : 1;
+  __IO uint16_t PEN08      : 1;
+  __IO uint16_t PEN09      : 1;
+  __IO uint16_t PEN10      : 1;
+  __IO uint16_t PEN11      : 1;
+  __IO uint16_t PEN12      : 1;
+  __IO uint16_t PEN13      : 1;
+  __IO uint16_t PEN14      : 1;
+  __IO uint16_t PEN15      : 1;
+} stc_mft_ppg_trg_field_t;
+
+typedef struct stc_mft_ppg_trg1_field
+{
+  __IO uint16_t PEN16      : 1;
+  __IO uint16_t PEN17      : 1;
+  __IO uint16_t PEN18      : 1;
+  __IO uint16_t PEN19      : 1;
+  __IO uint16_t PEN20      : 1;
+  __IO uint16_t PEN21      : 1;
+  __IO uint16_t PEN22      : 1;
+  __IO uint16_t PEN23      : 1;
+} stc_mft_ppg_trg1_field_t;
+
+typedef struct stc_mft_ppg_revc_field
+{
+  __IO uint16_t REV00      : 1;
+  __IO uint16_t REV01      : 1;
+  __IO uint16_t REV02      : 1;
+  __IO uint16_t REV03      : 1;
+  __IO uint16_t REV04      : 1;
+  __IO uint16_t REV05      : 1;
+  __IO uint16_t REV06      : 1;
+  __IO uint16_t REV07      : 1;
+  __IO uint16_t REV08      : 1;
+  __IO uint16_t REV09      : 1;
+  __IO uint16_t REV10      : 1;
+  __IO uint16_t REV11      : 1;
+  __IO uint16_t REV12      : 1;
+  __IO uint16_t REV13      : 1;
+  __IO uint16_t REV14      : 1;
+  __IO uint16_t REV15      : 1;
+} stc_mft_ppg_revc_field_t;
+
+typedef struct stc_mft_ppg_revc1_field
+{
+  __IO uint16_t REV16      : 1;
+  __IO uint16_t REV17      : 1;
+  __IO uint16_t REV18      : 1;
+  __IO uint16_t REV19      : 1;
+  __IO uint16_t REV20      : 1;
+  __IO uint16_t REV21      : 1;
+  __IO uint16_t REV22      : 1;
+  __IO uint16_t REV23      : 1;
+} stc_mft_ppg_revc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc1_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc1_field_t;
+
+typedef struct stc_mft_ppg_ppgc0_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc0_field_t;
+
+typedef struct stc_mft_ppg_ppgc3_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc3_field_t;
+
+typedef struct stc_mft_ppg_ppgc2_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc2_field_t;
+
+typedef struct stc_mft_ppg_gatec0_field
+{
+  __IO  uint8_t EDGE0      : 1;
+  __IO  uint8_t STRG0      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE2      : 1;
+  __IO  uint8_t STRG2      : 1;
+} stc_mft_ppg_gatec0_field_t;
+
+typedef struct stc_mft_ppg_ppgc5_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc5_field_t;
+
+typedef struct stc_mft_ppg_ppgc4_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc4_field_t;
+
+typedef struct stc_mft_ppg_ppgc7_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc7_field_t;
+
+typedef struct stc_mft_ppg_ppgc6_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc6_field_t;
+
+typedef struct stc_mft_ppg_gatec4_field
+{
+  __IO  uint8_t EDGE4      : 1;
+  __IO  uint8_t STRG4      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE6      : 1;
+  __IO  uint8_t STRG6      : 1;
+} stc_mft_ppg_gatec4_field_t;
+
+typedef struct stc_mft_ppg_ppgc9_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc9_field_t;
+
+typedef struct stc_mft_ppg_ppgc8_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc8_field_t;
+
+typedef struct stc_mft_ppg_ppgc11_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc11_field_t;
+
+typedef struct stc_mft_ppg_ppgc10_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc10_field_t;
+
+typedef struct stc_mft_ppg_gatec8_field
+{
+  __IO  uint8_t EDGE8      : 1;
+  __IO  uint8_t STRG8      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE10     : 1;
+  __IO  uint8_t STRG10     : 1;
+} stc_mft_ppg_gatec8_field_t;
+
+typedef struct stc_mft_ppg_ppgc13_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc13_field_t;
+
+typedef struct stc_mft_ppg_ppgc12_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc12_field_t;
+
+typedef struct stc_mft_ppg_ppgc15_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc15_field_t;
+
+typedef struct stc_mft_ppg_ppgc14_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc14_field_t;
+
+typedef struct stc_mft_ppg_gatec12_field
+{
+  __IO  uint8_t EDGE12     : 1;
+  __IO  uint8_t STRG12     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE14     : 1;
+  __IO  uint8_t STRG14     : 1;
+} stc_mft_ppg_gatec12_field_t;
+
+typedef struct stc_mft_ppg_ppgc17_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc17_field_t;
+
+typedef struct stc_mft_ppg_ppgc16_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc16_field_t;
+
+typedef struct stc_mft_ppg_ppgc19_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc19_field_t;
+
+typedef struct stc_mft_ppg_ppgc18_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc18_field_t;
+
+typedef struct stc_mft_ppg_gatec16_field
+{
+  __IO  uint8_t EDGE16     : 1;
+  __IO  uint8_t STRG16     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE18     : 1;
+  __IO  uint8_t STRG18     : 1;
+} stc_mft_ppg_gatec16_field_t;
+
+typedef struct stc_mft_ppg_ppgc21_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc21_field_t;
+
+typedef struct stc_mft_ppg_ppgc20_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc20_field_t;
+
+typedef struct stc_mft_ppg_ppgc23_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc23_field_t;
+
+typedef struct stc_mft_ppg_ppgc22_field
+{
+  __IO  uint8_t TTRG       : 1;
+  __IO  uint8_t MD         : 2;
+  __IO  uint8_t PCS0       : 1;
+  __IO  uint8_t PCS1       : 1;
+  __IO  uint8_t INTM       : 1;
+  __IO  uint8_t PUF        : 1;
+  __IO  uint8_t PIE        : 1;
+} stc_mft_ppg_ppgc22_field_t;
+
+typedef struct stc_mft_ppg_gatec20_field
+{
+  __IO  uint8_t EDGE20     : 1;
+  __IO  uint8_t STRG20     : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t EDGE22     : 1;
+  __IO  uint8_t STRG22     : 1;
+} stc_mft_ppg_gatec20_field_t;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* BT_PPG_MODULE register bit fields */
+typedef struct stc_bt_ppg_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD        : 3;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_ppg_tmcr_field_t;
+
+typedef struct stc_bt_ppg_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_ppg_stc_field_t;
+
+typedef struct stc_bt_ppg_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_ppg_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* BT_PWM_MODULE register bit fields */
+typedef struct stc_bt_pwm_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD        : 3;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t PMSK       : 1;
+  __IO uint16_t RTGEN      : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwm_tmcr_field_t;
+
+typedef struct stc_bt_pwm_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+  __IO  uint8_t DTIR       : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t UDIE       : 1;
+  __IO  uint8_t DTIE       : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_pwm_stc_field_t;
+
+typedef struct stc_bt_pwm_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwm_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* BT_RT_MODULE register bit fields */
+typedef struct stc_bt_rt_tmcr_field
+{
+  __IO uint16_t STRG       : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+  __IO uint16_t OSEL       : 1;
+  __IO uint16_t FMD        : 3;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_rt_tmcr_field_t;
+
+typedef struct stc_bt_rt_stc_field
+{
+  __IO  uint8_t UDIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TGIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t UDIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t TGIE       : 1;
+} stc_bt_rt_stc_field_t;
+
+typedef struct stc_bt_rt_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_rt_tmcr2_field_t;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* BT_PWC_MODULE register bit fields */
+typedef struct stc_bt_pwc_tmcr_field
+{
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t CTEN       : 1;
+  __IO uint16_t MDSE       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FMD        : 3;
+  __IO uint16_t T32        : 1;
+  __IO uint16_t EGS0       : 1;
+  __IO uint16_t EGS1       : 1;
+  __IO uint16_t EGS2       : 1;
+       uint16_t RESERVED3  : 1;
+  __IO uint16_t CKS0       : 1;
+  __IO uint16_t CKS1       : 1;
+  __IO uint16_t CKS2       : 1;
+} stc_bt_pwc_tmcr_field_t;
+
+typedef struct stc_bt_pwc_stc_field
+{
+  __IO  uint8_t OVIR       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t EDIR       : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t OVIE       : 1;
+        uint8_t RESERVED3  : 1;
+  __IO  uint8_t EDIE       : 1;
+  __IO  uint8_t ERR        : 1;
+} stc_bt_pwc_stc_field_t;
+
+typedef struct stc_bt_pwc_tmcr2_field
+{
+  __IO  uint8_t CKS3       : 1;
+} stc_bt_pwc_tmcr2_field_t;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* BTIOSEL03_MODULE register bit fields */
+typedef struct stc_btiosel03_btsel0123_field
+{
+  __IO  uint8_t SEL01_0    : 1;
+  __IO  uint8_t SEL01_1    : 1;
+  __IO  uint8_t SEL01_2    : 1;
+  __IO  uint8_t SEL01_3    : 1;
+  __IO  uint8_t SEL23_0    : 1;
+  __IO  uint8_t SEL23_1    : 1;
+  __IO  uint8_t SEL23_2    : 1;
+  __IO  uint8_t SEL23_3    : 1;
+} stc_btiosel03_btsel0123_field_t;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* BTIOSEL47_MODULE register bit fields */
+typedef struct stc_btiosel47_btsel4567_field
+{
+  __IO  uint8_t SEL45_0    : 1;
+  __IO  uint8_t SEL45_1    : 1;
+  __IO  uint8_t SEL45_2    : 1;
+  __IO  uint8_t SEL45_3    : 1;
+  __IO  uint8_t SEL67_0    : 1;
+  __IO  uint8_t SEL67_1    : 1;
+  __IO  uint8_t SEL67_2    : 1;
+  __IO  uint8_t SEL67_3    : 1;
+} stc_btiosel47_btsel4567_field_t;
+
+/******************************************************************************
+ * BTIOSEL811_MODULE
+ ******************************************************************************/
+/* BTIOSEL811_MODULE register bit fields */
+typedef struct stc_btiosel8b_btsel89ab_field
+{
+  __IO  uint8_t SEL89_0    : 1;
+  __IO  uint8_t SEL89_1    : 1;
+  __IO  uint8_t SEL89_2    : 1;
+  __IO  uint8_t SEL89_3    : 1;
+  __IO  uint8_t SELAB_0    : 1;
+  __IO  uint8_t SELAB_1    : 1;
+  __IO  uint8_t SELAB_2    : 1;
+  __IO  uint8_t SELAB_3    : 1;
+} stc_btiosel8b_btsel89ab_field_t;
+
+/******************************************************************************
+ * BTIOSEL1215_MODULE
+ ******************************************************************************/
+/* BTIOSEL1215_MODULE register bit fields */
+typedef struct stc_btioselcf_btselcdef_field
+{
+  __IO  uint8_t SELCD_0    : 1;
+  __IO  uint8_t SELCD_1    : 1;
+  __IO  uint8_t SELCD_2    : 1;
+  __IO  uint8_t SELCD_3    : 1;
+  __IO  uint8_t SELEF_0    : 1;
+  __IO  uint8_t SELEF_1    : 1;
+  __IO  uint8_t SELEF_2    : 1;
+  __IO  uint8_t SELEF_3    : 1;
+} stc_btioselcf_btselcdef_field_t;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* SBSSR_MODULE register bit fields */
+typedef struct stc_sbssr_btsssr_field
+{
+  __IO uint16_t SSR0       : 1;
+  __IO uint16_t SSR1       : 1;
+  __IO uint16_t SSR2       : 1;
+  __IO uint16_t SSR3       : 1;
+  __IO uint16_t SSR4       : 1;
+  __IO uint16_t SSR5       : 1;
+  __IO uint16_t SSR6       : 1;
+  __IO uint16_t SSR7       : 1;
+  __IO uint16_t SSR8       : 1;
+  __IO uint16_t SSR9       : 1;
+  __IO uint16_t SSR10      : 1;
+  __IO uint16_t SSR11      : 1;
+  __IO uint16_t SSR12      : 1;
+  __IO uint16_t SSR13      : 1;
+  __IO uint16_t SSR14      : 1;
+  __IO uint16_t SSR15      : 1;
+} stc_sbssr_btsssr_field_t;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* QPRC_MODULE register bit fields */
+typedef struct stc_qprc_qicr_field
+{
+  __IO uint16_t QPCMIE     : 1;
+  __IO uint16_t QPCMF      : 1;
+  __IO uint16_t QPRCMIE    : 1;
+  __IO uint16_t QPRCMF     : 1;
+  __IO uint16_t OUZIE      : 1;
+  __IO uint16_t UFDF       : 1;
+  __IO uint16_t OFDF       : 1;
+  __IO uint16_t ZIIF       : 1;
+  __IO uint16_t CDCIE      : 1;
+  __IO uint16_t CDCF       : 1;
+  __IO uint16_t DIRPC      : 1;
+  __IO uint16_t DIROU      : 1;
+  __IO uint16_t QPCNRCMIE  : 1;
+  __IO uint16_t QPCNRCMF   : 1;
+} stc_qprc_qicr_field_t;
+
+typedef struct stc_qprc_qicrl_field
+{
+  __IO  uint8_t QPCMIE     : 1;
+  __IO  uint8_t QPCMF      : 1;
+  __IO  uint8_t QPRCMIE    : 1;
+  __IO  uint8_t QPRCMF     : 1;
+  __IO  uint8_t OUZIE      : 1;
+  __IO  uint8_t UFDF       : 1;
+  __IO  uint8_t OFDF       : 1;
+  __IO  uint8_t ZIIF       : 1;
+} stc_qprc_qicrl_field_t;
+
+typedef struct stc_qprc_qicrh_field
+{
+  __IO  uint8_t CDCIE      : 1;
+  __IO  uint8_t CDCF       : 1;
+  __IO  uint8_t DIRPC      : 1;
+  __IO  uint8_t DIROU      : 1;
+  __IO  uint8_t QPCNRCMIE  : 1;
+  __IO  uint8_t QPCNRCMF   : 1;
+} stc_qprc_qicrh_field_t;
+
+typedef struct stc_qprc_qcr_field
+{
+  __IO uint16_t PCM0       : 1;
+  __IO uint16_t PCM1       : 1;
+  __IO uint16_t RCM0       : 1;
+  __IO uint16_t RCM1       : 1;
+  __IO uint16_t PSTP       : 1;
+  __IO uint16_t CGSC       : 1;
+  __IO uint16_t RSEL       : 1;
+  __IO uint16_t SWAP       : 1;
+  __IO uint16_t PCRM0      : 1;
+  __IO uint16_t PCRM1      : 1;
+  __IO uint16_t AES0       : 1;
+  __IO uint16_t AES1       : 1;
+  __IO uint16_t BES0       : 1;
+  __IO uint16_t BES1       : 1;
+  __IO uint16_t CGE0       : 1;
+  __IO uint16_t CGE1       : 1;
+} stc_qprc_qcr_field_t;
+
+typedef struct stc_qprc_qcrl_field
+{
+  __IO  uint8_t PCM0       : 1;
+  __IO  uint8_t PCM1       : 1;
+  __IO  uint8_t RCM0       : 1;
+  __IO  uint8_t RCM1       : 1;
+  __IO  uint8_t PSTP       : 1;
+  __IO  uint8_t CGSC       : 1;
+  __IO  uint8_t RSEL       : 1;
+  __IO  uint8_t SWAP       : 1;
+} stc_qprc_qcrl_field_t;
+
+typedef struct stc_qprc_qcrh_field
+{
+  __IO  uint8_t PCRM0      : 1;
+  __IO  uint8_t PCRM1      : 1;
+  __IO  uint8_t AES0       : 1;
+  __IO  uint8_t AES1       : 1;
+  __IO  uint8_t BES0       : 1;
+  __IO  uint8_t BES1       : 1;
+  __IO  uint8_t CGE0       : 1;
+  __IO  uint8_t CGE1       : 1;
+} stc_qprc_qcrh_field_t;
+
+typedef struct stc_qprc_qecr_field
+{
+  __IO uint16_t ORNGMD     : 1;
+  __IO uint16_t ORNGF      : 1;
+  __IO uint16_t ORNGIE     : 1;
+} stc_qprc_qecr_field_t;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* ADC12_MODULE register bit fields */
+typedef struct stc_adc_adsr_field
+{
+  __IO  uint8_t SCS        : 1;
+  __IO  uint8_t PCS        : 1;
+  __IO  uint8_t PCNS       : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t FDAS       : 1;
+  __IO  uint8_t ADSTP      : 1;
+} stc_adc_adsr_field_t;
+
+typedef struct stc_adc_adcr_field
+{
+  __IO  uint8_t OVRIE      : 1;
+  __IO  uint8_t CMPIE      : 1;
+  __IO  uint8_t PCIE       : 1;
+  __IO  uint8_t SCIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t CMPIF      : 1;
+  __IO  uint8_t PCIF       : 1;
+  __IO  uint8_t SCIF       : 1;
+} stc_adc_adcr_field_t;
+
+typedef struct stc_adc_sfns_field
+{
+  __IO  uint8_t SFS0       : 1;
+  __IO  uint8_t SFS1       : 1;
+  __IO  uint8_t SFS2       : 1;
+  __IO  uint8_t SFS3       : 1;
+} stc_adc_sfns_field_t;
+
+typedef struct stc_adc_sccr_field
+{
+  __IO  uint8_t SSTR       : 1;
+  __IO  uint8_t SHEN       : 1;
+  __IO  uint8_t RPT        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t SFCLR      : 1;
+  __IO  uint8_t SOVR       : 1;
+  __IO  uint8_t SFUL       : 1;
+  __IO  uint8_t SEMP       : 1;
+} stc_adc_sccr_field_t;
+
+typedef struct stc_adc_scfd_field
+{
+  __IO uint32_t SC0        : 1;
+  __IO uint32_t SC1        : 1;
+  __IO uint32_t SC2        : 1;
+  __IO uint32_t SC3        : 1;
+  __IO uint32_t SC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t SD0        : 1;
+  __IO uint32_t SD1        : 1;
+  __IO uint32_t SD2        : 1;
+  __IO uint32_t SD3        : 1;
+  __IO uint32_t SD4        : 1;
+  __IO uint32_t SD5        : 1;
+  __IO uint32_t SD6        : 1;
+  __IO uint32_t SD7        : 1;
+  __IO uint32_t SD8        : 1;
+  __IO uint32_t SD9        : 1;
+  __IO uint32_t SD10       : 1;
+  __IO uint32_t SD11       : 1;
+} stc_adc_scfd_field_t;
+
+typedef struct stc_adc_scfdl_field
+{
+  __IO uint16_t SC0        : 1;
+  __IO uint16_t SC1        : 1;
+  __IO uint16_t SC2        : 1;
+  __IO uint16_t SC3        : 1;
+  __IO uint16_t SC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t INVL       : 1;
+} stc_adc_scfdl_field_t;
+
+typedef struct stc_adc_scfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t SD0        : 1;
+  __IO uint16_t SD1        : 1;
+  __IO uint16_t SD2        : 1;
+  __IO uint16_t SD3        : 1;
+  __IO uint16_t SD4        : 1;
+  __IO uint16_t SD5        : 1;
+  __IO uint16_t SD6        : 1;
+  __IO uint16_t SD7        : 1;
+  __IO uint16_t SD8        : 1;
+  __IO uint16_t SD9        : 1;
+  __IO uint16_t SD10       : 1;
+  __IO uint16_t SD11       : 1;
+} stc_adc_scfdh_field_t;
+
+typedef struct stc_adc_scis23_field
+{
+  __IO uint16_t AN16       : 1;
+  __IO uint16_t AN17       : 1;
+  __IO uint16_t AN18       : 1;
+  __IO uint16_t AN19       : 1;
+  __IO uint16_t AN20       : 1;
+  __IO uint16_t AN21       : 1;
+  __IO uint16_t AN22       : 1;
+  __IO uint16_t AN23       : 1;
+  __IO uint16_t AN24       : 1;
+  __IO uint16_t AN25       : 1;
+  __IO uint16_t AN26       : 1;
+  __IO uint16_t AN27       : 1;
+  __IO uint16_t AN28       : 1;
+  __IO uint16_t AN29       : 1;
+  __IO uint16_t AN30       : 1;
+  __IO uint16_t AN31       : 1;
+} stc_adc_scis23_field_t;
+
+typedef struct stc_adc_scis2_field
+{
+  __IO  uint8_t AN16       : 1;
+  __IO  uint8_t AN17       : 1;
+  __IO  uint8_t AN18       : 1;
+  __IO  uint8_t AN19       : 1;
+  __IO  uint8_t AN20       : 1;
+  __IO  uint8_t AN21       : 1;
+  __IO  uint8_t AN22       : 1;
+  __IO  uint8_t AN23       : 1;
+} stc_adc_scis2_field_t;
+
+typedef struct stc_adc_scis3_field
+{
+  __IO  uint8_t AN24       : 1;
+  __IO  uint8_t AN25       : 1;
+  __IO  uint8_t AN26       : 1;
+  __IO  uint8_t AN27       : 1;
+  __IO  uint8_t AN28       : 1;
+  __IO  uint8_t AN29       : 1;
+  __IO  uint8_t AN30       : 1;
+  __IO  uint8_t AN31       : 1;
+} stc_adc_scis3_field_t;
+
+typedef struct stc_adc_scis01_field
+{
+  __IO uint16_t AN0        : 1;
+  __IO uint16_t AN1        : 1;
+  __IO uint16_t AN2        : 1;
+  __IO uint16_t AN3        : 1;
+  __IO uint16_t AN4        : 1;
+  __IO uint16_t AN5        : 1;
+  __IO uint16_t AN6        : 1;
+  __IO uint16_t AN7        : 1;
+  __IO uint16_t AN8        : 1;
+  __IO uint16_t AN9        : 1;
+  __IO uint16_t AN10       : 1;
+  __IO uint16_t AN11       : 1;
+  __IO uint16_t AN12       : 1;
+  __IO uint16_t AN13       : 1;
+  __IO uint16_t AN14       : 1;
+  __IO uint16_t AN15       : 1;
+} stc_adc_scis01_field_t;
+
+typedef struct stc_adc_scis0_field
+{
+  __IO  uint8_t AN0        : 1;
+  __IO  uint8_t AN1        : 1;
+  __IO  uint8_t AN2        : 1;
+  __IO  uint8_t AN3        : 1;
+  __IO  uint8_t AN4        : 1;
+  __IO  uint8_t AN5        : 1;
+  __IO  uint8_t AN6        : 1;
+  __IO  uint8_t AN7        : 1;
+} stc_adc_scis0_field_t;
+
+typedef struct stc_adc_scis1_field
+{
+  __IO  uint8_t AN8        : 1;
+  __IO  uint8_t AN9        : 1;
+  __IO  uint8_t AN10       : 1;
+  __IO  uint8_t AN11       : 1;
+  __IO  uint8_t AN12       : 1;
+  __IO  uint8_t AN13       : 1;
+  __IO  uint8_t AN14       : 1;
+  __IO  uint8_t AN15       : 1;
+} stc_adc_scis1_field_t;
+
+typedef struct stc_adc_pfns_field
+{
+  __IO  uint8_t PFS0       : 1;
+  __IO  uint8_t PFS1       : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TEST0      : 1;
+  __IO  uint8_t TEST1      : 1;
+} stc_adc_pfns_field_t;
+
+typedef struct stc_adc_pccr_field
+{
+  __IO  uint8_t PSTR       : 1;
+  __IO  uint8_t PHEN       : 1;
+  __IO  uint8_t PEEN       : 1;
+  __IO  uint8_t ESCE       : 1;
+  __IO  uint8_t PFCLR      : 1;
+  __IO  uint8_t POVR       : 1;
+  __IO  uint8_t PFUL       : 1;
+  __IO  uint8_t PEMP       : 1;
+} stc_adc_pccr_field_t;
+
+typedef struct stc_adc_pcfd_field
+{
+  __IO uint32_t PC0        : 1;
+  __IO uint32_t PC1        : 1;
+  __IO uint32_t PC2        : 1;
+  __IO uint32_t PC3        : 1;
+  __IO uint32_t PC4        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t INVL       : 1;
+       uint32_t RESERVED3  : 7;
+  __IO uint32_t PD0        : 1;
+  __IO uint32_t PD1        : 1;
+  __IO uint32_t PD2        : 1;
+  __IO uint32_t PD3        : 1;
+  __IO uint32_t PD4        : 1;
+  __IO uint32_t PD5        : 1;
+  __IO uint32_t PD6        : 1;
+  __IO uint32_t PD7        : 1;
+  __IO uint32_t PD8        : 1;
+  __IO uint32_t PD9        : 1;
+  __IO uint32_t PD10       : 1;
+  __IO uint32_t PD11       : 1;
+} stc_adc_pcfd_field_t;
+
+typedef struct stc_adc_pcfdl_field
+{
+  __IO uint16_t PC0        : 1;
+  __IO uint16_t PC1        : 1;
+  __IO uint16_t PC2        : 1;
+  __IO uint16_t PC3        : 1;
+  __IO uint16_t PC4        : 1;
+       uint16_t RESERVED1  : 3;
+  __IO uint16_t RS0        : 1;
+  __IO uint16_t RS1        : 1;
+  __IO uint16_t RS2        : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t INVL       : 1;
+} stc_adc_pcfdl_field_t;
+
+typedef struct stc_adc_pcfdh_field
+{
+       uint16_t RESERVED1  : 4;
+  __IO uint16_t PD0        : 1;
+  __IO uint16_t PD1        : 1;
+  __IO uint16_t PD2        : 1;
+  __IO uint16_t PD3        : 1;
+  __IO uint16_t PD4        : 1;
+  __IO uint16_t PD5        : 1;
+  __IO uint16_t PD6        : 1;
+  __IO uint16_t PD7        : 1;
+  __IO uint16_t PD8        : 1;
+  __IO uint16_t PD9        : 1;
+  __IO uint16_t PD10       : 1;
+  __IO uint16_t PD11       : 1;
+} stc_adc_pcfdh_field_t;
+
+typedef struct stc_adc_pcis_field
+{
+  __IO  uint8_t P1A0       : 1;
+  __IO  uint8_t P1A1       : 1;
+  __IO  uint8_t P1A2       : 1;
+  __IO  uint8_t P2A0       : 1;
+  __IO  uint8_t P2A1       : 1;
+  __IO  uint8_t P2A2       : 1;
+  __IO  uint8_t P2A3       : 1;
+  __IO  uint8_t P2A4       : 1;
+} stc_adc_pcis_field_t;
+
+typedef struct stc_adc_cmpcr_field
+{
+  __IO  uint8_t CCH0       : 1;
+  __IO  uint8_t CCH1       : 1;
+  __IO  uint8_t CCH2       : 1;
+  __IO  uint8_t CCH3       : 1;
+  __IO  uint8_t CCH4       : 1;
+  __IO  uint8_t CMD0       : 1;
+  __IO  uint8_t CMD1       : 1;
+  __IO  uint8_t CMPEN      : 1;
+} stc_adc_cmpcr_field_t;
+
+typedef struct stc_adc_cmpd_field
+{
+       uint16_t RESERVED1  : 6;
+  __IO uint16_t CMAD2      : 1;
+  __IO uint16_t CMAD3      : 1;
+  __IO uint16_t CMAD4      : 1;
+  __IO uint16_t CMAD5      : 1;
+  __IO uint16_t CMAD6      : 1;
+  __IO uint16_t CMAD7      : 1;
+  __IO uint16_t CMAD8      : 1;
+  __IO uint16_t CMAD9      : 1;
+  __IO uint16_t CMAD10     : 1;
+  __IO uint16_t CMAD11     : 1;
+} stc_adc_cmpd_field_t;
+
+typedef struct stc_adc_adss23_field
+{
+  __IO uint16_t TS16       : 1;
+  __IO uint16_t TS17       : 1;
+  __IO uint16_t TS18       : 1;
+  __IO uint16_t TS19       : 1;
+  __IO uint16_t TS20       : 1;
+  __IO uint16_t TS21       : 1;
+  __IO uint16_t TS22       : 1;
+  __IO uint16_t TS23       : 1;
+  __IO uint16_t TS24       : 1;
+  __IO uint16_t TS25       : 1;
+  __IO uint16_t TS26       : 1;
+  __IO uint16_t TS27       : 1;
+  __IO uint16_t TS28       : 1;
+  __IO uint16_t TS29       : 1;
+  __IO uint16_t TS30       : 1;
+  __IO uint16_t TS31       : 1;
+} stc_adc_adss23_field_t;
+
+typedef struct stc_adc_adss2_field
+{
+  __IO  uint8_t TS16       : 1;
+  __IO  uint8_t TS17       : 1;
+  __IO  uint8_t TS18       : 1;
+  __IO  uint8_t TS19       : 1;
+  __IO  uint8_t TS20       : 1;
+  __IO  uint8_t TS21       : 1;
+  __IO  uint8_t TS22       : 1;
+  __IO  uint8_t TS23       : 1;
+} stc_adc_adss2_field_t;
+
+typedef struct stc_adc_adss3_field
+{
+  __IO  uint8_t TS24       : 1;
+  __IO  uint8_t TS25       : 1;
+  __IO  uint8_t TS26       : 1;
+  __IO  uint8_t TS27       : 1;
+  __IO  uint8_t TS28       : 1;
+  __IO  uint8_t TS29       : 1;
+  __IO  uint8_t TS30       : 1;
+  __IO  uint8_t TS31       : 1;
+} stc_adc_adss3_field_t;
+
+typedef struct stc_adc_adss01_field
+{
+  __IO uint16_t TS0        : 1;
+  __IO uint16_t TS1        : 1;
+  __IO uint16_t TS2        : 1;
+  __IO uint16_t TS3        : 1;
+  __IO uint16_t TS4        : 1;
+  __IO uint16_t TS5        : 1;
+  __IO uint16_t TS6        : 1;
+  __IO uint16_t TS7        : 1;
+  __IO uint16_t TS8        : 1;
+  __IO uint16_t TS9        : 1;
+  __IO uint16_t TS10       : 1;
+  __IO uint16_t TS11       : 1;
+  __IO uint16_t TS12       : 1;
+  __IO uint16_t TS13       : 1;
+  __IO uint16_t TS14       : 1;
+  __IO uint16_t TS15       : 1;
+} stc_adc_adss01_field_t;
+
+typedef struct stc_adc_adss0_field
+{
+  __IO  uint8_t TS0        : 1;
+  __IO  uint8_t TS1        : 1;
+  __IO  uint8_t TS2        : 1;
+  __IO  uint8_t TS3        : 1;
+  __IO  uint8_t TS4        : 1;
+  __IO  uint8_t TS5        : 1;
+  __IO  uint8_t TS6        : 1;
+  __IO  uint8_t TS7        : 1;
+} stc_adc_adss0_field_t;
+
+typedef struct stc_adc_adss1_field
+{
+  __IO  uint8_t TS8        : 1;
+  __IO  uint8_t TS9        : 1;
+  __IO  uint8_t TS10       : 1;
+  __IO  uint8_t TS11       : 1;
+  __IO  uint8_t TS12       : 1;
+  __IO  uint8_t TS13       : 1;
+  __IO  uint8_t TS14       : 1;
+  __IO  uint8_t TS15       : 1;
+} stc_adc_adss1_field_t;
+
+typedef struct stc_adc_adst01_field
+{
+  __IO uint16_t ST10       : 1;
+  __IO uint16_t ST11       : 1;
+  __IO uint16_t ST12       : 1;
+  __IO uint16_t ST13       : 1;
+  __IO uint16_t ST14       : 1;
+  __IO uint16_t STX10      : 1;
+  __IO uint16_t STX11      : 1;
+  __IO uint16_t STX12      : 1;
+  __IO uint16_t ST00       : 1;
+  __IO uint16_t ST01       : 1;
+  __IO uint16_t ST02       : 1;
+  __IO uint16_t ST03       : 1;
+  __IO uint16_t ST04       : 1;
+  __IO uint16_t STX00      : 1;
+  __IO uint16_t STX01      : 1;
+  __IO uint16_t STX02      : 1;
+} stc_adc_adst01_field_t;
+
+typedef struct stc_adc_adst1_field
+{
+  __IO  uint8_t ST10       : 1;
+  __IO  uint8_t ST11       : 1;
+  __IO  uint8_t ST12       : 1;
+  __IO  uint8_t ST13       : 1;
+  __IO  uint8_t ST14       : 1;
+  __IO  uint8_t STX10      : 1;
+  __IO  uint8_t STX11      : 1;
+  __IO  uint8_t STX12      : 1;
+} stc_adc_adst1_field_t;
+
+typedef struct stc_adc_adst0_field
+{
+  __IO  uint8_t ST00       : 1;
+  __IO  uint8_t ST01       : 1;
+  __IO  uint8_t ST02       : 1;
+  __IO  uint8_t ST03       : 1;
+  __IO  uint8_t ST04       : 1;
+  __IO  uint8_t STX00      : 1;
+  __IO  uint8_t STX01      : 1;
+  __IO  uint8_t STX02      : 1;
+} stc_adc_adst0_field_t;
+
+typedef struct stc_adc_adct_field
+{
+  __IO  uint8_t CT0        : 1;
+  __IO  uint8_t CT1        : 1;
+  __IO  uint8_t CT2        : 1;
+  __IO  uint8_t CT3        : 1;
+  __IO  uint8_t CT4        : 1;
+  __IO  uint8_t CT5        : 1;
+  __IO  uint8_t CT6        : 1;
+  __IO  uint8_t CT7        : 1;
+} stc_adc_adct_field_t;
+
+typedef struct stc_adc_prtsl_field
+{
+  __IO  uint8_t PRTSL0     : 1;
+  __IO  uint8_t PRTSL1     : 1;
+  __IO  uint8_t PRTSL2     : 1;
+  __IO  uint8_t PRTSL3     : 1;
+} stc_adc_prtsl_field_t;
+
+typedef struct stc_adc_sctsl_field
+{
+  __IO  uint8_t SCTSL0     : 1;
+  __IO  uint8_t SCTSL1     : 1;
+  __IO  uint8_t SCTSL2     : 1;
+  __IO  uint8_t SCTSL3     : 1;
+} stc_adc_sctsl_field_t;
+
+typedef struct stc_adc_adcen_field
+{
+  __IO  uint8_t ENBL       : 1;
+  __IO  uint8_t READY      : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t CYCLSL0    : 1;
+  __IO  uint8_t CYCLSL1    : 1;
+} stc_adc_adcen_field_t;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CRTRIM_MODULE register bit fields */
+typedef struct stc_crtrim_mcr_psr_field
+{
+  __IO  uint8_t CSR0       : 1;
+  __IO  uint8_t CSR1       : 1;
+} stc_crtrim_mcr_psr_field_t;
+
+typedef struct stc_crtrim_mcr_ftrm_field
+{
+  __IO uint16_t TRD0       : 1;
+  __IO uint16_t TRD1       : 1;
+  __IO uint16_t TRD2       : 1;
+  __IO uint16_t TRD3       : 1;
+  __IO uint16_t TRD4       : 1;
+  __IO uint16_t TRD5       : 1;
+  __IO uint16_t TRD6       : 1;
+  __IO uint16_t TRD7       : 1;
+} stc_crtrim_mcr_ftrm_field_t;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* EXTI_MODULE registEN bit fields */
+typedef struct stc_exti_enir_field
+{
+  __IO uint16_t EN0        : 1;
+  __IO uint16_t EN1        : 1;
+  __IO uint16_t EN2        : 1;
+  __IO uint16_t EN3        : 1;
+  __IO uint16_t EN4        : 1;
+  __IO uint16_t EN5        : 1;
+  __IO uint16_t EN6        : 1;
+  __IO uint16_t EN7        : 1;
+  __IO uint16_t EN8        : 1;
+  __IO uint16_t EN9        : 1;
+  __IO uint16_t EN10       : 1;
+  __IO uint16_t EN11       : 1;
+  __IO uint16_t EN12       : 1;
+  __IO uint16_t EN13       : 1;
+  __IO uint16_t EN14       : 1;
+  __IO uint16_t EN15       : 1;
+  __IO uint16_t EN16       : 1;
+  __IO uint16_t EN17       : 1;
+  __IO uint16_t EN18       : 1;
+  __IO uint16_t EN19       : 1;
+  __IO uint16_t EN20       : 1;
+  __IO uint16_t EN21       : 1;
+  __IO uint16_t EN22       : 1;
+  __IO uint16_t EN23       : 1;
+  __IO uint16_t EN24       : 1;
+  __IO uint16_t EN25       : 1;
+  __IO uint16_t EN26       : 1;
+  __IO uint16_t EN27       : 1;
+  __IO uint16_t EN28       : 1;
+  __IO uint16_t EN29       : 1;
+  __IO uint16_t EN30       : 1;
+  __IO uint16_t EN31       : 1;
+} stc_exti_enir_field_t;
+
+typedef struct stc_exti_eirr_field
+{
+  __IO uint16_t ER0        : 1;
+  __IO uint16_t ER1        : 1;
+  __IO uint16_t ER2        : 1;
+  __IO uint16_t ER3        : 1;
+  __IO uint16_t ER4        : 1;
+  __IO uint16_t ER5        : 1;
+  __IO uint16_t ER6        : 1;
+  __IO uint16_t ER7        : 1;
+  __IO uint16_t ER8        : 1;
+  __IO uint16_t ER9        : 1;
+  __IO uint16_t ER10       : 1;
+  __IO uint16_t ER11       : 1;
+  __IO uint16_t ER12       : 1;
+  __IO uint16_t ER13       : 1;
+  __IO uint16_t ER14       : 1;
+  __IO uint16_t ER15       : 1;
+  __IO uint16_t ER16       : 1;
+  __IO uint16_t ER17       : 1;
+  __IO uint16_t ER18       : 1;
+  __IO uint16_t ER19       : 1;
+  __IO uint16_t ER20       : 1;
+  __IO uint16_t ER21       : 1;
+  __IO uint16_t ER22       : 1;
+  __IO uint16_t ER23       : 1;
+  __IO uint16_t ER24       : 1;
+  __IO uint16_t ER25       : 1;
+  __IO uint16_t ER26       : 1;
+  __IO uint16_t ER27       : 1;
+  __IO uint16_t ER28       : 1;
+  __IO uint16_t ER29       : 1;
+  __IO uint16_t ER30       : 1;
+  __IO uint16_t ER31       : 1;
+} stc_exti_eirr_field_t;
+
+typedef struct stc_exti_eicl_field
+{
+  __IO uint16_t ECL0       : 1;
+  __IO uint16_t ECL1       : 1;
+  __IO uint16_t ECL2       : 1;
+  __IO uint16_t ECL3       : 1;
+  __IO uint16_t ECL4       : 1;
+  __IO uint16_t ECL5       : 1;
+  __IO uint16_t ECL6       : 1;
+  __IO uint16_t ECL7       : 1;
+  __IO uint16_t ECL8       : 1;
+  __IO uint16_t ECL9       : 1;
+  __IO uint16_t ECL10      : 1;
+  __IO uint16_t ECL11      : 1;
+  __IO uint16_t ECL12      : 1;
+  __IO uint16_t ECL13      : 1;
+  __IO uint16_t ECL14      : 1;
+  __IO uint16_t ECL15      : 1;
+  __IO uint16_t ECL16      : 1;
+  __IO uint16_t ECL17      : 1;
+  __IO uint16_t ECL18      : 1;
+  __IO uint16_t ECL19      : 1;
+  __IO uint16_t ECL20      : 1;
+  __IO uint16_t ECL21      : 1;
+  __IO uint16_t ECL22      : 1;
+  __IO uint16_t ECL23      : 1;
+  __IO uint16_t ECL24      : 1;
+  __IO uint16_t ECL25      : 1;
+  __IO uint16_t ECL26      : 1;
+  __IO uint16_t ECL27      : 1;
+  __IO uint16_t ECL28      : 1;
+  __IO uint16_t ECL29      : 1;
+  __IO uint16_t ECL30      : 1;
+  __IO uint16_t ECL31      : 1;
+} stc_exti_eicl_field_t;
+
+typedef struct stc_exti_elvr_field
+{
+  __IO uint32_t LA0        : 1;
+  __IO uint32_t LB0        : 1;
+  __IO uint32_t LA1        : 1;
+  __IO uint32_t LB1        : 1;
+  __IO uint32_t LA2        : 1;
+  __IO uint32_t LB2        : 1;
+  __IO uint32_t LA3        : 1;
+  __IO uint32_t LB3        : 1;
+  __IO uint32_t LA4        : 1;
+  __IO uint32_t LB4        : 1;
+  __IO uint32_t LA5        : 1;
+  __IO uint32_t LB5        : 1;
+  __IO uint32_t LA6        : 1;
+  __IO uint32_t LB6        : 1;
+  __IO uint32_t LA7        : 1;
+  __IO uint32_t LB7        : 1;
+  __IO uint32_t LA8        : 1;
+  __IO uint32_t LB8        : 1;
+  __IO uint32_t LA9        : 1;
+  __IO uint32_t LB9        : 1;
+  __IO uint32_t LA10       : 1;
+  __IO uint32_t LB10       : 1;
+  __IO uint32_t LA11       : 1;
+  __IO uint32_t LB11       : 1;
+  __IO uint32_t LA12       : 1;
+  __IO uint32_t LB12       : 1;
+  __IO uint32_t LA13       : 1;
+  __IO uint32_t LB13       : 1;
+  __IO uint32_t LA14       : 1;
+  __IO uint32_t LB14       : 1;
+  __IO uint32_t LA15       : 1;
+  __IO uint32_t LB15       : 1;
+} stc_exti_elvr_field_t;
+
+typedef struct stc_exti_elvr1_field
+{
+  __IO uint32_t LA16       : 1;
+  __IO uint32_t LB16       : 1;
+  __IO uint32_t LA17       : 1;
+  __IO uint32_t LB17       : 1;
+  __IO uint32_t LA18       : 1;
+  __IO uint32_t LB18       : 1;
+  __IO uint32_t LA19       : 1;
+  __IO uint32_t LB19       : 1;
+  __IO uint32_t LA20       : 1;
+  __IO uint32_t LB20       : 1;
+  __IO uint32_t LA21       : 1;
+  __IO uint32_t LB21       : 1;
+  __IO uint32_t LA22       : 1;
+  __IO uint32_t LB22       : 1;
+  __IO uint32_t LA23       : 1;
+  __IO uint32_t LB23       : 1;
+  __IO uint32_t LA24       : 1;
+  __IO uint32_t LB24       : 1;
+  __IO uint32_t LA25       : 1;
+  __IO uint32_t LB25       : 1;
+  __IO uint32_t LA26       : 1;
+  __IO uint32_t LB26       : 1;
+  __IO uint32_t LA27       : 1;
+  __IO uint32_t LB27       : 1;
+  __IO uint32_t LA28       : 1;
+  __IO uint32_t LB28       : 1;
+  __IO uint32_t LA29       : 1;
+  __IO uint32_t LB29       : 1;
+  __IO uint32_t LA30       : 1;
+  __IO uint32_t LB30       : 1;
+  __IO uint32_t LA31       : 1;
+  __IO uint32_t LB31       : 1;
+} stc_exti_elvr1_field_t;
+
+typedef struct stc_exti_nmirr_field
+{
+  __IO  uint8_t NR0        : 1;
+} stc_exti_nmirr_field_t;
+
+typedef struct stc_exti_nmicl_field
+{
+  __IO  uint8_t NCL0       : 1;
+} stc_exti_nmicl_field_t;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* INTREQ_MODULE register bit fields */
+typedef struct stc_intreq_drqsel_field
+{
+  __IO uint32_t DRQSEL0    : 1;
+  __IO uint32_t DRQSEL1    : 1;
+  __IO uint32_t DRQSEL2    : 1;
+  __IO uint32_t DRQSEL3    : 1;
+  __IO uint32_t DRQSEL4    : 1;
+  __IO uint32_t DRQSEL5    : 1;
+  __IO uint32_t DRQSEL6    : 1;
+  __IO uint32_t DRQSEL7    : 1;
+  __IO uint32_t DRQSEL8    : 1;
+  __IO uint32_t DRQSEL9    : 1;
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+  __IO uint32_t DRQSEL15   : 1;
+  __IO uint32_t DRQSEL16   : 1;
+  __IO uint32_t DRQSEL17   : 1;
+  __IO uint32_t DRQSEL18   : 1;
+  __IO uint32_t DRQSEL19   : 1;
+  __IO uint32_t DRQSEL20   : 1;
+  __IO uint32_t DRQSEL21   : 1;
+  __IO uint32_t DRQSEL22   : 1;
+  __IO uint32_t DRQSEL23   : 1;
+  __IO uint32_t DRQSEL24   : 1;
+  __IO uint32_t DRQSEL25   : 1;
+  __IO uint32_t DRQSEL26   : 1;
+  __IO uint32_t DRQSEL27   : 1;
+  __IO uint32_t DRQSEL28   : 1;
+  __IO uint32_t DRQSEL29   : 1;
+  __IO uint32_t DRQSEL30   : 1;
+  __IO uint32_t DRQSEL31   : 1;
+} stc_intreq_drqsel_field_t;
+
+typedef struct stc_intreq_oddpks_field
+{
+  __IO  uint8_t ODDPKS0    : 1;
+  __IO  uint8_t ODDPKS1    : 1;
+  __IO  uint8_t ODDPKS2    : 1;
+  __IO  uint8_t ODDPKS3    : 1;
+  __IO  uint8_t ODDPKS4    : 1;
+} stc_intreq_oddpks_field_t;
+
+typedef struct stc_intreq_exc02mon_field
+{
+  __IO uint32_t NMI        : 1;
+  __IO uint32_t HWINT      : 1;
+} stc_intreq_exc02mon_field_t;
+
+typedef struct stc_intreq_irq00mon_field
+{
+  __IO uint32_t FCSINT     : 1;
+} stc_intreq_irq00mon_field_t;
+
+typedef struct stc_intreq_irq01mon_field
+{
+  __IO uint32_t SWWDTINT   : 1;
+} stc_intreq_irq01mon_field_t;
+
+typedef struct stc_intreq_irq02mon_field
+{
+  __IO uint32_t LVDINT     : 1;
+} stc_intreq_irq02mon_field_t;
+
+typedef struct stc_intreq_irq03mon_field
+{
+  __IO uint32_t WAVE0INT0  : 1;
+  __IO uint32_t WAVE0INT1  : 1;
+  __IO uint32_t WAVE0INT2  : 1;
+  __IO uint32_t WAVE0INT3  : 1;
+  __IO uint32_t WAVE1INT0  : 1;
+  __IO uint32_t WAVE1INT1  : 1;
+  __IO uint32_t WAVE1INT2  : 1;
+  __IO uint32_t WAVE1INT3  : 1;
+  __IO uint32_t WAVE2INT0  : 1;
+  __IO uint32_t WAVE2INT1  : 1;
+  __IO uint32_t WAVE2INT2  : 1;
+  __IO uint32_t WAVE2INT3  : 1;
+} stc_intreq_irq03mon_field_t;
+
+typedef struct stc_intreq_irq04mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+} stc_intreq_irq04mon_field_t;
+
+typedef struct stc_intreq_irq05mon_field
+{
+  __IO uint32_t EXTINT0    : 1;
+  __IO uint32_t EXTINT1    : 1;
+  __IO uint32_t EXTINT2    : 1;
+  __IO uint32_t EXTINT3    : 1;
+  __IO uint32_t EXTINT4    : 1;
+  __IO uint32_t EXTINT5    : 1;
+  __IO uint32_t EXTINT6    : 1;
+  __IO uint32_t EXTINT7    : 1;
+  __IO uint32_t EXTINT8    : 1;
+  __IO uint32_t EXTINT9    : 1;
+  __IO uint32_t EXTINT10   : 1;
+  __IO uint32_t EXTINT11   : 1;
+  __IO uint32_t EXTINT12   : 1;
+  __IO uint32_t EXTINT13   : 1;
+  __IO uint32_t EXTINT14   : 1;
+  __IO uint32_t EXTINT15   : 1;
+  __IO uint32_t EXTINT16   : 1;
+  __IO uint32_t EXTINT17   : 1;
+  __IO uint32_t EXTINT18   : 1;
+  __IO uint32_t EXTINT19   : 1;
+  __IO uint32_t EXTINT20   : 1;
+  __IO uint32_t EXTINT21   : 1;
+  __IO uint32_t EXTINT22   : 1;
+  __IO uint32_t EXTINT23   : 1;
+} stc_intreq_irq05mon_field_t;
+
+typedef struct stc_intreq_irq06mon_field
+{
+  __IO uint32_t TIMINT1    : 1;
+  __IO uint32_t TIMINT2    : 1;
+  __IO uint32_t QUD0INT0   : 1;
+  __IO uint32_t QUD0INT1   : 1;
+  __IO uint32_t QUD0INT2   : 1;
+  __IO uint32_t QUD0INT3   : 1;
+  __IO uint32_t QUD0INT4   : 1;
+  __IO uint32_t QUD0INT5   : 1;
+  __IO uint32_t QUD1INT0   : 1;
+  __IO uint32_t QUD1INT1   : 1;
+  __IO uint32_t QUD1INT2   : 1;
+  __IO uint32_t QUD1INT3   : 1;
+  __IO uint32_t QUD1INT4   : 1;
+  __IO uint32_t QUD1INT5   : 1;
+  __IO uint32_t QUD2INT0   : 1;
+  __IO uint32_t QUD2INT1   : 1;
+  __IO uint32_t QUD2INT2   : 1;
+  __IO uint32_t QUD2INT3   : 1;
+  __IO uint32_t QUD2INT4   : 1;
+  __IO uint32_t QUD2INT5   : 1;
+} stc_intreq_irq06mon_field_t;
+
+typedef struct stc_intreq_irq07mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq07mon_field_t;
+
+typedef struct stc_intreq_irq08mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq08mon_field_t;
+
+typedef struct stc_intreq_irq09mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq09mon_field_t;
+
+typedef struct stc_intreq_irq10mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq10mon_field_t;
+
+typedef struct stc_intreq_irq11mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq11mon_field_t;
+
+typedef struct stc_intreq_irq12mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq12mon_field_t;
+
+typedef struct stc_intreq_irq13mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq13mon_field_t;
+
+typedef struct stc_intreq_irq14mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq14mon_field_t;
+
+typedef struct stc_intreq_irq15mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq15mon_field_t;
+
+typedef struct stc_intreq_irq16mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq16mon_field_t;
+
+typedef struct stc_intreq_irq17mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq17mon_field_t;
+
+typedef struct stc_intreq_irq18mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq18mon_field_t;
+
+typedef struct stc_intreq_irq19mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq19mon_field_t;
+
+typedef struct stc_intreq_irq20mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq20mon_field_t;
+
+typedef struct stc_intreq_irq21mon_field
+{
+  __IO uint32_t FMSINT     : 1;
+} stc_intreq_irq21mon_field_t;
+
+typedef struct stc_intreq_irq22mon_field
+{
+  __IO uint32_t MFSINT0    : 1;
+  __IO uint32_t MFSINT1    : 1;
+} stc_intreq_irq22mon_field_t;
+
+typedef struct stc_intreq_irq23mon_field
+{
+  __IO uint32_t PPGINT0    : 1;
+  __IO uint32_t PPGINT1    : 1;
+  __IO uint32_t PPGINT2    : 1;
+  __IO uint32_t PPGINT3    : 1;
+  __IO uint32_t PPGINT4    : 1;
+  __IO uint32_t PPGINT5    : 1;
+  __IO uint32_t PPGINT6    : 1;
+  __IO uint32_t PPGINT7    : 1;
+  __IO uint32_t PPGINT8    : 1;
+} stc_intreq_irq23mon_field_t;
+
+typedef struct stc_intreq_irq24mon_field
+{
+  __IO uint32_t MOSCINT    : 1;
+  __IO uint32_t SOSCINT    : 1;
+  __IO uint32_t MPLLINT    : 1;
+  __IO uint32_t UPLLINT    : 1;
+  __IO uint32_t WCINT      : 1;
+} stc_intreq_irq24mon_field_t;
+
+typedef struct stc_intreq_irq25mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq25mon_field_t;
+
+typedef struct stc_intreq_irq26mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq26mon_field_t;
+
+typedef struct stc_intreq_irq27mon_field
+{
+  __IO uint32_t ADCINT0    : 1;
+  __IO uint32_t ADCINT1    : 1;
+  __IO uint32_t ADCINT2    : 1;
+  __IO uint32_t ADCINT3    : 1;
+} stc_intreq_irq27mon_field_t;
+
+typedef struct stc_intreq_irq28mon_field
+{
+  __IO uint32_t FRT0INT0   : 1;
+  __IO uint32_t FRT0INT1   : 1;
+  __IO uint32_t FRT0INT2   : 1;
+  __IO uint32_t FRT0INT3   : 1;
+  __IO uint32_t FRT0INT4   : 1;
+  __IO uint32_t FRT0INT5   : 1;
+  __IO uint32_t FRT1INT0   : 1;
+  __IO uint32_t FRT1INT1   : 1;
+  __IO uint32_t FRT1INT2   : 1;
+  __IO uint32_t FRT1INT3   : 1;
+  __IO uint32_t FRT1INT4   : 1;
+  __IO uint32_t FRT1INT5   : 1;
+  __IO uint32_t FRT2INT0   : 1;
+  __IO uint32_t FRT2INT1   : 1;
+  __IO uint32_t FRT2INT2   : 1;
+  __IO uint32_t FRT2INT3   : 1;
+  __IO uint32_t FRT2INT4   : 1;
+  __IO uint32_t FRT2INT5   : 1;
+} stc_intreq_irq28mon_field_t;
+
+typedef struct stc_intreq_irq29mon_field
+{
+  __IO uint32_t ICU0INT0   : 1;
+  __IO uint32_t ICU0INT1   : 1;
+  __IO uint32_t ICU0INT2   : 1;
+  __IO uint32_t ICU0INT3   : 1;
+  __IO uint32_t ICU1INT0   : 1;
+  __IO uint32_t ICU1INT1   : 1;
+  __IO uint32_t ICU1INT2   : 1;
+  __IO uint32_t ICU1INT3   : 1;
+  __IO uint32_t ICU2INT0   : 1;
+  __IO uint32_t ICU2INT1   : 1;
+  __IO uint32_t ICU2INT2   : 1;
+  __IO uint32_t ICU2INT3   : 1;
+} stc_intreq_irq29mon_field_t;
+
+typedef struct stc_intreq_irq30mon_field
+{
+  __IO uint32_t OCU0INT0   : 1;
+  __IO uint32_t OCU0INT1   : 1;
+  __IO uint32_t OCU0INT2   : 1;
+  __IO uint32_t OCU0INT3   : 1;
+  __IO uint32_t OCU0INT4   : 1;
+  __IO uint32_t OCU0INT5   : 1;
+  __IO uint32_t OCU1INT0   : 1;
+  __IO uint32_t OCU1INT1   : 1;
+  __IO uint32_t OCU1INT2   : 1;
+  __IO uint32_t OCU1INT3   : 1;
+  __IO uint32_t OCU1INT4   : 1;
+  __IO uint32_t OCU1INT5   : 1;
+  __IO uint32_t OCU2INT0   : 1;
+  __IO uint32_t OCU2INT1   : 1;
+  __IO uint32_t OCU2INT2   : 1;
+  __IO uint32_t OCU2INT3   : 1;
+  __IO uint32_t OCU2INT4   : 1;
+  __IO uint32_t OCU2INT5   : 1;
+} stc_intreq_irq30mon_field_t;
+
+typedef struct stc_intreq_irq31mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq31mon_field_t;
+
+typedef struct stc_intreq_irq32mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC0SBD    : 1;
+  __IO uint32_t MAC0PMI    : 1;
+  __IO uint32_t MAC0LPI    : 1;
+} stc_intreq_irq32mon_field_t;
+
+typedef struct stc_intreq_irq33mon_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAC1SBD    : 1;
+  __IO uint32_t MAC1PMI    : 1;
+} stc_intreq_irq33mon_field_t;
+
+typedef struct stc_intreq_irq34mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+} stc_intreq_irq34mon_field_t;
+
+typedef struct stc_intreq_irq35mon_field
+{
+  __IO uint32_t USB0INT0   : 1;
+  __IO uint32_t USB0INT1   : 1;
+  __IO uint32_t USB0INT2   : 1;
+  __IO uint32_t USB0INT3   : 1;
+  __IO uint32_t USB0INT4   : 1;
+  __IO uint32_t USB0INT5   : 1;
+} stc_intreq_irq35mon_field_t;
+
+typedef struct stc_intreq_irq36mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+} stc_intreq_irq36mon_field_t;
+
+typedef struct stc_intreq_irq37mon_field
+{
+  __IO uint32_t USB1INT0   : 1;
+  __IO uint32_t USB1INT1   : 1;
+  __IO uint32_t USB1INT2   : 1;
+  __IO uint32_t USB1INT3   : 1;
+  __IO uint32_t USB1INT4   : 1;
+  __IO uint32_t USB1INT5   : 1;
+} stc_intreq_irq37mon_field_t;
+
+typedef struct stc_intreq_irq38mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq38mon_field_t;
+
+typedef struct stc_intreq_irq39mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq39mon_field_t;
+
+typedef struct stc_intreq_irq40mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq40mon_field_t;
+
+typedef struct stc_intreq_irq41mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq41mon_field_t;
+
+typedef struct stc_intreq_irq42mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq42mon_field_t;
+
+typedef struct stc_intreq_irq43mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq43mon_field_t;
+
+typedef struct stc_intreq_irq44mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq44mon_field_t;
+
+typedef struct stc_intreq_irq45mon_field
+{
+  __IO uint32_t DMAINT     : 1;
+} stc_intreq_irq45mon_field_t;
+
+typedef struct stc_intreq_irq46mon_field
+{
+  __IO uint32_t BTINT0     : 1;
+  __IO uint32_t BTINT1     : 1;
+  __IO uint32_t BTINT2     : 1;
+  __IO uint32_t BTINT3     : 1;
+  __IO uint32_t BTINT4     : 1;
+  __IO uint32_t BTINT5     : 1;
+  __IO uint32_t BTINT6     : 1;
+  __IO uint32_t BTINT7     : 1;
+  __IO uint32_t BTINT8     : 1;
+  __IO uint32_t BTINT9     : 1;
+  __IO uint32_t BTINT10    : 1;
+  __IO uint32_t BTINT11    : 1;
+  __IO uint32_t BTINT12    : 1;
+  __IO uint32_t BTINT13    : 1;
+  __IO uint32_t BTINT14    : 1;
+  __IO uint32_t BTINT15    : 1;
+} stc_intreq_irq46mon_field_t;
+
+typedef struct stc_intreq_drqsel1_field
+{
+  __IO uint32_t DRQSEL10   : 1;
+  __IO uint32_t DRQSEL11   : 1;
+  __IO uint32_t DRQSEL12   : 1;
+  __IO uint32_t DRQSEL13   : 1;
+  __IO uint32_t DRQSEL14   : 1;
+} stc_intreq_drqsel1_field_t;
+
+typedef struct stc_intreq_dqesel_field
+{
+  __IO uint32_t ESEL100    : 1;
+  __IO uint32_t ESEL101    : 1;
+  __IO uint32_t ESEL102    : 1;
+  __IO uint32_t ESEL103    : 1;
+  __IO uint32_t ESEL110    : 1;
+  __IO uint32_t ESEL111    : 1;
+  __IO uint32_t ESEL112    : 1;
+  __IO uint32_t ESEL113    : 1;
+  __IO uint32_t ESEL240    : 1;
+  __IO uint32_t ESEL241    : 1;
+  __IO uint32_t ESEL242    : 1;
+  __IO uint32_t ESEL243    : 1;
+  __IO uint32_t ESEL250    : 1;
+  __IO uint32_t ESEL251    : 1;
+  __IO uint32_t ESEL252    : 1;
+  __IO uint32_t ESEL253    : 1;
+  __IO uint32_t ESEL260    : 1;
+  __IO uint32_t ESEL261    : 1;
+  __IO uint32_t ESEL262    : 1;
+  __IO uint32_t ESEL263    : 1;
+  __IO uint32_t ESEL270    : 1;
+  __IO uint32_t ESEL271    : 1;
+  __IO uint32_t ESEL272    : 1;
+  __IO uint32_t ESEL273    : 1;
+  __IO uint32_t ESEL300    : 1;
+  __IO uint32_t ESEL301    : 1;
+  __IO uint32_t ESEL302    : 1;
+  __IO uint32_t ESEL303    : 1;
+  __IO uint32_t ESEL310    : 1;
+  __IO uint32_t ESEL311    : 1;
+  __IO uint32_t ESEL312    : 1;
+  __IO uint32_t ESEL313    : 1;
+} stc_intreq_dqesel_field_t;
+
+typedef struct stc_intreq_oddpks1_field
+{
+  __IO  uint8_t ODDPKS10   : 1;
+  __IO  uint8_t ODDPKS11   : 1;
+  __IO  uint8_t ODDPKS12   : 1;
+  __IO  uint8_t ODDPKS13   : 1;
+  __IO  uint8_t ODDPKS14   : 1;
+} stc_intreq_oddpks1_field_t;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* GPIO_MODULE register bit fields */
+typedef struct stc_gpio_pfr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr0_field_t;
+
+typedef struct stc_gpio_pfr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr1_field_t;
+
+typedef struct stc_gpio_pfr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pfr2_field_t;
+
+typedef struct stc_gpio_pfr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr3_field_t;
+
+typedef struct stc_gpio_pfr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pfr4_field_t;
+
+typedef struct stc_gpio_pfr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pfr5_field_t;
+
+typedef struct stc_gpio_pfr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pfr6_field_t;
+
+typedef struct stc_gpio_pfr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfr7_field_t;
+
+typedef struct stc_gpio_pfr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfr8_field_t;
+
+typedef struct stc_gpio_pfr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pfr9_field_t;
+
+typedef struct stc_gpio_pfra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pfra_field_t;
+
+typedef struct stc_gpio_pfrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pfrb_field_t;
+
+typedef struct stc_gpio_pfrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pfrc_field_t;
+
+typedef struct stc_gpio_pfrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfrd_field_t;
+
+typedef struct stc_gpio_pfre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pfre_field_t;
+
+typedef struct stc_gpio_pfrf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pfrf_field_t;
+
+typedef struct stc_gpio_pcr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr0_field_t;
+
+typedef struct stc_gpio_pcr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr1_field_t;
+
+typedef struct stc_gpio_pcr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pcr2_field_t;
+
+typedef struct stc_gpio_pcr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr3_field_t;
+
+typedef struct stc_gpio_pcr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pcr4_field_t;
+
+typedef struct stc_gpio_pcr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pcr5_field_t;
+
+typedef struct stc_gpio_pcr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pcr6_field_t;
+
+typedef struct stc_gpio_pcr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcr7_field_t;
+
+typedef struct stc_gpio_pcr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pcr9_field_t;
+
+typedef struct stc_gpio_pcra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pcra_field_t;
+
+typedef struct stc_gpio_pcrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pcrb_field_t;
+
+typedef struct stc_gpio_pcrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pcrc_field_t;
+
+typedef struct stc_gpio_pcrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcrd_field_t;
+
+typedef struct stc_gpio_pcre_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pcre_field_t;
+
+typedef struct stc_gpio_ddr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr0_field_t;
+
+typedef struct stc_gpio_ddr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr1_field_t;
+
+typedef struct stc_gpio_ddr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_ddr2_field_t;
+
+typedef struct stc_gpio_ddr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr3_field_t;
+
+typedef struct stc_gpio_ddr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_ddr4_field_t;
+
+typedef struct stc_gpio_ddr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_ddr5_field_t;
+
+typedef struct stc_gpio_ddr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_ddr6_field_t;
+
+typedef struct stc_gpio_ddr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddr7_field_t;
+
+typedef struct stc_gpio_ddr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddr8_field_t;
+
+typedef struct stc_gpio_ddr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_ddr9_field_t;
+
+typedef struct stc_gpio_ddra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_ddra_field_t;
+
+typedef struct stc_gpio_ddrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_ddrb_field_t;
+
+typedef struct stc_gpio_ddrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_ddrc_field_t;
+
+typedef struct stc_gpio_ddrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddrd_field_t;
+
+typedef struct stc_gpio_ddre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_ddre_field_t;
+
+typedef struct stc_gpio_ddrf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_ddrf_field_t;
+
+typedef struct stc_gpio_pdir0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir0_field_t;
+
+typedef struct stc_gpio_pdir1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir1_field_t;
+
+typedef struct stc_gpio_pdir2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdir2_field_t;
+
+typedef struct stc_gpio_pdir3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir3_field_t;
+
+typedef struct stc_gpio_pdir4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdir4_field_t;
+
+typedef struct stc_gpio_pdir5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pdir5_field_t;
+
+typedef struct stc_gpio_pdir6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdir6_field_t;
+
+typedef struct stc_gpio_pdir7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdir7_field_t;
+
+typedef struct stc_gpio_pdir8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdir8_field_t;
+
+typedef struct stc_gpio_pdir9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdir9_field_t;
+
+typedef struct stc_gpio_pdira_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdira_field_t;
+
+typedef struct stc_gpio_pdirb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pdirb_field_t;
+
+typedef struct stc_gpio_pdirc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdirc_field_t;
+
+typedef struct stc_gpio_pdird_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdird_field_t;
+
+typedef struct stc_gpio_pdire_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdire_field_t;
+
+typedef struct stc_gpio_pdirf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdirf_field_t;
+
+typedef struct stc_gpio_pdor0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor0_field_t;
+
+typedef struct stc_gpio_pdor1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor1_field_t;
+
+typedef struct stc_gpio_pdor2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pdor2_field_t;
+
+typedef struct stc_gpio_pdor3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor3_field_t;
+
+typedef struct stc_gpio_pdor4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pdor4_field_t;
+
+typedef struct stc_gpio_pdor5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pdor5_field_t;
+
+typedef struct stc_gpio_pdor6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pdor6_field_t;
+
+typedef struct stc_gpio_pdor7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdor7_field_t;
+
+typedef struct stc_gpio_pdor8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdor8_field_t;
+
+typedef struct stc_gpio_pdor9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdor9_field_t;
+
+typedef struct stc_gpio_pdora_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pdora_field_t;
+
+typedef struct stc_gpio_pdorb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pdorb_field_t;
+
+typedef struct stc_gpio_pdorc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pdorc_field_t;
+
+typedef struct stc_gpio_pdord_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdord_field_t;
+
+typedef struct stc_gpio_pdore_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pdore_field_t;
+
+typedef struct stc_gpio_pdorf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pdorf_field_t;
+
+typedef struct stc_gpio_ade_field
+{
+  __IO uint32_t AN0        : 1;
+  __IO uint32_t AN1        : 1;
+  __IO uint32_t AN2        : 1;
+  __IO uint32_t AN3        : 1;
+  __IO uint32_t AN4        : 1;
+  __IO uint32_t AN5        : 1;
+  __IO uint32_t AN6        : 1;
+  __IO uint32_t AN7        : 1;
+  __IO uint32_t AN8        : 1;
+  __IO uint32_t AN9        : 1;
+  __IO uint32_t AN10       : 1;
+  __IO uint32_t AN11       : 1;
+  __IO uint32_t AN12       : 1;
+  __IO uint32_t AN13       : 1;
+  __IO uint32_t AN14       : 1;
+  __IO uint32_t AN15       : 1;
+  __IO uint32_t AN16       : 1;
+  __IO uint32_t AN17       : 1;
+  __IO uint32_t AN18       : 1;
+  __IO uint32_t AN19       : 1;
+  __IO uint32_t AN20       : 1;
+  __IO uint32_t AN21       : 1;
+  __IO uint32_t AN22       : 1;
+  __IO uint32_t AN23       : 1;
+  __IO uint32_t AN24       : 1;
+  __IO uint32_t AN25       : 1;
+  __IO uint32_t AN26       : 1;
+  __IO uint32_t AN27       : 1;
+  __IO uint32_t AN28       : 1;
+  __IO uint32_t AN29       : 1;
+  __IO uint32_t AN30       : 1;
+  __IO uint32_t AN31       : 1;
+} stc_gpio_ade_field_t;
+
+typedef struct stc_gpio_spsr_field
+{
+  __IO uint32_t SUBXC      : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MAINXC     : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USB0C      : 1;
+  __IO uint32_t USB1C      : 1;
+} stc_gpio_spsr_field_t;
+
+typedef struct stc_gpio_epfr00_field
+{
+  __IO uint32_t NMIS       : 1;
+  __IO uint32_t CROUTE0    : 1;
+  __IO uint32_t CROUTE1    : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t SUBOUTE0   : 1;
+  __IO uint32_t SUBOUTE1   : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t USBP0E     : 1;
+       uint32_t RESERVED3  : 3;
+  __IO uint32_t USBP1E     : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t JTAGEN0B   : 1;
+  __IO uint32_t JTAGEN1S   : 1;
+       uint32_t RESERVED5  : 6;
+  __IO uint32_t TRC0E      : 1;
+  __IO uint32_t TRC1E      : 1;
+} stc_gpio_epfr00_field_t;
+
+typedef struct stc_gpio_epfr01_field
+{
+  __IO uint32_t RTO00E0    : 1;
+  __IO uint32_t RTO00E1    : 1;
+  __IO uint32_t RTO01E0    : 1;
+  __IO uint32_t RTO01E1    : 1;
+  __IO uint32_t RTO02E0    : 1;
+  __IO uint32_t RTO02E1    : 1;
+  __IO uint32_t RTO03E0    : 1;
+  __IO uint32_t RTO03E1    : 1;
+  __IO uint32_t RTO04E0    : 1;
+  __IO uint32_t RTO04E1    : 1;
+  __IO uint32_t RTO05E0    : 1;
+  __IO uint32_t RTO05E1    : 1;
+  __IO uint32_t DTTI0C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI0S0    : 1;
+  __IO uint32_t DTTI0S1    : 1;
+  __IO uint32_t FRCK0S0    : 1;
+  __IO uint32_t FRCK0S1    : 1;
+  __IO uint32_t IC00S0     : 1;
+  __IO uint32_t IC00S1     : 1;
+  __IO uint32_t IC00S2     : 1;
+  __IO uint32_t IC01S0     : 1;
+  __IO uint32_t IC01S1     : 1;
+  __IO uint32_t IC01S2     : 1;
+  __IO uint32_t IC02S0     : 1;
+  __IO uint32_t IC02S1     : 1;
+  __IO uint32_t IC02S2     : 1;
+  __IO uint32_t IC03S0     : 1;
+  __IO uint32_t IC03S1     : 1;
+  __IO uint32_t IC03S2     : 1;
+} stc_gpio_epfr01_field_t;
+
+typedef struct stc_gpio_epfr02_field
+{
+  __IO uint32_t RTO10E0    : 1;
+  __IO uint32_t RTO10E1    : 1;
+  __IO uint32_t RTO11E0    : 1;
+  __IO uint32_t RTO11E1    : 1;
+  __IO uint32_t RTO12E0    : 1;
+  __IO uint32_t RTO12E1    : 1;
+  __IO uint32_t RTO13E0    : 1;
+  __IO uint32_t RTO13E1    : 1;
+  __IO uint32_t RTO14E0    : 1;
+  __IO uint32_t RTO14E1    : 1;
+  __IO uint32_t RTO15E0    : 1;
+  __IO uint32_t RTO15E1    : 1;
+  __IO uint32_t DTTI1C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI1S0    : 1;
+  __IO uint32_t DTTI1S1    : 1;
+  __IO uint32_t FRCK1S0    : 1;
+  __IO uint32_t FRCK1S1    : 1;
+  __IO uint32_t IC10S0     : 1;
+  __IO uint32_t IC10S1     : 1;
+  __IO uint32_t IC10S2     : 1;
+  __IO uint32_t IC11S0     : 1;
+  __IO uint32_t IC11S1     : 1;
+  __IO uint32_t IC11S2     : 1;
+  __IO uint32_t IC12S0     : 1;
+  __IO uint32_t IC12S1     : 1;
+  __IO uint32_t IC12S2     : 1;
+  __IO uint32_t IC13S0     : 1;
+  __IO uint32_t IC13S1     : 1;
+  __IO uint32_t IC13S2     : 1;
+} stc_gpio_epfr02_field_t;
+
+typedef struct stc_gpio_epfr03_field
+{
+  __IO uint32_t RTO20E0    : 1;
+  __IO uint32_t RTO20E1    : 1;
+  __IO uint32_t RTO21E0    : 1;
+  __IO uint32_t RTO21E1    : 1;
+  __IO uint32_t RTO22E0    : 1;
+  __IO uint32_t RTO22E1    : 1;
+  __IO uint32_t RTO23E0    : 1;
+  __IO uint32_t RTO23E1    : 1;
+  __IO uint32_t RTO24E0    : 1;
+  __IO uint32_t RTO24E1    : 1;
+  __IO uint32_t RTO25E0    : 1;
+  __IO uint32_t RTO25E1    : 1;
+  __IO uint32_t DTTI2C     : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t DTTI2S0    : 1;
+  __IO uint32_t DTTI2S1    : 1;
+  __IO uint32_t FRCK2S0    : 1;
+  __IO uint32_t FRCK2S1    : 1;
+  __IO uint32_t IC20S0     : 1;
+  __IO uint32_t IC20S1     : 1;
+  __IO uint32_t IC20S2     : 1;
+  __IO uint32_t IC21S0     : 1;
+  __IO uint32_t IC21S1     : 1;
+  __IO uint32_t IC21S2     : 1;
+  __IO uint32_t IC22S0     : 1;
+  __IO uint32_t IC22S1     : 1;
+  __IO uint32_t IC22S2     : 1;
+  __IO uint32_t IC23S0     : 1;
+  __IO uint32_t IC23S1     : 1;
+  __IO uint32_t IC23S2     : 1;
+} stc_gpio_epfr03_field_t;
+
+typedef struct stc_gpio_epfr04_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA0E0    : 1;
+  __IO uint32_t TIOA0E1    : 1;
+  __IO uint32_t TIOB0S0    : 1;
+  __IO uint32_t TIOB0S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA1S0    : 1;
+  __IO uint32_t TIOA1S1    : 1;
+  __IO uint32_t TIOA1E0    : 1;
+  __IO uint32_t TIOA1E1    : 1;
+  __IO uint32_t TIOB1S0    : 1;
+  __IO uint32_t TIOB1S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA2E0    : 1;
+  __IO uint32_t TIOA2E1    : 1;
+  __IO uint32_t TIOB2S0    : 1;
+  __IO uint32_t TIOB2S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA3S0    : 1;
+  __IO uint32_t TIOA3S1    : 1;
+  __IO uint32_t TIOA3E0    : 1;
+  __IO uint32_t TIOA3E1    : 1;
+  __IO uint32_t TIOB3S0    : 1;
+  __IO uint32_t TIOB3S1    : 1;
+} stc_gpio_epfr04_field_t;
+
+typedef struct stc_gpio_epfr05_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA4E0    : 1;
+  __IO uint32_t TIOA4E1    : 1;
+  __IO uint32_t TIOB4S0    : 1;
+  __IO uint32_t TIOB4S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA5S0    : 1;
+  __IO uint32_t TIOA5S1    : 1;
+  __IO uint32_t TIOA5E0    : 1;
+  __IO uint32_t TIOA5E1    : 1;
+  __IO uint32_t TIOB5S0    : 1;
+  __IO uint32_t TIOB5S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA6E0    : 1;
+  __IO uint32_t TIOA6E1    : 1;
+  __IO uint32_t TIOB6S0    : 1;
+  __IO uint32_t TIOB6S1    : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA7S0    : 1;
+  __IO uint32_t TIOA7S1    : 1;
+  __IO uint32_t TIOA7E0    : 1;
+  __IO uint32_t TIOA7E1    : 1;
+  __IO uint32_t TIOB7S0    : 1;
+  __IO uint32_t TIOB7S1    : 1;
+} stc_gpio_epfr05_field_t;
+
+typedef struct stc_gpio_epfr06_field
+{
+  __IO uint32_t EINT00S0   : 1;
+  __IO uint32_t EINT00S1   : 1;
+  __IO uint32_t EINT01S0   : 1;
+  __IO uint32_t EINT01S1   : 1;
+  __IO uint32_t EINT02S0   : 1;
+  __IO uint32_t EINT02S1   : 1;
+  __IO uint32_t EINT03S0   : 1;
+  __IO uint32_t EINT03S1   : 1;
+  __IO uint32_t EINT04S0   : 1;
+  __IO uint32_t EINT04S1   : 1;
+  __IO uint32_t EINT05S0   : 1;
+  __IO uint32_t EINT05S1   : 1;
+  __IO uint32_t EINT06S0   : 1;
+  __IO uint32_t EINT06S1   : 1;
+  __IO uint32_t EINT07S0   : 1;
+  __IO uint32_t EINT07S1   : 1;
+  __IO uint32_t EINT08S0   : 1;
+  __IO uint32_t EINT08S1   : 1;
+  __IO uint32_t EINT09S0   : 1;
+  __IO uint32_t EINT09S1   : 1;
+  __IO uint32_t EINT10S0   : 1;
+  __IO uint32_t EINT10S1   : 1;
+  __IO uint32_t EINT11S0   : 1;
+  __IO uint32_t EINT11S1   : 1;
+  __IO uint32_t EINT12S0   : 1;
+  __IO uint32_t EINT12S1   : 1;
+  __IO uint32_t EINT13S0   : 1;
+  __IO uint32_t EINT13S1   : 1;
+  __IO uint32_t EINT14S0   : 1;
+  __IO uint32_t EINT14S1   : 1;
+  __IO uint32_t EINT15S0   : 1;
+  __IO uint32_t EINT15S1   : 1;
+} stc_gpio_epfr06_field_t;
+
+typedef struct stc_gpio_epfr07_field
+{
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t SIN0S0     : 1;
+  __IO uint32_t SIN0S1     : 1;
+  __IO uint32_t SOT0B0     : 1;
+  __IO uint32_t SOT0B1     : 1;
+  __IO uint32_t SCK0B0     : 1;
+  __IO uint32_t SCK0B1     : 1;
+  __IO uint32_t SIN1S0     : 1;
+  __IO uint32_t SIN1S1     : 1;
+  __IO uint32_t SOT1B0     : 1;
+  __IO uint32_t SOT1B1     : 1;
+  __IO uint32_t SCK1B0     : 1;
+  __IO uint32_t SCK1B1     : 1;
+  __IO uint32_t SIN2S0     : 1;
+  __IO uint32_t SIN2S1     : 1;
+  __IO uint32_t SOT2B0     : 1;
+  __IO uint32_t SOT2B1     : 1;
+  __IO uint32_t SCK2B0     : 1;
+  __IO uint32_t SCK2B1     : 1;
+  __IO uint32_t SIN3S0     : 1;
+  __IO uint32_t SIN3S1     : 1;
+  __IO uint32_t SOT3B0     : 1;
+  __IO uint32_t SOT3B1     : 1;
+  __IO uint32_t SCK3B0     : 1;
+  __IO uint32_t SCK3B1     : 1;
+} stc_gpio_epfr07_field_t;
+
+typedef struct stc_gpio_epfr08_field
+{
+  __IO uint32_t RTS4E0     : 1;
+  __IO uint32_t RTS4E1     : 1;
+  __IO uint32_t CTS4S0     : 1;
+  __IO uint32_t CTS4S1     : 1;
+  __IO uint32_t SIN4S0     : 1;
+  __IO uint32_t SIN4S1     : 1;
+  __IO uint32_t SOT4B0     : 1;
+  __IO uint32_t SOT4B1     : 1;
+  __IO uint32_t SCK4B0     : 1;
+  __IO uint32_t SCK4B1     : 1;
+  __IO uint32_t SIN5S0     : 1;
+  __IO uint32_t SIN5S1     : 1;
+  __IO uint32_t SOT5B0     : 1;
+  __IO uint32_t SOT5B1     : 1;
+  __IO uint32_t SCK5B0     : 1;
+  __IO uint32_t SCK5B1     : 1;
+  __IO uint32_t SIN6S0     : 1;
+  __IO uint32_t SIN6S1     : 1;
+  __IO uint32_t SOT6B0     : 1;
+  __IO uint32_t SOT6B1     : 1;
+  __IO uint32_t SCK6B0     : 1;
+  __IO uint32_t SCK6B1     : 1;
+  __IO uint32_t SIN7S0     : 1;
+  __IO uint32_t SIN7S1     : 1;
+  __IO uint32_t SOT7B0     : 1;
+  __IO uint32_t SOT7B1     : 1;
+  __IO uint32_t SCK7B0     : 1;
+  __IO uint32_t SCK7B1     : 1;
+} stc_gpio_epfr08_field_t;
+
+typedef struct stc_gpio_epfr09_field
+{
+  __IO uint32_t QAIN0S0    : 1;
+  __IO uint32_t QAIN0S1    : 1;
+  __IO uint32_t QBIN0S0    : 1;
+  __IO uint32_t QBIN0S1    : 1;
+  __IO uint32_t QZIN0S0    : 1;
+  __IO uint32_t QZIN0S1    : 1;
+  __IO uint32_t QAIN1S0    : 1;
+  __IO uint32_t QAIN1S1    : 1;
+  __IO uint32_t QBIN1S0    : 1;
+  __IO uint32_t QBIN1S1    : 1;
+  __IO uint32_t QZIN1S0    : 1;
+  __IO uint32_t QZIN1S1    : 1;
+  __IO uint32_t ADTRG0S0   : 1;
+  __IO uint32_t ADTRG0S1   : 1;
+  __IO uint32_t ADTRG0S2   : 1;
+  __IO uint32_t ADTRG0S3   : 1;
+  __IO uint32_t ADTRG1S0   : 1;
+  __IO uint32_t ADTRG1S1   : 1;
+  __IO uint32_t ADTRG1S2   : 1;
+  __IO uint32_t ADTRG1S3   : 1;
+  __IO uint32_t ADTRG2S0   : 1;
+  __IO uint32_t ADTRG2S1   : 1;
+  __IO uint32_t ADTRG2S2   : 1;
+  __IO uint32_t ADTRG2S3   : 1;
+} stc_gpio_epfr09_field_t;
+
+typedef struct stc_gpio_epfr10_field
+{
+  __IO uint32_t UEDEFB     : 1;
+  __IO uint32_t UEDTHB     : 1;
+  __IO uint32_t UECLKE     : 1;
+  __IO uint32_t UEWEXE     : 1;
+  __IO uint32_t UEDQME     : 1;
+  __IO uint32_t UEOEXE     : 1;
+  __IO uint32_t UEFLSE     : 1;
+  __IO uint32_t UECS1E     : 1;
+  __IO uint32_t UECS2E     : 1;
+  __IO uint32_t UECS3E     : 1;
+  __IO uint32_t UECS4E     : 1;
+  __IO uint32_t UECS5E     : 1;
+  __IO uint32_t UECS6E     : 1;
+  __IO uint32_t UECS7E     : 1;
+  __IO uint32_t UEAOOE     : 1;
+  __IO uint32_t UEA08E     : 1;
+  __IO uint32_t UEA09E     : 1;
+  __IO uint32_t UEA10E     : 1;
+  __IO uint32_t UEA11E     : 1;
+  __IO uint32_t UEA12E     : 1;
+  __IO uint32_t UEA13E     : 1;
+  __IO uint32_t UEA14E     : 1;
+  __IO uint32_t UEA15E     : 1;
+  __IO uint32_t UEA16E     : 1;
+  __IO uint32_t UEA17E     : 1;
+  __IO uint32_t UEA18E     : 1;
+  __IO uint32_t UEA19E     : 1;
+  __IO uint32_t UEA20E     : 1;
+  __IO uint32_t UEA21E     : 1;
+  __IO uint32_t UEA22E     : 1;
+  __IO uint32_t UEA23E     : 1;
+  __IO uint32_t UEA24E     : 1;
+} stc_gpio_epfr10_field_t;
+
+typedef struct stc_gpio_epfr11_field
+{
+  __IO uint32_t UEALEE     : 1;
+  __IO uint32_t UECS0E     : 1;
+  __IO uint32_t UEA01E     : 1;
+  __IO uint32_t UEA02E     : 1;
+  __IO uint32_t UEA03E     : 1;
+  __IO uint32_t UEA04E     : 1;
+  __IO uint32_t UEA05E     : 1;
+  __IO uint32_t UEA06E     : 1;
+  __IO uint32_t UEA07E     : 1;
+  __IO uint32_t UED00B     : 1;
+  __IO uint32_t UED01B     : 1;
+  __IO uint32_t UED02B     : 1;
+  __IO uint32_t UED03B     : 1;
+  __IO uint32_t UED04B     : 1;
+  __IO uint32_t UED05B     : 1;
+  __IO uint32_t UED06B     : 1;
+  __IO uint32_t UED07B     : 1;
+  __IO uint32_t UED08B     : 1;
+  __IO uint32_t UED09B     : 1;
+  __IO uint32_t UED10B     : 1;
+  __IO uint32_t UED11B     : 1;
+  __IO uint32_t UED12B     : 1;
+  __IO uint32_t UED13B     : 1;
+  __IO uint32_t UED14B     : 1;
+  __IO uint32_t UED15B     : 1;
+  __IO uint32_t UERLC      : 1;
+} stc_gpio_epfr11_field_t;
+
+typedef struct stc_gpio_epfr12_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA8E0    : 1;
+  __IO uint32_t TIOA8E1    : 1;
+  __IO uint32_t TIOB8S0    : 1;
+  __IO uint32_t TIOB8S1    : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA9S0    : 1;
+  __IO uint32_t TIOA9S1    : 1;
+  __IO uint32_t TIOA9E0    : 1;
+  __IO uint32_t TIOA9E1    : 1;
+  __IO uint32_t TIOB9S0    : 1;
+  __IO uint32_t TIOB9S1    : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA10E0   : 1;
+  __IO uint32_t TIOA10E1   : 1;
+  __IO uint32_t TIOB10S0   : 1;
+  __IO uint32_t TIOB10S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA11S0   : 1;
+  __IO uint32_t TIOA11S1   : 1;
+  __IO uint32_t TIOA11E0   : 1;
+  __IO uint32_t TIOA11E1   : 1;
+  __IO uint32_t TIOB11S0   : 1;
+  __IO uint32_t TIOB11S1   : 1;
+} stc_gpio_epfr12_field_t;
+
+typedef struct stc_gpio_epfr13_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TIOA12E0   : 1;
+  __IO uint32_t TIOA12E1   : 1;
+  __IO uint32_t TIOB12S0   : 1;
+  __IO uint32_t TIOB12S1   : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t TIOA13S0   : 1;
+  __IO uint32_t TIOA13S1   : 1;
+  __IO uint32_t TIOA13E0   : 1;
+  __IO uint32_t TIOA13E1   : 1;
+  __IO uint32_t TIOB13S0   : 1;
+  __IO uint32_t TIOB13S1   : 1;
+       uint32_t RESERVED3  : 4;
+  __IO uint32_t TIOA14E0   : 1;
+  __IO uint32_t TIOA14E1   : 1;
+  __IO uint32_t TIOB14S0   : 1;
+  __IO uint32_t TIOB14S1   : 1;
+       uint32_t RESERVED4  : 2;
+  __IO uint32_t TIOA15S0   : 1;
+  __IO uint32_t TIOA15S1   : 1;
+  __IO uint32_t TIOA15E0   : 1;
+  __IO uint32_t TIOA15E1   : 1;
+  __IO uint32_t TIOB15S0   : 1;
+  __IO uint32_t TIOB15S1   : 1;
+} stc_gpio_epfr13_field_t;
+
+typedef struct stc_gpio_epfr14_field
+{
+  __IO uint32_t QAIN2S0    : 1;
+  __IO uint32_t QAIN2S1    : 1;
+  __IO uint32_t QBIN2S0    : 1;
+  __IO uint32_t QBIN2S1    : 1;
+  __IO uint32_t QZIN2S0    : 1;
+  __IO uint32_t QZIN2S1    : 1;
+       uint32_t RESERVED1  : 12;
+  __IO uint32_t E_TD0E     : 1;
+  __IO uint32_t E_TD1E     : 1;
+  __IO uint32_t E_TE0E     : 1;
+  __IO uint32_t E_TE1E     : 1;
+  __IO uint32_t E_MC0E     : 1;
+  __IO uint32_t E_MC1B     : 1;
+  __IO uint32_t E_MD0B     : 1;
+  __IO uint32_t E_MD1B     : 1;
+  __IO uint32_t E_CKE      : 1;
+  __IO uint32_t E_PSE      : 1;
+  __IO uint32_t E_SPLC0    : 1;
+  __IO uint32_t E_SPLC1    : 1;
+} stc_gpio_epfr14_field_t;
+
+typedef struct stc_gpio_epfr15_field
+{
+  __IO uint32_t EINT16S0   : 1;
+  __IO uint32_t EINT16S1   : 1;
+  __IO uint32_t EINT17S0   : 1;
+  __IO uint32_t EINT17S1   : 1;
+  __IO uint32_t EINT18S0   : 1;
+  __IO uint32_t EINT18S1   : 1;
+  __IO uint32_t EINT19S0   : 1;
+  __IO uint32_t EINT19S1   : 1;
+  __IO uint32_t EINT20S0   : 1;
+  __IO uint32_t EINT20S1   : 1;
+  __IO uint32_t EINT21S0   : 1;
+  __IO uint32_t EINT21S1   : 1;
+  __IO uint32_t EINT22S0   : 1;
+  __IO uint32_t EINT22S1   : 1;
+  __IO uint32_t EINT23S0   : 1;
+  __IO uint32_t EINT23S1   : 1;
+  __IO uint32_t EINT24S0   : 1;
+  __IO uint32_t EINT24S1   : 1;
+  __IO uint32_t EINT25S0   : 1;
+  __IO uint32_t EINT25S1   : 1;
+  __IO uint32_t EINT26S0   : 1;
+  __IO uint32_t EINT26S1   : 1;
+  __IO uint32_t EINT27S0   : 1;
+  __IO uint32_t EINT27S1   : 1;
+  __IO uint32_t EINT28S0   : 1;
+  __IO uint32_t EINT28S1   : 1;
+  __IO uint32_t EINT29S0   : 1;
+  __IO uint32_t EINT29S1   : 1;
+  __IO uint32_t EINT30S0   : 1;
+  __IO uint32_t EINT30S1   : 1;
+  __IO uint32_t EINT31S0   : 1;
+  __IO uint32_t EINT31S1   : 1;
+} stc_gpio_epfr15_field_t;
+
+typedef struct stc_gpio_pzr0_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr0_field_t;
+
+typedef struct stc_gpio_pzr1_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr1_field_t;
+
+typedef struct stc_gpio_pzr2_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+} stc_gpio_pzr2_field_t;
+
+typedef struct stc_gpio_pzr3_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr3_field_t;
+
+typedef struct stc_gpio_pzr4_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+} stc_gpio_pzr4_field_t;
+
+typedef struct stc_gpio_pzr5_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+} stc_gpio_pzr5_field_t;
+
+typedef struct stc_gpio_pzr6_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+} stc_gpio_pzr6_field_t;
+
+typedef struct stc_gpio_pzr7_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzr7_field_t;
+
+typedef struct stc_gpio_pzr8_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzr8_field_t;
+
+typedef struct stc_gpio_pzr9_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pzr9_field_t;
+
+typedef struct stc_gpio_pzra_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+} stc_gpio_pzra_field_t;
+
+typedef struct stc_gpio_pzrb_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+} stc_gpio_pzrb_field_t;
+
+typedef struct stc_gpio_pzrc_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+  __IO uint32_t P7         : 1;
+  __IO uint32_t P8         : 1;
+  __IO uint32_t P9         : 1;
+  __IO uint32_t PA         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t PC         : 1;
+  __IO uint32_t PD         : 1;
+  __IO uint32_t PE         : 1;
+  __IO uint32_t PF         : 1;
+} stc_gpio_pzrc_field_t;
+
+typedef struct stc_gpio_pzrd_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzrd_field_t;
+
+typedef struct stc_gpio_pzre_field
+{
+  __IO uint32_t P0         : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+} stc_gpio_pzre_field_t;
+
+typedef struct stc_gpio_pzrf_field
+{
+  __IO uint32_t P0         : 1;
+  __IO uint32_t P1         : 1;
+  __IO uint32_t P2         : 1;
+  __IO uint32_t P3         : 1;
+  __IO uint32_t P4         : 1;
+  __IO uint32_t P5         : 1;
+  __IO uint32_t P6         : 1;
+} stc_gpio_pzrf_field_t;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* LVD_MODULE register bit fields */
+typedef struct stc_lvd_lvd_ctl_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SVHI0      : 1;
+  __IO  uint8_t SVHI1      : 1;
+  __IO  uint8_t SVHI2      : 1;
+  __IO  uint8_t SVHI3      : 1;
+        uint8_t RESERVED2  : 1;
+  __IO  uint8_t LVDIE      : 1;
+} stc_lvd_lvd_ctl_field_t;
+
+typedef struct stc_lvd_lvd_str_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIR      : 1;
+} stc_lvd_lvd_str_field_t;
+
+typedef struct stc_lvd_lvd_clr_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDCL      : 1;
+} stc_lvd_lvd_clr_field_t;
+
+typedef struct stc_lvd_lvd_str2_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t LVDIRDY    : 1;
+} stc_lvd_lvd_str2_field_t;
+
+/******************************************************************************
+ * USB Ethernet CLK
+ ******************************************************************************/
+/* USB ETHERNET CLK register bit fields */
+typedef struct stc_usbethernetclk_uccr_field
+{
+  __IO  uint8_t UCEN0      : 1;
+  __IO  uint8_t UCSEL0     : 1;
+  __IO  uint8_t UCSEL1     : 1;
+  __IO  uint8_t UCEN1      : 1;
+  __IO  uint8_t ECEN       : 1;
+  __IO  uint8_t ECSEL0     : 1;
+  __IO  uint8_t ECSEL1     : 1;
+} stc_usbethernetclk_uccr_field_t;
+
+typedef struct stc_usbethernetclk_upcr1_field
+{
+  __IO  uint8_t UPLLEN     : 1;
+  __IO  uint8_t UPINC      : 1;
+} stc_usbethernetclk_upcr1_field_t;
+
+typedef struct stc_usbethernetclk_upcr2_field
+{
+  __IO  uint8_t UPOWT0     : 1;
+  __IO  uint8_t UPOWT1     : 1;
+  __IO  uint8_t UPOWT2     : 1;
+} stc_usbethernetclk_upcr2_field_t;
+
+typedef struct stc_usbethernetclk_upcr3_field
+{
+  __IO  uint8_t UPLLK0     : 1;
+  __IO  uint8_t UPLLK1     : 1;
+  __IO  uint8_t UPLLK2     : 1;
+  __IO  uint8_t UPLLK3     : 1;
+  __IO  uint8_t UPLLK4     : 1;
+} stc_usbethernetclk_upcr3_field_t;
+
+typedef struct stc_usbethernetclk_upcr4_field
+{
+  __IO  uint8_t UPLLN0     : 1;
+  __IO  uint8_t UPLLN1     : 1;
+  __IO  uint8_t UPLLN2     : 1;
+  __IO  uint8_t UPLLN3     : 1;
+  __IO  uint8_t UPLLN4     : 1;
+  __IO  uint8_t UPLLN5     : 1;
+  __IO  uint8_t UPLLN6     : 1;
+} stc_usbethernetclk_upcr4_field_t;
+
+typedef struct stc_usbethernetclk_up_str_field
+{
+  __IO  uint8_t UPRDY      : 1;
+} stc_usbethernetclk_up_str_field_t;
+
+typedef struct stc_usbethernetclk_upint_enr_field
+{
+  __IO  uint8_t UPCSE      : 1;
+} stc_usbethernetclk_upint_enr_field_t;
+
+typedef struct stc_usbethernetclk_upint_clr_field
+{
+  __IO  uint8_t UPCSC      : 1;
+} stc_usbethernetclk_upint_clr_field_t;
+
+typedef struct stc_usbethernetclk_upint_str_field
+{
+  __IO  uint8_t UPCSI      : 1;
+} stc_usbethernetclk_upint_str_field_t;
+
+typedef struct stc_usbethernetclk_upcr5_field
+{
+  __IO  uint8_t UPLLM0     : 1;
+  __IO  uint8_t UPLLM1     : 1;
+  __IO  uint8_t UPLLM2     : 1;
+  __IO  uint8_t UPLLM3     : 1;
+} stc_usbethernetclk_upcr5_field_t;
+
+typedef struct stc_usbethernetclk_upcr6_field
+{
+  __IO  uint8_t UBSR0      : 1;
+  __IO  uint8_t UBSR1      : 1;
+  __IO  uint8_t UBSR2      : 1;
+  __IO  uint8_t UBSR3      : 1;
+} stc_usbethernetclk_upcr6_field_t;
+
+typedef struct stc_usbethernetclk_upcr7_field
+{
+  __IO  uint8_t EPLLEN     : 1;
+} stc_usbethernetclk_upcr7_field_t;
+
+typedef struct stc_usbethernetclk_usben0_field
+{
+  __IO  uint8_t USBEN0     : 1;
+} stc_usbethernetclk_usben0_field_t;
+
+typedef struct stc_usbethernetclk_usben1_field
+{
+  __IO  uint8_t USBEN1     : 1;
+} stc_usbethernetclk_usben1_field_t;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* MFS03_UART_MODULE register bit fields */
+typedef struct stc_mfs03_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_uart_smr_field_t;
+
+typedef struct stc_mfs03_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_uart_scr_field_t;
+
+typedef struct stc_mfs03_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs03_uart_escr_field_t;
+
+typedef struct stc_mfs03_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_uart_ssr_field_t;
+
+typedef struct stc_mfs03_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_rdr_field_t;
+
+typedef struct stc_mfs03_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs03_uart_tdr_field_t;
+
+typedef struct stc_mfs03_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_uart_bgr_field_t;
+
+typedef struct stc_mfs03_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_uart_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* MFS03_CSIO_MODULE register bit fields */
+typedef struct stc_mfs03_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_csio_smr_field_t;
+
+typedef struct stc_mfs03_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_csio_scr_field_t;
+
+typedef struct stc_mfs03_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs03_csio_escr_field_t;
+
+typedef struct stc_mfs03_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_csio_ssr_field_t;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* MFS03_LIN_MODULE register bit fields */
+typedef struct stc_mfs03_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_lin_smr_field_t;
+
+typedef struct stc_mfs03_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs03_lin_scr_field_t;
+
+typedef struct stc_mfs03_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs03_lin_escr_field_t;
+
+typedef struct stc_mfs03_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_lin_ssr_field_t;
+
+typedef struct stc_mfs03_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs03_lin_bgr_field_t;
+
+typedef struct stc_mfs03_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs03_lin_bgr1_field_t;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* MFS03_I2C_MODULE register bit fields */
+typedef struct stc_mfs03_i2c_smr_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs03_i2c_smr_field_t;
+
+typedef struct stc_mfs03_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs03_i2c_ibcr_field_t;
+
+typedef struct stc_mfs03_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs03_i2c_ibsr_field_t;
+
+typedef struct stc_mfs03_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs03_i2c_ssr_field_t;
+
+typedef struct stc_mfs03_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs03_i2c_isba_field_t;
+
+typedef struct stc_mfs03_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs03_i2c_ismk_field_t;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* MFS47_UART_MODULE register bit fields */
+typedef struct stc_mfs47_uart_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_uart_smr_field_t;
+
+typedef struct stc_mfs47_uart_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_uart_scr_field_t;
+
+typedef struct stc_mfs47_uart_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t P          : 1;
+  __IO  uint8_t PEN        : 1;
+  __IO  uint8_t INV        : 1;
+  __IO  uint8_t ESBL       : 1;
+  __IO  uint8_t FLWEN      : 1;
+} stc_mfs47_uart_escr_field_t;
+
+typedef struct stc_mfs47_uart_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t PE         : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_uart_ssr_field_t;
+
+typedef struct stc_mfs47_uart_rdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_rdr_field_t;
+
+typedef struct stc_mfs47_uart_tdr_field
+{
+       uint16_t RESERVED1  : 8;
+  __IO uint16_t AD         : 1;
+} stc_mfs47_uart_tdr_field_t;
+
+typedef struct stc_mfs47_uart_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_uart_bgr_field_t;
+
+typedef struct stc_mfs47_uart_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_uart_bgr1_field_t;
+
+typedef struct stc_mfs47_uart_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_uart_fcr_field_t;
+
+typedef struct stc_mfs47_uart_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_uart_fcr0_field_t;
+
+typedef struct stc_mfs47_uart_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_uart_fcr1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_uart_fbyte_field_t;
+
+typedef struct stc_mfs47_uart_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_uart_fbyte1_field_t;
+
+typedef struct stc_mfs47_uart_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_uart_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* MFS47_CSIO_MODULE register bit fields */
+typedef struct stc_mfs47_csio_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+  __IO  uint8_t SCKE       : 1;
+  __IO  uint8_t BDS        : 1;
+  __IO  uint8_t SCINV      : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_csio_smr_field_t;
+
+typedef struct stc_mfs47_csio_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t SPI        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_csio_scr_field_t;
+
+typedef struct stc_mfs47_csio_escr_field
+{
+  __IO  uint8_t L0         : 1;
+  __IO  uint8_t L1         : 1;
+  __IO  uint8_t L2         : 1;
+  __IO  uint8_t WT0        : 1;
+  __IO  uint8_t WT1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SOP        : 1;
+} stc_mfs47_csio_escr_field_t;
+
+typedef struct stc_mfs47_csio_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+        uint8_t RESERVED1  : 3;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_csio_ssr_field_t;
+
+typedef struct stc_mfs47_csio_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_csio_fcr_field_t;
+
+typedef struct stc_mfs47_csio_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_csio_fcr0_field_t;
+
+typedef struct stc_mfs47_csio_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_csio_fcr1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_csio_fbyte_field_t;
+
+typedef struct stc_mfs47_csio_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_csio_fbyte1_field_t;
+
+typedef struct stc_mfs47_csio_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_csio_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* MFS47_LIN_MODULE register bit fields */
+typedef struct stc_mfs47_lin_smr_field
+{
+  __IO  uint8_t SOE        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t SBL        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_lin_smr_field_t;
+
+typedef struct stc_mfs47_lin_scr_field
+{
+  __IO  uint8_t TXE        : 1;
+  __IO  uint8_t RXE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t LBR        : 1;
+  __IO  uint8_t MS         : 1;
+  __IO  uint8_t UPCL       : 1;
+} stc_mfs47_lin_scr_field_t;
+
+typedef struct stc_mfs47_lin_escr_field
+{
+  __IO  uint8_t DEL0       : 1;
+  __IO  uint8_t DEL1       : 1;
+  __IO  uint8_t LBL0       : 1;
+  __IO  uint8_t LBL1       : 1;
+  __IO  uint8_t LBIE       : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t ESBL       : 1;
+} stc_mfs47_lin_escr_field_t;
+
+typedef struct stc_mfs47_lin_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t FRE        : 1;
+  __IO  uint8_t LBD        : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_lin_ssr_field_t;
+
+typedef struct stc_mfs47_lin_bgr_field
+{
+       uint16_t RESERVED1  : 15;
+  __IO uint16_t EXT        : 1;
+} stc_mfs47_lin_bgr_field_t;
+
+typedef struct stc_mfs47_lin_bgr1_field
+{
+        uint8_t RESERVED1  : 7;
+  __IO  uint8_t EXT        : 1;
+} stc_mfs47_lin_bgr1_field_t;
+
+typedef struct stc_mfs47_lin_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_lin_fcr_field_t;
+
+typedef struct stc_mfs47_lin_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_lin_fcr0_field_t;
+
+typedef struct stc_mfs47_lin_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_lin_fcr1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_lin_fbyte_field_t;
+
+typedef struct stc_mfs47_lin_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_lin_fbyte1_field_t;
+
+typedef struct stc_mfs47_lin_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_lin_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* MFS47_I2C_MODULE register bit fields */
+typedef struct stc_mfs47_i2c_smr_field
+{
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t TIE        : 1;
+  __IO  uint8_t RIE        : 1;
+  __IO  uint8_t WUCR       : 1;
+  __IO  uint8_t MD         : 3;
+} stc_mfs47_i2c_smr_field_t;
+
+typedef struct stc_mfs47_i2c_ibcr_field
+{
+  __IO  uint8_t INT        : 1;
+  __IO  uint8_t BER        : 1;
+  __IO  uint8_t INTE       : 1;
+  __IO  uint8_t CNDE       : 1;
+  __IO  uint8_t WSEL       : 1;
+  __IO  uint8_t ACKE       : 1;
+  __IO  uint8_t SCC        : 1;
+  __IO  uint8_t MSS        : 1;
+} stc_mfs47_i2c_ibcr_field_t;
+
+typedef struct stc_mfs47_i2c_ibsr_field
+{
+  __IO  uint8_t BB         : 1;
+  __IO  uint8_t SPC        : 1;
+  __IO  uint8_t RSC        : 1;
+  __IO  uint8_t AL         : 1;
+  __IO  uint8_t TRX        : 1;
+  __IO  uint8_t RSA        : 1;
+  __IO  uint8_t RACK       : 1;
+  __IO  uint8_t FBT        : 1;
+} stc_mfs47_i2c_ibsr_field_t;
+
+typedef struct stc_mfs47_i2c_ssr_field
+{
+  __IO  uint8_t TBI        : 1;
+  __IO  uint8_t TDRE       : 1;
+  __IO  uint8_t RDRF       : 1;
+  __IO  uint8_t ORE        : 1;
+  __IO  uint8_t TBIE       : 1;
+  __IO  uint8_t DMA        : 1;
+  __IO  uint8_t TSET       : 1;
+  __IO  uint8_t REC        : 1;
+} stc_mfs47_i2c_ssr_field_t;
+
+typedef struct stc_mfs47_i2c_isba_field
+{
+  __IO  uint8_t SA0        : 1;
+  __IO  uint8_t SA1        : 1;
+  __IO  uint8_t SA2        : 1;
+  __IO  uint8_t SA3        : 1;
+  __IO  uint8_t SA4        : 1;
+  __IO  uint8_t SA5        : 1;
+  __IO  uint8_t SA6        : 1;
+  __IO  uint8_t SAEN       : 1;
+} stc_mfs47_i2c_isba_field_t;
+
+typedef struct stc_mfs47_i2c_ismk_field
+{
+  __IO  uint8_t SM0        : 1;
+  __IO  uint8_t SM1        : 1;
+  __IO  uint8_t SM2        : 1;
+  __IO  uint8_t SM3        : 1;
+  __IO  uint8_t SM4        : 1;
+  __IO  uint8_t SM5        : 1;
+  __IO  uint8_t SM6        : 1;
+  __IO  uint8_t EN         : 1;
+} stc_mfs47_i2c_ismk_field_t;
+
+typedef struct stc_mfs47_i2c_fcr_field
+{
+  __IO uint16_t FE1        : 1;
+  __IO uint16_t FE2        : 1;
+  __IO uint16_t FCL1       : 1;
+  __IO uint16_t FCL2       : 1;
+  __IO uint16_t FSET       : 1;
+  __IO uint16_t FLD        : 1;
+  __IO uint16_t FLST       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t FSEL       : 1;
+  __IO uint16_t FTIE       : 1;
+  __IO uint16_t FDRQ       : 1;
+  __IO uint16_t FRIE       : 1;
+  __IO uint16_t FLSTE      : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t FTST0      : 1;
+  __IO uint16_t FTST1      : 1;
+} stc_mfs47_i2c_fcr_field_t;
+
+typedef struct stc_mfs47_i2c_fcr0_field
+{
+  __IO  uint8_t FE1        : 1;
+  __IO  uint8_t FE2        : 1;
+  __IO  uint8_t FCL1       : 1;
+  __IO  uint8_t FCL2       : 1;
+  __IO  uint8_t FSET       : 1;
+  __IO  uint8_t FLD        : 1;
+  __IO  uint8_t FLST       : 1;
+} stc_mfs47_i2c_fcr0_field_t;
+
+typedef struct stc_mfs47_i2c_fcr1_field
+{
+  __IO  uint8_t FSEL       : 1;
+  __IO  uint8_t FTIE       : 1;
+  __IO  uint8_t FDRQ       : 1;
+  __IO  uint8_t FRIE       : 1;
+  __IO  uint8_t FLSTE      : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t FTST0      : 1;
+  __IO  uint8_t FTST1      : 1;
+} stc_mfs47_i2c_fcr1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte_field
+{
+  __IO uint16_t FD0        : 1;
+  __IO uint16_t FD1        : 1;
+  __IO uint16_t FD2        : 1;
+  __IO uint16_t FD3        : 1;
+  __IO uint16_t FD4        : 1;
+  __IO uint16_t FD5        : 1;
+  __IO uint16_t FD6        : 1;
+  __IO uint16_t FD7        : 1;
+  __IO uint16_t FD8        : 1;
+  __IO uint16_t FD9        : 1;
+  __IO uint16_t FD10       : 1;
+  __IO uint16_t FD11       : 1;
+  __IO uint16_t FD12       : 1;
+  __IO uint16_t FD13       : 1;
+  __IO uint16_t FD14       : 1;
+  __IO uint16_t FD15       : 1;
+} stc_mfs47_i2c_fbyte_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte1_field
+{
+  __IO  uint8_t FD0        : 1;
+  __IO  uint8_t FD1        : 1;
+  __IO  uint8_t FD2        : 1;
+  __IO  uint8_t FD3        : 1;
+  __IO  uint8_t FD4        : 1;
+  __IO  uint8_t FD5        : 1;
+  __IO  uint8_t FD6        : 1;
+  __IO  uint8_t FD7        : 1;
+} stc_mfs47_i2c_fbyte1_field_t;
+
+typedef struct stc_mfs47_i2c_fbyte2_field
+{
+  __IO  uint8_t FD8        : 1;
+  __IO  uint8_t FD9        : 1;
+  __IO  uint8_t FD10       : 1;
+  __IO  uint8_t FD11       : 1;
+  __IO  uint8_t FD12       : 1;
+  __IO  uint8_t FD13       : 1;
+  __IO  uint8_t FD14       : 1;
+  __IO  uint8_t FD15       : 1;
+} stc_mfs47_i2c_fbyte2_field_t;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct stc_mfs_nfc_i2cdnf_field
+{
+  __IO uint16_t I2CDNF00   : 1;
+  __IO uint16_t I2CDNF01   : 1;
+  __IO uint16_t I2CDNF10   : 1;
+  __IO uint16_t I2CDNF11   : 1;
+  __IO uint16_t I2CDNF20   : 1;
+  __IO uint16_t I2CDNF21   : 1;
+  __IO uint16_t I2CDNF30   : 1;
+  __IO uint16_t I2CDNF31   : 1;
+  __IO uint16_t I2CDNF40   : 1;
+  __IO uint16_t I2CDNF41   : 1;
+  __IO uint16_t I2CDNF50   : 1;
+  __IO uint16_t I2CDNF51   : 1;
+  __IO uint16_t I2CDNF60   : 1;
+  __IO uint16_t I2CDNF61   : 1;
+  __IO uint16_t I2CDNF70   : 1;
+  __IO uint16_t I2CDNF71   : 1;
+} stc_mfs_nfc_i2cdnf_field_t;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC_MODULE register bit fields */
+typedef struct stc_crc_crccr_field
+{
+  __IO  uint8_t INIT       : 1;
+  __IO  uint8_t CRC32      : 1;
+  __IO  uint8_t LTLEND     : 1;
+  __IO  uint8_t LSBFST     : 1;
+  __IO  uint8_t CRCLTE     : 1;
+  __IO  uint8_t CRCLSF     : 1;
+  __IO  uint8_t FXOR       : 1;
+} stc_crc_crccr_field_t;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* WC_MODULE register bit fields */
+typedef struct stc_wc_wcrd_field
+{
+  __IO  uint8_t CTR0       : 1;
+  __IO  uint8_t CTR1       : 1;
+  __IO  uint8_t CTR2       : 1;
+  __IO  uint8_t CTR3       : 1;
+  __IO  uint8_t CTR4       : 1;
+  __IO  uint8_t CTR5       : 1;
+} stc_wc_wcrd_field_t;
+
+typedef struct stc_wc_wcrl_field
+{
+  __IO  uint8_t RLC0       : 1;
+  __IO  uint8_t RLC1       : 1;
+  __IO  uint8_t RLC2       : 1;
+  __IO  uint8_t RLC3       : 1;
+  __IO  uint8_t RLC4       : 1;
+  __IO  uint8_t RLC5       : 1;
+} stc_wc_wcrl_field_t;
+
+typedef struct stc_wc_wccr_field
+{
+  __IO  uint8_t WCIF       : 1;
+  __IO  uint8_t WCIE       : 1;
+  __IO  uint8_t CS0        : 1;
+  __IO  uint8_t CS1        : 1;
+        uint8_t RESERVED1  : 2;
+  __IO  uint8_t WCOP       : 1;
+  __IO  uint8_t WCEN       : 1;
+} stc_wc_wccr_field_t;
+
+typedef struct stc_wc_clk_sel_field
+{
+  __IO uint16_t SEL_IN     : 1;
+       uint16_t RESERVED1  : 7;
+  __IO uint16_t SEL_OUT    : 1;
+} stc_wc_clk_sel_field_t;
+
+typedef struct stc_wc_clk_en_field
+{
+  __IO  uint8_t CLK_EN     : 1;
+  __IO  uint8_t CLK_EN_R   : 1;
+} stc_wc_clk_en_field_t;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* EXBUS_MODULE register bit fields */
+typedef struct stc_exbus_mode0_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode0_field_t;
+
+typedef struct stc_exbus_mode1_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode1_field_t;
+
+typedef struct stc_exbus_mode2_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode2_field_t;
+
+typedef struct stc_exbus_mode3_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode3_field_t;
+
+typedef struct stc_exbus_mode4_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode4_field_t;
+
+typedef struct stc_exbus_mode5_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode5_field_t;
+
+typedef struct stc_exbus_mode6_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode6_field_t;
+
+typedef struct stc_exbus_mode7_field
+{
+  __IO uint32_t WDTH0      : 1;
+  __IO uint32_t WDTH1      : 1;
+  __IO uint32_t RBMON      : 1;
+  __IO uint32_t WEOFF      : 1;
+  __IO uint32_t NAND       : 1;
+  __IO uint32_t PAGE       : 1;
+  __IO uint32_t RDY        : 1;
+  __IO uint32_t SHRTDOUT   : 1;
+  __IO uint32_t MPXMODE    : 1;
+  __IO uint32_t ALEINV     : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t MPXDOFF    : 1;
+  __IO uint32_t MPXCSOF    : 1;
+  __IO uint32_t MOEXEUP    : 1;
+} stc_exbus_mode7_field_t;
+
+typedef struct stc_exbus_tim0_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim0_field_t;
+
+typedef struct stc_exbus_tim1_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim1_field_t;
+
+typedef struct stc_exbus_tim2_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim2_field_t;
+
+typedef struct stc_exbus_tim3_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim3_field_t;
+
+typedef struct stc_exbus_tim4_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim4_field_t;
+
+typedef struct stc_exbus_tim5_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim5_field_t;
+
+typedef struct stc_exbus_tim6_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim6_field_t;
+
+typedef struct stc_exbus_tim7_field
+{
+  __IO uint32_t RACC0      : 1;
+  __IO uint32_t RACC1      : 1;
+  __IO uint32_t RACC2      : 1;
+  __IO uint32_t RACC3      : 1;
+  __IO uint32_t RADC0      : 1;
+  __IO uint32_t RADC1      : 1;
+  __IO uint32_t RADC2      : 1;
+  __IO uint32_t RADC3      : 1;
+  __IO uint32_t FRADC0     : 1;
+  __IO uint32_t FRADC1     : 1;
+  __IO uint32_t FRADC2     : 1;
+  __IO uint32_t FRADC3     : 1;
+  __IO uint32_t RIDLC0     : 1;
+  __IO uint32_t RIDLC1     : 1;
+  __IO uint32_t RIDLC2     : 1;
+  __IO uint32_t RIDLC3     : 1;
+  __IO uint32_t WACC0      : 1;
+  __IO uint32_t WACC1      : 1;
+  __IO uint32_t WACC2      : 1;
+  __IO uint32_t WACC3      : 1;
+  __IO uint32_t WADC0      : 1;
+  __IO uint32_t WADC1      : 1;
+  __IO uint32_t WADC2      : 1;
+  __IO uint32_t WADC3      : 1;
+  __IO uint32_t WWEC0      : 1;
+  __IO uint32_t WWEC1      : 1;
+  __IO uint32_t WWEC2      : 1;
+  __IO uint32_t WWEC3      : 1;
+  __IO uint32_t WIDLC0     : 1;
+  __IO uint32_t WIDLC1     : 1;
+  __IO uint32_t WIDLC2     : 1;
+  __IO uint32_t WIDLC3     : 1;
+} stc_exbus_tim7_field_t;
+
+typedef struct stc_exbus_area0_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area0_field_t;
+
+typedef struct stc_exbus_area1_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area1_field_t;
+
+typedef struct stc_exbus_area2_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area2_field_t;
+
+typedef struct stc_exbus_area3_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area3_field_t;
+
+typedef struct stc_exbus_area4_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area4_field_t;
+
+typedef struct stc_exbus_area5_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area5_field_t;
+
+typedef struct stc_exbus_area6_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area6_field_t;
+
+typedef struct stc_exbus_area7_field
+{
+  __IO uint32_t ADDR0      : 1;
+  __IO uint32_t ADDR1      : 1;
+  __IO uint32_t ADDR2      : 1;
+  __IO uint32_t ADDR3      : 1;
+  __IO uint32_t ADDR4      : 1;
+  __IO uint32_t ADDR5      : 1;
+  __IO uint32_t ADDR6      : 1;
+  __IO uint32_t ADDR7      : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MASK0      : 1;
+  __IO uint32_t MASK1      : 1;
+  __IO uint32_t MASK2      : 1;
+  __IO uint32_t MASK3      : 1;
+  __IO uint32_t MASK4      : 1;
+  __IO uint32_t MASK5      : 1;
+  __IO uint32_t MASK6      : 1;
+} stc_exbus_area7_field_t;
+
+typedef struct stc_exbus_atim0_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim0_field_t;
+
+typedef struct stc_exbus_atim1_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim1_field_t;
+
+typedef struct stc_exbus_atim2_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim2_field_t;
+
+typedef struct stc_exbus_atim3_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim3_field_t;
+
+typedef struct stc_exbus_atim4_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim4_field_t;
+
+typedef struct stc_exbus_atim5_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim5_field_t;
+
+typedef struct stc_exbus_atim6_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim6_field_t;
+
+typedef struct stc_exbus_atim7_field
+{
+  __IO uint16_t ALC0       : 1;
+  __IO uint16_t ALC1       : 1;
+  __IO uint16_t ALC2       : 1;
+  __IO uint16_t ALC3       : 1;
+  __IO uint16_t ALES0      : 1;
+  __IO uint16_t ALES1      : 1;
+  __IO uint16_t ALES2      : 1;
+  __IO uint16_t ALES3      : 1;
+  __IO uint16_t ALEW0      : 1;
+  __IO uint16_t ALEW1      : 1;
+  __IO uint16_t ALEW2      : 1;
+  __IO uint16_t ALEW3      : 1;
+} stc_exbus_atim7_field_t;
+
+typedef struct stc_exbus_dclkr_field
+{
+  __IO  uint8_t MDIV0      : 1;
+  __IO  uint8_t MDIV1      : 1;
+  __IO  uint8_t MDIV2      : 1;
+  __IO  uint8_t MDIV3      : 1;
+  __IO  uint8_t MCLKON     : 1;
+} stc_exbus_dclkr_field_t;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB_MODULE register bit fields */
+typedef struct stc_usb_hcnt_field
+{
+  __IO uint16_t HOST       : 1;
+  __IO uint16_t URST       : 1;
+  __IO uint16_t SOFIRE     : 1;
+  __IO uint16_t DIRE       : 1;
+  __IO uint16_t CNNIRE     : 1;
+  __IO uint16_t CMPIRE     : 1;
+  __IO uint16_t URIRE      : 1;
+  __IO uint16_t RWKIRE     : 1;
+  __IO uint16_t RETRY      : 1;
+  __IO uint16_t CANCEL     : 1;
+  __IO uint16_t SOFSTEP    : 1;
+} stc_usb_hcnt_field_t;
+
+typedef struct stc_usb_hcnt0_field
+{
+  __IO  uint8_t HOST       : 1;
+  __IO  uint8_t URST       : 1;
+  __IO  uint8_t SOFIRE     : 1;
+  __IO  uint8_t DIRE       : 1;
+  __IO  uint8_t CNNIRE     : 1;
+  __IO  uint8_t CMPIRE     : 1;
+  __IO  uint8_t URIRE      : 1;
+  __IO  uint8_t RWKIRE     : 1;
+} stc_usb_hcnt0_field_t;
+
+typedef struct stc_usb_hcnt1_field
+{
+  __IO  uint8_t RETRY      : 1;
+  __IO  uint8_t CANCEL     : 1;
+  __IO  uint8_t SOFSTEP    : 1;
+} stc_usb_hcnt1_field_t;
+
+typedef struct stc_usb_hirq_field
+{
+  __IO  uint8_t SOFIRQ     : 1;
+  __IO  uint8_t DIRQ       : 1;
+  __IO  uint8_t CNNIRQ     : 1;
+  __IO  uint8_t CMPIRQ     : 1;
+  __IO  uint8_t URIRQ      : 1;
+  __IO  uint8_t RWKIRQ     : 1;
+        uint8_t RESERVED1  : 1;
+  __IO  uint8_t TCAN       : 1;
+} stc_usb_hirq_field_t;
+
+typedef struct stc_usb_herr_field
+{
+  __IO  uint8_t HS0        : 1;
+  __IO  uint8_t HS1        : 1;
+  __IO  uint8_t STUFF      : 1;
+  __IO  uint8_t TGERR      : 1;
+  __IO  uint8_t CRC        : 1;
+  __IO  uint8_t TOUT       : 1;
+  __IO  uint8_t RERR       : 1;
+  __IO  uint8_t LSTOF      : 1;
+} stc_usb_herr_field_t;
+
+typedef struct stc_usb_hstate_field
+{
+  __IO  uint8_t CSTAT      : 1;
+  __IO  uint8_t TMODE      : 1;
+  __IO  uint8_t SUSP       : 1;
+  __IO  uint8_t SOFBUSY    : 1;
+  __IO  uint8_t CLKSEL     : 1;
+  __IO  uint8_t ALIVE      : 1;
+} stc_usb_hstate_field_t;
+
+typedef struct stc_usb_hfcomp_field
+{
+  __IO  uint8_t FRAMECOMP0 : 1;
+  __IO  uint8_t FRAMECOMP1 : 1;
+  __IO  uint8_t FRAMECOMP2 : 1;
+  __IO  uint8_t FRAMECOMP3 : 1;
+  __IO  uint8_t FRAMECOMP4 : 1;
+  __IO  uint8_t FRAMECOMP5 : 1;
+  __IO  uint8_t FRAMECOMP6 : 1;
+  __IO  uint8_t FRAMECOMP7 : 1;
+} stc_usb_hfcomp_field_t;
+
+typedef struct stc_usb_hrtimer_field
+{
+  __IO uint16_t RTIMER0    : 1;
+  __IO uint16_t RTIMER1    : 1;
+  __IO uint16_t RTIMER2    : 1;
+  __IO uint16_t RTIMER3    : 1;
+  __IO uint16_t RTIMER4    : 1;
+  __IO uint16_t RTIMER5    : 1;
+  __IO uint16_t RTIMER6    : 1;
+  __IO uint16_t RTIMER7    : 1;
+  __IO uint16_t RTIMER8    : 1;
+  __IO uint16_t RTIMER9    : 1;
+  __IO uint16_t RTIMER10   : 1;
+  __IO uint16_t RTIMER11   : 1;
+  __IO uint16_t RTIMER12   : 1;
+  __IO uint16_t RTIMER13   : 1;
+  __IO uint16_t RTIMER14   : 1;
+  __IO uint16_t RTIMER15   : 1;
+} stc_usb_hrtimer_field_t;
+
+typedef struct stc_usb_hrtimer0_field
+{
+  __IO  uint8_t RTIMER00   : 1;
+  __IO  uint8_t RTIMER01   : 1;
+  __IO  uint8_t RTIMER02   : 1;
+  __IO  uint8_t RTIMER03   : 1;
+  __IO  uint8_t RTIMER04   : 1;
+  __IO  uint8_t RTIMER05   : 1;
+  __IO  uint8_t RTIMER06   : 1;
+  __IO  uint8_t RTIMER07   : 1;
+} stc_usb_hrtimer0_field_t;
+
+typedef struct stc_usb_hrtimer1_field
+{
+  __IO  uint8_t RTIMER10   : 1;
+  __IO  uint8_t RTIMER11   : 1;
+  __IO  uint8_t RTIMER12   : 1;
+  __IO  uint8_t RTIMER13   : 1;
+  __IO  uint8_t RTIMER14   : 1;
+  __IO  uint8_t RTIMER15   : 1;
+  __IO  uint8_t RTIMER16   : 1;
+  __IO  uint8_t RTIMER17   : 1;
+} stc_usb_hrtimer1_field_t;
+
+typedef struct stc_usb_hrtimer2_field
+{
+  __IO  uint8_t RTIMER20   : 1;
+  __IO  uint8_t RTIMER21   : 1;
+  __IO  uint8_t RTIMER22   : 1;
+} stc_usb_hrtimer2_field_t;
+
+typedef struct stc_usb_hadr_field
+{
+  __IO  uint8_t ADDRESS0   : 1;
+  __IO  uint8_t ADDRESS1   : 1;
+  __IO  uint8_t ADDRESS2   : 1;
+  __IO  uint8_t ADDRESS3   : 1;
+  __IO  uint8_t ADDRESS4   : 1;
+  __IO  uint8_t ADDRESS5   : 1;
+  __IO  uint8_t ADDRESS6   : 1;
+} stc_usb_hadr_field_t;
+
+typedef struct stc_usb_heof_field
+{
+  __IO uint16_t EOF0       : 1;
+  __IO uint16_t EOF1       : 1;
+  __IO uint16_t EOF2       : 1;
+  __IO uint16_t EOF3       : 1;
+  __IO uint16_t EOF4       : 1;
+  __IO uint16_t EOF5       : 1;
+  __IO uint16_t EOF6       : 1;
+  __IO uint16_t EOF7       : 1;
+  __IO uint16_t EOF8       : 1;
+  __IO uint16_t EOF9       : 1;
+  __IO uint16_t EOF10      : 1;
+  __IO uint16_t EOF11      : 1;
+  __IO uint16_t EOF12      : 1;
+  __IO uint16_t EOF13      : 1;
+  __IO uint16_t EOF14      : 1;
+  __IO uint16_t EOF15      : 1;
+} stc_usb_heof_field_t;
+
+typedef struct stc_usb_heof0_field
+{
+  __IO  uint8_t EOF00      : 1;
+  __IO  uint8_t EOF01      : 1;
+  __IO  uint8_t EOF02      : 1;
+  __IO  uint8_t EOF03      : 1;
+  __IO  uint8_t EOF04      : 1;
+  __IO  uint8_t EOF05      : 1;
+  __IO  uint8_t EOF06      : 1;
+  __IO  uint8_t EOF07      : 1;
+} stc_usb_heof0_field_t;
+
+typedef struct stc_usb_heof1_field
+{
+  __IO  uint8_t EOF10      : 1;
+  __IO  uint8_t EOF11      : 1;
+  __IO  uint8_t EOF12      : 1;
+  __IO  uint8_t EOF13      : 1;
+  __IO  uint8_t EOF14      : 1;
+  __IO  uint8_t EOF15      : 1;
+} stc_usb_heof1_field_t;
+
+typedef struct stc_usb_hframe_field
+{
+  __IO uint16_t FRAME0     : 1;
+  __IO uint16_t FRAME1     : 1;
+  __IO uint16_t FRAME2     : 1;
+  __IO uint16_t FRAME3     : 1;
+  __IO uint16_t FRAME4     : 1;
+  __IO uint16_t FRAME5     : 1;
+  __IO uint16_t FRAME6     : 1;
+  __IO uint16_t FRAME7     : 1;
+  __IO uint16_t FRAME8     : 1;
+  __IO uint16_t FRAME9     : 1;
+  __IO uint16_t FRAME10    : 1;
+} stc_usb_hframe_field_t;
+
+typedef struct stc_usb_hframe0_field
+{
+  __IO  uint8_t FRAME00    : 1;
+  __IO  uint8_t FRAME01    : 1;
+  __IO  uint8_t FRAME02    : 1;
+  __IO  uint8_t FRAME03    : 1;
+  __IO  uint8_t FRAME04    : 1;
+  __IO  uint8_t FRAME05    : 1;
+  __IO  uint8_t FRAME06    : 1;
+  __IO  uint8_t FRAME07    : 1;
+} stc_usb_hframe0_field_t;
+
+typedef struct stc_usb_hframe1_field
+{
+  __IO  uint8_t FRAME10    : 1;
+  __IO  uint8_t FRAME11    : 1;
+  __IO  uint8_t FRAME12    : 1;
+  __IO  uint8_t FRAME13    : 1;
+} stc_usb_hframe1_field_t;
+
+typedef struct stc_usb_htoken_field
+{
+  __IO  uint8_t ENDPT0     : 1;
+  __IO  uint8_t ENDPT1     : 1;
+  __IO  uint8_t ENDPT2     : 1;
+  __IO  uint8_t ENDPT3     : 1;
+  __IO  uint8_t TKNEN0     : 1;
+  __IO  uint8_t TKNEN1     : 1;
+  __IO  uint8_t TKNEN2     : 1;
+  __IO  uint8_t TGGL       : 1;
+} stc_usb_htoken_field_t;
+
+typedef struct stc_usb_udcc_field
+{
+  __IO uint16_t PWC        : 1;
+  __IO uint16_t RFBK       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t STALCLREN  : 1;
+  __IO uint16_t USTP       : 1;
+  __IO uint16_t HCONX      : 1;
+  __IO uint16_t RESUM      : 1;
+  __IO uint16_t RST        : 1;
+} stc_usb_udcc_field_t;
+
+typedef struct stc_usb_ep0c_field
+{
+  __IO uint16_t PKS00      : 1;
+  __IO uint16_t PKS01      : 1;
+  __IO uint16_t PKS02      : 1;
+  __IO uint16_t PKS03      : 1;
+  __IO uint16_t PKS04      : 1;
+  __IO uint16_t PKS05      : 1;
+  __IO uint16_t PKS06      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+} stc_usb_ep0c_field_t;
+
+typedef struct stc_usb_ep1c_field
+{
+  __IO uint16_t PKS10      : 1;
+  __IO uint16_t PKS11      : 1;
+  __IO uint16_t PKS12      : 1;
+  __IO uint16_t PKS13      : 1;
+  __IO uint16_t PKS14      : 1;
+  __IO uint16_t PKS15      : 1;
+  __IO uint16_t PKS16      : 1;
+  __IO uint16_t PKS17      : 1;
+  __IO uint16_t PKS18      : 1;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep1c_field_t;
+
+typedef struct stc_usb_ep2c_field
+{
+  __IO uint16_t PKS20      : 1;
+  __IO uint16_t PKS21      : 1;
+  __IO uint16_t PKS22      : 1;
+  __IO uint16_t PKS23      : 1;
+  __IO uint16_t PKS24      : 1;
+  __IO uint16_t PKS25      : 1;
+  __IO uint16_t PKS26      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep2c_field_t;
+
+typedef struct stc_usb_ep3c_field
+{
+  __IO uint16_t PKS30      : 1;
+  __IO uint16_t PKS31      : 1;
+  __IO uint16_t PKS32      : 1;
+  __IO uint16_t PKS33      : 1;
+  __IO uint16_t PKS34      : 1;
+  __IO uint16_t PKS35      : 1;
+  __IO uint16_t PKS36      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep3c_field_t;
+
+typedef struct stc_usb_ep4c_field
+{
+  __IO uint16_t PKS40      : 1;
+  __IO uint16_t PKS41      : 1;
+  __IO uint16_t PKS42      : 1;
+  __IO uint16_t PKS43      : 1;
+  __IO uint16_t PKS44      : 1;
+  __IO uint16_t PKS45      : 1;
+  __IO uint16_t PKS46      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep4c_field_t;
+
+typedef struct stc_usb_ep5c_field
+{
+  __IO uint16_t PKS50      : 1;
+  __IO uint16_t PKS51      : 1;
+  __IO uint16_t PKS52      : 1;
+  __IO uint16_t PKS53      : 1;
+  __IO uint16_t PKS54      : 1;
+  __IO uint16_t PKS55      : 1;
+  __IO uint16_t PKS56      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t STAL       : 1;
+  __IO uint16_t NULE       : 1;
+  __IO uint16_t DMAE       : 1;
+  __IO uint16_t DIR        : 1;
+  __IO uint16_t TYPE0      : 1;
+  __IO uint16_t TYPE1      : 1;
+  __IO uint16_t EPEN       : 1;
+} stc_usb_ep5c_field_t;
+
+typedef struct stc_usb_tmsp_field
+{
+  __IO uint16_t TMSP0      : 1;
+  __IO uint16_t TMSP1      : 1;
+  __IO uint16_t TMSP2      : 1;
+  __IO uint16_t TMSP3      : 1;
+  __IO uint16_t TMSP4      : 1;
+  __IO uint16_t TMSP5      : 1;
+  __IO uint16_t TMSP6      : 1;
+  __IO uint16_t TMSP7      : 1;
+  __IO uint16_t TMSP8      : 1;
+  __IO uint16_t TMSP9      : 1;
+  __IO uint16_t TMSP10     : 1;
+} stc_usb_tmsp_field_t;
+
+typedef struct stc_usb_udcs_field
+{
+  __IO  uint8_t CONF       : 1;
+  __IO  uint8_t SETP       : 1;
+  __IO  uint8_t WKUP       : 1;
+  __IO  uint8_t BRST       : 1;
+  __IO  uint8_t SOF        : 1;
+  __IO  uint8_t SUSP       : 1;
+} stc_usb_udcs_field_t;
+
+typedef struct stc_usb_udcie_field
+{
+  __IO  uint8_t CONFIE     : 1;
+  __IO  uint8_t CONFN      : 1;
+  __IO  uint8_t WKUPIE     : 1;
+  __IO  uint8_t BRSTIE     : 1;
+  __IO  uint8_t SOFIE      : 1;
+  __IO  uint8_t SUSPIE     : 1;
+} stc_usb_udcie_field_t;
+
+typedef struct stc_usb_ep0is_field
+{
+       uint16_t RESERVED1  : 10;
+  __IO uint16_t DRQI       : 1;
+       uint16_t RESERVED2  : 3;
+  __IO uint16_t DRQIIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0is_field_t;
+
+typedef struct stc_usb_ep0os_field
+{
+  __IO uint16_t SIZE0      : 1;
+  __IO uint16_t SIZE1      : 1;
+  __IO uint16_t SIZE2      : 1;
+  __IO uint16_t SIZE3      : 1;
+  __IO uint16_t SIZE4      : 1;
+  __IO uint16_t SIZE5      : 1;
+  __IO uint16_t SIZE6      : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQO       : 1;
+       uint16_t RESERVED2  : 2;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQOIE     : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep0os_field_t;
+
+typedef struct stc_usb_ep1s_field
+{
+  __IO uint16_t SIZE10     : 1;
+  __IO uint16_t SIZE11     : 1;
+  __IO uint16_t SIZE12     : 1;
+  __IO uint16_t SIZE13     : 1;
+  __IO uint16_t SIZE14     : 1;
+  __IO uint16_t SIZE15     : 1;
+  __IO uint16_t SIZE16     : 1;
+  __IO uint16_t SIZE17     : 1;
+  __IO uint16_t SIZE18     : 1;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED1  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep1s_field_t;
+
+typedef struct stc_usb_ep2s_field
+{
+  __IO uint16_t SIZE20     : 1;
+  __IO uint16_t SIZE21     : 1;
+  __IO uint16_t SIZE22     : 1;
+  __IO uint16_t SIZE23     : 1;
+  __IO uint16_t SIZE24     : 1;
+  __IO uint16_t SIZE25     : 1;
+  __IO uint16_t SIZE26     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep2s_field_t;
+
+typedef struct stc_usb_ep4s_field
+{
+  __IO uint16_t SIZE40     : 1;
+  __IO uint16_t SIZE41     : 1;
+  __IO uint16_t SIZE42     : 1;
+  __IO uint16_t SIZE43     : 1;
+  __IO uint16_t SIZE44     : 1;
+  __IO uint16_t SIZE45     : 1;
+  __IO uint16_t SIZE46     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep4s_field_t;
+
+typedef struct stc_usb_ep5s_field
+{
+  __IO uint16_t SIZE50     : 1;
+  __IO uint16_t SIZE51     : 1;
+  __IO uint16_t SIZE52     : 1;
+  __IO uint16_t SIZE53     : 1;
+  __IO uint16_t SIZE54     : 1;
+  __IO uint16_t SIZE55     : 1;
+  __IO uint16_t SIZE56     : 1;
+       uint16_t RESERVED1  : 2;
+  __IO uint16_t SPK        : 1;
+  __IO uint16_t DRQ        : 1;
+  __IO uint16_t BUSY       : 1;
+       uint16_t RESERVED2  : 1;
+  __IO uint16_t SPKIE      : 1;
+  __IO uint16_t DRQIE      : 1;
+  __IO uint16_t BFINI      : 1;
+} stc_usb_ep5s_field_t;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMAC_MODULE register bit fields */
+typedef struct stc_dmac_dmacr_field
+{
+       uint32_t RESERVED1  : 24;
+  __IO uint32_t DH0        : 1;
+  __IO uint32_t DH1        : 1;
+  __IO uint32_t DH2        : 1;
+  __IO uint32_t DH3        : 1;
+  __IO uint32_t PR         : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t DS         : 1;
+  __IO uint32_t DE         : 1;
+} stc_dmac_dmacr_field_t;
+
+typedef struct stc_dmac_dmaca0_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca0_field_t;
+
+typedef struct stc_dmac_dmacb0_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb0_field_t;
+
+typedef struct stc_dmac_dmaca1_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca1_field_t;
+
+typedef struct stc_dmac_dmacb1_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb1_field_t;
+
+typedef struct stc_dmac_dmaca2_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca2_field_t;
+
+typedef struct stc_dmac_dmacb2_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb2_field_t;
+
+typedef struct stc_dmac_dmaca3_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca3_field_t;
+
+typedef struct stc_dmac_dmacb3_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb3_field_t;
+
+typedef struct stc_dmac_dmaca4_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca4_field_t;
+
+typedef struct stc_dmac_dmacb4_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb4_field_t;
+
+typedef struct stc_dmac_dmaca5_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca5_field_t;
+
+typedef struct stc_dmac_dmacb5_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb5_field_t;
+
+typedef struct stc_dmac_dmaca6_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca6_field_t;
+
+typedef struct stc_dmac_dmacb6_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb6_field_t;
+
+typedef struct stc_dmac_dmaca7_field
+{
+  __IO uint32_t TC0        : 1;
+  __IO uint32_t TC1        : 1;
+  __IO uint32_t TC2        : 1;
+  __IO uint32_t TC3        : 1;
+  __IO uint32_t TC4        : 1;
+  __IO uint32_t TC5        : 1;
+  __IO uint32_t TC6        : 1;
+  __IO uint32_t TC7        : 1;
+  __IO uint32_t TC8        : 1;
+  __IO uint32_t TC9        : 1;
+  __IO uint32_t TC10       : 1;
+  __IO uint32_t TC11       : 1;
+  __IO uint32_t TC12       : 1;
+  __IO uint32_t TC13       : 1;
+  __IO uint32_t TC14       : 1;
+  __IO uint32_t TC15       : 1;
+  __IO uint32_t BC0        : 1;
+  __IO uint32_t BC1        : 1;
+  __IO uint32_t BC2        : 1;
+  __IO uint32_t BC3        : 1;
+       uint32_t RESERVED1  : 3;
+  __IO uint32_t IS0        : 1;
+  __IO uint32_t IS1        : 1;
+  __IO uint32_t IS2        : 1;
+  __IO uint32_t IS3        : 1;
+  __IO uint32_t IS4        : 1;
+  __IO uint32_t IS5        : 1;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t PB         : 1;
+  __IO uint32_t EB         : 1;
+} stc_dmac_dmaca7_field_t;
+
+typedef struct stc_dmac_dmacb7_field
+{
+  __IO uint32_t EM         : 1;
+       uint32_t RESERVED1  : 15;
+  __IO uint32_t SS0        : 1;
+  __IO uint32_t SS1        : 1;
+  __IO uint32_t SS2        : 1;
+  __IO uint32_t CI         : 1;
+  __IO uint32_t EI         : 1;
+  __IO uint32_t RD         : 1;
+  __IO uint32_t RS         : 1;
+  __IO uint32_t RC         : 1;
+  __IO uint32_t FD         : 1;
+  __IO uint32_t FS         : 1;
+  __IO uint32_t TW0        : 1;
+  __IO uint32_t TW1        : 1;
+  __IO uint32_t MS0        : 1;
+  __IO uint32_t MS1        : 1;
+} stc_dmac_dmacb7_field_t;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET_MAC_MODULE register bit fields */
+typedef struct stc_ethernet_mac_mcr_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t RE         : 1;
+  __IO uint32_t TE         : 1;
+  __IO uint32_t DC         : 1;
+  __IO uint32_t BL0        : 1;
+  __IO uint32_t BL1        : 1;
+  __IO uint32_t ACS        : 1;
+  __IO uint32_t LUD        : 1;
+  __IO uint32_t DR         : 1;
+  __IO uint32_t IPC        : 1;
+  __IO uint32_t DM         : 1;
+  __IO uint32_t LM         : 1;
+  __IO uint32_t DO         : 1;
+  __IO uint32_t FES        : 1;
+  __IO uint32_t PS         : 1;
+  __IO uint32_t DCRS       : 1;
+  __IO uint32_t IFG0       : 1;
+  __IO uint32_t IFG1       : 1;
+  __IO uint32_t IFG2       : 1;
+  __IO uint32_t JE         : 1;
+  __IO uint32_t BE         : 1;
+  __IO uint32_t JD         : 1;
+  __IO uint32_t WD         : 1;
+  __IO uint32_t TC         : 1;
+  __IO uint32_t CST        : 1;
+} stc_ethernet_mac_mcr_field_t;
+
+typedef struct stc_ethernet_mac_mffr_field
+{
+  __IO uint32_t PR         : 1;
+  __IO uint32_t HUC        : 1;
+  __IO uint32_t HMC        : 1;
+  __IO uint32_t DAIF       : 1;
+  __IO uint32_t PM         : 1;
+  __IO uint32_t DB         : 1;
+  __IO uint32_t PCF0       : 1;
+  __IO uint32_t PCF1       : 1;
+  __IO uint32_t SAIF       : 1;
+  __IO uint32_t SAF        : 1;
+  __IO uint32_t HPF        : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t RA         : 1;
+} stc_ethernet_mac_mffr_field_t;
+
+typedef struct stc_ethernet_mac_mhtrh_field
+{
+  __IO uint32_t HTH0       : 1;
+  __IO uint32_t HTH1       : 1;
+  __IO uint32_t HTH2       : 1;
+  __IO uint32_t HTH3       : 1;
+  __IO uint32_t HTH4       : 1;
+  __IO uint32_t HTH5       : 1;
+  __IO uint32_t HTH6       : 1;
+  __IO uint32_t HTH7       : 1;
+  __IO uint32_t HTH8       : 1;
+  __IO uint32_t HTH9       : 1;
+  __IO uint32_t HTH10      : 1;
+  __IO uint32_t HTH11      : 1;
+  __IO uint32_t HTH12      : 1;
+  __IO uint32_t HTH13      : 1;
+  __IO uint32_t HTH14      : 1;
+  __IO uint32_t HTH15      : 1;
+  __IO uint32_t HTH16      : 1;
+  __IO uint32_t HTH17      : 1;
+  __IO uint32_t HTH18      : 1;
+  __IO uint32_t HTH19      : 1;
+  __IO uint32_t HTH20      : 1;
+  __IO uint32_t HTH21      : 1;
+  __IO uint32_t HTH22      : 1;
+  __IO uint32_t HTH23      : 1;
+  __IO uint32_t HTH24      : 1;
+  __IO uint32_t HTH25      : 1;
+  __IO uint32_t HTH26      : 1;
+  __IO uint32_t HTH27      : 1;
+  __IO uint32_t HTH28      : 1;
+  __IO uint32_t HTH29      : 1;
+  __IO uint32_t HTH30      : 1;
+  __IO uint32_t HTH31      : 1;
+} stc_ethernet_mac_mhtrh_field_t;
+
+typedef struct stc_ethernet_mac_mhtrl_field
+{
+  __IO uint32_t HTL0       : 1;
+  __IO uint32_t HTL1       : 1;
+  __IO uint32_t HTL2       : 1;
+  __IO uint32_t HTL3       : 1;
+  __IO uint32_t HTL4       : 1;
+  __IO uint32_t HTL5       : 1;
+  __IO uint32_t HTL6       : 1;
+  __IO uint32_t HTL7       : 1;
+  __IO uint32_t HTL8       : 1;
+  __IO uint32_t HTL9       : 1;
+  __IO uint32_t HTL10      : 1;
+  __IO uint32_t HTL11      : 1;
+  __IO uint32_t HTL12      : 1;
+  __IO uint32_t HTL13      : 1;
+  __IO uint32_t HTL14      : 1;
+  __IO uint32_t HTL15      : 1;
+  __IO uint32_t HTL16      : 1;
+  __IO uint32_t HTL17      : 1;
+  __IO uint32_t HTL18      : 1;
+  __IO uint32_t HTL19      : 1;
+  __IO uint32_t HTL20      : 1;
+  __IO uint32_t HTL21      : 1;
+  __IO uint32_t HTL22      : 1;
+  __IO uint32_t HTL23      : 1;
+  __IO uint32_t HTL24      : 1;
+  __IO uint32_t HTL25      : 1;
+  __IO uint32_t HTL26      : 1;
+  __IO uint32_t HTL27      : 1;
+  __IO uint32_t HTL28      : 1;
+  __IO uint32_t HTL29      : 1;
+  __IO uint32_t HTL30      : 1;
+  __IO uint32_t HTL31      : 1;
+} stc_ethernet_mac_mhtrl_field_t;
+
+typedef struct stc_ethernet_mac_gar_field
+{
+  __IO uint32_t GB         : 1;
+  __IO uint32_t GW         : 1;
+  __IO uint32_t CR0        : 1;
+  __IO uint32_t CR1        : 1;
+  __IO uint32_t CR2        : 1;
+  __IO uint32_t CR3        : 1;
+  __IO uint32_t GR0        : 1;
+  __IO uint32_t GR1        : 1;
+  __IO uint32_t GR2        : 1;
+  __IO uint32_t GR3        : 1;
+  __IO uint32_t GR4        : 1;
+  __IO uint32_t PA0        : 1;
+  __IO uint32_t PA1        : 1;
+  __IO uint32_t PA2        : 1;
+  __IO uint32_t PA3        : 1;
+  __IO uint32_t PA4        : 1;
+} stc_ethernet_mac_gar_field_t;
+
+typedef struct stc_ethernet_mac_gdr_field
+{
+  __IO uint32_t GD0        : 1;
+  __IO uint32_t GD1        : 1;
+  __IO uint32_t GD2        : 1;
+  __IO uint32_t GD3        : 1;
+  __IO uint32_t GD4        : 1;
+  __IO uint32_t GD5        : 1;
+  __IO uint32_t GD6        : 1;
+  __IO uint32_t GD7        : 1;
+  __IO uint32_t GD8        : 1;
+  __IO uint32_t GD9        : 1;
+  __IO uint32_t GD10       : 1;
+  __IO uint32_t GD11       : 1;
+  __IO uint32_t GD12       : 1;
+  __IO uint32_t GD13       : 1;
+  __IO uint32_t GD14       : 1;
+  __IO uint32_t GD15       : 1;
+} stc_ethernet_mac_gdr_field_t;
+
+typedef struct stc_ethernet_mac_fcr_field
+{
+  __IO uint32_t FCB_BPA    : 1;
+  __IO uint32_t TFE        : 1;
+  __IO uint32_t RFE        : 1;
+  __IO uint32_t UP         : 1;
+  __IO uint32_t PLT0       : 1;
+  __IO uint32_t PLT1       : 1;
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t DZPQ       : 1;
+       uint32_t RESERVED2  : 8;
+  __IO uint32_t PT0        : 1;
+  __IO uint32_t PT1        : 1;
+  __IO uint32_t PT2        : 1;
+  __IO uint32_t PT3        : 1;
+  __IO uint32_t PT4        : 1;
+  __IO uint32_t PT5        : 1;
+  __IO uint32_t PT6        : 1;
+  __IO uint32_t PT7        : 1;
+  __IO uint32_t PT8        : 1;
+  __IO uint32_t PT9        : 1;
+  __IO uint32_t PT10       : 1;
+  __IO uint32_t PT11       : 1;
+  __IO uint32_t PT12       : 1;
+  __IO uint32_t PT13       : 1;
+  __IO uint32_t PT14       : 1;
+  __IO uint32_t PT15       : 1;
+} stc_ethernet_mac_fcr_field_t;
+
+typedef struct stc_ethernet_mac_vtr_field
+{
+  __IO uint32_t VL0        : 1;
+  __IO uint32_t VL1        : 1;
+  __IO uint32_t VL2        : 1;
+  __IO uint32_t VL3        : 1;
+  __IO uint32_t VL4        : 1;
+  __IO uint32_t VL5        : 1;
+  __IO uint32_t VL6        : 1;
+  __IO uint32_t VL7        : 1;
+  __IO uint32_t VL8        : 1;
+  __IO uint32_t VL9        : 1;
+  __IO uint32_t VL10       : 1;
+  __IO uint32_t VL11       : 1;
+  __IO uint32_t VL12       : 1;
+  __IO uint32_t VL13       : 1;
+  __IO uint32_t VL14       : 1;
+  __IO uint32_t VL15       : 1;
+  __IO uint32_t ETV        : 1;
+} stc_ethernet_mac_vtr_field_t;
+
+typedef struct stc_ethernet_mac_rwffr_field
+{
+  __IO uint32_t RWFFR0     : 1;
+  __IO uint32_t RWFFR1     : 1;
+  __IO uint32_t RWFFR2     : 1;
+  __IO uint32_t RWFFR3     : 1;
+  __IO uint32_t RWFFR4     : 1;
+  __IO uint32_t RWFFR5     : 1;
+  __IO uint32_t RWFFR6     : 1;
+  __IO uint32_t RWFFR7     : 1;
+  __IO uint32_t RWFFR8     : 1;
+  __IO uint32_t RWFFR9     : 1;
+  __IO uint32_t RWFFR10    : 1;
+  __IO uint32_t RWFFR11    : 1;
+  __IO uint32_t RWFFR12    : 1;
+  __IO uint32_t RWFFR13    : 1;
+  __IO uint32_t RWFFR14    : 1;
+  __IO uint32_t RWFFR15    : 1;
+  __IO uint32_t RWFFR16    : 1;
+  __IO uint32_t RWFFR17    : 1;
+  __IO uint32_t RWFFR18    : 1;
+  __IO uint32_t RWFFR19    : 1;
+  __IO uint32_t RWFFR20    : 1;
+  __IO uint32_t RWFFR21    : 1;
+  __IO uint32_t RWFFR22    : 1;
+  __IO uint32_t RWFFR23    : 1;
+  __IO uint32_t RWFFR24    : 1;
+  __IO uint32_t RWFFR25    : 1;
+  __IO uint32_t RWFFR26    : 1;
+  __IO uint32_t RWFFR27    : 1;
+  __IO uint32_t RWFFR28    : 1;
+  __IO uint32_t RWFFR29    : 1;
+  __IO uint32_t RWFFR30    : 1;
+  __IO uint32_t RWFFR31    : 1;
+} stc_ethernet_mac_rwffr_field_t;
+
+typedef struct stc_ethernet_mac_pmtr_field
+{
+  __IO uint32_t PD         : 1;
+  __IO uint32_t MPE        : 1;
+  __IO uint32_t WFE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t MPR        : 1;
+  __IO uint32_t WPR        : 1;
+       uint32_t RESERVED2  : 2;
+  __IO uint32_t GU         : 1;
+       uint32_t RESERVED3  :21;
+  __IO uint32_t RWFFRPR    : 1;
+} stc_ethernet_mac_pmtr_field_t;
+
+typedef struct stc_ethernet_mac_lpicsr_field
+{
+  __IO uint32_t TLPIEN     : 1;
+  __IO uint32_t TLPIEX     : 1;
+  __IO uint32_t RLPIEN     : 1;
+  __IO uint32_t RLPIEX     : 1;
+       uint32_t RESERVED1  : 4;
+  __IO uint32_t TLPIST     : 1;
+  __IO uint32_t RLPIST     : 1;
+       uint32_t RESERVED2  : 6;
+  __IO uint32_t LPIEN      : 1;
+  __IO uint32_t PLS        : 1;
+  __IO uint32_t PLSEN      : 1;
+  __IO uint32_t LPITXA     : 1;
+} stc_ethernet_mac_lpicsr_field_t;
+
+typedef struct stc_ethernet_mac_lpitcr_field
+{
+  __IO uint32_t TWT0       : 1;
+  __IO uint32_t TWT1       : 1;
+  __IO uint32_t TWT2       : 1;
+  __IO uint32_t TWT3       : 1;
+  __IO uint32_t TWT4       : 1;
+  __IO uint32_t TWT5       : 1;
+  __IO uint32_t TWT6       : 1;
+  __IO uint32_t TWT7       : 1;
+  __IO uint32_t TWT8       : 1;
+  __IO uint32_t TWT9       : 1;
+  __IO uint32_t TWT10      : 1;
+  __IO uint32_t TWT11      : 1;
+  __IO uint32_t TWT12      : 1;
+  __IO uint32_t TWT13      : 1;
+  __IO uint32_t TWT14      : 1;
+  __IO uint32_t TWT15      : 1;
+  __IO uint32_t LIT0       : 1;
+  __IO uint32_t LIT1       : 1;
+  __IO uint32_t LIT2       : 1;
+  __IO uint32_t LIT3       : 1;
+  __IO uint32_t LIT4       : 1;
+  __IO uint32_t LIT5       : 1;
+  __IO uint32_t LIT6       : 1;
+  __IO uint32_t LIT7       : 1;
+  __IO uint32_t LIT8       : 1;
+  __IO uint32_t LIT9       : 1;
+} stc_ethernet_mac_lpitcr_field_t;
+
+typedef struct stc_ethernet_mac_isr_field
+{
+  __IO uint32_t RGIS       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIS        : 1;
+  __IO uint32_t MIS        : 1;
+  __IO uint32_t RIS        : 1;
+  __IO uint32_t TIS        : 1;
+  __IO uint32_t COIS       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t TSIS       : 1;
+  __IO uint32_t LPIIS      : 1;
+} stc_ethernet_mac_isr_field_t;
+
+typedef struct stc_ethernet_mac_imr_field
+{
+  __IO uint32_t RGIM       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t PIM        : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t TSIM       : 1;
+  __IO uint32_t LPIIM      : 1;
+} stc_ethernet_mac_imr_field_t;
+
+typedef struct stc_ethernet_mac_mar0h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  :15;
+  __IO uint32_t MO         : 1;
+} stc_ethernet_mac_mar0h_field_t;
+
+typedef struct stc_ethernet_mac_mar0l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar0l_field_t;
+
+typedef struct stc_ethernet_mac_mar1h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar1h_field_t;
+
+typedef struct stc_ethernet_mac_mar1l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar1l_field_t;
+
+typedef struct stc_ethernet_mac_mar2h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar2h_field_t;
+
+typedef struct stc_ethernet_mac_mar2l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar2l_field_t;
+
+typedef struct stc_ethernet_mac_mar3h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar3h_field_t;
+
+typedef struct stc_ethernet_mac_mar3l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar3l_field_t;
+
+typedef struct stc_ethernet_mac_mar4h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar4h_field_t;
+
+typedef struct stc_ethernet_mac_mar4l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar4l_field_t;
+
+typedef struct stc_ethernet_mac_mar5h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar5h_field_t;
+
+typedef struct stc_ethernet_mac_mar5l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar5l_field_t;
+
+typedef struct stc_ethernet_mac_mar6h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar6h_field_t;
+
+typedef struct stc_ethernet_mac_mar6l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar6l_field_t;
+
+typedef struct stc_ethernet_mac_mar7h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar7h_field_t;
+
+typedef struct stc_ethernet_mac_mar7l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar7l_field_t;
+
+typedef struct stc_ethernet_mac_mar8h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar8h_field_t;
+
+typedef struct stc_ethernet_mac_mar8l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar8l_field_t;
+
+typedef struct stc_ethernet_mac_mar9h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar9h_field_t;
+
+typedef struct stc_ethernet_mac_mar9l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar9l_field_t;
+
+typedef struct stc_ethernet_mac_mar10h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar10h_field_t;
+
+typedef struct stc_ethernet_mac_mar10l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar10l_field_t;
+
+typedef struct stc_ethernet_mac_mar11h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar11h_field_t;
+
+typedef struct stc_ethernet_mac_mar11l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar11l_field_t;
+
+typedef struct stc_ethernet_mac_mar12h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar12h_field_t;
+
+typedef struct stc_ethernet_mac_mar12l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar12l_field_t;
+
+typedef struct stc_ethernet_mac_mar13h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar13h_field_t;
+
+typedef struct stc_ethernet_mac_mar13l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar13l_field_t;
+
+typedef struct stc_ethernet_mac_mar14h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar14h_field_t;
+
+typedef struct stc_ethernet_mac_mar14l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar14l_field_t;
+
+typedef struct stc_ethernet_mac_mar15h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar15h_field_t;
+
+typedef struct stc_ethernet_mac_mar15l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar15l_field_t;
+
+typedef struct stc_ethernet_mac_rgsr_field
+{
+  __IO uint32_t LM         : 1;
+  __IO uint32_t LSP0       : 1;
+  __IO uint32_t LSP1       : 1;
+  __IO uint32_t LS         : 1;
+} stc_ethernet_mac_rgsr_field_t;
+
+typedef struct stc_ethernet_mac_tscr_field
+{
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TFCU       : 1;
+  __IO uint32_t TSI        : 1;
+  __IO uint32_t TSU        : 1;
+  __IO uint32_t TITE       : 1;
+  __IO uint32_t TARU       : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t TSEA       : 1;
+  __IO uint32_t TSDB       : 1;
+  __IO uint32_t TSV2E      : 1;
+  __IO uint32_t TETSP      : 1;
+  __IO uint32_t TSIP6E     : 1;
+  __IO uint32_t TSIP4E     : 1;
+  __IO uint32_t TETSEM     : 1;
+  __IO uint32_t TSMRM      : 1;
+  __IO uint32_t TSPS0      : 1;
+  __IO uint32_t TSPS1      : 1;
+  __IO uint32_t TSENMF     : 1;
+       uint32_t RESERVED2  : 5;
+  __IO uint32_t ATSFC      : 1;
+} stc_ethernet_mac_tscr_field_t;
+
+typedef struct stc_ethernet_mac_ssir_field
+{
+  __IO uint32_t SSINC0     : 1;
+  __IO uint32_t SSINC1     : 1;
+  __IO uint32_t SSINC2     : 1;
+  __IO uint32_t SSINC3     : 1;
+  __IO uint32_t SSINC4     : 1;
+  __IO uint32_t SSINC5     : 1;
+  __IO uint32_t SSINC6     : 1;
+  __IO uint32_t SSINC7     : 1;
+} stc_ethernet_mac_ssir_field_t;
+
+typedef struct stc_ethernet_mac_stsr_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsr_field_t;
+
+typedef struct stc_ethernet_mac_stnr_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+} stc_ethernet_mac_stnr_field_t;
+
+typedef struct stc_ethernet_mac_stsur_field
+{
+  __IO uint32_t TSS0       : 1;
+  __IO uint32_t TSS1       : 1;
+  __IO uint32_t TSS2       : 1;
+  __IO uint32_t TSS3       : 1;
+  __IO uint32_t TSS4       : 1;
+  __IO uint32_t TSS5       : 1;
+  __IO uint32_t TSS6       : 1;
+  __IO uint32_t TSS7       : 1;
+  __IO uint32_t TSS8       : 1;
+  __IO uint32_t TSS9       : 1;
+  __IO uint32_t TSS10      : 1;
+  __IO uint32_t TSS11      : 1;
+  __IO uint32_t TSS12      : 1;
+  __IO uint32_t TSS13      : 1;
+  __IO uint32_t TSS14      : 1;
+  __IO uint32_t TSS15      : 1;
+  __IO uint32_t TSS16      : 1;
+  __IO uint32_t TSS17      : 1;
+  __IO uint32_t TSS18      : 1;
+  __IO uint32_t TSS19      : 1;
+  __IO uint32_t TSS20      : 1;
+  __IO uint32_t TSS21      : 1;
+  __IO uint32_t TSS22      : 1;
+  __IO uint32_t TSS23      : 1;
+  __IO uint32_t TSS24      : 1;
+  __IO uint32_t TSS25      : 1;
+  __IO uint32_t TSS26      : 1;
+  __IO uint32_t TSS27      : 1;
+  __IO uint32_t TSS28      : 1;
+  __IO uint32_t TSS29      : 1;
+  __IO uint32_t TSS30      : 1;
+  __IO uint32_t TSS31      : 1;
+} stc_ethernet_mac_stsur_field_t;
+
+typedef struct stc_ethernet_mac_stnur_field
+{
+  __IO uint32_t TSSS0      : 1;
+  __IO uint32_t TSSS1      : 1;
+  __IO uint32_t TSSS2      : 1;
+  __IO uint32_t TSSS3      : 1;
+  __IO uint32_t TSSS4      : 1;
+  __IO uint32_t TSSS5      : 1;
+  __IO uint32_t TSSS6      : 1;
+  __IO uint32_t TSSS7      : 1;
+  __IO uint32_t TSSS8      : 1;
+  __IO uint32_t TSSS9      : 1;
+  __IO uint32_t TSSS10     : 1;
+  __IO uint32_t TSSS11     : 1;
+  __IO uint32_t TSSS12     : 1;
+  __IO uint32_t TSSS13     : 1;
+  __IO uint32_t TSSS14     : 1;
+  __IO uint32_t TSSS15     : 1;
+  __IO uint32_t TSSS16     : 1;
+  __IO uint32_t TSSS17     : 1;
+  __IO uint32_t TSSS18     : 1;
+  __IO uint32_t TSSS19     : 1;
+  __IO uint32_t TSSS20     : 1;
+  __IO uint32_t TSSS21     : 1;
+  __IO uint32_t TSSS22     : 1;
+  __IO uint32_t TSSS23     : 1;
+  __IO uint32_t TSSS24     : 1;
+  __IO uint32_t TSSS25     : 1;
+  __IO uint32_t TSSS26     : 1;
+  __IO uint32_t TSSS27     : 1;
+  __IO uint32_t TSSS28     : 1;
+  __IO uint32_t TSSS29     : 1;
+  __IO uint32_t TSSS30     : 1;
+  __IO uint32_t ADDSUB     : 1;
+} stc_ethernet_mac_stnur_field_t;
+
+typedef struct stc_ethernet_mac_tsar_field
+{
+  __IO uint32_t TSAR0      : 1;
+  __IO uint32_t TSAR1      : 1;
+  __IO uint32_t TSAR2      : 1;
+  __IO uint32_t TSAR3      : 1;
+  __IO uint32_t TSAR4      : 1;
+  __IO uint32_t TSAR5      : 1;
+  __IO uint32_t TSAR6      : 1;
+  __IO uint32_t TSAR7      : 1;
+  __IO uint32_t TSAR8      : 1;
+  __IO uint32_t TSAR9      : 1;
+  __IO uint32_t TSAR10     : 1;
+  __IO uint32_t TSAR11     : 1;
+  __IO uint32_t TSAR12     : 1;
+  __IO uint32_t TSAR13     : 1;
+  __IO uint32_t TSAR14     : 1;
+  __IO uint32_t TSAR15     : 1;
+  __IO uint32_t TSAR16     : 1;
+  __IO uint32_t TSAR17     : 1;
+  __IO uint32_t TSAR18     : 1;
+  __IO uint32_t TSAR19     : 1;
+  __IO uint32_t TSAR20     : 1;
+  __IO uint32_t TSAR21     : 1;
+  __IO uint32_t TSAR22     : 1;
+  __IO uint32_t TSAR23     : 1;
+  __IO uint32_t TSAR24     : 1;
+  __IO uint32_t TSAR25     : 1;
+  __IO uint32_t TSAR26     : 1;
+  __IO uint32_t TSAR27     : 1;
+  __IO uint32_t TSAR28     : 1;
+  __IO uint32_t TSAR29     : 1;
+  __IO uint32_t TSAR30     : 1;
+  __IO uint32_t TSAR31     : 1;
+} stc_ethernet_mac_tsar_field_t;
+
+typedef struct stc_ethernet_mac_ttsr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+  __IO uint32_t TSTR31     : 1;
+} stc_ethernet_mac_ttsr_field_t;
+
+typedef struct stc_ethernet_mac_ttnr_field
+{
+  __IO uint32_t TSTR0      : 1;
+  __IO uint32_t TSTR1      : 1;
+  __IO uint32_t TSTR2      : 1;
+  __IO uint32_t TSTR3      : 1;
+  __IO uint32_t TSTR4      : 1;
+  __IO uint32_t TSTR5      : 1;
+  __IO uint32_t TSTR6      : 1;
+  __IO uint32_t TSTR7      : 1;
+  __IO uint32_t TSTR8      : 1;
+  __IO uint32_t TSTR9      : 1;
+  __IO uint32_t TSTR10     : 1;
+  __IO uint32_t TSTR11     : 1;
+  __IO uint32_t TSTR12     : 1;
+  __IO uint32_t TSTR13     : 1;
+  __IO uint32_t TSTR14     : 1;
+  __IO uint32_t TSTR15     : 1;
+  __IO uint32_t TSTR16     : 1;
+  __IO uint32_t TSTR17     : 1;
+  __IO uint32_t TSTR18     : 1;
+  __IO uint32_t TSTR19     : 1;
+  __IO uint32_t TSTR20     : 1;
+  __IO uint32_t TSTR21     : 1;
+  __IO uint32_t TSTR22     : 1;
+  __IO uint32_t TSTR23     : 1;
+  __IO uint32_t TSTR24     : 1;
+  __IO uint32_t TSTR25     : 1;
+  __IO uint32_t TSTR26     : 1;
+  __IO uint32_t TSTR27     : 1;
+  __IO uint32_t TSTR28     : 1;
+  __IO uint32_t TSTR29     : 1;
+  __IO uint32_t TSTR30     : 1;
+} stc_ethernet_mac_ttnr_field_t;
+
+typedef struct stc_ethernet_mac_sthwsr_field
+{
+  __IO uint32_t TSHWR0     : 1;
+  __IO uint32_t TSHWR1     : 1;
+  __IO uint32_t TSHWR2     : 1;
+  __IO uint32_t TSHWR3     : 1;
+  __IO uint32_t TSHWR4     : 1;
+  __IO uint32_t TSHWR5     : 1;
+  __IO uint32_t TSHWR6     : 1;
+  __IO uint32_t TSHWR7     : 1;
+  __IO uint32_t TSHWR8     : 1;
+  __IO uint32_t TSHWR9     : 1;
+  __IO uint32_t TSHWR10    : 1;
+  __IO uint32_t TSHWR11    : 1;
+  __IO uint32_t TSHWR12    : 1;
+  __IO uint32_t TSHWR13    : 1;
+  __IO uint32_t TSHWR14    : 1;
+  __IO uint32_t TSHWR15    : 1;
+} stc_ethernet_mac_sthwsr_field_t;
+
+typedef struct stc_ethernet_mac_tsr_field
+{
+  __IO uint32_t TSSOVF     : 1;
+  __IO uint32_t TSTART     : 1;
+  __IO uint32_t ATSTS      : 1;
+  __IO uint32_t TRGTER     : 1;
+       uint32_t RESERVED1  :20;
+  __IO uint32_t ATSSTM     : 1;
+  __IO uint32_t ATSNS0     : 1;
+  __IO uint32_t ATSNS1     : 1;
+  __IO uint32_t ATSNS2     : 1;
+} stc_ethernet_mac_tsr_field_t;
+
+typedef struct stc_ethernet_mac_ppscr_field
+{
+  __IO uint32_t PPSCTRL0   : 1;
+  __IO uint32_t PPSCTRL1   : 1;
+  __IO uint32_t PPSCTRL2   : 1;
+  __IO uint32_t PPSCTRL3   : 1;
+} stc_ethernet_mac_ppscr_field_t;
+
+typedef struct stc_ethernet_mac_atnr_field
+{
+  __IO uint32_t ATN0       : 1;
+  __IO uint32_t ATN1       : 1;
+  __IO uint32_t ATN2       : 1;
+  __IO uint32_t ATN3       : 1;
+  __IO uint32_t ATN4       : 1;
+  __IO uint32_t ATN5       : 1;
+  __IO uint32_t ATN6       : 1;
+  __IO uint32_t ATN7       : 1;
+  __IO uint32_t ATN8       : 1;
+  __IO uint32_t ATN9       : 1;
+  __IO uint32_t ATN10      : 1;
+  __IO uint32_t ATN11      : 1;
+  __IO uint32_t ATN12      : 1;
+  __IO uint32_t ATN13      : 1;
+  __IO uint32_t ATN14      : 1;
+  __IO uint32_t ATN15      : 1;
+  __IO uint32_t ATN16      : 1;
+  __IO uint32_t ATN17      : 1;
+  __IO uint32_t ATN18      : 1;
+  __IO uint32_t ATN19      : 1;
+  __IO uint32_t ATN20      : 1;
+  __IO uint32_t ATN21      : 1;
+  __IO uint32_t ATN22      : 1;
+  __IO uint32_t ATN23      : 1;
+  __IO uint32_t ATN24      : 1;
+  __IO uint32_t ATN25      : 1;
+  __IO uint32_t ATN26      : 1;
+  __IO uint32_t ATN27      : 1;
+  __IO uint32_t ATN28      : 1;
+  __IO uint32_t ATN29      : 1;
+  __IO uint32_t ATN30      : 1;
+} stc_ethernet_mac_atnr_field_t;
+
+typedef struct stc_ethernet_mac_atsr_field
+{
+  __IO uint32_t ATS0       : 1;
+  __IO uint32_t ATS1       : 1;
+  __IO uint32_t ATS2       : 1;
+  __IO uint32_t ATS3       : 1;
+  __IO uint32_t ATS4       : 1;
+  __IO uint32_t ATS5       : 1;
+  __IO uint32_t ATS6       : 1;
+  __IO uint32_t ATS7       : 1;
+  __IO uint32_t ATS8       : 1;
+  __IO uint32_t ATS9       : 1;
+  __IO uint32_t ATS10      : 1;
+  __IO uint32_t ATS11      : 1;
+  __IO uint32_t ATS12      : 1;
+  __IO uint32_t ATS13      : 1;
+  __IO uint32_t ATS14      : 1;
+  __IO uint32_t ATS15      : 1;
+  __IO uint32_t ATS16      : 1;
+  __IO uint32_t ATS17      : 1;
+  __IO uint32_t ATS18      : 1;
+  __IO uint32_t ATS19      : 1;
+  __IO uint32_t ATS20      : 1;
+  __IO uint32_t ATS21      : 1;
+  __IO uint32_t ATS22      : 1;
+  __IO uint32_t ATS23      : 1;
+  __IO uint32_t ATS24      : 1;
+  __IO uint32_t ATS25      : 1;
+  __IO uint32_t ATS26      : 1;
+  __IO uint32_t ATS27      : 1;
+  __IO uint32_t ATS28      : 1;
+  __IO uint32_t ATS29      : 1;
+  __IO uint32_t ATS30      : 1;
+  __IO uint32_t ATS31      : 1;
+} stc_ethernet_mac_atsr_field_t;
+
+typedef struct stc_ethernet_mac_mar16h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar16h_field_t;
+
+typedef struct stc_ethernet_mac_mar16l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar16l_field_t;
+
+typedef struct stc_ethernet_mac_mar17h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar17h_field_t;
+
+typedef struct stc_ethernet_mac_mar17l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar17l_field_t;
+
+typedef struct stc_ethernet_mac_mar18h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar18h_field_t;
+
+typedef struct stc_ethernet_mac_mar18l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar18l_field_t;
+
+typedef struct stc_ethernet_mac_mar19h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar19h_field_t;
+
+typedef struct stc_ethernet_mac_mar19l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar19l_field_t;
+
+typedef struct stc_ethernet_mac_mar20h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar20h_field_t;
+
+typedef struct stc_ethernet_mac_mar20l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar20l_field_t;
+
+typedef struct stc_ethernet_mac_mar21h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar21h_field_t;
+
+typedef struct stc_ethernet_mac_mar21l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar21l_field_t;
+
+typedef struct stc_ethernet_mac_mar22h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar22h_field_t;
+
+typedef struct stc_ethernet_mac_mar22l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar22l_field_t;
+
+typedef struct stc_ethernet_mac_mar23h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar23h_field_t;
+
+typedef struct stc_ethernet_mac_mar23l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar23l_field_t;
+
+typedef struct stc_ethernet_mac_mar24h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar24h_field_t;
+
+typedef struct stc_ethernet_mac_mar24l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar24l_field_t;
+
+typedef struct stc_ethernet_mac_mar25h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar25h_field_t;
+
+typedef struct stc_ethernet_mac_mar25l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar25l_field_t;
+
+typedef struct stc_ethernet_mac_mar26h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar26h_field_t;
+
+typedef struct stc_ethernet_mac_mar26l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar26l_field_t;
+
+typedef struct stc_ethernet_mac_mar27h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar27h_field_t;
+
+typedef struct stc_ethernet_mac_mar27l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar27l_field_t;
+
+typedef struct stc_ethernet_mac_mar28h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar28h_field_t;
+
+typedef struct stc_ethernet_mac_mar28l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar28l_field_t;
+
+typedef struct stc_ethernet_mac_mar29h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar29h_field_t;
+
+typedef struct stc_ethernet_mac_mar29l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar29l_field_t;
+
+typedef struct stc_ethernet_mac_mar30h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar30h_field_t;
+
+typedef struct stc_ethernet_mac_mar30l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar30l_field_t;
+
+typedef struct stc_ethernet_mac_mar31h_field
+{
+  __IO uint32_t A32        : 1;
+  __IO uint32_t A33        : 1;
+  __IO uint32_t A34        : 1;
+  __IO uint32_t A35        : 1;
+  __IO uint32_t A36        : 1;
+  __IO uint32_t A37        : 1;
+  __IO uint32_t A38        : 1;
+  __IO uint32_t A39        : 1;
+  __IO uint32_t A40        : 1;
+  __IO uint32_t A41        : 1;
+  __IO uint32_t A42        : 1;
+  __IO uint32_t A43        : 1;
+  __IO uint32_t A44        : 1;
+  __IO uint32_t A45        : 1;
+  __IO uint32_t A46        : 1;
+  __IO uint32_t A47        : 1;
+       uint32_t RESERVED1  : 8;
+  __IO uint32_t MBC0       : 1;
+  __IO uint32_t MBC1       : 1;
+  __IO uint32_t MBC2       : 1;
+  __IO uint32_t MBC3       : 1;
+  __IO uint32_t MBC4       : 1;
+  __IO uint32_t MBC5       : 1;
+  __IO uint32_t SA         : 1;
+  __IO uint32_t AE         : 1;
+} stc_ethernet_mac_mar31h_field_t;
+
+typedef struct stc_ethernet_mac_mar31l_field
+{
+  __IO uint32_t A0         : 1;
+  __IO uint32_t A1         : 1;
+  __IO uint32_t A2         : 1;
+  __IO uint32_t A3         : 1;
+  __IO uint32_t A4         : 1;
+  __IO uint32_t A5         : 1;
+  __IO uint32_t A6         : 1;
+  __IO uint32_t A7         : 1;
+  __IO uint32_t A8         : 1;
+  __IO uint32_t A9         : 1;
+  __IO uint32_t A10        : 1;
+  __IO uint32_t A11        : 1;
+  __IO uint32_t A12        : 1;
+  __IO uint32_t A13        : 1;
+  __IO uint32_t A14        : 1;
+  __IO uint32_t A15        : 1;
+  __IO uint32_t A16        : 1;
+  __IO uint32_t A17        : 1;
+  __IO uint32_t A18        : 1;
+  __IO uint32_t A19        : 1;
+  __IO uint32_t A20        : 1;
+  __IO uint32_t A21        : 1;
+  __IO uint32_t A22        : 1;
+  __IO uint32_t A23        : 1;
+  __IO uint32_t A24        : 1;
+  __IO uint32_t A25        : 1;
+  __IO uint32_t A26        : 1;
+  __IO uint32_t A27        : 1;
+  __IO uint32_t A28        : 1;
+  __IO uint32_t A29        : 1;
+  __IO uint32_t A30        : 1;
+  __IO uint32_t A31        : 1;
+} stc_ethernet_mac_mar31l_field_t;
+
+typedef struct stc_ethernet_mac_bmr_field
+{
+  __IO uint32_t SWR        : 1;
+  __IO uint32_t DA         : 1;
+  __IO uint32_t DSL0       : 1;
+  __IO uint32_t DSL1       : 1;
+  __IO uint32_t DSL2       : 1;
+  __IO uint32_t DSL3       : 1;
+  __IO uint32_t DSL4       : 1;
+  __IO uint32_t ATDS       : 1;
+  __IO uint32_t PBL0       : 1;
+  __IO uint32_t PBL1       : 1;
+  __IO uint32_t PBL2       : 1;
+  __IO uint32_t PBL3       : 1;
+  __IO uint32_t PBL4       : 1;
+  __IO uint32_t PBL5       : 1;
+  __IO uint32_t PR0        : 1;
+  __IO uint32_t PR1        : 1;
+  __IO uint32_t FB         : 1;
+  __IO uint32_t RPBL0      : 1;
+  __IO uint32_t RPBL1      : 1;
+  __IO uint32_t RPBL2      : 1;
+  __IO uint32_t RPBL3      : 1;
+  __IO uint32_t RPBL4      : 1;
+  __IO uint32_t RPBL5      : 1;
+  __IO uint32_t USP        : 1;
+  __IO uint32_t _8XPBL     : 1;
+  __IO uint32_t AAL        : 1;
+  __IO uint32_t MB         : 1;
+  __IO uint32_t TXPR       : 1;
+} stc_ethernet_mac_bmr_field_t;
+
+typedef struct stc_ethernet_mac_tpdr_field
+{
+  __IO uint32_t TPD0       : 1;
+  __IO uint32_t TPD1       : 1;
+  __IO uint32_t TPD2       : 1;
+  __IO uint32_t TPD3       : 1;
+  __IO uint32_t TPD4       : 1;
+  __IO uint32_t TPD5       : 1;
+  __IO uint32_t TPD6       : 1;
+  __IO uint32_t TPD7       : 1;
+  __IO uint32_t TPD8       : 1;
+  __IO uint32_t TPD9       : 1;
+  __IO uint32_t TPD10      : 1;
+  __IO uint32_t TPD11      : 1;
+  __IO uint32_t TPD12      : 1;
+  __IO uint32_t TPD13      : 1;
+  __IO uint32_t TPD14      : 1;
+  __IO uint32_t TPD15      : 1;
+  __IO uint32_t TPD16      : 1;
+  __IO uint32_t TPD17      : 1;
+  __IO uint32_t TPD18      : 1;
+  __IO uint32_t TPD19      : 1;
+  __IO uint32_t TPD20      : 1;
+  __IO uint32_t TPD21      : 1;
+  __IO uint32_t TPD22      : 1;
+  __IO uint32_t TPD23      : 1;
+  __IO uint32_t TPD24      : 1;
+  __IO uint32_t TPD25      : 1;
+  __IO uint32_t TPD26      : 1;
+  __IO uint32_t TPD27      : 1;
+  __IO uint32_t TPD28      : 1;
+  __IO uint32_t TPD29      : 1;
+  __IO uint32_t TPD30      : 1;
+  __IO uint32_t TPD31      : 1;
+} stc_ethernet_mac_tpdr_field_t;
+
+typedef struct stc_ethernet_mac_rpdr_field
+{
+  __IO uint32_t RPD0       : 1;
+  __IO uint32_t RPD1       : 1;
+  __IO uint32_t RPD2       : 1;
+  __IO uint32_t RPD3       : 1;
+  __IO uint32_t RPD4       : 1;
+  __IO uint32_t RPD5       : 1;
+  __IO uint32_t RPD6       : 1;
+  __IO uint32_t RPD7       : 1;
+  __IO uint32_t RPD8       : 1;
+  __IO uint32_t RPD9       : 1;
+  __IO uint32_t RPD10      : 1;
+  __IO uint32_t RPD11      : 1;
+  __IO uint32_t RPD12      : 1;
+  __IO uint32_t RPD13      : 1;
+  __IO uint32_t RPD14      : 1;
+  __IO uint32_t RPD15      : 1;
+  __IO uint32_t RPD16      : 1;
+  __IO uint32_t RPD17      : 1;
+  __IO uint32_t RPD18      : 1;
+  __IO uint32_t RPD19      : 1;
+  __IO uint32_t RPD20      : 1;
+  __IO uint32_t RPD21      : 1;
+  __IO uint32_t RPD22      : 1;
+  __IO uint32_t RPD23      : 1;
+  __IO uint32_t RPD24      : 1;
+  __IO uint32_t RPD25      : 1;
+  __IO uint32_t RPD26      : 1;
+  __IO uint32_t RPD27      : 1;
+  __IO uint32_t RPD28      : 1;
+  __IO uint32_t RPD29      : 1;
+  __IO uint32_t RPD30      : 1;
+  __IO uint32_t RPD31      : 1;
+} stc_ethernet_mac_rpdr_field_t;
+
+typedef struct stc_ethernet_mac_rdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t SRL2       : 1;
+  __IO uint32_t SRL3       : 1;
+  __IO uint32_t SRL4       : 1;
+  __IO uint32_t SRL5       : 1;
+  __IO uint32_t SRL6       : 1;
+  __IO uint32_t SRL7       : 1;
+  __IO uint32_t SRL8       : 1;
+  __IO uint32_t SRL9       : 1;
+  __IO uint32_t SRL10      : 1;
+  __IO uint32_t SRL11      : 1;
+  __IO uint32_t SRL12      : 1;
+  __IO uint32_t SRL13      : 1;
+  __IO uint32_t SRL14      : 1;
+  __IO uint32_t SRL15      : 1;
+  __IO uint32_t SRL16      : 1;
+  __IO uint32_t SRL17      : 1;
+  __IO uint32_t SRL18      : 1;
+  __IO uint32_t SRL19      : 1;
+  __IO uint32_t SRL20      : 1;
+  __IO uint32_t SRL21      : 1;
+  __IO uint32_t SRL22      : 1;
+  __IO uint32_t SRL23      : 1;
+  __IO uint32_t SRL24      : 1;
+  __IO uint32_t SRL25      : 1;
+  __IO uint32_t SRL26      : 1;
+  __IO uint32_t SRL27      : 1;
+  __IO uint32_t SRL28      : 1;
+  __IO uint32_t SRL29      : 1;
+  __IO uint32_t SRL30      : 1;
+  __IO uint32_t SRL31      : 1;
+} stc_ethernet_mac_rdlar_field_t;
+
+typedef struct stc_ethernet_mac_tdlar_field
+{
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t STL2       : 1;
+  __IO uint32_t STL3       : 1;
+  __IO uint32_t STL4       : 1;
+  __IO uint32_t STL5       : 1;
+  __IO uint32_t STL6       : 1;
+  __IO uint32_t STL7       : 1;
+  __IO uint32_t STL8       : 1;
+  __IO uint32_t STL9       : 1;
+  __IO uint32_t STL10      : 1;
+  __IO uint32_t STL11      : 1;
+  __IO uint32_t STL12      : 1;
+  __IO uint32_t STL13      : 1;
+  __IO uint32_t STL14      : 1;
+  __IO uint32_t STL15      : 1;
+  __IO uint32_t STL16      : 1;
+  __IO uint32_t STL17      : 1;
+  __IO uint32_t STL18      : 1;
+  __IO uint32_t STL19      : 1;
+  __IO uint32_t STL20      : 1;
+  __IO uint32_t STL21      : 1;
+  __IO uint32_t STL22      : 1;
+  __IO uint32_t STL23      : 1;
+  __IO uint32_t STL24      : 1;
+  __IO uint32_t STL25      : 1;
+  __IO uint32_t STL26      : 1;
+  __IO uint32_t STL27      : 1;
+  __IO uint32_t STL28      : 1;
+  __IO uint32_t STL29      : 1;
+  __IO uint32_t STL30      : 1;
+  __IO uint32_t STL31      : 1;
+} stc_ethernet_mac_tdlar_field_t;
+
+typedef struct stc_ethernet_mac_sr_field
+{
+  __IO uint32_t TI         : 1;
+  __IO uint32_t TPS        : 1;
+  __IO uint32_t TU         : 1;
+  __IO uint32_t TJT        : 1;
+  __IO uint32_t OVF        : 1;
+  __IO uint32_t UNF        : 1;
+  __IO uint32_t RI         : 1;
+  __IO uint32_t RU         : 1;
+  __IO uint32_t RPS        : 1;
+  __IO uint32_t RWT        : 1;
+  __IO uint32_t ETI        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBI        : 1;
+  __IO uint32_t ERI        : 1;
+  __IO uint32_t AIS        : 1;
+  __IO uint32_t NIS        : 1;
+  __IO uint32_t RS0        : 1;
+  __IO uint32_t RS1        : 1;
+  __IO uint32_t RS2        : 1;
+  __IO uint32_t TS0        : 1;
+  __IO uint32_t TS1        : 1;
+  __IO uint32_t TS2        : 1;
+  __IO uint32_t EB0        : 1;
+  __IO uint32_t EB1        : 1;
+  __IO uint32_t EB2        : 1;
+  __IO uint32_t GLI        : 1;
+  __IO uint32_t GMI        : 1;
+  __IO uint32_t GPI        : 1;
+  __IO uint32_t TTI        : 1;
+  __IO uint32_t GLPII      : 1;
+} stc_ethernet_mac_sr_field_t;
+
+typedef struct stc_ethernet_mac_omr_field
+{
+       uint32_t RESERVED1  : 1;
+  __IO uint32_t SR         : 1;
+  __IO uint32_t OSF        : 1;
+  __IO uint32_t RTC0       : 1;
+  __IO uint32_t RTC1       : 1;
+       uint32_t RESERVED2  : 1;
+  __IO uint32_t FUF        : 1;
+  __IO uint32_t FEF        : 1;
+       uint32_t RESERVED3  : 5;
+  __IO uint32_t ST         : 1;
+  __IO uint32_t TTC0       : 1;
+  __IO uint32_t TTC1       : 1;
+  __IO uint32_t TTC2       : 1;
+       uint32_t RESERVED4  : 3;
+  __IO uint32_t FTF        : 1;
+  __IO uint32_t TSF        : 1;
+       uint32_t RESERVED5  : 2;
+  __IO uint32_t DFF        : 1;
+  __IO uint32_t RSF        : 1;
+  __IO uint32_t DT         : 1;
+} stc_ethernet_mac_omr_field_t;
+
+typedef struct stc_ethernet_mac_ier_field
+{
+  __IO uint32_t TIE        : 1;
+  __IO uint32_t TSE        : 1;
+  __IO uint32_t TUE        : 1;
+  __IO uint32_t TJE        : 1;
+  __IO uint32_t OVE        : 1;
+  __IO uint32_t UNE        : 1;
+  __IO uint32_t RIE        : 1;
+  __IO uint32_t RUE        : 1;
+  __IO uint32_t RSE        : 1;
+  __IO uint32_t RWE        : 1;
+  __IO uint32_t ETE        : 1;
+       uint32_t RESERVED1  : 2;
+  __IO uint32_t FBE        : 1;
+  __IO uint32_t ERE        : 1;
+  __IO uint32_t AIE        : 1;
+  __IO uint32_t NIE        : 1;
+} stc_ethernet_mac_ier_field_t;
+
+typedef struct stc_ethernet_mac_mfbocr_field
+{
+  __IO uint32_t NMFH0      : 1;
+  __IO uint32_t NMFH1      : 1;
+  __IO uint32_t NMFH2      : 1;
+  __IO uint32_t NMFH3      : 1;
+  __IO uint32_t NMFH4      : 1;
+  __IO uint32_t NMFH5      : 1;
+  __IO uint32_t NMFH6      : 1;
+  __IO uint32_t NMFH7      : 1;
+  __IO uint32_t NMFH8      : 1;
+  __IO uint32_t NMFH9      : 1;
+  __IO uint32_t NMFH10     : 1;
+  __IO uint32_t NMFH11     : 1;
+  __IO uint32_t NMFH12     : 1;
+  __IO uint32_t NMFH13     : 1;
+  __IO uint32_t NMFH14     : 1;
+  __IO uint32_t NMFH15     : 1;
+  __IO uint32_t ONMFH      : 1;
+  __IO uint32_t NMFF0      : 1;
+  __IO uint32_t NMFF1      : 1;
+  __IO uint32_t NMFF2      : 1;
+  __IO uint32_t NMFF3      : 1;
+  __IO uint32_t NMFF4      : 1;
+  __IO uint32_t NMFF5      : 1;
+  __IO uint32_t NMFF6      : 1;
+  __IO uint32_t NMFF7      : 1;
+  __IO uint32_t NMFF8      : 1;
+  __IO uint32_t NMFF9      : 1;
+  __IO uint32_t NMFF10     : 1;
+  __IO uint32_t ONMFF      : 1;
+} stc_ethernet_mac_mfbocr_field_t;
+
+typedef struct stc_ethernet_mac_riwtr_field
+{
+  __IO uint32_t RIWT0      : 1;
+  __IO uint32_t RIWT1      : 1;
+  __IO uint32_t RIWT2      : 1;
+  __IO uint32_t RIWT3      : 1;
+  __IO uint32_t RIWT4      : 1;
+  __IO uint32_t RIWT5      : 1;
+  __IO uint32_t RIWT6      : 1;
+  __IO uint32_t RIWT7      : 1;
+} stc_ethernet_mac_riwtr_field_t;
+
+typedef struct stc_ethernet_mac_ahbsr_field
+{
+  __IO uint32_t AHBS       : 1;
+} stc_ethernet_mac_ahbsr_field_t;
+
+typedef struct stc_ethernet_mac_chtdr_field
+{
+  __IO uint32_t HTDAP0     : 1;
+  __IO uint32_t HTDAP1     : 1;
+  __IO uint32_t HTDAP2     : 1;
+  __IO uint32_t HTDAP3     : 1;
+  __IO uint32_t HTDAP4     : 1;
+  __IO uint32_t HTDAP5     : 1;
+  __IO uint32_t HTDAP6     : 1;
+  __IO uint32_t HTDAP7     : 1;
+  __IO uint32_t HTDAP8     : 1;
+  __IO uint32_t HTDAP9     : 1;
+  __IO uint32_t HTDAP10    : 1;
+  __IO uint32_t HTDAP11    : 1;
+  __IO uint32_t HTDAP12    : 1;
+  __IO uint32_t HTDAP13    : 1;
+  __IO uint32_t HTDAP14    : 1;
+  __IO uint32_t HTDAP15    : 1;
+  __IO uint32_t HTDAP16    : 1;
+  __IO uint32_t HTDAP17    : 1;
+  __IO uint32_t HTDAP18    : 1;
+  __IO uint32_t HTDAP19    : 1;
+  __IO uint32_t HTDAP20    : 1;
+  __IO uint32_t HTDAP21    : 1;
+  __IO uint32_t HTDAP22    : 1;
+  __IO uint32_t HTDAP23    : 1;
+  __IO uint32_t HTDAP24    : 1;
+  __IO uint32_t HTDAP25    : 1;
+  __IO uint32_t HTDAP26    : 1;
+  __IO uint32_t HTDAP27    : 1;
+  __IO uint32_t HTDAP28    : 1;
+  __IO uint32_t HTDAP29    : 1;
+  __IO uint32_t HTDAP30    : 1;
+  __IO uint32_t HTDAP31    : 1;
+} stc_ethernet_mac_chtdr_field_t;
+
+typedef struct stc_ethernet_mac_chrdr_field
+{
+  __IO uint32_t HRDAP0     : 1;
+  __IO uint32_t HRDAP1     : 1;
+  __IO uint32_t HRDAP2     : 1;
+  __IO uint32_t HRDAP3     : 1;
+  __IO uint32_t HRDAP4     : 1;
+  __IO uint32_t HRDAP5     : 1;
+  __IO uint32_t HRDAP6     : 1;
+  __IO uint32_t HRDAP7     : 1;
+  __IO uint32_t HRDAP8     : 1;
+  __IO uint32_t HRDAP9     : 1;
+  __IO uint32_t HRDAP10    : 1;
+  __IO uint32_t HRDAP11    : 1;
+  __IO uint32_t HRDAP12    : 1;
+  __IO uint32_t HRDAP13    : 1;
+  __IO uint32_t HRDAP14    : 1;
+  __IO uint32_t HRDAP15    : 1;
+  __IO uint32_t HRDAP16    : 1;
+  __IO uint32_t HRDAP17    : 1;
+  __IO uint32_t HRDAP18    : 1;
+  __IO uint32_t HRDAP19    : 1;
+  __IO uint32_t HRDAP20    : 1;
+  __IO uint32_t HRDAP21    : 1;
+  __IO uint32_t HRDAP22    : 1;
+  __IO uint32_t HRDAP23    : 1;
+  __IO uint32_t HRDAP24    : 1;
+  __IO uint32_t HRDAP25    : 1;
+  __IO uint32_t HRDAP26    : 1;
+  __IO uint32_t HRDAP27    : 1;
+  __IO uint32_t HRDAP28    : 1;
+  __IO uint32_t HRDAP29    : 1;
+  __IO uint32_t HRDAP30    : 1;
+  __IO uint32_t HRDAP31    : 1;
+} stc_ethernet_mac_chrdr_field_t;
+
+typedef struct stc_ethernet_mac_chtbar_field
+{
+  __IO uint32_t HTBAR0     : 1;
+  __IO uint32_t HTBAR1     : 1;
+  __IO uint32_t HTBAR2     : 1;
+  __IO uint32_t HTBAR3     : 1;
+  __IO uint32_t HTBAR4     : 1;
+  __IO uint32_t HTBAR5     : 1;
+  __IO uint32_t HTBAR6     : 1;
+  __IO uint32_t HTBAR7     : 1;
+  __IO uint32_t HTBAR8     : 1;
+  __IO uint32_t HTBAR9     : 1;
+  __IO uint32_t HTBAR10    : 1;
+  __IO uint32_t HTBAR11    : 1;
+  __IO uint32_t HTBAR12    : 1;
+  __IO uint32_t HTBAR13    : 1;
+  __IO uint32_t HTBAR14    : 1;
+  __IO uint32_t HTBAR15    : 1;
+  __IO uint32_t HTBAR16    : 1;
+  __IO uint32_t HTBAR17    : 1;
+  __IO uint32_t HTBAR18    : 1;
+  __IO uint32_t HTBAR19    : 1;
+  __IO uint32_t HTBAR20    : 1;
+  __IO uint32_t HTBAR21    : 1;
+  __IO uint32_t HTBAR22    : 1;
+  __IO uint32_t HTBAR23    : 1;
+  __IO uint32_t HTBAR24    : 1;
+  __IO uint32_t HTBAR25    : 1;
+  __IO uint32_t HTBAR26    : 1;
+  __IO uint32_t HTBAR27    : 1;
+  __IO uint32_t HTBAR28    : 1;
+  __IO uint32_t HTBAR29    : 1;
+  __IO uint32_t HTBAR30    : 1;
+  __IO uint32_t HTBAR31    : 1;
+} stc_ethernet_mac_chtbar_field_t;
+
+typedef struct stc_ethernet_mac_chrbar_field
+{
+  __IO uint32_t HRBAR0     : 1;
+  __IO uint32_t HRBAR1     : 1;
+  __IO uint32_t HRBAR2     : 1;
+  __IO uint32_t HRBAR3     : 1;
+  __IO uint32_t HRBAR4     : 1;
+  __IO uint32_t HRBAR5     : 1;
+  __IO uint32_t HRBAR6     : 1;
+  __IO uint32_t HRBAR7     : 1;
+  __IO uint32_t HRBAR8     : 1;
+  __IO uint32_t HRBAR9     : 1;
+  __IO uint32_t HRBAR10    : 1;
+  __IO uint32_t HRBAR11    : 1;
+  __IO uint32_t HRBAR12    : 1;
+  __IO uint32_t HRBAR13    : 1;
+  __IO uint32_t HRBAR14    : 1;
+  __IO uint32_t HRBAR15    : 1;
+  __IO uint32_t HRBAR16    : 1;
+  __IO uint32_t HRBAR17    : 1;
+  __IO uint32_t HRBAR18    : 1;
+  __IO uint32_t HRBAR19    : 1;
+  __IO uint32_t HRBAR20    : 1;
+  __IO uint32_t HRBAR21    : 1;
+  __IO uint32_t HRBAR22    : 1;
+  __IO uint32_t HRBAR23    : 1;
+  __IO uint32_t HRBAR24    : 1;
+  __IO uint32_t HRBAR25    : 1;
+  __IO uint32_t HRBAR26    : 1;
+  __IO uint32_t HRBAR27    : 1;
+  __IO uint32_t HRBAR28    : 1;
+  __IO uint32_t HRBAR29    : 1;
+  __IO uint32_t HRBAR30    : 1;
+  __IO uint32_t HRBAR31    : 1;
+} stc_ethernet_mac_chrbar_field_t;
+
+/* ETHERNET_CONTROL_MODULE register bit fields */
+typedef struct stc_ethernet_control_eth_mode_field
+{
+  __IO uint32_t IFMODE     : 1;
+       uint32_t RESERVED1  : 7;
+  __IO uint32_t RST0       : 1;
+  __IO uint32_t RST1       : 1;
+       uint32_t RESERVED2  :18;
+  __IO uint32_t ASZPPSSEL  : 1;
+} stc_ethernet_control_eth_mode_field_t;
+
+typedef struct stc_ethernet_control_eth_clkg_field
+{
+  __IO uint32_t MACEN0     : 1;
+  __IO uint32_t MACEN1     : 1;
+} stc_ethernet_control_eth_clkg_field_t;
+
+/******************************************************************************
+ * Peripheral register structures
+ ******************************************************************************/
+
+/******************************************************************************
+ * Flash_IF_MODULE
+ ******************************************************************************/
+/* Flash interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t FASZR;
+    stc_flash_if_faszr_field_t FASZR_f;
+  };
+  union {
+    __IO uint32_t FRWTR;
+    stc_flash_if_frwtr_field_t FRWTR_f;
+  };
+  union {
+    __IO uint32_t FSTR;
+    stc_flash_if_fstr_field_t FSTR_f;
+  };
+        uint8_t RESERVED0[4];
+  union {
+    __IO uint32_t FSYNDN;
+    stc_flash_if_fsyndn_field_t FSYNDN_f;
+  };
+  union {
+    __IO uint32_t FBFCR;
+    stc_flash_if_fbfcr_field_t FBFCR_f;
+  };
+        uint8_t RESERVED1[232];
+  union {
+    __IO uint32_t CRTRMM;
+    stc_flash_if_crtrmm_field_t CRTRMM_f;
+  };
+}FM3_FLASH_IF_TypeDef;
+
+/******************************************************************************
+ * Clock_Reset_MODULE
+ ******************************************************************************/
+/* Clock and reset registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SCM_CTL;
+    stc_crg_scm_ctl_field_t SCM_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t SCM_STR;
+    stc_crg_scm_str_field_t SCM_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  __IO uint32_t STB_CTL;
+  union {
+    __IO uint16_t RST_STR;
+    stc_crg_rst_str_field_t RST_STR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t BSC_PSR;
+    stc_crg_bsc_psr_field_t BSC_PSR_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t APBC0_PSR;
+    stc_crg_apbc0_psr_field_t APBC0_PSR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t APBC1_PSR;
+    stc_crg_apbc1_psr_field_t APBC1_PSR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t APBC2_PSR;
+    stc_crg_apbc2_psr_field_t APBC2_PSR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t SWC_PSR;
+    stc_crg_swc_psr_field_t SWC_PSR_f;
+  };
+        uint8_t RESERVED7[7];
+  union {
+    __IO  uint8_t TTC_PSR;
+    stc_crg_ttc_psr_field_t TTC_PSR_f;
+  };
+        uint8_t RESERVED8[7];
+  union {
+    __IO  uint8_t CSW_TMR;
+    stc_crg_csw_tmr_field_t CSW_TMR_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t PSW_TMR;
+    stc_crg_psw_tmr_field_t PSW_TMR_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PLL_CTL1;
+    stc_crg_pll_ctl1_field_t PLL_CTL1_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t PLL_CTL2;
+    stc_crg_pll_ctl2_field_t PLL_CTL2_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO uint16_t CSV_CTL;
+    stc_crg_csv_ctl_field_t CSV_CTL_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO  uint8_t CSV_STR;
+    stc_crg_csv_str_field_t CSV_STR_f;
+  };
+        uint8_t RESERVED14[3];
+  __IO uint16_t FCSWH_CTL;
+        uint8_t RESERVED15[2];
+  __IO uint16_t FCSWL_CTL;
+        uint8_t RESERVED16[2];
+  __IO uint16_t FCSWD_CTL;
+        uint8_t RESERVED17[2];
+  union {
+    __IO  uint8_t DBWDT_CTL;
+    stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f;
+  };
+        uint8_t RESERVED18[11];
+  union {
+    __IO  uint8_t INT_ENR;
+    stc_crg_int_enr_field_t INT_ENR_f;
+  };
+        uint8_t RESERVED19[3];
+  union {
+    __IO  uint8_t INT_STR;
+    stc_crg_int_str_field_t INT_STR_f;
+  };
+        uint8_t RESERVED20[3];
+  union {
+    __IO  uint8_t INT_CLR;
+    stc_crg_int_clr_field_t INT_CLR_f;
+  };
+}FM3_CRG_TypeDef;
+
+/******************************************************************************
+ * HWWDT_MODULE
+ ******************************************************************************/
+/* Hardware watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDG_LDR;
+  __IO uint32_t WDG_VLR;
+  union {
+    __IO  uint8_t WDG_CTL;
+    stc_hwwdt_wdg_ctl_field_t WDG_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO  uint8_t WDG_ICL;
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t WDG_RIS;
+    stc_hwwdt_wdg_ris_field_t WDG_RIS_f;
+  };
+        uint8_t RESERVED2[3055];
+  __IO uint32_t WDG_LCK;
+}FM3_HWWDT_TypeDef;
+
+/******************************************************************************
+ * SWWDT_MODULE
+ ******************************************************************************/
+/* Software watchdog registers */
+typedef struct
+{
+  __IO uint32_t WDOGLOAD;
+  __IO uint32_t WDOGVALUE;
+  union {
+    __IO  uint8_t WDOGCONTROL;
+    stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t WDOGINTCLR;
+  union {
+    __IO  uint8_t WDOGRIS;
+    stc_swwdt_wdogris_field_t WDOGRIS_f;
+  };
+        uint8_t RESERVED1[3055];
+  __IO uint32_t WDOGLOCK;
+}FM3_SWWDT_TypeDef;
+
+/******************************************************************************
+ * DTIM_MODULE
+ ******************************************************************************/
+/* Dual timer 1/2 registers */
+typedef struct
+{
+  __IO uint32_t TIMER1LOAD;
+  __IO uint32_t TIMER1VALUE;
+  union {
+    __IO uint32_t TIMER1CONTROL;
+    stc_dtim_timer1control_field_t TIMER1CONTROL_f;
+  };
+  __IO uint32_t TIMER1INTCLR;
+  union {
+    __IO uint32_t TIMER1RIS;
+    stc_dtim_timer1ris_field_t TIMER1RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER1MIS;
+    stc_dtim_timer1mis_field_t TIMER1MIS_f;
+  };
+  __IO uint32_t TIMER1BGLOAD;
+        uint8_t RESERVED0[4];
+  __IO uint32_t TIMER2LOAD;
+  __IO uint32_t TIMER2VALUE;
+  union {
+    __IO uint32_t TIMER2CONTROL;
+    stc_dtim_timer2control_field_t TIMER2CONTROL_f;
+  };
+  __IO uint32_t TIMER2INTCLR;
+  union {
+    __IO uint32_t TIMER2RIS;
+    stc_dtim_timer2ris_field_t TIMER2RIS_f;
+  };
+  union {
+    __IO uint32_t TIMER2MIS;
+    stc_dtim_timer2mis_field_t TIMER2MIS_f;
+  };
+  __IO uint32_t TIMER2BGLOAD;
+}FM3_DTIM_TypeDef;
+
+/******************************************************************************
+ * MFT_FRT_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Free Running Timer registers */
+typedef struct
+{
+        uint8_t RESERVED0[40];
+  __IO uint16_t TCCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TCDT0;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TCSA0;
+    stc_mft_frt_tcsa0_field_t TCSA0_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t TCSB0;
+    stc_mft_frt_tcsb0_field_t TCSB0_f;
+  };
+        uint8_t RESERVED4[2];
+  __IO uint16_t TCCP1;
+        uint8_t RESERVED5[2];
+  __IO uint16_t TCDT1;
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t TCSA1;
+    stc_mft_frt_tcsa1_field_t TCSA1_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t TCSB1;
+    stc_mft_frt_tcsb1_field_t TCSB1_f;
+  };
+        uint8_t RESERVED8[2];
+  __IO uint16_t TCCP2;
+        uint8_t RESERVED9[2];
+  __IO uint16_t TCDT2;
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t TCSA2;
+    stc_mft_frt_tcsa2_field_t TCSA2_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t TCSB2;
+    stc_mft_frt_tcsb2_field_t TCSB2_f;
+  };
+}FM3_MFT_FRT_TypeDef;
+
+/******************************************************************************
+ * MFT_OCU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+typedef struct
+{
+  __IO uint16_t OCCP0;
+        uint8_t RESERVED0[2];
+  __IO uint16_t OCCP1;
+        uint8_t RESERVED1[2];
+  __IO uint16_t OCCP2;
+        uint8_t RESERVED2[2];
+  __IO uint16_t OCCP3;
+        uint8_t RESERVED3[2];
+  __IO uint16_t OCCP4;
+        uint8_t RESERVED4[2];
+  __IO uint16_t OCCP5;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t OCSA10;
+    stc_mft_ocu_ocsa10_field_t OCSA10_f;
+  };
+  union {
+    __IO  uint8_t OCSB10;
+    stc_mft_ocu_ocsb10_field_t OCSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t OCSA32;
+    stc_mft_ocu_ocsa32_field_t OCSA32_f;
+  };
+  union {
+    __IO  uint8_t OCSB32;
+    stc_mft_ocu_ocsb32_field_t OCSB32_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO  uint8_t OCSA54;
+    stc_mft_ocu_ocsa54_field_t OCSA54_f;
+  };
+  union {
+    __IO  uint8_t OCSB54;
+    stc_mft_ocu_ocsb54_field_t OCSB54_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t OCSC;
+    stc_mft_ocu_ocsc_field_t OCSC_f;
+  };
+        uint8_t RESERVED9[50];
+  union {
+    __IO  uint8_t OCFS10;
+    stc_mft_ocu_ocfs10_field_t OCFS10_f;
+  };
+  union {
+    __IO  uint8_t OCFS32;
+    stc_mft_ocu_ocfs32_field_t OCFS32_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO  uint8_t OCFS54;
+    stc_mft_ocu_ocfs54_field_t OCFS54_f;
+  };
+}FM3_MFT_OCU_TypeDef;
+
+/******************************************************************************
+ * MFT_WFG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+typedef struct
+{
+        uint8_t RESERVED0[128];
+  __IO uint16_t WFTM10;
+        uint8_t RESERVED1[2];
+  __IO uint16_t WFTM32;
+        uint8_t RESERVED2[2];
+  __IO uint16_t WFTM54;
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t WFSA10;
+    stc_mft_wfg_wfsa10_field_t WFSA10_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t WFSA32;
+    stc_mft_wfg_wfsa32_field_t WFSA32_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t WFSA54;
+    stc_mft_wfg_wfsa54_field_t WFSA54_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t WFIR;
+    stc_mft_wfg_wfir_field_t WFIR_f;
+  };
+        uint8_t RESERVED7[2];
+  union {
+    __IO uint16_t NZCL;
+    stc_mft_wfg_nzcl_field_t NZCL_f;
+  };
+}FM3_MFT_WFG_TypeDef;
+
+/******************************************************************************
+ * MFT_ICU_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[96];
+  union {
+    __IO  uint8_t ICFS10;
+    stc_mft_icu_icfs10_field_t ICFS10_f;
+  };
+  union {
+    __IO  uint8_t ICFS32;
+    stc_mft_icu_icfs32_field_t ICFS32_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint16_t ICCP0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ICCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ICCP2;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ICCP3;
+        uint8_t RESERVED5[2];
+  union {
+    __IO  uint8_t ICSA10;
+    stc_mft_icu_icsa10_field_t ICSA10_f;
+  };
+  union {
+    __IO  uint8_t ICSB10;
+    stc_mft_icu_icsb10_field_t ICSB10_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ICSA32;
+    stc_mft_icu_icsa32_field_t ICSA32_f;
+  };
+  union {
+    __IO  uint8_t ICSB32;
+    stc_mft_icu_icsb32_field_t ICSB32_f;
+  };
+}FM3_MFT_ICU_TypeDef;
+
+/******************************************************************************
+ * MFT_ADCMP_MODULE
+ ******************************************************************************/
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+typedef struct
+{
+        uint8_t RESERVED0[160];
+  __IO uint16_t ACCP0;
+        uint8_t RESERVED1[2];
+  __IO uint16_t ACCPDN0;
+        uint8_t RESERVED2[2];
+  __IO uint16_t ACCP1;
+        uint8_t RESERVED3[2];
+  __IO uint16_t ACCPDN1;
+        uint8_t RESERVED4[2];
+  __IO uint16_t ACCP2;
+        uint8_t RESERVED5[2];
+  __IO uint16_t ACCPDN2;
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t ACSB;
+    stc_mft_adcmp_acsb_field_t ACSB_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t ACSA;
+    stc_mft_adcmp_acsa_field_t ACSA_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t ATSA;
+    stc_mft_adcmp_atsa_field_t ATSA_f;
+  };
+}FM3_MFT_ADCMP_TypeDef;
+
+/******************************************************************************
+ * MFT_PPG_MODULE
+ ******************************************************************************/
+/* Multifunction Timer PPG registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t TTCR0;
+    stc_mft_ppg_ttcr0_field_t TTCR0_f;
+  };
+        uint8_t RESERVED1[7];
+  __IO  uint8_t COMP0;
+        uint8_t RESERVED2[2];
+  __IO  uint8_t COMP2;
+        uint8_t RESERVED3[4];
+  __IO  uint8_t COMP4;
+        uint8_t RESERVED4[2];
+  __IO  uint8_t COMP6;
+        uint8_t RESERVED5[12];
+  union {
+    __IO  uint8_t TTCR1;
+    stc_mft_ppg_ttcr1_field_t TTCR1_f;
+  };
+        uint8_t RESERVED6[7];
+  __IO  uint8_t COMP1;
+        uint8_t RESERVED7[2];
+  __IO  uint8_t COMP3;
+        uint8_t RESERVED8[4];
+  __IO  uint8_t COMP5;
+        uint8_t RESERVED9[2];
+  __IO  uint8_t COMP7;
+        uint8_t RESERVED10[12];
+  union {
+    __IO  uint8_t TTCR2;
+    stc_mft_ppg_ttcr2_field_t TTCR2_f;
+  };
+        uint8_t RESERVED11[7];
+  __IO  uint8_t COMP8;
+        uint8_t RESERVED12[2];
+  __IO  uint8_t COMP10;
+        uint8_t RESERVED13[4];
+  __IO  uint8_t COMP12;
+        uint8_t RESERVED14[2];
+  __IO  uint8_t COMP14;
+        uint8_t RESERVED15[171];
+  union {
+    __IO uint16_t TRG;
+    stc_mft_ppg_trg_field_t TRG_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t REVC;
+    stc_mft_ppg_revc_field_t REVC_f;
+  };
+        uint8_t RESERVED17[58];
+  union {
+    __IO uint16_t TRG1;
+    stc_mft_ppg_trg1_field_t TRG1_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t REVC1;
+    stc_mft_ppg_revc1_field_t REVC1_f;
+  };
+        uint8_t RESERVED19[186];
+  union {
+    __IO  uint8_t PPGC1;
+    stc_mft_ppg_ppgc1_field_t PPGC1_f;
+  };
+  union {
+    __IO  uint8_t PPGC0;
+    stc_mft_ppg_ppgc0_field_t PPGC0_f;
+  };
+        uint8_t RESERVED20[2];
+  union {
+    __IO  uint8_t PPGC3;
+    stc_mft_ppg_ppgc3_field_t PPGC3_f;
+  };
+  union {
+    __IO  uint8_t PPGC2;
+    stc_mft_ppg_ppgc2_field_t PPGC2_f;
+  };
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t PRL0;
+    struct {
+      __IO  uint8_t PRLL0;
+      __IO  uint8_t PRLH0;
+    };
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t PRL1;
+    struct {
+      __IO  uint8_t PRLL1;
+      __IO  uint8_t PRLH1;
+    };
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t PRL2;
+    struct {
+      __IO  uint8_t PRLL2;
+      __IO  uint8_t PRLH2;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t PRL3;
+    struct {
+      __IO  uint8_t PRLL3;
+      __IO  uint8_t PRLH3;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO  uint8_t GATEC0;
+    stc_mft_ppg_gatec0_field_t GATEC0_f;
+  };
+        uint8_t RESERVED26[39];
+  union {
+    __IO  uint8_t PPGC5;
+    stc_mft_ppg_ppgc5_field_t PPGC5_f;
+  };
+  union {
+    __IO  uint8_t PPGC4;
+    stc_mft_ppg_ppgc4_field_t PPGC4_f;
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO  uint8_t PPGC7;
+    stc_mft_ppg_ppgc7_field_t PPGC7_f;
+  };
+  union {
+    __IO  uint8_t PPGC6;
+    stc_mft_ppg_ppgc6_field_t PPGC6_f;
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t PRL4;
+    struct {
+      __IO  uint8_t PRLL4;
+      __IO  uint8_t PRLH4;
+    };
+  };
+        uint8_t RESERVED29[2];
+  union {
+    __IO uint16_t PRL5;
+    struct {
+      __IO  uint8_t PRLL5;
+      __IO  uint8_t PRLH5;
+    };
+  };
+        uint8_t RESERVED30[2];
+  union {
+    __IO uint16_t PRL6;
+    struct {
+      __IO  uint8_t PRLL6;
+      __IO  uint8_t PRLH6;
+    };
+  };
+        uint8_t RESERVED31[2];
+  union {
+    __IO uint16_t PRL7;
+    struct {
+      __IO  uint8_t PRLL7;
+      __IO  uint8_t PRLH7;
+    };
+  };
+        uint8_t RESERVED32[2];
+  union {
+    __IO  uint8_t GATEC4;
+    stc_mft_ppg_gatec4_field_t GATEC4_f;
+  };
+        uint8_t RESERVED33[39];
+  union {
+    __IO  uint8_t PPGC9;
+    stc_mft_ppg_ppgc9_field_t PPGC9_f;
+  };
+  union {
+    __IO  uint8_t PPGC8;
+    stc_mft_ppg_ppgc8_field_t PPGC8_f;
+  };
+        uint8_t RESERVED34[2];
+  union {
+    __IO  uint8_t PPGC11;
+    stc_mft_ppg_ppgc11_field_t PPGC11_f;
+  };
+  union {
+    __IO  uint8_t PPGC10;
+    stc_mft_ppg_ppgc10_field_t PPGC10_f;
+  };
+        uint8_t RESERVED35[2];
+  union {
+    __IO uint16_t PRL8;
+    struct {
+      __IO  uint8_t PRLL8;
+      __IO  uint8_t PRLH8;
+    };
+  };
+        uint8_t RESERVED36[2];
+  union {
+    __IO uint16_t PRL9;
+    struct {
+      __IO  uint8_t PRLL9;
+      __IO  uint8_t PRLH9;
+    };
+  };
+        uint8_t RESERVED37[2];
+  union {
+    __IO uint16_t PRL10;
+    struct {
+      __IO  uint8_t PRLL10;
+      __IO  uint8_t PRLH10;
+    };
+  };
+        uint8_t RESERVED38[2];
+  union {
+    __IO uint16_t PRL11;
+    struct {
+      __IO  uint8_t PRLL11;
+      __IO  uint8_t PRLH11;
+    };
+  };
+        uint8_t RESERVED39[2];
+  union {
+    __IO  uint8_t GATEC8;
+    stc_mft_ppg_gatec8_field_t GATEC8_f;
+  };
+        uint8_t RESERVED40[39];
+  union {
+    __IO  uint8_t PPGC13;
+    stc_mft_ppg_ppgc13_field_t PPGC13_f;
+  };
+  union {
+    __IO  uint8_t PPGC12;
+    stc_mft_ppg_ppgc12_field_t PPGC12_f;
+  };
+        uint8_t RESERVED41[2];
+  union {
+    __IO  uint8_t PPGC15;
+    stc_mft_ppg_ppgc15_field_t PPGC15_f;
+  };
+  union {
+    __IO  uint8_t PPGC14;
+    stc_mft_ppg_ppgc14_field_t PPGC14_f;
+  };
+        uint8_t RESERVED42[2];
+  union {
+    __IO uint16_t PRL12;
+    struct {
+      __IO  uint8_t PRLL12;
+      __IO  uint8_t PRLH12;
+    };
+  };
+        uint8_t RESERVED43[2];
+  union {
+    __IO uint16_t PRL13;
+    struct {
+      __IO  uint8_t PRLL13;
+      __IO  uint8_t PRLH13;
+    };
+  };
+        uint8_t RESERVED44[2];
+  union {
+    __IO uint16_t PRL14;
+    struct {
+      __IO  uint8_t PRLL14;
+      __IO  uint8_t PRLH14;
+    };
+  };
+        uint8_t RESERVED45[2];
+  union {
+    __IO uint16_t PRL15;
+    struct {
+      __IO  uint8_t PRLL15;
+      __IO  uint8_t PRLH15;
+    };
+  };
+        uint8_t RESERVED46[2];
+  union {
+    __IO  uint8_t GATEC12;
+    stc_mft_ppg_gatec12_field_t GATEC12_f;
+  };
+        uint8_t RESERVED47[39];  
+  union {
+    __IO  uint8_t PPGC17;
+    stc_mft_ppg_ppgc17_field_t PPGC17_f;
+  };
+  union {
+    __IO  uint8_t PPGC16;
+    stc_mft_ppg_ppgc16_field_t PPGC16_f;
+  };
+        uint8_t RESERVED48[2];
+  union {
+    __IO  uint8_t PPGC19;
+    stc_mft_ppg_ppgc19_field_t PPGC19_f;
+  };
+  union {
+    __IO  uint8_t PPGC18;
+    stc_mft_ppg_ppgc18_field_t PPGC18_f;
+  };
+        uint8_t RESERVED49[2];
+  union {
+    __IO uint16_t PRL16;
+    struct {
+      __IO  uint8_t PRLL16;
+      __IO  uint8_t PRLH16;
+    };
+  };
+        uint8_t RESERVED50[2];
+  union {
+    __IO uint16_t PRL17;
+    struct {
+      __IO  uint8_t PRLL17;
+      __IO  uint8_t PRLH17;
+    };
+  };
+        uint8_t RESERVED51[2];
+  union {
+    __IO uint16_t PRL18;
+    struct {
+      __IO  uint8_t PRLL18;
+      __IO  uint8_t PRLH18;
+    };
+  };
+        uint8_t RESERVED52[2];
+  union {
+    __IO uint16_t PRL19;
+    struct {
+      __IO  uint8_t PRLL19;
+      __IO  uint8_t PRLH19;
+    };
+  };
+        uint8_t RESERVED53[2];
+  union {
+    __IO  uint8_t GATEC16;
+    stc_mft_ppg_gatec16_field_t GATEC16_f;
+  };
+        uint8_t RESERVED54[39];
+  union {
+    __IO  uint8_t PPGC21;
+    stc_mft_ppg_ppgc21_field_t PPGC21_f;
+  };
+  union {
+    __IO  uint8_t PPGC20;
+    stc_mft_ppg_ppgc20_field_t PPGC20_f;
+  };
+        uint8_t RESERVED55[2];
+  union {
+    __IO  uint8_t PPGC23;
+    stc_mft_ppg_ppgc23_field_t PPGC23_f;
+  };
+  union {
+    __IO  uint8_t PPGC22;
+    stc_mft_ppg_ppgc22_field_t PPGC22_f;
+  };
+        uint8_t RESERVED56[2];
+  union {
+    __IO uint16_t PRL20;
+    struct {
+      __IO  uint8_t PRLL20;
+      __IO  uint8_t PRLH20;
+    };
+  };
+        uint8_t RESERVED57[2];
+  union {
+    __IO uint16_t PRL21;
+    struct {
+      __IO  uint8_t PRLL21;
+      __IO  uint8_t PRLH21;
+    };
+  };
+        uint8_t RESERVED58[2];
+  union {
+    __IO uint16_t PRL22;
+    struct {
+      __IO  uint8_t PRLL22;
+      __IO  uint8_t PRLH22;
+    };
+  };
+        uint8_t RESERVED59[2];
+  union {
+    __IO uint16_t PRL23;
+    struct {
+      __IO  uint8_t PRLL23;
+      __IO  uint8_t PRLH23;
+    };
+  };
+        uint8_t RESERVED60[2];
+  union {
+    __IO  uint8_t GATEC20;
+    stc_mft_ppg_gatec20_field_t GATEC20_f;
+  };
+}FM3_MFT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PPG_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PPG registers */
+typedef struct
+{
+  __IO uint16_t PRLL;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PRLH;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_ppg_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_ppg_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_ppg_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PPG_TypeDef;
+
+/******************************************************************************
+ * BT_PWM_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWM registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t PDUT;
+        uint8_t RESERVED1[2];
+  __IO uint16_t TMR;
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwm_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwm_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwm_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWM_TypeDef;
+
+/******************************************************************************
+ * BT_RT_MODULE
+ ******************************************************************************/
+/* Base Timer 0 RT registers */
+typedef struct
+{
+  __IO uint16_t PCSR;
+        uint8_t RESERVED0[6];
+  __IO uint16_t TMR;
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_rt_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_rt_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_rt_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_RT_TypeDef;
+
+/******************************************************************************
+ * BT_PWC_MODULE
+ ******************************************************************************/
+/* Base Timer 0 PWC registers */
+typedef struct
+{
+        uint8_t RESERVED0[4];
+  __IO uint16_t DTBF;
+        uint8_t RESERVED1[6];
+  union {
+    __IO uint16_t TMCR;
+    stc_bt_pwc_tmcr_field_t TMCR_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO  uint8_t STC;
+    stc_bt_pwc_stc_field_t STC_f;
+  };
+  union {
+    __IO  uint8_t TMCR2;
+    stc_bt_pwc_tmcr2_field_t TMCR2_f;
+  };
+}FM3_BT_PWC_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL03_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL0123;
+    stc_btiosel03_btsel0123_field_t BTSEL0123_f;
+  };
+}FM3_BTIOSEL03_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL47_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL4567;
+    stc_btiosel47_btsel4567_field_t BTSEL4567_f;
+  };
+}FM3_BTIOSEL47_TypeDef;
+
+/******************************************************************************
+ * BTIOSEL8B_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSEL89AB;
+    stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f;
+  };
+}FM3_BTIOSEL8B_TypeDef;
+
+/******************************************************************************
+ * BTIOSELCF_MODULE
+ ******************************************************************************/
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+typedef struct
+{
+        uint8_t RESERVED0;
+  union {
+    __IO  uint8_t BTSELCDEF;
+    stc_btioselcf_btselcdef_field_t BTSELCDEF_f;
+  };
+}FM3_BTIOSELCF_TypeDef;
+
+/******************************************************************************
+ * SBSSR_MODULE
+ ******************************************************************************/
+/* Software based Simulation Startup (Base Timer) register */
+typedef struct
+{
+  union {
+    __IO uint16_t BTSSSR;
+    stc_sbssr_btsssr_field_t BTSSSR_f;
+  };
+}FM3_SBSSR_TypeDef;
+
+/******************************************************************************
+ * QPRC_MODULE
+ ******************************************************************************/
+/* Quad position and revolution counter channel 0 registers */
+typedef struct
+{
+  __IO uint16_t QPCR;
+        uint8_t RESERVED0[2];
+  __IO uint16_t QRCR;
+        uint8_t RESERVED1[2];
+  __IO uint16_t QPCCR;
+        uint8_t RESERVED2[2];
+  __IO uint16_t QPRCR;
+        uint8_t RESERVED3[2];
+  __IO uint16_t QMPR;
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t QICR;
+      stc_qprc_qicr_field_t QICR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QICRL;
+        stc_qprc_qicrl_field_t QICRL_f;
+      };
+      union {
+        __IO  uint8_t QICRH;
+        stc_qprc_qicrh_field_t QICRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t QCR;
+      stc_qprc_qcr_field_t QCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t QCRL;
+        stc_qprc_qcrl_field_t QCRL_f;
+      };
+      union {
+        __IO  uint8_t QCRH;
+        stc_qprc_qcrh_field_t QCRH_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t QECR;
+    stc_qprc_qecr_field_t QECR_f;
+  };
+        uint8_t RESERVED7[30];
+  __IO uint16_t QRCRR;
+  __IO uint16_t QPCRR;
+}FM3_QPRC_TypeDef;
+
+/******************************************************************************
+ * ADC12_MODULE
+ ******************************************************************************/
+/* 12-bit ADC unit 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t ADSR;
+    stc_adc_adsr_field_t ADSR_f;
+  };
+  union {
+    __IO  uint8_t ADCR;
+    stc_adc_adcr_field_t ADCR_f;
+  };
+        uint8_t RESERVED0[6];
+  union {
+    __IO  uint8_t SFNS;
+    stc_adc_sfns_field_t SFNS_f;
+  };
+  union {
+    __IO  uint8_t SCCR;
+    stc_adc_sccr_field_t SCCR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint32_t SCFD;
+      stc_adc_scfd_field_t SCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t SCFDL;
+        stc_adc_scfdl_field_t SCFDL_f;
+      };
+      union {
+        __IO uint16_t SCFDH;
+        stc_adc_scfdh_field_t SCFDH_f;
+      };
+    };
+  };
+  union {
+    union {
+      __IO uint16_t SCIS23;
+      stc_adc_scis23_field_t SCIS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS2;
+        stc_adc_scis2_field_t SCIS2_f;
+      };
+      union {
+        __IO  uint8_t SCIS3;
+        stc_adc_scis3_field_t SCIS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t SCIS01;
+      stc_adc_scis01_field_t SCIS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t SCIS0;
+        stc_adc_scis0_field_t SCIS0_f;
+      };
+      union {
+        __IO  uint8_t SCIS1;
+        stc_adc_scis1_field_t SCIS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t PFNS;
+    stc_adc_pfns_field_t PFNS_f;
+  };
+  union {
+    __IO  uint8_t PCCR;
+    stc_adc_pccr_field_t PCCR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint32_t PCFD;
+      stc_adc_pcfd_field_t PCFD_f;
+    };
+    struct {
+      union {
+        __IO uint16_t PCFDL;
+        stc_adc_pcfdl_field_t PCFDL_f;
+      };
+      union {
+        __IO uint16_t PCFDH;
+        stc_adc_pcfdh_field_t PCFDH_f;
+      };
+    };
+  };
+  union {
+    __IO  uint8_t PCIS;
+    stc_adc_pcis_field_t PCIS_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t CMPCR;
+    stc_adc_cmpcr_field_t CMPCR_f;
+  };
+        uint8_t RESERVED6;
+  union {
+    __IO uint16_t CMPD;
+    stc_adc_cmpd_field_t CMPD_f;
+  };
+  union {
+    union {
+      __IO uint16_t ADSS23;
+      stc_adc_adss23_field_t ADSS23_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS2;
+        stc_adc_adss2_field_t ADSS2_f;
+      };
+      union {
+        __IO  uint8_t ADSS3;
+        stc_adc_adss3_field_t ADSS3_f;
+      };
+    };
+  };
+        uint8_t RESERVED7[2];
+  union {
+    union {
+      __IO uint16_t ADSS01;
+      stc_adc_adss01_field_t ADSS01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADSS0;
+        stc_adc_adss0_field_t ADSS0_f;
+      };
+      union {
+        __IO  uint8_t ADSS1;
+        stc_adc_adss1_field_t ADSS1_f;
+      };
+    };
+  };
+        uint8_t RESERVED8[2];
+  union {
+    union {
+      __IO uint16_t ADST01;
+      stc_adc_adst01_field_t ADST01_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t ADST1;
+        stc_adc_adst1_field_t ADST1_f;
+      };
+      union {
+        __IO  uint8_t ADST0;
+        stc_adc_adst0_field_t ADST0_f;
+      };
+    };
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO  uint8_t ADCT;
+    stc_adc_adct_field_t ADCT_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t PRTSL;
+    stc_adc_prtsl_field_t PRTSL_f;
+  };
+  union {
+    __IO  uint8_t SCTSL;
+    stc_adc_sctsl_field_t SCTSL_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO  uint8_t ADCEN;
+    stc_adc_adcen_field_t ADCEN_f;
+  };
+}FM3_ADC_TypeDef;
+
+/******************************************************************************
+ * CRTRIM_MODULE
+ ******************************************************************************/
+/* CR trimming registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t MCR_PSR;
+    stc_crtrim_mcr_psr_field_t MCR_PSR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO uint16_t MCR_FTRM;
+    stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f;
+  };
+        uint8_t RESERVED1[6];
+  __IO uint32_t MCR_RLR;
+}FM3_CRTRIM_TypeDef;
+
+/******************************************************************************
+ * EXTI_MODULE
+ ******************************************************************************/
+/* External interrupt registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ENIR;
+    stc_exti_enir_field_t ENIR_f;
+  };
+  union {
+    __IO uint32_t EIRR;
+    stc_exti_eirr_field_t EIRR_f;
+  };
+  union {
+    __IO uint32_t EICL;
+    stc_exti_eicl_field_t EICL_f;
+  };
+  union {
+    __IO uint32_t ELVR;
+    stc_exti_elvr_field_t ELVR_f;
+  };
+  union {
+    __IO uint32_t ELVR1;
+    stc_exti_elvr1_field_t ELVR1_f;
+  };
+  union {
+    __IO  uint8_t NMIRR;
+    stc_exti_nmirr_field_t NMIRR_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t NMICL;
+    stc_exti_nmicl_field_t NMICL_f;
+  };
+}FM3_EXTI_TypeDef;
+
+/******************************************************************************
+ * INTREQ_MODULE
+ ******************************************************************************/
+/* Interrupt request read registers */
+typedef struct
+{
+  union {
+    __IO uint32_t DRQSEL;
+    stc_intreq_drqsel_field_t DRQSEL_f;
+  };
+        uint8_t RESERVED0[7];
+  union {
+    __IO  uint8_t ODDPKS;
+    stc_intreq_oddpks_field_t ODDPKS_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t EXC02MON;
+    stc_intreq_exc02mon_field_t EXC02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ00MON;
+    stc_intreq_irq00mon_field_t IRQ00MON_f;
+  };
+  union {
+    __IO uint32_t IRQ01MON;
+    stc_intreq_irq01mon_field_t IRQ01MON_f;
+  };
+  union {
+    __IO uint32_t IRQ02MON;
+    stc_intreq_irq02mon_field_t IRQ02MON_f;
+  };
+  union {
+    __IO uint32_t IRQ03MON;
+    stc_intreq_irq03mon_field_t IRQ03MON_f;
+  };
+  union {
+    __IO uint32_t IRQ04MON;
+    stc_intreq_irq04mon_field_t IRQ04MON_f;
+  };
+  union {
+    __IO uint32_t IRQ05MON;
+    stc_intreq_irq05mon_field_t IRQ05MON_f;
+  };
+  union {
+    __IO uint32_t IRQ06MON;
+    stc_intreq_irq06mon_field_t IRQ06MON_f;
+  };
+  union {
+    __IO uint32_t IRQ07MON;
+    stc_intreq_irq07mon_field_t IRQ07MON_f;
+  };
+  union {
+    __IO uint32_t IRQ08MON;
+    stc_intreq_irq08mon_field_t IRQ08MON_f;
+  };
+  union {
+    __IO uint32_t IRQ09MON;
+    stc_intreq_irq09mon_field_t IRQ09MON_f;
+  };
+  union {
+    __IO uint32_t IRQ10MON;
+    stc_intreq_irq10mon_field_t IRQ10MON_f;
+  };
+  union {
+    __IO uint32_t IRQ11MON;
+    stc_intreq_irq11mon_field_t IRQ11MON_f;
+  };
+  union {
+    __IO uint32_t IRQ12MON;
+    stc_intreq_irq12mon_field_t IRQ12MON_f;
+  };
+  union {
+    __IO uint32_t IRQ13MON;
+    stc_intreq_irq13mon_field_t IRQ13MON_f;
+  };
+  union {
+    __IO uint32_t IRQ14MON;
+    stc_intreq_irq14mon_field_t IRQ14MON_f;
+  };
+  union {
+    __IO uint32_t IRQ15MON;
+    stc_intreq_irq15mon_field_t IRQ15MON_f;
+  };
+  union {
+    __IO uint32_t IRQ16MON;
+    stc_intreq_irq16mon_field_t IRQ16MON_f;
+  };
+  union {
+    __IO uint32_t IRQ17MON;
+    stc_intreq_irq17mon_field_t IRQ17MON_f;
+  };
+  union {
+    __IO uint32_t IRQ18MON;
+    stc_intreq_irq18mon_field_t IRQ18MON_f;
+  };
+  union {
+    __IO uint32_t IRQ19MON;
+    stc_intreq_irq19mon_field_t IRQ19MON_f;
+  };
+  union {
+    __IO uint32_t IRQ20MON;
+    stc_intreq_irq20mon_field_t IRQ20MON_f;
+  };
+  union {
+    __IO uint32_t IRQ21MON;
+    stc_intreq_irq21mon_field_t IRQ21MON_f;
+  };
+  union {
+    __IO uint32_t IRQ22MON;
+    stc_intreq_irq22mon_field_t IRQ22MON_f;
+  };
+  union {
+    __IO uint32_t IRQ23MON;
+    stc_intreq_irq23mon_field_t IRQ23MON_f;
+  };
+  union {
+    __IO uint32_t IRQ24MON;
+    stc_intreq_irq24mon_field_t IRQ24MON_f;
+  };
+  union {
+    __IO uint32_t IRQ25MON;
+    stc_intreq_irq25mon_field_t IRQ25MON_f;
+  };
+  union {
+    __IO uint32_t IRQ26MON;
+    stc_intreq_irq26mon_field_t IRQ26MON_f;
+  };
+  union {
+    __IO uint32_t IRQ27MON;
+    stc_intreq_irq27mon_field_t IRQ27MON_f;
+  };
+  union {
+    __IO uint32_t IRQ28MON;
+    stc_intreq_irq28mon_field_t IRQ28MON_f;
+  };
+  union {
+    __IO uint32_t IRQ29MON;
+    stc_intreq_irq29mon_field_t IRQ29MON_f;
+  };
+  union {
+    __IO uint32_t IRQ30MON;
+    stc_intreq_irq30mon_field_t IRQ30MON_f;
+  };
+  union {
+    __IO uint32_t IRQ31MON;
+    stc_intreq_irq31mon_field_t IRQ31MON_f;
+  };
+  union {
+    __IO uint32_t IRQ32MON;
+    stc_intreq_irq32mon_field_t IRQ32MON_f;
+  };
+  union {
+    __IO uint32_t IRQ33MON;
+    stc_intreq_irq33mon_field_t IRQ33MON_f;
+  };
+  union {
+    __IO uint32_t IRQ34MON;
+    stc_intreq_irq34mon_field_t IRQ34MON_f;
+  };
+  union {
+    __IO uint32_t IRQ35MON;
+    stc_intreq_irq35mon_field_t IRQ35MON_f;
+  };
+  union {
+    __IO uint32_t IRQ36MON;
+    stc_intreq_irq36mon_field_t IRQ36MON_f;
+  };
+  union {
+    __IO uint32_t IRQ37MON;
+    stc_intreq_irq37mon_field_t IRQ37MON_f;
+  };
+  union {
+    __IO uint32_t IRQ38MON;
+    stc_intreq_irq38mon_field_t IRQ38MON_f;
+  };
+  union {
+    __IO uint32_t IRQ39MON;
+    stc_intreq_irq39mon_field_t IRQ39MON_f;
+  };
+  union {
+    __IO uint32_t IRQ40MON;
+    stc_intreq_irq40mon_field_t IRQ40MON_f;
+  };
+  union {
+    __IO uint32_t IRQ41MON;
+    stc_intreq_irq41mon_field_t IRQ41MON_f;
+  };
+  union {
+    __IO uint32_t IRQ42MON;
+    stc_intreq_irq42mon_field_t IRQ42MON_f;
+  };
+  union {
+    __IO uint32_t IRQ43MON;
+    stc_intreq_irq43mon_field_t IRQ43MON_f;
+  };
+  union {
+    __IO uint32_t IRQ44MON;
+    stc_intreq_irq44mon_field_t IRQ44MON_f;
+  };
+  union {
+    __IO uint32_t IRQ45MON;
+    stc_intreq_irq45mon_field_t IRQ45MON_f;
+  };
+  union {
+    __IO uint32_t IRQ46MON;
+    stc_intreq_irq46mon_field_t IRQ46MON_f;
+  };
+    __IO uint32_t IRQ47MON;
+        uint8_t RESERVED2[300];
+  union {
+    __IO uint32_t DRQSEL1;
+    stc_intreq_drqsel1_field_t DRQSEL1_f;
+  };
+  union {
+    __IO uint32_t DQESEL;
+    stc_intreq_dqesel_field_t DQESEL_f;
+  };
+        uint8_t RESERVED3[7];
+  union {
+    __IO  uint8_t ODDPKS1;
+    stc_intreq_oddpks1_field_t ODDPKS1_f;
+  };
+}FM3_INTREQ_TypeDef;
+
+/******************************************************************************
+ * GPIO_MODULE
+ ******************************************************************************/
+/* General purpose I/O registers */
+typedef struct
+{
+  union {
+    __IO uint32_t PFR0;
+    stc_gpio_pfr0_field_t PFR0_f;
+  };
+  union {
+    __IO uint32_t PFR1;
+    stc_gpio_pfr1_field_t PFR1_f;
+  };
+  union {
+    __IO uint32_t PFR2;
+    stc_gpio_pfr2_field_t PFR2_f;
+  };
+  union {
+    __IO uint32_t PFR3;
+    stc_gpio_pfr3_field_t PFR3_f;
+  };
+  union {
+    __IO uint32_t PFR4;
+    stc_gpio_pfr4_field_t PFR4_f;
+  };
+  union {
+    __IO uint32_t PFR5;
+    stc_gpio_pfr5_field_t PFR5_f;
+  };
+  union {
+    __IO uint32_t PFR6;
+    stc_gpio_pfr6_field_t PFR6_f;
+  };
+  union {
+    __IO uint32_t PFR7;
+    stc_gpio_pfr7_field_t PFR7_f;
+  };
+  union {
+    __IO uint32_t PFR8;
+    stc_gpio_pfr8_field_t PFR8_f;
+  };
+  union {
+    __IO uint32_t PFR9;
+    stc_gpio_pfr9_field_t PFR9_f;
+  };
+  union {
+    __IO uint32_t PFRA;
+    stc_gpio_pfra_field_t PFRA_f;
+  };
+  union {
+    __IO uint32_t PFRB;
+    stc_gpio_pfrb_field_t PFRB_f;
+  };
+  union {
+    __IO uint32_t PFRC;
+    stc_gpio_pfrc_field_t PFRC_f;
+  };
+  union {
+    __IO uint32_t PFRD;
+    stc_gpio_pfrd_field_t PFRD_f;
+  };
+  union {
+    __IO uint32_t PFRE;
+    stc_gpio_pfre_field_t PFRE_f;
+  };
+  union {
+    __IO uint32_t PFRF;
+    stc_gpio_pfrf_field_t PFRF_f;
+  };
+        uint8_t RESERVED0[192];
+  union {
+    __IO uint32_t PCR0;
+    stc_gpio_pcr0_field_t PCR0_f;
+  };
+  union {
+    __IO uint32_t PCR1;
+    stc_gpio_pcr1_field_t PCR1_f;
+  };
+  union {
+    __IO uint32_t PCR2;
+    stc_gpio_pcr2_field_t PCR2_f;
+  };
+  union {
+    __IO uint32_t PCR3;
+    stc_gpio_pcr3_field_t PCR3_f;
+  };
+  union {
+    __IO uint32_t PCR4;
+    stc_gpio_pcr4_field_t PCR4_f;
+  };
+  union {
+    __IO uint32_t PCR5;
+    stc_gpio_pcr5_field_t PCR5_f;
+  };
+  union {
+    __IO uint32_t PCR6;
+    stc_gpio_pcr6_field_t PCR6_f;
+  };
+  union {
+    __IO uint32_t PCR7;
+    stc_gpio_pcr7_field_t PCR7_f;
+  };
+  __IO uint32_t PCR8;
+  union {
+    __IO uint32_t PCR9;
+    stc_gpio_pcr9_field_t PCR9_f;
+  };
+  union {
+    __IO uint32_t PCRA;
+    stc_gpio_pcra_field_t PCRA_f;
+  };
+  union {
+    __IO uint32_t PCRB;
+    stc_gpio_pcrb_field_t PCRB_f;
+  };
+  union {
+    __IO uint32_t PCRC;
+    stc_gpio_pcrc_field_t PCRC_f;
+  };
+  union {
+    __IO uint32_t PCRD;
+    stc_gpio_pcrd_field_t PCRD_f;
+  };
+  union {
+    __IO uint32_t PCRE;
+    stc_gpio_pcre_field_t PCRE_f;
+  };
+  __IO uint32_t PCRF;
+        uint8_t RESERVED1[192];
+  union {
+    __IO uint32_t DDR0;
+    stc_gpio_ddr0_field_t DDR0_f;
+  };
+  union {
+    __IO uint32_t DDR1;
+    stc_gpio_ddr1_field_t DDR1_f;
+  };
+  union {
+    __IO uint32_t DDR2;
+    stc_gpio_ddr2_field_t DDR2_f;
+  };
+  union {
+    __IO uint32_t DDR3;
+    stc_gpio_ddr3_field_t DDR3_f;
+  };
+  union {
+    __IO uint32_t DDR4;
+    stc_gpio_ddr4_field_t DDR4_f;
+  };
+  union {
+    __IO uint32_t DDR5;
+    stc_gpio_ddr5_field_t DDR5_f;
+  };
+  union {
+    __IO uint32_t DDR6;
+    stc_gpio_ddr6_field_t DDR6_f;
+  };
+  union {
+    __IO uint32_t DDR7;
+    stc_gpio_ddr7_field_t DDR7_f;
+  };
+  union {
+    __IO uint32_t DDR8;
+    stc_gpio_ddr8_field_t DDR8_f;
+  };
+  union {
+    __IO uint32_t DDR9;
+    stc_gpio_ddr9_field_t DDR9_f;
+  };
+  union {
+    __IO uint32_t DDRA;
+    stc_gpio_ddra_field_t DDRA_f;
+  };
+  union {
+    __IO uint32_t DDRB;
+    stc_gpio_ddrb_field_t DDRB_f;
+  };
+  union {
+    __IO uint32_t DDRC;
+    stc_gpio_ddrc_field_t DDRC_f;
+  };
+  union {
+    __IO uint32_t DDRD;
+    stc_gpio_ddrd_field_t DDRD_f;
+  };
+  union {
+    __IO uint32_t DDRE;
+    stc_gpio_ddre_field_t DDRE_f;
+  };
+  union {
+    __IO uint32_t DDRF;
+    stc_gpio_ddrf_field_t DDRF_f;
+  };
+        uint8_t RESERVED2[192];
+  union {
+    __IO uint32_t PDIR0;
+    stc_gpio_pdir0_field_t PDIR0_f;
+  };
+  union {
+    __IO uint32_t PDIR1;
+    stc_gpio_pdir1_field_t PDIR1_f;
+  };
+  union {
+    __IO uint32_t PDIR2;
+    stc_gpio_pdir2_field_t PDIR2_f;
+  };
+  union {
+    __IO uint32_t PDIR3;
+    stc_gpio_pdir3_field_t PDIR3_f;
+  };
+  union {
+    __IO uint32_t PDIR4;
+    stc_gpio_pdir4_field_t PDIR4_f;
+  };
+  union {
+    __IO uint32_t PDIR5;
+    stc_gpio_pdir5_field_t PDIR5_f;
+  };
+  union {
+    __IO uint32_t PDIR6;
+    stc_gpio_pdir6_field_t PDIR6_f;
+  };
+  union {
+    __IO uint32_t PDIR7;
+    stc_gpio_pdir7_field_t PDIR7_f;
+  };
+  union {
+    __IO uint32_t PDIR8;
+    stc_gpio_pdir8_field_t PDIR8_f;
+  };
+  union {
+    __IO uint32_t PDIR9;
+    stc_gpio_pdir9_field_t PDIR9_f;
+  };
+  union {
+    __IO uint32_t PDIRA;
+    stc_gpio_pdira_field_t PDIRA_f;
+  };
+  union {
+    __IO uint32_t PDIRB;
+    stc_gpio_pdirb_field_t PDIRB_f;
+  };
+  union {
+    __IO uint32_t PDIRC;
+    stc_gpio_pdirc_field_t PDIRC_f;
+  };
+  union {
+    __IO uint32_t PDIRD;
+    stc_gpio_pdird_field_t PDIRD_f;
+  };
+  union {
+    __IO uint32_t PDIRE;
+    stc_gpio_pdire_field_t PDIRE_f;
+  };
+  union {
+    __IO uint32_t PDIRF;
+    stc_gpio_pdirf_field_t PDIRF_f;
+  };
+        uint8_t RESERVED3[192];
+  union {
+    __IO uint32_t PDOR0;
+    stc_gpio_pdor0_field_t PDOR0_f;
+  };
+  union {
+    __IO uint32_t PDOR1;
+    stc_gpio_pdor1_field_t PDOR1_f;
+  };
+  union {
+    __IO uint32_t PDOR2;
+    stc_gpio_pdor2_field_t PDOR2_f;
+  };
+  union {
+    __IO uint32_t PDOR3;
+    stc_gpio_pdor3_field_t PDOR3_f;
+  };
+  union {
+    __IO uint32_t PDOR4;
+    stc_gpio_pdor4_field_t PDOR4_f;
+  };
+  union {
+    __IO uint32_t PDOR5;
+    stc_gpio_pdor5_field_t PDOR5_f;
+  };
+  union {
+    __IO uint32_t PDOR6;
+    stc_gpio_pdor6_field_t PDOR6_f;
+  };
+  union {
+    __IO uint32_t PDOR7;
+    stc_gpio_pdor7_field_t PDOR7_f;
+  };
+  union {
+    __IO uint32_t PDOR8;
+    stc_gpio_pdor8_field_t PDOR8_f;
+  };
+  union {
+    __IO uint32_t PDOR9;
+    stc_gpio_pdor9_field_t PDOR9_f;
+  };
+  union {
+    __IO uint32_t PDORA;
+    stc_gpio_pdora_field_t PDORA_f;
+  };
+  union {
+    __IO uint32_t PDORB;
+    stc_gpio_pdorb_field_t PDORB_f;
+  };
+  union {
+    __IO uint32_t PDORC;
+    stc_gpio_pdorc_field_t PDORC_f;
+  };
+  union {
+    __IO uint32_t PDORD;
+    stc_gpio_pdord_field_t PDORD_f;
+  };
+  union {
+    __IO uint32_t PDORE;
+    stc_gpio_pdore_field_t PDORE_f;
+  };
+  union {
+    __IO uint32_t PDORF;
+    stc_gpio_pdorf_field_t PDORF_f;
+  };
+        uint8_t RESERVED4[192];
+  union {
+    __IO uint32_t ADE;
+    stc_gpio_ade_field_t ADE_f;
+  };
+        uint8_t RESERVED5[124];
+  union {
+    __IO uint32_t SPSR;
+    stc_gpio_spsr_field_t SPSR_f;
+  };
+        uint8_t RESERVED6[124];
+  union {
+    __IO uint32_t EPFR00;
+    stc_gpio_epfr00_field_t EPFR00_f;
+  };
+  union {
+    __IO uint32_t EPFR01;
+    stc_gpio_epfr01_field_t EPFR01_f;
+  };
+  union {
+    __IO uint32_t EPFR02;
+    stc_gpio_epfr02_field_t EPFR02_f;
+  };
+  union {
+    __IO uint32_t EPFR03;
+    stc_gpio_epfr03_field_t EPFR03_f;
+  };
+  union {
+    __IO uint32_t EPFR04;
+    stc_gpio_epfr04_field_t EPFR04_f;
+  };
+  union {
+    __IO uint32_t EPFR05;
+    stc_gpio_epfr05_field_t EPFR05_f;
+  };
+  union {
+    __IO uint32_t EPFR06;
+    stc_gpio_epfr06_field_t EPFR06_f;
+  };
+  union {
+    __IO uint32_t EPFR07;
+    stc_gpio_epfr07_field_t EPFR07_f;
+  };
+  union {
+    __IO uint32_t EPFR08;
+    stc_gpio_epfr08_field_t EPFR08_f;
+  };
+  union {
+    __IO uint32_t EPFR09;
+    stc_gpio_epfr09_field_t EPFR09_f;
+  };
+  union {
+    __IO uint32_t EPFR10;
+    stc_gpio_epfr10_field_t EPFR10_f;
+  };
+  union {
+    __IO uint32_t EPFR11;
+    stc_gpio_epfr11_field_t EPFR11_f;
+  };
+  union {
+    __IO uint32_t EPFR12;
+    stc_gpio_epfr12_field_t EPFR12_f;
+  };
+  union {
+    __IO uint32_t EPFR13;
+    stc_gpio_epfr13_field_t EPFR13_f;
+  };
+  union {
+    __IO uint32_t EPFR14;
+    stc_gpio_epfr14_field_t EPFR14_f;
+  };
+  union {
+    __IO uint32_t EPFR15;
+    stc_gpio_epfr15_field_t EPFR15_f;
+  };
+        uint8_t RESERVED7[192];
+  union {
+    __IO uint32_t PZR0;
+    stc_gpio_pzr0_field_t PZR0_f;
+  };
+  union {
+    __IO uint32_t PZR1;
+    stc_gpio_pzr1_field_t PZR1_f;
+  };
+  union {
+    __IO uint32_t PZR2;
+    stc_gpio_pzr2_field_t PZR2_f;
+  };
+  union {
+    __IO uint32_t PZR3;
+    stc_gpio_pzr3_field_t PZR3_f;
+  };
+  union {
+    __IO uint32_t PZR4;
+    stc_gpio_pzr4_field_t PZR4_f;
+  };
+  union {
+    __IO uint32_t PZR5;
+    stc_gpio_pzr5_field_t PZR5_f;
+  };
+  union {
+    __IO uint32_t PZR6;
+    stc_gpio_pzr6_field_t PZR6_f;
+  };
+  union {
+    __IO uint32_t PZR7;
+    stc_gpio_pzr7_field_t PZR7_f;
+  };
+  union {
+    __IO uint32_t PZR8;
+    stc_gpio_pzr8_field_t PZR8_f;
+  };
+  union {
+    __IO uint32_t PZR9;
+    stc_gpio_pzr9_field_t PZR9_f;
+  };
+  union {
+    __IO uint32_t PZRA;
+    stc_gpio_pzra_field_t PZRA_f;
+  };
+  union {
+    __IO uint32_t PZRB;
+    stc_gpio_pzrb_field_t PZRB_f;
+  };
+  union {
+    __IO uint32_t PZRC;
+    stc_gpio_pzrc_field_t PZRC_f;
+  };
+  union {
+    __IO uint32_t PZRD;
+    stc_gpio_pzrd_field_t PZRD_f;
+  };
+  union {
+    __IO uint32_t PZRE;
+    stc_gpio_pzre_field_t PZRE_f;
+  };
+  union {
+    __IO uint32_t PZRF;
+    stc_gpio_pzrf_field_t PZRF_f;
+  };
+}FM3_GPIO_TypeDef;
+
+/******************************************************************************
+ * LVD_MODULE
+ ******************************************************************************/
+/* Low voltage detection registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t LVD_CTL;
+    stc_lvd_lvd_ctl_field_t LVD_CTL_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t LVD_STR;
+    stc_lvd_lvd_str_field_t LVD_STR_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t LVD_CLR;
+    stc_lvd_lvd_clr_field_t LVD_CLR_f;
+  };
+        uint8_t RESERVED2[3];
+  __IO uint32_t LVD_RLR;
+  union {
+    __IO  uint8_t LVD_STR2;
+    stc_lvd_lvd_str2_field_t LVD_STR2_f;
+  };
+}FM3_LVD_TypeDef;
+
+/******************************************************************************
+ * USBETHERNETCLK
+ ******************************************************************************/
+/* USB Ethernet clock registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t UCCR;
+    stc_usbethernetclk_uccr_field_t UCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  union {
+    __IO  uint8_t UPCR1;
+    stc_usbethernetclk_upcr1_field_t UPCR1_f;
+  };
+        uint8_t RESERVED1[3];
+  union {
+    __IO  uint8_t UPCR2;
+    stc_usbethernetclk_upcr2_field_t UPCR2_f;
+  };
+        uint8_t RESERVED2[3];
+  union {
+    __IO  uint8_t UPCR3;
+    stc_usbethernetclk_upcr3_field_t UPCR3_f;
+  };
+        uint8_t RESERVED3[3];
+  union {
+    __IO  uint8_t UPCR4;
+    stc_usbethernetclk_upcr4_field_t UPCR4_f;
+  };
+        uint8_t RESERVED4[3];
+  union {
+    __IO  uint8_t UP_STR;
+    stc_usbethernetclk_up_str_field_t UP_STR_f;
+  };
+        uint8_t RESERVED5[3];
+  union {
+    __IO  uint8_t UPINT_ENR;
+    stc_usbethernetclk_upint_enr_field_t UPINT_ENR_f;
+  };
+        uint8_t RESERVED6[3];
+  union {
+    __IO  uint8_t UPINT_CLR;
+    stc_usbethernetclk_upint_clr_field_t UPINT_CLR_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO  uint8_t UPINT_STR;
+    stc_usbethernetclk_upint_str_field_t UPINT_STR_f;
+  };
+        uint8_t RESERVED8[3];
+  union {
+    __IO  uint8_t UPCR5;
+    stc_usbethernetclk_upcr5_field_t UPCR5_f;
+  };
+        uint8_t RESERVED9[3];
+  union {
+    __IO  uint8_t UPCR6;
+    stc_usbethernetclk_upcr6_field_t UPCR6_f;
+  };
+        uint8_t RESERVED10[3];
+  union {
+    __IO  uint8_t UPCR7;
+    stc_usbethernetclk_upcr7_field_t UPCR7_f;
+  };
+        uint8_t RESERVED11[3];
+  union {
+    __IO  uint8_t USBEN0;
+    stc_usbethernetclk_usben0_field_t USBEN0_f;
+  };
+        uint8_t RESERVED12[3];
+  union {
+    __IO  uint8_t USBEN1;
+    stc_usbethernetclk_usben1_field_t USBEN1_f;
+  };
+}FM3_USBETHERNETCLK_TypeDef;
+
+/******************************************************************************
+ * MFS03_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs03_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs03_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_UART_TypeDef;
+
+/******************************************************************************
+ * MFS03_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+}FM3_MFS03_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS03_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs03_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs03_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs03_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs03_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+}FM3_MFS03_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS03_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 0 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs03_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs03_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs03_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs03_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs03_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs03_i2c_ismk_field_t ISMK_f;
+  };
+}FM3_MFS03_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS47_UART_MODULE
+ ******************************************************************************/
+/* UART asynchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_uart_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_uart_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_uart_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_uart_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    union {
+      __IO uint16_t RDR;
+      stc_mfs47_uart_rdr_field_t RDR_f;
+    };
+    union {
+      __IO uint16_t TDR;
+      stc_mfs47_uart_tdr_field_t TDR_f;
+    };
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_uart_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_uart_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_uart_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_uart_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_uart_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_uart_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_uart_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_uart_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_UART_TypeDef;
+
+/******************************************************************************
+ * MFS47_CSIO_MODULE
+ ******************************************************************************/
+/* UART synchronous channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_csio_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_csio_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_csio_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_csio_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_csio_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_csio_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_csio_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_csio_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_csio_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_csio_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_CSIO_TypeDef;
+
+/******************************************************************************
+ * MFS47_LIN_MODULE
+ ******************************************************************************/
+/* UART LIN channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_lin_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t SCR;
+    stc_mfs47_lin_scr_field_t SCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t ESCR;
+    stc_mfs47_lin_escr_field_t ESCR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_lin_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t BGR;
+      stc_mfs47_lin_bgr_field_t BGR_f;
+    };
+    struct {
+      __IO  uint8_t BGR0;
+      union {
+        __IO  uint8_t BGR1;
+        stc_mfs47_lin_bgr1_field_t BGR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[6];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_lin_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_lin_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_lin_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_lin_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_lin_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_lin_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_LIN_TypeDef;
+
+/******************************************************************************
+ * MFS47_I2C_MODULE
+ ******************************************************************************/
+/* I2C channel 4 registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t SMR;
+    stc_mfs47_i2c_smr_field_t SMR_f;
+  };
+  union {
+    __IO  uint8_t IBCR;
+    stc_mfs47_i2c_ibcr_field_t IBCR_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t IBSR;
+    stc_mfs47_i2c_ibsr_field_t IBSR_f;
+  };
+  union {
+    __IO  uint8_t SSR;
+    stc_mfs47_i2c_ssr_field_t SSR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t RDR;
+    __IO uint16_t TDR;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t BGR;
+    struct {
+      __IO  uint8_t BGR0;
+      __IO  uint8_t BGR1;
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t ISBA;
+    stc_mfs47_i2c_isba_field_t ISBA_f;
+  };
+  union {
+    __IO  uint8_t ISMK;
+    stc_mfs47_i2c_ismk_field_t ISMK_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t FCR;
+      stc_mfs47_i2c_fcr_field_t FCR_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FCR0;
+        stc_mfs47_i2c_fcr0_field_t FCR0_f;
+      };
+      union {
+        __IO  uint8_t FCR1;
+        stc_mfs47_i2c_fcr1_field_t FCR1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t FBYTE;
+      stc_mfs47_i2c_fbyte_field_t FBYTE_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t FBYTE1;
+        stc_mfs47_i2c_fbyte1_field_t FBYTE1_f;
+      };
+      union {
+        __IO  uint8_t FBYTE2;
+        stc_mfs47_i2c_fbyte2_field_t FBYTE2_f;
+      };
+    };
+  };
+}FM3_MFS47_I2C_TypeDef;
+
+/******************************************************************************
+ * MFS_NFC_MODULE
+ ******************************************************************************/
+/* MFS_NFC_MODULE register bit fields */
+typedef struct
+{
+  union {
+    __IO  uint16_t I2CDNF;
+    stc_mfs_nfc_i2cdnf_field_t I2CDNF_f;
+  };
+}FM3_MFS_NFC_TypeDef;
+
+/******************************************************************************
+ * CRC_MODULE
+ ******************************************************************************/
+/* CRC registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t CRCCR;
+    stc_crc_crccr_field_t CRCCR_f;
+  };
+        uint8_t RESERVED0[3];
+  __IO uint32_t CRCINIT;
+  union {
+    __IO uint32_t CRCIN;
+    struct {
+      union {
+        __IO uint16_t CRCINL;
+        struct {
+          __IO  uint8_t CRCINLL;
+          __IO  uint8_t CRCINLH;
+        };
+      };
+      union {
+        __IO uint16_t CRCINH;
+        struct {
+          __IO  uint8_t CRCINHL;
+          __IO  uint8_t CRCINHH;
+        };
+      };
+    };
+  };
+  __IO uint32_t CRCR;
+}FM3_CRC_TypeDef;
+
+/******************************************************************************
+ * WC_MODULE
+ ******************************************************************************/
+/* Watch counter registers */
+typedef struct
+{
+  union {
+    __IO  uint8_t WCRD;
+    stc_wc_wcrd_field_t WCRD_f;
+  };
+  union {
+    __IO  uint8_t WCRL;
+    stc_wc_wcrl_field_t WCRL_f;
+  };
+  union {
+    __IO  uint8_t WCCR;
+    stc_wc_wccr_field_t WCCR_f;
+  };
+        uint8_t RESERVED0[13];
+  union {
+    __IO uint16_t CLK_SEL;
+    stc_wc_clk_sel_field_t CLK_SEL_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t CLK_EN;
+    stc_wc_clk_en_field_t CLK_EN_f;
+  };
+}FM3_WC_TypeDef;
+
+/******************************************************************************
+ * EXBUS_MODULE
+ ******************************************************************************/
+/* External bus interface registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MODE0;
+    stc_exbus_mode0_field_t MODE0_f;
+  };
+  union {
+    __IO uint32_t MODE1;
+    stc_exbus_mode1_field_t MODE1_f;
+  };
+  union {
+    __IO uint32_t MODE2;
+    stc_exbus_mode2_field_t MODE2_f;
+  };
+  union {
+    __IO uint32_t MODE3;
+    stc_exbus_mode3_field_t MODE3_f;
+  };
+  union {
+    __IO uint32_t MODE4;
+    stc_exbus_mode4_field_t MODE4_f;
+  };
+  union {
+    __IO uint32_t MODE5;
+    stc_exbus_mode5_field_t MODE5_f;
+  };
+  union {
+    __IO uint32_t MODE6;
+    stc_exbus_mode6_field_t MODE6_f;
+  };
+  union {
+    __IO uint32_t MODE7;
+    stc_exbus_mode7_field_t MODE7_f;
+  };
+  union {
+    __IO uint32_t TIM0;
+    stc_exbus_tim0_field_t TIM0_f;
+  };
+  union {
+    __IO uint32_t TIM1;
+    stc_exbus_tim1_field_t TIM1_f;
+  };
+  union {
+    __IO uint32_t TIM2;
+    stc_exbus_tim2_field_t TIM2_f;
+  };
+  union {
+    __IO uint32_t TIM3;
+    stc_exbus_tim3_field_t TIM3_f;
+  };
+  union {
+    __IO uint32_t TIM4;
+    stc_exbus_tim4_field_t TIM4_f;
+  };
+  union {
+    __IO uint32_t TIM5;
+    stc_exbus_tim5_field_t TIM5_f;
+  };
+  union {
+    __IO uint32_t TIM6;
+    stc_exbus_tim6_field_t TIM6_f;
+  };
+  union {
+    __IO uint32_t TIM7;
+    stc_exbus_tim7_field_t TIM7_f;
+  };
+  union {
+    __IO uint32_t AREA0;
+    stc_exbus_area0_field_t AREA0_f;
+  };
+  union {
+    __IO uint32_t AREA1;
+    stc_exbus_area1_field_t AREA1_f;
+  };
+  union {
+    __IO uint32_t AREA2;
+    stc_exbus_area2_field_t AREA2_f;
+  };
+  union {
+    __IO uint32_t AREA3;
+    stc_exbus_area3_field_t AREA3_f;
+  };
+  union {
+    __IO uint32_t AREA4;
+    stc_exbus_area4_field_t AREA4_f;
+  };
+  union {
+    __IO uint32_t AREA5;
+    stc_exbus_area5_field_t AREA5_f;
+  };
+  union {
+    __IO uint32_t AREA6;
+    stc_exbus_area6_field_t AREA6_f;
+  };
+  union {
+    __IO uint32_t AREA7;
+    stc_exbus_area7_field_t AREA7_f;
+  };
+  union {
+    __IO uint16_t ATIM0;
+    stc_exbus_atim0_field_t ATIM0_f;
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO uint16_t ATIM1;
+    stc_exbus_atim1_field_t ATIM1_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO uint16_t ATIM2;
+    stc_exbus_atim2_field_t ATIM2_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    __IO uint16_t ATIM3;
+    stc_exbus_atim3_field_t ATIM3_f;
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO uint16_t ATIM4;
+    stc_exbus_atim4_field_t ATIM4_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    __IO uint16_t ATIM5;
+    stc_exbus_atim5_field_t ATIM5_f;
+  };
+        uint8_t RESERVED5[2];
+  union {
+    __IO uint16_t ATIM6;
+    stc_exbus_atim6_field_t ATIM6_f;
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO uint16_t ATIM7;
+    stc_exbus_atim7_field_t ATIM7_f;
+  };
+        uint8_t RESERVED7[642];
+  union {
+    __IO  uint8_t DCLKR;
+    stc_exbus_dclkr_field_t DCLKR_f;
+  };
+}FM3_EXBUS_TypeDef;
+
+/******************************************************************************
+ * USB_MODULE
+ ******************************************************************************/
+/* USB channel 0 registers */
+typedef struct
+{
+  union {
+    union {
+      __IO uint16_t HCNT;
+      stc_usb_hcnt_field_t HCNT_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HCNT0;
+        stc_usb_hcnt0_field_t HCNT0_f;
+      };
+      union {
+        __IO  uint8_t HCNT1;
+        stc_usb_hcnt1_field_t HCNT1_f;
+      };
+    };
+  };
+        uint8_t RESERVED0[2];
+  union {
+    __IO  uint8_t HIRQ;
+    stc_usb_hirq_field_t HIRQ_f;
+  };
+  union {
+    __IO  uint8_t HERR;
+    stc_usb_herr_field_t HERR_f;
+  };
+        uint8_t RESERVED1[2];
+  union {
+    __IO  uint8_t HSTATE;
+    stc_usb_hstate_field_t HSTATE_f;
+  };
+  union {
+    __IO  uint8_t HFCOMP;
+    stc_usb_hfcomp_field_t HFCOMP_f;
+  };
+        uint8_t RESERVED2[2];
+  union {
+    union {
+      __IO uint16_t HRTIMER;
+      stc_usb_hrtimer_field_t HRTIMER_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HRTIMER0;
+        stc_usb_hrtimer0_field_t HRTIMER0_f;
+      };
+      union {
+        __IO  uint8_t HRTIMER1;
+        stc_usb_hrtimer1_field_t HRTIMER1_f;
+      };
+    };
+  };
+        uint8_t RESERVED3[2];
+  union {
+    __IO  uint8_t HRTIMER2;
+    stc_usb_hrtimer2_field_t HRTIMER2_f;
+  };
+  union {
+    __IO  uint8_t HADR;
+    stc_usb_hadr_field_t HADR_f;
+  };
+        uint8_t RESERVED4[2];
+  union {
+    union {
+      __IO uint16_t HEOF;
+      stc_usb_heof_field_t HEOF_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HEOF0;
+        stc_usb_heof0_field_t HEOF0_f;
+      };
+      union {
+        __IO  uint8_t HEOF1;
+        stc_usb_heof1_field_t HEOF1_f;
+      };
+    };
+  };
+        uint8_t RESERVED5[2];
+  union {
+    union {
+      __IO uint16_t HFRAME;
+      stc_usb_hframe_field_t HFRAME_f;
+    };
+    struct {
+      union {
+        __IO  uint8_t HFRAME0;
+        stc_usb_hframe0_field_t HFRAME0_f;
+      };
+      union {
+        __IO  uint8_t HFRAME1;
+        stc_usb_hframe1_field_t HFRAME1_f;
+      };
+    };
+  };
+        uint8_t RESERVED6[2];
+  union {
+    __IO  uint8_t HTOKEN;
+    stc_usb_htoken_field_t HTOKEN_f;
+  };
+        uint8_t RESERVED7[3];
+  union {
+    __IO uint16_t UDCC;
+    stc_usb_udcc_field_t UDCC_f;
+  };
+        uint8_t RESERVED8[2];
+  union {
+    __IO uint16_t EP0C;
+    stc_usb_ep0c_field_t EP0C_f;
+  };
+        uint8_t RESERVED9[2];
+  union {
+    __IO uint16_t EP1C;
+    stc_usb_ep1c_field_t EP1C_f;
+  };
+        uint8_t RESERVED10[2];
+  union {
+    __IO uint16_t EP2C;
+    stc_usb_ep2c_field_t EP2C_f;
+  };
+        uint8_t RESERVED11[2];
+  union {
+    __IO uint16_t EP3C;
+    stc_usb_ep3c_field_t EP3C_f;
+  };
+        uint8_t RESERVED12[2];
+  union {
+    __IO uint16_t EP4C;
+    stc_usb_ep4c_field_t EP4C_f;
+  };
+        uint8_t RESERVED13[2];
+  union {
+    __IO uint16_t EP5C;
+    stc_usb_ep5c_field_t EP5C_f;
+  };
+        uint8_t RESERVED14[2];
+  union {
+    __IO uint16_t TMSP;
+    stc_usb_tmsp_field_t TMSP_f;
+  };
+        uint8_t RESERVED15[2];
+  union {
+    __IO  uint8_t UDCS;
+    stc_usb_udcs_field_t UDCS_f;
+  };
+  union {
+    __IO  uint8_t UDCIE;
+    stc_usb_udcie_field_t UDCIE_f;
+  };
+        uint8_t RESERVED16[2];
+  union {
+    __IO uint16_t EP0IS;
+    stc_usb_ep0is_field_t EP0IS_f;
+  };
+        uint8_t RESERVED17[2];
+  union {
+    __IO uint16_t EP0OS;
+    stc_usb_ep0os_field_t EP0OS_f;
+  };
+        uint8_t RESERVED18[2];
+  union {
+    __IO uint16_t EP1S;
+    stc_usb_ep1s_field_t EP1S_f;
+  };
+        uint8_t RESERVED19[2];
+  union {
+    __IO uint16_t EP2S;
+    stc_usb_ep2s_field_t EP2S_f;
+  };
+        uint8_t RESERVED20[2];
+  __IO uint16_t EP3S;
+        uint8_t RESERVED21[2];
+  union {
+    __IO uint16_t EP4S;
+    stc_usb_ep4s_field_t EP4S_f;
+  };
+        uint8_t RESERVED22[2];
+  union {
+    __IO uint16_t EP5S;
+    stc_usb_ep5s_field_t EP5S_f;
+  };
+        uint8_t RESERVED23[2];
+  union {
+    __IO uint16_t EP0DT;
+    struct {
+      __IO  uint8_t EP0DTL;
+      __IO  uint8_t EP0DTH;
+    };
+  };
+        uint8_t RESERVED24[2];
+  union {
+    __IO uint16_t EP1DT;
+    struct {
+      __IO  uint8_t EP1DTL;
+      __IO  uint8_t EP1DTH;
+    };
+  };
+        uint8_t RESERVED25[2];
+  union {
+    __IO uint16_t EP2DT;
+    struct {
+      __IO  uint8_t EP2DTL;
+      __IO  uint8_t EP2DTH;
+    };
+  };
+        uint8_t RESERVED26[2];
+  union {
+    __IO uint16_t EP3DT;
+    struct {
+      __IO  uint8_t EP3DTL;
+      __IO  uint8_t EP3DTH;
+    };
+  };
+        uint8_t RESERVED27[2];
+  union {
+    __IO uint16_t EP4DT;
+    struct {
+      __IO  uint8_t EP4DTL;
+      __IO  uint8_t EP4DTH;
+    };
+  };
+        uint8_t RESERVED28[2];
+  union {
+    __IO uint16_t EP5DT;
+    struct {
+      __IO  uint8_t EP5DTL;
+      __IO  uint8_t EP5DTH;
+    };
+  };
+}FM3_USB_TypeDef;
+
+/******************************************************************************
+ * DMAC_MODULE
+ ******************************************************************************/
+/* DMA controller */
+typedef struct
+{
+  union {
+    __IO uint32_t DMACR;
+    stc_dmac_dmacr_field_t DMACR_f;
+  };
+        uint8_t RESERVED0[12];
+  union {
+    __IO uint32_t DMACA0;
+    stc_dmac_dmaca0_field_t DMACA0_f;
+  };
+  union {
+    __IO uint32_t DMACB0;
+    stc_dmac_dmacb0_field_t DMACB0_f;
+  };
+  __IO uint32_t DMACSA0;
+  __IO uint32_t DMACDA0;
+  union {
+    __IO uint32_t DMACA1;
+    stc_dmac_dmaca1_field_t DMACA1_f;
+  };
+  union {
+    __IO uint32_t DMACB1;
+    stc_dmac_dmacb1_field_t DMACB1_f;
+  };
+  __IO uint32_t DMACSA1;
+  __IO uint32_t DMACDA1;
+  union {
+    __IO uint32_t DMACA2;
+    stc_dmac_dmaca2_field_t DMACA2_f;
+  };
+  union {
+    __IO uint32_t DMACB2;
+    stc_dmac_dmacb2_field_t DMACB2_f;
+  };
+  __IO uint32_t DMACSA2;
+  __IO uint32_t DMACDA2;
+  union {
+    __IO uint32_t DMACA3;
+    stc_dmac_dmaca3_field_t DMACA3_f;
+  };
+  union {
+    __IO uint32_t DMACB3;
+    stc_dmac_dmacb3_field_t DMACB3_f;
+  };
+  __IO uint32_t DMACSA3;
+  __IO uint32_t DMACDA3;
+  union {
+    __IO uint32_t DMACA4;
+    stc_dmac_dmaca4_field_t DMACA4_f;
+  };
+  union {
+    __IO uint32_t DMACB4;
+    stc_dmac_dmacb4_field_t DMACB4_f;
+  };
+  __IO uint32_t DMACSA4;
+  __IO uint32_t DMACDA4;
+  union {
+    __IO uint32_t DMACA5;
+    stc_dmac_dmaca5_field_t DMACA5_f;
+  };
+  union {
+    __IO uint32_t DMACB5;
+    stc_dmac_dmacb5_field_t DMACB5_f;
+  };
+  __IO uint32_t DMACSA5;
+  __IO uint32_t DMACDA5;
+  union {
+    __IO uint32_t DMACA6;
+    stc_dmac_dmaca6_field_t DMACA6_f;
+  };
+  union {
+    __IO uint32_t DMACB6;
+    stc_dmac_dmacb6_field_t DMACB6_f;
+  };
+  __IO uint32_t DMACSA6;
+  __IO uint32_t DMACDA6;
+  union {
+    __IO uint32_t DMACA7;
+    stc_dmac_dmaca7_field_t DMACA7_f;
+  };
+  union {
+    __IO uint32_t DMACB7;
+    stc_dmac_dmacb7_field_t DMACB7_f;
+  };
+  __IO uint32_t DMACSA7;
+  __IO uint32_t DMACDA7;
+}FM3_DMAC_TypeDef;
+
+/******************************************************************************
+ * ETHERNET_MAC_MODULE
+ ******************************************************************************/
+/* ETHERNET-MAC registers */
+typedef struct
+{
+  union {
+    __IO uint32_t MCR;
+    stc_ethernet_mac_mcr_field_t MCR_f;
+  };
+  union {
+    __IO uint32_t MFFR;
+    stc_ethernet_mac_mffr_field_t MFFR_f;
+  };
+  union {
+    __IO uint32_t MHTRH;
+    stc_ethernet_mac_mhtrh_field_t MHTRH_f;
+  };
+  union {
+    __IO uint32_t MHTRL;
+    stc_ethernet_mac_mhtrl_field_t MHTRL_f;
+  };
+  union {
+    __IO uint32_t GAR;
+    stc_ethernet_mac_gar_field_t GAR_f;
+  };
+  union {
+    __IO uint32_t GDR;
+    stc_ethernet_mac_gdr_field_t GDR_f;
+  };
+  union {
+    __IO uint32_t FCR;
+    stc_ethernet_mac_fcr_field_t FCR_f;
+  };
+  union {
+    __IO uint32_t VTR;
+    stc_ethernet_mac_vtr_field_t VTR_f;
+  };
+        uint8_t RESERVED0[8];
+  union {
+    __IO uint32_t RWFFR;
+    stc_ethernet_mac_rwffr_field_t RWFFR_f;
+  };
+  union {
+    __IO uint32_t PMTR;
+    stc_ethernet_mac_pmtr_field_t PMTR_f;
+  };
+  union {
+    __IO uint32_t LPICSR;
+    stc_ethernet_mac_lpicsr_field_t LPICSR_f;
+  };
+  union {
+    __IO uint32_t LPITCR;
+    stc_ethernet_mac_lpitcr_field_t LPITCR_f;
+  };
+  union {
+    __IO uint32_t ISR;
+    stc_ethernet_mac_isr_field_t ISR_f;
+  };
+  union {
+    __IO uint32_t IMR;
+    stc_ethernet_mac_imr_field_t IMR_f;
+  };
+  union {
+    __IO uint32_t MAR0H;
+    stc_ethernet_mac_mar0h_field_t MAR0H_f;
+  };
+  union {
+    __IO uint32_t MAR0L;
+    stc_ethernet_mac_mar0l_field_t MAR0L_f;
+  };
+  union {
+    __IO uint32_t MAR1H;
+    stc_ethernet_mac_mar1h_field_t MAR1H_f;
+  };
+  union {
+    __IO uint32_t MAR1L;
+    stc_ethernet_mac_mar1l_field_t MAR1L_f;
+  };
+  union {
+    __IO uint32_t MAR2H;
+    stc_ethernet_mac_mar2h_field_t MAR2H_f;
+  };
+  union {
+    __IO uint32_t MAR2L;
+    stc_ethernet_mac_mar2l_field_t MAR2L_f;
+  };
+  union {
+    __IO uint32_t MAR3H;
+    stc_ethernet_mac_mar3h_field_t MAR3H_f;
+  };
+  union {
+    __IO uint32_t MAR3L;
+    stc_ethernet_mac_mar3l_field_t MAR3L_f;
+  };
+  union {
+    __IO uint32_t MAR4H;
+    stc_ethernet_mac_mar4h_field_t MAR4H_f;
+  };
+  union {
+    __IO uint32_t MAR4L;
+    stc_ethernet_mac_mar4l_field_t MAR4L_f;
+  };
+  union {
+    __IO uint32_t MAR5H;
+    stc_ethernet_mac_mar5h_field_t MAR5H_f;
+  };
+  union {
+    __IO uint32_t MAR5L;
+    stc_ethernet_mac_mar5l_field_t MAR5L_f;
+  };
+  union {
+    __IO uint32_t MAR6H;
+    stc_ethernet_mac_mar6h_field_t MAR6H_f;
+  };
+  union {
+    __IO uint32_t MAR6L;
+    stc_ethernet_mac_mar6l_field_t MAR6L_f;
+  };
+  union {
+    __IO uint32_t MAR7H;
+    stc_ethernet_mac_mar7h_field_t MAR7H_f;
+  };
+  union {
+    __IO uint32_t MAR7L;
+    stc_ethernet_mac_mar7l_field_t MAR7L_f;
+  };
+  union {
+    __IO uint32_t MAR8H;
+    stc_ethernet_mac_mar8h_field_t MAR8H_f;
+  };
+  union {
+    __IO uint32_t MAR8L;
+    stc_ethernet_mac_mar8l_field_t MAR8L_f;
+  };
+  union {
+    __IO uint32_t MAR9H;
+    stc_ethernet_mac_mar9h_field_t MAR9H_f;
+  };
+  union {
+    __IO uint32_t MAR9L;
+    stc_ethernet_mac_mar9l_field_t MAR9L_f;
+  };
+  union {
+    __IO uint32_t MAR10H;
+    stc_ethernet_mac_mar10h_field_t MAR10H_f;
+  };
+  union {
+    __IO uint32_t MAR10L;
+    stc_ethernet_mac_mar10l_field_t MAR10L_f;
+  };
+  union {
+    __IO uint32_t MAR11H;
+    stc_ethernet_mac_mar11h_field_t MAR11H_f;
+  };
+  union {
+    __IO uint32_t MAR11L;
+    stc_ethernet_mac_mar11l_field_t MAR11L_f;
+  };
+  union {
+    __IO uint32_t MAR12H;
+    stc_ethernet_mac_mar12h_field_t MAR12H_f;
+  };
+  union {
+    __IO uint32_t MAR12L;
+    stc_ethernet_mac_mar12l_field_t MAR12L_f;
+  };
+  union {
+    __IO uint32_t MAR13H;
+    stc_ethernet_mac_mar13h_field_t MAR13H_f;
+  };
+  union {
+    __IO uint32_t MAR13L;
+    stc_ethernet_mac_mar13l_field_t MAR13L_f;
+  };
+  union {
+    __IO uint32_t MAR14H;
+    stc_ethernet_mac_mar14h_field_t MAR14H_f;
+  };
+  union {
+    __IO uint32_t MAR14L;
+    stc_ethernet_mac_mar14l_field_t MAR14L_f;
+  };
+  union {
+    __IO uint32_t MAR15H;
+    stc_ethernet_mac_mar15h_field_t MAR15H_f;
+  };
+  union {
+    __IO uint32_t MAR15L;
+    stc_ethernet_mac_mar15l_field_t MAR15L_f;
+  };
+        uint8_t RESERVED1[24];
+  union {
+    __IO uint32_t RGSR;
+    stc_ethernet_mac_rgsr_field_t RGSR_f;
+  };
+        uint8_t RESERVED2[36];
+  __IO uint32_t mmc_cntl;
+  __IO uint32_t mmc_intr_rx;
+  __IO uint32_t mmc_intr_tx;
+  __IO uint32_t mmc_intr_mask_rx;
+  __IO uint32_t mmc_intr_mask_tx;
+  __IO uint32_t txoctetcount_gb;
+  __IO uint32_t txframecount_gb;
+  __IO uint32_t txbroadcastframes_g;
+  __IO uint32_t txmulticastframes_g;
+  __IO uint32_t tx64octets_gb;
+  __IO uint32_t tx65to127octets_gb;
+  __IO uint32_t tx128to255octets_gb;
+  __IO uint32_t tx256to511octets_gb;
+  __IO uint32_t tx512to1023octets_gb;
+  __IO uint32_t tx1024tomaxoctets_gb;
+  __IO uint32_t txunicastframes_gb;
+  __IO uint32_t txmulticastframes_gb;
+  __IO uint32_t txbroadcastframes_gb;
+  __IO uint32_t txunderflowerror;
+  __IO uint32_t txsinglecol_g;
+  __IO uint32_t txmulticol_g;
+  __IO uint32_t txdeferred;
+  __IO uint32_t txlatecol;
+  __IO uint32_t txexesscol;
+  __IO uint32_t txcarriererror;
+  __IO uint32_t txoctetcount_g;
+  __IO uint32_t txframecount_g;
+  __IO uint32_t txexecessdef_g;
+  __IO uint32_t txpauseframes;
+  __IO uint32_t txvlanframes_g;
+        uint8_t RESERVED3[8];
+  __IO uint32_t rxframecount_gb;
+  __IO uint32_t rxoctetcount_gb;
+  __IO uint32_t rxoctetcount_g;
+  __IO uint32_t rxbroadcastframes_g;
+  __IO uint32_t rxmulticastframes_g;
+  __IO uint32_t rxcrcerror;
+  __IO uint32_t rxallignmenterror;
+  __IO uint32_t rxrunterror;
+  __IO uint32_t rxjabbererror;
+  __IO uint32_t rxundersize_g;
+  __IO uint32_t rxoversize_g;
+  __IO uint32_t rx64octets_gb;
+  __IO uint32_t rx65to127octets_gb;
+  __IO uint32_t rx128to255octets_gb;
+  __IO uint32_t rx256to511octets_gb;
+  __IO uint32_t rx512to1023octets_gb;
+  __IO uint32_t rx1024tomaxoctets_gb;
+  __IO uint32_t rxunicastframes_g;
+  __IO uint32_t rxlengtherror;
+  __IO uint32_t rxoutofrangetype;
+  __IO uint32_t rxpauseframes;
+  __IO uint32_t rxfifooverflow;
+  __IO uint32_t rxvlanframes_gb;
+  __IO uint32_t rxwatchdogerror;
+        uint8_t RESERVED4[32];
+  __IO uint32_t mmc_ipc_intr_mask_rx;
+        uint8_t RESERVED5[4];
+  __IO uint32_t mmc_ipc_intr_rx;
+        uint8_t RESERVED6[4];
+  __IO uint32_t rxipv4_gd_frms;
+  __IO uint32_t rxipv4_hdrerr_frms;
+  __IO uint32_t rxipv4_nopay_frms;
+  __IO uint32_t rxipv4_frag_frms;
+  __IO uint32_t rxipv4_udsbl_frms;
+  __IO uint32_t rxipv6_gd_frms;
+  __IO uint32_t rxipv6_hdrerr_frms;
+  __IO uint32_t rxipv6_nopay_frms;
+  __IO uint32_t rxudp_gd_frms;
+  __IO uint32_t rxudp_err_frms;
+  __IO uint32_t rxtcp_gd_frms;
+  __IO uint32_t rxtcp_err_frms;
+  __IO uint32_t rxicmp_gd_frms;
+  __IO uint32_t rxicmp_err_frms;
+        uint8_t RESERVED7[8];
+  __IO uint32_t rxipv4_gd_octets;
+  __IO uint32_t rxipv4_hdrerr_octets;
+  __IO uint32_t rxipv4_nopay_octets;
+  __IO uint32_t rxipv4_frag_octets;
+  __IO uint32_t rxipv4_udsbl_octets;
+  __IO uint32_t rxipv6_gd_octets;
+  __IO uint32_t rxipv6_hdrerr_octets;
+  __IO uint32_t rxipv6_nopay_octets;
+  __IO uint32_t rxudp_gd_octets;
+  __IO uint32_t rxudp_err_octets;
+  __IO uint32_t rxtcp_gd_octets;
+  __IO uint32_t rxtcp_err_octets;
+  __IO uint32_t rxicmp_gd_octets;
+  __IO uint32_t rxicmp_err_octets;
+        uint8_t RESERVED8[1144];
+  union {
+    __IO uint32_t TSCR;
+    stc_ethernet_mac_tscr_field_t TSCR_f;
+  };
+  union {
+    __IO uint32_t SSIR;
+    stc_ethernet_mac_ssir_field_t SSIR_f;
+  };
+  union {
+    __IO uint32_t STSR;
+    stc_ethernet_mac_stsr_field_t STSR_f;
+  };
+  union {
+    __IO uint32_t STNR;
+    stc_ethernet_mac_stnr_field_t STNR_f;
+  };
+  union {
+    __IO uint32_t STSUR;
+    stc_ethernet_mac_stsur_field_t STSUR_f;
+  };
+  union {
+    __IO uint32_t STNUR;
+    stc_ethernet_mac_stnur_field_t STNUR_f;
+  };
+  union {
+    __IO uint32_t TSAR;
+    stc_ethernet_mac_tsar_field_t TSAR_f;
+  };
+  union {
+    __IO uint32_t TTSR;
+    stc_ethernet_mac_ttsr_field_t TTSR_f;
+  };
+  union {
+    __IO uint32_t TTNR;
+    stc_ethernet_mac_ttnr_field_t TTNR_f;
+  };
+  union {
+    __IO uint32_t STHWSR;
+    stc_ethernet_mac_sthwsr_field_t STHWSR_f;
+  };
+  union {
+    __IO uint32_t TSR;
+    stc_ethernet_mac_tsr_field_t TSR_f;
+  };
+  union {
+    __IO uint32_t PPSCR;
+    stc_ethernet_mac_ppscr_field_t PPSCR_f;
+  };
+  union {
+    __IO uint32_t ATNR;
+    stc_ethernet_mac_atnr_field_t ATNR_f;
+  };
+  union {
+    __IO uint32_t ATSR;
+    stc_ethernet_mac_atsr_field_t ATSR_f;
+  };
+        uint8_t RESERVED9[200];
+  union {
+    __IO uint32_t MAR16H;
+    stc_ethernet_mac_mar16h_field_t MAR16H_f;
+  };
+  union {
+    __IO uint32_t MAR16L;
+    stc_ethernet_mac_mar16l_field_t MAR16L_f;
+  };
+  union {
+    __IO uint32_t MAR17H;
+    stc_ethernet_mac_mar17h_field_t MAR17H_f;
+  };
+  union {
+    __IO uint32_t MAR17L;
+    stc_ethernet_mac_mar17l_field_t MAR17L_f;
+  };
+  union {
+    __IO uint32_t MAR18H;
+    stc_ethernet_mac_mar18h_field_t MAR18H_f;
+  };
+  union {
+    __IO uint32_t MAR18L;
+    stc_ethernet_mac_mar18l_field_t MAR18L_f;
+  };
+  union {
+    __IO uint32_t MAR19H;
+    stc_ethernet_mac_mar19h_field_t MAR19H_f;
+  };
+  union {
+    __IO uint32_t MAR19L;
+    stc_ethernet_mac_mar19l_field_t MAR19L_f;
+  };
+  union {
+    __IO uint32_t MAR20H;
+    stc_ethernet_mac_mar20h_field_t MAR20H_f;
+  };
+  union {
+    __IO uint32_t MAR20L;
+    stc_ethernet_mac_mar20l_field_t MAR20L_f;
+  };
+  union {
+    __IO uint32_t MAR21H;
+    stc_ethernet_mac_mar21h_field_t MAR21H_f;
+  };
+  union {
+    __IO uint32_t MAR21L;
+    stc_ethernet_mac_mar21l_field_t MAR21L_f;
+  };
+  union {
+    __IO uint32_t MAR22H;
+    stc_ethernet_mac_mar22h_field_t MAR22H_f;
+  };
+  union {
+    __IO uint32_t MAR22L;
+    stc_ethernet_mac_mar22l_field_t MAR22L_f;
+  };
+  union {
+    __IO uint32_t MAR23H;
+    stc_ethernet_mac_mar23h_field_t MAR23H_f;
+  };
+  union {
+    __IO uint32_t MAR23L;
+    stc_ethernet_mac_mar23l_field_t MAR23L_f;
+  };
+  union {
+    __IO uint32_t MAR24H;
+    stc_ethernet_mac_mar24h_field_t MAR24H_f;
+  };
+  union {
+    __IO uint32_t MAR24L;
+    stc_ethernet_mac_mar24l_field_t MAR24L_f;
+  };
+  union {
+    __IO uint32_t MAR25H;
+    stc_ethernet_mac_mar25h_field_t MAR25H_f;
+  };
+  union {
+    __IO uint32_t MAR25L;
+    stc_ethernet_mac_mar25l_field_t MAR25L_f;
+  };
+  union {
+    __IO uint32_t MAR26H;
+    stc_ethernet_mac_mar26h_field_t MAR26H_f;
+  };
+  union {
+    __IO uint32_t MAR26L;
+    stc_ethernet_mac_mar26l_field_t MAR26L_f;
+  };
+  union {
+    __IO uint32_t MAR27H;
+    stc_ethernet_mac_mar27h_field_t MAR27H_f;
+  };
+  union {
+    __IO uint32_t MAR27L;
+    stc_ethernet_mac_mar27l_field_t MAR27L_f;
+  };
+  union {
+    __IO uint32_t MAR28H;
+    stc_ethernet_mac_mar28h_field_t MAR28H_f;
+  };
+  union {
+    __IO uint32_t MAR28L;
+    stc_ethernet_mac_mar28l_field_t MAR28L_f;
+  };
+  union {
+    __IO uint32_t MAR29H;
+    stc_ethernet_mac_mar29h_field_t MAR29H_f;
+  };
+  union {
+    __IO uint32_t MAR29L;
+    stc_ethernet_mac_mar29l_field_t MAR29L_f;
+  };
+  union {
+    __IO uint32_t MAR30H;
+    stc_ethernet_mac_mar30h_field_t MAR30H_f;
+  };
+  union {
+    __IO uint32_t MAR30L;
+    stc_ethernet_mac_mar30l_field_t MAR30L_f;
+  };
+  union {
+    __IO uint32_t MAR31H;
+    stc_ethernet_mac_mar31h_field_t MAR31H_f;
+  };
+  union {
+    __IO uint32_t MAR31L;
+    stc_ethernet_mac_mar31l_field_t MAR31L_f;
+  };
+        uint8_t RESERVED10[1920];
+  union {
+    __IO uint32_t BMR;
+    stc_ethernet_mac_bmr_field_t BMR_f;
+  };
+  union {
+    __IO uint32_t TPDR;
+    stc_ethernet_mac_tpdr_field_t TPDR_f;
+  };
+  union {
+    __IO uint32_t RPDR;
+    stc_ethernet_mac_rpdr_field_t RPDR_f;
+  };
+  union {
+    __IO uint32_t RDLAR;
+    stc_ethernet_mac_rdlar_field_t RDLAR_f;
+  };
+  union {
+    __IO uint32_t TDLAR;
+    stc_ethernet_mac_tdlar_field_t TDLAR_f;
+  };
+  union {
+    __IO uint32_t SR;
+    stc_ethernet_mac_sr_field_t SR_f;
+  };
+  union {
+    __IO uint32_t OMR;
+    stc_ethernet_mac_omr_field_t OMR_f;
+  };
+  union {
+    __IO uint32_t IER;
+    stc_ethernet_mac_ier_field_t IER_f;
+  };
+  union {
+    __IO uint32_t MFBOCR;
+    stc_ethernet_mac_mfbocr_field_t MFBOCR_f;
+  };
+  union {
+    __IO uint32_t RIWTR;
+    stc_ethernet_mac_riwtr_field_t RIWTR_f;
+  };
+        uint8_t RESERVED11[4];
+  union {
+    __IO uint32_t AHBSR;
+    stc_ethernet_mac_ahbsr_field_t AHBSR_f;
+  };
+        uint8_t RESERVED12[24];
+  union {
+    __IO uint32_t CHTDR;
+    stc_ethernet_mac_chtdr_field_t CHTDR_f;
+  };
+  union {
+    __IO uint32_t CHRDR;
+    stc_ethernet_mac_chrdr_field_t CHRDR_f;
+  };
+  union {
+    __IO uint32_t CHTBAR;
+    stc_ethernet_mac_chtbar_field_t CHTBAR_f;
+  };
+  union {
+    __IO uint32_t CHRBAR;
+    stc_ethernet_mac_chrbar_field_t CHRBAR_f;
+  };
+}FM3_ETHERNET_MAC_TypeDef;
+
+/* ETHERNET-CONTROL registers */
+typedef struct
+{
+  union {
+    __IO uint32_t ETH_MODE;
+    stc_ethernet_control_eth_mode_field_t ETH_MODE_f;
+  };
+        uint8_t RESERVED1[4];
+  union {
+    __IO uint32_t ETH_CLKG;
+    stc_ethernet_control_eth_clkg_field_t ETH_CLKG_f;
+  };
+}FM3_ETHERNET_CONTROL_TypeDef;
+
+/******************************************************************************
+ * Peripheral memory map
+ ******************************************************************************/
+#define FM3_FLASH_BASE        (0x00000000UL)                 /* Flash Base                             */
+#define FM3_PERIPH_BASE       (0x40000000UL)                 /* Peripheral  Base                       */
+#define FM3_CM3_BASE          (0xE0100000UL)                 /* CM3 Private                            */
+
+#define FM3_FLASH_IF_BASE     (FM3_PERIPH_BASE + 0x00000UL)  /* Flash interface registers              */
+#define FM3_CRG_BASE          (FM3_PERIPH_BASE + 0x10000UL)  /* Clock and reset registers              */
+#define FM3_HWWDT_BASE        (FM3_PERIPH_BASE + 0x11000UL)  /* Hardware watchdog registers            */
+#define FM3_SWWDT_BASE        (FM3_PERIPH_BASE + 0x12000UL)  /* Software watchdog registers            */
+#define FM3_DTIM_BASE         (FM3_PERIPH_BASE + 0x15000UL)  /* Dual timer 1/2 registers               */
+#define FM3_MFT0_FRT_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Free Running Timer registers */
+#define FM3_MFT0_OCU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Output Compare Unit registers */
+#define FM3_MFT0_WFG_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT0_ICU_BASE     (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 Input Capture Unit registers */
+#define FM3_MFT0_ADCMP_BASE   (FM3_PERIPH_BASE + 0x20000UL)  /* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define FM3_MFT1_FRT_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Free Running Timer registers */
+#define FM3_MFT1_OCU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Output Compare Unit registers */
+#define FM3_MFT1_WFG_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT1_ICU_BASE     (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 Input Capture Unit registers */
+#define FM3_MFT1_ADCMP_BASE   (FM3_PERIPH_BASE + 0x21000UL)  /* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define FM3_MFT2_FRT_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Free Running Timer registers */
+#define FM3_MFT2_OCU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Output Compare Unit registers */
+#define FM3_MFT2_WFG_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define FM3_MFT2_ICU_BASE     (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 Input Capture Unit registers */
+#define FM3_MFT2_ADCMP_BASE   (FM3_PERIPH_BASE + 0x22000UL)  /* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define FM3_MFT_PPG_BASE      (FM3_PERIPH_BASE + 0x24000UL)  /* Multifunction Timer PPG registers      */
+#define FM3_BT0_PPG_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PPG registers             */
+#define FM3_BT0_PWM_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWM registers             */
+#define FM3_BT0_RT_BASE       (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 RT registers              */
+#define FM3_BT0_PWC_BASE      (FM3_PERIPH_BASE + 0x25000UL)  /* Base Timer 0 PWC registers             */
+#define FM3_BT1_PPG_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PPG registers             */
+#define FM3_BT1_PWM_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWM registers             */
+#define FM3_BT1_RT_BASE       (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 RT registers              */
+#define FM3_BT1_PWC_BASE      (FM3_PERIPH_BASE + 0x25040UL)  /* Base Timer 1 PWC registers             */
+#define FM3_BT2_PPG_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PPG registers             */
+#define FM3_BT2_PWM_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWM registers             */
+#define FM3_BT2_RT_BASE       (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 RT registers              */
+#define FM3_BT2_PWC_BASE      (FM3_PERIPH_BASE + 0x25080UL)  /* Base Timer 2 PWC registers             */
+#define FM3_BT3_PPG_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PPG registers             */
+#define FM3_BT3_PWM_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWM registers             */
+#define FM3_BT3_RT_BASE       (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 RT registers              */
+#define FM3_BT3_PWC_BASE      (FM3_PERIPH_BASE + 0x250C0UL)  /* Base Timer 3 PWC registers             */
+#define FM3_BT4_PPG_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PPG registers             */
+#define FM3_BT4_PWM_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWM registers             */
+#define FM3_BT4_RT_BASE       (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 RT registers              */
+#define FM3_BT4_PWC_BASE      (FM3_PERIPH_BASE + 0x25200UL)  /* Base Timer 4 PWC registers             */
+#define FM3_BT5_PPG_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PPG registers             */
+#define FM3_BT5_PWM_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWM registers             */
+#define FM3_BT5_RT_BASE       (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 RT registers              */
+#define FM3_BT5_PWC_BASE      (FM3_PERIPH_BASE + 0x25240UL)  /* Base Timer 5 PWC registers             */
+#define FM3_BT6_PPG_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PPG registers             */
+#define FM3_BT6_PWM_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWM registers             */
+#define FM3_BT6_RT_BASE       (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 RT registers              */
+#define FM3_BT6_PWC_BASE      (FM3_PERIPH_BASE + 0x25280UL)  /* Base Timer 6 PWC registers             */
+#define FM3_BT7_PPG_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PPG registers             */
+#define FM3_BT7_PWM_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWM registers             */
+#define FM3_BT7_RT_BASE       (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 RT registers              */
+#define FM3_BT7_PWC_BASE      (FM3_PERIPH_BASE + 0x252C0UL)  /* Base Timer 7 PWC registers             */
+#define FM3_BTIOSEL03_BASE    (FM3_PERIPH_BASE + 0x25100UL)  /* Base Timer I/O selector channel 0 - channel 3 registers */
+#define FM3_BTIOSEL47_BASE    (FM3_PERIPH_BASE + 0x25300UL)  /* Base Timer I/O selector channel 4 - channel 7 registers */
+#define FM3_BT8_PPG_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT8_PWM_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT8_RT_BASE       (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT8_PWC_BASE      (FM3_PERIPH_BASE + 0x25400UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT9_PPG_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT9_PWM_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT9_RT_BASE       (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT9_PWC_BASE      (FM3_PERIPH_BASE + 0x25440UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT10_PPG_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT10_PWM_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT10_RT_BASE      (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT10_PWC_BASE     (FM3_PERIPH_BASE + 0x25480UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT11_PPG_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT11_PWM_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT11_RT_BASE      (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT11_PWC_BASE     (FM3_PERIPH_BASE + 0x254C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BT12_PPG_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PPG registers             */
+#define FM3_BT12_PWM_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWM registers             */
+#define FM3_BT12_RT_BASE      (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 RT registers              */
+#define FM3_BT12_PWC_BASE     (FM3_PERIPH_BASE + 0x25600UL)  /* Base Timer 8 PWC registers             */
+#define FM3_BT13_PPG_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PPG registers             */
+#define FM3_BT13_PWM_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWM registers             */
+#define FM3_BT13_RT_BASE      (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 RT registers              */
+#define FM3_BT13_PWC_BASE     (FM3_PERIPH_BASE + 0x25640UL)  /* Base Timer 9 PWC registers             */
+#define FM3_BT14_PPG_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PPG registers            */
+#define FM3_BT14_PWM_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWM registers            */
+#define FM3_BT14_RT_BASE      (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 RT registers             */
+#define FM3_BT14_PWC_BASE     (FM3_PERIPH_BASE + 0x25680UL)  /* Base Timer 10 PWC registers            */
+#define FM3_BT15_PPG_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PPG registers            */
+#define FM3_BT15_PWM_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWM registers            */
+#define FM3_BT15_RT_BASE      (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 RT registers             */
+#define FM3_BT15_PWC_BASE     (FM3_PERIPH_BASE + 0x256C0UL)  /* Base Timer 11 PWC registers            */
+#define FM3_BTIOSEL8B_BASE    (FM3_PERIPH_BASE + 0x25500UL)  /* Base Timer I/O selector channel 8 - channel 11 registers */
+#define FM3_BTIOSELCF_BASE    (FM3_PERIPH_BASE + 0x25700UL)  /* Base Timer I/O selector channel 12 - channel 15 registers */
+#define FM3_SBSSR_BASE        (FM3_PERIPH_BASE + 0x25FFCUL)  /* Software based Simulation Startup (Base Timer) register */
+#define FM3_QPRC0_BASE        (FM3_PERIPH_BASE + 0x26000UL)  /* Quad position and revolution counter channel 0 registers */
+#define FM3_QPRC1_BASE        (FM3_PERIPH_BASE + 0x26040UL)  /* Quad position and revolution counter channel 1 registers */
+#define FM3_QPRC2_BASE        (FM3_PERIPH_BASE + 0x26080UL)  /* Quad position and revolution counter channel 2 registers */
+#define FM3_ADC0_BASE         (FM3_PERIPH_BASE + 0x27000UL)  /* 12-bit ADC unit 0 registers            */
+#define FM3_ADC1_BASE         (FM3_PERIPH_BASE + 0x27100UL)  /* 12-bit ADC unit 1 registers            */
+#define FM3_ADC2_BASE         (FM3_PERIPH_BASE + 0x27200UL)  /* 12-bit ADC unit 2 registers            */
+#define FM3_CRTRIM_BASE       (FM3_PERIPH_BASE + 0x2E000UL)  /* CR trimming registers                  */
+#define FM3_EXTI_BASE         (FM3_PERIPH_BASE + 0x30000UL)  /* External interrupt registers           */
+#define FM3_INTREQ_BASE       (FM3_PERIPH_BASE + 0x31000UL)  /* Interrupt request read registers       */
+#define FM3_GPIO_BASE         (FM3_PERIPH_BASE + 0x33000UL)  /* General purpose I/O registers          */
+#define FM3_LVD_BASE          (FM3_PERIPH_BASE + 0x35000UL)  /* Low voltage detection registers        */
+#define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL)  /* USB clock registers                    */
+#define FM3_MFS0_UART_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART asynchronous channel 0 registers  */
+#define FM3_MFS0_CSIO_BASE    (FM3_PERIPH_BASE + 0x38000UL)  /* UART synchronous channel 0 registers   */
+#define FM3_MFS0_LIN_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* UART LIN channel 0 registers           */
+#define FM3_MFS0_I2C_BASE     (FM3_PERIPH_BASE + 0x38000UL)  /* I2C channel 0 registers                */
+#define FM3_MFS1_UART_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART asynchronous channel 1 registers  */
+#define FM3_MFS1_CSIO_BASE    (FM3_PERIPH_BASE + 0x38100UL)  /* UART synchronous channel 1 registers   */
+#define FM3_MFS1_LIN_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* UART LIN channel 1 registers           */
+#define FM3_MFS1_I2C_BASE     (FM3_PERIPH_BASE + 0x38100UL)  /* I2C channel 1 registers                */
+#define FM3_MFS2_UART_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART asynchronous channel 2 registers  */
+#define FM3_MFS2_CSIO_BASE    (FM3_PERIPH_BASE + 0x38200UL)  /* UART synchronous channel 2 registers   */
+#define FM3_MFS2_LIN_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* UART LIN channel 2 registers           */
+#define FM3_MFS2_I2C_BASE     (FM3_PERIPH_BASE + 0x38200UL)  /* I2C channel 2 registers                */
+#define FM3_MFS3_UART_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART asynchronous channel 3 registers  */
+#define FM3_MFS3_CSIO_BASE    (FM3_PERIPH_BASE + 0x38300UL)  /* UART synchronous channel 3 registers   */
+#define FM3_MFS3_LIN_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* UART LIN channel 3 registers           */
+#define FM3_MFS3_I2C_BASE     (FM3_PERIPH_BASE + 0x38300UL)  /* I2C channel 3 registers                */
+#define FM3_MFS4_UART_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART asynchronous channel 4 registers  */
+#define FM3_MFS4_CSIO_BASE    (FM3_PERIPH_BASE + 0x38400UL)  /* UART synchronous channel 4 registers   */
+#define FM3_MFS4_LIN_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* UART LIN channel 4 registers           */
+#define FM3_MFS4_I2C_BASE     (FM3_PERIPH_BASE + 0x38400UL)  /* I2C channel 4 registers                */
+#define FM3_MFS5_UART_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART asynchronous channel 5 registers  */
+#define FM3_MFS5_CSIO_BASE    (FM3_PERIPH_BASE + 0x38500UL)  /* UART synchronous channel 5 registers   */
+#define FM3_MFS5_LIN_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* UART LIN channel 5 registers           */
+#define FM3_MFS5_I2C_BASE     (FM3_PERIPH_BASE + 0x38500UL)  /* I2C channel 5 registers                */
+#define FM3_MFS6_UART_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART asynchronous channel 6 registers  */
+#define FM3_MFS6_CSIO_BASE    (FM3_PERIPH_BASE + 0x38600UL)  /* UART synchronous channel 6 registers   */
+#define FM3_MFS6_LIN_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* UART LIN channel 6 registers           */
+#define FM3_MFS6_I2C_BASE     (FM3_PERIPH_BASE + 0x38600UL)  /* I2C channel 6 registers                */
+#define FM3_MFS7_UART_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART asynchronous channel 7 registers  */
+#define FM3_MFS7_CSIO_BASE    (FM3_PERIPH_BASE + 0x38700UL)  /* UART synchronous channel 7 registers   */
+#define FM3_MFS7_LIN_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* UART LIN channel 7 registers           */
+#define FM3_MFS7_I2C_BASE     (FM3_PERIPH_BASE + 0x38700UL)  /* I2C channel 7 registers                */
+#define FM3_MFS_NFC_BASE      (FM3_PERIPH_BASE + 0x38800UL)  /* MFS Noise Filter Control register      */
+#define FM3_CRC_BASE          (FM3_PERIPH_BASE + 0x39000UL)  /* CRC registers                          */
+#define FM3_WC_BASE           (FM3_PERIPH_BASE + 0x3A000UL)  /* Watch counter registers                */
+#define FM3_EXBUS_BASE        (FM3_PERIPH_BASE + 0x3F000UL)  /* External bus interface registers       */
+#define FM3_USB0_BASE         (FM3_PERIPH_BASE + 0x42100UL)  /* USB channel 0 registers                */
+#define FM3_USB1_BASE         (FM3_PERIPH_BASE + 0x52100UL)  /* USB channel 1 registers                */
+#define FM3_DMAC_BASE         (FM3_PERIPH_BASE + 0x60000UL)  /* DMA controller                         */
+#define FM3_ETHERNET_MAC0_BASE    (FM3_PERIPH_BASE + 0x64000UL) /* Ethernet MAC 0 registers            */
+#define FM3_ETHERNET_CONTROL_BASE (FM3_PERIPH_BASE + 0x66000UL) /* Ethernet MAC control registers      */
+#define FM3_ETHERNET_MAC1_BASE    (FM3_PERIPH_BASE + 0x67000UL) /* Ethernet MAC 1 registers            */
+
+/******************************************************************************
+ * Peripheral declaration
+ ******************************************************************************/
+#define FM3_FLASH_IF    ((FM3_FLASH_IF_TypeDef *)FM3_FLASH_IF_BASE)
+#define FM3_CRG         ((FM3_CRG_TypeDef *)FM3_CRG_BASE)
+#define FM3_HWWDT       ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE)
+#define FM3_SWWDT       ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE)
+#define FM3_DTIM        ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE)
+#define FM3_MFT0_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE)
+#define FM3_MFT0_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE)
+#define FM3_MFT0_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE)
+#define FM3_MFT0_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE)
+#define FM3_MFT0_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE)
+#define FM3_MFT1_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE)
+#define FM3_MFT1_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE)
+#define FM3_MFT1_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE)
+#define FM3_MFT1_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE)
+#define FM3_MFT1_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE)
+#define FM3_MFT2_FRT    ((FM3_MFT_FRT_TypeDef *)FM3_MFT2_FRT_BASE)
+#define FM3_MFT2_OCU    ((FM3_MFT_OCU_TypeDef *)FM3_MFT2_OCU_BASE)
+#define FM3_MFT2_WFG    ((FM3_MFT_WFG_TypeDef *)FM3_MFT2_WFG_BASE)
+#define FM3_MFT2_ICU    ((FM3_MFT_ICU_TypeDef *)FM3_MFT2_ICU_BASE)
+#define FM3_MFT2_ADCMP  ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT2_ADCMP_BASE)
+#define FM3_MFT_PPG     ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE)
+#define FM3_BT0_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE)
+#define FM3_BT0_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE)
+#define FM3_BT0_RT      ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE)
+#define FM3_BT0_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE)
+#define FM3_BT1_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE)
+#define FM3_BT1_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE)
+#define FM3_BT1_RT      ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE)
+#define FM3_BT1_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE)
+#define FM3_BT2_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE)
+#define FM3_BT2_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE)
+#define FM3_BT2_RT      ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE)
+#define FM3_BT2_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE)
+#define FM3_BT3_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE)
+#define FM3_BT3_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE)
+#define FM3_BT3_RT      ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE)
+#define FM3_BT3_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE)
+#define FM3_BT4_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE)
+#define FM3_BT4_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE)
+#define FM3_BT4_RT      ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE)
+#define FM3_BT4_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE)
+#define FM3_BT5_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE)
+#define FM3_BT5_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE)
+#define FM3_BT5_RT      ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE)
+#define FM3_BT5_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE)
+#define FM3_BT6_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE)
+#define FM3_BT6_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE)
+#define FM3_BT6_RT      ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE)
+#define FM3_BT6_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE)
+#define FM3_BT7_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE)
+#define FM3_BT7_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE)
+#define FM3_BT7_RT      ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE)
+#define FM3_BT7_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE)
+#define FM3_BTIOSEL03   ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE)
+#define FM3_BTIOSEL47   ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE)
+#define FM3_BT8_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT8_PPG_BASE)
+#define FM3_BT8_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT8_PWM_BASE)
+#define FM3_BT8_RT      ((FM3_BT_RT_TypeDef *)FM3_BT8_RT_BASE)
+#define FM3_BT8_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT8_PWC_BASE)
+#define FM3_BT9_PPG     ((FM3_BT_PPG_TypeDef *)FM3_BT9_PPG_BASE)
+#define FM3_BT9_PWM     ((FM3_BT_PWM_TypeDef *)FM3_BT9_PWM_BASE)
+#define FM3_BT9_RT      ((FM3_BT_RT_TypeDef *)FM3_BT9_RT_BASE)
+#define FM3_BT9_PWC     ((FM3_BT_PWC_TypeDef *)FM3_BT9_PWC_BASE)
+#define FM3_BT10_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT10_PPG_BASE)
+#define FM3_BT10_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT10_PWM_BASE)
+#define FM3_BT10_RT     ((FM3_BT_RT_TypeDef *)FM3_BT10_RT_BASE)
+#define FM3_BT10_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT10_PWC_BASE)
+#define FM3_BT11_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT11_PPG_BASE)
+#define FM3_BT11_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT11_PWM_BASE)
+#define FM3_BT11_RT     ((FM3_BT_RT_TypeDef *)FM3_BT11_RT_BASE)
+#define FM3_BT11_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT11_PWC_BASE)
+#define FM3_BT12_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT12_PPG_BASE)
+#define FM3_BT12_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT12_PWM_BASE)
+#define FM3_BT12_RT     ((FM3_BT_RT_TypeDef *)FM3_BT12_RT_BASE)
+#define FM3_BT12_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT12_PWC_BASE)
+#define FM3_BT13_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT13_PPG_BASE)
+#define FM3_BT13_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT13_PWM_BASE)
+#define FM3_BT13_RT     ((FM3_BT_RT_TypeDef *)FM3_BT13_RT_BASE)
+#define FM3_BT13_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT13_PWC_BASE)
+#define FM3_BT14_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT14_PPG_BASE)
+#define FM3_BT14_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT14_PWM_BASE)
+#define FM3_BT14_RT     ((FM3_BT_RT_TypeDef *)FM3_BT14_RT_BASE)
+#define FM3_BT14_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT14_PWC_BASE)
+#define FM3_BT15_PPG    ((FM3_BT_PPG_TypeDef *)FM3_BT15_PPG_BASE)
+#define FM3_BT15_PWM    ((FM3_BT_PWM_TypeDef *)FM3_BT15_PWM_BASE)
+#define FM3_BT15_RT     ((FM3_BT_RT_TypeDef *)FM3_BT15_RT_BASE)
+#define FM3_BT15_PWC    ((FM3_BT_PWC_TypeDef *)FM3_BT15_PWC_BASE)
+#define FM3_BTIOSEL8B   ((FM3_BTIOSEL8B_TypeDef *)FM3_BTIOSEL8B_BASE)
+#define FM3_BTIOSELCF   ((FM3_BTIOSELCF_TypeDef *)FM3_BTIOSELCF_BASE)
+#define FM3_SBSSR       ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE)
+#define FM3_QPRC0       ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE)
+#define FM3_QPRC1       ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE)
+#define FM3_QPRC2       ((FM3_QPRC_TypeDef *)FM3_QPRC2_BASE)
+#define FM3_ADC0        ((FM3_ADC_TypeDef *)FM3_ADC0_BASE)
+#define FM3_ADC1        ((FM3_ADC_TypeDef *)FM3_ADC1_BASE)
+#define FM3_ADC2        ((FM3_ADC_TypeDef *)FM3_ADC2_BASE)
+#define FM3_CRTRIM      ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE)
+#define FM3_EXTI        ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE)
+#define FM3_INTREQ      ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE)
+#define FM3_GPIO        ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE)
+#define FM3_LVD         ((FM3_LVD_TypeDef *)FM3_LVD_BASE)
+#define FM3_USBETHERNETCLK ((FM3_USBETHERNETCLK_TypeDef *)FM3_USBETHERNETCLK_BASE)
+#define FM3_MFS0_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE)
+#define FM3_MFS0_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE)
+#define FM3_MFS0_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE)
+#define FM3_MFS0_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE)
+#define FM3_MFS1_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE)
+#define FM3_MFS1_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE)
+#define FM3_MFS1_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE)
+#define FM3_MFS1_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE)
+#define FM3_MFS2_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE)
+#define FM3_MFS2_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE)
+#define FM3_MFS2_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE)
+#define FM3_MFS2_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE)
+#define FM3_MFS3_UART   ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE)
+#define FM3_MFS3_CSIO   ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE)
+#define FM3_MFS3_LIN    ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE)
+#define FM3_MFS3_I2C    ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE)
+#define FM3_MFS4_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE)
+#define FM3_MFS4_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE)
+#define FM3_MFS4_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE)
+#define FM3_MFS4_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE)
+#define FM3_MFS5_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE)
+#define FM3_MFS5_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE)
+#define FM3_MFS5_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE)
+#define FM3_MFS5_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE)
+#define FM3_MFS6_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE)
+#define FM3_MFS6_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE)
+#define FM3_MFS6_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE)
+#define FM3_MFS6_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE)
+#define FM3_MFS7_UART   ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE)
+#define FM3_MFS7_CSIO   ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE)
+#define FM3_MFS7_LIN    ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE)
+#define FM3_MFS7_I2C    ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE)
+#define FM3_MFS_NFC     ((FM3_MFS_NFC_TypeDef *)FM3_MFS_NFC_BASE)
+#define FM3_CRC         ((FM3_CRC_TypeDef *)FM3_CRC_BASE)
+#define FM3_WC          ((FM3_WC_TypeDef *)FM3_WC_BASE)
+#define FM3_EXBUS       ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE)
+#define FM3_USB0        ((FM3_USB_TypeDef *)FM3_USB0_BASE)
+#define FM3_USB1        ((FM3_USB_TypeDef *)FM3_USB1_BASE)
+#define FM3_DMAC        ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE)
+#define FM3_ETHERNET_MAC0    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC0_BASE)
+#define FM3_ETHERNET_CONTROL ((FM3_ETHERNET_SET_TypeDef *)FM3_ETHERNET_SET_BASE)
+#define FM3_ETHERNET_MAC1    ((FM3_ETHERNET_MAC_TypeDef *)FM3_ETHERNET_MAC1_BASE)
+
+/******************************************************************************
+ * Peripheral Bit Band Alias declaration
+ ******************************************************************************/
+
+/* Flash interface registers */
+#define bFM3_FLASH_IF_FASZR_ASZ0               *((volatile unsigned int*)(0x42000000UL))
+#define bFM3_FLASH_IF_FASZR_ASZ1               *((volatile unsigned int*)(0x42000004UL))
+#define bFM3_FLASH_IF_FRWTR_RWT0               *((volatile unsigned int*)(0x42000080UL))
+#define bFM3_FLASH_IF_FRWTR_RWT1               *((volatile unsigned int*)(0x42000084UL))
+#define bFM3_FLASH_IF_FSTR_RDY                 *((volatile unsigned int*)(0x42000100UL))
+#define bFM3_FLASH_IF_FSTR_HNG                 *((volatile unsigned int*)(0x42000104UL))
+#define bFM3_FLASH_IF_FSTR_EER                 *((volatile unsigned int*)(0x42000108UL))
+#define bFM3_FLASH_IF_FSYNDN_SD0               *((volatile unsigned int*)(0x42000200UL))
+#define bFM3_FLASH_IF_FSYNDN_SD1               *((volatile unsigned int*)(0x42000204UL))
+#define bFM3_FLASH_IF_FSYNDN_SD2               *((volatile unsigned int*)(0x42000208UL))
+#define bFM3_FLASH_IF_FBFCR_BE                 *((volatile unsigned int*)(0x42000280UL))
+#define bFM3_FLASH_IF_FBFCR_BS                 *((volatile unsigned int*)(0x42000284UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM0             *((volatile unsigned int*)(0x42002000UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM1             *((volatile unsigned int*)(0x42002004UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM2             *((volatile unsigned int*)(0x42002008UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM3             *((volatile unsigned int*)(0x4200200CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM4             *((volatile unsigned int*)(0x42002010UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM5             *((volatile unsigned int*)(0x42002014UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM6             *((volatile unsigned int*)(0x42002018UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM7             *((volatile unsigned int*)(0x4200201CUL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM8             *((volatile unsigned int*)(0x42002020UL))
+#define bFM3_FLASH_IF_CRTRMM_TRMM9             *((volatile unsigned int*)(0x42002024UL))
+
+/* Clock and reset registers */
+#define bFM3_CRG_SCM_CTL_MOSCE                 *((volatile unsigned int*)(0x42200004UL))
+#define bFM3_CRG_SCM_CTL_SOSCE                 *((volatile unsigned int*)(0x4220000CUL))
+#define bFM3_CRG_SCM_CTL_PLLE                  *((volatile unsigned int*)(0x42200010UL))
+#define bFM3_CRG_SCM_CTL_RCS0                  *((volatile unsigned int*)(0x42200014UL))
+#define bFM3_CRG_SCM_CTL_RCS1                  *((volatile unsigned int*)(0x42200018UL))
+#define bFM3_CRG_SCM_CTL_RCS2                  *((volatile unsigned int*)(0x4220001CUL))
+#define bFM3_CRG_SCM_STR_MORDY                 *((volatile unsigned int*)(0x42200084UL))
+#define bFM3_CRG_SCM_STR_SORDY                 *((volatile unsigned int*)(0x4220008CUL))
+#define bFM3_CRG_SCM_STR_PLRDY                 *((volatile unsigned int*)(0x42200090UL))
+#define bFM3_CRG_SCM_STR_RCM0                  *((volatile unsigned int*)(0x42200094UL))
+#define bFM3_CRG_SCM_STR_RCM1                  *((volatile unsigned int*)(0x42200098UL))
+#define bFM3_CRG_SCM_STR_RCM2                  *((volatile unsigned int*)(0x4220009CUL))
+#define bFM3_CRG_RST_STR_PONR                  *((volatile unsigned int*)(0x42200180UL))
+#define bFM3_CRG_RST_STR_INITX                 *((volatile unsigned int*)(0x42200184UL))
+#define bFM3_CRG_RST_STR_SWDT                  *((volatile unsigned int*)(0x42200190UL))
+#define bFM3_CRG_RST_STR_HWDT                  *((volatile unsigned int*)(0x42200194UL))
+#define bFM3_CRG_RST_STR_CSVR                  *((volatile unsigned int*)(0x42200198UL))
+#define bFM3_CRG_RST_STR_FCSR                  *((volatile unsigned int*)(0x4220019CUL))
+#define bFM3_CRG_RST_STR_SRST                  *((volatile unsigned int*)(0x422001A0UL))
+#define bFM3_CRG_BSC_PSR_BSR0                  *((volatile unsigned int*)(0x42200200UL))
+#define bFM3_CRG_BSC_PSR_BSR1                  *((volatile unsigned int*)(0x42200204UL))
+#define bFM3_CRG_BSC_PSR_BSR2                  *((volatile unsigned int*)(0x42200208UL))
+#define bFM3_CRG_APBC0_PSR_APBC00              *((volatile unsigned int*)(0x42200280UL))
+#define bFM3_CRG_APBC0_PSR_APBC01              *((volatile unsigned int*)(0x42200284UL))
+#define bFM3_CRG_APBC1_PSR_APBC10              *((volatile unsigned int*)(0x42200300UL))
+#define bFM3_CRG_APBC1_PSR_APBC11              *((volatile unsigned int*)(0x42200304UL))
+#define bFM3_CRG_APBC1_PSR_APBC1RST            *((volatile unsigned int*)(0x42200310UL))
+#define bFM3_CRG_APBC1_PSR_APBC1EN             *((volatile unsigned int*)(0x4220031CUL))
+#define bFM3_CRG_APBC2_PSR_APBC20              *((volatile unsigned int*)(0x42200380UL))
+#define bFM3_CRG_APBC2_PSR_APBC21              *((volatile unsigned int*)(0x42200384UL))
+#define bFM3_CRG_APBC2_PSR_APBC2RST            *((volatile unsigned int*)(0x42200390UL))
+#define bFM3_CRG_APBC2_PSR_APBC2EN             *((volatile unsigned int*)(0x4220039CUL))
+#define bFM3_CRG_SWC_PSR_SWDS0                 *((volatile unsigned int*)(0x42200400UL))
+#define bFM3_CRG_SWC_PSR_SWDS1                 *((volatile unsigned int*)(0x42200404UL))
+#define bFM3_CRG_SWC_PSR_TESTB                 *((volatile unsigned int*)(0x4220041CUL))
+#define bFM3_CRG_TTC_PSR_TTC0                  *((volatile unsigned int*)(0x42200500UL))
+#define bFM3_CRG_TTC_PSR_TTC1                  *((volatile unsigned int*)(0x42200504UL))
+#define bFM3_CRG_CSW_TMR_MOWT0                 *((volatile unsigned int*)(0x42200600UL))
+#define bFM3_CRG_CSW_TMR_MOWT1                 *((volatile unsigned int*)(0x42200604UL))
+#define bFM3_CRG_CSW_TMR_MOWT2                 *((volatile unsigned int*)(0x42200608UL))
+#define bFM3_CRG_CSW_TMR_MOWT3                 *((volatile unsigned int*)(0x4220060CUL))
+#define bFM3_CRG_CSW_TMR_SOWT0                 *((volatile unsigned int*)(0x42200610UL))
+#define bFM3_CRG_CSW_TMR_SOWT1                 *((volatile unsigned int*)(0x42200614UL))
+#define bFM3_CRG_CSW_TMR_SOWT2                 *((volatile unsigned int*)(0x42200618UL))
+#define bFM3_CRG_PSW_TMR_POWT0                 *((volatile unsigned int*)(0x42200680UL))
+#define bFM3_CRG_PSW_TMR_POWT1                 *((volatile unsigned int*)(0x42200684UL))
+#define bFM3_CRG_PSW_TMR_POWT2                 *((volatile unsigned int*)(0x42200688UL))
+#define bFM3_CRG_PSW_TMR_PINC                  *((volatile unsigned int*)(0x42200690UL))
+#define bFM3_CRG_PLL_CTL1_PLLM0                *((volatile unsigned int*)(0x42200700UL))
+#define bFM3_CRG_PLL_CTL1_PLLM1                *((volatile unsigned int*)(0x42200704UL))
+#define bFM3_CRG_PLL_CTL1_PLLM2                *((volatile unsigned int*)(0x42200708UL))
+#define bFM3_CRG_PLL_CTL1_PLLM3                *((volatile unsigned int*)(0x4220070CUL))
+#define bFM3_CRG_PLL_CTL1_PLLK0                *((volatile unsigned int*)(0x42200710UL))
+#define bFM3_CRG_PLL_CTL1_PLLK1                *((volatile unsigned int*)(0x42200714UL))
+#define bFM3_CRG_PLL_CTL1_PLLK2                *((volatile unsigned int*)(0x42200718UL))
+#define bFM3_CRG_PLL_CTL1_PLLK3                *((volatile unsigned int*)(0x4220071CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN0                *((volatile unsigned int*)(0x42200780UL))
+#define bFM3_CRG_PLL_CTL2_PLLN1                *((volatile unsigned int*)(0x42200784UL))
+#define bFM3_CRG_PLL_CTL2_PLLN2                *((volatile unsigned int*)(0x42200788UL))
+#define bFM3_CRG_PLL_CTL2_PLLN3                *((volatile unsigned int*)(0x4220078CUL))
+#define bFM3_CRG_PLL_CTL2_PLLN4                *((volatile unsigned int*)(0x42200790UL))
+#define bFM3_CRG_PLL_CTL2_PLLN5                *((volatile unsigned int*)(0x42200794UL))
+#define bFM3_CRG_CSV_CTL_MCSVE                 *((volatile unsigned int*)(0x42200800UL))
+#define bFM3_CRG_CSV_CTL_SCSVE                 *((volatile unsigned int*)(0x42200804UL))
+#define bFM3_CRG_CSV_CTL_FCSDE                 *((volatile unsigned int*)(0x42200820UL))
+#define bFM3_CRG_CSV_CTL_FCSRE                 *((volatile unsigned int*)(0x42200824UL))
+#define bFM3_CRG_CSV_CTL_FCD0                  *((volatile unsigned int*)(0x42200830UL))
+#define bFM3_CRG_CSV_CTL_FCD1                  *((volatile unsigned int*)(0x42200834UL))
+#define bFM3_CRG_CSV_CTL_FCD2                  *((volatile unsigned int*)(0x42200838UL))
+#define bFM3_CRG_CSV_STR_MCMF                  *((volatile unsigned int*)(0x42200880UL))
+#define bFM3_CRG_CSV_STR_SCMF                  *((volatile unsigned int*)(0x42200884UL))
+#define bFM3_CRG_DBWDT_CTL_DPSWBE              *((volatile unsigned int*)(0x42200A94UL))
+#define bFM3_CRG_DBWDT_CTL_DPHWBE              *((volatile unsigned int*)(0x42200A9CUL))
+#define bFM3_CRG_INT_ENR_MCSE                  *((volatile unsigned int*)(0x42200C00UL))
+#define bFM3_CRG_INT_ENR_SCSE                  *((volatile unsigned int*)(0x42200C04UL))
+#define bFM3_CRG_INT_ENR_PCSE                  *((volatile unsigned int*)(0x42200C08UL))
+#define bFM3_CRG_INT_ENR_FCSE                  *((volatile unsigned int*)(0x42200C14UL))
+#define bFM3_CRG_INT_STR_MCSI                  *((volatile unsigned int*)(0x42200C80UL))
+#define bFM3_CRG_INT_STR_SCSI                  *((volatile unsigned int*)(0x42200C84UL))
+#define bFM3_CRG_INT_STR_PCSI                  *((volatile unsigned int*)(0x42200C88UL))
+#define bFM3_CRG_INT_STR_FCSI                  *((volatile unsigned int*)(0x42200C94UL))
+#define bFM3_CRG_INT_CLR_MCSC                  *((volatile unsigned int*)(0x42200D00UL))
+#define bFM3_CRG_INT_CLR_SCSC                  *((volatile unsigned int*)(0x42200D04UL))
+#define bFM3_CRG_INT_CLR_PCSC                  *((volatile unsigned int*)(0x42200D08UL))
+#define bFM3_CRG_INT_CLR_FCSC                  *((volatile unsigned int*)(0x42200D14UL))
+
+/* Hardware watchdog registers */
+#define bFM3_HWWDT_WDG_CTL_INTEN               *((volatile unsigned int*)(0x42220100UL))
+#define bFM3_HWWDT_WDG_CTL_RESEN               *((volatile unsigned int*)(0x42220104UL))
+#define bFM3_HWWDT_WDG_RIS_RIS                 *((volatile unsigned int*)(0x42220200UL))
+
+/* Software watchdog registers */
+#define bFM3_SWWDT_WDOGCONTROL_INTEN           *((volatile unsigned int*)(0x42240100UL))
+#define bFM3_SWWDT_WDOGCONTROL_RESEN           *((volatile unsigned int*)(0x42240104UL))
+#define bFM3_SWWDT_WDOGRIS_RIS                 *((volatile unsigned int*)(0x42240200UL))
+
+/* Dual timer 1/2 registers */
+#define bFM3_DTIM_TIMER1CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0100UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0104UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0108UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A010CUL))
+#define bFM3_DTIM_TIMER1CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0114UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0118UL))
+#define bFM3_DTIM_TIMER1CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A011CUL))
+#define bFM3_DTIM_TIMER1RIS_TIMER1RIS          *((volatile unsigned int*)(0x422A0200UL))
+#define bFM3_DTIM_TIMER1MIS_TIMER1MIS          *((volatile unsigned int*)(0x422A0280UL))
+#define bFM3_DTIM_TIMER2CONTROL_ONESHOT        *((volatile unsigned int*)(0x422A0500UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE      *((volatile unsigned int*)(0x422A0504UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0      *((volatile unsigned int*)(0x422A0508UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1      *((volatile unsigned int*)(0x422A050CUL))
+#define bFM3_DTIM_TIMER2CONTROL_INTENABLE      *((volatile unsigned int*)(0x422A0514UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE      *((volatile unsigned int*)(0x422A0518UL))
+#define bFM3_DTIM_TIMER2CONTROL_TIMEREN        *((volatile unsigned int*)(0x422A051CUL))
+#define bFM3_DTIM_TIMER2RIS_TIMER2RIS          *((volatile unsigned int*)(0x422A0600UL))
+#define bFM3_DTIM_TIMER2MIS_TIMER2MIS          *((volatile unsigned int*)(0x422A0680UL))
+
+/* Multifunction Timer unit 0 Free Running Timer registers */
+#define bFM3_MFT0_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42400600UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42400604UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42400608UL))
+#define bFM3_MFT0_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4240060CUL))
+#define bFM3_MFT0_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42400610UL))
+#define bFM3_MFT0_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42400614UL))
+#define bFM3_MFT0_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42400618UL))
+#define bFM3_MFT0_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4240061CUL))
+#define bFM3_MFT0_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42400620UL))
+#define bFM3_MFT0_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42400624UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42400634UL))
+#define bFM3_MFT0_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42400638UL))
+#define bFM3_MFT0_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4240063CUL))
+#define bFM3_MFT0_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42400680UL))
+#define bFM3_MFT0_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42400684UL))
+#define bFM3_MFT0_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42400688UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42400800UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42400804UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42400808UL))
+#define bFM3_MFT0_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4240080CUL))
+#define bFM3_MFT0_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42400810UL))
+#define bFM3_MFT0_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42400814UL))
+#define bFM3_MFT0_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42400818UL))
+#define bFM3_MFT0_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4240081CUL))
+#define bFM3_MFT0_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42400820UL))
+#define bFM3_MFT0_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42400824UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42400834UL))
+#define bFM3_MFT0_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42400838UL))
+#define bFM3_MFT0_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4240083CUL))
+#define bFM3_MFT0_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42400880UL))
+#define bFM3_MFT0_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42400884UL))
+#define bFM3_MFT0_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42400888UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42400A00UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42400A04UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42400A08UL))
+#define bFM3_MFT0_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42400A0CUL))
+#define bFM3_MFT0_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42400A10UL))
+#define bFM3_MFT0_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42400A14UL))
+#define bFM3_MFT0_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42400A18UL))
+#define bFM3_MFT0_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42400A1CUL))
+#define bFM3_MFT0_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42400A20UL))
+#define bFM3_MFT0_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42400A24UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42400A34UL))
+#define bFM3_MFT0_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42400A38UL))
+#define bFM3_MFT0_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42400A3CUL))
+#define bFM3_MFT0_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42400A80UL))
+#define bFM3_MFT0_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42400A84UL))
+#define bFM3_MFT0_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42400A88UL))
+
+/* Multifunction Timer unit 0 Output Compare Unit registers */
+#define bFM3_MFT0_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42400300UL))
+#define bFM3_MFT0_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42400304UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42400308UL))
+#define bFM3_MFT0_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4240030CUL))
+#define bFM3_MFT0_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42400310UL))
+#define bFM3_MFT0_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42400314UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42400318UL))
+#define bFM3_MFT0_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4240031CUL))
+#define bFM3_MFT0_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42400320UL))
+#define bFM3_MFT0_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42400324UL))
+#define bFM3_MFT0_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42400330UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42400334UL))
+#define bFM3_MFT0_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42400338UL))
+#define bFM3_MFT0_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42400380UL))
+#define bFM3_MFT0_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42400384UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42400388UL))
+#define bFM3_MFT0_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4240038CUL))
+#define bFM3_MFT0_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42400390UL))
+#define bFM3_MFT0_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42400394UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42400398UL))
+#define bFM3_MFT0_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4240039CUL))
+#define bFM3_MFT0_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424003A0UL))
+#define bFM3_MFT0_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424003A4UL))
+#define bFM3_MFT0_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424003B0UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424003B4UL))
+#define bFM3_MFT0_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424003B8UL))
+#define bFM3_MFT0_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42400400UL))
+#define bFM3_MFT0_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42400404UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42400408UL))
+#define bFM3_MFT0_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4240040CUL))
+#define bFM3_MFT0_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42400410UL))
+#define bFM3_MFT0_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42400414UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42400418UL))
+#define bFM3_MFT0_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4240041CUL))
+#define bFM3_MFT0_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42400420UL))
+#define bFM3_MFT0_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42400424UL))
+#define bFM3_MFT0_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42400430UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42400434UL))
+#define bFM3_MFT0_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42400438UL))
+#define bFM3_MFT0_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424004A0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424004A4UL))
+#define bFM3_MFT0_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424004A8UL))
+#define bFM3_MFT0_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424004ACUL))
+#define bFM3_MFT0_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424004B0UL))
+#define bFM3_MFT0_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424004B4UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42400B00UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42400B04UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42400B08UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42400B0CUL))
+#define bFM3_MFT0_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42400B10UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42400B14UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42400B18UL))
+#define bFM3_MFT0_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42400B1CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42400B20UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42400B24UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42400B28UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42400B2CUL))
+#define bFM3_MFT0_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42400B30UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42400B34UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42400B38UL))
+#define bFM3_MFT0_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42400B3CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42400B80UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42400B84UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42400B88UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42400B8CUL))
+#define bFM3_MFT0_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42400B90UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42400B94UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42400B98UL))
+#define bFM3_MFT0_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42400B9CUL))
+
+/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT0_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42401180UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42401184UL))
+#define bFM3_MFT0_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42401188UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42401198UL))
+#define bFM3_MFT0_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4240119CUL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424011A0UL))
+#define bFM3_MFT0_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424011A4UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424011A8UL))
+#define bFM3_MFT0_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424011ACUL))
+#define bFM3_MFT0_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424011B0UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42401200UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42401204UL))
+#define bFM3_MFT0_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42401208UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42401218UL))
+#define bFM3_MFT0_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4240121CUL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42401220UL))
+#define bFM3_MFT0_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42401224UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42401228UL))
+#define bFM3_MFT0_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4240122CUL))
+#define bFM3_MFT0_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42401230UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42401280UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42401284UL))
+#define bFM3_MFT0_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42401288UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42401298UL))
+#define bFM3_MFT0_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4240129CUL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424012A0UL))
+#define bFM3_MFT0_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424012A4UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424012A8UL))
+#define bFM3_MFT0_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424012ACUL))
+#define bFM3_MFT0_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424012B0UL))
+#define bFM3_MFT0_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42401300UL))
+#define bFM3_MFT0_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42401304UL))
+#define bFM3_MFT0_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42401310UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42401314UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42401318UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4240131CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42401320UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42401324UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42401328UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4240132CUL))
+#define bFM3_MFT0_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42401330UL))
+#define bFM3_MFT0_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42401334UL))
+#define bFM3_MFT0_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42401338UL))
+#define bFM3_MFT0_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4240133CUL))
+#define bFM3_MFT0_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42401380UL))
+#define bFM3_MFT0_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42401384UL))
+#define bFM3_MFT0_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42401388UL))
+#define bFM3_MFT0_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4240138CUL))
+#define bFM3_MFT0_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42401390UL))
+
+/* Multifunction Timer unit 0 Input Capture Unit registers */
+#define bFM3_MFT0_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42400C00UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42400C04UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42400C08UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42400C0CUL))
+#define bFM3_MFT0_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42400C10UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42400C14UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42400C18UL))
+#define bFM3_MFT0_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42400C1CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42400C20UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42400C24UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42400C28UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42400C2CUL))
+#define bFM3_MFT0_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42400C30UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42400C34UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42400C38UL))
+#define bFM3_MFT0_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42400C3CUL))
+#define bFM3_MFT0_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42400F00UL))
+#define bFM3_MFT0_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42400F04UL))
+#define bFM3_MFT0_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42400F08UL))
+#define bFM3_MFT0_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42400F0CUL))
+#define bFM3_MFT0_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42400F10UL))
+#define bFM3_MFT0_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42400F14UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42400F18UL))
+#define bFM3_MFT0_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42400F1CUL))
+#define bFM3_MFT0_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42400F20UL))
+#define bFM3_MFT0_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42400F24UL))
+#define bFM3_MFT0_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42400F80UL))
+#define bFM3_MFT0_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42400F84UL))
+#define bFM3_MFT0_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42400F88UL))
+#define bFM3_MFT0_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42400F8CUL))
+#define bFM3_MFT0_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42400F90UL))
+#define bFM3_MFT0_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42400F94UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42400F98UL))
+#define bFM3_MFT0_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42400F9CUL))
+#define bFM3_MFT0_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42400FA0UL))
+#define bFM3_MFT0_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42400FA4UL))
+
+/* Multifunction Timer unit 0 ADC Start Compare Unit registers */
+#define bFM3_MFT0_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42401700UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42401704UL))
+#define bFM3_MFT0_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42401708UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42401710UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42401714UL))
+#define bFM3_MFT0_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42401718UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42401780UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42401784UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42401788UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4240178CUL))
+#define bFM3_MFT0_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42401790UL))
+#define bFM3_MFT0_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42401794UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424017A0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424017A4UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424017A8UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424017ACUL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424017B0UL))
+#define bFM3_MFT0_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424017B4UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42401800UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42401804UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42401808UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4240180CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42401810UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42401814UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42401820UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42401824UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42401828UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4240182CUL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42401830UL))
+#define bFM3_MFT0_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42401834UL))
+
+/* Multifunction Timer unit 1 Free Running Timer registers */
+#define bFM3_MFT1_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42420600UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42420604UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42420608UL))
+#define bFM3_MFT1_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4242060CUL))
+#define bFM3_MFT1_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42420610UL))
+#define bFM3_MFT1_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42420614UL))
+#define bFM3_MFT1_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42420618UL))
+#define bFM3_MFT1_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4242061CUL))
+#define bFM3_MFT1_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42420620UL))
+#define bFM3_MFT1_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42420624UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42420634UL))
+#define bFM3_MFT1_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42420638UL))
+#define bFM3_MFT1_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4242063CUL))
+#define bFM3_MFT1_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42420680UL))
+#define bFM3_MFT1_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42420684UL))
+#define bFM3_MFT1_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42420688UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42420800UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42420804UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42420808UL))
+#define bFM3_MFT1_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4242080CUL))
+#define bFM3_MFT1_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42420810UL))
+#define bFM3_MFT1_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42420814UL))
+#define bFM3_MFT1_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42420818UL))
+#define bFM3_MFT1_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4242081CUL))
+#define bFM3_MFT1_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42420820UL))
+#define bFM3_MFT1_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42420824UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42420834UL))
+#define bFM3_MFT1_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42420838UL))
+#define bFM3_MFT1_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4242083CUL))
+#define bFM3_MFT1_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42420880UL))
+#define bFM3_MFT1_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42420884UL))
+#define bFM3_MFT1_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42420888UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42420A00UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42420A04UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42420A08UL))
+#define bFM3_MFT1_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42420A0CUL))
+#define bFM3_MFT1_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42420A10UL))
+#define bFM3_MFT1_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42420A14UL))
+#define bFM3_MFT1_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42420A18UL))
+#define bFM3_MFT1_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42420A1CUL))
+#define bFM3_MFT1_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42420A20UL))
+#define bFM3_MFT1_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42420A24UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42420A34UL))
+#define bFM3_MFT1_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42420A38UL))
+#define bFM3_MFT1_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42420A3CUL))
+#define bFM3_MFT1_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42420A80UL))
+#define bFM3_MFT1_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42420A84UL))
+#define bFM3_MFT1_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42420A88UL))
+
+/* Multifunction Timer unit 1 Output Compare Unit registers */
+#define bFM3_MFT1_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42420300UL))
+#define bFM3_MFT1_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42420304UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42420308UL))
+#define bFM3_MFT1_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4242030CUL))
+#define bFM3_MFT1_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42420310UL))
+#define bFM3_MFT1_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42420314UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42420318UL))
+#define bFM3_MFT1_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4242031CUL))
+#define bFM3_MFT1_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42420320UL))
+#define bFM3_MFT1_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42420324UL))
+#define bFM3_MFT1_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42420330UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42420334UL))
+#define bFM3_MFT1_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42420338UL))
+#define bFM3_MFT1_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42420380UL))
+#define bFM3_MFT1_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42420384UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42420388UL))
+#define bFM3_MFT1_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4242038CUL))
+#define bFM3_MFT1_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42420390UL))
+#define bFM3_MFT1_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42420394UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42420398UL))
+#define bFM3_MFT1_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4242039CUL))
+#define bFM3_MFT1_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424203A0UL))
+#define bFM3_MFT1_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424203A4UL))
+#define bFM3_MFT1_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424203B0UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424203B4UL))
+#define bFM3_MFT1_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424203B8UL))
+#define bFM3_MFT1_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42420400UL))
+#define bFM3_MFT1_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42420404UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42420408UL))
+#define bFM3_MFT1_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4242040CUL))
+#define bFM3_MFT1_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42420410UL))
+#define bFM3_MFT1_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42420414UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42420418UL))
+#define bFM3_MFT1_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4242041CUL))
+#define bFM3_MFT1_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42420420UL))
+#define bFM3_MFT1_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42420424UL))
+#define bFM3_MFT1_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42420430UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42420434UL))
+#define bFM3_MFT1_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42420438UL))
+#define bFM3_MFT1_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424204A0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424204A4UL))
+#define bFM3_MFT1_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424204A8UL))
+#define bFM3_MFT1_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424204ACUL))
+#define bFM3_MFT1_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424204B0UL))
+#define bFM3_MFT1_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424204B4UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42420B00UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42420B04UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42420B08UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42420B0CUL))
+#define bFM3_MFT1_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42420B10UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42420B14UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42420B18UL))
+#define bFM3_MFT1_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42420B1CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42420B20UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42420B24UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42420B28UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42420B2CUL))
+#define bFM3_MFT1_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42420B30UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42420B34UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42420B38UL))
+#define bFM3_MFT1_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42420B3CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42420B80UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42420B84UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42420B88UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42420B8CUL))
+#define bFM3_MFT1_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42420B90UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42420B94UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42420B98UL))
+#define bFM3_MFT1_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42420B9CUL))
+
+/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT1_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42421180UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42421184UL))
+#define bFM3_MFT1_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42421188UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42421198UL))
+#define bFM3_MFT1_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4242119CUL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424211A0UL))
+#define bFM3_MFT1_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424211A4UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424211A8UL))
+#define bFM3_MFT1_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424211ACUL))
+#define bFM3_MFT1_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424211B0UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42421200UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42421204UL))
+#define bFM3_MFT1_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42421208UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42421218UL))
+#define bFM3_MFT1_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4242121CUL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42421220UL))
+#define bFM3_MFT1_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42421224UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42421228UL))
+#define bFM3_MFT1_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4242122CUL))
+#define bFM3_MFT1_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42421230UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42421280UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42421284UL))
+#define bFM3_MFT1_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42421288UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42421298UL))
+#define bFM3_MFT1_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4242129CUL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424212A0UL))
+#define bFM3_MFT1_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424212A4UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424212A8UL))
+#define bFM3_MFT1_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424212ACUL))
+#define bFM3_MFT1_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424212B0UL))
+#define bFM3_MFT1_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42421300UL))
+#define bFM3_MFT1_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42421304UL))
+#define bFM3_MFT1_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42421310UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42421314UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42421318UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4242131CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42421320UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42421324UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42421328UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4242132CUL))
+#define bFM3_MFT1_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42421330UL))
+#define bFM3_MFT1_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42421334UL))
+#define bFM3_MFT1_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42421338UL))
+#define bFM3_MFT1_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4242133CUL))
+#define bFM3_MFT1_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42421380UL))
+#define bFM3_MFT1_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42421384UL))
+#define bFM3_MFT1_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42421388UL))
+#define bFM3_MFT1_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4242138CUL))
+#define bFM3_MFT1_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42421390UL))
+
+/* Multifunction Timer unit 1 Input Capture Unit registers */
+#define bFM3_MFT1_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42420C00UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42420C04UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42420C08UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42420C0CUL))
+#define bFM3_MFT1_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42420C10UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42420C14UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42420C18UL))
+#define bFM3_MFT1_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42420C1CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42420C20UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42420C24UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42420C28UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42420C2CUL))
+#define bFM3_MFT1_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42420C30UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42420C34UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42420C38UL))
+#define bFM3_MFT1_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42420C3CUL))
+#define bFM3_MFT1_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42420F00UL))
+#define bFM3_MFT1_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42420F04UL))
+#define bFM3_MFT1_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42420F08UL))
+#define bFM3_MFT1_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42420F0CUL))
+#define bFM3_MFT1_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42420F10UL))
+#define bFM3_MFT1_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42420F14UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42420F18UL))
+#define bFM3_MFT1_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42420F1CUL))
+#define bFM3_MFT1_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42420F20UL))
+#define bFM3_MFT1_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42420F24UL))
+#define bFM3_MFT1_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42420F80UL))
+#define bFM3_MFT1_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42420F84UL))
+#define bFM3_MFT1_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42420F88UL))
+#define bFM3_MFT1_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42420F8CUL))
+#define bFM3_MFT1_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42420F90UL))
+#define bFM3_MFT1_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42420F94UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42420F98UL))
+#define bFM3_MFT1_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42420F9CUL))
+#define bFM3_MFT1_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42420FA0UL))
+#define bFM3_MFT1_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42420FA4UL))
+
+/* Multifunction Timer unit 1 ADC Start Compare Unit registers */
+#define bFM3_MFT1_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42421700UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42421704UL))
+#define bFM3_MFT1_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42421708UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42421710UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42421714UL))
+#define bFM3_MFT1_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42421718UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42421780UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42421784UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42421788UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4242178CUL))
+#define bFM3_MFT1_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42421790UL))
+#define bFM3_MFT1_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42421794UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424217A0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424217A4UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424217A8UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424217ACUL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424217B0UL))
+#define bFM3_MFT1_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424217B4UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42421800UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42421804UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42421808UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4242180CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42421810UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42421814UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42421820UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42421824UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42421828UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4242182CUL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42421830UL))
+#define bFM3_MFT1_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42421834UL))
+
+/* Multifunction Timer unit 2 Free Running Timer registers */
+#define bFM3_MFT2_FRT_TCSA0_CLK0               *((volatile unsigned int*)(0x42440600UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK1               *((volatile unsigned int*)(0x42440604UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK2               *((volatile unsigned int*)(0x42440608UL))
+#define bFM3_MFT2_FRT_TCSA0_CLK3               *((volatile unsigned int*)(0x4244060CUL))
+#define bFM3_MFT2_FRT_TCSA0_SCLR               *((volatile unsigned int*)(0x42440610UL))
+#define bFM3_MFT2_FRT_TCSA0_MODE               *((volatile unsigned int*)(0x42440614UL))
+#define bFM3_MFT2_FRT_TCSA0_STOP               *((volatile unsigned int*)(0x42440618UL))
+#define bFM3_MFT2_FRT_TCSA0_BFE                *((volatile unsigned int*)(0x4244061CUL))
+#define bFM3_MFT2_FRT_TCSA0_ICRE               *((volatile unsigned int*)(0x42440620UL))
+#define bFM3_MFT2_FRT_TCSA0_ICLR               *((volatile unsigned int*)(0x42440624UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZE              *((volatile unsigned int*)(0x42440634UL))
+#define bFM3_MFT2_FRT_TCSA0_IRQZF              *((volatile unsigned int*)(0x42440638UL))
+#define bFM3_MFT2_FRT_TCSA0_ECKE               *((volatile unsigned int*)(0x4244063CUL))
+#define bFM3_MFT2_FRT_TCSB0_AD0E               *((volatile unsigned int*)(0x42440680UL))
+#define bFM3_MFT2_FRT_TCSB0_AD1E               *((volatile unsigned int*)(0x42440684UL))
+#define bFM3_MFT2_FRT_TCSB0_AD2E               *((volatile unsigned int*)(0x42440688UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK0               *((volatile unsigned int*)(0x42440800UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK1               *((volatile unsigned int*)(0x42440804UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK2               *((volatile unsigned int*)(0x42440808UL))
+#define bFM3_MFT2_FRT_TCSA1_CLK3               *((volatile unsigned int*)(0x4244080CUL))
+#define bFM3_MFT2_FRT_TCSA1_SCLR               *((volatile unsigned int*)(0x42440810UL))
+#define bFM3_MFT2_FRT_TCSA1_MODE               *((volatile unsigned int*)(0x42440814UL))
+#define bFM3_MFT2_FRT_TCSA1_STOP               *((volatile unsigned int*)(0x42440818UL))
+#define bFM3_MFT2_FRT_TCSA1_BFE                *((volatile unsigned int*)(0x4244081CUL))
+#define bFM3_MFT2_FRT_TCSA1_ICRE               *((volatile unsigned int*)(0x42440820UL))
+#define bFM3_MFT2_FRT_TCSA1_ICLR               *((volatile unsigned int*)(0x42440824UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZE              *((volatile unsigned int*)(0x42440834UL))
+#define bFM3_MFT2_FRT_TCSA1_IRQZF              *((volatile unsigned int*)(0x42440838UL))
+#define bFM3_MFT2_FRT_TCSA1_ECKE               *((volatile unsigned int*)(0x4244083CUL))
+#define bFM3_MFT2_FRT_TCSB1_AD0E               *((volatile unsigned int*)(0x42440880UL))
+#define bFM3_MFT2_FRT_TCSB1_AD1E               *((volatile unsigned int*)(0x42440884UL))
+#define bFM3_MFT2_FRT_TCSB1_AD2E               *((volatile unsigned int*)(0x42440888UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK0               *((volatile unsigned int*)(0x42440A00UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK1               *((volatile unsigned int*)(0x42440A04UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK2               *((volatile unsigned int*)(0x42440A08UL))
+#define bFM3_MFT2_FRT_TCSA2_CLK3               *((volatile unsigned int*)(0x42440A0CUL))
+#define bFM3_MFT2_FRT_TCSA2_SCLR               *((volatile unsigned int*)(0x42440A10UL))
+#define bFM3_MFT2_FRT_TCSA2_MODE               *((volatile unsigned int*)(0x42440A14UL))
+#define bFM3_MFT2_FRT_TCSA2_STOP               *((volatile unsigned int*)(0x42440A18UL))
+#define bFM3_MFT2_FRT_TCSA2_BFE                *((volatile unsigned int*)(0x42440A1CUL))
+#define bFM3_MFT2_FRT_TCSA2_ICRE               *((volatile unsigned int*)(0x42440A20UL))
+#define bFM3_MFT2_FRT_TCSA2_ICLR               *((volatile unsigned int*)(0x42440A24UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZE              *((volatile unsigned int*)(0x42440A34UL))
+#define bFM3_MFT2_FRT_TCSA2_IRQZF              *((volatile unsigned int*)(0x42440A38UL))
+#define bFM3_MFT2_FRT_TCSA2_ECKE               *((volatile unsigned int*)(0x42440A3CUL))
+#define bFM3_MFT2_FRT_TCSB2_AD0E               *((volatile unsigned int*)(0x42440A80UL))
+#define bFM3_MFT2_FRT_TCSB2_AD1E               *((volatile unsigned int*)(0x42440A84UL))
+#define bFM3_MFT2_FRT_TCSB2_AD2E               *((volatile unsigned int*)(0x42440A88UL))
+
+/* Multifunction Timer unit 2 Output Compare Unit registers */
+#define bFM3_MFT2_OCU_OCSA10_CST0              *((volatile unsigned int*)(0x42440300UL))
+#define bFM3_MFT2_OCU_OCSA10_CST1              *((volatile unsigned int*)(0x42440304UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS0             *((volatile unsigned int*)(0x42440308UL))
+#define bFM3_MFT2_OCU_OCSA10_BDIS1             *((volatile unsigned int*)(0x4244030CUL))
+#define bFM3_MFT2_OCU_OCSA10_IOE0              *((volatile unsigned int*)(0x42440310UL))
+#define bFM3_MFT2_OCU_OCSA10_IOE1              *((volatile unsigned int*)(0x42440314UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP0              *((volatile unsigned int*)(0x42440318UL))
+#define bFM3_MFT2_OCU_OCSA10_IOP1              *((volatile unsigned int*)(0x4244031CUL))
+#define bFM3_MFT2_OCU_OCSB10_OTD0              *((volatile unsigned int*)(0x42440320UL))
+#define bFM3_MFT2_OCU_OCSB10_OTD1              *((volatile unsigned int*)(0x42440324UL))
+#define bFM3_MFT2_OCU_OCSB10_CMOD              *((volatile unsigned int*)(0x42440330UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS0              *((volatile unsigned int*)(0x42440334UL))
+#define bFM3_MFT2_OCU_OCSB10_BTS1              *((volatile unsigned int*)(0x42440338UL))
+#define bFM3_MFT2_OCU_OCSA32_CST2              *((volatile unsigned int*)(0x42440380UL))
+#define bFM3_MFT2_OCU_OCSA32_CST3              *((volatile unsigned int*)(0x42440384UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS2             *((volatile unsigned int*)(0x42440388UL))
+#define bFM3_MFT2_OCU_OCSA32_BDIS3             *((volatile unsigned int*)(0x4244038CUL))
+#define bFM3_MFT2_OCU_OCSA32_IOE2              *((volatile unsigned int*)(0x42440390UL))
+#define bFM3_MFT2_OCU_OCSA32_IOE3              *((volatile unsigned int*)(0x42440394UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP2              *((volatile unsigned int*)(0x42440398UL))
+#define bFM3_MFT2_OCU_OCSA32_IOP3              *((volatile unsigned int*)(0x4244039CUL))
+#define bFM3_MFT2_OCU_OCSB32_OTD2              *((volatile unsigned int*)(0x424403A0UL))
+#define bFM3_MFT2_OCU_OCSB32_OTD3              *((volatile unsigned int*)(0x424403A4UL))
+#define bFM3_MFT2_OCU_OCSB32_CMOD              *((volatile unsigned int*)(0x424403B0UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS2              *((volatile unsigned int*)(0x424403B4UL))
+#define bFM3_MFT2_OCU_OCSB32_BTS3              *((volatile unsigned int*)(0x424403B8UL))
+#define bFM3_MFT2_OCU_OCSA54_CST4              *((volatile unsigned int*)(0x42440400UL))
+#define bFM3_MFT2_OCU_OCSA54_CST5              *((volatile unsigned int*)(0x42440404UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS4             *((volatile unsigned int*)(0x42440408UL))
+#define bFM3_MFT2_OCU_OCSA54_BDIS5             *((volatile unsigned int*)(0x4244040CUL))
+#define bFM3_MFT2_OCU_OCSA54_IOE4              *((volatile unsigned int*)(0x42440410UL))
+#define bFM3_MFT2_OCU_OCSA54_IOE5              *((volatile unsigned int*)(0x42440414UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP4              *((volatile unsigned int*)(0x42440418UL))
+#define bFM3_MFT2_OCU_OCSA54_IOP5              *((volatile unsigned int*)(0x4244041CUL))
+#define bFM3_MFT2_OCU_OCSB54_OTD4              *((volatile unsigned int*)(0x42440420UL))
+#define bFM3_MFT2_OCU_OCSB54_OTD5              *((volatile unsigned int*)(0x42440424UL))
+#define bFM3_MFT2_OCU_OCSB54_CMOD              *((volatile unsigned int*)(0x42440430UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS4              *((volatile unsigned int*)(0x42440434UL))
+#define bFM3_MFT2_OCU_OCSB54_BTS5              *((volatile unsigned int*)(0x42440438UL))
+#define bFM3_MFT2_OCU_OCSC_MOD0                *((volatile unsigned int*)(0x424404A0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD1                *((volatile unsigned int*)(0x424404A4UL))
+#define bFM3_MFT2_OCU_OCSC_MOD2                *((volatile unsigned int*)(0x424404A8UL))
+#define bFM3_MFT2_OCU_OCSC_MOD3                *((volatile unsigned int*)(0x424404ACUL))
+#define bFM3_MFT2_OCU_OCSC_MOD4                *((volatile unsigned int*)(0x424404B0UL))
+#define bFM3_MFT2_OCU_OCSC_MOD5                *((volatile unsigned int*)(0x424404B4UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO00             *((volatile unsigned int*)(0x42440B00UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO01             *((volatile unsigned int*)(0x42440B04UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO02             *((volatile unsigned int*)(0x42440B08UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO03             *((volatile unsigned int*)(0x42440B0CUL))
+#define bFM3_MFT2_OCU_OCFS10_FSO10             *((volatile unsigned int*)(0x42440B10UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO11             *((volatile unsigned int*)(0x42440B14UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO12             *((volatile unsigned int*)(0x42440B18UL))
+#define bFM3_MFT2_OCU_OCFS10_FSO13             *((volatile unsigned int*)(0x42440B1CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO20             *((volatile unsigned int*)(0x42440B20UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO21             *((volatile unsigned int*)(0x42440B24UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO22             *((volatile unsigned int*)(0x42440B28UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO23             *((volatile unsigned int*)(0x42440B2CUL))
+#define bFM3_MFT2_OCU_OCFS32_FSO30             *((volatile unsigned int*)(0x42440B30UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO31             *((volatile unsigned int*)(0x42440B34UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO32             *((volatile unsigned int*)(0x42440B38UL))
+#define bFM3_MFT2_OCU_OCFS32_FSO33             *((volatile unsigned int*)(0x42440B3CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO40             *((volatile unsigned int*)(0x42440B80UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO41             *((volatile unsigned int*)(0x42440B84UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO42             *((volatile unsigned int*)(0x42440B88UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO43             *((volatile unsigned int*)(0x42440B8CUL))
+#define bFM3_MFT2_OCU_OCFS54_FSO50             *((volatile unsigned int*)(0x42440B90UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO51             *((volatile unsigned int*)(0x42440B94UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO52             *((volatile unsigned int*)(0x42440B98UL))
+#define bFM3_MFT2_OCU_OCFS54_FSO53             *((volatile unsigned int*)(0x42440B9CUL))
+
+/* Multifunction Timer unit 2 Waveform Generator and Noise Canceler registers */
+#define bFM3_MFT2_WFG_WFSA10_DCK0              *((volatile unsigned int*)(0x42441180UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK1              *((volatile unsigned int*)(0x42441184UL))
+#define bFM3_MFT2_WFG_WFSA10_DCK2              *((volatile unsigned int*)(0x42441188UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN0             *((volatile unsigned int*)(0x42441198UL))
+#define bFM3_MFT2_WFG_WFSA10_GTEN1             *((volatile unsigned int*)(0x4244119CUL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL0             *((volatile unsigned int*)(0x424411A0UL))
+#define bFM3_MFT2_WFG_WFSA10_PSEL1             *((volatile unsigned int*)(0x424411A4UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN0             *((volatile unsigned int*)(0x424411A8UL))
+#define bFM3_MFT2_WFG_WFSA10_PGEN1             *((volatile unsigned int*)(0x424411ACUL))
+#define bFM3_MFT2_WFG_WFSA10_DMOD              *((volatile unsigned int*)(0x424411B0UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK0              *((volatile unsigned int*)(0x42441200UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK1              *((volatile unsigned int*)(0x42441204UL))
+#define bFM3_MFT2_WFG_WFSA32_DCK2              *((volatile unsigned int*)(0x42441208UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN0             *((volatile unsigned int*)(0x42441218UL))
+#define bFM3_MFT2_WFG_WFSA32_GTEN1             *((volatile unsigned int*)(0x4244121CUL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL0             *((volatile unsigned int*)(0x42441220UL))
+#define bFM3_MFT2_WFG_WFSA32_PSEL1             *((volatile unsigned int*)(0x42441224UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN0             *((volatile unsigned int*)(0x42441228UL))
+#define bFM3_MFT2_WFG_WFSA32_PGEN1             *((volatile unsigned int*)(0x4244122CUL))
+#define bFM3_MFT2_WFG_WFSA32_DMOD              *((volatile unsigned int*)(0x42441230UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK0              *((volatile unsigned int*)(0x42441280UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK1              *((volatile unsigned int*)(0x42441284UL))
+#define bFM3_MFT2_WFG_WFSA54_DCK2              *((volatile unsigned int*)(0x42441288UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN0             *((volatile unsigned int*)(0x42441298UL))
+#define bFM3_MFT2_WFG_WFSA54_GTEN1             *((volatile unsigned int*)(0x4244129CUL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL0             *((volatile unsigned int*)(0x424412A0UL))
+#define bFM3_MFT2_WFG_WFSA54_PSEL1             *((volatile unsigned int*)(0x424412A4UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN0             *((volatile unsigned int*)(0x424412A8UL))
+#define bFM3_MFT2_WFG_WFSA54_PGEN1             *((volatile unsigned int*)(0x424412ACUL))
+#define bFM3_MFT2_WFG_WFSA54_DMOD              *((volatile unsigned int*)(0x424412B0UL))
+#define bFM3_MFT2_WFG_WFIR_DTIF                *((volatile unsigned int*)(0x42441300UL))
+#define bFM3_MFT2_WFG_WFIR_DTIC                *((volatile unsigned int*)(0x42441304UL))
+#define bFM3_MFT2_WFG_WFIR_TMIF10              *((volatile unsigned int*)(0x42441310UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC10              *((volatile unsigned int*)(0x42441314UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE10              *((volatile unsigned int*)(0x42441318UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS10              *((volatile unsigned int*)(0x4244131CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF32              *((volatile unsigned int*)(0x42441320UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC32              *((volatile unsigned int*)(0x42441324UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE32              *((volatile unsigned int*)(0x42441328UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS32              *((volatile unsigned int*)(0x4244132CUL))
+#define bFM3_MFT2_WFG_WFIR_TMIF54              *((volatile unsigned int*)(0x42441330UL))
+#define bFM3_MFT2_WFG_WFIR_TMIC54              *((volatile unsigned int*)(0x42441334UL))
+#define bFM3_MFT2_WFG_WFIR_TMIE54              *((volatile unsigned int*)(0x42441338UL))
+#define bFM3_MFT2_WFG_WFIR_TMIS54              *((volatile unsigned int*)(0x4244133CUL))
+#define bFM3_MFT2_WFG_NZCL_DTIE                *((volatile unsigned int*)(0x42441380UL))
+#define bFM3_MFT2_WFG_NZCL_NWS0                *((volatile unsigned int*)(0x42441384UL))
+#define bFM3_MFT2_WFG_NZCL_NWS1                *((volatile unsigned int*)(0x42441388UL))
+#define bFM3_MFT2_WFG_NZCL_NWS2                *((volatile unsigned int*)(0x4244138CUL))
+#define bFM3_MFT2_WFG_NZCL_SDTI                *((volatile unsigned int*)(0x42441390UL))
+
+/* Multifunction Timer unit 2 Input Capture Unit registers */
+#define bFM3_MFT2_ICU_ICFS10_FSI00             *((volatile unsigned int*)(0x42440C00UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI01             *((volatile unsigned int*)(0x42440C04UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI02             *((volatile unsigned int*)(0x42440C08UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI03             *((volatile unsigned int*)(0x42440C0CUL))
+#define bFM3_MFT2_ICU_ICFS10_FSI10             *((volatile unsigned int*)(0x42440C10UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI11             *((volatile unsigned int*)(0x42440C14UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI12             *((volatile unsigned int*)(0x42440C18UL))
+#define bFM3_MFT2_ICU_ICFS10_FSI13             *((volatile unsigned int*)(0x42440C1CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI20             *((volatile unsigned int*)(0x42440C20UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI21             *((volatile unsigned int*)(0x42440C24UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI22             *((volatile unsigned int*)(0x42440C28UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI23             *((volatile unsigned int*)(0x42440C2CUL))
+#define bFM3_MFT2_ICU_ICFS32_FSI30             *((volatile unsigned int*)(0x42440C30UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI31             *((volatile unsigned int*)(0x42440C34UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI32             *((volatile unsigned int*)(0x42440C38UL))
+#define bFM3_MFT2_ICU_ICFS32_FSI33             *((volatile unsigned int*)(0x42440C3CUL))
+#define bFM3_MFT2_ICU_ICSA10_EG00              *((volatile unsigned int*)(0x42440F00UL))
+#define bFM3_MFT2_ICU_ICSA10_EG01              *((volatile unsigned int*)(0x42440F04UL))
+#define bFM3_MFT2_ICU_ICSA10_EG10              *((volatile unsigned int*)(0x42440F08UL))
+#define bFM3_MFT2_ICU_ICSA10_EG11              *((volatile unsigned int*)(0x42440F0CUL))
+#define bFM3_MFT2_ICU_ICSA10_ICE0              *((volatile unsigned int*)(0x42440F10UL))
+#define bFM3_MFT2_ICU_ICSA10_ICE1              *((volatile unsigned int*)(0x42440F14UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP0              *((volatile unsigned int*)(0x42440F18UL))
+#define bFM3_MFT2_ICU_ICSA10_ICP1              *((volatile unsigned int*)(0x42440F1CUL))
+#define bFM3_MFT2_ICU_ICSB10_IEI0              *((volatile unsigned int*)(0x42440F20UL))
+#define bFM3_MFT2_ICU_ICSB10_IEI1              *((volatile unsigned int*)(0x42440F24UL))
+#define bFM3_MFT2_ICU_ICSA32_EG20              *((volatile unsigned int*)(0x42440F80UL))
+#define bFM3_MFT2_ICU_ICSA32_EG21              *((volatile unsigned int*)(0x42440F84UL))
+#define bFM3_MFT2_ICU_ICSA32_EG30              *((volatile unsigned int*)(0x42440F88UL))
+#define bFM3_MFT2_ICU_ICSA32_EG31              *((volatile unsigned int*)(0x42440F8CUL))
+#define bFM3_MFT2_ICU_ICSA32_ICE2              *((volatile unsigned int*)(0x42440F90UL))
+#define bFM3_MFT2_ICU_ICSA32_ICE3              *((volatile unsigned int*)(0x42440F94UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP2              *((volatile unsigned int*)(0x42440F98UL))
+#define bFM3_MFT2_ICU_ICSA32_ICP3              *((volatile unsigned int*)(0x42440F9CUL))
+#define bFM3_MFT2_ICU_ICSB32_IEI2              *((volatile unsigned int*)(0x42440FA0UL))
+#define bFM3_MFT2_ICU_ICSB32_IEI3              *((volatile unsigned int*)(0x42440FA4UL))
+
+/* Multifunction Timer unit 2 ADC Start Compare Unit registers */
+#define bFM3_MFT2_ADCMP_ACSB_BDIS0             *((volatile unsigned int*)(0x42441700UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS1             *((volatile unsigned int*)(0x42441704UL))
+#define bFM3_MFT2_ADCMP_ACSB_BDIS2             *((volatile unsigned int*)(0x42441708UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS0              *((volatile unsigned int*)(0x42441710UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS1              *((volatile unsigned int*)(0x42441714UL))
+#define bFM3_MFT2_ADCMP_ACSB_BTS2              *((volatile unsigned int*)(0x42441718UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE00              *((volatile unsigned int*)(0x42441780UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE01              *((volatile unsigned int*)(0x42441784UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE10              *((volatile unsigned int*)(0x42441788UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE11              *((volatile unsigned int*)(0x4244178CUL))
+#define bFM3_MFT2_ADCMP_ACSA_CE20              *((volatile unsigned int*)(0x42441790UL))
+#define bFM3_MFT2_ADCMP_ACSA_CE21              *((volatile unsigned int*)(0x42441794UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL00             *((volatile unsigned int*)(0x424417A0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL01             *((volatile unsigned int*)(0x424417A4UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL10             *((volatile unsigned int*)(0x424417A8UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL11             *((volatile unsigned int*)(0x424417ACUL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL20             *((volatile unsigned int*)(0x424417B0UL))
+#define bFM3_MFT2_ADCMP_ACSA_SEL21             *((volatile unsigned int*)(0x424417B4UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S0             *((volatile unsigned int*)(0x42441800UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0S1             *((volatile unsigned int*)(0x42441804UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S0             *((volatile unsigned int*)(0x42441808UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1S1             *((volatile unsigned int*)(0x4244180CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S0             *((volatile unsigned int*)(0x42441810UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2S1             *((volatile unsigned int*)(0x42441814UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P0             *((volatile unsigned int*)(0x42441820UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD0P1             *((volatile unsigned int*)(0x42441824UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P0             *((volatile unsigned int*)(0x42441828UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD1P1             *((volatile unsigned int*)(0x4244182CUL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P0             *((volatile unsigned int*)(0x42441830UL))
+#define bFM3_MFT2_ADCMP_ATSA_AD2P1             *((volatile unsigned int*)(0x42441834UL))
+
+/* Multifunction Timer PPG registers */
+#define bFM3_MFT_PPG_TTCR0_STR0                *((volatile unsigned int*)(0x42480020UL))
+#define bFM3_MFT_PPG_TTCR0_MONI0               *((volatile unsigned int*)(0x42480024UL))
+#define bFM3_MFT_PPG_TTCR0_CS00                *((volatile unsigned int*)(0x42480028UL))
+#define bFM3_MFT_PPG_TTCR0_CS01                *((volatile unsigned int*)(0x4248002CUL))
+#define bFM3_MFT_PPG_TTCR0_TRG0O               *((volatile unsigned int*)(0x42480030UL))
+#define bFM3_MFT_PPG_TTCR0_TRG2O               *((volatile unsigned int*)(0x42480034UL))
+#define bFM3_MFT_PPG_TTCR0_TRG4O               *((volatile unsigned int*)(0x42480038UL))
+#define bFM3_MFT_PPG_TTCR0_TRG6O               *((volatile unsigned int*)(0x4248003CUL))
+#define bFM3_MFT_PPG_TTCR1_STR1                *((volatile unsigned int*)(0x42480420UL))
+#define bFM3_MFT_PPG_TTCR1_MONI1               *((volatile unsigned int*)(0x42480424UL))
+#define bFM3_MFT_PPG_TTCR1_CS10                *((volatile unsigned int*)(0x42480428UL))
+#define bFM3_MFT_PPG_TTCR1_CS11                *((volatile unsigned int*)(0x4248042CUL))
+#define bFM3_MFT_PPG_TTCR1_TRG1O               *((volatile unsigned int*)(0x42480430UL))
+#define bFM3_MFT_PPG_TTCR1_TRG3O               *((volatile unsigned int*)(0x42480434UL))
+#define bFM3_MFT_PPG_TTCR1_TRG5O               *((volatile unsigned int*)(0x42480438UL))
+#define bFM3_MFT_PPG_TTCR1_TRG7O               *((volatile unsigned int*)(0x4248043CUL))
+#define bFM3_MFT_PPG_TTCR2_STR2                *((volatile unsigned int*)(0x42480820UL))
+#define bFM3_MFT_PPG_TTCR2_MONI2               *((volatile unsigned int*)(0x42480824UL))
+#define bFM3_MFT_PPG_TTCR2_CS20                *((volatile unsigned int*)(0x42480828UL))
+#define bFM3_MFT_PPG_TTCR2_CS21                *((volatile unsigned int*)(0x4248082CUL))
+#define bFM3_MFT_PPG_TTCR2_TRG16O              *((volatile unsigned int*)(0x42480830UL))
+#define bFM3_MFT_PPG_TTCR2_TRG18O              *((volatile unsigned int*)(0x42480834UL))
+#define bFM3_MFT_PPG_TTCR2_TRG20O              *((volatile unsigned int*)(0x42480838UL))
+#define bFM3_MFT_PPG_TTCR2_TRG22O              *((volatile unsigned int*)(0x4248083CUL))
+#define bFM3_MFT_PPG_TRG_PEN00                 *((volatile unsigned int*)(0x42482000UL))
+#define bFM3_MFT_PPG_TRG_PEN01                 *((volatile unsigned int*)(0x42482004UL))
+#define bFM3_MFT_PPG_TRG_PEN02                 *((volatile unsigned int*)(0x42482008UL))
+#define bFM3_MFT_PPG_TRG_PEN03                 *((volatile unsigned int*)(0x4248200CUL))
+#define bFM3_MFT_PPG_TRG_PEN04                 *((volatile unsigned int*)(0x42482010UL))
+#define bFM3_MFT_PPG_TRG_PEN05                 *((volatile unsigned int*)(0x42482014UL))
+#define bFM3_MFT_PPG_TRG_PEN06                 *((volatile unsigned int*)(0x42482018UL))
+#define bFM3_MFT_PPG_TRG_PEN07                 *((volatile unsigned int*)(0x4248201CUL))
+#define bFM3_MFT_PPG_TRG_PEN08                 *((volatile unsigned int*)(0x42482020UL))
+#define bFM3_MFT_PPG_TRG_PEN09                 *((volatile unsigned int*)(0x42482024UL))
+#define bFM3_MFT_PPG_TRG_PEN10                 *((volatile unsigned int*)(0x42482028UL))
+#define bFM3_MFT_PPG_TRG_PEN11                 *((volatile unsigned int*)(0x4248202CUL))
+#define bFM3_MFT_PPG_TRG_PEN12                 *((volatile unsigned int*)(0x42482030UL))
+#define bFM3_MFT_PPG_TRG_PEN13                 *((volatile unsigned int*)(0x42482034UL))
+#define bFM3_MFT_PPG_TRG_PEN14                 *((volatile unsigned int*)(0x42482038UL))
+#define bFM3_MFT_PPG_TRG_PEN15                 *((volatile unsigned int*)(0x4248203CUL))
+#define bFM3_MFT_PPG_REVC_REV00                *((volatile unsigned int*)(0x42482080UL))
+#define bFM3_MFT_PPG_REVC_REV01                *((volatile unsigned int*)(0x42482084UL))
+#define bFM3_MFT_PPG_REVC_REV02                *((volatile unsigned int*)(0x42482088UL))
+#define bFM3_MFT_PPG_REVC_REV03                *((volatile unsigned int*)(0x4248208CUL))
+#define bFM3_MFT_PPG_REVC_REV04                *((volatile unsigned int*)(0x42482090UL))
+#define bFM3_MFT_PPG_REVC_REV05                *((volatile unsigned int*)(0x42482094UL))
+#define bFM3_MFT_PPG_REVC_REV06                *((volatile unsigned int*)(0x42482098UL))
+#define bFM3_MFT_PPG_REVC_REV07                *((volatile unsigned int*)(0x4248209CUL))
+#define bFM3_MFT_PPG_REVC_REV08                *((volatile unsigned int*)(0x424820A0UL))
+#define bFM3_MFT_PPG_REVC_REV09                *((volatile unsigned int*)(0x424820A4UL))
+#define bFM3_MFT_PPG_REVC_REV10                *((volatile unsigned int*)(0x424820A8UL))
+#define bFM3_MFT_PPG_REVC_REV11                *((volatile unsigned int*)(0x424820ACUL))
+#define bFM3_MFT_PPG_REVC_REV12                *((volatile unsigned int*)(0x424820B0UL))
+#define bFM3_MFT_PPG_REVC_REV13                *((volatile unsigned int*)(0x424820B4UL))
+#define bFM3_MFT_PPG_REVC_REV14                *((volatile unsigned int*)(0x424820B8UL))
+#define bFM3_MFT_PPG_REVC_REV15                *((volatile unsigned int*)(0x424820BCUL))
+#define bFM3_MFT_PPG_TRG1_PEN16                *((volatile unsigned int*)(0x42482800UL))
+#define bFM3_MFT_PPG_TRG1_PEN17                *((volatile unsigned int*)(0x42482804UL))
+#define bFM3_MFT_PPG_TRG1_PEN18                *((volatile unsigned int*)(0x42482808UL))
+#define bFM3_MFT_PPG_TRG1_PEN19                *((volatile unsigned int*)(0x4248280CUL))
+#define bFM3_MFT_PPG_TRG1_PEN20                *((volatile unsigned int*)(0x42482810UL))
+#define bFM3_MFT_PPG_TRG1_PEN21                *((volatile unsigned int*)(0x42482814UL))
+#define bFM3_MFT_PPG_TRG1_PEN22                *((volatile unsigned int*)(0x42482818UL))
+#define bFM3_MFT_PPG_TRG1_PEN23                *((volatile unsigned int*)(0x4248281CUL))
+#define bFM3_MFT_PPG_REVC1_REV16               *((volatile unsigned int*)(0x42482880UL))
+#define bFM3_MFT_PPG_REVC1_REV17               *((volatile unsigned int*)(0x42482884UL))
+#define bFM3_MFT_PPG_REVC1_REV18               *((volatile unsigned int*)(0x42482888UL))
+#define bFM3_MFT_PPG_REVC1_REV19               *((volatile unsigned int*)(0x4248288CUL))
+#define bFM3_MFT_PPG_REVC1_REV20               *((volatile unsigned int*)(0x42482890UL))
+#define bFM3_MFT_PPG_REVC1_REV21               *((volatile unsigned int*)(0x42482894UL))
+#define bFM3_MFT_PPG_REVC1_REV22               *((volatile unsigned int*)(0x42482898UL))
+#define bFM3_MFT_PPG_REVC1_REV23               *((volatile unsigned int*)(0x4248289CUL))
+#define bFM3_MFT_PPG_PPGC1_TTRG                *((volatile unsigned int*)(0x42484000UL))
+#define bFM3_MFT_PPG_PPGC1_PCS0                *((volatile unsigned int*)(0x4248400CUL))
+#define bFM3_MFT_PPG_PPGC1_PCS1                *((volatile unsigned int*)(0x42484010UL))
+#define bFM3_MFT_PPG_PPGC1_INTM                *((volatile unsigned int*)(0x42484014UL))
+#define bFM3_MFT_PPG_PPGC1_PUF                 *((volatile unsigned int*)(0x42484018UL))
+#define bFM3_MFT_PPG_PPGC1_PIE                 *((volatile unsigned int*)(0x4248401CUL))
+#define bFM3_MFT_PPG_PPGC0_TTRG                *((volatile unsigned int*)(0x42484020UL))
+#define bFM3_MFT_PPG_PPGC0_PCS0                *((volatile unsigned int*)(0x4248402CUL))
+#define bFM3_MFT_PPG_PPGC0_PCS1                *((volatile unsigned int*)(0x42484030UL))
+#define bFM3_MFT_PPG_PPGC0_INTM                *((volatile unsigned int*)(0x42484034UL))
+#define bFM3_MFT_PPG_PPGC0_PUF                 *((volatile unsigned int*)(0x42484038UL))
+#define bFM3_MFT_PPG_PPGC0_PIE                 *((volatile unsigned int*)(0x4248403CUL))
+#define bFM3_MFT_PPG_PPGC3_TTRG                *((volatile unsigned int*)(0x42484080UL))
+#define bFM3_MFT_PPG_PPGC3_PCS0                *((volatile unsigned int*)(0x4248408CUL))
+#define bFM3_MFT_PPG_PPGC3_PCS1                *((volatile unsigned int*)(0x42484090UL))
+#define bFM3_MFT_PPG_PPGC3_INTM                *((volatile unsigned int*)(0x42484094UL))
+#define bFM3_MFT_PPG_PPGC3_PUF                 *((volatile unsigned int*)(0x42484098UL))
+#define bFM3_MFT_PPG_PPGC3_PIE                 *((volatile unsigned int*)(0x4248409CUL))
+#define bFM3_MFT_PPG_PPGC2_TTRG                *((volatile unsigned int*)(0x424840A0UL))
+#define bFM3_MFT_PPG_PPGC2_PCS0                *((volatile unsigned int*)(0x424840ACUL))
+#define bFM3_MFT_PPG_PPGC2_PCS1                *((volatile unsigned int*)(0x424840B0UL))
+#define bFM3_MFT_PPG_PPGC2_INTM                *((volatile unsigned int*)(0x424840B4UL))
+#define bFM3_MFT_PPG_PPGC2_PUF                 *((volatile unsigned int*)(0x424840B8UL))
+#define bFM3_MFT_PPG_PPGC2_PIE                 *((volatile unsigned int*)(0x424840BCUL))
+#define bFM3_MFT_PPG_GATEC0_EDGE0              *((volatile unsigned int*)(0x42484300UL))
+#define bFM3_MFT_PPG_GATEC0_STRG0              *((volatile unsigned int*)(0x42484304UL))
+#define bFM3_MFT_PPG_GATEC0_EDGE2              *((volatile unsigned int*)(0x42484310UL))
+#define bFM3_MFT_PPG_GATEC0_STRG2              *((volatile unsigned int*)(0x42484314UL))
+#define bFM3_MFT_PPG_PPGC5_TTRG                *((volatile unsigned int*)(0x42484800UL))
+#define bFM3_MFT_PPG_PPGC5_PCS0                *((volatile unsigned int*)(0x4248480CUL))
+#define bFM3_MFT_PPG_PPGC5_PCS1                *((volatile unsigned int*)(0x42484810UL))
+#define bFM3_MFT_PPG_PPGC5_INTM                *((volatile unsigned int*)(0x42484814UL))
+#define bFM3_MFT_PPG_PPGC5_PUF                 *((volatile unsigned int*)(0x42484818UL))
+#define bFM3_MFT_PPG_PPGC5_PIE                 *((volatile unsigned int*)(0x4248481CUL))
+#define bFM3_MFT_PPG_PPGC4_TTRG                *((volatile unsigned int*)(0x42484820UL))
+#define bFM3_MFT_PPG_PPGC4_PCS0                *((volatile unsigned int*)(0x4248482CUL))
+#define bFM3_MFT_PPG_PPGC4_PCS1                *((volatile unsigned int*)(0x42484830UL))
+#define bFM3_MFT_PPG_PPGC4_INTM                *((volatile unsigned int*)(0x42484834UL))
+#define bFM3_MFT_PPG_PPGC4_PUF                 *((volatile unsigned int*)(0x42484838UL))
+#define bFM3_MFT_PPG_PPGC4_PIE                 *((volatile unsigned int*)(0x4248483CUL))
+#define bFM3_MFT_PPG_PPGC7_TTRG                *((volatile unsigned int*)(0x42484880UL))
+#define bFM3_MFT_PPG_PPGC7_PCS0                *((volatile unsigned int*)(0x4248488CUL))
+#define bFM3_MFT_PPG_PPGC7_PCS1                *((volatile unsigned int*)(0x42484890UL))
+#define bFM3_MFT_PPG_PPGC7_INTM                *((volatile unsigned int*)(0x42484894UL))
+#define bFM3_MFT_PPG_PPGC7_PUF                 *((volatile unsigned int*)(0x42484898UL))
+#define bFM3_MFT_PPG_PPGC7_PIE                 *((volatile unsigned int*)(0x4248489CUL))
+#define bFM3_MFT_PPG_PPGC6_TTRG                *((volatile unsigned int*)(0x424848A0UL))
+#define bFM3_MFT_PPG_PPGC6_PCS0                *((volatile unsigned int*)(0x424848ACUL))
+#define bFM3_MFT_PPG_PPGC6_PCS1                *((volatile unsigned int*)(0x424848B0UL))
+#define bFM3_MFT_PPG_PPGC6_INTM                *((volatile unsigned int*)(0x424848B4UL))
+#define bFM3_MFT_PPG_PPGC6_PUF                 *((volatile unsigned int*)(0x424848B8UL))
+#define bFM3_MFT_PPG_PPGC6_PIE                 *((volatile unsigned int*)(0x424848BCUL))
+#define bFM3_MFT_PPG_GATEC4_EDGE4              *((volatile unsigned int*)(0x42484B00UL))
+#define bFM3_MFT_PPG_GATEC4_STRG4              *((volatile unsigned int*)(0x42484B04UL))
+#define bFM3_MFT_PPG_GATEC4_EDGE6              *((volatile unsigned int*)(0x42484B10UL))
+#define bFM3_MFT_PPG_GATEC4_STRG6              *((volatile unsigned int*)(0x42484B14UL))
+#define bFM3_MFT_PPG_PPGC9_TTRG                *((volatile unsigned int*)(0x42485000UL))
+#define bFM3_MFT_PPG_PPGC9_PCS0                *((volatile unsigned int*)(0x4248500CUL))
+#define bFM3_MFT_PPG_PPGC9_PCS1                *((volatile unsigned int*)(0x42485010UL))
+#define bFM3_MFT_PPG_PPGC9_INTM                *((volatile unsigned int*)(0x42485014UL))
+#define bFM3_MFT_PPG_PPGC9_PUF                 *((volatile unsigned int*)(0x42485018UL))
+#define bFM3_MFT_PPG_PPGC9_PIE                 *((volatile unsigned int*)(0x4248501CUL))
+#define bFM3_MFT_PPG_PPGC8_TTRG                *((volatile unsigned int*)(0x42485020UL))
+#define bFM3_MFT_PPG_PPGC8_PCS0                *((volatile unsigned int*)(0x4248502CUL))
+#define bFM3_MFT_PPG_PPGC8_PCS1                *((volatile unsigned int*)(0x42485030UL))
+#define bFM3_MFT_PPG_PPGC8_INTM                *((volatile unsigned int*)(0x42485034UL))
+#define bFM3_MFT_PPG_PPGC8_PUF                 *((volatile unsigned int*)(0x42485038UL))
+#define bFM3_MFT_PPG_PPGC8_PIE                 *((volatile unsigned int*)(0x4248503CUL))
+#define bFM3_MFT_PPG_PPGC11_TTRG               *((volatile unsigned int*)(0x42485080UL))
+#define bFM3_MFT_PPG_PPGC11_PCS0               *((volatile unsigned int*)(0x4248508CUL))
+#define bFM3_MFT_PPG_PPGC11_PCS1               *((volatile unsigned int*)(0x42485090UL))
+#define bFM3_MFT_PPG_PPGC11_INTM               *((volatile unsigned int*)(0x42485094UL))
+#define bFM3_MFT_PPG_PPGC11_PUF                *((volatile unsigned int*)(0x42485098UL))
+#define bFM3_MFT_PPG_PPGC11_PIE                *((volatile unsigned int*)(0x4248509CUL))
+#define bFM3_MFT_PPG_PPGC10_TTRG               *((volatile unsigned int*)(0x424850A0UL))
+#define bFM3_MFT_PPG_PPGC10_PCS0               *((volatile unsigned int*)(0x424850ACUL))
+#define bFM3_MFT_PPG_PPGC10_PCS1               *((volatile unsigned int*)(0x424850B0UL))
+#define bFM3_MFT_PPG_PPGC10_INTM               *((volatile unsigned int*)(0x424850B4UL))
+#define bFM3_MFT_PPG_PPGC10_PUF                *((volatile unsigned int*)(0x424850B8UL))
+#define bFM3_MFT_PPG_PPGC10_PIE                *((volatile unsigned int*)(0x424850BCUL))
+#define bFM3_MFT_PPG_GATEC8_EDGE8              *((volatile unsigned int*)(0x42485300UL))
+#define bFM3_MFT_PPG_GATEC8_STRG8              *((volatile unsigned int*)(0x42485304UL))
+#define bFM3_MFT_PPG_GATEC8_EDGE10             *((volatile unsigned int*)(0x42485310UL))
+#define bFM3_MFT_PPG_GATEC8_STRG10             *((volatile unsigned int*)(0x42485314UL))
+#define bFM3_MFT_PPG_PPGC13_TTRG               *((volatile unsigned int*)(0x42485800UL))
+#define bFM3_MFT_PPG_PPGC13_PCS0               *((volatile unsigned int*)(0x4248580CUL))
+#define bFM3_MFT_PPG_PPGC13_PCS1               *((volatile unsigned int*)(0x42485810UL))
+#define bFM3_MFT_PPG_PPGC13_INTM               *((volatile unsigned int*)(0x42485814UL))
+#define bFM3_MFT_PPG_PPGC13_PUF                *((volatile unsigned int*)(0x42485818UL))
+#define bFM3_MFT_PPG_PPGC13_PIE                *((volatile unsigned int*)(0x4248581CUL))
+#define bFM3_MFT_PPG_PPGC12_TTRG               *((volatile unsigned int*)(0x42485820UL))
+#define bFM3_MFT_PPG_PPGC12_PCS0               *((volatile unsigned int*)(0x4248582CUL))
+#define bFM3_MFT_PPG_PPGC12_PCS1               *((volatile unsigned int*)(0x42485830UL))
+#define bFM3_MFT_PPG_PPGC12_INTM               *((volatile unsigned int*)(0x42485834UL))
+#define bFM3_MFT_PPG_PPGC12_PUF                *((volatile unsigned int*)(0x42485838UL))
+#define bFM3_MFT_PPG_PPGC12_PIE                *((volatile unsigned int*)(0x4248583CUL))
+#define bFM3_MFT_PPG_PPGC15_TTRG               *((volatile unsigned int*)(0x42485880UL))
+#define bFM3_MFT_PPG_PPGC15_PCS0               *((volatile unsigned int*)(0x4248588CUL))
+#define bFM3_MFT_PPG_PPGC15_PCS1               *((volatile unsigned int*)(0x42485890UL))
+#define bFM3_MFT_PPG_PPGC15_INTM               *((volatile unsigned int*)(0x42485894UL))
+#define bFM3_MFT_PPG_PPGC15_PUF                *((volatile unsigned int*)(0x42485898UL))
+#define bFM3_MFT_PPG_PPGC15_PIE                *((volatile unsigned int*)(0x4248589CUL))
+#define bFM3_MFT_PPG_PPGC14_TTRG               *((volatile unsigned int*)(0x424858A0UL))
+#define bFM3_MFT_PPG_PPGC14_PCS0               *((volatile unsigned int*)(0x424858ACUL))
+#define bFM3_MFT_PPG_PPGC14_PCS1               *((volatile unsigned int*)(0x424858B0UL))
+#define bFM3_MFT_PPG_PPGC14_INTM               *((volatile unsigned int*)(0x424858B4UL))
+#define bFM3_MFT_PPG_PPGC14_PUF                *((volatile unsigned int*)(0x424858B8UL))
+#define bFM3_MFT_PPG_PPGC14_PIE                *((volatile unsigned int*)(0x424858BCUL))
+#define bFM3_MFT_PPG_GATEC12_EDGE12            *((volatile unsigned int*)(0x42485B00UL))
+#define bFM3_MFT_PPG_GATEC12_STRG12            *((volatile unsigned int*)(0x42485B04UL))
+#define bFM3_MFT_PPG_GATEC12_EDGE14            *((volatile unsigned int*)(0x42485B10UL))
+#define bFM3_MFT_PPG_GATEC12_STRG14            *((volatile unsigned int*)(0x42485B14UL))
+#define bFM3_MFT_PPG_PPGC17_TTRG               *((volatile unsigned int*)(0x42486000UL))
+#define bFM3_MFT_PPG_PPGC17_PCS0               *((volatile unsigned int*)(0x4248600CUL))
+#define bFM3_MFT_PPG_PPGC17_PCS1               *((volatile unsigned int*)(0x42486010UL))
+#define bFM3_MFT_PPG_PPGC17_INTM               *((volatile unsigned int*)(0x42486014UL))
+#define bFM3_MFT_PPG_PPGC17_PUF                *((volatile unsigned int*)(0x42486018UL))
+#define bFM3_MFT_PPG_PPGC17_PIE                *((volatile unsigned int*)(0x4248601CUL))
+#define bFM3_MFT_PPG_PPGC16_TTRG               *((volatile unsigned int*)(0x42486020UL))
+#define bFM3_MFT_PPG_PPGC16_PCS0               *((volatile unsigned int*)(0x4248602CUL))
+#define bFM3_MFT_PPG_PPGC16_PCS1               *((volatile unsigned int*)(0x42486030UL))
+#define bFM3_MFT_PPG_PPGC16_INTM               *((volatile unsigned int*)(0x42486034UL))
+#define bFM3_MFT_PPG_PPGC16_PUF                *((volatile unsigned int*)(0x42486038UL))
+#define bFM3_MFT_PPG_PPGC16_PIE                *((volatile unsigned int*)(0x4248603CUL))
+#define bFM3_MFT_PPG_PPGC19_TTRG               *((volatile unsigned int*)(0x42486080UL))
+#define bFM3_MFT_PPG_PPGC19_PCS0               *((volatile unsigned int*)(0x4248608CUL))
+#define bFM3_MFT_PPG_PPGC19_PCS1               *((volatile unsigned int*)(0x42486090UL))
+#define bFM3_MFT_PPG_PPGC19_INTM               *((volatile unsigned int*)(0x42486094UL))
+#define bFM3_MFT_PPG_PPGC19_PUF                *((volatile unsigned int*)(0x42486098UL))
+#define bFM3_MFT_PPG_PPGC19_PIE                *((volatile unsigned int*)(0x4248609CUL))
+#define bFM3_MFT_PPG_PPGC18_TTRG               *((volatile unsigned int*)(0x424860A0UL))
+#define bFM3_MFT_PPG_PPGC18_PCS0               *((volatile unsigned int*)(0x424860ACUL))
+#define bFM3_MFT_PPG_PPGC18_PCS1               *((volatile unsigned int*)(0x424860B0UL))
+#define bFM3_MFT_PPG_PPGC18_INTM               *((volatile unsigned int*)(0x424860B4UL))
+#define bFM3_MFT_PPG_PPGC18_PUF                *((volatile unsigned int*)(0x424860B8UL))
+#define bFM3_MFT_PPG_PPGC18_PIE                *((volatile unsigned int*)(0x424860BCUL))
+#define bFM3_MFT_PPG_GATEC16_EDGE16            *((volatile unsigned int*)(0x42486300UL))
+#define bFM3_MFT_PPG_GATEC16_STRG16            *((volatile unsigned int*)(0x42486304UL))
+#define bFM3_MFT_PPG_GATEC16_EDGE18            *((volatile unsigned int*)(0x42486310UL))
+#define bFM3_MFT_PPG_GATEC16_STRG18            *((volatile unsigned int*)(0x42486314UL))
+#define bFM3_MFT_PPG_PPGC21_TTRG               *((volatile unsigned int*)(0x42486800UL))
+#define bFM3_MFT_PPG_PPGC21_PCS0               *((volatile unsigned int*)(0x4248680CUL))
+#define bFM3_MFT_PPG_PPGC21_PCS1               *((volatile unsigned int*)(0x42486810UL))
+#define bFM3_MFT_PPG_PPGC21_INTM               *((volatile unsigned int*)(0x42486814UL))
+#define bFM3_MFT_PPG_PPGC21_PUF                *((volatile unsigned int*)(0x42486818UL))
+#define bFM3_MFT_PPG_PPGC21_PIE                *((volatile unsigned int*)(0x4248681CUL))
+#define bFM3_MFT_PPG_PPGC20_TTRG               *((volatile unsigned int*)(0x42486820UL))
+#define bFM3_MFT_PPG_PPGC20_PCS0               *((volatile unsigned int*)(0x4248682CUL))
+#define bFM3_MFT_PPG_PPGC20_PCS1               *((volatile unsigned int*)(0x42486830UL))
+#define bFM3_MFT_PPG_PPGC20_INTM               *((volatile unsigned int*)(0x42486834UL))
+#define bFM3_MFT_PPG_PPGC20_PUF                *((volatile unsigned int*)(0x42486838UL))
+#define bFM3_MFT_PPG_PPGC20_PIE                *((volatile unsigned int*)(0x4248683CUL))
+#define bFM3_MFT_PPG_PPGC23_TTRG               *((volatile unsigned int*)(0x42486880UL))
+#define bFM3_MFT_PPG_PPGC23_PCS0               *((volatile unsigned int*)(0x4248688CUL))
+#define bFM3_MFT_PPG_PPGC23_PCS1               *((volatile unsigned int*)(0x42486890UL))
+#define bFM3_MFT_PPG_PPGC23_INTM               *((volatile unsigned int*)(0x42486894UL))
+#define bFM3_MFT_PPG_PPGC23_PUF                *((volatile unsigned int*)(0x42486898UL))
+#define bFM3_MFT_PPG_PPGC23_PIE                *((volatile unsigned int*)(0x4248689CUL))
+#define bFM3_MFT_PPG_PPGC22_TTRG               *((volatile unsigned int*)(0x424868A0UL))
+#define bFM3_MFT_PPG_PPGC22_PCS0               *((volatile unsigned int*)(0x424868ACUL))
+#define bFM3_MFT_PPG_PPGC22_PCS1               *((volatile unsigned int*)(0x424868B0UL))
+#define bFM3_MFT_PPG_PPGC22_INTM               *((volatile unsigned int*)(0x424868B4UL))
+#define bFM3_MFT_PPG_PPGC22_PUF                *((volatile unsigned int*)(0x424868B8UL))
+#define bFM3_MFT_PPG_PPGC22_PIE                *((volatile unsigned int*)(0x424868BCUL))
+#define bFM3_MFT_PPG_GATEC20_EDGE20            *((volatile unsigned int*)(0x42486B00UL))
+#define bFM3_MFT_PPG_GATEC20_STRG20            *((volatile unsigned int*)(0x42486B04UL))
+#define bFM3_MFT_PPG_GATEC20_EDGE22            *((volatile unsigned int*)(0x42486B10UL))
+#define bFM3_MFT_PPG_GATEC20_STRG22            *((volatile unsigned int*)(0x42486B14UL))
+
+/* Base Timer 0 PPG registers */
+#define bFM3_BT0_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWM registers */
+#define bFM3_BT0_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A01ACUL))
+#define bFM3_BT0_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0204UL))
+#define bFM3_BT0_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0214UL))
+#define bFM3_BT0_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 RT registers */
+#define bFM3_BT0_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0180UL))
+#define bFM3_BT0_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A018CUL))
+#define bFM3_BT0_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 0 PWC registers */
+#define bFM3_BT0_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0184UL))
+#define bFM3_BT0_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0188UL))
+#define bFM3_BT0_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A019CUL))
+#define bFM3_BT0_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A01A0UL))
+#define bFM3_BT0_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A01A4UL))
+#define bFM3_BT0_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A01A8UL))
+#define bFM3_BT0_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A01B0UL))
+#define bFM3_BT0_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A01B4UL))
+#define bFM3_BT0_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A01B8UL))
+#define bFM3_BT0_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0200UL))
+#define bFM3_BT0_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0208UL))
+#define bFM3_BT0_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0210UL))
+#define bFM3_BT0_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0218UL))
+#define bFM3_BT0_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A021CUL))
+#define bFM3_BT0_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0220UL))
+
+/* Base Timer 1 PPG registers */
+#define bFM3_BT1_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWM registers */
+#define bFM3_BT1_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A09ACUL))
+#define bFM3_BT1_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A0A04UL))
+#define bFM3_BT1_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A0A14UL))
+#define bFM3_BT1_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 RT registers */
+#define bFM3_BT1_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A0980UL))
+#define bFM3_BT1_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A098CUL))
+#define bFM3_BT1_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 1 PWC registers */
+#define bFM3_BT1_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A0984UL))
+#define bFM3_BT1_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A0988UL))
+#define bFM3_BT1_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A099CUL))
+#define bFM3_BT1_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A09A0UL))
+#define bFM3_BT1_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A09A4UL))
+#define bFM3_BT1_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A09A8UL))
+#define bFM3_BT1_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A09B0UL))
+#define bFM3_BT1_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A09B4UL))
+#define bFM3_BT1_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A09B8UL))
+#define bFM3_BT1_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A0A00UL))
+#define bFM3_BT1_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A0A08UL))
+#define bFM3_BT1_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A0A10UL))
+#define bFM3_BT1_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A0A18UL))
+#define bFM3_BT1_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A0A1CUL))
+#define bFM3_BT1_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A0A20UL))
+
+/* Base Timer 2 PPG registers */
+#define bFM3_BT2_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWM registers */
+#define bFM3_BT2_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A11ACUL))
+#define bFM3_BT2_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1204UL))
+#define bFM3_BT2_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1214UL))
+#define bFM3_BT2_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 RT registers */
+#define bFM3_BT2_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1180UL))
+#define bFM3_BT2_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A118CUL))
+#define bFM3_BT2_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 2 PWC registers */
+#define bFM3_BT2_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1184UL))
+#define bFM3_BT2_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1188UL))
+#define bFM3_BT2_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A119CUL))
+#define bFM3_BT2_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A11A0UL))
+#define bFM3_BT2_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A11A4UL))
+#define bFM3_BT2_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A11A8UL))
+#define bFM3_BT2_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A11B0UL))
+#define bFM3_BT2_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A11B4UL))
+#define bFM3_BT2_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A11B8UL))
+#define bFM3_BT2_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1200UL))
+#define bFM3_BT2_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1208UL))
+#define bFM3_BT2_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1210UL))
+#define bFM3_BT2_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1218UL))
+#define bFM3_BT2_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A121CUL))
+#define bFM3_BT2_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1220UL))
+
+/* Base Timer 3 PPG registers */
+#define bFM3_BT3_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWM registers */
+#define bFM3_BT3_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A19ACUL))
+#define bFM3_BT3_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A1A04UL))
+#define bFM3_BT3_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A1A14UL))
+#define bFM3_BT3_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 RT registers */
+#define bFM3_BT3_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A1980UL))
+#define bFM3_BT3_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A198CUL))
+#define bFM3_BT3_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 3 PWC registers */
+#define bFM3_BT3_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A1984UL))
+#define bFM3_BT3_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A1988UL))
+#define bFM3_BT3_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A199CUL))
+#define bFM3_BT3_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A19A0UL))
+#define bFM3_BT3_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A19A4UL))
+#define bFM3_BT3_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A19A8UL))
+#define bFM3_BT3_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A19B0UL))
+#define bFM3_BT3_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A19B4UL))
+#define bFM3_BT3_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A19B8UL))
+#define bFM3_BT3_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A1A00UL))
+#define bFM3_BT3_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A1A08UL))
+#define bFM3_BT3_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A1A10UL))
+#define bFM3_BT3_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A1A18UL))
+#define bFM3_BT3_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A1A1CUL))
+#define bFM3_BT3_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A1A20UL))
+
+/* Base Timer 4 PPG registers */
+#define bFM3_BT4_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWM registers */
+#define bFM3_BT4_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A41ACUL))
+#define bFM3_BT4_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4204UL))
+#define bFM3_BT4_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4214UL))
+#define bFM3_BT4_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 RT registers */
+#define bFM3_BT4_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4180UL))
+#define bFM3_BT4_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A418CUL))
+#define bFM3_BT4_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 4 PWC registers */
+#define bFM3_BT4_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4184UL))
+#define bFM3_BT4_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4188UL))
+#define bFM3_BT4_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A419CUL))
+#define bFM3_BT4_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A41A0UL))
+#define bFM3_BT4_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A41A4UL))
+#define bFM3_BT4_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A41A8UL))
+#define bFM3_BT4_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A41B0UL))
+#define bFM3_BT4_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A41B4UL))
+#define bFM3_BT4_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A41B8UL))
+#define bFM3_BT4_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4200UL))
+#define bFM3_BT4_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4208UL))
+#define bFM3_BT4_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4210UL))
+#define bFM3_BT4_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4218UL))
+#define bFM3_BT4_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A421CUL))
+#define bFM3_BT4_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4220UL))
+
+/* Base Timer 5 PPG registers */
+#define bFM3_BT5_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWM registers */
+#define bFM3_BT5_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A49ACUL))
+#define bFM3_BT5_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A4A04UL))
+#define bFM3_BT5_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A4A14UL))
+#define bFM3_BT5_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 RT registers */
+#define bFM3_BT5_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A4980UL))
+#define bFM3_BT5_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A498CUL))
+#define bFM3_BT5_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 5 PWC registers */
+#define bFM3_BT5_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A4984UL))
+#define bFM3_BT5_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A4988UL))
+#define bFM3_BT5_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A499CUL))
+#define bFM3_BT5_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A49A0UL))
+#define bFM3_BT5_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A49A4UL))
+#define bFM3_BT5_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A49A8UL))
+#define bFM3_BT5_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A49B0UL))
+#define bFM3_BT5_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A49B4UL))
+#define bFM3_BT5_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A49B8UL))
+#define bFM3_BT5_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A4A00UL))
+#define bFM3_BT5_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A4A08UL))
+#define bFM3_BT5_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A4A10UL))
+#define bFM3_BT5_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A4A18UL))
+#define bFM3_BT5_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A4A1CUL))
+#define bFM3_BT5_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A4A20UL))
+
+/* Base Timer 6 PPG registers */
+#define bFM3_BT6_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWM registers */
+#define bFM3_BT6_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A51ACUL))
+#define bFM3_BT6_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5204UL))
+#define bFM3_BT6_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5214UL))
+#define bFM3_BT6_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 RT registers */
+#define bFM3_BT6_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5180UL))
+#define bFM3_BT6_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A518CUL))
+#define bFM3_BT6_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 6 PWC registers */
+#define bFM3_BT6_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5184UL))
+#define bFM3_BT6_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5188UL))
+#define bFM3_BT6_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A519CUL))
+#define bFM3_BT6_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A51A0UL))
+#define bFM3_BT6_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A51A4UL))
+#define bFM3_BT6_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A51A8UL))
+#define bFM3_BT6_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A51B0UL))
+#define bFM3_BT6_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A51B4UL))
+#define bFM3_BT6_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A51B8UL))
+#define bFM3_BT6_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5200UL))
+#define bFM3_BT6_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5208UL))
+#define bFM3_BT6_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5210UL))
+#define bFM3_BT6_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5218UL))
+#define bFM3_BT6_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A521CUL))
+#define bFM3_BT6_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5220UL))
+
+/* Base Timer 7 PPG registers */
+#define bFM3_BT7_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWM registers */
+#define bFM3_BT7_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A59ACUL))
+#define bFM3_BT7_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A5A04UL))
+#define bFM3_BT7_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A5A14UL))
+#define bFM3_BT7_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 RT registers */
+#define bFM3_BT7_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A5980UL))
+#define bFM3_BT7_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A598CUL))
+#define bFM3_BT7_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer 7 PWC registers */
+#define bFM3_BT7_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A5984UL))
+#define bFM3_BT7_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A5988UL))
+#define bFM3_BT7_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A599CUL))
+#define bFM3_BT7_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A59A0UL))
+#define bFM3_BT7_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A59A4UL))
+#define bFM3_BT7_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A59A8UL))
+#define bFM3_BT7_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A59B0UL))
+#define bFM3_BT7_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A59B4UL))
+#define bFM3_BT7_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A59B8UL))
+#define bFM3_BT7_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A5A00UL))
+#define bFM3_BT7_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A5A08UL))
+#define bFM3_BT7_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A5A10UL))
+#define bFM3_BT7_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A5A18UL))
+#define bFM3_BT7_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A5A1CUL))
+#define bFM3_BT7_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A5A20UL))
+
+/* Base Timer I/O selector channel 0 - channel 3 registers */
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0       *((volatile unsigned int*)(0x424A2020UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1       *((volatile unsigned int*)(0x424A2024UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2       *((volatile unsigned int*)(0x424A2028UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3       *((volatile unsigned int*)(0x424A202CUL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0       *((volatile unsigned int*)(0x424A2030UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1       *((volatile unsigned int*)(0x424A2034UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2       *((volatile unsigned int*)(0x424A2038UL))
+#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3       *((volatile unsigned int*)(0x424A203CUL))
+
+/* Base Timer I/O selector channel 4 - channel 7 registers */
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0       *((volatile unsigned int*)(0x424A6020UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1       *((volatile unsigned int*)(0x424A6024UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2       *((volatile unsigned int*)(0x424A6028UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3       *((volatile unsigned int*)(0x424A602CUL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0       *((volatile unsigned int*)(0x424A6030UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1       *((volatile unsigned int*)(0x424A6034UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2       *((volatile unsigned int*)(0x424A6038UL))
+#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3       *((volatile unsigned int*)(0x424A603CUL))
+
+/* Base Timer 8 PPG registers */
+#define bFM3_BT8_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWM registers */
+#define bFM3_BT8_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A81ACUL))
+#define bFM3_BT8_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8204UL))
+#define bFM3_BT8_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8214UL))
+#define bFM3_BT8_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 RT registers */
+#define bFM3_BT8_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8180UL))
+#define bFM3_BT8_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A818CUL))
+#define bFM3_BT8_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 8 PWC registers */
+#define bFM3_BT8_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8184UL))
+#define bFM3_BT8_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8188UL))
+#define bFM3_BT8_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A819CUL))
+#define bFM3_BT8_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A81A0UL))
+#define bFM3_BT8_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A81A4UL))
+#define bFM3_BT8_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A81A8UL))
+#define bFM3_BT8_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A81B0UL))
+#define bFM3_BT8_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A81B4UL))
+#define bFM3_BT8_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A81B8UL))
+#define bFM3_BT8_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8200UL))
+#define bFM3_BT8_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8208UL))
+#define bFM3_BT8_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8210UL))
+#define bFM3_BT8_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8218UL))
+#define bFM3_BT8_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A821CUL))
+#define bFM3_BT8_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8220UL))
+
+/* Base Timer 9 PPG registers */
+#define bFM3_BT9_PPG_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PPG_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PPG_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PPG_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PPG_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PPG_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PPG_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PPG_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PPG_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PPG_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PPG_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PPG_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PPG_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PPG_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PPG_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PPG_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWM registers */
+#define bFM3_BT9_PWM_TMCR_STRG                 *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_PWM_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWM_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWM_TMCR_OSEL                 *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_PWM_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWM_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWM_TMCR_PMSK                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWM_TMCR_RTGEN                *((volatile unsigned int*)(0x424A89ACUL))
+#define bFM3_BT9_PWM_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWM_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWM_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWM_STC_UDIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWM_STC_DTIR                  *((volatile unsigned int*)(0x424A8A04UL))
+#define bFM3_BT9_PWM_STC_TGIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWM_STC_UDIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWM_STC_DTIE                  *((volatile unsigned int*)(0x424A8A14UL))
+#define bFM3_BT9_PWM_STC_TGIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWM_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 RT registers */
+#define bFM3_BT9_RT_TMCR_STRG                  *((volatile unsigned int*)(0x424A8980UL))
+#define bFM3_BT9_RT_TMCR_CTEN                  *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_RT_TMCR_MDSE                  *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_RT_TMCR_OSEL                  *((volatile unsigned int*)(0x424A898CUL))
+#define bFM3_BT9_RT_TMCR_T32                   *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_RT_TMCR_EGS0                  *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_RT_TMCR_EGS1                  *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_RT_TMCR_CKS0                  *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_RT_TMCR_CKS1                  *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_RT_TMCR_CKS2                  *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_RT_STC_UDIR                   *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_RT_STC_TGIR                   *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_RT_STC_UDIE                   *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_RT_STC_TGIE                   *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_RT_TMCR2_CKS3                 *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 9 PWC registers */
+#define bFM3_BT9_PWC_TMCR_CTEN                 *((volatile unsigned int*)(0x424A8984UL))
+#define bFM3_BT9_PWC_TMCR_MDSE                 *((volatile unsigned int*)(0x424A8988UL))
+#define bFM3_BT9_PWC_TMCR_T32                  *((volatile unsigned int*)(0x424A899CUL))
+#define bFM3_BT9_PWC_TMCR_EGS0                 *((volatile unsigned int*)(0x424A89A0UL))
+#define bFM3_BT9_PWC_TMCR_EGS1                 *((volatile unsigned int*)(0x424A89A4UL))
+#define bFM3_BT9_PWC_TMCR_EGS2                 *((volatile unsigned int*)(0x424A89A8UL))
+#define bFM3_BT9_PWC_TMCR_CKS0                 *((volatile unsigned int*)(0x424A89B0UL))
+#define bFM3_BT9_PWC_TMCR_CKS1                 *((volatile unsigned int*)(0x424A89B4UL))
+#define bFM3_BT9_PWC_TMCR_CKS2                 *((volatile unsigned int*)(0x424A89B8UL))
+#define bFM3_BT9_PWC_STC_OVIR                  *((volatile unsigned int*)(0x424A8A00UL))
+#define bFM3_BT9_PWC_STC_EDIR                  *((volatile unsigned int*)(0x424A8A08UL))
+#define bFM3_BT9_PWC_STC_OVIE                  *((volatile unsigned int*)(0x424A8A10UL))
+#define bFM3_BT9_PWC_STC_EDIE                  *((volatile unsigned int*)(0x424A8A18UL))
+#define bFM3_BT9_PWC_STC_ERR                   *((volatile unsigned int*)(0x424A8A1CUL))
+#define bFM3_BT9_PWC_TMCR2_CKS3                *((volatile unsigned int*)(0x424A8A20UL))
+
+/* Base Timer 10 PPG registers */
+#define bFM3_BT10_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWM registers */
+#define bFM3_BT10_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A91ACUL))
+#define bFM3_BT10_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9204UL))
+#define bFM3_BT10_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9214UL))
+#define bFM3_BT10_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 RT registers */
+#define bFM3_BT10_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9180UL))
+#define bFM3_BT10_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A918CUL))
+#define bFM3_BT10_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 10 PWC registers */
+#define bFM3_BT10_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9184UL))
+#define bFM3_BT10_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9188UL))
+#define bFM3_BT10_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A919CUL))
+#define bFM3_BT10_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A91A0UL))
+#define bFM3_BT10_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A91A4UL))
+#define bFM3_BT10_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A91A8UL))
+#define bFM3_BT10_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A91B0UL))
+#define bFM3_BT10_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A91B4UL))
+#define bFM3_BT10_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A91B8UL))
+#define bFM3_BT10_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9200UL))
+#define bFM3_BT10_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9208UL))
+#define bFM3_BT10_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9210UL))
+#define bFM3_BT10_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9218UL))
+#define bFM3_BT10_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A921CUL))
+#define bFM3_BT10_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9220UL))
+
+/* Base Timer 11 PPG registers */
+#define bFM3_BT11_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWM registers */
+#define bFM3_BT11_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424A99ACUL))
+#define bFM3_BT11_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424A9A04UL))
+#define bFM3_BT11_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424A9A14UL))
+#define bFM3_BT11_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 RT registers */
+#define bFM3_BT11_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424A9980UL))
+#define bFM3_BT11_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424A998CUL))
+#define bFM3_BT11_RT_TMCR_T32                  *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_RT_STC_UDIR                  *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_RT_STC_TGIR                  *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_RT_STC_UDIE                  *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_RT_STC_TGIE                  *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 11 PWC registers */
+#define bFM3_BT11_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424A9984UL))
+#define bFM3_BT11_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424A9988UL))
+#define bFM3_BT11_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424A999CUL))
+#define bFM3_BT11_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424A99A0UL))
+#define bFM3_BT11_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424A99A4UL))
+#define bFM3_BT11_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424A99A8UL))
+#define bFM3_BT11_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424A99B0UL))
+#define bFM3_BT11_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424A99B4UL))
+#define bFM3_BT11_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424A99B8UL))
+#define bFM3_BT11_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424A9A00UL))
+#define bFM3_BT11_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424A9A08UL))
+#define bFM3_BT11_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424A9A10UL))
+#define bFM3_BT11_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424A9A18UL))
+#define bFM3_BT11_PWC_STC_ERR                  *((volatile unsigned int*)(0x424A9A1CUL))
+#define bFM3_BT11_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424A9A20UL))
+
+/* Base Timer 12 PPG registers */
+#define bFM3_BT12_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWM registers */
+#define bFM3_BT12_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC1ACUL))
+#define bFM3_BT12_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AC204UL))
+#define bFM3_BT12_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AC214UL))
+#define bFM3_BT12_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 RT registers */
+#define bFM3_BT12_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC180UL))
+#define bFM3_BT12_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC18CUL))
+#define bFM3_BT12_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 12 PWC registers */
+#define bFM3_BT12_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC184UL))
+#define bFM3_BT12_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC188UL))
+#define bFM3_BT12_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC19CUL))
+#define bFM3_BT12_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC1A0UL))
+#define bFM3_BT12_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC1A4UL))
+#define bFM3_BT12_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC1A8UL))
+#define bFM3_BT12_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC1B0UL))
+#define bFM3_BT12_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC1B4UL))
+#define bFM3_BT12_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC1B8UL))
+#define bFM3_BT12_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AC200UL))
+#define bFM3_BT12_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AC208UL))
+#define bFM3_BT12_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AC210UL))
+#define bFM3_BT12_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AC218UL))
+#define bFM3_BT12_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AC21CUL))
+#define bFM3_BT12_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AC220UL))
+
+/* Base Timer 13 PPG registers */
+#define bFM3_BT13_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWM registers */
+#define bFM3_BT13_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AC9ACUL))
+#define bFM3_BT13_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ACA04UL))
+#define bFM3_BT13_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ACA14UL))
+#define bFM3_BT13_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 RT registers */
+#define bFM3_BT13_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AC980UL))
+#define bFM3_BT13_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AC98CUL))
+#define bFM3_BT13_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 13 PWC registers */
+#define bFM3_BT13_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AC984UL))
+#define bFM3_BT13_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AC988UL))
+#define bFM3_BT13_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AC99CUL))
+#define bFM3_BT13_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AC9A0UL))
+#define bFM3_BT13_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AC9A4UL))
+#define bFM3_BT13_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AC9A8UL))
+#define bFM3_BT13_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AC9B0UL))
+#define bFM3_BT13_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AC9B4UL))
+#define bFM3_BT13_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AC9B8UL))
+#define bFM3_BT13_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ACA00UL))
+#define bFM3_BT13_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ACA08UL))
+#define bFM3_BT13_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ACA10UL))
+#define bFM3_BT13_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ACA18UL))
+#define bFM3_BT13_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ACA1CUL))
+#define bFM3_BT13_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ACA20UL))
+
+/* Base Timer 14 PPG registers */
+#define bFM3_BT14_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWM registers */
+#define bFM3_BT14_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD1ACUL))
+#define bFM3_BT14_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424AD204UL))
+#define bFM3_BT14_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424AD214UL))
+#define bFM3_BT14_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 RT registers */
+#define bFM3_BT14_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD180UL))
+#define bFM3_BT14_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD18CUL))
+#define bFM3_BT14_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_RT_STC_UDIR                  *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_RT_STC_TGIR                  *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_RT_STC_UDIE                  *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_RT_STC_TGIE                  *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 14 PWC registers */
+#define bFM3_BT14_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD184UL))
+#define bFM3_BT14_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD188UL))
+#define bFM3_BT14_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD19CUL))
+#define bFM3_BT14_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD1A0UL))
+#define bFM3_BT14_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD1A4UL))
+#define bFM3_BT14_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD1A8UL))
+#define bFM3_BT14_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD1B0UL))
+#define bFM3_BT14_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD1B4UL))
+#define bFM3_BT14_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD1B8UL))
+#define bFM3_BT14_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424AD200UL))
+#define bFM3_BT14_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424AD208UL))
+#define bFM3_BT14_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424AD210UL))
+#define bFM3_BT14_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424AD218UL))
+#define bFM3_BT14_PWC_STC_ERR                  *((volatile unsigned int*)(0x424AD21CUL))
+#define bFM3_BT14_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424AD220UL))
+
+/* Base Timer 15 PPG registers */
+#define bFM3_BT15_PPG_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PPG_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PPG_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PPG_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PPG_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PPG_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PPG_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PPG_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PPG_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PPG_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PPG_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PPG_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PPG_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PPG_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PPG_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PPG_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWM registers */
+#define bFM3_BT15_PWM_TMCR_STRG                *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_PWM_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWM_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWM_TMCR_OSEL                *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_PWM_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWM_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWM_TMCR_PMSK                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWM_TMCR_RTGEN               *((volatile unsigned int*)(0x424AD9ACUL))
+#define bFM3_BT15_PWM_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWM_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWM_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWM_STC_UDIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWM_STC_DTIR                 *((volatile unsigned int*)(0x424ADA04UL))
+#define bFM3_BT15_PWM_STC_TGIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWM_STC_UDIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWM_STC_DTIE                 *((volatile unsigned int*)(0x424ADA14UL))
+#define bFM3_BT15_PWM_STC_TGIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWM_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 RT registers */
+#define bFM3_BT15_RT_TMCR_STRG                 *((volatile unsigned int*)(0x424AD980UL))
+#define bFM3_BT15_RT_TMCR_CTEN                 *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_RT_TMCR_MDSE                 *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_RT_TMCR_OSEL                 *((volatile unsigned int*)(0x424AD98CUL))
+#define bFM3_BT15_RT_TMCR_T32                  *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_RT_TMCR_EGS0                 *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_RT_TMCR_EGS1                 *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_RT_TMCR_CKS0                 *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_RT_TMCR_CKS1                 *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_RT_TMCR_CKS2                 *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_RT_STC_UDIR                  *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_RT_STC_TGIR                  *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_RT_STC_UDIE                  *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_RT_STC_TGIE                  *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_RT_TMCR2_CKS3                *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer 15 PWC registers */
+#define bFM3_BT15_PWC_TMCR_CTEN                *((volatile unsigned int*)(0x424AD984UL))
+#define bFM3_BT15_PWC_TMCR_MDSE                *((volatile unsigned int*)(0x424AD988UL))
+#define bFM3_BT15_PWC_TMCR_T32                 *((volatile unsigned int*)(0x424AD99CUL))
+#define bFM3_BT15_PWC_TMCR_EGS0                *((volatile unsigned int*)(0x424AD9A0UL))
+#define bFM3_BT15_PWC_TMCR_EGS1                *((volatile unsigned int*)(0x424AD9A4UL))
+#define bFM3_BT15_PWC_TMCR_EGS2                *((volatile unsigned int*)(0x424AD9A8UL))
+#define bFM3_BT15_PWC_TMCR_CKS0                *((volatile unsigned int*)(0x424AD9B0UL))
+#define bFM3_BT15_PWC_TMCR_CKS1                *((volatile unsigned int*)(0x424AD9B4UL))
+#define bFM3_BT15_PWC_TMCR_CKS2                *((volatile unsigned int*)(0x424AD9B8UL))
+#define bFM3_BT15_PWC_STC_OVIR                 *((volatile unsigned int*)(0x424ADA00UL))
+#define bFM3_BT15_PWC_STC_EDIR                 *((volatile unsigned int*)(0x424ADA08UL))
+#define bFM3_BT15_PWC_STC_OVIE                 *((volatile unsigned int*)(0x424ADA10UL))
+#define bFM3_BT15_PWC_STC_EDIE                 *((volatile unsigned int*)(0x424ADA18UL))
+#define bFM3_BT15_PWC_STC_ERR                  *((volatile unsigned int*)(0x424ADA1CUL))
+#define bFM3_BT15_PWC_TMCR2_CKS3               *((volatile unsigned int*)(0x424ADA20UL))
+
+/* Base Timer I/O selector channel 8 - channel 11 registers */
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_0       *((volatile unsigned int*)(0x424AA020UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_1       *((volatile unsigned int*)(0x424AA024UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_2       *((volatile unsigned int*)(0x424AA028UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SEL89_3       *((volatile unsigned int*)(0x424AA02CUL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_0       *((volatile unsigned int*)(0x424AA030UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_1       *((volatile unsigned int*)(0x424AA034UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_2       *((volatile unsigned int*)(0x424AA038UL))
+#define bFM3_BTIOSEL8B_BTSEL89AB_SELAB_3       *((volatile unsigned int*)(0x424AA03CUL))
+
+/* Base Timer I/O selector channel 12 - channel 15 registers */
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_0       *((volatile unsigned int*)(0x424AE020UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_1       *((volatile unsigned int*)(0x424AE024UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_2       *((volatile unsigned int*)(0x424AE028UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELCD_3       *((volatile unsigned int*)(0x424AE02CUL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_0       *((volatile unsigned int*)(0x424AE030UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_1       *((volatile unsigned int*)(0x424AE034UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_2       *((volatile unsigned int*)(0x424AE038UL))
+#define bFM3_BTIOSELCF_BTSELCDEF_SELEF_3       *((volatile unsigned int*)(0x424AE03CUL))
+
+/* Software based Simulation Startup (Base Timer) register */
+#define bFM3_SBSSR_BTSSSR_SSR0                 *((volatile unsigned int*)(0x424BFF80UL))
+#define bFM3_SBSSR_BTSSSR_SSR1                 *((volatile unsigned int*)(0x424BFF84UL))
+#define bFM3_SBSSR_BTSSSR_SSR2                 *((volatile unsigned int*)(0x424BFF88UL))
+#define bFM3_SBSSR_BTSSSR_SSR3                 *((volatile unsigned int*)(0x424BFF8CUL))
+#define bFM3_SBSSR_BTSSSR_SSR4                 *((volatile unsigned int*)(0x424BFF90UL))
+#define bFM3_SBSSR_BTSSSR_SSR5                 *((volatile unsigned int*)(0x424BFF94UL))
+#define bFM3_SBSSR_BTSSSR_SSR6                 *((volatile unsigned int*)(0x424BFF98UL))
+#define bFM3_SBSSR_BTSSSR_SSR7                 *((volatile unsigned int*)(0x424BFF9CUL))
+#define bFM3_SBSSR_BTSSSR_SSR8                 *((volatile unsigned int*)(0x424BFFA0UL))
+#define bFM3_SBSSR_BTSSSR_SSR9                 *((volatile unsigned int*)(0x424BFFA4UL))
+#define bFM3_SBSSR_BTSSSR_SSR10                *((volatile unsigned int*)(0x424BFFA8UL))
+#define bFM3_SBSSR_BTSSSR_SSR11                *((volatile unsigned int*)(0x424BFFACUL))
+#define bFM3_SBSSR_BTSSSR_SSR12                *((volatile unsigned int*)(0x424BFFB0UL))
+#define bFM3_SBSSR_BTSSSR_SSR13                *((volatile unsigned int*)(0x424BFFB4UL))
+#define bFM3_SBSSR_BTSSSR_SSR14                *((volatile unsigned int*)(0x424BFFB8UL))
+#define bFM3_SBSSR_BTSSSR_SSR15                *((volatile unsigned int*)(0x424BFFBCUL))
+
+/* Quad position and revolution counter channel 0 registers */
+#define bFM3_QPRC0_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICR_UFDF                   *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICR_OFDF                   *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICR_ZIIF                   *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICR_CDCIE                  *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICR_CDCF                   *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICR_DIRPC                  *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICR_DIROU                  *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0280UL))
+#define bFM3_QPRC0_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0284UL))
+#define bFM3_QPRC0_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0288UL))
+#define bFM3_QPRC0_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C028CUL))
+#define bFM3_QPRC0_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0290UL))
+#define bFM3_QPRC0_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0294UL))
+#define bFM3_QPRC0_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0298UL))
+#define bFM3_QPRC0_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C029CUL))
+#define bFM3_QPRC0_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C02A0UL))
+#define bFM3_QPRC0_QICRH_CDCF                  *((volatile unsigned int*)(0x424C02A4UL))
+#define bFM3_QPRC0_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C02A8UL))
+#define bFM3_QPRC0_QICRH_DIROU                 *((volatile unsigned int*)(0x424C02ACUL))
+#define bFM3_QPRC0_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C02B0UL))
+#define bFM3_QPRC0_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C02B4UL))
+#define bFM3_QPRC0_QCR_PCM0                    *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCR_PCM1                    *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCR_RCM0                    *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCR_RCM1                    *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCR_PSTP                    *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCR_CGSC                    *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCR_RSEL                    *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCR_SWAP                    *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCR_AES0                    *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCR_AES1                    *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCR_BES0                    *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCR_BES1                    *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCR_CGE0                    *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCR_CGE1                    *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0300UL))
+#define bFM3_QPRC0_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0304UL))
+#define bFM3_QPRC0_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0308UL))
+#define bFM3_QPRC0_QCRL_RCM1                   *((volatile unsigned int*)(0x424C030CUL))
+#define bFM3_QPRC0_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0310UL))
+#define bFM3_QPRC0_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0314UL))
+#define bFM3_QPRC0_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0318UL))
+#define bFM3_QPRC0_QCRL_SWAP                   *((volatile unsigned int*)(0x424C031CUL))
+#define bFM3_QPRC0_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0320UL))
+#define bFM3_QPRC0_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0324UL))
+#define bFM3_QPRC0_QCRH_AES0                   *((volatile unsigned int*)(0x424C0328UL))
+#define bFM3_QPRC0_QCRH_AES1                   *((volatile unsigned int*)(0x424C032CUL))
+#define bFM3_QPRC0_QCRH_BES0                   *((volatile unsigned int*)(0x424C0330UL))
+#define bFM3_QPRC0_QCRH_BES1                   *((volatile unsigned int*)(0x424C0334UL))
+#define bFM3_QPRC0_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0338UL))
+#define bFM3_QPRC0_QCRH_CGE1                   *((volatile unsigned int*)(0x424C033CUL))
+#define bFM3_QPRC0_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0380UL))
+#define bFM3_QPRC0_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0384UL))
+#define bFM3_QPRC0_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0388UL))
+
+/* Quad position and revolution counter channel 1 registers */
+#define bFM3_QPRC1_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICR_QPCMF                  *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICR_OUZIE                  *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICR_UFDF                   *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICR_OFDF                   *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICR_ZIIF                   *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICR_CDCIE                  *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICR_CDCF                   *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICR_DIRPC                  *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICR_DIROU                  *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C0A80UL))
+#define bFM3_QPRC1_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C0A84UL))
+#define bFM3_QPRC1_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C0A88UL))
+#define bFM3_QPRC1_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C0A8CUL))
+#define bFM3_QPRC1_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C0A90UL))
+#define bFM3_QPRC1_QICRL_UFDF                  *((volatile unsigned int*)(0x424C0A94UL))
+#define bFM3_QPRC1_QICRL_OFDF                  *((volatile unsigned int*)(0x424C0A98UL))
+#define bFM3_QPRC1_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C0A9CUL))
+#define bFM3_QPRC1_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C0AA0UL))
+#define bFM3_QPRC1_QICRH_CDCF                  *((volatile unsigned int*)(0x424C0AA4UL))
+#define bFM3_QPRC1_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C0AA8UL))
+#define bFM3_QPRC1_QICRH_DIROU                 *((volatile unsigned int*)(0x424C0AACUL))
+#define bFM3_QPRC1_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C0AB0UL))
+#define bFM3_QPRC1_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C0AB4UL))
+#define bFM3_QPRC1_QCR_PCM0                    *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCR_PCM1                    *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCR_RCM0                    *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCR_RCM1                    *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCR_PSTP                    *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCR_CGSC                    *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCR_RSEL                    *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCR_SWAP                    *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCR_PCRM0                   *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCR_PCRM1                   *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCR_AES0                    *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCR_AES1                    *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCR_BES0                    *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCR_BES1                    *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCR_CGE0                    *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCR_CGE1                    *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QCRL_PCM0                   *((volatile unsigned int*)(0x424C0B00UL))
+#define bFM3_QPRC1_QCRL_PCM1                   *((volatile unsigned int*)(0x424C0B04UL))
+#define bFM3_QPRC1_QCRL_RCM0                   *((volatile unsigned int*)(0x424C0B08UL))
+#define bFM3_QPRC1_QCRL_RCM1                   *((volatile unsigned int*)(0x424C0B0CUL))
+#define bFM3_QPRC1_QCRL_PSTP                   *((volatile unsigned int*)(0x424C0B10UL))
+#define bFM3_QPRC1_QCRL_CGSC                   *((volatile unsigned int*)(0x424C0B14UL))
+#define bFM3_QPRC1_QCRL_RSEL                   *((volatile unsigned int*)(0x424C0B18UL))
+#define bFM3_QPRC1_QCRL_SWAP                   *((volatile unsigned int*)(0x424C0B1CUL))
+#define bFM3_QPRC1_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C0B20UL))
+#define bFM3_QPRC1_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C0B24UL))
+#define bFM3_QPRC1_QCRH_AES0                   *((volatile unsigned int*)(0x424C0B28UL))
+#define bFM3_QPRC1_QCRH_AES1                   *((volatile unsigned int*)(0x424C0B2CUL))
+#define bFM3_QPRC1_QCRH_BES0                   *((volatile unsigned int*)(0x424C0B30UL))
+#define bFM3_QPRC1_QCRH_BES1                   *((volatile unsigned int*)(0x424C0B34UL))
+#define bFM3_QPRC1_QCRH_CGE0                   *((volatile unsigned int*)(0x424C0B38UL))
+#define bFM3_QPRC1_QCRH_CGE1                   *((volatile unsigned int*)(0x424C0B3CUL))
+#define bFM3_QPRC1_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C0B80UL))
+#define bFM3_QPRC1_QECR_ORNGF                  *((volatile unsigned int*)(0x424C0B84UL))
+#define bFM3_QPRC1_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C0B88UL))
+
+/* Quad position and revolution counter channel 2 registers */
+#define bFM3_QPRC2_QICR_QPCMIE                 *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICR_QPCMF                  *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICR_QPRCMIE                *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICR_QPRCMF                 *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICR_OUZIE                  *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICR_UFDF                   *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICR_OFDF                   *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICR_ZIIF                   *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICR_CDCIE                  *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICR_CDCF                   *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICR_DIRPC                  *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICR_DIROU                  *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICR_QPCNRCMIE              *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICR_QPCNRCMF               *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QICRL_QPCMIE                *((volatile unsigned int*)(0x424C1280UL))
+#define bFM3_QPRC2_QICRL_QPCMF                 *((volatile unsigned int*)(0x424C1284UL))
+#define bFM3_QPRC2_QICRL_QPRCMIE               *((volatile unsigned int*)(0x424C1288UL))
+#define bFM3_QPRC2_QICRL_QPRCMF                *((volatile unsigned int*)(0x424C128CUL))
+#define bFM3_QPRC2_QICRL_OUZIE                 *((volatile unsigned int*)(0x424C1290UL))
+#define bFM3_QPRC2_QICRL_UFDF                  *((volatile unsigned int*)(0x424C1294UL))
+#define bFM3_QPRC2_QICRL_OFDF                  *((volatile unsigned int*)(0x424C1298UL))
+#define bFM3_QPRC2_QICRL_ZIIF                  *((volatile unsigned int*)(0x424C129CUL))
+#define bFM3_QPRC2_QICRH_CDCIE                 *((volatile unsigned int*)(0x424C12A0UL))
+#define bFM3_QPRC2_QICRH_CDCF                  *((volatile unsigned int*)(0x424C12A4UL))
+#define bFM3_QPRC2_QICRH_DIRPC                 *((volatile unsigned int*)(0x424C12A8UL))
+#define bFM3_QPRC2_QICRH_DIROU                 *((volatile unsigned int*)(0x424C12ACUL))
+#define bFM3_QPRC2_QICRH_QPCNRCMIE             *((volatile unsigned int*)(0x424C12B0UL))
+#define bFM3_QPRC2_QICRH_QPCNRCMF              *((volatile unsigned int*)(0x424C12B4UL))
+#define bFM3_QPRC2_QCR_PCM0                    *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCR_PCM1                    *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCR_RCM0                    *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCR_RCM1                    *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCR_PSTP                    *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCR_CGSC                    *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCR_RSEL                    *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCR_SWAP                    *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCR_PCRM0                   *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCR_PCRM1                   *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCR_AES0                    *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCR_AES1                    *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCR_BES0                    *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCR_BES1                    *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCR_CGE0                    *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCR_CGE1                    *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QCRL_PCM0                   *((volatile unsigned int*)(0x424C1300UL))
+#define bFM3_QPRC2_QCRL_PCM1                   *((volatile unsigned int*)(0x424C1304UL))
+#define bFM3_QPRC2_QCRL_RCM0                   *((volatile unsigned int*)(0x424C1308UL))
+#define bFM3_QPRC2_QCRL_RCM1                   *((volatile unsigned int*)(0x424C130CUL))
+#define bFM3_QPRC2_QCRL_PSTP                   *((volatile unsigned int*)(0x424C1310UL))
+#define bFM3_QPRC2_QCRL_CGSC                   *((volatile unsigned int*)(0x424C1314UL))
+#define bFM3_QPRC2_QCRL_RSEL                   *((volatile unsigned int*)(0x424C1318UL))
+#define bFM3_QPRC2_QCRL_SWAP                   *((volatile unsigned int*)(0x424C131CUL))
+#define bFM3_QPRC2_QCRH_PCRM0                  *((volatile unsigned int*)(0x424C1320UL))
+#define bFM3_QPRC2_QCRH_PCRM1                  *((volatile unsigned int*)(0x424C1324UL))
+#define bFM3_QPRC2_QCRH_AES0                   *((volatile unsigned int*)(0x424C1328UL))
+#define bFM3_QPRC2_QCRH_AES1                   *((volatile unsigned int*)(0x424C132CUL))
+#define bFM3_QPRC2_QCRH_BES0                   *((volatile unsigned int*)(0x424C1330UL))
+#define bFM3_QPRC2_QCRH_BES1                   *((volatile unsigned int*)(0x424C1334UL))
+#define bFM3_QPRC2_QCRH_CGE0                   *((volatile unsigned int*)(0x424C1338UL))
+#define bFM3_QPRC2_QCRH_CGE1                   *((volatile unsigned int*)(0x424C133CUL))
+#define bFM3_QPRC2_QECR_ORNGMD                 *((volatile unsigned int*)(0x424C1380UL))
+#define bFM3_QPRC2_QECR_ORNGF                  *((volatile unsigned int*)(0x424C1384UL))
+#define bFM3_QPRC2_QECR_ORNGIE                 *((volatile unsigned int*)(0x424C1388UL))
+
+/* 12-bit ADC unit 0 registers */
+#define bFM3_ADC0_ADSR_SCS                     *((volatile unsigned int*)(0x424E0000UL))
+#define bFM3_ADC0_ADSR_PCS                     *((volatile unsigned int*)(0x424E0004UL))
+#define bFM3_ADC0_ADSR_PCNS                    *((volatile unsigned int*)(0x424E0008UL))
+#define bFM3_ADC0_ADSR_FDAS                    *((volatile unsigned int*)(0x424E0018UL))
+#define bFM3_ADC0_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E001CUL))
+#define bFM3_ADC0_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E0020UL))
+#define bFM3_ADC0_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E0024UL))
+#define bFM3_ADC0_ADCR_PCIE                    *((volatile unsigned int*)(0x424E0028UL))
+#define bFM3_ADC0_ADCR_SCIE                    *((volatile unsigned int*)(0x424E002CUL))
+#define bFM3_ADC0_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E0034UL))
+#define bFM3_ADC0_ADCR_PCIF                    *((volatile unsigned int*)(0x424E0038UL))
+#define bFM3_ADC0_ADCR_SCIF                    *((volatile unsigned int*)(0x424E003CUL))
+#define bFM3_ADC0_SFNS_SFS0                    *((volatile unsigned int*)(0x424E0100UL))
+#define bFM3_ADC0_SFNS_SFS1                    *((volatile unsigned int*)(0x424E0104UL))
+#define bFM3_ADC0_SFNS_SFS2                    *((volatile unsigned int*)(0x424E0108UL))
+#define bFM3_ADC0_SFNS_SFS3                    *((volatile unsigned int*)(0x424E010CUL))
+#define bFM3_ADC0_SCCR_SSTR                    *((volatile unsigned int*)(0x424E0120UL))
+#define bFM3_ADC0_SCCR_SHEN                    *((volatile unsigned int*)(0x424E0124UL))
+#define bFM3_ADC0_SCCR_RPT                     *((volatile unsigned int*)(0x424E0128UL))
+#define bFM3_ADC0_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E0130UL))
+#define bFM3_ADC0_SCCR_SOVR                    *((volatile unsigned int*)(0x424E0134UL))
+#define bFM3_ADC0_SCCR_SFUL                    *((volatile unsigned int*)(0x424E0138UL))
+#define bFM3_ADC0_SCCR_SEMP                    *((volatile unsigned int*)(0x424E013CUL))
+#define bFM3_ADC0_SCFD_SC0                     *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFD_SC1                     *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFD_SC2                     *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFD_SC3                     *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFD_SC4                     *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFD_RS0                     *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFD_RS1                     *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFD_INVL                    *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFD_SD0                     *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFD_SD1                     *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFD_SD2                     *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFD_SD3                     *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFD_SD4                     *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFD_SD5                     *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFD_SD6                     *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFD_SD7                     *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFD_SD8                     *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFD_SD9                     *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFD_SD10                    *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFD_SD11                    *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCFDL_SC0                    *((volatile unsigned int*)(0x424E0180UL))
+#define bFM3_ADC0_SCFDL_SC1                    *((volatile unsigned int*)(0x424E0184UL))
+#define bFM3_ADC0_SCFDL_SC2                    *((volatile unsigned int*)(0x424E0188UL))
+#define bFM3_ADC0_SCFDL_SC3                    *((volatile unsigned int*)(0x424E018CUL))
+#define bFM3_ADC0_SCFDL_SC4                    *((volatile unsigned int*)(0x424E0190UL))
+#define bFM3_ADC0_SCFDL_RS0                    *((volatile unsigned int*)(0x424E01A0UL))
+#define bFM3_ADC0_SCFDL_RS1                    *((volatile unsigned int*)(0x424E01A4UL))
+#define bFM3_ADC0_SCFDL_INVL                   *((volatile unsigned int*)(0x424E01B0UL))
+#define bFM3_ADC0_SCFDH_SD0                    *((volatile unsigned int*)(0x424E01D0UL))
+#define bFM3_ADC0_SCFDH_SD1                    *((volatile unsigned int*)(0x424E01D4UL))
+#define bFM3_ADC0_SCFDH_SD2                    *((volatile unsigned int*)(0x424E01D8UL))
+#define bFM3_ADC0_SCFDH_SD3                    *((volatile unsigned int*)(0x424E01DCUL))
+#define bFM3_ADC0_SCFDH_SD4                    *((volatile unsigned int*)(0x424E01E0UL))
+#define bFM3_ADC0_SCFDH_SD5                    *((volatile unsigned int*)(0x424E01E4UL))
+#define bFM3_ADC0_SCFDH_SD6                    *((volatile unsigned int*)(0x424E01E8UL))
+#define bFM3_ADC0_SCFDH_SD7                    *((volatile unsigned int*)(0x424E01ECUL))
+#define bFM3_ADC0_SCFDH_SD8                    *((volatile unsigned int*)(0x424E01F0UL))
+#define bFM3_ADC0_SCFDH_SD9                    *((volatile unsigned int*)(0x424E01F4UL))
+#define bFM3_ADC0_SCFDH_SD10                   *((volatile unsigned int*)(0x424E01F8UL))
+#define bFM3_ADC0_SCFDH_SD11                   *((volatile unsigned int*)(0x424E01FCUL))
+#define bFM3_ADC0_SCIS23_AN16                  *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS23_AN17                  *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS23_AN18                  *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS23_AN19                  *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS23_AN20                  *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS23_AN21                  *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS23_AN22                  *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS23_AN23                  *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS23_AN24                  *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS23_AN25                  *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS23_AN26                  *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS23_AN27                  *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS23_AN28                  *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS23_AN29                  *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS23_AN30                  *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS23_AN31                  *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS2_AN16                   *((volatile unsigned int*)(0x424E0200UL))
+#define bFM3_ADC0_SCIS2_AN17                   *((volatile unsigned int*)(0x424E0204UL))
+#define bFM3_ADC0_SCIS2_AN18                   *((volatile unsigned int*)(0x424E0208UL))
+#define bFM3_ADC0_SCIS2_AN19                   *((volatile unsigned int*)(0x424E020CUL))
+#define bFM3_ADC0_SCIS2_AN20                   *((volatile unsigned int*)(0x424E0210UL))
+#define bFM3_ADC0_SCIS2_AN21                   *((volatile unsigned int*)(0x424E0214UL))
+#define bFM3_ADC0_SCIS2_AN22                   *((volatile unsigned int*)(0x424E0218UL))
+#define bFM3_ADC0_SCIS2_AN23                   *((volatile unsigned int*)(0x424E021CUL))
+#define bFM3_ADC0_SCIS3_AN24                   *((volatile unsigned int*)(0x424E0220UL))
+#define bFM3_ADC0_SCIS3_AN25                   *((volatile unsigned int*)(0x424E0224UL))
+#define bFM3_ADC0_SCIS3_AN26                   *((volatile unsigned int*)(0x424E0228UL))
+#define bFM3_ADC0_SCIS3_AN27                   *((volatile unsigned int*)(0x424E022CUL))
+#define bFM3_ADC0_SCIS3_AN28                   *((volatile unsigned int*)(0x424E0230UL))
+#define bFM3_ADC0_SCIS3_AN29                   *((volatile unsigned int*)(0x424E0234UL))
+#define bFM3_ADC0_SCIS3_AN30                   *((volatile unsigned int*)(0x424E0238UL))
+#define bFM3_ADC0_SCIS3_AN31                   *((volatile unsigned int*)(0x424E023CUL))
+#define bFM3_ADC0_SCIS01_AN0                   *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS01_AN1                   *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS01_AN2                   *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS01_AN3                   *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS01_AN4                   *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS01_AN5                   *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS01_AN6                   *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS01_AN7                   *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS01_AN8                   *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS01_AN9                   *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS01_AN10                  *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS01_AN11                  *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS01_AN12                  *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS01_AN13                  *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS01_AN14                  *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS01_AN15                  *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_SCIS0_AN0                    *((volatile unsigned int*)(0x424E0280UL))
+#define bFM3_ADC0_SCIS0_AN1                    *((volatile unsigned int*)(0x424E0284UL))
+#define bFM3_ADC0_SCIS0_AN2                    *((volatile unsigned int*)(0x424E0288UL))
+#define bFM3_ADC0_SCIS0_AN3                    *((volatile unsigned int*)(0x424E028CUL))
+#define bFM3_ADC0_SCIS0_AN4                    *((volatile unsigned int*)(0x424E0290UL))
+#define bFM3_ADC0_SCIS0_AN5                    *((volatile unsigned int*)(0x424E0294UL))
+#define bFM3_ADC0_SCIS0_AN6                    *((volatile unsigned int*)(0x424E0298UL))
+#define bFM3_ADC0_SCIS0_AN7                    *((volatile unsigned int*)(0x424E029CUL))
+#define bFM3_ADC0_SCIS1_AN8                    *((volatile unsigned int*)(0x424E02A0UL))
+#define bFM3_ADC0_SCIS1_AN9                    *((volatile unsigned int*)(0x424E02A4UL))
+#define bFM3_ADC0_SCIS1_AN10                   *((volatile unsigned int*)(0x424E02A8UL))
+#define bFM3_ADC0_SCIS1_AN11                   *((volatile unsigned int*)(0x424E02ACUL))
+#define bFM3_ADC0_SCIS1_AN12                   *((volatile unsigned int*)(0x424E02B0UL))
+#define bFM3_ADC0_SCIS1_AN13                   *((volatile unsigned int*)(0x424E02B4UL))
+#define bFM3_ADC0_SCIS1_AN14                   *((volatile unsigned int*)(0x424E02B8UL))
+#define bFM3_ADC0_SCIS1_AN15                   *((volatile unsigned int*)(0x424E02BCUL))
+#define bFM3_ADC0_PFNS_PFS0                    *((volatile unsigned int*)(0x424E0300UL))
+#define bFM3_ADC0_PFNS_PFS1                    *((volatile unsigned int*)(0x424E0304UL))
+#define bFM3_ADC0_PFNS_TEST0                   *((volatile unsigned int*)(0x424E0310UL))
+#define bFM3_ADC0_PFNS_TEST1                   *((volatile unsigned int*)(0x424E0314UL))
+#define bFM3_ADC0_PCCR_PSTR                    *((volatile unsigned int*)(0x424E0320UL))
+#define bFM3_ADC0_PCCR_PHEN                    *((volatile unsigned int*)(0x424E0324UL))
+#define bFM3_ADC0_PCCR_PEEN                    *((volatile unsigned int*)(0x424E0328UL))
+#define bFM3_ADC0_PCCR_ESCE                    *((volatile unsigned int*)(0x424E032CUL))
+#define bFM3_ADC0_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E0330UL))
+#define bFM3_ADC0_PCCR_POVR                    *((volatile unsigned int*)(0x424E0334UL))
+#define bFM3_ADC0_PCCR_PFUL                    *((volatile unsigned int*)(0x424E0338UL))
+#define bFM3_ADC0_PCCR_PEMP                    *((volatile unsigned int*)(0x424E033CUL))
+#define bFM3_ADC0_PCFD_PC0                     *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFD_PC1                     *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFD_PC2                     *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFD_PC3                     *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFD_PC4                     *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFD_RS0                     *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFD_RS1                     *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFD_RS2                     *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFD_INVL                    *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFD_PD0                     *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFD_PD1                     *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFD_PD2                     *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFD_PD3                     *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFD_PD4                     *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFD_PD5                     *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFD_PD6                     *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFD_PD7                     *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFD_PD8                     *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFD_PD9                     *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFD_PD10                    *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFD_PD11                    *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCFDL_PC0                    *((volatile unsigned int*)(0x424E0380UL))
+#define bFM3_ADC0_PCFDL_PC1                    *((volatile unsigned int*)(0x424E0384UL))
+#define bFM3_ADC0_PCFDL_PC2                    *((volatile unsigned int*)(0x424E0388UL))
+#define bFM3_ADC0_PCFDL_PC3                    *((volatile unsigned int*)(0x424E038CUL))
+#define bFM3_ADC0_PCFDL_PC4                    *((volatile unsigned int*)(0x424E0390UL))
+#define bFM3_ADC0_PCFDL_RS0                    *((volatile unsigned int*)(0x424E03A0UL))
+#define bFM3_ADC0_PCFDL_RS1                    *((volatile unsigned int*)(0x424E03A4UL))
+#define bFM3_ADC0_PCFDL_RS2                    *((volatile unsigned int*)(0x424E03A8UL))
+#define bFM3_ADC0_PCFDL_INVL                   *((volatile unsigned int*)(0x424E03B0UL))
+#define bFM3_ADC0_PCFDH_PD0                    *((volatile unsigned int*)(0x424E03D0UL))
+#define bFM3_ADC0_PCFDH_PD1                    *((volatile unsigned int*)(0x424E03D4UL))
+#define bFM3_ADC0_PCFDH_PD2                    *((volatile unsigned int*)(0x424E03D8UL))
+#define bFM3_ADC0_PCFDH_PD3                    *((volatile unsigned int*)(0x424E03DCUL))
+#define bFM3_ADC0_PCFDH_PD4                    *((volatile unsigned int*)(0x424E03E0UL))
+#define bFM3_ADC0_PCFDH_PD5                    *((volatile unsigned int*)(0x424E03E4UL))
+#define bFM3_ADC0_PCFDH_PD6                    *((volatile unsigned int*)(0x424E03E8UL))
+#define bFM3_ADC0_PCFDH_PD7                    *((volatile unsigned int*)(0x424E03ECUL))
+#define bFM3_ADC0_PCFDH_PD8                    *((volatile unsigned int*)(0x424E03F0UL))
+#define bFM3_ADC0_PCFDH_PD9                    *((volatile unsigned int*)(0x424E03F4UL))
+#define bFM3_ADC0_PCFDH_PD10                   *((volatile unsigned int*)(0x424E03F8UL))
+#define bFM3_ADC0_PCFDH_PD11                   *((volatile unsigned int*)(0x424E03FCUL))
+#define bFM3_ADC0_PCIS_P1A0                    *((volatile unsigned int*)(0x424E0400UL))
+#define bFM3_ADC0_PCIS_P1A1                    *((volatile unsigned int*)(0x424E0404UL))
+#define bFM3_ADC0_PCIS_P1A2                    *((volatile unsigned int*)(0x424E0408UL))
+#define bFM3_ADC0_PCIS_P2A0                    *((volatile unsigned int*)(0x424E040CUL))
+#define bFM3_ADC0_PCIS_P2A1                    *((volatile unsigned int*)(0x424E0410UL))
+#define bFM3_ADC0_PCIS_P2A2                    *((volatile unsigned int*)(0x424E0414UL))
+#define bFM3_ADC0_PCIS_P2A3                    *((volatile unsigned int*)(0x424E0418UL))
+#define bFM3_ADC0_PCIS_P2A4                    *((volatile unsigned int*)(0x424E041CUL))
+#define bFM3_ADC0_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E0480UL))
+#define bFM3_ADC0_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E0484UL))
+#define bFM3_ADC0_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E0488UL))
+#define bFM3_ADC0_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E048CUL))
+#define bFM3_ADC0_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E0490UL))
+#define bFM3_ADC0_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E0494UL))
+#define bFM3_ADC0_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E0498UL))
+#define bFM3_ADC0_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E049CUL))
+#define bFM3_ADC0_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E04D8UL))
+#define bFM3_ADC0_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E04DCUL))
+#define bFM3_ADC0_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E04E0UL))
+#define bFM3_ADC0_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E04E4UL))
+#define bFM3_ADC0_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E04E8UL))
+#define bFM3_ADC0_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E04ECUL))
+#define bFM3_ADC0_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E04F0UL))
+#define bFM3_ADC0_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E04F4UL))
+#define bFM3_ADC0_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E04F8UL))
+#define bFM3_ADC0_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E04FCUL))
+#define bFM3_ADC0_ADSS23_TS16                  *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS23_TS17                  *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS23_TS18                  *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS23_TS19                  *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS23_TS20                  *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS23_TS21                  *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS23_TS22                  *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS23_TS23                  *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS23_TS24                  *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS23_TS25                  *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS23_TS26                  *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS23_TS27                  *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS23_TS28                  *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS23_TS29                  *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS23_TS30                  *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS23_TS31                  *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS2_TS16                   *((volatile unsigned int*)(0x424E0500UL))
+#define bFM3_ADC0_ADSS2_TS17                   *((volatile unsigned int*)(0x424E0504UL))
+#define bFM3_ADC0_ADSS2_TS18                   *((volatile unsigned int*)(0x424E0508UL))
+#define bFM3_ADC0_ADSS2_TS19                   *((volatile unsigned int*)(0x424E050CUL))
+#define bFM3_ADC0_ADSS2_TS20                   *((volatile unsigned int*)(0x424E0510UL))
+#define bFM3_ADC0_ADSS2_TS21                   *((volatile unsigned int*)(0x424E0514UL))
+#define bFM3_ADC0_ADSS2_TS22                   *((volatile unsigned int*)(0x424E0518UL))
+#define bFM3_ADC0_ADSS2_TS23                   *((volatile unsigned int*)(0x424E051CUL))
+#define bFM3_ADC0_ADSS3_TS24                   *((volatile unsigned int*)(0x424E0520UL))
+#define bFM3_ADC0_ADSS3_TS25                   *((volatile unsigned int*)(0x424E0524UL))
+#define bFM3_ADC0_ADSS3_TS26                   *((volatile unsigned int*)(0x424E0528UL))
+#define bFM3_ADC0_ADSS3_TS27                   *((volatile unsigned int*)(0x424E052CUL))
+#define bFM3_ADC0_ADSS3_TS28                   *((volatile unsigned int*)(0x424E0530UL))
+#define bFM3_ADC0_ADSS3_TS29                   *((volatile unsigned int*)(0x424E0534UL))
+#define bFM3_ADC0_ADSS3_TS30                   *((volatile unsigned int*)(0x424E0538UL))
+#define bFM3_ADC0_ADSS3_TS31                   *((volatile unsigned int*)(0x424E053CUL))
+#define bFM3_ADC0_ADSS01_TS0                   *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS01_TS1                   *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS01_TS2                   *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS01_TS3                   *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS01_TS4                   *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS01_TS5                   *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS01_TS6                   *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS01_TS7                   *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS01_TS8                   *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS01_TS9                   *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS01_TS10                  *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS01_TS11                  *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS01_TS12                  *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS01_TS13                  *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS01_TS14                  *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS01_TS15                  *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADSS0_TS0                    *((volatile unsigned int*)(0x424E0580UL))
+#define bFM3_ADC0_ADSS0_TS1                    *((volatile unsigned int*)(0x424E0584UL))
+#define bFM3_ADC0_ADSS0_TS2                    *((volatile unsigned int*)(0x424E0588UL))
+#define bFM3_ADC0_ADSS0_TS3                    *((volatile unsigned int*)(0x424E058CUL))
+#define bFM3_ADC0_ADSS0_TS4                    *((volatile unsigned int*)(0x424E0590UL))
+#define bFM3_ADC0_ADSS0_TS5                    *((volatile unsigned int*)(0x424E0594UL))
+#define bFM3_ADC0_ADSS0_TS6                    *((volatile unsigned int*)(0x424E0598UL))
+#define bFM3_ADC0_ADSS0_TS7                    *((volatile unsigned int*)(0x424E059CUL))
+#define bFM3_ADC0_ADSS1_TS8                    *((volatile unsigned int*)(0x424E05A0UL))
+#define bFM3_ADC0_ADSS1_TS9                    *((volatile unsigned int*)(0x424E05A4UL))
+#define bFM3_ADC0_ADSS1_TS10                   *((volatile unsigned int*)(0x424E05A8UL))
+#define bFM3_ADC0_ADSS1_TS11                   *((volatile unsigned int*)(0x424E05ACUL))
+#define bFM3_ADC0_ADSS1_TS12                   *((volatile unsigned int*)(0x424E05B0UL))
+#define bFM3_ADC0_ADSS1_TS13                   *((volatile unsigned int*)(0x424E05B4UL))
+#define bFM3_ADC0_ADSS1_TS14                   *((volatile unsigned int*)(0x424E05B8UL))
+#define bFM3_ADC0_ADSS1_TS15                   *((volatile unsigned int*)(0x424E05BCUL))
+#define bFM3_ADC0_ADST01_ST10                  *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST01_ST11                  *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST01_ST12                  *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST01_ST13                  *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST01_ST14                  *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST01_STX10                 *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST01_STX11                 *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST01_STX12                 *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST01_ST00                  *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST01_ST01                  *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST01_ST02                  *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST01_ST03                  *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST01_ST04                  *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST01_STX00                 *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST01_STX01                 *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST01_STX02                 *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADST1_ST10                   *((volatile unsigned int*)(0x424E0600UL))
+#define bFM3_ADC0_ADST1_ST11                   *((volatile unsigned int*)(0x424E0604UL))
+#define bFM3_ADC0_ADST1_ST12                   *((volatile unsigned int*)(0x424E0608UL))
+#define bFM3_ADC0_ADST1_ST13                   *((volatile unsigned int*)(0x424E060CUL))
+#define bFM3_ADC0_ADST1_ST14                   *((volatile unsigned int*)(0x424E0610UL))
+#define bFM3_ADC0_ADST1_STX10                  *((volatile unsigned int*)(0x424E0614UL))
+#define bFM3_ADC0_ADST1_STX11                  *((volatile unsigned int*)(0x424E0618UL))
+#define bFM3_ADC0_ADST1_STX12                  *((volatile unsigned int*)(0x424E061CUL))
+#define bFM3_ADC0_ADST0_ST00                   *((volatile unsigned int*)(0x424E0620UL))
+#define bFM3_ADC0_ADST0_ST01                   *((volatile unsigned int*)(0x424E0624UL))
+#define bFM3_ADC0_ADST0_ST02                   *((volatile unsigned int*)(0x424E0628UL))
+#define bFM3_ADC0_ADST0_ST03                   *((volatile unsigned int*)(0x424E062CUL))
+#define bFM3_ADC0_ADST0_ST04                   *((volatile unsigned int*)(0x424E0630UL))
+#define bFM3_ADC0_ADST0_STX00                  *((volatile unsigned int*)(0x424E0634UL))
+#define bFM3_ADC0_ADST0_STX01                  *((volatile unsigned int*)(0x424E0638UL))
+#define bFM3_ADC0_ADST0_STX02                  *((volatile unsigned int*)(0x424E063CUL))
+#define bFM3_ADC0_ADCT_CT0                     *((volatile unsigned int*)(0x424E0680UL))
+#define bFM3_ADC0_ADCT_CT1                     *((volatile unsigned int*)(0x424E0684UL))
+#define bFM3_ADC0_ADCT_CT2                     *((volatile unsigned int*)(0x424E0688UL))
+#define bFM3_ADC0_ADCT_CT3                     *((volatile unsigned int*)(0x424E068CUL))
+#define bFM3_ADC0_ADCT_CT4                     *((volatile unsigned int*)(0x424E0690UL))
+#define bFM3_ADC0_ADCT_CT5                     *((volatile unsigned int*)(0x424E0694UL))
+#define bFM3_ADC0_ADCT_CT6                     *((volatile unsigned int*)(0x424E0698UL))
+#define bFM3_ADC0_ADCT_CT7                     *((volatile unsigned int*)(0x424E069CUL))
+#define bFM3_ADC0_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E0700UL))
+#define bFM3_ADC0_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E0704UL))
+#define bFM3_ADC0_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E0708UL))
+#define bFM3_ADC0_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E070CUL))
+#define bFM3_ADC0_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E0720UL))
+#define bFM3_ADC0_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E0724UL))
+#define bFM3_ADC0_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E0728UL))
+#define bFM3_ADC0_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E072CUL))
+#define bFM3_ADC0_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E0780UL))
+#define bFM3_ADC0_ADCEN_READY                  *((volatile unsigned int*)(0x424E0784UL))
+#define bFM3_ADC0_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E0790UL))
+#define bFM3_ADC0_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E0794UL))
+
+/* 12-bit ADC unit 1 registers */
+#define bFM3_ADC1_ADSR_SCS                     *((volatile unsigned int*)(0x424E2000UL))
+#define bFM3_ADC1_ADSR_PCS                     *((volatile unsigned int*)(0x424E2004UL))
+#define bFM3_ADC1_ADSR_PCNS                    *((volatile unsigned int*)(0x424E2008UL))
+#define bFM3_ADC1_ADSR_FDAS                    *((volatile unsigned int*)(0x424E2018UL))
+#define bFM3_ADC1_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E201CUL))
+#define bFM3_ADC1_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E2020UL))
+#define bFM3_ADC1_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E2024UL))
+#define bFM3_ADC1_ADCR_PCIE                    *((volatile unsigned int*)(0x424E2028UL))
+#define bFM3_ADC1_ADCR_SCIE                    *((volatile unsigned int*)(0x424E202CUL))
+#define bFM3_ADC1_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E2034UL))
+#define bFM3_ADC1_ADCR_PCIF                    *((volatile unsigned int*)(0x424E2038UL))
+#define bFM3_ADC1_ADCR_SCIF                    *((volatile unsigned int*)(0x424E203CUL))
+#define bFM3_ADC1_SFNS_SFS0                    *((volatile unsigned int*)(0x424E2100UL))
+#define bFM3_ADC1_SFNS_SFS1                    *((volatile unsigned int*)(0x424E2104UL))
+#define bFM3_ADC1_SFNS_SFS2                    *((volatile unsigned int*)(0x424E2108UL))
+#define bFM3_ADC1_SFNS_SFS3                    *((volatile unsigned int*)(0x424E210CUL))
+#define bFM3_ADC1_SCCR_SSTR                    *((volatile unsigned int*)(0x424E2120UL))
+#define bFM3_ADC1_SCCR_SHEN                    *((volatile unsigned int*)(0x424E2124UL))
+#define bFM3_ADC1_SCCR_RPT                     *((volatile unsigned int*)(0x424E2128UL))
+#define bFM3_ADC1_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E2130UL))
+#define bFM3_ADC1_SCCR_SOVR                    *((volatile unsigned int*)(0x424E2134UL))
+#define bFM3_ADC1_SCCR_SFUL                    *((volatile unsigned int*)(0x424E2138UL))
+#define bFM3_ADC1_SCCR_SEMP                    *((volatile unsigned int*)(0x424E213CUL))
+#define bFM3_ADC1_SCFD_SC0                     *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFD_SC1                     *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFD_SC2                     *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFD_SC3                     *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFD_SC4                     *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFD_RS0                     *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFD_RS1                     *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFD_INVL                    *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFD_SD0                     *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFD_SD1                     *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFD_SD2                     *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFD_SD3                     *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFD_SD4                     *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFD_SD5                     *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFD_SD6                     *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFD_SD7                     *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFD_SD8                     *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFD_SD9                     *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFD_SD10                    *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFD_SD11                    *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCFDL_SC0                    *((volatile unsigned int*)(0x424E2180UL))
+#define bFM3_ADC1_SCFDL_SC1                    *((volatile unsigned int*)(0x424E2184UL))
+#define bFM3_ADC1_SCFDL_SC2                    *((volatile unsigned int*)(0x424E2188UL))
+#define bFM3_ADC1_SCFDL_SC3                    *((volatile unsigned int*)(0x424E218CUL))
+#define bFM3_ADC1_SCFDL_SC4                    *((volatile unsigned int*)(0x424E2190UL))
+#define bFM3_ADC1_SCFDL_RS0                    *((volatile unsigned int*)(0x424E21A0UL))
+#define bFM3_ADC1_SCFDL_RS1                    *((volatile unsigned int*)(0x424E21A4UL))
+#define bFM3_ADC1_SCFDL_INVL                   *((volatile unsigned int*)(0x424E21B0UL))
+#define bFM3_ADC1_SCFDH_SD0                    *((volatile unsigned int*)(0x424E21D0UL))
+#define bFM3_ADC1_SCFDH_SD1                    *((volatile unsigned int*)(0x424E21D4UL))
+#define bFM3_ADC1_SCFDH_SD2                    *((volatile unsigned int*)(0x424E21D8UL))
+#define bFM3_ADC1_SCFDH_SD3                    *((volatile unsigned int*)(0x424E21DCUL))
+#define bFM3_ADC1_SCFDH_SD4                    *((volatile unsigned int*)(0x424E21E0UL))
+#define bFM3_ADC1_SCFDH_SD5                    *((volatile unsigned int*)(0x424E21E4UL))
+#define bFM3_ADC1_SCFDH_SD6                    *((volatile unsigned int*)(0x424E21E8UL))
+#define bFM3_ADC1_SCFDH_SD7                    *((volatile unsigned int*)(0x424E21ECUL))
+#define bFM3_ADC1_SCFDH_SD8                    *((volatile unsigned int*)(0x424E21F0UL))
+#define bFM3_ADC1_SCFDH_SD9                    *((volatile unsigned int*)(0x424E21F4UL))
+#define bFM3_ADC1_SCFDH_SD10                   *((volatile unsigned int*)(0x424E21F8UL))
+#define bFM3_ADC1_SCFDH_SD11                   *((volatile unsigned int*)(0x424E21FCUL))
+#define bFM3_ADC1_SCIS23_AN16                  *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS23_AN17                  *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS23_AN18                  *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS23_AN19                  *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS23_AN20                  *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS23_AN21                  *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS23_AN22                  *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS23_AN23                  *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS23_AN24                  *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS23_AN25                  *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS23_AN26                  *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS23_AN27                  *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS23_AN28                  *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS23_AN29                  *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS23_AN30                  *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS23_AN31                  *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS2_AN16                   *((volatile unsigned int*)(0x424E2200UL))
+#define bFM3_ADC1_SCIS2_AN17                   *((volatile unsigned int*)(0x424E2204UL))
+#define bFM3_ADC1_SCIS2_AN18                   *((volatile unsigned int*)(0x424E2208UL))
+#define bFM3_ADC1_SCIS2_AN19                   *((volatile unsigned int*)(0x424E220CUL))
+#define bFM3_ADC1_SCIS2_AN20                   *((volatile unsigned int*)(0x424E2210UL))
+#define bFM3_ADC1_SCIS2_AN21                   *((volatile unsigned int*)(0x424E2214UL))
+#define bFM3_ADC1_SCIS2_AN22                   *((volatile unsigned int*)(0x424E2218UL))
+#define bFM3_ADC1_SCIS2_AN23                   *((volatile unsigned int*)(0x424E221CUL))
+#define bFM3_ADC1_SCIS3_AN24                   *((volatile unsigned int*)(0x424E2220UL))
+#define bFM3_ADC1_SCIS3_AN25                   *((volatile unsigned int*)(0x424E2224UL))
+#define bFM3_ADC1_SCIS3_AN26                   *((volatile unsigned int*)(0x424E2228UL))
+#define bFM3_ADC1_SCIS3_AN27                   *((volatile unsigned int*)(0x424E222CUL))
+#define bFM3_ADC1_SCIS3_AN28                   *((volatile unsigned int*)(0x424E2230UL))
+#define bFM3_ADC1_SCIS3_AN29                   *((volatile unsigned int*)(0x424E2234UL))
+#define bFM3_ADC1_SCIS3_AN30                   *((volatile unsigned int*)(0x424E2238UL))
+#define bFM3_ADC1_SCIS3_AN31                   *((volatile unsigned int*)(0x424E223CUL))
+#define bFM3_ADC1_SCIS01_AN0                   *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS01_AN1                   *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS01_AN2                   *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS01_AN3                   *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS01_AN4                   *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS01_AN5                   *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS01_AN6                   *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS01_AN7                   *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS01_AN8                   *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS01_AN9                   *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS01_AN10                  *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS01_AN11                  *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS01_AN12                  *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS01_AN13                  *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS01_AN14                  *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS01_AN15                  *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_SCIS0_AN0                    *((volatile unsigned int*)(0x424E2280UL))
+#define bFM3_ADC1_SCIS0_AN1                    *((volatile unsigned int*)(0x424E2284UL))
+#define bFM3_ADC1_SCIS0_AN2                    *((volatile unsigned int*)(0x424E2288UL))
+#define bFM3_ADC1_SCIS0_AN3                    *((volatile unsigned int*)(0x424E228CUL))
+#define bFM3_ADC1_SCIS0_AN4                    *((volatile unsigned int*)(0x424E2290UL))
+#define bFM3_ADC1_SCIS0_AN5                    *((volatile unsigned int*)(0x424E2294UL))
+#define bFM3_ADC1_SCIS0_AN6                    *((volatile unsigned int*)(0x424E2298UL))
+#define bFM3_ADC1_SCIS0_AN7                    *((volatile unsigned int*)(0x424E229CUL))
+#define bFM3_ADC1_SCIS1_AN8                    *((volatile unsigned int*)(0x424E22A0UL))
+#define bFM3_ADC1_SCIS1_AN9                    *((volatile unsigned int*)(0x424E22A4UL))
+#define bFM3_ADC1_SCIS1_AN10                   *((volatile unsigned int*)(0x424E22A8UL))
+#define bFM3_ADC1_SCIS1_AN11                   *((volatile unsigned int*)(0x424E22ACUL))
+#define bFM3_ADC1_SCIS1_AN12                   *((volatile unsigned int*)(0x424E22B0UL))
+#define bFM3_ADC1_SCIS1_AN13                   *((volatile unsigned int*)(0x424E22B4UL))
+#define bFM3_ADC1_SCIS1_AN14                   *((volatile unsigned int*)(0x424E22B8UL))
+#define bFM3_ADC1_SCIS1_AN15                   *((volatile unsigned int*)(0x424E22BCUL))
+#define bFM3_ADC1_PFNS_PFS0                    *((volatile unsigned int*)(0x424E2300UL))
+#define bFM3_ADC1_PFNS_PFS1                    *((volatile unsigned int*)(0x424E2304UL))
+#define bFM3_ADC1_PFNS_TEST0                   *((volatile unsigned int*)(0x424E2310UL))
+#define bFM3_ADC1_PFNS_TEST1                   *((volatile unsigned int*)(0x424E2314UL))
+#define bFM3_ADC1_PCCR_PSTR                    *((volatile unsigned int*)(0x424E2320UL))
+#define bFM3_ADC1_PCCR_PHEN                    *((volatile unsigned int*)(0x424E2324UL))
+#define bFM3_ADC1_PCCR_PEEN                    *((volatile unsigned int*)(0x424E2328UL))
+#define bFM3_ADC1_PCCR_ESCE                    *((volatile unsigned int*)(0x424E232CUL))
+#define bFM3_ADC1_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E2330UL))
+#define bFM3_ADC1_PCCR_POVR                    *((volatile unsigned int*)(0x424E2334UL))
+#define bFM3_ADC1_PCCR_PFUL                    *((volatile unsigned int*)(0x424E2338UL))
+#define bFM3_ADC1_PCCR_PEMP                    *((volatile unsigned int*)(0x424E233CUL))
+#define bFM3_ADC1_PCFD_PC0                     *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFD_PC1                     *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFD_PC2                     *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFD_PC3                     *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFD_PC4                     *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFD_RS0                     *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFD_RS1                     *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFD_RS2                     *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFD_INVL                    *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFD_PD0                     *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFD_PD1                     *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFD_PD2                     *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFD_PD3                     *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFD_PD4                     *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFD_PD5                     *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFD_PD6                     *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFD_PD7                     *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFD_PD8                     *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFD_PD9                     *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFD_PD10                    *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFD_PD11                    *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCFDL_PC0                    *((volatile unsigned int*)(0x424E2380UL))
+#define bFM3_ADC1_PCFDL_PC1                    *((volatile unsigned int*)(0x424E2384UL))
+#define bFM3_ADC1_PCFDL_PC2                    *((volatile unsigned int*)(0x424E2388UL))
+#define bFM3_ADC1_PCFDL_PC3                    *((volatile unsigned int*)(0x424E238CUL))
+#define bFM3_ADC1_PCFDL_PC4                    *((volatile unsigned int*)(0x424E2390UL))
+#define bFM3_ADC1_PCFDL_RS0                    *((volatile unsigned int*)(0x424E23A0UL))
+#define bFM3_ADC1_PCFDL_RS1                    *((volatile unsigned int*)(0x424E23A4UL))
+#define bFM3_ADC1_PCFDL_RS2                    *((volatile unsigned int*)(0x424E23A8UL))
+#define bFM3_ADC1_PCFDL_INVL                   *((volatile unsigned int*)(0x424E23B0UL))
+#define bFM3_ADC1_PCFDH_PD0                    *((volatile unsigned int*)(0x424E23D0UL))
+#define bFM3_ADC1_PCFDH_PD1                    *((volatile unsigned int*)(0x424E23D4UL))
+#define bFM3_ADC1_PCFDH_PD2                    *((volatile unsigned int*)(0x424E23D8UL))
+#define bFM3_ADC1_PCFDH_PD3                    *((volatile unsigned int*)(0x424E23DCUL))
+#define bFM3_ADC1_PCFDH_PD4                    *((volatile unsigned int*)(0x424E23E0UL))
+#define bFM3_ADC1_PCFDH_PD5                    *((volatile unsigned int*)(0x424E23E4UL))
+#define bFM3_ADC1_PCFDH_PD6                    *((volatile unsigned int*)(0x424E23E8UL))
+#define bFM3_ADC1_PCFDH_PD7                    *((volatile unsigned int*)(0x424E23ECUL))
+#define bFM3_ADC1_PCFDH_PD8                    *((volatile unsigned int*)(0x424E23F0UL))
+#define bFM3_ADC1_PCFDH_PD9                    *((volatile unsigned int*)(0x424E23F4UL))
+#define bFM3_ADC1_PCFDH_PD10                   *((volatile unsigned int*)(0x424E23F8UL))
+#define bFM3_ADC1_PCFDH_PD11                   *((volatile unsigned int*)(0x424E23FCUL))
+#define bFM3_ADC1_PCIS_P1A0                    *((volatile unsigned int*)(0x424E2400UL))
+#define bFM3_ADC1_PCIS_P1A1                    *((volatile unsigned int*)(0x424E2404UL))
+#define bFM3_ADC1_PCIS_P1A2                    *((volatile unsigned int*)(0x424E2408UL))
+#define bFM3_ADC1_PCIS_P2A0                    *((volatile unsigned int*)(0x424E240CUL))
+#define bFM3_ADC1_PCIS_P2A1                    *((volatile unsigned int*)(0x424E2410UL))
+#define bFM3_ADC1_PCIS_P2A2                    *((volatile unsigned int*)(0x424E2414UL))
+#define bFM3_ADC1_PCIS_P2A3                    *((volatile unsigned int*)(0x424E2418UL))
+#define bFM3_ADC1_PCIS_P2A4                    *((volatile unsigned int*)(0x424E241CUL))
+#define bFM3_ADC1_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E2480UL))
+#define bFM3_ADC1_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E2484UL))
+#define bFM3_ADC1_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E2488UL))
+#define bFM3_ADC1_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E248CUL))
+#define bFM3_ADC1_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E2490UL))
+#define bFM3_ADC1_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E2494UL))
+#define bFM3_ADC1_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E2498UL))
+#define bFM3_ADC1_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E249CUL))
+#define bFM3_ADC1_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E24D8UL))
+#define bFM3_ADC1_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E24DCUL))
+#define bFM3_ADC1_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E24E0UL))
+#define bFM3_ADC1_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E24E4UL))
+#define bFM3_ADC1_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E24E8UL))
+#define bFM3_ADC1_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E24ECUL))
+#define bFM3_ADC1_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E24F0UL))
+#define bFM3_ADC1_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E24F4UL))
+#define bFM3_ADC1_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E24F8UL))
+#define bFM3_ADC1_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E24FCUL))
+#define bFM3_ADC1_ADSS23_TS16                  *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS23_TS17                  *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS23_TS18                  *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS23_TS19                  *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS23_TS20                  *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS23_TS21                  *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS23_TS22                  *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS23_TS23                  *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS23_TS24                  *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS23_TS25                  *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS23_TS26                  *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS23_TS27                  *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS23_TS28                  *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS23_TS29                  *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS23_TS30                  *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS23_TS31                  *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS2_TS16                   *((volatile unsigned int*)(0x424E2500UL))
+#define bFM3_ADC1_ADSS2_TS17                   *((volatile unsigned int*)(0x424E2504UL))
+#define bFM3_ADC1_ADSS2_TS18                   *((volatile unsigned int*)(0x424E2508UL))
+#define bFM3_ADC1_ADSS2_TS19                   *((volatile unsigned int*)(0x424E250CUL))
+#define bFM3_ADC1_ADSS2_TS20                   *((volatile unsigned int*)(0x424E2510UL))
+#define bFM3_ADC1_ADSS2_TS21                   *((volatile unsigned int*)(0x424E2514UL))
+#define bFM3_ADC1_ADSS2_TS22                   *((volatile unsigned int*)(0x424E2518UL))
+#define bFM3_ADC1_ADSS2_TS23                   *((volatile unsigned int*)(0x424E251CUL))
+#define bFM3_ADC1_ADSS3_TS24                   *((volatile unsigned int*)(0x424E2520UL))
+#define bFM3_ADC1_ADSS3_TS25                   *((volatile unsigned int*)(0x424E2524UL))
+#define bFM3_ADC1_ADSS3_TS26                   *((volatile unsigned int*)(0x424E2528UL))
+#define bFM3_ADC1_ADSS3_TS27                   *((volatile unsigned int*)(0x424E252CUL))
+#define bFM3_ADC1_ADSS3_TS28                   *((volatile unsigned int*)(0x424E2530UL))
+#define bFM3_ADC1_ADSS3_TS29                   *((volatile unsigned int*)(0x424E2534UL))
+#define bFM3_ADC1_ADSS3_TS30                   *((volatile unsigned int*)(0x424E2538UL))
+#define bFM3_ADC1_ADSS3_TS31                   *((volatile unsigned int*)(0x424E253CUL))
+#define bFM3_ADC1_ADSS01_TS0                   *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS01_TS1                   *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS01_TS2                   *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS01_TS3                   *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS01_TS4                   *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS01_TS5                   *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS01_TS6                   *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS01_TS7                   *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS01_TS8                   *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS01_TS9                   *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS01_TS10                  *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS01_TS11                  *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS01_TS12                  *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS01_TS13                  *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS01_TS14                  *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS01_TS15                  *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADSS0_TS0                    *((volatile unsigned int*)(0x424E2580UL))
+#define bFM3_ADC1_ADSS0_TS1                    *((volatile unsigned int*)(0x424E2584UL))
+#define bFM3_ADC1_ADSS0_TS2                    *((volatile unsigned int*)(0x424E2588UL))
+#define bFM3_ADC1_ADSS0_TS3                    *((volatile unsigned int*)(0x424E258CUL))
+#define bFM3_ADC1_ADSS0_TS4                    *((volatile unsigned int*)(0x424E2590UL))
+#define bFM3_ADC1_ADSS0_TS5                    *((volatile unsigned int*)(0x424E2594UL))
+#define bFM3_ADC1_ADSS0_TS6                    *((volatile unsigned int*)(0x424E2598UL))
+#define bFM3_ADC1_ADSS0_TS7                    *((volatile unsigned int*)(0x424E259CUL))
+#define bFM3_ADC1_ADSS1_TS8                    *((volatile unsigned int*)(0x424E25A0UL))
+#define bFM3_ADC1_ADSS1_TS9                    *((volatile unsigned int*)(0x424E25A4UL))
+#define bFM3_ADC1_ADSS1_TS10                   *((volatile unsigned int*)(0x424E25A8UL))
+#define bFM3_ADC1_ADSS1_TS11                   *((volatile unsigned int*)(0x424E25ACUL))
+#define bFM3_ADC1_ADSS1_TS12                   *((volatile unsigned int*)(0x424E25B0UL))
+#define bFM3_ADC1_ADSS1_TS13                   *((volatile unsigned int*)(0x424E25B4UL))
+#define bFM3_ADC1_ADSS1_TS14                   *((volatile unsigned int*)(0x424E25B8UL))
+#define bFM3_ADC1_ADSS1_TS15                   *((volatile unsigned int*)(0x424E25BCUL))
+#define bFM3_ADC1_ADST01_ST10                  *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST01_ST11                  *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST01_ST12                  *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST01_ST13                  *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST01_ST14                  *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST01_STX10                 *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST01_STX11                 *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST01_STX12                 *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST01_ST00                  *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST01_ST01                  *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST01_ST02                  *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST01_ST03                  *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST01_ST04                  *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST01_STX00                 *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST01_STX01                 *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST01_STX02                 *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADST1_ST10                   *((volatile unsigned int*)(0x424E2600UL))
+#define bFM3_ADC1_ADST1_ST11                   *((volatile unsigned int*)(0x424E2604UL))
+#define bFM3_ADC1_ADST1_ST12                   *((volatile unsigned int*)(0x424E2608UL))
+#define bFM3_ADC1_ADST1_ST13                   *((volatile unsigned int*)(0x424E260CUL))
+#define bFM3_ADC1_ADST1_ST14                   *((volatile unsigned int*)(0x424E2610UL))
+#define bFM3_ADC1_ADST1_STX10                  *((volatile unsigned int*)(0x424E2614UL))
+#define bFM3_ADC1_ADST1_STX11                  *((volatile unsigned int*)(0x424E2618UL))
+#define bFM3_ADC1_ADST1_STX12                  *((volatile unsigned int*)(0x424E261CUL))
+#define bFM3_ADC1_ADST0_ST00                   *((volatile unsigned int*)(0x424E2620UL))
+#define bFM3_ADC1_ADST0_ST01                   *((volatile unsigned int*)(0x424E2624UL))
+#define bFM3_ADC1_ADST0_ST02                   *((volatile unsigned int*)(0x424E2628UL))
+#define bFM3_ADC1_ADST0_ST03                   *((volatile unsigned int*)(0x424E262CUL))
+#define bFM3_ADC1_ADST0_ST04                   *((volatile unsigned int*)(0x424E2630UL))
+#define bFM3_ADC1_ADST0_STX00                  *((volatile unsigned int*)(0x424E2634UL))
+#define bFM3_ADC1_ADST0_STX01                  *((volatile unsigned int*)(0x424E2638UL))
+#define bFM3_ADC1_ADST0_STX02                  *((volatile unsigned int*)(0x424E263CUL))
+#define bFM3_ADC1_ADCT_CT0                     *((volatile unsigned int*)(0x424E2680UL))
+#define bFM3_ADC1_ADCT_CT1                     *((volatile unsigned int*)(0x424E2684UL))
+#define bFM3_ADC1_ADCT_CT2                     *((volatile unsigned int*)(0x424E2688UL))
+#define bFM3_ADC1_ADCT_CT3                     *((volatile unsigned int*)(0x424E268CUL))
+#define bFM3_ADC1_ADCT_CT4                     *((volatile unsigned int*)(0x424E2690UL))
+#define bFM3_ADC1_ADCT_CT5                     *((volatile unsigned int*)(0x424E2694UL))
+#define bFM3_ADC1_ADCT_CT6                     *((volatile unsigned int*)(0x424E2698UL))
+#define bFM3_ADC1_ADCT_CT7                     *((volatile unsigned int*)(0x424E269CUL))
+#define bFM3_ADC1_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E2700UL))
+#define bFM3_ADC1_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E2704UL))
+#define bFM3_ADC1_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E2708UL))
+#define bFM3_ADC1_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E270CUL))
+#define bFM3_ADC1_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E2720UL))
+#define bFM3_ADC1_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E2724UL))
+#define bFM3_ADC1_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E2728UL))
+#define bFM3_ADC1_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E272CUL))
+#define bFM3_ADC1_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E2780UL))
+#define bFM3_ADC1_ADCEN_READY                  *((volatile unsigned int*)(0x424E2784UL))
+#define bFM3_ADC1_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E2790UL))
+#define bFM3_ADC1_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E2794UL))
+
+/* 12-bit ADC unit 2 registers */
+#define bFM3_ADC2_ADSR_SCS                     *((volatile unsigned int*)(0x424E4000UL))
+#define bFM3_ADC2_ADSR_PCS                     *((volatile unsigned int*)(0x424E4004UL))
+#define bFM3_ADC2_ADSR_PCNS                    *((volatile unsigned int*)(0x424E4008UL))
+#define bFM3_ADC2_ADSR_FDAS                    *((volatile unsigned int*)(0x424E4018UL))
+#define bFM3_ADC2_ADSR_ADSTP                   *((volatile unsigned int*)(0x424E401CUL))
+#define bFM3_ADC2_ADCR_OVRIE                   *((volatile unsigned int*)(0x424E4020UL))
+#define bFM3_ADC2_ADCR_CMPIE                   *((volatile unsigned int*)(0x424E4024UL))
+#define bFM3_ADC2_ADCR_PCIE                    *((volatile unsigned int*)(0x424E4028UL))
+#define bFM3_ADC2_ADCR_SCIE                    *((volatile unsigned int*)(0x424E402CUL))
+#define bFM3_ADC2_ADCR_CMPIF                   *((volatile unsigned int*)(0x424E4034UL))
+#define bFM3_ADC2_ADCR_PCIF                    *((volatile unsigned int*)(0x424E4038UL))
+#define bFM3_ADC2_ADCR_SCIF                    *((volatile unsigned int*)(0x424E403CUL))
+#define bFM3_ADC2_SFNS_SFS0                    *((volatile unsigned int*)(0x424E4100UL))
+#define bFM3_ADC2_SFNS_SFS1                    *((volatile unsigned int*)(0x424E4104UL))
+#define bFM3_ADC2_SFNS_SFS2                    *((volatile unsigned int*)(0x424E4108UL))
+#define bFM3_ADC2_SFNS_SFS3                    *((volatile unsigned int*)(0x424E410CUL))
+#define bFM3_ADC2_SCCR_SSTR                    *((volatile unsigned int*)(0x424E4120UL))
+#define bFM3_ADC2_SCCR_SHEN                    *((volatile unsigned int*)(0x424E4124UL))
+#define bFM3_ADC2_SCCR_RPT                     *((volatile unsigned int*)(0x424E4128UL))
+#define bFM3_ADC2_SCCR_SFCLR                   *((volatile unsigned int*)(0x424E4130UL))
+#define bFM3_ADC2_SCCR_SOVR                    *((volatile unsigned int*)(0x424E4134UL))
+#define bFM3_ADC2_SCCR_SFUL                    *((volatile unsigned int*)(0x424E4138UL))
+#define bFM3_ADC2_SCCR_SEMP                    *((volatile unsigned int*)(0x424E413CUL))
+#define bFM3_ADC2_SCFD_SC0                     *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFD_SC1                     *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFD_SC2                     *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFD_SC3                     *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFD_SC4                     *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFD_RS0                     *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFD_RS1                     *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFD_INVL                    *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFD_SD0                     *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFD_SD1                     *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFD_SD2                     *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFD_SD3                     *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFD_SD4                     *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFD_SD5                     *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFD_SD6                     *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFD_SD7                     *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFD_SD8                     *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFD_SD9                     *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFD_SD10                    *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFD_SD11                    *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCFDL_SC0                    *((volatile unsigned int*)(0x424E4180UL))
+#define bFM3_ADC2_SCFDL_SC1                    *((volatile unsigned int*)(0x424E4184UL))
+#define bFM3_ADC2_SCFDL_SC2                    *((volatile unsigned int*)(0x424E4188UL))
+#define bFM3_ADC2_SCFDL_SC3                    *((volatile unsigned int*)(0x424E418CUL))
+#define bFM3_ADC2_SCFDL_SC4                    *((volatile unsigned int*)(0x424E4190UL))
+#define bFM3_ADC2_SCFDL_RS0                    *((volatile unsigned int*)(0x424E41A0UL))
+#define bFM3_ADC2_SCFDL_RS1                    *((volatile unsigned int*)(0x424E41A4UL))
+#define bFM3_ADC2_SCFDL_INVL                   *((volatile unsigned int*)(0x424E41B0UL))
+#define bFM3_ADC2_SCFDH_SD0                    *((volatile unsigned int*)(0x424E41D0UL))
+#define bFM3_ADC2_SCFDH_SD1                    *((volatile unsigned int*)(0x424E41D4UL))
+#define bFM3_ADC2_SCFDH_SD2                    *((volatile unsigned int*)(0x424E41D8UL))
+#define bFM3_ADC2_SCFDH_SD3                    *((volatile unsigned int*)(0x424E41DCUL))
+#define bFM3_ADC2_SCFDH_SD4                    *((volatile unsigned int*)(0x424E41E0UL))
+#define bFM3_ADC2_SCFDH_SD5                    *((volatile unsigned int*)(0x424E41E4UL))
+#define bFM3_ADC2_SCFDH_SD6                    *((volatile unsigned int*)(0x424E41E8UL))
+#define bFM3_ADC2_SCFDH_SD7                    *((volatile unsigned int*)(0x424E41ECUL))
+#define bFM3_ADC2_SCFDH_SD8                    *((volatile unsigned int*)(0x424E41F0UL))
+#define bFM3_ADC2_SCFDH_SD9                    *((volatile unsigned int*)(0x424E41F4UL))
+#define bFM3_ADC2_SCFDH_SD10                   *((volatile unsigned int*)(0x424E41F8UL))
+#define bFM3_ADC2_SCFDH_SD11                   *((volatile unsigned int*)(0x424E41FCUL))
+#define bFM3_ADC2_SCIS23_AN16                  *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS23_AN17                  *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS23_AN18                  *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS23_AN19                  *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS23_AN20                  *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS23_AN21                  *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS23_AN22                  *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS23_AN23                  *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS23_AN24                  *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS23_AN25                  *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS23_AN26                  *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS23_AN27                  *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS23_AN28                  *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS23_AN29                  *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS23_AN30                  *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS23_AN31                  *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS2_AN16                   *((volatile unsigned int*)(0x424E4200UL))
+#define bFM3_ADC2_SCIS2_AN17                   *((volatile unsigned int*)(0x424E4204UL))
+#define bFM3_ADC2_SCIS2_AN18                   *((volatile unsigned int*)(0x424E4208UL))
+#define bFM3_ADC2_SCIS2_AN19                   *((volatile unsigned int*)(0x424E420CUL))
+#define bFM3_ADC2_SCIS2_AN20                   *((volatile unsigned int*)(0x424E4210UL))
+#define bFM3_ADC2_SCIS2_AN21                   *((volatile unsigned int*)(0x424E4214UL))
+#define bFM3_ADC2_SCIS2_AN22                   *((volatile unsigned int*)(0x424E4218UL))
+#define bFM3_ADC2_SCIS2_AN23                   *((volatile unsigned int*)(0x424E421CUL))
+#define bFM3_ADC2_SCIS3_AN24                   *((volatile unsigned int*)(0x424E4220UL))
+#define bFM3_ADC2_SCIS3_AN25                   *((volatile unsigned int*)(0x424E4224UL))
+#define bFM3_ADC2_SCIS3_AN26                   *((volatile unsigned int*)(0x424E4228UL))
+#define bFM3_ADC2_SCIS3_AN27                   *((volatile unsigned int*)(0x424E422CUL))
+#define bFM3_ADC2_SCIS3_AN28                   *((volatile unsigned int*)(0x424E4230UL))
+#define bFM3_ADC2_SCIS3_AN29                   *((volatile unsigned int*)(0x424E4234UL))
+#define bFM3_ADC2_SCIS3_AN30                   *((volatile unsigned int*)(0x424E4238UL))
+#define bFM3_ADC2_SCIS3_AN31                   *((volatile unsigned int*)(0x424E423CUL))
+#define bFM3_ADC2_SCIS01_AN0                   *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS01_AN1                   *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS01_AN2                   *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS01_AN3                   *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS01_AN4                   *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS01_AN5                   *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS01_AN6                   *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS01_AN7                   *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS01_AN8                   *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS01_AN9                   *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS01_AN10                  *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS01_AN11                  *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS01_AN12                  *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS01_AN13                  *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS01_AN14                  *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS01_AN15                  *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_SCIS0_AN0                    *((volatile unsigned int*)(0x424E4280UL))
+#define bFM3_ADC2_SCIS0_AN1                    *((volatile unsigned int*)(0x424E4284UL))
+#define bFM3_ADC2_SCIS0_AN2                    *((volatile unsigned int*)(0x424E4288UL))
+#define bFM3_ADC2_SCIS0_AN3                    *((volatile unsigned int*)(0x424E428CUL))
+#define bFM3_ADC2_SCIS0_AN4                    *((volatile unsigned int*)(0x424E4290UL))
+#define bFM3_ADC2_SCIS0_AN5                    *((volatile unsigned int*)(0x424E4294UL))
+#define bFM3_ADC2_SCIS0_AN6                    *((volatile unsigned int*)(0x424E4298UL))
+#define bFM3_ADC2_SCIS0_AN7                    *((volatile unsigned int*)(0x424E429CUL))
+#define bFM3_ADC2_SCIS1_AN8                    *((volatile unsigned int*)(0x424E42A0UL))
+#define bFM3_ADC2_SCIS1_AN9                    *((volatile unsigned int*)(0x424E42A4UL))
+#define bFM3_ADC2_SCIS1_AN10                   *((volatile unsigned int*)(0x424E42A8UL))
+#define bFM3_ADC2_SCIS1_AN11                   *((volatile unsigned int*)(0x424E42ACUL))
+#define bFM3_ADC2_SCIS1_AN12                   *((volatile unsigned int*)(0x424E42B0UL))
+#define bFM3_ADC2_SCIS1_AN13                   *((volatile unsigned int*)(0x424E42B4UL))
+#define bFM3_ADC2_SCIS1_AN14                   *((volatile unsigned int*)(0x424E42B8UL))
+#define bFM3_ADC2_SCIS1_AN15                   *((volatile unsigned int*)(0x424E42BCUL))
+#define bFM3_ADC2_PFNS_PFS0                    *((volatile unsigned int*)(0x424E4300UL))
+#define bFM3_ADC2_PFNS_PFS1                    *((volatile unsigned int*)(0x424E4304UL))
+#define bFM3_ADC2_PFNS_TEST0                   *((volatile unsigned int*)(0x424E4310UL))
+#define bFM3_ADC2_PFNS_TEST1                   *((volatile unsigned int*)(0x424E4314UL))
+#define bFM3_ADC2_PCCR_PSTR                    *((volatile unsigned int*)(0x424E4320UL))
+#define bFM3_ADC2_PCCR_PHEN                    *((volatile unsigned int*)(0x424E4324UL))
+#define bFM3_ADC2_PCCR_PEEN                    *((volatile unsigned int*)(0x424E4328UL))
+#define bFM3_ADC2_PCCR_ESCE                    *((volatile unsigned int*)(0x424E432CUL))
+#define bFM3_ADC2_PCCR_PFCLR                   *((volatile unsigned int*)(0x424E4330UL))
+#define bFM3_ADC2_PCCR_POVR                    *((volatile unsigned int*)(0x424E4334UL))
+#define bFM3_ADC2_PCCR_PFUL                    *((volatile unsigned int*)(0x424E4338UL))
+#define bFM3_ADC2_PCCR_PEMP                    *((volatile unsigned int*)(0x424E433CUL))
+#define bFM3_ADC2_PCFD_PC0                     *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFD_PC1                     *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFD_PC2                     *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFD_PC3                     *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFD_PC4                     *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFD_RS0                     *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFD_RS1                     *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFD_RS2                     *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFD_INVL                    *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFD_PD0                     *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFD_PD1                     *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFD_PD2                     *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFD_PD3                     *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFD_PD4                     *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFD_PD5                     *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFD_PD6                     *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFD_PD7                     *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFD_PD8                     *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFD_PD9                     *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFD_PD10                    *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFD_PD11                    *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCFDL_PC0                    *((volatile unsigned int*)(0x424E4380UL))
+#define bFM3_ADC2_PCFDL_PC1                    *((volatile unsigned int*)(0x424E4384UL))
+#define bFM3_ADC2_PCFDL_PC2                    *((volatile unsigned int*)(0x424E4388UL))
+#define bFM3_ADC2_PCFDL_PC3                    *((volatile unsigned int*)(0x424E438CUL))
+#define bFM3_ADC2_PCFDL_PC4                    *((volatile unsigned int*)(0x424E4390UL))
+#define bFM3_ADC2_PCFDL_RS0                    *((volatile unsigned int*)(0x424E43A0UL))
+#define bFM3_ADC2_PCFDL_RS1                    *((volatile unsigned int*)(0x424E43A4UL))
+#define bFM3_ADC2_PCFDL_RS2                    *((volatile unsigned int*)(0x424E43A8UL))
+#define bFM3_ADC2_PCFDL_INVL                   *((volatile unsigned int*)(0x424E43B0UL))
+#define bFM3_ADC2_PCFDH_PD0                    *((volatile unsigned int*)(0x424E43D0UL))
+#define bFM3_ADC2_PCFDH_PD1                    *((volatile unsigned int*)(0x424E43D4UL))
+#define bFM3_ADC2_PCFDH_PD2                    *((volatile unsigned int*)(0x424E43D8UL))
+#define bFM3_ADC2_PCFDH_PD3                    *((volatile unsigned int*)(0x424E43DCUL))
+#define bFM3_ADC2_PCFDH_PD4                    *((volatile unsigned int*)(0x424E43E0UL))
+#define bFM3_ADC2_PCFDH_PD5                    *((volatile unsigned int*)(0x424E43E4UL))
+#define bFM3_ADC2_PCFDH_PD6                    *((volatile unsigned int*)(0x424E43E8UL))
+#define bFM3_ADC2_PCFDH_PD7                    *((volatile unsigned int*)(0x424E43ECUL))
+#define bFM3_ADC2_PCFDH_PD8                    *((volatile unsigned int*)(0x424E43F0UL))
+#define bFM3_ADC2_PCFDH_PD9                    *((volatile unsigned int*)(0x424E43F4UL))
+#define bFM3_ADC2_PCFDH_PD10                   *((volatile unsigned int*)(0x424E43F8UL))
+#define bFM3_ADC2_PCFDH_PD11                   *((volatile unsigned int*)(0x424E43FCUL))
+#define bFM3_ADC2_PCIS_P1A0                    *((volatile unsigned int*)(0x424E4400UL))
+#define bFM3_ADC2_PCIS_P1A1                    *((volatile unsigned int*)(0x424E4404UL))
+#define bFM3_ADC2_PCIS_P1A2                    *((volatile unsigned int*)(0x424E4408UL))
+#define bFM3_ADC2_PCIS_P2A0                    *((volatile unsigned int*)(0x424E440CUL))
+#define bFM3_ADC2_PCIS_P2A1                    *((volatile unsigned int*)(0x424E4410UL))
+#define bFM3_ADC2_PCIS_P2A2                    *((volatile unsigned int*)(0x424E4414UL))
+#define bFM3_ADC2_PCIS_P2A3                    *((volatile unsigned int*)(0x424E4418UL))
+#define bFM3_ADC2_PCIS_P2A4                    *((volatile unsigned int*)(0x424E441CUL))
+#define bFM3_ADC2_CMPCR_CCH0                   *((volatile unsigned int*)(0x424E4480UL))
+#define bFM3_ADC2_CMPCR_CCH1                   *((volatile unsigned int*)(0x424E4484UL))
+#define bFM3_ADC2_CMPCR_CCH2                   *((volatile unsigned int*)(0x424E4488UL))
+#define bFM3_ADC2_CMPCR_CCH3                   *((volatile unsigned int*)(0x424E448CUL))
+#define bFM3_ADC2_CMPCR_CCH4                   *((volatile unsigned int*)(0x424E4490UL))
+#define bFM3_ADC2_CMPCR_CMD0                   *((volatile unsigned int*)(0x424E4494UL))
+#define bFM3_ADC2_CMPCR_CMD1                   *((volatile unsigned int*)(0x424E4498UL))
+#define bFM3_ADC2_CMPCR_CMPEN                  *((volatile unsigned int*)(0x424E449CUL))
+#define bFM3_ADC2_CMPD_CMAD2                   *((volatile unsigned int*)(0x424E44D8UL))
+#define bFM3_ADC2_CMPD_CMAD3                   *((volatile unsigned int*)(0x424E44DCUL))
+#define bFM3_ADC2_CMPD_CMAD4                   *((volatile unsigned int*)(0x424E44E0UL))
+#define bFM3_ADC2_CMPD_CMAD5                   *((volatile unsigned int*)(0x424E44E4UL))
+#define bFM3_ADC2_CMPD_CMAD6                   *((volatile unsigned int*)(0x424E44E8UL))
+#define bFM3_ADC2_CMPD_CMAD7                   *((volatile unsigned int*)(0x424E44ECUL))
+#define bFM3_ADC2_CMPD_CMAD8                   *((volatile unsigned int*)(0x424E44F0UL))
+#define bFM3_ADC2_CMPD_CMAD9                   *((volatile unsigned int*)(0x424E44F4UL))
+#define bFM3_ADC2_CMPD_CMAD10                  *((volatile unsigned int*)(0x424E44F8UL))
+#define bFM3_ADC2_CMPD_CMAD11                  *((volatile unsigned int*)(0x424E44FCUL))
+#define bFM3_ADC2_ADSS23_TS16                  *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS23_TS17                  *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS23_TS18                  *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS23_TS19                  *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS23_TS20                  *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS23_TS21                  *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS23_TS22                  *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS23_TS23                  *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS23_TS24                  *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS23_TS25                  *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS23_TS26                  *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS23_TS27                  *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS23_TS28                  *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS23_TS29                  *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS23_TS30                  *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS23_TS31                  *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS2_TS16                   *((volatile unsigned int*)(0x424E4500UL))
+#define bFM3_ADC2_ADSS2_TS17                   *((volatile unsigned int*)(0x424E4504UL))
+#define bFM3_ADC2_ADSS2_TS18                   *((volatile unsigned int*)(0x424E4508UL))
+#define bFM3_ADC2_ADSS2_TS19                   *((volatile unsigned int*)(0x424E450CUL))
+#define bFM3_ADC2_ADSS2_TS20                   *((volatile unsigned int*)(0x424E4510UL))
+#define bFM3_ADC2_ADSS2_TS21                   *((volatile unsigned int*)(0x424E4514UL))
+#define bFM3_ADC2_ADSS2_TS22                   *((volatile unsigned int*)(0x424E4518UL))
+#define bFM3_ADC2_ADSS2_TS23                   *((volatile unsigned int*)(0x424E451CUL))
+#define bFM3_ADC2_ADSS3_TS24                   *((volatile unsigned int*)(0x424E4520UL))
+#define bFM3_ADC2_ADSS3_TS25                   *((volatile unsigned int*)(0x424E4524UL))
+#define bFM3_ADC2_ADSS3_TS26                   *((volatile unsigned int*)(0x424E4528UL))
+#define bFM3_ADC2_ADSS3_TS27                   *((volatile unsigned int*)(0x424E452CUL))
+#define bFM3_ADC2_ADSS3_TS28                   *((volatile unsigned int*)(0x424E4530UL))
+#define bFM3_ADC2_ADSS3_TS29                   *((volatile unsigned int*)(0x424E4534UL))
+#define bFM3_ADC2_ADSS3_TS30                   *((volatile unsigned int*)(0x424E4538UL))
+#define bFM3_ADC2_ADSS3_TS31                   *((volatile unsigned int*)(0x424E453CUL))
+#define bFM3_ADC2_ADSS01_TS0                   *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS01_TS1                   *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS01_TS2                   *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS01_TS3                   *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS01_TS4                   *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS01_TS5                   *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS01_TS6                   *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS01_TS7                   *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS01_TS8                   *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS01_TS9                   *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS01_TS10                  *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS01_TS11                  *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS01_TS12                  *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS01_TS13                  *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS01_TS14                  *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS01_TS15                  *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADSS0_TS0                    *((volatile unsigned int*)(0x424E4580UL))
+#define bFM3_ADC2_ADSS0_TS1                    *((volatile unsigned int*)(0x424E4584UL))
+#define bFM3_ADC2_ADSS0_TS2                    *((volatile unsigned int*)(0x424E4588UL))
+#define bFM3_ADC2_ADSS0_TS3                    *((volatile unsigned int*)(0x424E458CUL))
+#define bFM3_ADC2_ADSS0_TS4                    *((volatile unsigned int*)(0x424E4590UL))
+#define bFM3_ADC2_ADSS0_TS5                    *((volatile unsigned int*)(0x424E4594UL))
+#define bFM3_ADC2_ADSS0_TS6                    *((volatile unsigned int*)(0x424E4598UL))
+#define bFM3_ADC2_ADSS0_TS7                    *((volatile unsigned int*)(0x424E459CUL))
+#define bFM3_ADC2_ADSS1_TS8                    *((volatile unsigned int*)(0x424E45A0UL))
+#define bFM3_ADC2_ADSS1_TS9                    *((volatile unsigned int*)(0x424E45A4UL))
+#define bFM3_ADC2_ADSS1_TS10                   *((volatile unsigned int*)(0x424E45A8UL))
+#define bFM3_ADC2_ADSS1_TS11                   *((volatile unsigned int*)(0x424E45ACUL))
+#define bFM3_ADC2_ADSS1_TS12                   *((volatile unsigned int*)(0x424E45B0UL))
+#define bFM3_ADC2_ADSS1_TS13                   *((volatile unsigned int*)(0x424E45B4UL))
+#define bFM3_ADC2_ADSS1_TS14                   *((volatile unsigned int*)(0x424E45B8UL))
+#define bFM3_ADC2_ADSS1_TS15                   *((volatile unsigned int*)(0x424E45BCUL))
+#define bFM3_ADC2_ADST01_ST10                  *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST01_ST11                  *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST01_ST12                  *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST01_ST13                  *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST01_ST14                  *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST01_STX10                 *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST01_STX11                 *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST01_STX12                 *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST01_ST00                  *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST01_ST01                  *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST01_ST02                  *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST01_ST03                  *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST01_ST04                  *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST01_STX00                 *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST01_STX01                 *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST01_STX02                 *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADST1_ST10                   *((volatile unsigned int*)(0x424E4600UL))
+#define bFM3_ADC2_ADST1_ST11                   *((volatile unsigned int*)(0x424E4604UL))
+#define bFM3_ADC2_ADST1_ST12                   *((volatile unsigned int*)(0x424E4608UL))
+#define bFM3_ADC2_ADST1_ST13                   *((volatile unsigned int*)(0x424E460CUL))
+#define bFM3_ADC2_ADST1_ST14                   *((volatile unsigned int*)(0x424E4610UL))
+#define bFM3_ADC2_ADST1_STX10                  *((volatile unsigned int*)(0x424E4614UL))
+#define bFM3_ADC2_ADST1_STX11                  *((volatile unsigned int*)(0x424E4618UL))
+#define bFM3_ADC2_ADST1_STX12                  *((volatile unsigned int*)(0x424E461CUL))
+#define bFM3_ADC2_ADST0_ST00                   *((volatile unsigned int*)(0x424E4620UL))
+#define bFM3_ADC2_ADST0_ST01                   *((volatile unsigned int*)(0x424E4624UL))
+#define bFM3_ADC2_ADST0_ST02                   *((volatile unsigned int*)(0x424E4628UL))
+#define bFM3_ADC2_ADST0_ST03                   *((volatile unsigned int*)(0x424E462CUL))
+#define bFM3_ADC2_ADST0_ST04                   *((volatile unsigned int*)(0x424E4630UL))
+#define bFM3_ADC2_ADST0_STX00                  *((volatile unsigned int*)(0x424E4634UL))
+#define bFM3_ADC2_ADST0_STX01                  *((volatile unsigned int*)(0x424E4638UL))
+#define bFM3_ADC2_ADST0_STX02                  *((volatile unsigned int*)(0x424E463CUL))
+#define bFM3_ADC2_ADCT_CT0                     *((volatile unsigned int*)(0x424E4680UL))
+#define bFM3_ADC2_ADCT_CT1                     *((volatile unsigned int*)(0x424E4684UL))
+#define bFM3_ADC2_ADCT_CT2                     *((volatile unsigned int*)(0x424E4688UL))
+#define bFM3_ADC2_ADCT_CT3                     *((volatile unsigned int*)(0x424E468CUL))
+#define bFM3_ADC2_ADCT_CT4                     *((volatile unsigned int*)(0x424E4690UL))
+#define bFM3_ADC2_ADCT_CT5                     *((volatile unsigned int*)(0x424E4694UL))
+#define bFM3_ADC2_ADCT_CT6                     *((volatile unsigned int*)(0x424E4698UL))
+#define bFM3_ADC2_ADCT_CT7                     *((volatile unsigned int*)(0x424E469CUL))
+#define bFM3_ADC2_PRTSL_PRTSL0                 *((volatile unsigned int*)(0x424E4700UL))
+#define bFM3_ADC2_PRTSL_PRTSL1                 *((volatile unsigned int*)(0x424E4704UL))
+#define bFM3_ADC2_PRTSL_PRTSL2                 *((volatile unsigned int*)(0x424E4708UL))
+#define bFM3_ADC2_PRTSL_PRTSL3                 *((volatile unsigned int*)(0x424E470CUL))
+#define bFM3_ADC2_SCTSL_SCTSL0                 *((volatile unsigned int*)(0x424E4720UL))
+#define bFM3_ADC2_SCTSL_SCTSL1                 *((volatile unsigned int*)(0x424E4724UL))
+#define bFM3_ADC2_SCTSL_SCTSL2                 *((volatile unsigned int*)(0x424E4728UL))
+#define bFM3_ADC2_SCTSL_SCTSL3                 *((volatile unsigned int*)(0x424E472CUL))
+#define bFM3_ADC2_ADCEN_ENBL                   *((volatile unsigned int*)(0x424E4780UL))
+#define bFM3_ADC2_ADCEN_READY                  *((volatile unsigned int*)(0x424E4784UL))
+#define bFM3_ADC2_ADCEN_CYCLSL0                *((volatile unsigned int*)(0x424E4790UL))
+#define bFM3_ADC2_ADCEN_CYCLSL1                *((volatile unsigned int*)(0x424E4794UL))
+
+/* CR trimming registers */
+#define bFM3_CRTRIM_MCR_PSR_CSR0               *((volatile unsigned int*)(0x425C0000UL))
+#define bFM3_CRTRIM_MCR_PSR_CSR1               *((volatile unsigned int*)(0x425C0004UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD0              *((volatile unsigned int*)(0x425C0080UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD1              *((volatile unsigned int*)(0x425C0084UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD2              *((volatile unsigned int*)(0x425C0088UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD3              *((volatile unsigned int*)(0x425C008CUL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD4              *((volatile unsigned int*)(0x425C0090UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD5              *((volatile unsigned int*)(0x425C0094UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD6              *((volatile unsigned int*)(0x425C0098UL))
+#define bFM3_CRTRIM_MCR_FTRM_TRD7              *((volatile unsigned int*)(0x425C009CUL))
+
+/* External interrupt registers */
+#define bFM3_EXTI_ENIR_EN0                     *((volatile unsigned int*)(0x42600000UL))
+#define bFM3_EXTI_ENIR_EN1                     *((volatile unsigned int*)(0x42600004UL))
+#define bFM3_EXTI_ENIR_EN2                     *((volatile unsigned int*)(0x42600008UL))
+#define bFM3_EXTI_ENIR_EN3                     *((volatile unsigned int*)(0x4260000CUL))
+#define bFM3_EXTI_ENIR_EN4                     *((volatile unsigned int*)(0x42600010UL))
+#define bFM3_EXTI_ENIR_EN5                     *((volatile unsigned int*)(0x42600014UL))
+#define bFM3_EXTI_ENIR_EN6                     *((volatile unsigned int*)(0x42600018UL))
+#define bFM3_EXTI_ENIR_EN7                     *((volatile unsigned int*)(0x4260001CUL))
+#define bFM3_EXTI_ENIR_EN8                     *((volatile unsigned int*)(0x42600020UL))
+#define bFM3_EXTI_ENIR_EN9                     *((volatile unsigned int*)(0x42600024UL))
+#define bFM3_EXTI_ENIR_EN10                    *((volatile unsigned int*)(0x42600028UL))
+#define bFM3_EXTI_ENIR_EN11                    *((volatile unsigned int*)(0x4260002CUL))
+#define bFM3_EXTI_ENIR_EN12                    *((volatile unsigned int*)(0x42600030UL))
+#define bFM3_EXTI_ENIR_EN13                    *((volatile unsigned int*)(0x42600034UL))
+#define bFM3_EXTI_ENIR_EN14                    *((volatile unsigned int*)(0x42600038UL))
+#define bFM3_EXTI_ENIR_EN15                    *((volatile unsigned int*)(0x4260003CUL))
+#define bFM3_EXTI_ENIR_EN16                    *((volatile unsigned int*)(0x42600040UL))
+#define bFM3_EXTI_ENIR_EN17                    *((volatile unsigned int*)(0x42600044UL))
+#define bFM3_EXTI_ENIR_EN18                    *((volatile unsigned int*)(0x42600048UL))
+#define bFM3_EXTI_ENIR_EN19                    *((volatile unsigned int*)(0x4260004CUL))
+#define bFM3_EXTI_ENIR_EN20                    *((volatile unsigned int*)(0x42600050UL))
+#define bFM3_EXTI_ENIR_EN21                    *((volatile unsigned int*)(0x42600054UL))
+#define bFM3_EXTI_ENIR_EN22                    *((volatile unsigned int*)(0x42600058UL))
+#define bFM3_EXTI_ENIR_EN23                    *((volatile unsigned int*)(0x4260005CUL))
+#define bFM3_EXTI_ENIR_EN24                    *((volatile unsigned int*)(0x42600060UL))
+#define bFM3_EXTI_ENIR_EN25                    *((volatile unsigned int*)(0x42600064UL))
+#define bFM3_EXTI_ENIR_EN26                    *((volatile unsigned int*)(0x42600068UL))
+#define bFM3_EXTI_ENIR_EN27                    *((volatile unsigned int*)(0x4260006CUL))
+#define bFM3_EXTI_ENIR_EN28                    *((volatile unsigned int*)(0x42600070UL))
+#define bFM3_EXTI_ENIR_EN29                    *((volatile unsigned int*)(0x42600074UL))
+#define bFM3_EXTI_ENIR_EN30                    *((volatile unsigned int*)(0x42600078UL))
+#define bFM3_EXTI_ENIR_EN31                    *((volatile unsigned int*)(0x4260007CUL))
+#define bFM3_EXTI_EIRR_ER0                     *((volatile unsigned int*)(0x42600080UL))
+#define bFM3_EXTI_EIRR_ER1                     *((volatile unsigned int*)(0x42600084UL))
+#define bFM3_EXTI_EIRR_ER2                     *((volatile unsigned int*)(0x42600088UL))
+#define bFM3_EXTI_EIRR_ER3                     *((volatile unsigned int*)(0x4260008CUL))
+#define bFM3_EXTI_EIRR_ER4                     *((volatile unsigned int*)(0x42600090UL))
+#define bFM3_EXTI_EIRR_ER5                     *((volatile unsigned int*)(0x42600094UL))
+#define bFM3_EXTI_EIRR_ER6                     *((volatile unsigned int*)(0x42600098UL))
+#define bFM3_EXTI_EIRR_ER7                     *((volatile unsigned int*)(0x4260009CUL))
+#define bFM3_EXTI_EIRR_ER8                     *((volatile unsigned int*)(0x426000A0UL))
+#define bFM3_EXTI_EIRR_ER9                     *((volatile unsigned int*)(0x426000A4UL))
+#define bFM3_EXTI_EIRR_ER10                    *((volatile unsigned int*)(0x426000A8UL))
+#define bFM3_EXTI_EIRR_ER11                    *((volatile unsigned int*)(0x426000ACUL))
+#define bFM3_EXTI_EIRR_ER12                    *((volatile unsigned int*)(0x426000B0UL))
+#define bFM3_EXTI_EIRR_ER13                    *((volatile unsigned int*)(0x426000B4UL))
+#define bFM3_EXTI_EIRR_ER14                    *((volatile unsigned int*)(0x426000B8UL))
+#define bFM3_EXTI_EIRR_ER15                    *((volatile unsigned int*)(0x426000BCUL))
+#define bFM3_EXTI_EIRR_ER16                    *((volatile unsigned int*)(0x426000C0UL))
+#define bFM3_EXTI_EIRR_ER17                    *((volatile unsigned int*)(0x426000C4UL))
+#define bFM3_EXTI_EIRR_ER18                    *((volatile unsigned int*)(0x426000C8UL))
+#define bFM3_EXTI_EIRR_ER19                    *((volatile unsigned int*)(0x426000CCUL))
+#define bFM3_EXTI_EIRR_ER20                    *((volatile unsigned int*)(0x426000D0UL))
+#define bFM3_EXTI_EIRR_ER21                    *((volatile unsigned int*)(0x426000D4UL))
+#define bFM3_EXTI_EIRR_ER22                    *((volatile unsigned int*)(0x426000D8UL))
+#define bFM3_EXTI_EIRR_ER23                    *((volatile unsigned int*)(0x426000DCUL))
+#define bFM3_EXTI_EIRR_ER24                    *((volatile unsigned int*)(0x426000E0UL))
+#define bFM3_EXTI_EIRR_ER25                    *((volatile unsigned int*)(0x426000E4UL))
+#define bFM3_EXTI_EIRR_ER26                    *((volatile unsigned int*)(0x426000E8UL))
+#define bFM3_EXTI_EIRR_ER27                    *((volatile unsigned int*)(0x426000ECUL))
+#define bFM3_EXTI_EIRR_ER28                    *((volatile unsigned int*)(0x426000F0UL))
+#define bFM3_EXTI_EIRR_ER29                    *((volatile unsigned int*)(0x426000F4UL))
+#define bFM3_EXTI_EIRR_ER30                    *((volatile unsigned int*)(0x426000F8UL))
+#define bFM3_EXTI_EIRR_ER31                    *((volatile unsigned int*)(0x426000FCUL))
+#define bFM3_EXTI_EICL_ECL0                    *((volatile unsigned int*)(0x42600100UL))
+#define bFM3_EXTI_EICL_ECL1                    *((volatile unsigned int*)(0x42600104UL))
+#define bFM3_EXTI_EICL_ECL2                    *((volatile unsigned int*)(0x42600108UL))
+#define bFM3_EXTI_EICL_ECL3                    *((volatile unsigned int*)(0x4260010CUL))
+#define bFM3_EXTI_EICL_ECL4                    *((volatile unsigned int*)(0x42600110UL))
+#define bFM3_EXTI_EICL_ECL5                    *((volatile unsigned int*)(0x42600114UL))
+#define bFM3_EXTI_EICL_ECL6                    *((volatile unsigned int*)(0x42600118UL))
+#define bFM3_EXTI_EICL_ECL7                    *((volatile unsigned int*)(0x4260011CUL))
+#define bFM3_EXTI_EICL_ECL8                    *((volatile unsigned int*)(0x42600120UL))
+#define bFM3_EXTI_EICL_ECL9                    *((volatile unsigned int*)(0x42600124UL))
+#define bFM3_EXTI_EICL_ECL10                   *((volatile unsigned int*)(0x42600128UL))
+#define bFM3_EXTI_EICL_ECL11                   *((volatile unsigned int*)(0x4260012CUL))
+#define bFM3_EXTI_EICL_ECL12                   *((volatile unsigned int*)(0x42600130UL))
+#define bFM3_EXTI_EICL_ECL13                   *((volatile unsigned int*)(0x42600134UL))
+#define bFM3_EXTI_EICL_ECL14                   *((volatile unsigned int*)(0x42600138UL))
+#define bFM3_EXTI_EICL_ECL15                   *((volatile unsigned int*)(0x4260013CUL))
+#define bFM3_EXTI_EICL_ECL16                   *((volatile unsigned int*)(0x42600140UL))
+#define bFM3_EXTI_EICL_ECL17                   *((volatile unsigned int*)(0x42600144UL))
+#define bFM3_EXTI_EICL_ECL18                   *((volatile unsigned int*)(0x42600148UL))
+#define bFM3_EXTI_EICL_ECL19                   *((volatile unsigned int*)(0x4260014CUL))
+#define bFM3_EXTI_EICL_ECL20                   *((volatile unsigned int*)(0x42600150UL))
+#define bFM3_EXTI_EICL_ECL21                   *((volatile unsigned int*)(0x42600154UL))
+#define bFM3_EXTI_EICL_ECL22                   *((volatile unsigned int*)(0x42600158UL))
+#define bFM3_EXTI_EICL_ECL23                   *((volatile unsigned int*)(0x4260015CUL))
+#define bFM3_EXTI_EICL_ECL24                   *((volatile unsigned int*)(0x42600160UL))
+#define bFM3_EXTI_EICL_ECL25                   *((volatile unsigned int*)(0x42600164UL))
+#define bFM3_EXTI_EICL_ECL26                   *((volatile unsigned int*)(0x42600168UL))
+#define bFM3_EXTI_EICL_ECL27                   *((volatile unsigned int*)(0x4260016CUL))
+#define bFM3_EXTI_EICL_ECL28                   *((volatile unsigned int*)(0x42600170UL))
+#define bFM3_EXTI_EICL_ECL29                   *((volatile unsigned int*)(0x42600174UL))
+#define bFM3_EXTI_EICL_ECL30                   *((volatile unsigned int*)(0x42600178UL))
+#define bFM3_EXTI_EICL_ECL31                   *((volatile unsigned int*)(0x4260017CUL))
+#define bFM3_EXTI_ELVR_LA0                     *((volatile unsigned int*)(0x42600180UL))
+#define bFM3_EXTI_ELVR_LB0                     *((volatile unsigned int*)(0x42600184UL))
+#define bFM3_EXTI_ELVR_LA1                     *((volatile unsigned int*)(0x42600188UL))
+#define bFM3_EXTI_ELVR_LB1                     *((volatile unsigned int*)(0x4260018CUL))
+#define bFM3_EXTI_ELVR_LA2                     *((volatile unsigned int*)(0x42600190UL))
+#define bFM3_EXTI_ELVR_LB2                     *((volatile unsigned int*)(0x42600194UL))
+#define bFM3_EXTI_ELVR_LA3                     *((volatile unsigned int*)(0x42600198UL))
+#define bFM3_EXTI_ELVR_LB3                     *((volatile unsigned int*)(0x4260019CUL))
+#define bFM3_EXTI_ELVR_LA4                     *((volatile unsigned int*)(0x426001A0UL))
+#define bFM3_EXTI_ELVR_LB4                     *((volatile unsigned int*)(0x426001A4UL))
+#define bFM3_EXTI_ELVR_LA5                     *((volatile unsigned int*)(0x426001A8UL))
+#define bFM3_EXTI_ELVR_LB5                     *((volatile unsigned int*)(0x426001ACUL))
+#define bFM3_EXTI_ELVR_LA6                     *((volatile unsigned int*)(0x426001B0UL))
+#define bFM3_EXTI_ELVR_LB6                     *((volatile unsigned int*)(0x426001B4UL))
+#define bFM3_EXTI_ELVR_LA7                     *((volatile unsigned int*)(0x426001B8UL))
+#define bFM3_EXTI_ELVR_LB7                     *((volatile unsigned int*)(0x426001BCUL))
+#define bFM3_EXTI_ELVR_LA8                     *((volatile unsigned int*)(0x426001C0UL))
+#define bFM3_EXTI_ELVR_LB8                     *((volatile unsigned int*)(0x426001C4UL))
+#define bFM3_EXTI_ELVR_LA9                     *((volatile unsigned int*)(0x426001C8UL))
+#define bFM3_EXTI_ELVR_LB9                     *((volatile unsigned int*)(0x426001CCUL))
+#define bFM3_EXTI_ELVR_LA10                    *((volatile unsigned int*)(0x426001D0UL))
+#define bFM3_EXTI_ELVR_LB10                    *((volatile unsigned int*)(0x426001D4UL))
+#define bFM3_EXTI_ELVR_LA11                    *((volatile unsigned int*)(0x426001D8UL))
+#define bFM3_EXTI_ELVR_LB11                    *((volatile unsigned int*)(0x426001DCUL))
+#define bFM3_EXTI_ELVR_LA12                    *((volatile unsigned int*)(0x426001E0UL))
+#define bFM3_EXTI_ELVR_LB12                    *((volatile unsigned int*)(0x426001E4UL))
+#define bFM3_EXTI_ELVR_LA13                    *((volatile unsigned int*)(0x426001E8UL))
+#define bFM3_EXTI_ELVR_LB13                    *((volatile unsigned int*)(0x426001ECUL))
+#define bFM3_EXTI_ELVR_LA14                    *((volatile unsigned int*)(0x426001F0UL))
+#define bFM3_EXTI_ELVR_LB14                    *((volatile unsigned int*)(0x426001F4UL))
+#define bFM3_EXTI_ELVR_LA15                    *((volatile unsigned int*)(0x426001F8UL))
+#define bFM3_EXTI_ELVR_LB15                    *((volatile unsigned int*)(0x426001FCUL))
+#define bFM3_EXTI_ELVR_LA16                    *((volatile unsigned int*)(0x42600200UL))
+#define bFM3_EXTI_ELVR_LB16                    *((volatile unsigned int*)(0x42600204UL))
+#define bFM3_EXTI_ELVR_LA17                    *((volatile unsigned int*)(0x42600208UL))
+#define bFM3_EXTI_ELVR_LB17                    *((volatile unsigned int*)(0x4260020CUL))
+#define bFM3_EXTI_ELVR_LA18                    *((volatile unsigned int*)(0x42600210UL))
+#define bFM3_EXTI_ELVR_LB18                    *((volatile unsigned int*)(0x42600214UL))
+#define bFM3_EXTI_ELVR_LA19                    *((volatile unsigned int*)(0x42600218UL))
+#define bFM3_EXTI_ELVR_LB19                    *((volatile unsigned int*)(0x4260021CUL))
+#define bFM3_EXTI_ELVR_LA20                    *((volatile unsigned int*)(0x42600220UL))
+#define bFM3_EXTI_ELVR_LB20                    *((volatile unsigned int*)(0x42600224UL))
+#define bFM3_EXTI_ELVR_LA21                    *((volatile unsigned int*)(0x42600228UL))
+#define bFM3_EXTI_ELVR_LB21                    *((volatile unsigned int*)(0x4260022CUL))
+#define bFM3_EXTI_ELVR_LA22                    *((volatile unsigned int*)(0x42600230UL))
+#define bFM3_EXTI_ELVR_LB22                    *((volatile unsigned int*)(0x42600234UL))
+#define bFM3_EXTI_ELVR_LA23                    *((volatile unsigned int*)(0x42600238UL))
+#define bFM3_EXTI_ELVR_LB23                    *((volatile unsigned int*)(0x4260023CUL))
+#define bFM3_EXTI_ELVR_LA24                    *((volatile unsigned int*)(0x42600240UL))
+#define bFM3_EXTI_ELVR_LB24                    *((volatile unsigned int*)(0x42600244UL))
+#define bFM3_EXTI_ELVR_LA25                    *((volatile unsigned int*)(0x42600248UL))
+#define bFM3_EXTI_ELVR_LB25                    *((volatile unsigned int*)(0x4260024CUL))
+#define bFM3_EXTI_ELVR_LA26                    *((volatile unsigned int*)(0x42600250UL))
+#define bFM3_EXTI_ELVR_LB26                    *((volatile unsigned int*)(0x42600254UL))
+#define bFM3_EXTI_ELVR_LA27                    *((volatile unsigned int*)(0x42600258UL))
+#define bFM3_EXTI_ELVR_LB27                    *((volatile unsigned int*)(0x4260025CUL))
+#define bFM3_EXTI_ELVR_LA28                    *((volatile unsigned int*)(0x42600260UL))
+#define bFM3_EXTI_ELVR_LB28                    *((volatile unsigned int*)(0x42600264UL))
+#define bFM3_EXTI_ELVR_LA29                    *((volatile unsigned int*)(0x42600268UL))
+#define bFM3_EXTI_ELVR_LB29                    *((volatile unsigned int*)(0x4260026CUL))
+#define bFM3_EXTI_ELVR_LA30                    *((volatile unsigned int*)(0x42600270UL))
+#define bFM3_EXTI_ELVR_LB30                    *((volatile unsigned int*)(0x42600274UL))
+#define bFM3_EXTI_ELVR_LA31                    *((volatile unsigned int*)(0x42600278UL))
+#define bFM3_EXTI_ELVR_LB31                    *((volatile unsigned int*)(0x4260027CUL))
+#define bFM3_EXTI_NMIRR_NR0                    *((volatile unsigned int*)(0x42600280UL))
+#define bFM3_EXTI_NMICL_NCL0                   *((volatile unsigned int*)(0x42600300UL))
+
+/* Interrupt request read registers */
+#define bFM3_INTREQ_DRQSEL_DRQSEL0             *((volatile unsigned int*)(0x42620000UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL1             *((volatile unsigned int*)(0x42620004UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL2             *((volatile unsigned int*)(0x42620008UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL3             *((volatile unsigned int*)(0x4262000CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL4             *((volatile unsigned int*)(0x42620010UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL5             *((volatile unsigned int*)(0x42620014UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL6             *((volatile unsigned int*)(0x42620018UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL7             *((volatile unsigned int*)(0x4262001CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL8             *((volatile unsigned int*)(0x42620020UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL9             *((volatile unsigned int*)(0x42620024UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL10            *((volatile unsigned int*)(0x42620028UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL11            *((volatile unsigned int*)(0x4262002CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL12            *((volatile unsigned int*)(0x42620030UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL13            *((volatile unsigned int*)(0x42620034UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL14            *((volatile unsigned int*)(0x42620038UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL15            *((volatile unsigned int*)(0x4262003CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL16            *((volatile unsigned int*)(0x42620040UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL17            *((volatile unsigned int*)(0x42620044UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL18            *((volatile unsigned int*)(0x42620048UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL19            *((volatile unsigned int*)(0x4262004CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL20            *((volatile unsigned int*)(0x42620050UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL21            *((volatile unsigned int*)(0x42620054UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL22            *((volatile unsigned int*)(0x42620058UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL23            *((volatile unsigned int*)(0x4262005CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL24            *((volatile unsigned int*)(0x42620060UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL25            *((volatile unsigned int*)(0x42620064UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL26            *((volatile unsigned int*)(0x42620068UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL27            *((volatile unsigned int*)(0x4262006CUL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL28            *((volatile unsigned int*)(0x42620070UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL29            *((volatile unsigned int*)(0x42620074UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL30            *((volatile unsigned int*)(0x42620078UL))
+#define bFM3_INTREQ_DRQSEL_DRQSEL31            *((volatile unsigned int*)(0x4262007CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS0             *((volatile unsigned char*)(0x42620160UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS1             *((volatile unsigned char*)(0x42620164UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS2             *((volatile unsigned char*)(0x42620168UL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS3             *((volatile unsigned char*)(0x4262016CUL))
+#define bFM3_INTREQ_ODDPKS_ODDPKS4             *((volatile unsigned char*)(0x42620170UL))
+#define bFM3_INTREQ_EXC02MON_NMI               *((volatile unsigned int*)(0x42620200UL))
+#define bFM3_INTREQ_EXC02MON_HWINT             *((volatile unsigned int*)(0x42620204UL))
+#define bFM3_INTREQ_IRQ00MON_FCSINT            *((volatile unsigned int*)(0x42620280UL))
+#define bFM3_INTREQ_IRQ01MON_SWWDTINT          *((volatile unsigned int*)(0x42620300UL))
+#define bFM3_INTREQ_IRQ02MON_LVDINT            *((volatile unsigned int*)(0x42620380UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT0         *((volatile unsigned int*)(0x42620400UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT1         *((volatile unsigned int*)(0x42620404UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT2         *((volatile unsigned int*)(0x42620408UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE0INT3         *((volatile unsigned int*)(0x4262040CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT0         *((volatile unsigned int*)(0x42620410UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT1         *((volatile unsigned int*)(0x42620414UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT2         *((volatile unsigned int*)(0x42620418UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE1INT3         *((volatile unsigned int*)(0x4262041CUL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT0         *((volatile unsigned int*)(0x42620420UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT1         *((volatile unsigned int*)(0x42620424UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT2         *((volatile unsigned int*)(0x42620428UL))
+#define bFM3_INTREQ_IRQ03MON_WAVE2INT3         *((volatile unsigned int*)(0x4262042CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT0           *((volatile unsigned int*)(0x42620480UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT1           *((volatile unsigned int*)(0x42620484UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT2           *((volatile unsigned int*)(0x42620488UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT3           *((volatile unsigned int*)(0x4262048CUL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT4           *((volatile unsigned int*)(0x42620490UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT5           *((volatile unsigned int*)(0x42620494UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT6           *((volatile unsigned int*)(0x42620498UL))
+#define bFM3_INTREQ_IRQ04MON_EXTINT7           *((volatile unsigned int*)(0x4262049CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT0           *((volatile unsigned int*)(0x42620500UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT1           *((volatile unsigned int*)(0x42620504UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT2           *((volatile unsigned int*)(0x42620508UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT3           *((volatile unsigned int*)(0x4262050CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT4           *((volatile unsigned int*)(0x42620510UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT5           *((volatile unsigned int*)(0x42620514UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT6           *((volatile unsigned int*)(0x42620518UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT7           *((volatile unsigned int*)(0x4262051CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT8           *((volatile unsigned int*)(0x42620520UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT9           *((volatile unsigned int*)(0x42620524UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT10          *((volatile unsigned int*)(0x42620528UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT11          *((volatile unsigned int*)(0x4262052CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT12          *((volatile unsigned int*)(0x42620530UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT13          *((volatile unsigned int*)(0x42620534UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT14          *((volatile unsigned int*)(0x42620538UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT15          *((volatile unsigned int*)(0x4262053CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT16          *((volatile unsigned int*)(0x42620540UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT17          *((volatile unsigned int*)(0x42620544UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT18          *((volatile unsigned int*)(0x42620548UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT19          *((volatile unsigned int*)(0x4262054CUL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT20          *((volatile unsigned int*)(0x42620550UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT21          *((volatile unsigned int*)(0x42620554UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT22          *((volatile unsigned int*)(0x42620558UL))
+#define bFM3_INTREQ_IRQ05MON_EXTINT23          *((volatile unsigned int*)(0x4262055CUL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT1           *((volatile unsigned int*)(0x42620580UL))
+#define bFM3_INTREQ_IRQ06MON_TIMINT2           *((volatile unsigned int*)(0x42620584UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT0          *((volatile unsigned int*)(0x42620588UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT1          *((volatile unsigned int*)(0x4262058CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT2          *((volatile unsigned int*)(0x42620590UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT3          *((volatile unsigned int*)(0x42620594UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT4          *((volatile unsigned int*)(0x42620598UL))
+#define bFM3_INTREQ_IRQ06MON_QUD0INT5          *((volatile unsigned int*)(0x4262059CUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT0          *((volatile unsigned int*)(0x426205A0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT1          *((volatile unsigned int*)(0x426205A4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT2          *((volatile unsigned int*)(0x426205A8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT3          *((volatile unsigned int*)(0x426205ACUL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT4          *((volatile unsigned int*)(0x426205B0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD1INT5          *((volatile unsigned int*)(0x426205B4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT0          *((volatile unsigned int*)(0x426205B8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT1          *((volatile unsigned int*)(0x426205BCUL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT2          *((volatile unsigned int*)(0x426205C0UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT3          *((volatile unsigned int*)(0x426205C4UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT4          *((volatile unsigned int*)(0x426205C8UL))
+#define bFM3_INTREQ_IRQ06MON_QUD2INT5          *((volatile unsigned int*)(0x426205CCUL))
+#define bFM3_INTREQ_IRQ07MON_FMSINT            *((volatile unsigned int*)(0x42620600UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT0           *((volatile unsigned int*)(0x42620680UL))
+#define bFM3_INTREQ_IRQ08MON_MFSINT1           *((volatile unsigned int*)(0x42620684UL))
+#define bFM3_INTREQ_IRQ09MON_FMSINT            *((volatile unsigned int*)(0x42620700UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT0           *((volatile unsigned int*)(0x42620780UL))
+#define bFM3_INTREQ_IRQ10MON_MFSINT1           *((volatile unsigned int*)(0x42620784UL))
+#define bFM3_INTREQ_IRQ11MON_FMSINT            *((volatile unsigned int*)(0x42620800UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT0           *((volatile unsigned int*)(0x42620880UL))
+#define bFM3_INTREQ_IRQ12MON_MFSINT1           *((volatile unsigned int*)(0x42620884UL))
+#define bFM3_INTREQ_IRQ13MON_FMSINT            *((volatile unsigned int*)(0x42620900UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT0           *((volatile unsigned int*)(0x42620980UL))
+#define bFM3_INTREQ_IRQ14MON_MFSINT1           *((volatile unsigned int*)(0x42620984UL))
+#define bFM3_INTREQ_IRQ15MON_FMSINT            *((volatile unsigned int*)(0x42620A00UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT0           *((volatile unsigned int*)(0x42620A80UL))
+#define bFM3_INTREQ_IRQ16MON_MFSINT1           *((volatile unsigned int*)(0x42620A84UL))
+#define bFM3_INTREQ_IRQ17MON_FMSINT            *((volatile unsigned int*)(0x42620B00UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT0           *((volatile unsigned int*)(0x42620B80UL))
+#define bFM3_INTREQ_IRQ18MON_MFSINT1           *((volatile unsigned int*)(0x42620B84UL))
+#define bFM3_INTREQ_IRQ19MON_FMSINT            *((volatile unsigned int*)(0x42620C00UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT0           *((volatile unsigned int*)(0x42620C80UL))
+#define bFM3_INTREQ_IRQ20MON_MFSINT1           *((volatile unsigned int*)(0x42620C84UL))
+#define bFM3_INTREQ_IRQ21MON_FMSINT            *((volatile unsigned int*)(0x42620D00UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT0           *((volatile unsigned int*)(0x42620D80UL))
+#define bFM3_INTREQ_IRQ22MON_MFSINT1           *((volatile unsigned int*)(0x42620D84UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT0           *((volatile unsigned int*)(0x42620E00UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT1           *((volatile unsigned int*)(0x42620E04UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT2           *((volatile unsigned int*)(0x42620E08UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT3           *((volatile unsigned int*)(0x42620E0CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT4           *((volatile unsigned int*)(0x42620E10UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT5           *((volatile unsigned int*)(0x42620E14UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT6           *((volatile unsigned int*)(0x42620E18UL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT7           *((volatile unsigned int*)(0x42620E1CUL))
+#define bFM3_INTREQ_IRQ23MON_PPGINT8           *((volatile unsigned int*)(0x42620E20UL))
+#define bFM3_INTREQ_IRQ24MON_MOSCINT           *((volatile unsigned int*)(0x42620E80UL))
+#define bFM3_INTREQ_IRQ24MON_SOSCINT           *((volatile unsigned int*)(0x42620E84UL))
+#define bFM3_INTREQ_IRQ24MON_MPLLINT           *((volatile unsigned int*)(0x42620E88UL))
+#define bFM3_INTREQ_IRQ24MON_UPLLINT           *((volatile unsigned int*)(0x42620E8CUL))
+#define bFM3_INTREQ_IRQ24MON_WCINT             *((volatile unsigned int*)(0x42620E90UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT0           *((volatile unsigned int*)(0x42620F00UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT1           *((volatile unsigned int*)(0x42620F04UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT2           *((volatile unsigned int*)(0x42620F08UL))
+#define bFM3_INTREQ_IRQ25MON_ADCINT3           *((volatile unsigned int*)(0x42620F0CUL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT0           *((volatile unsigned int*)(0x42620F80UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT1           *((volatile unsigned int*)(0x42620F84UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT2           *((volatile unsigned int*)(0x42620F88UL))
+#define bFM3_INTREQ_IRQ26MON_ADCINT3           *((volatile unsigned int*)(0x42620F8CUL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT0           *((volatile unsigned int*)(0x42621000UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT1           *((volatile unsigned int*)(0x42621004UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT2           *((volatile unsigned int*)(0x42621008UL))
+#define bFM3_INTREQ_IRQ27MON_ADCINT3           *((volatile unsigned int*)(0x4262100CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT0          *((volatile unsigned int*)(0x42621080UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT1          *((volatile unsigned int*)(0x42621084UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT2          *((volatile unsigned int*)(0x42621088UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT3          *((volatile unsigned int*)(0x4262108CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT4          *((volatile unsigned int*)(0x42621090UL))
+#define bFM3_INTREQ_IRQ28MON_FRT0INT5          *((volatile unsigned int*)(0x42621094UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT0          *((volatile unsigned int*)(0x42621098UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT1          *((volatile unsigned int*)(0x4262109CUL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT2          *((volatile unsigned int*)(0x426210A0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT3          *((volatile unsigned int*)(0x426210A4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT4          *((volatile unsigned int*)(0x426210A8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT1INT5          *((volatile unsigned int*)(0x426210ACUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT0          *((volatile unsigned int*)(0x426210B0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT1          *((volatile unsigned int*)(0x426210B4UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT2          *((volatile unsigned int*)(0x426210B8UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT3          *((volatile unsigned int*)(0x426210BCUL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT4          *((volatile unsigned int*)(0x426210C0UL))
+#define bFM3_INTREQ_IRQ28MON_FRT2INT5          *((volatile unsigned int*)(0x426210C4UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT0          *((volatile unsigned int*)(0x42621100UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT1          *((volatile unsigned int*)(0x42621104UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT2          *((volatile unsigned int*)(0x42621108UL))
+#define bFM3_INTREQ_IRQ29MON_ICU0INT3          *((volatile unsigned int*)(0x4262110CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT0          *((volatile unsigned int*)(0x42621110UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT1          *((volatile unsigned int*)(0x42621114UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT2          *((volatile unsigned int*)(0x42621118UL))
+#define bFM3_INTREQ_IRQ29MON_ICU1INT3          *((volatile unsigned int*)(0x4262111CUL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT0          *((volatile unsigned int*)(0x42621120UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT1          *((volatile unsigned int*)(0x42621124UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT2          *((volatile unsigned int*)(0x42621128UL))
+#define bFM3_INTREQ_IRQ29MON_ICU2INT3          *((volatile unsigned int*)(0x4262112CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT0          *((volatile unsigned int*)(0x42621180UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT1          *((volatile unsigned int*)(0x42621184UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT2          *((volatile unsigned int*)(0x42621188UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT3          *((volatile unsigned int*)(0x4262118CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT4          *((volatile unsigned int*)(0x42621190UL))
+#define bFM3_INTREQ_IRQ30MON_OCU0INT5          *((volatile unsigned int*)(0x42621194UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT0          *((volatile unsigned int*)(0x42621198UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT1          *((volatile unsigned int*)(0x4262119CUL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT2          *((volatile unsigned int*)(0x426211A0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT3          *((volatile unsigned int*)(0x426211A4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT4          *((volatile unsigned int*)(0x426211A8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU1INT5          *((volatile unsigned int*)(0x426211ACUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT0          *((volatile unsigned int*)(0x426211B0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT1          *((volatile unsigned int*)(0x426211B4UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT2          *((volatile unsigned int*)(0x426211B8UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT3          *((volatile unsigned int*)(0x426211BCUL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT4          *((volatile unsigned int*)(0x426211C0UL))
+#define bFM3_INTREQ_IRQ30MON_OCU2INT5          *((volatile unsigned int*)(0x426211C4UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT0            *((volatile unsigned int*)(0x42621200UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT1            *((volatile unsigned int*)(0x42621204UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT2            *((volatile unsigned int*)(0x42621208UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT3            *((volatile unsigned int*)(0x4262120CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT4            *((volatile unsigned int*)(0x42621210UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT5            *((volatile unsigned int*)(0x42621214UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT6            *((volatile unsigned int*)(0x42621218UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT7            *((volatile unsigned int*)(0x4262121CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT8            *((volatile unsigned int*)(0x42621220UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT9            *((volatile unsigned int*)(0x42621224UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT10           *((volatile unsigned int*)(0x42621228UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT11           *((volatile unsigned int*)(0x4262122CUL))
+#define bFM3_INTREQ_IRQ31MON_BTINT12           *((volatile unsigned int*)(0x42621230UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT13           *((volatile unsigned int*)(0x42621234UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT14           *((volatile unsigned int*)(0x42621238UL))
+#define bFM3_INTREQ_IRQ31MON_BTINT15           *((volatile unsigned int*)(0x4262123CUL))
+#define bFM3_INTREQ_IRQ32MON_MAC0SBD           *((volatile unsigned int*)(0x42621284UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0PMI           *((volatile unsigned int*)(0x42621288UL))
+#define bFM3_INTREQ_IRQ32MON_MAC0LPI           *((volatile unsigned int*)(0x4262128CUL))
+#define bFM3_INTREQ_IRQ33MON_MAC1SBD           *((volatile unsigned int*)(0x42621304UL))
+#define bFM3_INTREQ_IRQ33MON_MAC1PMI           *((volatile unsigned int*)(0x42621308UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT0          *((volatile unsigned int*)(0x42621380UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT1          *((volatile unsigned int*)(0x42621384UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT2          *((volatile unsigned int*)(0x42621388UL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT3          *((volatile unsigned int*)(0x4262138CUL))
+#define bFM3_INTREQ_IRQ34MON_USB0INT4          *((volatile unsigned int*)(0x42621390UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT0          *((volatile unsigned int*)(0x42621400UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT1          *((volatile unsigned int*)(0x42621404UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT2          *((volatile unsigned int*)(0x42621408UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT3          *((volatile unsigned int*)(0x4262140CUL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT4          *((volatile unsigned int*)(0x42621410UL))
+#define bFM3_INTREQ_IRQ35MON_USB0INT5          *((volatile unsigned int*)(0x42621414UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT0          *((volatile unsigned int*)(0x42621480UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT1          *((volatile unsigned int*)(0x42621484UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT2          *((volatile unsigned int*)(0x42621488UL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT3          *((volatile unsigned int*)(0x4262148CUL))
+#define bFM3_INTREQ_IRQ36MON_USB1INT4          *((volatile unsigned int*)(0x42621490UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT0          *((volatile unsigned int*)(0x42621500UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT1          *((volatile unsigned int*)(0x42621504UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT2          *((volatile unsigned int*)(0x42621508UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT3          *((volatile unsigned int*)(0x4262150CUL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT4          *((volatile unsigned int*)(0x42621510UL))
+#define bFM3_INTREQ_IRQ37MON_USB1INT5          *((volatile unsigned int*)(0x42621514UL))
+#define bFM3_INTREQ_IRQ38MON_DMAINT            *((volatile unsigned int*)(0x42621580UL))
+#define bFM3_INTREQ_IRQ39MON_DMAINT            *((volatile unsigned int*)(0x42621600UL))
+#define bFM3_INTREQ_IRQ40MON_DMAINT            *((volatile unsigned int*)(0x42621680UL))
+#define bFM3_INTREQ_IRQ41MON_DMAINT            *((volatile unsigned int*)(0x42621700UL))
+#define bFM3_INTREQ_IRQ42MON_DMAINT            *((volatile unsigned int*)(0x42621780UL))
+#define bFM3_INTREQ_IRQ43MON_DMAINT            *((volatile unsigned int*)(0x42621800UL))
+#define bFM3_INTREQ_IRQ44MON_DMAINT            *((volatile unsigned int*)(0x42621880UL))
+#define bFM3_INTREQ_IRQ45MON_DMAINT            *((volatile unsigned int*)(0x42621900UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT0            *((volatile unsigned int*)(0x42621980UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT1            *((volatile unsigned int*)(0x42621984UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT2            *((volatile unsigned int*)(0x42621988UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT3            *((volatile unsigned int*)(0x4262198CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT4            *((volatile unsigned int*)(0x42621990UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT5            *((volatile unsigned int*)(0x42621994UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT6            *((volatile unsigned int*)(0x42621998UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT7            *((volatile unsigned int*)(0x4262199CUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT8            *((volatile unsigned int*)(0x426219A0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT9            *((volatile unsigned int*)(0x426219A4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT10           *((volatile unsigned int*)(0x426219A8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT11           *((volatile unsigned int*)(0x426219ACUL))
+#define bFM3_INTREQ_IRQ46MON_BTINT12           *((volatile unsigned int*)(0x426219B0UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT13           *((volatile unsigned int*)(0x426219B4UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT14           *((volatile unsigned int*)(0x426219B8UL))
+#define bFM3_INTREQ_IRQ46MON_BTINT15           *((volatile unsigned int*)(0x426219BCUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL10           *((volatile unsigned int*)(0x42624000UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL11           *((volatile unsigned int*)(0x42624004UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL12           *((volatile unsigned int*)(0x42624008UL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL13           *((volatile unsigned int*)(0x4262400CUL))
+#define bFM3_INTREQ_DRQSEL1_DRQSEL14           *((volatile unsigned int*)(0x42624010UL))
+#define bFM3_INTREQ_DQESEL_ESEL100             *((volatile unsigned int*)(0x42624080UL))
+#define bFM3_INTREQ_DQESEL_ESEL101             *((volatile unsigned int*)(0x42624084UL))
+#define bFM3_INTREQ_DQESEL_ESEL102             *((volatile unsigned int*)(0x42624088UL))
+#define bFM3_INTREQ_DQESEL_ESEL103             *((volatile unsigned int*)(0x4262408CUL))
+#define bFM3_INTREQ_DQESEL_ESEL110             *((volatile unsigned int*)(0x42624090UL))
+#define bFM3_INTREQ_DQESEL_ESEL111             *((volatile unsigned int*)(0x42624094UL))
+#define bFM3_INTREQ_DQESEL_ESEL112             *((volatile unsigned int*)(0x42624098UL))
+#define bFM3_INTREQ_DQESEL_ESEL113             *((volatile unsigned int*)(0x4262409CUL))
+#define bFM3_INTREQ_DQESEL_ESEL240             *((volatile unsigned int*)(0x426240A0UL))
+#define bFM3_INTREQ_DQESEL_ESEL241             *((volatile unsigned int*)(0x426240A4UL))
+#define bFM3_INTREQ_DQESEL_ESEL242             *((volatile unsigned int*)(0x426240A8UL))
+#define bFM3_INTREQ_DQESEL_ESEL243             *((volatile unsigned int*)(0x426240ACUL))
+#define bFM3_INTREQ_DQESEL_ESEL250             *((volatile unsigned int*)(0x426240B0UL))
+#define bFM3_INTREQ_DQESEL_ESEL251             *((volatile unsigned int*)(0x426240B4UL))
+#define bFM3_INTREQ_DQESEL_ESEL252             *((volatile unsigned int*)(0x426240B8UL))
+#define bFM3_INTREQ_DQESEL_ESEL253             *((volatile unsigned int*)(0x426240BCUL))
+#define bFM3_INTREQ_DQESEL_ESEL260             *((volatile unsigned int*)(0x426240C0UL))
+#define bFM3_INTREQ_DQESEL_ESEL261             *((volatile unsigned int*)(0x426240C4UL))
+#define bFM3_INTREQ_DQESEL_ESEL262             *((volatile unsigned int*)(0x426240C8UL))
+#define bFM3_INTREQ_DQESEL_ESEL263             *((volatile unsigned int*)(0x426240CCUL))
+#define bFM3_INTREQ_DQESEL_ESEL270             *((volatile unsigned int*)(0x426240D0UL))
+#define bFM3_INTREQ_DQESEL_ESEL271             *((volatile unsigned int*)(0x426240D4UL))
+#define bFM3_INTREQ_DQESEL_ESEL272             *((volatile unsigned int*)(0x426240D8UL))
+#define bFM3_INTREQ_DQESEL_ESEL273             *((volatile unsigned int*)(0x426240DCUL))
+#define bFM3_INTREQ_DQESEL_ESEL300             *((volatile unsigned int*)(0x426240E0UL))
+#define bFM3_INTREQ_DQESEL_ESEL301             *((volatile unsigned int*)(0x426240E4UL))
+#define bFM3_INTREQ_DQESEL_ESEL302             *((volatile unsigned int*)(0x426240E8UL))
+#define bFM3_INTREQ_DQESEL_ESEL303             *((volatile unsigned int*)(0x426240ECUL))
+#define bFM3_INTREQ_DQESEL_ESEL310             *((volatile unsigned int*)(0x426240F0UL))
+#define bFM3_INTREQ_DQESEL_ESEL311             *((volatile unsigned int*)(0x426240F4UL))
+#define bFM3_INTREQ_DQESEL_ESEL312             *((volatile unsigned int*)(0x426240F8UL))
+#define bFM3_INTREQ_DQESEL_ESEL313             *((volatile unsigned int*)(0x426240FCUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS10           *((volatile unsigned char*)(0x426241E0UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS11           *((volatile unsigned char*)(0x426241E4UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS12           *((volatile unsigned char*)(0x426241E8UL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS13           *((volatile unsigned char*)(0x426241ECUL))
+#define bFM3_INTREQ_ODDPKS1_ODDPKS14           *((volatile unsigned char*)(0x426241F0UL))
+
+/* General purpose I/O registers */
+#define bFM3_GPIO_PFR0_P0                      *((volatile unsigned int*)(0x42660000UL))
+#define bFM3_GPIO_PFR0_P1                      *((volatile unsigned int*)(0x42660004UL))
+#define bFM3_GPIO_PFR0_P2                      *((volatile unsigned int*)(0x42660008UL))
+#define bFM3_GPIO_PFR0_P3                      *((volatile unsigned int*)(0x4266000CUL))
+#define bFM3_GPIO_PFR0_P4                      *((volatile unsigned int*)(0x42660010UL))
+#define bFM3_GPIO_PFR0_P5                      *((volatile unsigned int*)(0x42660014UL))
+#define bFM3_GPIO_PFR0_P6                      *((volatile unsigned int*)(0x42660018UL))
+#define bFM3_GPIO_PFR0_P7                      *((volatile unsigned int*)(0x4266001CUL))
+#define bFM3_GPIO_PFR0_P8                      *((volatile unsigned int*)(0x42660020UL))
+#define bFM3_GPIO_PFR0_P9                      *((volatile unsigned int*)(0x42660024UL))
+#define bFM3_GPIO_PFR1_P0                      *((volatile unsigned int*)(0x42660080UL))
+#define bFM3_GPIO_PFR1_P1                      *((volatile unsigned int*)(0x42660084UL))
+#define bFM3_GPIO_PFR1_P2                      *((volatile unsigned int*)(0x42660088UL))
+#define bFM3_GPIO_PFR1_P3                      *((volatile unsigned int*)(0x4266008CUL))
+#define bFM3_GPIO_PFR1_P4                      *((volatile unsigned int*)(0x42660090UL))
+#define bFM3_GPIO_PFR1_P5                      *((volatile unsigned int*)(0x42660094UL))
+#define bFM3_GPIO_PFR1_P6                      *((volatile unsigned int*)(0x42660098UL))
+#define bFM3_GPIO_PFR1_P7                      *((volatile unsigned int*)(0x4266009CUL))
+#define bFM3_GPIO_PFR1_P8                      *((volatile unsigned int*)(0x426600A0UL))
+#define bFM3_GPIO_PFR1_P9                      *((volatile unsigned int*)(0x426600A4UL))
+#define bFM3_GPIO_PFR1_PA                      *((volatile unsigned int*)(0x426600A8UL))
+#define bFM3_GPIO_PFR1_PB                      *((volatile unsigned int*)(0x426600ACUL))
+#define bFM3_GPIO_PFR1_PC                      *((volatile unsigned int*)(0x426600B0UL))
+#define bFM3_GPIO_PFR1_PD                      *((volatile unsigned int*)(0x426600B4UL))
+#define bFM3_GPIO_PFR1_PE                      *((volatile unsigned int*)(0x426600B8UL))
+#define bFM3_GPIO_PFR1_PF                      *((volatile unsigned int*)(0x426600BCUL))
+#define bFM3_GPIO_PFR2_P0                      *((volatile unsigned int*)(0x42660100UL))
+#define bFM3_GPIO_PFR2_P1                      *((volatile unsigned int*)(0x42660104UL))
+#define bFM3_GPIO_PFR2_P2                      *((volatile unsigned int*)(0x42660108UL))
+#define bFM3_GPIO_PFR2_P3                      *((volatile unsigned int*)(0x4266010CUL))
+#define bFM3_GPIO_PFR2_P4                      *((volatile unsigned int*)(0x42660110UL))
+#define bFM3_GPIO_PFR2_P5                      *((volatile unsigned int*)(0x42660114UL))
+#define bFM3_GPIO_PFR2_P6                      *((volatile unsigned int*)(0x42660118UL))
+#define bFM3_GPIO_PFR2_P7                      *((volatile unsigned int*)(0x4266011CUL))
+#define bFM3_GPIO_PFR2_P8                      *((volatile unsigned int*)(0x42660120UL))
+#define bFM3_GPIO_PFR2_P9                      *((volatile unsigned int*)(0x42660124UL))
+#define bFM3_GPIO_PFR3_P0                      *((volatile unsigned int*)(0x42660180UL))
+#define bFM3_GPIO_PFR3_P1                      *((volatile unsigned int*)(0x42660184UL))
+#define bFM3_GPIO_PFR3_P2                      *((volatile unsigned int*)(0x42660188UL))
+#define bFM3_GPIO_PFR3_P3                      *((volatile unsigned int*)(0x4266018CUL))
+#define bFM3_GPIO_PFR3_P4                      *((volatile unsigned int*)(0x42660190UL))
+#define bFM3_GPIO_PFR3_P5                      *((volatile unsigned int*)(0x42660194UL))
+#define bFM3_GPIO_PFR3_P6                      *((volatile unsigned int*)(0x42660198UL))
+#define bFM3_GPIO_PFR3_P7                      *((volatile unsigned int*)(0x4266019CUL))
+#define bFM3_GPIO_PFR3_P8                      *((volatile unsigned int*)(0x426601A0UL))
+#define bFM3_GPIO_PFR3_P9                      *((volatile unsigned int*)(0x426601A4UL))
+#define bFM3_GPIO_PFR3_PA                      *((volatile unsigned int*)(0x426601A8UL))
+#define bFM3_GPIO_PFR3_PB                      *((volatile unsigned int*)(0x426601ACUL))
+#define bFM3_GPIO_PFR3_PC                      *((volatile unsigned int*)(0x426601B0UL))
+#define bFM3_GPIO_PFR3_PD                      *((volatile unsigned int*)(0x426601B4UL))
+#define bFM3_GPIO_PFR3_PE                      *((volatile unsigned int*)(0x426601B8UL))
+#define bFM3_GPIO_PFR3_PF                      *((volatile unsigned int*)(0x426601BCUL))
+#define bFM3_GPIO_PFR4_P0                      *((volatile unsigned int*)(0x42660200UL))
+#define bFM3_GPIO_PFR4_P1                      *((volatile unsigned int*)(0x42660204UL))
+#define bFM3_GPIO_PFR4_P2                      *((volatile unsigned int*)(0x42660208UL))
+#define bFM3_GPIO_PFR4_P3                      *((volatile unsigned int*)(0x4266020CUL))
+#define bFM3_GPIO_PFR4_P4                      *((volatile unsigned int*)(0x42660210UL))
+#define bFM3_GPIO_PFR4_P5                      *((volatile unsigned int*)(0x42660214UL))
+#define bFM3_GPIO_PFR4_P6                      *((volatile unsigned int*)(0x42660218UL))
+#define bFM3_GPIO_PFR4_P7                      *((volatile unsigned int*)(0x4266021CUL))
+#define bFM3_GPIO_PFR4_P8                      *((volatile unsigned int*)(0x42660220UL))
+#define bFM3_GPIO_PFR4_P9                      *((volatile unsigned int*)(0x42660224UL))
+#define bFM3_GPIO_PFR4_PA                      *((volatile unsigned int*)(0x42660228UL))
+#define bFM3_GPIO_PFR4_PB                      *((volatile unsigned int*)(0x4266022CUL))
+#define bFM3_GPIO_PFR4_PC                      *((volatile unsigned int*)(0x42660230UL))
+#define bFM3_GPIO_PFR4_PD                      *((volatile unsigned int*)(0x42660234UL))
+#define bFM3_GPIO_PFR4_PE                      *((volatile unsigned int*)(0x42660238UL))
+#define bFM3_GPIO_PFR5_P0                      *((volatile unsigned int*)(0x42660280UL))
+#define bFM3_GPIO_PFR5_P1                      *((volatile unsigned int*)(0x42660284UL))
+#define bFM3_GPIO_PFR5_P2                      *((volatile unsigned int*)(0x42660288UL))
+#define bFM3_GPIO_PFR5_P3                      *((volatile unsigned int*)(0x4266028CUL))
+#define bFM3_GPIO_PFR5_P4                      *((volatile unsigned int*)(0x42660290UL))
+#define bFM3_GPIO_PFR5_P5                      *((volatile unsigned int*)(0x42660294UL))
+#define bFM3_GPIO_PFR5_P6                      *((volatile unsigned int*)(0x42660298UL))
+#define bFM3_GPIO_PFR5_P7                      *((volatile unsigned int*)(0x4266029CUL))
+#define bFM3_GPIO_PFR5_P8                      *((volatile unsigned int*)(0x426602A0UL))
+#define bFM3_GPIO_PFR5_P9                      *((volatile unsigned int*)(0x426602A4UL))
+#define bFM3_GPIO_PFR5_PA                      *((volatile unsigned int*)(0x426602A8UL))
+#define bFM3_GPIO_PFR5_PB                      *((volatile unsigned int*)(0x426602ACUL))
+#define bFM3_GPIO_PFR5_PC                      *((volatile unsigned int*)(0x426602B0UL))
+#define bFM3_GPIO_PFR5_PD                      *((volatile unsigned int*)(0x426602B4UL))
+#define bFM3_GPIO_PFR6_P0                      *((volatile unsigned int*)(0x42660300UL))
+#define bFM3_GPIO_PFR6_P1                      *((volatile unsigned int*)(0x42660304UL))
+#define bFM3_GPIO_PFR6_P2                      *((volatile unsigned int*)(0x42660308UL))
+#define bFM3_GPIO_PFR7_P0                      *((volatile unsigned int*)(0x42660380UL))
+#define bFM3_GPIO_PFR7_P1                      *((volatile unsigned int*)(0x42660384UL))
+#define bFM3_GPIO_PFR7_P2                      *((volatile unsigned int*)(0x42660388UL))
+#define bFM3_GPIO_PFR7_P3                      *((volatile unsigned int*)(0x4266038CUL))
+#define bFM3_GPIO_PFR7_P4                      *((volatile unsigned int*)(0x42660390UL))
+#define bFM3_GPIO_PFR7_P5                      *((volatile unsigned int*)(0x42660394UL))
+#define bFM3_GPIO_PFR7_P6                      *((volatile unsigned int*)(0x42660398UL))
+#define bFM3_GPIO_PFR7_P7                      *((volatile unsigned int*)(0x4266039CUL))
+#define bFM3_GPIO_PFR7_P8                      *((volatile unsigned int*)(0x426603A0UL))
+#define bFM3_GPIO_PFR7_P9                      *((volatile unsigned int*)(0x426603A4UL))
+#define bFM3_GPIO_PFR7_PA                      *((volatile unsigned int*)(0x426603A8UL))
+#define bFM3_GPIO_PFR7_PB                      *((volatile unsigned int*)(0x426603ACUL))
+#define bFM3_GPIO_PFR7_PC                      *((volatile unsigned int*)(0x426603B0UL))
+#define bFM3_GPIO_PFR7_PD                      *((volatile unsigned int*)(0x426603B4UL))
+#define bFM3_GPIO_PFR7_PE                      *((volatile unsigned int*)(0x426603B8UL))
+#define bFM3_GPIO_PFR7_PF                      *((volatile unsigned int*)(0x426603BCUL))
+#define bFM3_GPIO_PFR8_P0                      *((volatile unsigned int*)(0x42660400UL))
+#define bFM3_GPIO_PFR8_P1                      *((volatile unsigned int*)(0x42660404UL))
+#define bFM3_GPIO_PFR8_P2                      *((volatile unsigned int*)(0x42660408UL))
+#define bFM3_GPIO_PFR8_P3                      *((volatile unsigned int*)(0x4266040CUL))
+#define bFM3_GPIO_PFR9_P0                      *((volatile unsigned int*)(0x42660480UL))
+#define bFM3_GPIO_PFR9_P1                      *((volatile unsigned int*)(0x42660484UL))
+#define bFM3_GPIO_PFR9_P2                      *((volatile unsigned int*)(0x42660488UL))
+#define bFM3_GPIO_PFR9_P3                      *((volatile unsigned int*)(0x4266048CUL))
+#define bFM3_GPIO_PFR9_P4                      *((volatile unsigned int*)(0x42660490UL))
+#define bFM3_GPIO_PFR9_P5                      *((volatile unsigned int*)(0x42660494UL))
+#define bFM3_GPIO_PFRA_P0                      *((volatile unsigned int*)(0x42660500UL))
+#define bFM3_GPIO_PFRA_P1                      *((volatile unsigned int*)(0x42660504UL))
+#define bFM3_GPIO_PFRA_P2                      *((volatile unsigned int*)(0x42660508UL))
+#define bFM3_GPIO_PFRA_P3                      *((volatile unsigned int*)(0x4266050CUL))
+#define bFM3_GPIO_PFRA_P4                      *((volatile unsigned int*)(0x42660510UL))
+#define bFM3_GPIO_PFRA_P5                      *((volatile unsigned int*)(0x42660514UL))
+#define bFM3_GPIO_PFRB_P0                      *((volatile unsigned int*)(0x42660580UL))
+#define bFM3_GPIO_PFRB_P1                      *((volatile unsigned int*)(0x42660584UL))
+#define bFM3_GPIO_PFRB_P2                      *((volatile unsigned int*)(0x42660588UL))
+#define bFM3_GPIO_PFRB_P3                      *((volatile unsigned int*)(0x4266058CUL))
+#define bFM3_GPIO_PFRB_P4                      *((volatile unsigned int*)(0x42660590UL))
+#define bFM3_GPIO_PFRB_P5                      *((volatile unsigned int*)(0x42660594UL))
+#define bFM3_GPIO_PFRB_P6                      *((volatile unsigned int*)(0x42660598UL))
+#define bFM3_GPIO_PFRB_P7                      *((volatile unsigned int*)(0x4266059CUL))
+#define bFM3_GPIO_PFRC_P0                      *((volatile unsigned int*)(0x42660600UL))
+#define bFM3_GPIO_PFRC_P1                      *((volatile unsigned int*)(0x42660604UL))
+#define bFM3_GPIO_PFRC_P2                      *((volatile unsigned int*)(0x42660608UL))
+#define bFM3_GPIO_PFRC_P3                      *((volatile unsigned int*)(0x4266060CUL))
+#define bFM3_GPIO_PFRC_P4                      *((volatile unsigned int*)(0x42660610UL))
+#define bFM3_GPIO_PFRC_P5                      *((volatile unsigned int*)(0x42660614UL))
+#define bFM3_GPIO_PFRC_P6                      *((volatile unsigned int*)(0x42660618UL))
+#define bFM3_GPIO_PFRC_P7                      *((volatile unsigned int*)(0x4266061CUL))
+#define bFM3_GPIO_PFRC_P8                      *((volatile unsigned int*)(0x42660620UL))
+#define bFM3_GPIO_PFRC_P9                      *((volatile unsigned int*)(0x42660624UL))
+#define bFM3_GPIO_PFRC_PA                      *((volatile unsigned int*)(0x42660628UL))
+#define bFM3_GPIO_PFRC_PB                      *((volatile unsigned int*)(0x4266062CUL))
+#define bFM3_GPIO_PFRC_PC                      *((volatile unsigned int*)(0x42660630UL))
+#define bFM3_GPIO_PFRC_PD                      *((volatile unsigned int*)(0x42660634UL))
+#define bFM3_GPIO_PFRC_PE                      *((volatile unsigned int*)(0x42660638UL))
+#define bFM3_GPIO_PFRC_PF                      *((volatile unsigned int*)(0x4266063CUL))
+#define bFM3_GPIO_PFRD_P0                      *((volatile unsigned int*)(0x42660680UL))
+#define bFM3_GPIO_PFRD_P1                      *((volatile unsigned int*)(0x42660684UL))
+#define bFM3_GPIO_PFRD_P2                      *((volatile unsigned int*)(0x42660688UL))
+#define bFM3_GPIO_PFRD_P3                      *((volatile unsigned int*)(0x4266068CUL))
+#define bFM3_GPIO_PFRE_P0                      *((volatile unsigned int*)(0x42660700UL))
+#define bFM3_GPIO_PFRE_P2                      *((volatile unsigned int*)(0x42660708UL))
+#define bFM3_GPIO_PFRE_P3                      *((volatile unsigned int*)(0x4266070CUL))
+#define bFM3_GPIO_PFRF_P0                      *((volatile unsigned int*)(0x42660780UL))
+#define bFM3_GPIO_PFRF_P1                      *((volatile unsigned int*)(0x42660784UL))
+#define bFM3_GPIO_PFRF_P2                      *((volatile unsigned int*)(0x42660788UL))
+#define bFM3_GPIO_PFRF_P3                      *((volatile unsigned int*)(0x4266078CUL))
+#define bFM3_GPIO_PFRF_P4                      *((volatile unsigned int*)(0x42660790UL))
+#define bFM3_GPIO_PFRF_P5                      *((volatile unsigned int*)(0x42660794UL))
+#define bFM3_GPIO_PFRF_P6                      *((volatile unsigned int*)(0x42660798UL))
+#define bFM3_GPIO_PCR0_P0                      *((volatile unsigned int*)(0x42662000UL))
+#define bFM3_GPIO_PCR0_P1                      *((volatile unsigned int*)(0x42662004UL))
+#define bFM3_GPIO_PCR0_P2                      *((volatile unsigned int*)(0x42662008UL))
+#define bFM3_GPIO_PCR0_P3                      *((volatile unsigned int*)(0x4266200CUL))
+#define bFM3_GPIO_PCR0_P4                      *((volatile unsigned int*)(0x42662010UL))
+#define bFM3_GPIO_PCR0_P5                      *((volatile unsigned int*)(0x42662014UL))
+#define bFM3_GPIO_PCR0_P6                      *((volatile unsigned int*)(0x42662018UL))
+#define bFM3_GPIO_PCR0_P7                      *((volatile unsigned int*)(0x4266201CUL))
+#define bFM3_GPIO_PCR0_P8                      *((volatile unsigned int*)(0x42662020UL))
+#define bFM3_GPIO_PCR0_P9                      *((volatile unsigned int*)(0x42662024UL))
+#define bFM3_GPIO_PCR1_P0                      *((volatile unsigned int*)(0x42662080UL))
+#define bFM3_GPIO_PCR1_P1                      *((volatile unsigned int*)(0x42662084UL))
+#define bFM3_GPIO_PCR1_P2                      *((volatile unsigned int*)(0x42662088UL))
+#define bFM3_GPIO_PCR1_P3                      *((volatile unsigned int*)(0x4266208CUL))
+#define bFM3_GPIO_PCR1_P4                      *((volatile unsigned int*)(0x42662090UL))
+#define bFM3_GPIO_PCR1_P5                      *((volatile unsigned int*)(0x42662094UL))
+#define bFM3_GPIO_PCR1_P6                      *((volatile unsigned int*)(0x42662098UL))
+#define bFM3_GPIO_PCR1_P7                      *((volatile unsigned int*)(0x4266209CUL))
+#define bFM3_GPIO_PCR1_P8                      *((volatile unsigned int*)(0x426620A0UL))
+#define bFM3_GPIO_PCR1_P9                      *((volatile unsigned int*)(0x426620A4UL))
+#define bFM3_GPIO_PCR1_PA                      *((volatile unsigned int*)(0x426620A8UL))
+#define bFM3_GPIO_PCR1_PB                      *((volatile unsigned int*)(0x426620ACUL))
+#define bFM3_GPIO_PCR1_PC                      *((volatile unsigned int*)(0x426620B0UL))
+#define bFM3_GPIO_PCR1_PD                      *((volatile unsigned int*)(0x426620B4UL))
+#define bFM3_GPIO_PCR1_PE                      *((volatile unsigned int*)(0x426620B8UL))
+#define bFM3_GPIO_PCR1_PF                      *((volatile unsigned int*)(0x426620BCUL))
+#define bFM3_GPIO_PCR2_P0                      *((volatile unsigned int*)(0x42662100UL))
+#define bFM3_GPIO_PCR2_P1                      *((volatile unsigned int*)(0x42662104UL))
+#define bFM3_GPIO_PCR2_P2                      *((volatile unsigned int*)(0x42662108UL))
+#define bFM3_GPIO_PCR2_P3                      *((volatile unsigned int*)(0x4266210CUL))
+#define bFM3_GPIO_PCR2_P4                      *((volatile unsigned int*)(0x42662110UL))
+#define bFM3_GPIO_PCR2_P5                      *((volatile unsigned int*)(0x42662114UL))
+#define bFM3_GPIO_PCR2_P6                      *((volatile unsigned int*)(0x42662118UL))
+#define bFM3_GPIO_PCR2_P7                      *((volatile unsigned int*)(0x4266211CUL))
+#define bFM3_GPIO_PCR2_P8                      *((volatile unsigned int*)(0x42662120UL))
+#define bFM3_GPIO_PCR2_P9                      *((volatile unsigned int*)(0x42662124UL))
+#define bFM3_GPIO_PCR3_P0                      *((volatile unsigned int*)(0x42662180UL))
+#define bFM3_GPIO_PCR3_P1                      *((volatile unsigned int*)(0x42662184UL))
+#define bFM3_GPIO_PCR3_P2                      *((volatile unsigned int*)(0x42662188UL))
+#define bFM3_GPIO_PCR3_P3                      *((volatile unsigned int*)(0x4266218CUL))
+#define bFM3_GPIO_PCR3_P4                      *((volatile unsigned int*)(0x42662190UL))
+#define bFM3_GPIO_PCR3_P5                      *((volatile unsigned int*)(0x42662194UL))
+#define bFM3_GPIO_PCR3_P6                      *((volatile unsigned int*)(0x42662198UL))
+#define bFM3_GPIO_PCR3_P7                      *((volatile unsigned int*)(0x4266219CUL))
+#define bFM3_GPIO_PCR3_P8                      *((volatile unsigned int*)(0x426621A0UL))
+#define bFM3_GPIO_PCR3_P9                      *((volatile unsigned int*)(0x426621A4UL))
+#define bFM3_GPIO_PCR3_PA                      *((volatile unsigned int*)(0x426621A8UL))
+#define bFM3_GPIO_PCR3_PB                      *((volatile unsigned int*)(0x426621ACUL))
+#define bFM3_GPIO_PCR3_PC                      *((volatile unsigned int*)(0x426621B0UL))
+#define bFM3_GPIO_PCR3_PD                      *((volatile unsigned int*)(0x426621B4UL))
+#define bFM3_GPIO_PCR3_PE                      *((volatile unsigned int*)(0x426621B8UL))
+#define bFM3_GPIO_PCR3_PF                      *((volatile unsigned int*)(0x426621BCUL))
+#define bFM3_GPIO_PCR4_P0                      *((volatile unsigned int*)(0x42662200UL))
+#define bFM3_GPIO_PCR4_P1                      *((volatile unsigned int*)(0x42662204UL))
+#define bFM3_GPIO_PCR4_P2                      *((volatile unsigned int*)(0x42662208UL))
+#define bFM3_GPIO_PCR4_P3                      *((volatile unsigned int*)(0x4266220CUL))
+#define bFM3_GPIO_PCR4_P4                      *((volatile unsigned int*)(0x42662210UL))
+#define bFM3_GPIO_PCR4_P5                      *((volatile unsigned int*)(0x42662214UL))
+#define bFM3_GPIO_PCR4_P6                      *((volatile unsigned int*)(0x42662218UL))
+#define bFM3_GPIO_PCR4_P7                      *((volatile unsigned int*)(0x4266221CUL))
+#define bFM3_GPIO_PCR4_P8                      *((volatile unsigned int*)(0x42662220UL))
+#define bFM3_GPIO_PCR4_P9                      *((volatile unsigned int*)(0x42662224UL))
+#define bFM3_GPIO_PCR4_PA                      *((volatile unsigned int*)(0x42662228UL))
+#define bFM3_GPIO_PCR4_PB                      *((volatile unsigned int*)(0x4266222CUL))
+#define bFM3_GPIO_PCR4_PC                      *((volatile unsigned int*)(0x42662230UL))
+#define bFM3_GPIO_PCR4_PD                      *((volatile unsigned int*)(0x42662234UL))
+#define bFM3_GPIO_PCR4_PE                      *((volatile unsigned int*)(0x42662238UL))
+#define bFM3_GPIO_PCR5_P0                      *((volatile unsigned int*)(0x42662280UL))
+#define bFM3_GPIO_PCR5_P1                      *((volatile unsigned int*)(0x42662284UL))
+#define bFM3_GPIO_PCR5_P2                      *((volatile unsigned int*)(0x42662288UL))
+#define bFM3_GPIO_PCR5_P3                      *((volatile unsigned int*)(0x4266228CUL))
+#define bFM3_GPIO_PCR5_P4                      *((volatile unsigned int*)(0x42662290UL))
+#define bFM3_GPIO_PCR5_P5                      *((volatile unsigned int*)(0x42662294UL))
+#define bFM3_GPIO_PCR5_P6                      *((volatile unsigned int*)(0x42662298UL))
+#define bFM3_GPIO_PCR5_P7                      *((volatile unsigned int*)(0x4266229CUL))
+#define bFM3_GPIO_PCR5_P8                      *((volatile unsigned int*)(0x426622A0UL))
+#define bFM3_GPIO_PCR5_P9                      *((volatile unsigned int*)(0x426622A4UL))
+#define bFM3_GPIO_PCR5_PA                      *((volatile unsigned int*)(0x426622A8UL))
+#define bFM3_GPIO_PCR5_PB                      *((volatile unsigned int*)(0x426622ACUL))
+#define bFM3_GPIO_PCR5_PC                      *((volatile unsigned int*)(0x426622B0UL))
+#define bFM3_GPIO_PCR5_PD                      *((volatile unsigned int*)(0x426622B4UL))
+#define bFM3_GPIO_PCR6_P0                      *((volatile unsigned int*)(0x42662300UL))
+#define bFM3_GPIO_PCR6_P1                      *((volatile unsigned int*)(0x42662304UL))
+#define bFM3_GPIO_PCR6_P2                      *((volatile unsigned int*)(0x42662308UL))
+#define bFM3_GPIO_PCR7_P0                      *((volatile unsigned int*)(0x42662380UL))
+#define bFM3_GPIO_PCR7_P1                      *((volatile unsigned int*)(0x42662384UL))
+#define bFM3_GPIO_PCR7_P2                      *((volatile unsigned int*)(0x42662388UL))
+#define bFM3_GPIO_PCR7_P3                      *((volatile unsigned int*)(0x4266238CUL))
+#define bFM3_GPIO_PCR7_P4                      *((volatile unsigned int*)(0x42662390UL))
+#define bFM3_GPIO_PCR7_P5                      *((volatile unsigned int*)(0x42662394UL))
+#define bFM3_GPIO_PCR7_P6                      *((volatile unsigned int*)(0x42662398UL))
+#define bFM3_GPIO_PCR7_P7                      *((volatile unsigned int*)(0x4266239CUL))
+#define bFM3_GPIO_PCR7_P8                      *((volatile unsigned int*)(0x426623A0UL))
+#define bFM3_GPIO_PCR7_P9                      *((volatile unsigned int*)(0x426623A4UL))
+#define bFM3_GPIO_PCR7_PA                      *((volatile unsigned int*)(0x426623A8UL))
+#define bFM3_GPIO_PCR7_PB                      *((volatile unsigned int*)(0x426623ACUL))
+#define bFM3_GPIO_PCR7_PC                      *((volatile unsigned int*)(0x426623B0UL))
+#define bFM3_GPIO_PCR7_PD                      *((volatile unsigned int*)(0x426623B4UL))
+#define bFM3_GPIO_PCR7_PE                      *((volatile unsigned int*)(0x426623B8UL))
+#define bFM3_GPIO_PCR7_PF                      *((volatile unsigned int*)(0x426623BCUL))
+#define bFM3_GPIO_PCR9_P0                      *((volatile unsigned int*)(0x42662480UL))
+#define bFM3_GPIO_PCR9_P1                      *((volatile unsigned int*)(0x42662484UL))
+#define bFM3_GPIO_PCR9_P2                      *((volatile unsigned int*)(0x42662488UL))
+#define bFM3_GPIO_PCR9_P3                      *((volatile unsigned int*)(0x4266248CUL))
+#define bFM3_GPIO_PCR9_P4                      *((volatile unsigned int*)(0x42662490UL))
+#define bFM3_GPIO_PCR9_P5                      *((volatile unsigned int*)(0x42662494UL))
+#define bFM3_GPIO_PCRA_P0                      *((volatile unsigned int*)(0x42662500UL))
+#define bFM3_GPIO_PCRA_P1                      *((volatile unsigned int*)(0x42662504UL))
+#define bFM3_GPIO_PCRA_P2                      *((volatile unsigned int*)(0x42662508UL))
+#define bFM3_GPIO_PCRA_P3                      *((volatile unsigned int*)(0x4266250CUL))
+#define bFM3_GPIO_PCRA_P4                      *((volatile unsigned int*)(0x42662510UL))
+#define bFM3_GPIO_PCRA_P5                      *((volatile unsigned int*)(0x42662514UL))
+#define bFM3_GPIO_PCRB_P0                      *((volatile unsigned int*)(0x42662580UL))
+#define bFM3_GPIO_PCRB_P1                      *((volatile unsigned int*)(0x42662584UL))
+#define bFM3_GPIO_PCRB_P2                      *((volatile unsigned int*)(0x42662588UL))
+#define bFM3_GPIO_PCRB_P3                      *((volatile unsigned int*)(0x4266258CUL))
+#define bFM3_GPIO_PCRB_P4                      *((volatile unsigned int*)(0x42662590UL))
+#define bFM3_GPIO_PCRB_P5                      *((volatile unsigned int*)(0x42662594UL))
+#define bFM3_GPIO_PCRB_P6                      *((volatile unsigned int*)(0x42662598UL))
+#define bFM3_GPIO_PCRB_P7                      *((volatile unsigned int*)(0x4266259CUL))
+#define bFM3_GPIO_PCRC_P0                      *((volatile unsigned int*)(0x42662600UL))
+#define bFM3_GPIO_PCRC_P1                      *((volatile unsigned int*)(0x42662604UL))
+#define bFM3_GPIO_PCRC_P2                      *((volatile unsigned int*)(0x42662608UL))
+#define bFM3_GPIO_PCRC_P3                      *((volatile unsigned int*)(0x4266260CUL))
+#define bFM3_GPIO_PCRC_P4                      *((volatile unsigned int*)(0x42662610UL))
+#define bFM3_GPIO_PCRC_P5                      *((volatile unsigned int*)(0x42662614UL))
+#define bFM3_GPIO_PCRC_P6                      *((volatile unsigned int*)(0x42662618UL))
+#define bFM3_GPIO_PCRC_P7                      *((volatile unsigned int*)(0x4266261CUL))
+#define bFM3_GPIO_PCRC_P8                      *((volatile unsigned int*)(0x42662620UL))
+#define bFM3_GPIO_PCRC_P9                      *((volatile unsigned int*)(0x42662624UL))
+#define bFM3_GPIO_PCRC_PA                      *((volatile unsigned int*)(0x42662628UL))
+#define bFM3_GPIO_PCRC_PB                      *((volatile unsigned int*)(0x4266262CUL))
+#define bFM3_GPIO_PCRC_PC                      *((volatile unsigned int*)(0x42662630UL))
+#define bFM3_GPIO_PCRC_PD                      *((volatile unsigned int*)(0x42662634UL))
+#define bFM3_GPIO_PCRC_PE                      *((volatile unsigned int*)(0x42662638UL))
+#define bFM3_GPIO_PCRC_PF                      *((volatile unsigned int*)(0x4266263CUL))
+#define bFM3_GPIO_PCRD_P0                      *((volatile unsigned int*)(0x42662680UL))
+#define bFM3_GPIO_PCRD_P1                      *((volatile unsigned int*)(0x42662684UL))
+#define bFM3_GPIO_PCRD_P2                      *((volatile unsigned int*)(0x42662688UL))
+#define bFM3_GPIO_PCRD_P3                      *((volatile unsigned int*)(0x4266268CUL))
+#define bFM3_GPIO_PCRE_P2                      *((volatile unsigned int*)(0x42662708UL))
+#define bFM3_GPIO_PCRE_P3                      *((volatile unsigned int*)(0x4266270CUL))
+#define bFM3_GPIO_DDR0_P0                      *((volatile unsigned int*)(0x42664000UL))
+#define bFM3_GPIO_DDR0_P1                      *((volatile unsigned int*)(0x42664004UL))
+#define bFM3_GPIO_DDR0_P2                      *((volatile unsigned int*)(0x42664008UL))
+#define bFM3_GPIO_DDR0_P3                      *((volatile unsigned int*)(0x4266400CUL))
+#define bFM3_GPIO_DDR0_P4                      *((volatile unsigned int*)(0x42664010UL))
+#define bFM3_GPIO_DDR0_P5                      *((volatile unsigned int*)(0x42664014UL))
+#define bFM3_GPIO_DDR0_P6                      *((volatile unsigned int*)(0x42664018UL))
+#define bFM3_GPIO_DDR0_P7                      *((volatile unsigned int*)(0x4266401CUL))
+#define bFM3_GPIO_DDR0_P8                      *((volatile unsigned int*)(0x42664020UL))
+#define bFM3_GPIO_DDR0_P9                      *((volatile unsigned int*)(0x42664024UL))
+#define bFM3_GPIO_DDR1_P0                      *((volatile unsigned int*)(0x42664080UL))
+#define bFM3_GPIO_DDR1_P1                      *((volatile unsigned int*)(0x42664084UL))
+#define bFM3_GPIO_DDR1_P2                      *((volatile unsigned int*)(0x42664088UL))
+#define bFM3_GPIO_DDR1_P3                      *((volatile unsigned int*)(0x4266408CUL))
+#define bFM3_GPIO_DDR1_P4                      *((volatile unsigned int*)(0x42664090UL))
+#define bFM3_GPIO_DDR1_P5                      *((volatile unsigned int*)(0x42664094UL))
+#define bFM3_GPIO_DDR1_P6                      *((volatile unsigned int*)(0x42664098UL))
+#define bFM3_GPIO_DDR1_P7                      *((volatile unsigned int*)(0x4266409CUL))
+#define bFM3_GPIO_DDR1_P8                      *((volatile unsigned int*)(0x426640A0UL))
+#define bFM3_GPIO_DDR1_P9                      *((volatile unsigned int*)(0x426640A4UL))
+#define bFM3_GPIO_DDR1_PA                      *((volatile unsigned int*)(0x426640A8UL))
+#define bFM3_GPIO_DDR1_PB                      *((volatile unsigned int*)(0x426640ACUL))
+#define bFM3_GPIO_DDR1_PC                      *((volatile unsigned int*)(0x426640B0UL))
+#define bFM3_GPIO_DDR1_PD                      *((volatile unsigned int*)(0x426640B4UL))
+#define bFM3_GPIO_DDR1_PE                      *((volatile unsigned int*)(0x426640B8UL))
+#define bFM3_GPIO_DDR1_PF                      *((volatile unsigned int*)(0x426640BCUL))
+#define bFM3_GPIO_DDR2_P0                      *((volatile unsigned int*)(0x42664100UL))
+#define bFM3_GPIO_DDR2_P1                      *((volatile unsigned int*)(0x42664104UL))
+#define bFM3_GPIO_DDR2_P2                      *((volatile unsigned int*)(0x42664108UL))
+#define bFM3_GPIO_DDR2_P3                      *((volatile unsigned int*)(0x4266410CUL))
+#define bFM3_GPIO_DDR2_P4                      *((volatile unsigned int*)(0x42664110UL))
+#define bFM3_GPIO_DDR2_P5                      *((volatile unsigned int*)(0x42664114UL))
+#define bFM3_GPIO_DDR2_P6                      *((volatile unsigned int*)(0x42664118UL))
+#define bFM3_GPIO_DDR2_P7                      *((volatile unsigned int*)(0x4266411CUL))
+#define bFM3_GPIO_DDR2_P8                      *((volatile unsigned int*)(0x42664120UL))
+#define bFM3_GPIO_DDR2_P9                      *((volatile unsigned int*)(0x42664124UL))
+#define bFM3_GPIO_DDR3_P0                      *((volatile unsigned int*)(0x42664180UL))
+#define bFM3_GPIO_DDR3_P1                      *((volatile unsigned int*)(0x42664184UL))
+#define bFM3_GPIO_DDR3_P2                      *((volatile unsigned int*)(0x42664188UL))
+#define bFM3_GPIO_DDR3_P3                      *((volatile unsigned int*)(0x4266418CUL))
+#define bFM3_GPIO_DDR3_P4                      *((volatile unsigned int*)(0x42664190UL))
+#define bFM3_GPIO_DDR3_P5                      *((volatile unsigned int*)(0x42664194UL))
+#define bFM3_GPIO_DDR3_P6                      *((volatile unsigned int*)(0x42664198UL))
+#define bFM3_GPIO_DDR3_P7                      *((volatile unsigned int*)(0x4266419CUL))
+#define bFM3_GPIO_DDR3_P8                      *((volatile unsigned int*)(0x426641A0UL))
+#define bFM3_GPIO_DDR3_P9                      *((volatile unsigned int*)(0x426641A4UL))
+#define bFM3_GPIO_DDR3_PA                      *((volatile unsigned int*)(0x426641A8UL))
+#define bFM3_GPIO_DDR3_PB                      *((volatile unsigned int*)(0x426641ACUL))
+#define bFM3_GPIO_DDR3_PC                      *((volatile unsigned int*)(0x426641B0UL))
+#define bFM3_GPIO_DDR3_PD                      *((volatile unsigned int*)(0x426641B4UL))
+#define bFM3_GPIO_DDR3_PE                      *((volatile unsigned int*)(0x426641B8UL))
+#define bFM3_GPIO_DDR3_PF                      *((volatile unsigned int*)(0x426641BCUL))
+#define bFM3_GPIO_DDR4_P0                      *((volatile unsigned int*)(0x42664200UL))
+#define bFM3_GPIO_DDR4_P1                      *((volatile unsigned int*)(0x42664204UL))
+#define bFM3_GPIO_DDR4_P2                      *((volatile unsigned int*)(0x42664208UL))
+#define bFM3_GPIO_DDR4_P3                      *((volatile unsigned int*)(0x4266420CUL))
+#define bFM3_GPIO_DDR4_P4                      *((volatile unsigned int*)(0x42664210UL))
+#define bFM3_GPIO_DDR4_P5                      *((volatile unsigned int*)(0x42664214UL))
+#define bFM3_GPIO_DDR4_P6                      *((volatile unsigned int*)(0x42664218UL))
+#define bFM3_GPIO_DDR4_P7                      *((volatile unsigned int*)(0x4266421CUL))
+#define bFM3_GPIO_DDR4_P8                      *((volatile unsigned int*)(0x42664220UL))
+#define bFM3_GPIO_DDR4_P9                      *((volatile unsigned int*)(0x42664224UL))
+#define bFM3_GPIO_DDR4_PA                      *((volatile unsigned int*)(0x42664228UL))
+#define bFM3_GPIO_DDR4_PB                      *((volatile unsigned int*)(0x4266422CUL))
+#define bFM3_GPIO_DDR4_PC                      *((volatile unsigned int*)(0x42664230UL))
+#define bFM3_GPIO_DDR4_PD                      *((volatile unsigned int*)(0x42664234UL))
+#define bFM3_GPIO_DDR4_PE                      *((volatile unsigned int*)(0x42664238UL))
+#define bFM3_GPIO_DDR5_P0                      *((volatile unsigned int*)(0x42664280UL))
+#define bFM3_GPIO_DDR5_P1                      *((volatile unsigned int*)(0x42664284UL))
+#define bFM3_GPIO_DDR5_P2                      *((volatile unsigned int*)(0x42664288UL))
+#define bFM3_GPIO_DDR5_P3                      *((volatile unsigned int*)(0x4266428CUL))
+#define bFM3_GPIO_DDR5_P4                      *((volatile unsigned int*)(0x42664290UL))
+#define bFM3_GPIO_DDR5_P5                      *((volatile unsigned int*)(0x42664294UL))
+#define bFM3_GPIO_DDR5_P6                      *((volatile unsigned int*)(0x42664298UL))
+#define bFM3_GPIO_DDR5_P7                      *((volatile unsigned int*)(0x4266429CUL))
+#define bFM3_GPIO_DDR5_P8                      *((volatile unsigned int*)(0x426642A0UL))
+#define bFM3_GPIO_DDR5_P9                      *((volatile unsigned int*)(0x426642A4UL))
+#define bFM3_GPIO_DDR5_PA                      *((volatile unsigned int*)(0x426642A8UL))
+#define bFM3_GPIO_DDR5_PB                      *((volatile unsigned int*)(0x426642ACUL))
+#define bFM3_GPIO_DDR5_PC                      *((volatile unsigned int*)(0x426642B0UL))
+#define bFM3_GPIO_DDR5_PD                      *((volatile unsigned int*)(0x426642B4UL))
+#define bFM3_GPIO_DDR6_P0                      *((volatile unsigned int*)(0x42664300UL))
+#define bFM3_GPIO_DDR6_P1                      *((volatile unsigned int*)(0x42664304UL))
+#define bFM3_GPIO_DDR6_P2                      *((volatile unsigned int*)(0x42664308UL))
+#define bFM3_GPIO_DDR7_P0                      *((volatile unsigned int*)(0x42664380UL))
+#define bFM3_GPIO_DDR7_P1                      *((volatile unsigned int*)(0x42664384UL))
+#define bFM3_GPIO_DDR7_P2                      *((volatile unsigned int*)(0x42664388UL))
+#define bFM3_GPIO_DDR7_P3                      *((volatile unsigned int*)(0x4266438CUL))
+#define bFM3_GPIO_DDR7_P4                      *((volatile unsigned int*)(0x42664390UL))
+#define bFM3_GPIO_DDR7_P5                      *((volatile unsigned int*)(0x42664394UL))
+#define bFM3_GPIO_DDR7_P6                      *((volatile unsigned int*)(0x42664398UL))
+#define bFM3_GPIO_DDR7_P7                      *((volatile unsigned int*)(0x4266439CUL))
+#define bFM3_GPIO_DDR7_P8                      *((volatile unsigned int*)(0x426643A0UL))
+#define bFM3_GPIO_DDR7_P9                      *((volatile unsigned int*)(0x426643A4UL))
+#define bFM3_GPIO_DDR7_PA                      *((volatile unsigned int*)(0x426643A8UL))
+#define bFM3_GPIO_DDR7_PB                      *((volatile unsigned int*)(0x426643ACUL))
+#define bFM3_GPIO_DDR7_PC                      *((volatile unsigned int*)(0x426643B0UL))
+#define bFM3_GPIO_DDR7_PD                      *((volatile unsigned int*)(0x426643B4UL))
+#define bFM3_GPIO_DDR7_PE                      *((volatile unsigned int*)(0x426643B8UL))
+#define bFM3_GPIO_DDR7_PF                      *((volatile unsigned int*)(0x426643BCUL))
+#define bFM3_GPIO_DDR8_P0                      *((volatile unsigned int*)(0x42664400UL))
+#define bFM3_GPIO_DDR8_P1                      *((volatile unsigned int*)(0x42664404UL))
+#define bFM3_GPIO_DDR8_P2                      *((volatile unsigned int*)(0x42664408UL))
+#define bFM3_GPIO_DDR8_P3                      *((volatile unsigned int*)(0x4266440CUL))
+#define bFM3_GPIO_DDR9_P0                      *((volatile unsigned int*)(0x42664480UL))
+#define bFM3_GPIO_DDR9_P1                      *((volatile unsigned int*)(0x42664484UL))
+#define bFM3_GPIO_DDR9_P2                      *((volatile unsigned int*)(0x42664488UL))
+#define bFM3_GPIO_DDR9_P3                      *((volatile unsigned int*)(0x4266448CUL))
+#define bFM3_GPIO_DDR9_P4                      *((volatile unsigned int*)(0x42664490UL))
+#define bFM3_GPIO_DDR9_P5                      *((volatile unsigned int*)(0x42664494UL))
+#define bFM3_GPIO_DDRA_P0                      *((volatile unsigned int*)(0x42664500UL))
+#define bFM3_GPIO_DDRA_P1                      *((volatile unsigned int*)(0x42664504UL))
+#define bFM3_GPIO_DDRA_P2                      *((volatile unsigned int*)(0x42664508UL))
+#define bFM3_GPIO_DDRA_P3                      *((volatile unsigned int*)(0x4266450CUL))
+#define bFM3_GPIO_DDRA_P4                      *((volatile unsigned int*)(0x42664510UL))
+#define bFM3_GPIO_DDRA_P5                      *((volatile unsigned int*)(0x42664514UL))
+#define bFM3_GPIO_DDRB_P0                      *((volatile unsigned int*)(0x42664580UL))
+#define bFM3_GPIO_DDRB_P1                      *((volatile unsigned int*)(0x42664584UL))
+#define bFM3_GPIO_DDRB_P2                      *((volatile unsigned int*)(0x42664588UL))
+#define bFM3_GPIO_DDRB_P3                      *((volatile unsigned int*)(0x4266458CUL))
+#define bFM3_GPIO_DDRB_P4                      *((volatile unsigned int*)(0x42664590UL))
+#define bFM3_GPIO_DDRB_P5                      *((volatile unsigned int*)(0x42664594UL))
+#define bFM3_GPIO_DDRB_P6                      *((volatile unsigned int*)(0x42664598UL))
+#define bFM3_GPIO_DDRB_P7                      *((volatile unsigned int*)(0x4266459CUL))
+#define bFM3_GPIO_DDRC_P0                      *((volatile unsigned int*)(0x42664600UL))
+#define bFM3_GPIO_DDRC_P1                      *((volatile unsigned int*)(0x42664604UL))
+#define bFM3_GPIO_DDRC_P2                      *((volatile unsigned int*)(0x42664608UL))
+#define bFM3_GPIO_DDRC_P3                      *((volatile unsigned int*)(0x4266460CUL))
+#define bFM3_GPIO_DDRC_P4                      *((volatile unsigned int*)(0x42664610UL))
+#define bFM3_GPIO_DDRC_P5                      *((volatile unsigned int*)(0x42664614UL))
+#define bFM3_GPIO_DDRC_P6                      *((volatile unsigned int*)(0x42664618UL))
+#define bFM3_GPIO_DDRC_P7                      *((volatile unsigned int*)(0x4266461CUL))
+#define bFM3_GPIO_DDRC_P8                      *((volatile unsigned int*)(0x42664620UL))
+#define bFM3_GPIO_DDRC_P9                      *((volatile unsigned int*)(0x42664624UL))
+#define bFM3_GPIO_DDRC_PA                      *((volatile unsigned int*)(0x42664628UL))
+#define bFM3_GPIO_DDRC_PB                      *((volatile unsigned int*)(0x4266462CUL))
+#define bFM3_GPIO_DDRC_PC                      *((volatile unsigned int*)(0x42664630UL))
+#define bFM3_GPIO_DDRC_PD                      *((volatile unsigned int*)(0x42664634UL))
+#define bFM3_GPIO_DDRC_PE                      *((volatile unsigned int*)(0x42664638UL))
+#define bFM3_GPIO_DDRC_PF                      *((volatile unsigned int*)(0x4266463CUL))
+#define bFM3_GPIO_DDRD_P0                      *((volatile unsigned int*)(0x42664680UL))
+#define bFM3_GPIO_DDRD_P1                      *((volatile unsigned int*)(0x42664684UL))
+#define bFM3_GPIO_DDRD_P2                      *((volatile unsigned int*)(0x42664688UL))
+#define bFM3_GPIO_DDRD_P3                      *((volatile unsigned int*)(0x4266468CUL))
+#define bFM3_GPIO_DDRE_P0                      *((volatile unsigned int*)(0x42664700UL))
+#define bFM3_GPIO_DDRE_P2                      *((volatile unsigned int*)(0x42664708UL))
+#define bFM3_GPIO_DDRE_P3                      *((volatile unsigned int*)(0x4266470CUL))
+#define bFM3_GPIO_DDRF_P0                      *((volatile unsigned int*)(0x42664780UL))
+#define bFM3_GPIO_DDRF_P1                      *((volatile unsigned int*)(0x42664784UL))
+#define bFM3_GPIO_DDRF_P2                      *((volatile unsigned int*)(0x42664788UL))
+#define bFM3_GPIO_DDRF_P3                      *((volatile unsigned int*)(0x4266478CUL))
+#define bFM3_GPIO_DDRF_P4                      *((volatile unsigned int*)(0x42664790UL))
+#define bFM3_GPIO_DDRF_P5                      *((volatile unsigned int*)(0x42664794UL))
+#define bFM3_GPIO_DDRF_P6                      *((volatile unsigned int*)(0x42664798UL))
+#define bFM3_GPIO_PDIR0_P0                     *((volatile unsigned int*)(0x42666000UL))
+#define bFM3_GPIO_PDIR0_P1                     *((volatile unsigned int*)(0x42666004UL))
+#define bFM3_GPIO_PDIR0_P2                     *((volatile unsigned int*)(0x42666008UL))
+#define bFM3_GPIO_PDIR0_P3                     *((volatile unsigned int*)(0x4266600CUL))
+#define bFM3_GPIO_PDIR0_P4                     *((volatile unsigned int*)(0x42666010UL))
+#define bFM3_GPIO_PDIR0_P5                     *((volatile unsigned int*)(0x42666014UL))
+#define bFM3_GPIO_PDIR0_P6                     *((volatile unsigned int*)(0x42666018UL))
+#define bFM3_GPIO_PDIR0_P7                     *((volatile unsigned int*)(0x4266601CUL))
+#define bFM3_GPIO_PDIR0_P8                     *((volatile unsigned int*)(0x42666020UL))
+#define bFM3_GPIO_PDIR0_P9                     *((volatile unsigned int*)(0x42666024UL))
+#define bFM3_GPIO_PDIR1_P0                     *((volatile unsigned int*)(0x42666080UL))
+#define bFM3_GPIO_PDIR1_P1                     *((volatile unsigned int*)(0x42666084UL))
+#define bFM3_GPIO_PDIR1_P2                     *((volatile unsigned int*)(0x42666088UL))
+#define bFM3_GPIO_PDIR1_P3                     *((volatile unsigned int*)(0x4266608CUL))
+#define bFM3_GPIO_PDIR1_P4                     *((volatile unsigned int*)(0x42666090UL))
+#define bFM3_GPIO_PDIR1_P5                     *((volatile unsigned int*)(0x42666094UL))
+#define bFM3_GPIO_PDIR1_P6                     *((volatile unsigned int*)(0x42666098UL))
+#define bFM3_GPIO_PDIR1_P7                     *((volatile unsigned int*)(0x4266609CUL))
+#define bFM3_GPIO_PDIR1_P8                     *((volatile unsigned int*)(0x426660A0UL))
+#define bFM3_GPIO_PDIR1_P9                     *((volatile unsigned int*)(0x426660A4UL))
+#define bFM3_GPIO_PDIR1_PA                     *((volatile unsigned int*)(0x426660A8UL))
+#define bFM3_GPIO_PDIR1_PB                     *((volatile unsigned int*)(0x426660ACUL))
+#define bFM3_GPIO_PDIR1_PC                     *((volatile unsigned int*)(0x426660B0UL))
+#define bFM3_GPIO_PDIR1_PD                     *((volatile unsigned int*)(0x426660B4UL))
+#define bFM3_GPIO_PDIR1_PE                     *((volatile unsigned int*)(0x426660B8UL))
+#define bFM3_GPIO_PDIR1_PF                     *((volatile unsigned int*)(0x426660BCUL))
+#define bFM3_GPIO_PDIR2_P0                     *((volatile unsigned int*)(0x42666100UL))
+#define bFM3_GPIO_PDIR2_P1                     *((volatile unsigned int*)(0x42666104UL))
+#define bFM3_GPIO_PDIR2_P2                     *((volatile unsigned int*)(0x42666108UL))
+#define bFM3_GPIO_PDIR2_P3                     *((volatile unsigned int*)(0x4266610CUL))
+#define bFM3_GPIO_PDIR2_P4                     *((volatile unsigned int*)(0x42666110UL))
+#define bFM3_GPIO_PDIR2_P5                     *((volatile unsigned int*)(0x42666114UL))
+#define bFM3_GPIO_PDIR2_P6                     *((volatile unsigned int*)(0x42666118UL))
+#define bFM3_GPIO_PDIR2_P7                     *((volatile unsigned int*)(0x4266611CUL))
+#define bFM3_GPIO_PDIR2_P8                     *((volatile unsigned int*)(0x42666120UL))
+#define bFM3_GPIO_PDIR2_P9                     *((volatile unsigned int*)(0x42666124UL))
+#define bFM3_GPIO_PDIR3_P0                     *((volatile unsigned int*)(0x42666180UL))
+#define bFM3_GPIO_PDIR3_P1                     *((volatile unsigned int*)(0x42666184UL))
+#define bFM3_GPIO_PDIR3_P2                     *((volatile unsigned int*)(0x42666188UL))
+#define bFM3_GPIO_PDIR3_P3                     *((volatile unsigned int*)(0x4266618CUL))
+#define bFM3_GPIO_PDIR3_P4                     *((volatile unsigned int*)(0x42666190UL))
+#define bFM3_GPIO_PDIR3_P5                     *((volatile unsigned int*)(0x42666194UL))
+#define bFM3_GPIO_PDIR3_P6                     *((volatile unsigned int*)(0x42666198UL))
+#define bFM3_GPIO_PDIR3_P7                     *((volatile unsigned int*)(0x4266619CUL))
+#define bFM3_GPIO_PDIR3_P8                     *((volatile unsigned int*)(0x426661A0UL))
+#define bFM3_GPIO_PDIR3_P9                     *((volatile unsigned int*)(0x426661A4UL))
+#define bFM3_GPIO_PDIR3_PA                     *((volatile unsigned int*)(0x426661A8UL))
+#define bFM3_GPIO_PDIR3_PB                     *((volatile unsigned int*)(0x426661ACUL))
+#define bFM3_GPIO_PDIR3_PC                     *((volatile unsigned int*)(0x426661B0UL))
+#define bFM3_GPIO_PDIR3_PD                     *((volatile unsigned int*)(0x426661B4UL))
+#define bFM3_GPIO_PDIR3_PE                     *((volatile unsigned int*)(0x426661B8UL))
+#define bFM3_GPIO_PDIR3_PF                     *((volatile unsigned int*)(0x426661BCUL))
+#define bFM3_GPIO_PDIR4_P0                     *((volatile unsigned int*)(0x42666200UL))
+#define bFM3_GPIO_PDIR4_P1                     *((volatile unsigned int*)(0x42666204UL))
+#define bFM3_GPIO_PDIR4_P2                     *((volatile unsigned int*)(0x42666208UL))
+#define bFM3_GPIO_PDIR4_P3                     *((volatile unsigned int*)(0x4266620CUL))
+#define bFM3_GPIO_PDIR4_P4                     *((volatile unsigned int*)(0x42666210UL))
+#define bFM3_GPIO_PDIR4_P5                     *((volatile unsigned int*)(0x42666214UL))
+#define bFM3_GPIO_PDIR4_P6                     *((volatile unsigned int*)(0x42666218UL))
+#define bFM3_GPIO_PDIR4_P7                     *((volatile unsigned int*)(0x4266621CUL))
+#define bFM3_GPIO_PDIR4_P8                     *((volatile unsigned int*)(0x42666220UL))
+#define bFM3_GPIO_PDIR4_P9                     *((volatile unsigned int*)(0x42666224UL))
+#define bFM3_GPIO_PDIR4_PA                     *((volatile unsigned int*)(0x42666228UL))
+#define bFM3_GPIO_PDIR4_PB                     *((volatile unsigned int*)(0x4266622CUL))
+#define bFM3_GPIO_PDIR4_PC                     *((volatile unsigned int*)(0x42666230UL))
+#define bFM3_GPIO_PDIR4_PD                     *((volatile unsigned int*)(0x42666234UL))
+#define bFM3_GPIO_PDIR4_PE                     *((volatile unsigned int*)(0x42666238UL))
+#define bFM3_GPIO_PDIR5_P0                     *((volatile unsigned int*)(0x42666280UL))
+#define bFM3_GPIO_PDIR5_P1                     *((volatile unsigned int*)(0x42666284UL))
+#define bFM3_GPIO_PDIR5_P2                     *((volatile unsigned int*)(0x42666288UL))
+#define bFM3_GPIO_PDIR5_P3                     *((volatile unsigned int*)(0x4266628CUL))
+#define bFM3_GPIO_PDIR5_P4                     *((volatile unsigned int*)(0x42666290UL))
+#define bFM3_GPIO_PDIR5_P5                     *((volatile unsigned int*)(0x42666294UL))
+#define bFM3_GPIO_PDIR5_P6                     *((volatile unsigned int*)(0x42666298UL))
+#define bFM3_GPIO_PDIR5_P7                     *((volatile unsigned int*)(0x4266629CUL))
+#define bFM3_GPIO_PDIR5_P8                     *((volatile unsigned int*)(0x426662A0UL))
+#define bFM3_GPIO_PDIR5_P9                     *((volatile unsigned int*)(0x426662A4UL))
+#define bFM3_GPIO_PDIR5_PA                     *((volatile unsigned int*)(0x426662A8UL))
+#define bFM3_GPIO_PDIR5_PB                     *((volatile unsigned int*)(0x426662ACUL))
+#define bFM3_GPIO_PDIR5_PC                     *((volatile unsigned int*)(0x426662B0UL))
+#define bFM3_GPIO_PDIR5_PD                     *((volatile unsigned int*)(0x426662B4UL))
+#define bFM3_GPIO_PDIR6_P0                     *((volatile unsigned int*)(0x42666300UL))
+#define bFM3_GPIO_PDIR6_P1                     *((volatile unsigned int*)(0x42666304UL))
+#define bFM3_GPIO_PDIR6_P2                     *((volatile unsigned int*)(0x42666308UL))
+#define bFM3_GPIO_PDIR7_P0                     *((volatile unsigned int*)(0x42666380UL))
+#define bFM3_GPIO_PDIR7_P1                     *((volatile unsigned int*)(0x42666384UL))
+#define bFM3_GPIO_PDIR7_P2                     *((volatile unsigned int*)(0x42666388UL))
+#define bFM3_GPIO_PDIR7_P3                     *((volatile unsigned int*)(0x4266638CUL))
+#define bFM3_GPIO_PDIR7_P4                     *((volatile unsigned int*)(0x42666390UL))
+#define bFM3_GPIO_PDIR7_P5                     *((volatile unsigned int*)(0x42666394UL))
+#define bFM3_GPIO_PDIR7_P6                     *((volatile unsigned int*)(0x42666398UL))
+#define bFM3_GPIO_PDIR7_P7                     *((volatile unsigned int*)(0x4266639CUL))
+#define bFM3_GPIO_PDIR7_P8                     *((volatile unsigned int*)(0x426663A0UL))
+#define bFM3_GPIO_PDIR7_P9                     *((volatile unsigned int*)(0x426663A4UL))
+#define bFM3_GPIO_PDIR7_PA                     *((volatile unsigned int*)(0x426663A8UL))
+#define bFM3_GPIO_PDIR7_PB                     *((volatile unsigned int*)(0x426663ACUL))
+#define bFM3_GPIO_PDIR7_PC                     *((volatile unsigned int*)(0x426663B0UL))
+#define bFM3_GPIO_PDIR7_PD                     *((volatile unsigned int*)(0x426663B4UL))
+#define bFM3_GPIO_PDIR7_PE                     *((volatile unsigned int*)(0x426663B8UL))
+#define bFM3_GPIO_PDIR7_PF                     *((volatile unsigned int*)(0x426663BCUL))
+#define bFM3_GPIO_PDIR8_P0                     *((volatile unsigned int*)(0x42666400UL))
+#define bFM3_GPIO_PDIR8_P1                     *((volatile unsigned int*)(0x42666404UL))
+#define bFM3_GPIO_PDIR8_P2                     *((volatile unsigned int*)(0x42666408UL))
+#define bFM3_GPIO_PDIR8_P3                     *((volatile unsigned int*)(0x4266640CUL))
+#define bFM3_GPIO_PDIR9_P0                     *((volatile unsigned int*)(0x42666480UL))
+#define bFM3_GPIO_PDIR9_P1                     *((volatile unsigned int*)(0x42666484UL))
+#define bFM3_GPIO_PDIR9_P2                     *((volatile unsigned int*)(0x42666488UL))
+#define bFM3_GPIO_PDIR9_P3                     *((volatile unsigned int*)(0x4266648CUL))
+#define bFM3_GPIO_PDIR9_P4                     *((volatile unsigned int*)(0x42666490UL))
+#define bFM3_GPIO_PDIR9_P5                     *((volatile unsigned int*)(0x42666494UL))
+#define bFM3_GPIO_PDIRA_P0                     *((volatile unsigned int*)(0x42666500UL))
+#define bFM3_GPIO_PDIRA_P1                     *((volatile unsigned int*)(0x42666504UL))
+#define bFM3_GPIO_PDIRA_P2                     *((volatile unsigned int*)(0x42666508UL))
+#define bFM3_GPIO_PDIRA_P3                     *((volatile unsigned int*)(0x4266650CUL))
+#define bFM3_GPIO_PDIRA_P4                     *((volatile unsigned int*)(0x42666510UL))
+#define bFM3_GPIO_PDIRA_P5                     *((volatile unsigned int*)(0x42666514UL))
+#define bFM3_GPIO_PDIRB_P0                     *((volatile unsigned int*)(0x42666580UL))
+#define bFM3_GPIO_PDIRB_P1                     *((volatile unsigned int*)(0x42666584UL))
+#define bFM3_GPIO_PDIRB_P2                     *((volatile unsigned int*)(0x42666588UL))
+#define bFM3_GPIO_PDIRB_P3                     *((volatile unsigned int*)(0x4266658CUL))
+#define bFM3_GPIO_PDIRB_P4                     *((volatile unsigned int*)(0x42666590UL))
+#define bFM3_GPIO_PDIRB_P5                     *((volatile unsigned int*)(0x42666594UL))
+#define bFM3_GPIO_PDIRB_P6                     *((volatile unsigned int*)(0x42666598UL))
+#define bFM3_GPIO_PDIRB_P7                     *((volatile unsigned int*)(0x4266659CUL))
+#define bFM3_GPIO_PDIRC_P0                     *((volatile unsigned int*)(0x42666600UL))
+#define bFM3_GPIO_PDIRC_P1                     *((volatile unsigned int*)(0x42666604UL))
+#define bFM3_GPIO_PDIRC_P2                     *((volatile unsigned int*)(0x42666608UL))
+#define bFM3_GPIO_PDIRC_P3                     *((volatile unsigned int*)(0x4266660CUL))
+#define bFM3_GPIO_PDIRC_P4                     *((volatile unsigned int*)(0x42666610UL))
+#define bFM3_GPIO_PDIRC_P5                     *((volatile unsigned int*)(0x42666614UL))
+#define bFM3_GPIO_PDIRC_P6                     *((volatile unsigned int*)(0x42666618UL))
+#define bFM3_GPIO_PDIRC_P7                     *((volatile unsigned int*)(0x4266661CUL))
+#define bFM3_GPIO_PDIRC_P8                     *((volatile unsigned int*)(0x42666620UL))
+#define bFM3_GPIO_PDIRC_P9                     *((volatile unsigned int*)(0x42666624UL))
+#define bFM3_GPIO_PDIRC_PA                     *((volatile unsigned int*)(0x42666628UL))
+#define bFM3_GPIO_PDIRC_PB                     *((volatile unsigned int*)(0x4266662CUL))
+#define bFM3_GPIO_PDIRC_PC                     *((volatile unsigned int*)(0x42666630UL))
+#define bFM3_GPIO_PDIRC_PD                     *((volatile unsigned int*)(0x42666634UL))
+#define bFM3_GPIO_PDIRC_PE                     *((volatile unsigned int*)(0x42666638UL))
+#define bFM3_GPIO_PDIRC_PF                     *((volatile unsigned int*)(0x4266663CUL))
+#define bFM3_GPIO_PDIRD_P0                     *((volatile unsigned int*)(0x42666680UL))
+#define bFM3_GPIO_PDIRD_P1                     *((volatile unsigned int*)(0x42666684UL))
+#define bFM3_GPIO_PDIRD_P2                     *((volatile unsigned int*)(0x42666688UL))
+#define bFM3_GPIO_PDIRD_P3                     *((volatile unsigned int*)(0x4266668CUL))
+#define bFM3_GPIO_PDIRE_P0                     *((volatile unsigned int*)(0x42666700UL))
+#define bFM3_GPIO_PDIRE_P2                     *((volatile unsigned int*)(0x42666708UL))
+#define bFM3_GPIO_PDIRE_P3                     *((volatile unsigned int*)(0x4266670CUL))
+#define bFM3_GPIO_PDIRF_P0                     *((volatile unsigned int*)(0x42666780UL))
+#define bFM3_GPIO_PDIRF_P1                     *((volatile unsigned int*)(0x42666784UL))
+#define bFM3_GPIO_PDIRF_P2                     *((volatile unsigned int*)(0x42666788UL))
+#define bFM3_GPIO_PDIRF_P3                     *((volatile unsigned int*)(0x4266678CUL))
+#define bFM3_GPIO_PDIRF_P4                     *((volatile unsigned int*)(0x42666790UL))
+#define bFM3_GPIO_PDIRF_P5                     *((volatile unsigned int*)(0x42666794UL))
+#define bFM3_GPIO_PDIRF_P6                     *((volatile unsigned int*)(0x42666798UL))
+#define bFM3_GPIO_PDOR0_P0                     *((volatile unsigned int*)(0x42668000UL))
+#define bFM3_GPIO_PDOR0_P1                     *((volatile unsigned int*)(0x42668004UL))
+#define bFM3_GPIO_PDOR0_P2                     *((volatile unsigned int*)(0x42668008UL))
+#define bFM3_GPIO_PDOR0_P3                     *((volatile unsigned int*)(0x4266800CUL))
+#define bFM3_GPIO_PDOR0_P4                     *((volatile unsigned int*)(0x42668010UL))
+#define bFM3_GPIO_PDOR0_P5                     *((volatile unsigned int*)(0x42668014UL))
+#define bFM3_GPIO_PDOR0_P6                     *((volatile unsigned int*)(0x42668018UL))
+#define bFM3_GPIO_PDOR0_P7                     *((volatile unsigned int*)(0x4266801CUL))
+#define bFM3_GPIO_PDOR0_P8                     *((volatile unsigned int*)(0x42668020UL))
+#define bFM3_GPIO_PDOR0_P9                     *((volatile unsigned int*)(0x42668024UL))
+#define bFM3_GPIO_PDOR1_P0                     *((volatile unsigned int*)(0x42668080UL))
+#define bFM3_GPIO_PDOR1_P1                     *((volatile unsigned int*)(0x42668084UL))
+#define bFM3_GPIO_PDOR1_P2                     *((volatile unsigned int*)(0x42668088UL))
+#define bFM3_GPIO_PDOR1_P3                     *((volatile unsigned int*)(0x4266808CUL))
+#define bFM3_GPIO_PDOR1_P4                     *((volatile unsigned int*)(0x42668090UL))
+#define bFM3_GPIO_PDOR1_P5                     *((volatile unsigned int*)(0x42668094UL))
+#define bFM3_GPIO_PDOR1_P6                     *((volatile unsigned int*)(0x42668098UL))
+#define bFM3_GPIO_PDOR1_P7                     *((volatile unsigned int*)(0x4266809CUL))
+#define bFM3_GPIO_PDOR1_P8                     *((volatile unsigned int*)(0x426680A0UL))
+#define bFM3_GPIO_PDOR1_P9                     *((volatile unsigned int*)(0x426680A4UL))
+#define bFM3_GPIO_PDOR1_PA                     *((volatile unsigned int*)(0x426680A8UL))
+#define bFM3_GPIO_PDOR1_PB                     *((volatile unsigned int*)(0x426680ACUL))
+#define bFM3_GPIO_PDOR1_PC                     *((volatile unsigned int*)(0x426680B0UL))
+#define bFM3_GPIO_PDOR1_PD                     *((volatile unsigned int*)(0x426680B4UL))
+#define bFM3_GPIO_PDOR1_PE                     *((volatile unsigned int*)(0x426680B8UL))
+#define bFM3_GPIO_PDOR1_PF                     *((volatile unsigned int*)(0x426680BCUL))
+#define bFM3_GPIO_PDOR2_P0                     *((volatile unsigned int*)(0x42668100UL))
+#define bFM3_GPIO_PDOR2_P1                     *((volatile unsigned int*)(0x42668104UL))
+#define bFM3_GPIO_PDOR2_P2                     *((volatile unsigned int*)(0x42668108UL))
+#define bFM3_GPIO_PDOR2_P3                     *((volatile unsigned int*)(0x4266810CUL))
+#define bFM3_GPIO_PDOR2_P4                     *((volatile unsigned int*)(0x42668110UL))
+#define bFM3_GPIO_PDOR2_P5                     *((volatile unsigned int*)(0x42668114UL))
+#define bFM3_GPIO_PDOR2_P6                     *((volatile unsigned int*)(0x42668118UL))
+#define bFM3_GPIO_PDOR2_P7                     *((volatile unsigned int*)(0x4266811CUL))
+#define bFM3_GPIO_PDOR2_P8                     *((volatile unsigned int*)(0x42668120UL))
+#define bFM3_GPIO_PDOR2_P9                     *((volatile unsigned int*)(0x42668124UL))
+#define bFM3_GPIO_PDOR3_P0                     *((volatile unsigned int*)(0x42668180UL))
+#define bFM3_GPIO_PDOR3_P1                     *((volatile unsigned int*)(0x42668184UL))
+#define bFM3_GPIO_PDOR3_P2                     *((volatile unsigned int*)(0x42668188UL))
+#define bFM3_GPIO_PDOR3_P3                     *((volatile unsigned int*)(0x4266818CUL))
+#define bFM3_GPIO_PDOR3_P4                     *((volatile unsigned int*)(0x42668190UL))
+#define bFM3_GPIO_PDOR3_P5                     *((volatile unsigned int*)(0x42668194UL))
+#define bFM3_GPIO_PDOR3_P6                     *((volatile unsigned int*)(0x42668198UL))
+#define bFM3_GPIO_PDOR3_P7                     *((volatile unsigned int*)(0x4266819CUL))
+#define bFM3_GPIO_PDOR3_P8                     *((volatile unsigned int*)(0x426681A0UL))
+#define bFM3_GPIO_PDOR3_P9                     *((volatile unsigned int*)(0x426681A4UL))
+#define bFM3_GPIO_PDOR3_PA                     *((volatile unsigned int*)(0x426681A8UL))
+#define bFM3_GPIO_PDOR3_PB                     *((volatile unsigned int*)(0x426681ACUL))
+#define bFM3_GPIO_PDOR3_PC                     *((volatile unsigned int*)(0x426681B0UL))
+#define bFM3_GPIO_PDOR3_PD                     *((volatile unsigned int*)(0x426681B4UL))
+#define bFM3_GPIO_PDOR3_PE                     *((volatile unsigned int*)(0x426681B8UL))
+#define bFM3_GPIO_PDOR3_PF                     *((volatile unsigned int*)(0x426681BCUL))
+#define bFM3_GPIO_PDOR4_P0                     *((volatile unsigned int*)(0x42668200UL))
+#define bFM3_GPIO_PDOR4_P1                     *((volatile unsigned int*)(0x42668204UL))
+#define bFM3_GPIO_PDOR4_P2                     *((volatile unsigned int*)(0x42668208UL))
+#define bFM3_GPIO_PDOR4_P3                     *((volatile unsigned int*)(0x4266820CUL))
+#define bFM3_GPIO_PDOR4_P4                     *((volatile unsigned int*)(0x42668210UL))
+#define bFM3_GPIO_PDOR4_P5                     *((volatile unsigned int*)(0x42668214UL))
+#define bFM3_GPIO_PDOR4_P6                     *((volatile unsigned int*)(0x42668218UL))
+#define bFM3_GPIO_PDOR4_P7                     *((volatile unsigned int*)(0x4266821CUL))
+#define bFM3_GPIO_PDOR4_P8                     *((volatile unsigned int*)(0x42668220UL))
+#define bFM3_GPIO_PDOR4_P9                     *((volatile unsigned int*)(0x42668224UL))
+#define bFM3_GPIO_PDOR4_PA                     *((volatile unsigned int*)(0x42668228UL))
+#define bFM3_GPIO_PDOR4_PB                     *((volatile unsigned int*)(0x4266822CUL))
+#define bFM3_GPIO_PDOR4_PC                     *((volatile unsigned int*)(0x42668230UL))
+#define bFM3_GPIO_PDOR4_PD                     *((volatile unsigned int*)(0x42668234UL))
+#define bFM3_GPIO_PDOR4_PE                     *((volatile unsigned int*)(0x42668238UL))
+#define bFM3_GPIO_PDOR5_P0                     *((volatile unsigned int*)(0x42668280UL))
+#define bFM3_GPIO_PDOR5_P1                     *((volatile unsigned int*)(0x42668284UL))
+#define bFM3_GPIO_PDOR5_P2                     *((volatile unsigned int*)(0x42668288UL))
+#define bFM3_GPIO_PDOR5_P3                     *((volatile unsigned int*)(0x4266828CUL))
+#define bFM3_GPIO_PDOR5_P4                     *((volatile unsigned int*)(0x42668290UL))
+#define bFM3_GPIO_PDOR5_P5                     *((volatile unsigned int*)(0x42668294UL))
+#define bFM3_GPIO_PDOR5_P6                     *((volatile unsigned int*)(0x42668298UL))
+#define bFM3_GPIO_PDOR5_P7                     *((volatile unsigned int*)(0x4266829CUL))
+#define bFM3_GPIO_PDOR5_P8                     *((volatile unsigned int*)(0x426682A0UL))
+#define bFM3_GPIO_PDOR5_P9                     *((volatile unsigned int*)(0x426682A4UL))
+#define bFM3_GPIO_PDOR5_PA                     *((volatile unsigned int*)(0x426682A8UL))
+#define bFM3_GPIO_PDOR5_PB                     *((volatile unsigned int*)(0x426682ACUL))
+#define bFM3_GPIO_PDOR5_PC                     *((volatile unsigned int*)(0x426682B0UL))
+#define bFM3_GPIO_PDOR5_PD                     *((volatile unsigned int*)(0x426682B4UL))
+#define bFM3_GPIO_PDOR6_P0                     *((volatile unsigned int*)(0x42668300UL))
+#define bFM3_GPIO_PDOR6_P1                     *((volatile unsigned int*)(0x42668304UL))
+#define bFM3_GPIO_PDOR6_P2                     *((volatile unsigned int*)(0x42668308UL))
+#define bFM3_GPIO_PDOR7_P0                     *((volatile unsigned int*)(0x42668380UL))
+#define bFM3_GPIO_PDOR7_P1                     *((volatile unsigned int*)(0x42668384UL))
+#define bFM3_GPIO_PDOR7_P2                     *((volatile unsigned int*)(0x42668388UL))
+#define bFM3_GPIO_PDOR7_P3                     *((volatile unsigned int*)(0x4266838CUL))
+#define bFM3_GPIO_PDOR7_P4                     *((volatile unsigned int*)(0x42668390UL))
+#define bFM3_GPIO_PDOR7_P5                     *((volatile unsigned int*)(0x42668394UL))
+#define bFM3_GPIO_PDOR7_P6                     *((volatile unsigned int*)(0x42668398UL))
+#define bFM3_GPIO_PDOR7_P7                     *((volatile unsigned int*)(0x4266839CUL))
+#define bFM3_GPIO_PDOR7_P8                     *((volatile unsigned int*)(0x426683A0UL))
+#define bFM3_GPIO_PDOR7_P9                     *((volatile unsigned int*)(0x426683A4UL))
+#define bFM3_GPIO_PDOR7_PA                     *((volatile unsigned int*)(0x426683A8UL))
+#define bFM3_GPIO_PDOR7_PB                     *((volatile unsigned int*)(0x426683ACUL))
+#define bFM3_GPIO_PDOR7_PC                     *((volatile unsigned int*)(0x426683B0UL))
+#define bFM3_GPIO_PDOR7_PD                     *((volatile unsigned int*)(0x426683B4UL))
+#define bFM3_GPIO_PDOR7_PE                     *((volatile unsigned int*)(0x426683B8UL))
+#define bFM3_GPIO_PDOR7_PF                     *((volatile unsigned int*)(0x426683BCUL))
+#define bFM3_GPIO_PDOR8_P0                     *((volatile unsigned int*)(0x42668400UL))
+#define bFM3_GPIO_PDOR8_P1                     *((volatile unsigned int*)(0x42668404UL))
+#define bFM3_GPIO_PDOR8_P2                     *((volatile unsigned int*)(0x42668408UL))
+#define bFM3_GPIO_PDOR8_P3                     *((volatile unsigned int*)(0x4266840CUL))
+#define bFM3_GPIO_PDOR9_P0                     *((volatile unsigned int*)(0x42668480UL))
+#define bFM3_GPIO_PDOR9_P1                     *((volatile unsigned int*)(0x42668484UL))
+#define bFM3_GPIO_PDOR9_P2                     *((volatile unsigned int*)(0x42668488UL))
+#define bFM3_GPIO_PDOR9_P3                     *((volatile unsigned int*)(0x4266848CUL))
+#define bFM3_GPIO_PDOR9_P4                     *((volatile unsigned int*)(0x42668490UL))
+#define bFM3_GPIO_PDOR9_P5                     *((volatile unsigned int*)(0x42668494UL))
+#define bFM3_GPIO_PDORA_P0                     *((volatile unsigned int*)(0x42668500UL))
+#define bFM3_GPIO_PDORA_P1                     *((volatile unsigned int*)(0x42668504UL))
+#define bFM3_GPIO_PDORA_P2                     *((volatile unsigned int*)(0x42668508UL))
+#define bFM3_GPIO_PDORA_P3                     *((volatile unsigned int*)(0x4266850CUL))
+#define bFM3_GPIO_PDORA_P4                     *((volatile unsigned int*)(0x42668510UL))
+#define bFM3_GPIO_PDORA_P5                     *((volatile unsigned int*)(0x42668514UL))
+#define bFM3_GPIO_PDORB_P0                     *((volatile unsigned int*)(0x42668580UL))
+#define bFM3_GPIO_PDORB_P1                     *((volatile unsigned int*)(0x42668584UL))
+#define bFM3_GPIO_PDORB_P2                     *((volatile unsigned int*)(0x42668588UL))
+#define bFM3_GPIO_PDORB_P3                     *((volatile unsigned int*)(0x4266858CUL))
+#define bFM3_GPIO_PDORB_P4                     *((volatile unsigned int*)(0x42668590UL))
+#define bFM3_GPIO_PDORB_P5                     *((volatile unsigned int*)(0x42668594UL))
+#define bFM3_GPIO_PDORB_P6                     *((volatile unsigned int*)(0x42668598UL))
+#define bFM3_GPIO_PDORB_P7                     *((volatile unsigned int*)(0x4266859CUL))
+#define bFM3_GPIO_PDORC_P0                     *((volatile unsigned int*)(0x42668600UL))
+#define bFM3_GPIO_PDORC_P1                     *((volatile unsigned int*)(0x42668604UL))
+#define bFM3_GPIO_PDORC_P2                     *((volatile unsigned int*)(0x42668608UL))
+#define bFM3_GPIO_PDORC_P3                     *((volatile unsigned int*)(0x4266860CUL))
+#define bFM3_GPIO_PDORC_P4                     *((volatile unsigned int*)(0x42668610UL))
+#define bFM3_GPIO_PDORC_P5                     *((volatile unsigned int*)(0x42668614UL))
+#define bFM3_GPIO_PDORC_P6                     *((volatile unsigned int*)(0x42668618UL))
+#define bFM3_GPIO_PDORC_P7                     *((volatile unsigned int*)(0x4266861CUL))
+#define bFM3_GPIO_PDORC_P8                     *((volatile unsigned int*)(0x42668620UL))
+#define bFM3_GPIO_PDORC_P9                     *((volatile unsigned int*)(0x42668624UL))
+#define bFM3_GPIO_PDORC_PA                     *((volatile unsigned int*)(0x42668628UL))
+#define bFM3_GPIO_PDORC_PB                     *((volatile unsigned int*)(0x4266862CUL))
+#define bFM3_GPIO_PDORC_PC                     *((volatile unsigned int*)(0x42668630UL))
+#define bFM3_GPIO_PDORC_PD                     *((volatile unsigned int*)(0x42668634UL))
+#define bFM3_GPIO_PDORC_PE                     *((volatile unsigned int*)(0x42668638UL))
+#define bFM3_GPIO_PDORC_PF                     *((volatile unsigned int*)(0x4266863CUL))
+#define bFM3_GPIO_PDORD_P0                     *((volatile unsigned int*)(0x42668680UL))
+#define bFM3_GPIO_PDORD_P1                     *((volatile unsigned int*)(0x42668684UL))
+#define bFM3_GPIO_PDORD_P2                     *((volatile unsigned int*)(0x42668688UL))
+#define bFM3_GPIO_PDORD_P3                     *((volatile unsigned int*)(0x4266868CUL))
+#define bFM3_GPIO_PDORE_P0                     *((volatile unsigned int*)(0x42668700UL))
+#define bFM3_GPIO_PDORE_P2                     *((volatile unsigned int*)(0x42668708UL))
+#define bFM3_GPIO_PDORE_P3                     *((volatile unsigned int*)(0x4266870CUL))
+#define bFM3_GPIO_PDORF_P0                     *((volatile unsigned int*)(0x42668780UL))
+#define bFM3_GPIO_PDORF_P1                     *((volatile unsigned int*)(0x42668784UL))
+#define bFM3_GPIO_PDORF_P2                     *((volatile unsigned int*)(0x42668788UL))
+#define bFM3_GPIO_PDORF_P3                     *((volatile unsigned int*)(0x4266878CUL))
+#define bFM3_GPIO_PDORF_P4                     *((volatile unsigned int*)(0x42668790UL))
+#define bFM3_GPIO_PDORF_P5                     *((volatile unsigned int*)(0x42668794UL))
+#define bFM3_GPIO_PDORF_P6                     *((volatile unsigned int*)(0x42668798UL))
+#define bFM3_GPIO_ADE_AN0                      *((volatile unsigned int*)(0x4266A000UL))
+#define bFM3_GPIO_ADE_AN1                      *((volatile unsigned int*)(0x4266A004UL))
+#define bFM3_GPIO_ADE_AN2                      *((volatile unsigned int*)(0x4266A008UL))
+#define bFM3_GPIO_ADE_AN3                      *((volatile unsigned int*)(0x4266A00CUL))
+#define bFM3_GPIO_ADE_AN4                      *((volatile unsigned int*)(0x4266A010UL))
+#define bFM3_GPIO_ADE_AN5                      *((volatile unsigned int*)(0x4266A014UL))
+#define bFM3_GPIO_ADE_AN6                      *((volatile unsigned int*)(0x4266A018UL))
+#define bFM3_GPIO_ADE_AN7                      *((volatile unsigned int*)(0x4266A01CUL))
+#define bFM3_GPIO_ADE_AN8                      *((volatile unsigned int*)(0x4266A020UL))
+#define bFM3_GPIO_ADE_AN9                      *((volatile unsigned int*)(0x4266A024UL))
+#define bFM3_GPIO_ADE_AN10                     *((volatile unsigned int*)(0x4266A028UL))
+#define bFM3_GPIO_ADE_AN11                     *((volatile unsigned int*)(0x4266A02CUL))
+#define bFM3_GPIO_ADE_AN12                     *((volatile unsigned int*)(0x4266A030UL))
+#define bFM3_GPIO_ADE_AN13                     *((volatile unsigned int*)(0x4266A034UL))
+#define bFM3_GPIO_ADE_AN14                     *((volatile unsigned int*)(0x4266A038UL))
+#define bFM3_GPIO_ADE_AN15                     *((volatile unsigned int*)(0x4266A03CUL))
+#define bFM3_GPIO_ADE_AN16                     *((volatile unsigned int*)(0x4266A040UL))
+#define bFM3_GPIO_ADE_AN17                     *((volatile unsigned int*)(0x4266A044UL))
+#define bFM3_GPIO_ADE_AN18                     *((volatile unsigned int*)(0x4266A048UL))
+#define bFM3_GPIO_ADE_AN19                     *((volatile unsigned int*)(0x4266A04CUL))
+#define bFM3_GPIO_ADE_AN20                     *((volatile unsigned int*)(0x4266A050UL))
+#define bFM3_GPIO_ADE_AN21                     *((volatile unsigned int*)(0x4266A054UL))
+#define bFM3_GPIO_ADE_AN22                     *((volatile unsigned int*)(0x4266A058UL))
+#define bFM3_GPIO_ADE_AN23                     *((volatile unsigned int*)(0x4266A05CUL))
+#define bFM3_GPIO_ADE_AN24                     *((volatile unsigned int*)(0x4266A060UL))
+#define bFM3_GPIO_ADE_AN25                     *((volatile unsigned int*)(0x4266A064UL))
+#define bFM3_GPIO_ADE_AN26                     *((volatile unsigned int*)(0x4266A068UL))
+#define bFM3_GPIO_ADE_AN27                     *((volatile unsigned int*)(0x4266A06CUL))
+#define bFM3_GPIO_ADE_AN28                     *((volatile unsigned int*)(0x4266A070UL))
+#define bFM3_GPIO_ADE_AN29                     *((volatile unsigned int*)(0x4266A074UL))
+#define bFM3_GPIO_ADE_AN30                     *((volatile unsigned int*)(0x4266A078UL))
+#define bFM3_GPIO_ADE_AN31                     *((volatile unsigned int*)(0x4266A07CUL))
+#define bFM3_GPIO_SPSR_SUBXC                   *((volatile unsigned int*)(0x4266B000UL))
+#define bFM3_GPIO_SPSR_MAINXC                  *((volatile unsigned int*)(0x4266B008UL))
+#define bFM3_GPIO_SPSR_USB0C                   *((volatile unsigned int*)(0x4266B010UL))
+#define bFM3_GPIO_SPSR_USB1C                   *((volatile unsigned int*)(0x4266B014UL))
+#define bFM3_GPIO_EPFR00_NMIS                  *((volatile unsigned int*)(0x4266C000UL))
+#define bFM3_GPIO_EPFR00_CROUTE0               *((volatile unsigned int*)(0x4266C004UL))
+#define bFM3_GPIO_EPFR00_CROUTE1               *((volatile unsigned int*)(0x4266C008UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE0              *((volatile unsigned int*)(0x4266C018UL))
+#define bFM3_GPIO_EPFR00_SUBOUTE1              *((volatile unsigned int*)(0x4266C01CUL))
+#define bFM3_GPIO_EPFR00_USBP0E                *((volatile unsigned int*)(0x4266C024UL))
+#define bFM3_GPIO_EPFR00_USBP1E                *((volatile unsigned int*)(0x4266C034UL))
+#define bFM3_GPIO_EPFR00_JTAGEN0B              *((volatile unsigned int*)(0x4266C040UL))
+#define bFM3_GPIO_EPFR00_JTAGEN1S              *((volatile unsigned int*)(0x4266C044UL))
+#define bFM3_GPIO_EPFR00_TRC0E                 *((volatile unsigned int*)(0x4266C060UL))
+#define bFM3_GPIO_EPFR00_TRC1E                 *((volatile unsigned int*)(0x4266C064UL))
+#define bFM3_GPIO_EPFR01_RTO00E0               *((volatile unsigned int*)(0x4266C080UL))
+#define bFM3_GPIO_EPFR01_RTO00E1               *((volatile unsigned int*)(0x4266C084UL))
+#define bFM3_GPIO_EPFR01_RTO01E0               *((volatile unsigned int*)(0x4266C088UL))
+#define bFM3_GPIO_EPFR01_RTO01E1               *((volatile unsigned int*)(0x4266C08CUL))
+#define bFM3_GPIO_EPFR01_RTO02E0               *((volatile unsigned int*)(0x4266C090UL))
+#define bFM3_GPIO_EPFR01_RTO02E1               *((volatile unsigned int*)(0x4266C094UL))
+#define bFM3_GPIO_EPFR01_RTO03E0               *((volatile unsigned int*)(0x4266C098UL))
+#define bFM3_GPIO_EPFR01_RTO03E1               *((volatile unsigned int*)(0x4266C09CUL))
+#define bFM3_GPIO_EPFR01_RTO04E0               *((volatile unsigned int*)(0x4266C0A0UL))
+#define bFM3_GPIO_EPFR01_RTO04E1               *((volatile unsigned int*)(0x4266C0A4UL))
+#define bFM3_GPIO_EPFR01_RTO05E0               *((volatile unsigned int*)(0x4266C0A8UL))
+#define bFM3_GPIO_EPFR01_RTO05E1               *((volatile unsigned int*)(0x4266C0ACUL))
+#define bFM3_GPIO_EPFR01_DTTI0C                *((volatile unsigned int*)(0x4266C0B0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S0               *((volatile unsigned int*)(0x4266C0C0UL))
+#define bFM3_GPIO_EPFR01_DTTI0S1               *((volatile unsigned int*)(0x4266C0C4UL))
+#define bFM3_GPIO_EPFR01_FRCK0S0               *((volatile unsigned int*)(0x4266C0C8UL))
+#define bFM3_GPIO_EPFR01_FRCK0S1               *((volatile unsigned int*)(0x4266C0CCUL))
+#define bFM3_GPIO_EPFR01_IC00S0                *((volatile unsigned int*)(0x4266C0D0UL))
+#define bFM3_GPIO_EPFR01_IC00S1                *((volatile unsigned int*)(0x4266C0D4UL))
+#define bFM3_GPIO_EPFR01_IC00S2                *((volatile unsigned int*)(0x4266C0D8UL))
+#define bFM3_GPIO_EPFR01_IC01S0                *((volatile unsigned int*)(0x4266C0DCUL))
+#define bFM3_GPIO_EPFR01_IC01S1                *((volatile unsigned int*)(0x4266C0E0UL))
+#define bFM3_GPIO_EPFR01_IC01S2                *((volatile unsigned int*)(0x4266C0E4UL))
+#define bFM3_GPIO_EPFR01_IC02S0                *((volatile unsigned int*)(0x4266C0E8UL))
+#define bFM3_GPIO_EPFR01_IC02S1                *((volatile unsigned int*)(0x4266C0ECUL))
+#define bFM3_GPIO_EPFR01_IC02S2                *((volatile unsigned int*)(0x4266C0F0UL))
+#define bFM3_GPIO_EPFR01_IC03S0                *((volatile unsigned int*)(0x4266C0F4UL))
+#define bFM3_GPIO_EPFR01_IC03S1                *((volatile unsigned int*)(0x4266C0F8UL))
+#define bFM3_GPIO_EPFR01_IC03S2                *((volatile unsigned int*)(0x4266C0FCUL))
+#define bFM3_GPIO_EPFR02_RTO10E0               *((volatile unsigned int*)(0x4266C100UL))
+#define bFM3_GPIO_EPFR02_RTO10E1               *((volatile unsigned int*)(0x4266C104UL))
+#define bFM3_GPIO_EPFR02_RTO11E0               *((volatile unsigned int*)(0x4266C108UL))
+#define bFM3_GPIO_EPFR02_RTO11E1               *((volatile unsigned int*)(0x4266C10CUL))
+#define bFM3_GPIO_EPFR02_RTO12E0               *((volatile unsigned int*)(0x4266C110UL))
+#define bFM3_GPIO_EPFR02_RTO12E1               *((volatile unsigned int*)(0x4266C114UL))
+#define bFM3_GPIO_EPFR02_RTO13E0               *((volatile unsigned int*)(0x4266C118UL))
+#define bFM3_GPIO_EPFR02_RTO13E1               *((volatile unsigned int*)(0x4266C11CUL))
+#define bFM3_GPIO_EPFR02_RTO14E0               *((volatile unsigned int*)(0x4266C120UL))
+#define bFM3_GPIO_EPFR02_RTO14E1               *((volatile unsigned int*)(0x4266C124UL))
+#define bFM3_GPIO_EPFR02_RTO15E0               *((volatile unsigned int*)(0x4266C128UL))
+#define bFM3_GPIO_EPFR02_RTO15E1               *((volatile unsigned int*)(0x4266C12CUL))
+#define bFM3_GPIO_EPFR02_DTTI1C                *((volatile unsigned int*)(0x4266C130UL))
+#define bFM3_GPIO_EPFR02_DTTI1S0               *((volatile unsigned int*)(0x4266C140UL))
+#define bFM3_GPIO_EPFR02_DTTI1S1               *((volatile unsigned int*)(0x4266C144UL))
+#define bFM3_GPIO_EPFR02_FRCK1S0               *((volatile unsigned int*)(0x4266C148UL))
+#define bFM3_GPIO_EPFR02_FRCK1S1               *((volatile unsigned int*)(0x4266C14CUL))
+#define bFM3_GPIO_EPFR02_IC10S0                *((volatile unsigned int*)(0x4266C150UL))
+#define bFM3_GPIO_EPFR02_IC10S1                *((volatile unsigned int*)(0x4266C154UL))
+#define bFM3_GPIO_EPFR02_IC10S2                *((volatile unsigned int*)(0x4266C158UL))
+#define bFM3_GPIO_EPFR02_IC11S0                *((volatile unsigned int*)(0x4266C15CUL))
+#define bFM3_GPIO_EPFR02_IC11S1                *((volatile unsigned int*)(0x4266C160UL))
+#define bFM3_GPIO_EPFR02_IC11S2                *((volatile unsigned int*)(0x4266C164UL))
+#define bFM3_GPIO_EPFR02_IC12S0                *((volatile unsigned int*)(0x4266C168UL))
+#define bFM3_GPIO_EPFR02_IC12S1                *((volatile unsigned int*)(0x4266C16CUL))
+#define bFM3_GPIO_EPFR02_IC12S2                *((volatile unsigned int*)(0x4266C170UL))
+#define bFM3_GPIO_EPFR02_IC13S0                *((volatile unsigned int*)(0x4266C174UL))
+#define bFM3_GPIO_EPFR02_IC13S1                *((volatile unsigned int*)(0x4266C178UL))
+#define bFM3_GPIO_EPFR02_IC13S2                *((volatile unsigned int*)(0x4266C17CUL))
+#define bFM3_GPIO_EPFR03_RTO20E0               *((volatile unsigned int*)(0x4266C180UL))
+#define bFM3_GPIO_EPFR03_RTO20E1               *((volatile unsigned int*)(0x4266C184UL))
+#define bFM3_GPIO_EPFR03_RTO21E0               *((volatile unsigned int*)(0x4266C188UL))
+#define bFM3_GPIO_EPFR03_RTO21E1               *((volatile unsigned int*)(0x4266C18CUL))
+#define bFM3_GPIO_EPFR03_RTO22E0               *((volatile unsigned int*)(0x4266C190UL))
+#define bFM3_GPIO_EPFR03_RTO22E1               *((volatile unsigned int*)(0x4266C194UL))
+#define bFM3_GPIO_EPFR03_RTO23E0               *((volatile unsigned int*)(0x4266C198UL))
+#define bFM3_GPIO_EPFR03_RTO23E1               *((volatile unsigned int*)(0x4266C19CUL))
+#define bFM3_GPIO_EPFR03_RTO24E0               *((volatile unsigned int*)(0x4266C1A0UL))
+#define bFM3_GPIO_EPFR03_RTO24E1               *((volatile unsigned int*)(0x4266C1A4UL))
+#define bFM3_GPIO_EPFR03_RTO25E0               *((volatile unsigned int*)(0x4266C1A8UL))
+#define bFM3_GPIO_EPFR03_RTO25E1               *((volatile unsigned int*)(0x4266C1ACUL))
+#define bFM3_GPIO_EPFR03_DTTI2C                *((volatile unsigned int*)(0x4266C1B0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S0               *((volatile unsigned int*)(0x4266C1C0UL))
+#define bFM3_GPIO_EPFR03_DTTI2S1               *((volatile unsigned int*)(0x4266C1C4UL))
+#define bFM3_GPIO_EPFR03_FRCK2S0               *((volatile unsigned int*)(0x4266C1C8UL))
+#define bFM3_GPIO_EPFR03_FRCK2S1               *((volatile unsigned int*)(0x4266C1CCUL))
+#define bFM3_GPIO_EPFR03_IC20S0                *((volatile unsigned int*)(0x4266C1D0UL))
+#define bFM3_GPIO_EPFR03_IC20S1                *((volatile unsigned int*)(0x4266C1D4UL))
+#define bFM3_GPIO_EPFR03_IC20S2                *((volatile unsigned int*)(0x4266C1D8UL))
+#define bFM3_GPIO_EPFR03_IC21S0                *((volatile unsigned int*)(0x4266C1DCUL))
+#define bFM3_GPIO_EPFR03_IC21S1                *((volatile unsigned int*)(0x4266C1E0UL))
+#define bFM3_GPIO_EPFR03_IC21S2                *((volatile unsigned int*)(0x4266C1E4UL))
+#define bFM3_GPIO_EPFR03_IC22S0                *((volatile unsigned int*)(0x4266C1E8UL))
+#define bFM3_GPIO_EPFR03_IC22S1                *((volatile unsigned int*)(0x4266C1ECUL))
+#define bFM3_GPIO_EPFR03_IC22S2                *((volatile unsigned int*)(0x4266C1F0UL))
+#define bFM3_GPIO_EPFR03_IC23S0                *((volatile unsigned int*)(0x4266C1F4UL))
+#define bFM3_GPIO_EPFR03_IC23S1                *((volatile unsigned int*)(0x4266C1F8UL))
+#define bFM3_GPIO_EPFR03_IC23S2                *((volatile unsigned int*)(0x4266C1FCUL))
+#define bFM3_GPIO_EPFR04_TIOA0E0               *((volatile unsigned int*)(0x4266C208UL))
+#define bFM3_GPIO_EPFR04_TIOA0E1               *((volatile unsigned int*)(0x4266C20CUL))
+#define bFM3_GPIO_EPFR04_TIOB0S0               *((volatile unsigned int*)(0x4266C210UL))
+#define bFM3_GPIO_EPFR04_TIOB0S1               *((volatile unsigned int*)(0x4266C214UL))
+#define bFM3_GPIO_EPFR04_TIOA1S0               *((volatile unsigned int*)(0x4266C220UL))
+#define bFM3_GPIO_EPFR04_TIOA1S1               *((volatile unsigned int*)(0x4266C224UL))
+#define bFM3_GPIO_EPFR04_TIOA1E0               *((volatile unsigned int*)(0x4266C228UL))
+#define bFM3_GPIO_EPFR04_TIOA1E1               *((volatile unsigned int*)(0x4266C22CUL))
+#define bFM3_GPIO_EPFR04_TIOB1S0               *((volatile unsigned int*)(0x4266C230UL))
+#define bFM3_GPIO_EPFR04_TIOB1S1               *((volatile unsigned int*)(0x4266C234UL))
+#define bFM3_GPIO_EPFR04_TIOA2E0               *((volatile unsigned int*)(0x4266C248UL))
+#define bFM3_GPIO_EPFR04_TIOA2E1               *((volatile unsigned int*)(0x4266C24CUL))
+#define bFM3_GPIO_EPFR04_TIOB2S0               *((volatile unsigned int*)(0x4266C250UL))
+#define bFM3_GPIO_EPFR04_TIOB2S1               *((volatile unsigned int*)(0x4266C254UL))
+#define bFM3_GPIO_EPFR04_TIOA3S0               *((volatile unsigned int*)(0x4266C260UL))
+#define bFM3_GPIO_EPFR04_TIOA3S1               *((volatile unsigned int*)(0x4266C264UL))
+#define bFM3_GPIO_EPFR04_TIOA3E0               *((volatile unsigned int*)(0x4266C268UL))
+#define bFM3_GPIO_EPFR04_TIOA3E1               *((volatile unsigned int*)(0x4266C26CUL))
+#define bFM3_GPIO_EPFR04_TIOB3S0               *((volatile unsigned int*)(0x4266C270UL))
+#define bFM3_GPIO_EPFR04_TIOB3S1               *((volatile unsigned int*)(0x4266C274UL))
+#define bFM3_GPIO_EPFR05_TIOA4E0               *((volatile unsigned int*)(0x4266C288UL))
+#define bFM3_GPIO_EPFR05_TIOA4E1               *((volatile unsigned int*)(0x4266C28CUL))
+#define bFM3_GPIO_EPFR05_TIOB4S0               *((volatile unsigned int*)(0x4266C290UL))
+#define bFM3_GPIO_EPFR05_TIOB4S1               *((volatile unsigned int*)(0x4266C294UL))
+#define bFM3_GPIO_EPFR05_TIOA5S0               *((volatile unsigned int*)(0x4266C2A0UL))
+#define bFM3_GPIO_EPFR05_TIOA5S1               *((volatile unsigned int*)(0x4266C2A4UL))
+#define bFM3_GPIO_EPFR05_TIOA5E0               *((volatile unsigned int*)(0x4266C2A8UL))
+#define bFM3_GPIO_EPFR05_TIOA5E1               *((volatile unsigned int*)(0x4266C2ACUL))
+#define bFM3_GPIO_EPFR05_TIOB5S0               *((volatile unsigned int*)(0x4266C2B0UL))
+#define bFM3_GPIO_EPFR05_TIOB5S1               *((volatile unsigned int*)(0x4266C2B4UL))
+#define bFM3_GPIO_EPFR05_TIOA6E0               *((volatile unsigned int*)(0x4266C2C8UL))
+#define bFM3_GPIO_EPFR05_TIOA6E1               *((volatile unsigned int*)(0x4266C2CCUL))
+#define bFM3_GPIO_EPFR05_TIOB6S0               *((volatile unsigned int*)(0x4266C2D0UL))
+#define bFM3_GPIO_EPFR05_TIOB6S1               *((volatile unsigned int*)(0x4266C2D4UL))
+#define bFM3_GPIO_EPFR05_TIOA7S0               *((volatile unsigned int*)(0x4266C2E0UL))
+#define bFM3_GPIO_EPFR05_TIOA7S1               *((volatile unsigned int*)(0x4266C2E4UL))
+#define bFM3_GPIO_EPFR05_TIOA7E0               *((volatile unsigned int*)(0x4266C2E8UL))
+#define bFM3_GPIO_EPFR05_TIOA7E1               *((volatile unsigned int*)(0x4266C2ECUL))
+#define bFM3_GPIO_EPFR05_TIOB7S0               *((volatile unsigned int*)(0x4266C2F0UL))
+#define bFM3_GPIO_EPFR05_TIOB7S1               *((volatile unsigned int*)(0x4266C2F4UL))
+#define bFM3_GPIO_EPFR06_EINT00S0              *((volatile unsigned int*)(0x4266C300UL))
+#define bFM3_GPIO_EPFR06_EINT00S1              *((volatile unsigned int*)(0x4266C304UL))
+#define bFM3_GPIO_EPFR06_EINT01S0              *((volatile unsigned int*)(0x4266C308UL))
+#define bFM3_GPIO_EPFR06_EINT01S1              *((volatile unsigned int*)(0x4266C30CUL))
+#define bFM3_GPIO_EPFR06_EINT02S0              *((volatile unsigned int*)(0x4266C310UL))
+#define bFM3_GPIO_EPFR06_EINT02S1              *((volatile unsigned int*)(0x4266C314UL))
+#define bFM3_GPIO_EPFR06_EINT03S0              *((volatile unsigned int*)(0x4266C318UL))
+#define bFM3_GPIO_EPFR06_EINT03S1              *((volatile unsigned int*)(0x4266C31CUL))
+#define bFM3_GPIO_EPFR06_EINT04S0              *((volatile unsigned int*)(0x4266C320UL))
+#define bFM3_GPIO_EPFR06_EINT04S1              *((volatile unsigned int*)(0x4266C324UL))
+#define bFM3_GPIO_EPFR06_EINT05S0              *((volatile unsigned int*)(0x4266C328UL))
+#define bFM3_GPIO_EPFR06_EINT05S1              *((volatile unsigned int*)(0x4266C32CUL))
+#define bFM3_GPIO_EPFR06_EINT06S0              *((volatile unsigned int*)(0x4266C330UL))
+#define bFM3_GPIO_EPFR06_EINT06S1              *((volatile unsigned int*)(0x4266C334UL))
+#define bFM3_GPIO_EPFR06_EINT07S0              *((volatile unsigned int*)(0x4266C338UL))
+#define bFM3_GPIO_EPFR06_EINT07S1              *((volatile unsigned int*)(0x4266C33CUL))
+#define bFM3_GPIO_EPFR06_EINT08S0              *((volatile unsigned int*)(0x4266C340UL))
+#define bFM3_GPIO_EPFR06_EINT08S1              *((volatile unsigned int*)(0x4266C344UL))
+#define bFM3_GPIO_EPFR06_EINT09S0              *((volatile unsigned int*)(0x4266C348UL))
+#define bFM3_GPIO_EPFR06_EINT09S1              *((volatile unsigned int*)(0x4266C34CUL))
+#define bFM3_GPIO_EPFR06_EINT10S0              *((volatile unsigned int*)(0x4266C350UL))
+#define bFM3_GPIO_EPFR06_EINT10S1              *((volatile unsigned int*)(0x4266C354UL))
+#define bFM3_GPIO_EPFR06_EINT11S0              *((volatile unsigned int*)(0x4266C358UL))
+#define bFM3_GPIO_EPFR06_EINT11S1              *((volatile unsigned int*)(0x4266C35CUL))
+#define bFM3_GPIO_EPFR06_EINT12S0              *((volatile unsigned int*)(0x4266C360UL))
+#define bFM3_GPIO_EPFR06_EINT12S1              *((volatile unsigned int*)(0x4266C364UL))
+#define bFM3_GPIO_EPFR06_EINT13S0              *((volatile unsigned int*)(0x4266C368UL))
+#define bFM3_GPIO_EPFR06_EINT13S1              *((volatile unsigned int*)(0x4266C36CUL))
+#define bFM3_GPIO_EPFR06_EINT14S0              *((volatile unsigned int*)(0x4266C370UL))
+#define bFM3_GPIO_EPFR06_EINT14S1              *((volatile unsigned int*)(0x4266C374UL))
+#define bFM3_GPIO_EPFR06_EINT15S0              *((volatile unsigned int*)(0x4266C378UL))
+#define bFM3_GPIO_EPFR06_EINT15S1              *((volatile unsigned int*)(0x4266C37CUL))
+#define bFM3_GPIO_EPFR07_SIN0S0                *((volatile unsigned int*)(0x4266C390UL))
+#define bFM3_GPIO_EPFR07_SIN0S1                *((volatile unsigned int*)(0x4266C394UL))
+#define bFM3_GPIO_EPFR07_SOT0B0                *((volatile unsigned int*)(0x4266C398UL))
+#define bFM3_GPIO_EPFR07_SOT0B1                *((volatile unsigned int*)(0x4266C39CUL))
+#define bFM3_GPIO_EPFR07_SCK0B0                *((volatile unsigned int*)(0x4266C3A0UL))
+#define bFM3_GPIO_EPFR07_SCK0B1                *((volatile unsigned int*)(0x4266C3A4UL))
+#define bFM3_GPIO_EPFR07_SIN1S0                *((volatile unsigned int*)(0x4266C3A8UL))
+#define bFM3_GPIO_EPFR07_SIN1S1                *((volatile unsigned int*)(0x4266C3ACUL))
+#define bFM3_GPIO_EPFR07_SOT1B0                *((volatile unsigned int*)(0x4266C3B0UL))
+#define bFM3_GPIO_EPFR07_SOT1B1                *((volatile unsigned int*)(0x4266C3B4UL))
+#define bFM3_GPIO_EPFR07_SCK1B0                *((volatile unsigned int*)(0x4266C3B8UL))
+#define bFM3_GPIO_EPFR07_SCK1B1                *((volatile unsigned int*)(0x4266C3BCUL))
+#define bFM3_GPIO_EPFR07_SIN2S0                *((volatile unsigned int*)(0x4266C3C0UL))
+#define bFM3_GPIO_EPFR07_SIN2S1                *((volatile unsigned int*)(0x4266C3C4UL))
+#define bFM3_GPIO_EPFR07_SOT2B0                *((volatile unsigned int*)(0x4266C3C8UL))
+#define bFM3_GPIO_EPFR07_SOT2B1                *((volatile unsigned int*)(0x4266C3CCUL))
+#define bFM3_GPIO_EPFR07_SCK2B0                *((volatile unsigned int*)(0x4266C3D0UL))
+#define bFM3_GPIO_EPFR07_SCK2B1                *((volatile unsigned int*)(0x4266C3D4UL))
+#define bFM3_GPIO_EPFR07_SIN3S0                *((volatile unsigned int*)(0x4266C3D8UL))
+#define bFM3_GPIO_EPFR07_SIN3S1                *((volatile unsigned int*)(0x4266C3DCUL))
+#define bFM3_GPIO_EPFR07_SOT3B0                *((volatile unsigned int*)(0x4266C3E0UL))
+#define bFM3_GPIO_EPFR07_SOT3B1                *((volatile unsigned int*)(0x4266C3E4UL))
+#define bFM3_GPIO_EPFR07_SCK3B0                *((volatile unsigned int*)(0x4266C3E8UL))
+#define bFM3_GPIO_EPFR07_SCK3B1                *((volatile unsigned int*)(0x4266C3ECUL))
+#define bFM3_GPIO_EPFR08_RTS4E0                *((volatile unsigned int*)(0x4266C400UL))
+#define bFM3_GPIO_EPFR08_RTS4E1                *((volatile unsigned int*)(0x4266C404UL))
+#define bFM3_GPIO_EPFR08_CTS4S0                *((volatile unsigned int*)(0x4266C408UL))
+#define bFM3_GPIO_EPFR08_CTS4S1                *((volatile unsigned int*)(0x4266C40CUL))
+#define bFM3_GPIO_EPFR08_SIN4S0                *((volatile unsigned int*)(0x4266C410UL))
+#define bFM3_GPIO_EPFR08_SIN4S1                *((volatile unsigned int*)(0x4266C414UL))
+#define bFM3_GPIO_EPFR08_SOT4B0                *((volatile unsigned int*)(0x4266C418UL))
+#define bFM3_GPIO_EPFR08_SOT4B1                *((volatile unsigned int*)(0x4266C41CUL))
+#define bFM3_GPIO_EPFR08_SCK4B0                *((volatile unsigned int*)(0x4266C420UL))
+#define bFM3_GPIO_EPFR08_SCK4B1                *((volatile unsigned int*)(0x4266C424UL))
+#define bFM3_GPIO_EPFR08_SIN5S0                *((volatile unsigned int*)(0x4266C428UL))
+#define bFM3_GPIO_EPFR08_SIN5S1                *((volatile unsigned int*)(0x4266C42CUL))
+#define bFM3_GPIO_EPFR08_SOT5B0                *((volatile unsigned int*)(0x4266C430UL))
+#define bFM3_GPIO_EPFR08_SOT5B1                *((volatile unsigned int*)(0x4266C434UL))
+#define bFM3_GPIO_EPFR08_SCK5B0                *((volatile unsigned int*)(0x4266C438UL))
+#define bFM3_GPIO_EPFR08_SCK5B1                *((volatile unsigned int*)(0x4266C43CUL))
+#define bFM3_GPIO_EPFR08_SIN6S0                *((volatile unsigned int*)(0x4266C440UL))
+#define bFM3_GPIO_EPFR08_SIN6S1                *((volatile unsigned int*)(0x4266C444UL))
+#define bFM3_GPIO_EPFR08_SOT6B0                *((volatile unsigned int*)(0x4266C448UL))
+#define bFM3_GPIO_EPFR08_SOT6B1                *((volatile unsigned int*)(0x4266C44CUL))
+#define bFM3_GPIO_EPFR08_SCK6B0                *((volatile unsigned int*)(0x4266C450UL))
+#define bFM3_GPIO_EPFR08_SCK6B1                *((volatile unsigned int*)(0x4266C454UL))
+#define bFM3_GPIO_EPFR08_SIN7S0                *((volatile unsigned int*)(0x4266C458UL))
+#define bFM3_GPIO_EPFR08_SIN7S1                *((volatile unsigned int*)(0x4266C45CUL))
+#define bFM3_GPIO_EPFR08_SOT7B0                *((volatile unsigned int*)(0x4266C460UL))
+#define bFM3_GPIO_EPFR08_SOT7B1                *((volatile unsigned int*)(0x4266C464UL))
+#define bFM3_GPIO_EPFR08_SCK7B0                *((volatile unsigned int*)(0x4266C468UL))
+#define bFM3_GPIO_EPFR08_SCK7B1                *((volatile unsigned int*)(0x4266C46CUL))
+#define bFM3_GPIO_EPFR09_QAIN0S0               *((volatile unsigned int*)(0x4266C480UL))
+#define bFM3_GPIO_EPFR09_QAIN0S1               *((volatile unsigned int*)(0x4266C484UL))
+#define bFM3_GPIO_EPFR09_QBIN0S0               *((volatile unsigned int*)(0x4266C488UL))
+#define bFM3_GPIO_EPFR09_QBIN0S1               *((volatile unsigned int*)(0x4266C48CUL))
+#define bFM3_GPIO_EPFR09_QZIN0S0               *((volatile unsigned int*)(0x4266C490UL))
+#define bFM3_GPIO_EPFR09_QZIN0S1               *((volatile unsigned int*)(0x4266C494UL))
+#define bFM3_GPIO_EPFR09_QAIN1S0               *((volatile unsigned int*)(0x4266C498UL))
+#define bFM3_GPIO_EPFR09_QAIN1S1               *((volatile unsigned int*)(0x4266C49CUL))
+#define bFM3_GPIO_EPFR09_QBIN1S0               *((volatile unsigned int*)(0x4266C4A0UL))
+#define bFM3_GPIO_EPFR09_QBIN1S1               *((volatile unsigned int*)(0x4266C4A4UL))
+#define bFM3_GPIO_EPFR09_QZIN1S0               *((volatile unsigned int*)(0x4266C4A8UL))
+#define bFM3_GPIO_EPFR09_QZIN1S1               *((volatile unsigned int*)(0x4266C4ACUL))
+#define bFM3_GPIO_EPFR09_ADTRG0S0              *((volatile unsigned int*)(0x4266C4B0UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S1              *((volatile unsigned int*)(0x4266C4B4UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S2              *((volatile unsigned int*)(0x4266C4B8UL))
+#define bFM3_GPIO_EPFR09_ADTRG0S3              *((volatile unsigned int*)(0x4266C4BCUL))
+#define bFM3_GPIO_EPFR09_ADTRG1S0              *((volatile unsigned int*)(0x4266C4C0UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S1              *((volatile unsigned int*)(0x4266C4C4UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S2              *((volatile unsigned int*)(0x4266C4C8UL))
+#define bFM3_GPIO_EPFR09_ADTRG1S3              *((volatile unsigned int*)(0x4266C4CCUL))
+#define bFM3_GPIO_EPFR09_ADTRG2S0              *((volatile unsigned int*)(0x4266C4D0UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S1              *((volatile unsigned int*)(0x4266C4D4UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S2              *((volatile unsigned int*)(0x4266C4D8UL))
+#define bFM3_GPIO_EPFR09_ADTRG2S3              *((volatile unsigned int*)(0x4266C4DCUL))
+#define bFM3_GPIO_EPFR10_UEDEFB                *((volatile unsigned int*)(0x4266C500UL))
+#define bFM3_GPIO_EPFR10_UEDTHB                *((volatile unsigned int*)(0x4266C504UL))
+#define bFM3_GPIO_EPFR10_UECLKE                *((volatile unsigned int*)(0x4266C508UL))
+#define bFM3_GPIO_EPFR10_UEWEXE                *((volatile unsigned int*)(0x4266C50CUL))
+#define bFM3_GPIO_EPFR10_UEDQME                *((volatile unsigned int*)(0x4266C510UL))
+#define bFM3_GPIO_EPFR10_UEOEXE                *((volatile unsigned int*)(0x4266C514UL))
+#define bFM3_GPIO_EPFR10_UEFLSE                *((volatile unsigned int*)(0x4266C518UL))
+#define bFM3_GPIO_EPFR10_UECS1E                *((volatile unsigned int*)(0x4266C51CUL))
+#define bFM3_GPIO_EPFR10_UECS2E                *((volatile unsigned int*)(0x4266C520UL))
+#define bFM3_GPIO_EPFR10_UECS3E                *((volatile unsigned int*)(0x4266C524UL))
+#define bFM3_GPIO_EPFR10_UECS4E                *((volatile unsigned int*)(0x4266C528UL))
+#define bFM3_GPIO_EPFR10_UECS5E                *((volatile unsigned int*)(0x4266C52CUL))
+#define bFM3_GPIO_EPFR10_UECS6E                *((volatile unsigned int*)(0x4266C530UL))
+#define bFM3_GPIO_EPFR10_UECS7E                *((volatile unsigned int*)(0x4266C534UL))
+#define bFM3_GPIO_EPFR10_UEAOOE                *((volatile unsigned int*)(0x4266C538UL))
+#define bFM3_GPIO_EPFR10_UEA08E                *((volatile unsigned int*)(0x4266C53CUL))
+#define bFM3_GPIO_EPFR10_UEA09E                *((volatile unsigned int*)(0x4266C540UL))
+#define bFM3_GPIO_EPFR10_UEA10E                *((volatile unsigned int*)(0x4266C544UL))
+#define bFM3_GPIO_EPFR10_UEA11E                *((volatile unsigned int*)(0x4266C548UL))
+#define bFM3_GPIO_EPFR10_UEA12E                *((volatile unsigned int*)(0x4266C54CUL))
+#define bFM3_GPIO_EPFR10_UEA13E                *((volatile unsigned int*)(0x4266C550UL))
+#define bFM3_GPIO_EPFR10_UEA14E                *((volatile unsigned int*)(0x4266C554UL))
+#define bFM3_GPIO_EPFR10_UEA15E                *((volatile unsigned int*)(0x4266C558UL))
+#define bFM3_GPIO_EPFR10_UEA16E                *((volatile unsigned int*)(0x4266C55CUL))
+#define bFM3_GPIO_EPFR10_UEA17E                *((volatile unsigned int*)(0x4266C560UL))
+#define bFM3_GPIO_EPFR10_UEA18E                *((volatile unsigned int*)(0x4266C564UL))
+#define bFM3_GPIO_EPFR10_UEA19E                *((volatile unsigned int*)(0x4266C568UL))
+#define bFM3_GPIO_EPFR10_UEA20E                *((volatile unsigned int*)(0x4266C56CUL))
+#define bFM3_GPIO_EPFR10_UEA21E                *((volatile unsigned int*)(0x4266C570UL))
+#define bFM3_GPIO_EPFR10_UEA22E                *((volatile unsigned int*)(0x4266C574UL))
+#define bFM3_GPIO_EPFR10_UEA23E                *((volatile unsigned int*)(0x4266C578UL))
+#define bFM3_GPIO_EPFR10_UEA24E                *((volatile unsigned int*)(0x4266C57CUL))
+#define bFM3_GPIO_EPFR11_UEALEE                *((volatile unsigned int*)(0x4266C580UL))
+#define bFM3_GPIO_EPFR11_UECS0E                *((volatile unsigned int*)(0x4266C584UL))
+#define bFM3_GPIO_EPFR11_UEA01E                *((volatile unsigned int*)(0x4266C588UL))
+#define bFM3_GPIO_EPFR11_UEA02E                *((volatile unsigned int*)(0x4266C58CUL))
+#define bFM3_GPIO_EPFR11_UEA03E                *((volatile unsigned int*)(0x4266C590UL))
+#define bFM3_GPIO_EPFR11_UEA04E                *((volatile unsigned int*)(0x4266C594UL))
+#define bFM3_GPIO_EPFR11_UEA05E                *((volatile unsigned int*)(0x4266C598UL))
+#define bFM3_GPIO_EPFR11_UEA06E                *((volatile unsigned int*)(0x4266C59CUL))
+#define bFM3_GPIO_EPFR11_UEA07E                *((volatile unsigned int*)(0x4266C5A0UL))
+#define bFM3_GPIO_EPFR11_UED00B                *((volatile unsigned int*)(0x4266C5A4UL))
+#define bFM3_GPIO_EPFR11_UED01B                *((volatile unsigned int*)(0x4266C5A8UL))
+#define bFM3_GPIO_EPFR11_UED02B                *((volatile unsigned int*)(0x4266C5ACUL))
+#define bFM3_GPIO_EPFR11_UED03B                *((volatile unsigned int*)(0x4266C5B0UL))
+#define bFM3_GPIO_EPFR11_UED04B                *((volatile unsigned int*)(0x4266C5B4UL))
+#define bFM3_GPIO_EPFR11_UED05B                *((volatile unsigned int*)(0x4266C5B8UL))
+#define bFM3_GPIO_EPFR11_UED06B                *((volatile unsigned int*)(0x4266C5BCUL))
+#define bFM3_GPIO_EPFR11_UED07B                *((volatile unsigned int*)(0x4266C5C0UL))
+#define bFM3_GPIO_EPFR11_UED08B                *((volatile unsigned int*)(0x4266C5C4UL))
+#define bFM3_GPIO_EPFR11_UED09B                *((volatile unsigned int*)(0x4266C5C8UL))
+#define bFM3_GPIO_EPFR11_UED10B                *((volatile unsigned int*)(0x4266C5CCUL))
+#define bFM3_GPIO_EPFR11_UED11B                *((volatile unsigned int*)(0x4266C5D0UL))
+#define bFM3_GPIO_EPFR11_UED12B                *((volatile unsigned int*)(0x4266C5D4UL))
+#define bFM3_GPIO_EPFR11_UED13B                *((volatile unsigned int*)(0x4266C5D8UL))
+#define bFM3_GPIO_EPFR11_UED14B                *((volatile unsigned int*)(0x4266C5DCUL))
+#define bFM3_GPIO_EPFR11_UED15B                *((volatile unsigned int*)(0x4266C5E0UL))
+#define bFM3_GPIO_EPFR11_UERLC                 *((volatile unsigned int*)(0x4266C5E4UL))
+#define bFM3_GPIO_EPFR12_TIOA8E0               *((volatile unsigned int*)(0x4266C608UL))
+#define bFM3_GPIO_EPFR12_TIOA8E1               *((volatile unsigned int*)(0x4266C60CUL))
+#define bFM3_GPIO_EPFR12_TIOB8S0               *((volatile unsigned int*)(0x4266C610UL))
+#define bFM3_GPIO_EPFR12_TIOB8S1               *((volatile unsigned int*)(0x4266C614UL))
+#define bFM3_GPIO_EPFR12_TIOA9S0               *((volatile unsigned int*)(0x4266C620UL))
+#define bFM3_GPIO_EPFR12_TIOA9S1               *((volatile unsigned int*)(0x4266C624UL))
+#define bFM3_GPIO_EPFR12_TIOA9E0               *((volatile unsigned int*)(0x4266C628UL))
+#define bFM3_GPIO_EPFR12_TIOA9E1               *((volatile unsigned int*)(0x4266C62CUL))
+#define bFM3_GPIO_EPFR12_TIOB9S0               *((volatile unsigned int*)(0x4266C630UL))
+#define bFM3_GPIO_EPFR12_TIOB9S1               *((volatile unsigned int*)(0x4266C634UL))
+#define bFM3_GPIO_EPFR12_TIOA10E0              *((volatile unsigned int*)(0x4266C648UL))
+#define bFM3_GPIO_EPFR12_TIOA10E1              *((volatile unsigned int*)(0x4266C64CUL))
+#define bFM3_GPIO_EPFR12_TIOB10S0              *((volatile unsigned int*)(0x4266C650UL))
+#define bFM3_GPIO_EPFR12_TIOB10S1              *((volatile unsigned int*)(0x4266C654UL))
+#define bFM3_GPIO_EPFR12_TIOA11S0              *((volatile unsigned int*)(0x4266C660UL))
+#define bFM3_GPIO_EPFR12_TIOA11S1              *((volatile unsigned int*)(0x4266C664UL))
+#define bFM3_GPIO_EPFR12_TIOA11E0              *((volatile unsigned int*)(0x4266C668UL))
+#define bFM3_GPIO_EPFR12_TIOA11E1              *((volatile unsigned int*)(0x4266C66CUL))
+#define bFM3_GPIO_EPFR12_TIOB11S0              *((volatile unsigned int*)(0x4266C670UL))
+#define bFM3_GPIO_EPFR12_TIOB11S1              *((volatile unsigned int*)(0x4266C674UL))
+#define bFM3_GPIO_EPFR13_TIOA12E0              *((volatile unsigned int*)(0x4266C688UL))
+#define bFM3_GPIO_EPFR13_TIOA12E1              *((volatile unsigned int*)(0x4266C68CUL))
+#define bFM3_GPIO_EPFR13_TIOB12S0              *((volatile unsigned int*)(0x4266C690UL))
+#define bFM3_GPIO_EPFR13_TIOB12S1              *((volatile unsigned int*)(0x4266C694UL))
+#define bFM3_GPIO_EPFR13_TIOA13S0              *((volatile unsigned int*)(0x4266C6A0UL))
+#define bFM3_GPIO_EPFR13_TIOA13S1              *((volatile unsigned int*)(0x4266C6A4UL))
+#define bFM3_GPIO_EPFR13_TIOA13E0              *((volatile unsigned int*)(0x4266C6A8UL))
+#define bFM3_GPIO_EPFR13_TIOA13E1              *((volatile unsigned int*)(0x4266C6ACUL))
+#define bFM3_GPIO_EPFR13_TIOB13S0              *((volatile unsigned int*)(0x4266C6B0UL))
+#define bFM3_GPIO_EPFR13_TIOB13S1              *((volatile unsigned int*)(0x4266C6B4UL))
+#define bFM3_GPIO_EPFR13_TIOA14E0              *((volatile unsigned int*)(0x4266C6C8UL))
+#define bFM3_GPIO_EPFR13_TIOA14E1              *((volatile unsigned int*)(0x4266C6CCUL))
+#define bFM3_GPIO_EPFR13_TIOB14S0              *((volatile unsigned int*)(0x4266C6D0UL))
+#define bFM3_GPIO_EPFR13_TIOB14S1              *((volatile unsigned int*)(0x4266C6D4UL))
+#define bFM3_GPIO_EPFR13_TIOA15S0              *((volatile unsigned int*)(0x4266C6E0UL))
+#define bFM3_GPIO_EPFR13_TIOA15S1              *((volatile unsigned int*)(0x4266C6E4UL))
+#define bFM3_GPIO_EPFR13_TIOA15E0              *((volatile unsigned int*)(0x4266C6E8UL))
+#define bFM3_GPIO_EPFR13_TIOA15E1              *((volatile unsigned int*)(0x4266C6ECUL))
+#define bFM3_GPIO_EPFR13_TIOB15S0              *((volatile unsigned int*)(0x4266C6F0UL))
+#define bFM3_GPIO_EPFR13_TIOB15S1              *((volatile unsigned int*)(0x4266C6F4UL))
+#define bFM3_GPIO_EPFR14_QAIN2S0               *((volatile unsigned int*)(0x4266C700UL))
+#define bFM3_GPIO_EPFR14_QAIN2S1               *((volatile unsigned int*)(0x4266C704UL))
+#define bFM3_GPIO_EPFR14_QBIN2S0               *((volatile unsigned int*)(0x4266C708UL))
+#define bFM3_GPIO_EPFR14_QBIN2S1               *((volatile unsigned int*)(0x4266C70CUL))
+#define bFM3_GPIO_EPFR14_QZIN2S0               *((volatile unsigned int*)(0x4266C710UL))
+#define bFM3_GPIO_EPFR14_QZIN2S1               *((volatile unsigned int*)(0x4266C714UL))
+#define bFM3_GPIO_EPFR14_E_TD0E                *((volatile unsigned int*)(0x4266C748UL))
+#define bFM3_GPIO_EPFR14_E_TD1E                *((volatile unsigned int*)(0x4266C74CUL))
+#define bFM3_GPIO_EPFR14_E_TE0E                *((volatile unsigned int*)(0x4266C750UL))
+#define bFM3_GPIO_EPFR14_E_TE1E                *((volatile unsigned int*)(0x4266C754UL))
+#define bFM3_GPIO_EPFR14_E_MC0E                *((volatile unsigned int*)(0x4266C758UL))
+#define bFM3_GPIO_EPFR14_E_MC1B                *((volatile unsigned int*)(0x4266C75CUL))
+#define bFM3_GPIO_EPFR14_E_MD0B                *((volatile unsigned int*)(0x4266C760UL))
+#define bFM3_GPIO_EPFR14_E_MD1B                *((volatile unsigned int*)(0x4266C764UL))
+#define bFM3_GPIO_EPFR14_E_CKE                 *((volatile unsigned int*)(0x4266C768UL))
+#define bFM3_GPIO_EPFR14_E_PSE                 *((volatile unsigned int*)(0x4266C76CUL))
+#define bFM3_GPIO_EPFR14_E_SPLC0               *((volatile unsigned int*)(0x4266C770UL))
+#define bFM3_GPIO_EPFR14_E_SPLC1               *((volatile unsigned int*)(0x4266C774UL))
+#define bFM3_GPIO_EPFR15_EINT16S0              *((volatile unsigned int*)(0x4266C780UL))
+#define bFM3_GPIO_EPFR15_EINT16S1              *((volatile unsigned int*)(0x4266C784UL))
+#define bFM3_GPIO_EPFR15_EINT17S0              *((volatile unsigned int*)(0x4266C788UL))
+#define bFM3_GPIO_EPFR15_EINT17S1              *((volatile unsigned int*)(0x4266C78CUL))
+#define bFM3_GPIO_EPFR15_EINT18S0              *((volatile unsigned int*)(0x4266C790UL))
+#define bFM3_GPIO_EPFR15_EINT18S1              *((volatile unsigned int*)(0x4266C794UL))
+#define bFM3_GPIO_EPFR15_EINT19S0              *((volatile unsigned int*)(0x4266C798UL))
+#define bFM3_GPIO_EPFR15_EINT19S1              *((volatile unsigned int*)(0x4266C79CUL))
+#define bFM3_GPIO_EPFR15_EINT20S0              *((volatile unsigned int*)(0x4266C7A0UL))
+#define bFM3_GPIO_EPFR15_EINT20S1              *((volatile unsigned int*)(0x4266C7A4UL))
+#define bFM3_GPIO_EPFR15_EINT21S0              *((volatile unsigned int*)(0x4266C7A8UL))
+#define bFM3_GPIO_EPFR15_EINT21S1              *((volatile unsigned int*)(0x4266C7ACUL))
+#define bFM3_GPIO_EPFR15_EINT22S0              *((volatile unsigned int*)(0x4266C7B0UL))
+#define bFM3_GPIO_EPFR15_EINT22S1              *((volatile unsigned int*)(0x4266C7B4UL))
+#define bFM3_GPIO_EPFR15_EINT23S0              *((volatile unsigned int*)(0x4266C7B8UL))
+#define bFM3_GPIO_EPFR15_EINT23S1              *((volatile unsigned int*)(0x4266C7BCUL))
+#define bFM3_GPIO_EPFR15_EINT24S0              *((volatile unsigned int*)(0x4266C7C0UL))
+#define bFM3_GPIO_EPFR15_EINT24S1              *((volatile unsigned int*)(0x4266C7C4UL))
+#define bFM3_GPIO_EPFR15_EINT25S0              *((volatile unsigned int*)(0x4266C7C8UL))
+#define bFM3_GPIO_EPFR15_EINT25S1              *((volatile unsigned int*)(0x4266C7CCUL))
+#define bFM3_GPIO_EPFR15_EINT26S0              *((volatile unsigned int*)(0x4266C7D0UL))
+#define bFM3_GPIO_EPFR15_EINT26S1              *((volatile unsigned int*)(0x4266C7D4UL))
+#define bFM3_GPIO_EPFR15_EINT27S0              *((volatile unsigned int*)(0x4266C7D8UL))
+#define bFM3_GPIO_EPFR15_EINT27S1              *((volatile unsigned int*)(0x4266C7DCUL))
+#define bFM3_GPIO_EPFR15_EINT28S0              *((volatile unsigned int*)(0x4266C7E0UL))
+#define bFM3_GPIO_EPFR15_EINT28S1              *((volatile unsigned int*)(0x4266C7E4UL))
+#define bFM3_GPIO_EPFR15_EINT29S0              *((volatile unsigned int*)(0x4266C7E8UL))
+#define bFM3_GPIO_EPFR15_EINT29S1              *((volatile unsigned int*)(0x4266C7ECUL))
+#define bFM3_GPIO_EPFR15_EINT30S0              *((volatile unsigned int*)(0x4266C7F0UL))
+#define bFM3_GPIO_EPFR15_EINT30S1              *((volatile unsigned int*)(0x4266C7F4UL))
+#define bFM3_GPIO_EPFR15_EINT31S0              *((volatile unsigned int*)(0x4266C7F8UL))
+#define bFM3_GPIO_EPFR15_EINT31S1              *((volatile unsigned int*)(0x4266C7FCUL))
+#define bFM3_GPIO_PZR0_P0                      *((volatile unsigned int*)(0x4266E000UL))
+#define bFM3_GPIO_PZR0_P1                      *((volatile unsigned int*)(0x4266E004UL))
+#define bFM3_GPIO_PZR0_P2                      *((volatile unsigned int*)(0x4266E008UL))
+#define bFM3_GPIO_PZR0_P3                      *((volatile unsigned int*)(0x4266E00CUL))
+#define bFM3_GPIO_PZR0_P4                      *((volatile unsigned int*)(0x4266E010UL))
+#define bFM3_GPIO_PZR0_P5                      *((volatile unsigned int*)(0x4266E014UL))
+#define bFM3_GPIO_PZR0_P6                      *((volatile unsigned int*)(0x4266E018UL))
+#define bFM3_GPIO_PZR0_P7                      *((volatile unsigned int*)(0x4266E01CUL))
+#define bFM3_GPIO_PZR0_P8                      *((volatile unsigned int*)(0x4266E020UL))
+#define bFM3_GPIO_PZR0_P9                      *((volatile unsigned int*)(0x4266E024UL))
+#define bFM3_GPIO_PZR1_P0                      *((volatile unsigned int*)(0x4266E080UL))
+#define bFM3_GPIO_PZR1_P1                      *((volatile unsigned int*)(0x4266E084UL))
+#define bFM3_GPIO_PZR1_P2                      *((volatile unsigned int*)(0x4266E088UL))
+#define bFM3_GPIO_PZR1_P3                      *((volatile unsigned int*)(0x4266E08CUL))
+#define bFM3_GPIO_PZR1_P4                      *((volatile unsigned int*)(0x4266E090UL))
+#define bFM3_GPIO_PZR1_P5                      *((volatile unsigned int*)(0x4266E094UL))
+#define bFM3_GPIO_PZR1_P6                      *((volatile unsigned int*)(0x4266E098UL))
+#define bFM3_GPIO_PZR1_P7                      *((volatile unsigned int*)(0x4266E09CUL))
+#define bFM3_GPIO_PZR1_P8                      *((volatile unsigned int*)(0x4266E0A0UL))
+#define bFM3_GPIO_PZR1_P9                      *((volatile unsigned int*)(0x4266E0A4UL))
+#define bFM3_GPIO_PZR1_PA                      *((volatile unsigned int*)(0x4266E0A8UL))
+#define bFM3_GPIO_PZR1_PB                      *((volatile unsigned int*)(0x4266E0ACUL))
+#define bFM3_GPIO_PZR1_PC                      *((volatile unsigned int*)(0x4266E0B0UL))
+#define bFM3_GPIO_PZR1_PD                      *((volatile unsigned int*)(0x4266E0B4UL))
+#define bFM3_GPIO_PZR1_PE                      *((volatile unsigned int*)(0x4266E0B8UL))
+#define bFM3_GPIO_PZR1_PF                      *((volatile unsigned int*)(0x4266E0BCUL))
+#define bFM3_GPIO_PZR2_P0                      *((volatile unsigned int*)(0x4266E100UL))
+#define bFM3_GPIO_PZR2_P1                      *((volatile unsigned int*)(0x4266E104UL))
+#define bFM3_GPIO_PZR2_P2                      *((volatile unsigned int*)(0x4266E108UL))
+#define bFM3_GPIO_PZR2_P3                      *((volatile unsigned int*)(0x4266E10CUL))
+#define bFM3_GPIO_PZR2_P4                      *((volatile unsigned int*)(0x4266E110UL))
+#define bFM3_GPIO_PZR2_P5                      *((volatile unsigned int*)(0x4266E114UL))
+#define bFM3_GPIO_PZR2_P6                      *((volatile unsigned int*)(0x4266E118UL))
+#define bFM3_GPIO_PZR2_P7                      *((volatile unsigned int*)(0x4266E11CUL))
+#define bFM3_GPIO_PZR2_P8                      *((volatile unsigned int*)(0x4266E120UL))
+#define bFM3_GPIO_PZR2_P9                      *((volatile unsigned int*)(0x4266E124UL))
+#define bFM3_GPIO_PZR3_P0                      *((volatile unsigned int*)(0x4266E180UL))
+#define bFM3_GPIO_PZR3_P1                      *((volatile unsigned int*)(0x4266E184UL))
+#define bFM3_GPIO_PZR3_P2                      *((volatile unsigned int*)(0x4266E188UL))
+#define bFM3_GPIO_PZR3_P3                      *((volatile unsigned int*)(0x4266E18CUL))
+#define bFM3_GPIO_PZR3_P4                      *((volatile unsigned int*)(0x4266E190UL))
+#define bFM3_GPIO_PZR3_P5                      *((volatile unsigned int*)(0x4266E194UL))
+#define bFM3_GPIO_PZR3_P6                      *((volatile unsigned int*)(0x4266E198UL))
+#define bFM3_GPIO_PZR3_P7                      *((volatile unsigned int*)(0x4266E19CUL))
+#define bFM3_GPIO_PZR3_P8                      *((volatile unsigned int*)(0x4266E1A0UL))
+#define bFM3_GPIO_PZR3_P9                      *((volatile unsigned int*)(0x4266E1A4UL))
+#define bFM3_GPIO_PZR3_PA                      *((volatile unsigned int*)(0x4266E1A8UL))
+#define bFM3_GPIO_PZR3_PB                      *((volatile unsigned int*)(0x4266E1ACUL))
+#define bFM3_GPIO_PZR3_PC                      *((volatile unsigned int*)(0x4266E1B0UL))
+#define bFM3_GPIO_PZR3_PD                      *((volatile unsigned int*)(0x4266E1B4UL))
+#define bFM3_GPIO_PZR3_PE                      *((volatile unsigned int*)(0x4266E1B8UL))
+#define bFM3_GPIO_PZR3_PF                      *((volatile unsigned int*)(0x4266E1BCUL))
+#define bFM3_GPIO_PZR4_P0                      *((volatile unsigned int*)(0x4266E200UL))
+#define bFM3_GPIO_PZR4_P1                      *((volatile unsigned int*)(0x4266E204UL))
+#define bFM3_GPIO_PZR4_P2                      *((volatile unsigned int*)(0x4266E208UL))
+#define bFM3_GPIO_PZR4_P3                      *((volatile unsigned int*)(0x4266E20CUL))
+#define bFM3_GPIO_PZR4_P4                      *((volatile unsigned int*)(0x4266E210UL))
+#define bFM3_GPIO_PZR4_P5                      *((volatile unsigned int*)(0x4266E214UL))
+#define bFM3_GPIO_PZR4_P6                      *((volatile unsigned int*)(0x4266E218UL))
+#define bFM3_GPIO_PZR4_P7                      *((volatile unsigned int*)(0x4266E21CUL))
+#define bFM3_GPIO_PZR4_P8                      *((volatile unsigned int*)(0x4266E220UL))
+#define bFM3_GPIO_PZR4_P9                      *((volatile unsigned int*)(0x4266E224UL))
+#define bFM3_GPIO_PZR4_PA                      *((volatile unsigned int*)(0x4266E228UL))
+#define bFM3_GPIO_PZR4_PB                      *((volatile unsigned int*)(0x4266E22CUL))
+#define bFM3_GPIO_PZR4_PC                      *((volatile unsigned int*)(0x4266E230UL))
+#define bFM3_GPIO_PZR4_PD                      *((volatile unsigned int*)(0x4266E234UL))
+#define bFM3_GPIO_PZR4_PE                      *((volatile unsigned int*)(0x4266E238UL))
+#define bFM3_GPIO_PZR5_P0                      *((volatile unsigned int*)(0x4266E280UL))
+#define bFM3_GPIO_PZR5_P1                      *((volatile unsigned int*)(0x4266E284UL))
+#define bFM3_GPIO_PZR5_P2                      *((volatile unsigned int*)(0x4266E288UL))
+#define bFM3_GPIO_PZR5_P3                      *((volatile unsigned int*)(0x4266E28CUL))
+#define bFM3_GPIO_PZR5_P4                      *((volatile unsigned int*)(0x4266E290UL))
+#define bFM3_GPIO_PZR5_P5                      *((volatile unsigned int*)(0x4266E294UL))
+#define bFM3_GPIO_PZR5_P6                      *((volatile unsigned int*)(0x4266E298UL))
+#define bFM3_GPIO_PZR5_P7                      *((volatile unsigned int*)(0x4266E29CUL))
+#define bFM3_GPIO_PZR5_P8                      *((volatile unsigned int*)(0x4266E2A0UL))
+#define bFM3_GPIO_PZR5_P9                      *((volatile unsigned int*)(0x4266E2A4UL))
+#define bFM3_GPIO_PZR5_PA                      *((volatile unsigned int*)(0x4266E2A8UL))
+#define bFM3_GPIO_PZR5_PB                      *((volatile unsigned int*)(0x4266E2ACUL))
+#define bFM3_GPIO_PZR5_PC                      *((volatile unsigned int*)(0x4266E2B0UL))
+#define bFM3_GPIO_PZR5_PD                      *((volatile unsigned int*)(0x4266E2B4UL))
+#define bFM3_GPIO_PZR6_P0                      *((volatile unsigned int*)(0x4266E300UL))
+#define bFM3_GPIO_PZR6_P1                      *((volatile unsigned int*)(0x4266E304UL))
+#define bFM3_GPIO_PZR6_P2                      *((volatile unsigned int*)(0x4266E308UL))
+#define bFM3_GPIO_PZR7_P0                      *((volatile unsigned int*)(0x4266E380UL))
+#define bFM3_GPIO_PZR7_P1                      *((volatile unsigned int*)(0x4266E384UL))
+#define bFM3_GPIO_PZR7_P2                      *((volatile unsigned int*)(0x4266E388UL))
+#define bFM3_GPIO_PZR7_P3                      *((volatile unsigned int*)(0x4266E38CUL))
+#define bFM3_GPIO_PZR7_P4                      *((volatile unsigned int*)(0x4266E390UL))
+#define bFM3_GPIO_PZR7_P5                      *((volatile unsigned int*)(0x4266E394UL))
+#define bFM3_GPIO_PZR7_P6                      *((volatile unsigned int*)(0x4266E398UL))
+#define bFM3_GPIO_PZR7_P7                      *((volatile unsigned int*)(0x4266E39CUL))
+#define bFM3_GPIO_PZR7_P8                      *((volatile unsigned int*)(0x4266E3A0UL))
+#define bFM3_GPIO_PZR7_P9                      *((volatile unsigned int*)(0x4266E3A4UL))
+#define bFM3_GPIO_PZR7_PA                      *((volatile unsigned int*)(0x4266E3A8UL))
+#define bFM3_GPIO_PZR7_PB                      *((volatile unsigned int*)(0x4266E3ACUL))
+#define bFM3_GPIO_PZR7_PC                      *((volatile unsigned int*)(0x4266E3B0UL))
+#define bFM3_GPIO_PZR7_PD                      *((volatile unsigned int*)(0x4266E3B4UL))
+#define bFM3_GPIO_PZR7_PE                      *((volatile unsigned int*)(0x4266E3B8UL))
+#define bFM3_GPIO_PZR7_PF                      *((volatile unsigned int*)(0x4266E3BCUL))
+#define bFM3_GPIO_PZR8_P0                      *((volatile unsigned int*)(0x4266E400UL))
+#define bFM3_GPIO_PZR8_P1                      *((volatile unsigned int*)(0x4266E404UL))
+#define bFM3_GPIO_PZR8_P2                      *((volatile unsigned int*)(0x4266E408UL))
+#define bFM3_GPIO_PZR8_P3                      *((volatile unsigned int*)(0x4266E40CUL))
+#define bFM3_GPIO_PZR9_P0                      *((volatile unsigned int*)(0x4266E480UL))
+#define bFM3_GPIO_PZR9_P1                      *((volatile unsigned int*)(0x4266E484UL))
+#define bFM3_GPIO_PZR9_P2                      *((volatile unsigned int*)(0x4266E488UL))
+#define bFM3_GPIO_PZR9_P3                      *((volatile unsigned int*)(0x4266E48CUL))
+#define bFM3_GPIO_PZR9_P4                      *((volatile unsigned int*)(0x4266E490UL))
+#define bFM3_GPIO_PZR9_P5                      *((volatile unsigned int*)(0x4266E494UL))
+#define bFM3_GPIO_PZRA_P0                      *((volatile unsigned int*)(0x4266E500UL))
+#define bFM3_GPIO_PZRA_P1                      *((volatile unsigned int*)(0x4266E504UL))
+#define bFM3_GPIO_PZRA_P2                      *((volatile unsigned int*)(0x4266E508UL))
+#define bFM3_GPIO_PZRA_P3                      *((volatile unsigned int*)(0x4266E50CUL))
+#define bFM3_GPIO_PZRA_P4                      *((volatile unsigned int*)(0x4266E510UL))
+#define bFM3_GPIO_PZRA_P5                      *((volatile unsigned int*)(0x4266E514UL))
+#define bFM3_GPIO_PZRB_P0                      *((volatile unsigned int*)(0x4266E580UL))
+#define bFM3_GPIO_PZRB_P1                      *((volatile unsigned int*)(0x4266E584UL))
+#define bFM3_GPIO_PZRB_P2                      *((volatile unsigned int*)(0x4266E588UL))
+#define bFM3_GPIO_PZRB_P3                      *((volatile unsigned int*)(0x4266E58CUL))
+#define bFM3_GPIO_PZRB_P4                      *((volatile unsigned int*)(0x4266E590UL))
+#define bFM3_GPIO_PZRB_P5                      *((volatile unsigned int*)(0x4266E594UL))
+#define bFM3_GPIO_PZRB_P6                      *((volatile unsigned int*)(0x4266E598UL))
+#define bFM3_GPIO_PZRB_P7                      *((volatile unsigned int*)(0x4266E59CUL))
+#define bFM3_GPIO_PZRC_P0                      *((volatile unsigned int*)(0x4266E600UL))
+#define bFM3_GPIO_PZRC_P1                      *((volatile unsigned int*)(0x4266E604UL))
+#define bFM3_GPIO_PZRC_P2                      *((volatile unsigned int*)(0x4266E608UL))
+#define bFM3_GPIO_PZRC_P3                      *((volatile unsigned int*)(0x4266E60CUL))
+#define bFM3_GPIO_PZRC_P4                      *((volatile unsigned int*)(0x4266E610UL))
+#define bFM3_GPIO_PZRC_P5                      *((volatile unsigned int*)(0x4266E614UL))
+#define bFM3_GPIO_PZRC_P6                      *((volatile unsigned int*)(0x4266E618UL))
+#define bFM3_GPIO_PZRC_P7                      *((volatile unsigned int*)(0x4266E61CUL))
+#define bFM3_GPIO_PZRC_P8                      *((volatile unsigned int*)(0x4266E620UL))
+#define bFM3_GPIO_PZRC_P9                      *((volatile unsigned int*)(0x4266E624UL))
+#define bFM3_GPIO_PZRC_PA                      *((volatile unsigned int*)(0x4266E628UL))
+#define bFM3_GPIO_PZRC_PB                      *((volatile unsigned int*)(0x4266E62CUL))
+#define bFM3_GPIO_PZRC_PC                      *((volatile unsigned int*)(0x4266E630UL))
+#define bFM3_GPIO_PZRC_PD                      *((volatile unsigned int*)(0x4266E634UL))
+#define bFM3_GPIO_PZRC_PE                      *((volatile unsigned int*)(0x4266E638UL))
+#define bFM3_GPIO_PZRC_PF                      *((volatile unsigned int*)(0x4266E63CUL))
+#define bFM3_GPIO_PZRD_P0                      *((volatile unsigned int*)(0x4266E680UL))
+#define bFM3_GPIO_PZRD_P1                      *((volatile unsigned int*)(0x4266E684UL))
+#define bFM3_GPIO_PZRD_P2                      *((volatile unsigned int*)(0x4266E688UL))
+#define bFM3_GPIO_PZRD_P3                      *((volatile unsigned int*)(0x4266E68CUL))
+#define bFM3_GPIO_PZRE_P0                      *((volatile unsigned int*)(0x4266E700UL))
+#define bFM3_GPIO_PZRE_P2                      *((volatile unsigned int*)(0x4266E708UL))
+#define bFM3_GPIO_PZRE_P3                      *((volatile unsigned int*)(0x4266E70CUL))
+#define bFM3_GPIO_PZRF_P0                      *((volatile unsigned int*)(0x4266E780UL))
+#define bFM3_GPIO_PZRF_P1                      *((volatile unsigned int*)(0x4266E784UL))
+#define bFM3_GPIO_PZRF_P2                      *((volatile unsigned int*)(0x4266E788UL))
+#define bFM3_GPIO_PZRF_P3                      *((volatile unsigned int*)(0x4266E78CUL))
+#define bFM3_GPIO_PZRF_P4                      *((volatile unsigned int*)(0x4266E790UL))
+#define bFM3_GPIO_PZRF_P5                      *((volatile unsigned int*)(0x4266E794UL))
+#define bFM3_GPIO_PZRF_P6                      *((volatile unsigned int*)(0x4266E798UL))
+
+/* Low voltage detection registers */
+#define bFM3_LVD_LVD_CTL_SVHI0                 *((volatile unsigned int*)(0x426A0008UL))
+#define bFM3_LVD_LVD_CTL_SVHI1                 *((volatile unsigned int*)(0x426A000CUL))
+#define bFM3_LVD_LVD_CTL_SVHI2                 *((volatile unsigned int*)(0x426A0010UL))
+#define bFM3_LVD_LVD_CTL_SVHI3                 *((volatile unsigned int*)(0x426A0014UL))
+#define bFM3_LVD_LVD_CTL_LVDIE                 *((volatile unsigned int*)(0x426A001CUL))
+#define bFM3_LVD_LVD_STR_LVDIR                 *((volatile unsigned int*)(0x426A009CUL))
+#define bFM3_LVD_LVD_CLR_LVDCL                 *((volatile unsigned int*)(0x426A011CUL))
+#define bFM3_LVD_LVD_STR2_LVDIRDY              *((volatile unsigned int*)(0x426A021CUL))
+
+/* USB clock registers */
+#define bFM3_USBETHERNETCLK_UCCR_UCEN0         *((volatile unsigned int*)(0x426C0000UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL0        *((volatile unsigned int*)(0x426C0004UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCSEL1        *((volatile unsigned int*)(0x426C0008UL))
+#define bFM3_USBETHERNETCLK_UCCR_UCEN1         *((volatile unsigned int*)(0x426C000CUL))
+#define bFM3_USBETHERNETCLK_UCCR_ECEN          *((volatile unsigned int*)(0x426C0010UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL0        *((volatile unsigned int*)(0x426C0014UL))
+#define bFM3_USBETHERNETCLK_UCCR_ECSEL1        *((volatile unsigned int*)(0x426C0018UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPLLEN       *((volatile unsigned int*)(0x426C0080UL))
+#define bFM3_USBETHERNETCLK_UPCR1_UPINC        *((volatile unsigned int*)(0x426C0084UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT0       *((volatile unsigned int*)(0x426C0100UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT1       *((volatile unsigned int*)(0x426C0104UL))
+#define bFM3_USBETHERNETCLK_UPCR2_UPOWT2       *((volatile unsigned int*)(0x426C0108UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK0       *((volatile unsigned int*)(0x426C0180UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK1       *((volatile unsigned int*)(0x426C0184UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK2       *((volatile unsigned int*)(0x426C0188UL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK3       *((volatile unsigned int*)(0x426C018CUL))
+#define bFM3_USBETHERNETCLK_UPCR3_UPLLK4       *((volatile unsigned int*)(0x426C0190UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN0       *((volatile unsigned int*)(0x426C0200UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN1       *((volatile unsigned int*)(0x426C0204UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN2       *((volatile unsigned int*)(0x426C0208UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN3       *((volatile unsigned int*)(0x426C020CUL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN4       *((volatile unsigned int*)(0x426C0210UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN5       *((volatile unsigned int*)(0x426C0214UL))
+#define bFM3_USBETHERNETCLK_UPCR4_UPLLN6       *((volatile unsigned int*)(0x426C0218UL))
+#define bFM3_USBETHERNETCLK_UP_STR_UPRDY       *((volatile unsigned int*)(0x426C0280UL))
+#define bFM3_USBETHERNETCLK_UPINT_ENR_UPCSE    *((volatile unsigned int*)(0x426C0300UL))
+#define bFM3_USBETHERNETCLK_UPINT_CLR_UPCSC    *((volatile unsigned int*)(0x426C0380UL))
+#define bFM3_USBETHERNETCLK_UPINT_STR_UPCSI    *((volatile unsigned int*)(0x426C0400UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM0       *((volatile unsigned int*)(0x426C0480UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM1       *((volatile unsigned int*)(0x426C0484UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM2       *((volatile unsigned int*)(0x426C0488UL))
+#define bFM3_USBETHERNETCLK_UPCR5_UPLLM3       *((volatile unsigned int*)(0x426C048CUL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR0        *((volatile unsigned int*)(0x426C0500UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR1        *((volatile unsigned int*)(0x426C0504UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR2        *((volatile unsigned int*)(0x426C0508UL))
+#define bFM3_USBETHERNETCLK_UPCR6_UBSR3        *((volatile unsigned int*)(0x426C050CUL))
+#define bFM3_USBETHERNETCLK_UPCR7_EPLLEN       *((volatile unsigned int*)(0x426C0580UL))
+#define bFM3_USBETHERNETCLK_USBEN0_USBEN0      *((volatile unsigned int*)(0x426C0600UL))
+#define bFM3_USBETHERNETCLK_USBEN1_USBEN1      *((volatile unsigned int*)(0x426C0680UL))
+
+/* UART asynchronous channel 0 registers */
+#define bFM3_MFS0_UART_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_UART_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_UART_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_UART_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_UART_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_UART_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_UART_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_UART_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_UART_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_UART_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_UART_ESCR_P                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_UART_ESCR_PEN                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_UART_ESCR_INV                *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_UART_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_UART_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_UART_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_UART_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_UART_SSR_FRE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_UART_SSR_PE                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_UART_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_UART_RDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_TDR_AD                  *((volatile unsigned int*)(0x42700120UL))
+#define bFM3_MFS0_UART_BGR_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_UART_BGR1_EXT                *((volatile unsigned int*)(0x427001BCUL))
+
+/* UART synchronous channel 0 registers */
+#define bFM3_MFS0_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42700004UL))
+#define bFM3_MFS0_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427000BCUL))
+
+/* UART LIN channel 0 registers */
+#define bFM3_MFS0_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42700000UL))
+#define bFM3_MFS0_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_LIN_SCR_MS                   *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_LIN_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427001BCUL))
+#define bFM3_MFS0_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427001BCUL))
+
+/* I2C channel 0 registers */
+#define bFM3_MFS0_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42700008UL))
+#define bFM3_MFS0_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270000CUL))
+#define bFM3_MFS0_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42700010UL))
+#define bFM3_MFS0_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42700020UL))
+#define bFM3_MFS0_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42700024UL))
+#define bFM3_MFS0_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42700028UL))
+#define bFM3_MFS0_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270002CUL))
+#define bFM3_MFS0_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42700030UL))
+#define bFM3_MFS0_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42700034UL))
+#define bFM3_MFS0_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42700038UL))
+#define bFM3_MFS0_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270003CUL))
+#define bFM3_MFS0_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42700080UL))
+#define bFM3_MFS0_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42700084UL))
+#define bFM3_MFS0_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42700088UL))
+#define bFM3_MFS0_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270008CUL))
+#define bFM3_MFS0_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42700090UL))
+#define bFM3_MFS0_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42700094UL))
+#define bFM3_MFS0_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42700098UL))
+#define bFM3_MFS0_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270009CUL))
+#define bFM3_MFS0_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427000A0UL))
+#define bFM3_MFS0_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427000A4UL))
+#define bFM3_MFS0_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427000A8UL))
+#define bFM3_MFS0_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427000ACUL))
+#define bFM3_MFS0_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427000B0UL))
+#define bFM3_MFS0_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427000B4UL))
+#define bFM3_MFS0_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427000B8UL))
+#define bFM3_MFS0_I2C_SSR_REC                  *((volatile unsigned int*)(0x427000BCUL))
+#define bFM3_MFS0_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42700200UL))
+#define bFM3_MFS0_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42700204UL))
+#define bFM3_MFS0_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42700208UL))
+#define bFM3_MFS0_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270020CUL))
+#define bFM3_MFS0_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42700210UL))
+#define bFM3_MFS0_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42700214UL))
+#define bFM3_MFS0_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42700218UL))
+#define bFM3_MFS0_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270021CUL))
+#define bFM3_MFS0_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42700220UL))
+#define bFM3_MFS0_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42700224UL))
+#define bFM3_MFS0_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42700228UL))
+#define bFM3_MFS0_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270022CUL))
+#define bFM3_MFS0_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42700230UL))
+#define bFM3_MFS0_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42700234UL))
+#define bFM3_MFS0_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42700238UL))
+#define bFM3_MFS0_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270023CUL))
+
+/* UART asynchronous channel 1 registers */
+#define bFM3_MFS1_UART_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_UART_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_UART_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_UART_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_UART_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_UART_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_UART_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_UART_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_UART_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_UART_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_UART_ESCR_P                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_UART_ESCR_PEN                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_UART_ESCR_INV                *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_UART_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_UART_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_UART_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_UART_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_UART_SSR_FRE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_UART_SSR_PE                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_UART_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_UART_RDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_TDR_AD                  *((volatile unsigned int*)(0x42702120UL))
+#define bFM3_MFS1_UART_BGR_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_UART_BGR1_EXT                *((volatile unsigned int*)(0x427021BCUL))
+
+/* UART synchronous channel 1 registers */
+#define bFM3_MFS1_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42702004UL))
+#define bFM3_MFS1_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427020BCUL))
+
+/* UART LIN channel 1 registers */
+#define bFM3_MFS1_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42702000UL))
+#define bFM3_MFS1_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_LIN_SCR_MS                   *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_LIN_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427021BCUL))
+#define bFM3_MFS1_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427021BCUL))
+
+/* I2C channel 1 registers */
+#define bFM3_MFS1_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42702008UL))
+#define bFM3_MFS1_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270200CUL))
+#define bFM3_MFS1_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42702010UL))
+#define bFM3_MFS1_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42702020UL))
+#define bFM3_MFS1_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42702024UL))
+#define bFM3_MFS1_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42702028UL))
+#define bFM3_MFS1_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270202CUL))
+#define bFM3_MFS1_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42702030UL))
+#define bFM3_MFS1_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42702034UL))
+#define bFM3_MFS1_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42702038UL))
+#define bFM3_MFS1_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270203CUL))
+#define bFM3_MFS1_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42702080UL))
+#define bFM3_MFS1_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42702084UL))
+#define bFM3_MFS1_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42702088UL))
+#define bFM3_MFS1_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270208CUL))
+#define bFM3_MFS1_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42702090UL))
+#define bFM3_MFS1_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42702094UL))
+#define bFM3_MFS1_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42702098UL))
+#define bFM3_MFS1_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270209CUL))
+#define bFM3_MFS1_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427020A0UL))
+#define bFM3_MFS1_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427020A4UL))
+#define bFM3_MFS1_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427020A8UL))
+#define bFM3_MFS1_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427020ACUL))
+#define bFM3_MFS1_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427020B0UL))
+#define bFM3_MFS1_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427020B4UL))
+#define bFM3_MFS1_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427020B8UL))
+#define bFM3_MFS1_I2C_SSR_REC                  *((volatile unsigned int*)(0x427020BCUL))
+#define bFM3_MFS1_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42702200UL))
+#define bFM3_MFS1_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42702204UL))
+#define bFM3_MFS1_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42702208UL))
+#define bFM3_MFS1_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270220CUL))
+#define bFM3_MFS1_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42702210UL))
+#define bFM3_MFS1_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42702214UL))
+#define bFM3_MFS1_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42702218UL))
+#define bFM3_MFS1_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270221CUL))
+#define bFM3_MFS1_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42702220UL))
+#define bFM3_MFS1_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42702224UL))
+#define bFM3_MFS1_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42702228UL))
+#define bFM3_MFS1_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270222CUL))
+#define bFM3_MFS1_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42702230UL))
+#define bFM3_MFS1_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42702234UL))
+#define bFM3_MFS1_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42702238UL))
+#define bFM3_MFS1_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270223CUL))
+
+/* UART asynchronous channel 2 registers */
+#define bFM3_MFS2_UART_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_UART_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_UART_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_UART_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_UART_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_UART_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_UART_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_UART_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_UART_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_UART_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_UART_ESCR_P                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_UART_ESCR_PEN                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_UART_ESCR_INV                *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_UART_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_UART_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_UART_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_UART_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_UART_SSR_FRE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_UART_SSR_PE                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_UART_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_UART_RDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_TDR_AD                  *((volatile unsigned int*)(0x42704120UL))
+#define bFM3_MFS2_UART_BGR_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_UART_BGR1_EXT                *((volatile unsigned int*)(0x427041BCUL))
+
+/* UART synchronous channel 2 registers */
+#define bFM3_MFS2_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42704004UL))
+#define bFM3_MFS2_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427040BCUL))
+
+/* UART LIN channel 2 registers */
+#define bFM3_MFS2_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42704000UL))
+#define bFM3_MFS2_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_LIN_SCR_MS                   *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_LIN_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427041BCUL))
+#define bFM3_MFS2_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427041BCUL))
+
+/* I2C channel 2 registers */
+#define bFM3_MFS2_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42704008UL))
+#define bFM3_MFS2_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270400CUL))
+#define bFM3_MFS2_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42704010UL))
+#define bFM3_MFS2_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42704020UL))
+#define bFM3_MFS2_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42704024UL))
+#define bFM3_MFS2_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42704028UL))
+#define bFM3_MFS2_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270402CUL))
+#define bFM3_MFS2_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42704030UL))
+#define bFM3_MFS2_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42704034UL))
+#define bFM3_MFS2_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42704038UL))
+#define bFM3_MFS2_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270403CUL))
+#define bFM3_MFS2_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42704080UL))
+#define bFM3_MFS2_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42704084UL))
+#define bFM3_MFS2_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42704088UL))
+#define bFM3_MFS2_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270408CUL))
+#define bFM3_MFS2_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42704090UL))
+#define bFM3_MFS2_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42704094UL))
+#define bFM3_MFS2_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42704098UL))
+#define bFM3_MFS2_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270409CUL))
+#define bFM3_MFS2_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427040A0UL))
+#define bFM3_MFS2_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427040A4UL))
+#define bFM3_MFS2_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427040A8UL))
+#define bFM3_MFS2_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427040ACUL))
+#define bFM3_MFS2_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427040B0UL))
+#define bFM3_MFS2_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427040B4UL))
+#define bFM3_MFS2_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427040B8UL))
+#define bFM3_MFS2_I2C_SSR_REC                  *((volatile unsigned int*)(0x427040BCUL))
+#define bFM3_MFS2_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42704200UL))
+#define bFM3_MFS2_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42704204UL))
+#define bFM3_MFS2_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42704208UL))
+#define bFM3_MFS2_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270420CUL))
+#define bFM3_MFS2_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42704210UL))
+#define bFM3_MFS2_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42704214UL))
+#define bFM3_MFS2_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42704218UL))
+#define bFM3_MFS2_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270421CUL))
+#define bFM3_MFS2_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42704220UL))
+#define bFM3_MFS2_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42704224UL))
+#define bFM3_MFS2_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42704228UL))
+#define bFM3_MFS2_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270422CUL))
+#define bFM3_MFS2_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42704230UL))
+#define bFM3_MFS2_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42704234UL))
+#define bFM3_MFS2_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42704238UL))
+#define bFM3_MFS2_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270423CUL))
+
+/* UART asynchronous channel 3 registers */
+#define bFM3_MFS3_UART_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_UART_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_UART_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_UART_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_UART_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_UART_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_UART_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_UART_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_UART_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_UART_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_UART_ESCR_P                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_UART_ESCR_PEN                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_UART_ESCR_INV                *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_UART_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_UART_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_UART_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_UART_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_UART_SSR_FRE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_UART_SSR_PE                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_UART_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_UART_RDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_TDR_AD                  *((volatile unsigned int*)(0x42706120UL))
+#define bFM3_MFS3_UART_BGR_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_UART_BGR1_EXT                *((volatile unsigned int*)(0x427061BCUL))
+
+/* UART synchronous channel 3 registers */
+#define bFM3_MFS3_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42706004UL))
+#define bFM3_MFS3_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427060BCUL))
+
+/* UART LIN channel 3 registers */
+#define bFM3_MFS3_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42706000UL))
+#define bFM3_MFS3_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_LIN_SCR_MS                   *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_LIN_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427061BCUL))
+#define bFM3_MFS3_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427061BCUL))
+
+/* I2C channel 3 registers */
+#define bFM3_MFS3_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42706008UL))
+#define bFM3_MFS3_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270600CUL))
+#define bFM3_MFS3_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42706010UL))
+#define bFM3_MFS3_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42706020UL))
+#define bFM3_MFS3_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42706024UL))
+#define bFM3_MFS3_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42706028UL))
+#define bFM3_MFS3_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270602CUL))
+#define bFM3_MFS3_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42706030UL))
+#define bFM3_MFS3_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42706034UL))
+#define bFM3_MFS3_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42706038UL))
+#define bFM3_MFS3_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270603CUL))
+#define bFM3_MFS3_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42706080UL))
+#define bFM3_MFS3_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42706084UL))
+#define bFM3_MFS3_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42706088UL))
+#define bFM3_MFS3_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270608CUL))
+#define bFM3_MFS3_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42706090UL))
+#define bFM3_MFS3_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42706094UL))
+#define bFM3_MFS3_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42706098UL))
+#define bFM3_MFS3_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270609CUL))
+#define bFM3_MFS3_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427060A0UL))
+#define bFM3_MFS3_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427060A4UL))
+#define bFM3_MFS3_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427060A8UL))
+#define bFM3_MFS3_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427060ACUL))
+#define bFM3_MFS3_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427060B0UL))
+#define bFM3_MFS3_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427060B4UL))
+#define bFM3_MFS3_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427060B8UL))
+#define bFM3_MFS3_I2C_SSR_REC                  *((volatile unsigned int*)(0x427060BCUL))
+#define bFM3_MFS3_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42706200UL))
+#define bFM3_MFS3_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42706204UL))
+#define bFM3_MFS3_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42706208UL))
+#define bFM3_MFS3_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270620CUL))
+#define bFM3_MFS3_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42706210UL))
+#define bFM3_MFS3_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42706214UL))
+#define bFM3_MFS3_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42706218UL))
+#define bFM3_MFS3_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270621CUL))
+#define bFM3_MFS3_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42706220UL))
+#define bFM3_MFS3_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42706224UL))
+#define bFM3_MFS3_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42706228UL))
+#define bFM3_MFS3_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270622CUL))
+#define bFM3_MFS3_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42706230UL))
+#define bFM3_MFS3_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42706234UL))
+#define bFM3_MFS3_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42706238UL))
+#define bFM3_MFS3_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270623CUL))
+
+/* UART asynchronous channel 4 registers */
+#define bFM3_MFS4_UART_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_UART_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_UART_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_UART_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_UART_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_UART_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_UART_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_UART_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_UART_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_UART_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_UART_ESCR_P                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_UART_ESCR_PEN                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_UART_ESCR_INV                *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_UART_ESCR_ESBL               *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_UART_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_UART_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_UART_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_UART_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_UART_SSR_FRE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_UART_SSR_PE                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_UART_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_UART_RDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_TDR_AD                  *((volatile unsigned int*)(0x42708120UL))
+#define bFM3_MFS4_UART_BGR_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_BGR1_EXT                *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_UART_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_UART_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_UART_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_UART_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_UART_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_UART_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_UART_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_UART_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_UART_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_UART_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_UART_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_UART_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART synchronous channel 4 registers */
+#define bFM3_MFS4_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x42708004UL))
+#define bFM3_MFS4_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_CSIO_SCR_MS                  *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_CSIO_SSR_REC                 *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART LIN channel 4 registers */
+#define bFM3_MFS4_LIN_SMR_SOE                  *((volatile unsigned int*)(0x42708000UL))
+#define bFM3_MFS4_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_LIN_SCR_TXE                  *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_LIN_SCR_RXE                  *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_LIN_SCR_RIE                  *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_LIN_SCR_LBR                  *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_LIN_SCR_MS                   *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_LIN_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_LIN_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_LIN_SSR_FRE                  *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_LIN_SSR_LBD                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_LIN_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_LIN_BGR_EXT                  *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x427081BCUL))
+#define bFM3_MFS4_LIN_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_LIN_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_LIN_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* I2C channel 4 registers */
+#define bFM3_MFS4_I2C_SMR_TIE                  *((volatile unsigned int*)(0x42708008UL))
+#define bFM3_MFS4_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270800CUL))
+#define bFM3_MFS4_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x42708010UL))
+#define bFM3_MFS4_I2C_IBCR_INT                 *((volatile unsigned int*)(0x42708020UL))
+#define bFM3_MFS4_I2C_IBCR_BER                 *((volatile unsigned int*)(0x42708024UL))
+#define bFM3_MFS4_I2C_IBCR_INTE                *((volatile unsigned int*)(0x42708028UL))
+#define bFM3_MFS4_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270802CUL))
+#define bFM3_MFS4_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x42708030UL))
+#define bFM3_MFS4_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x42708034UL))
+#define bFM3_MFS4_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x42708038UL))
+#define bFM3_MFS4_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270803CUL))
+#define bFM3_MFS4_I2C_IBSR_BB                  *((volatile unsigned int*)(0x42708080UL))
+#define bFM3_MFS4_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x42708084UL))
+#define bFM3_MFS4_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x42708088UL))
+#define bFM3_MFS4_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270808CUL))
+#define bFM3_MFS4_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x42708090UL))
+#define bFM3_MFS4_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x42708094UL))
+#define bFM3_MFS4_I2C_IBSR_RACK                *((volatile unsigned int*)(0x42708098UL))
+#define bFM3_MFS4_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270809CUL))
+#define bFM3_MFS4_I2C_SSR_TBI                  *((volatile unsigned int*)(0x427080A0UL))
+#define bFM3_MFS4_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x427080A4UL))
+#define bFM3_MFS4_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x427080A8UL))
+#define bFM3_MFS4_I2C_SSR_ORE                  *((volatile unsigned int*)(0x427080ACUL))
+#define bFM3_MFS4_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x427080B0UL))
+#define bFM3_MFS4_I2C_SSR_DMA                  *((volatile unsigned int*)(0x427080B4UL))
+#define bFM3_MFS4_I2C_SSR_TSET                 *((volatile unsigned int*)(0x427080B8UL))
+#define bFM3_MFS4_I2C_SSR_REC                  *((volatile unsigned int*)(0x427080BCUL))
+#define bFM3_MFS4_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x42708200UL))
+#define bFM3_MFS4_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x42708204UL))
+#define bFM3_MFS4_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x42708208UL))
+#define bFM3_MFS4_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270820CUL))
+#define bFM3_MFS4_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x42708210UL))
+#define bFM3_MFS4_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x42708214UL))
+#define bFM3_MFS4_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x42708218UL))
+#define bFM3_MFS4_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270821CUL))
+#define bFM3_MFS4_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x42708220UL))
+#define bFM3_MFS4_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x42708224UL))
+#define bFM3_MFS4_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x42708228UL))
+#define bFM3_MFS4_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270822CUL))
+#define bFM3_MFS4_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x42708230UL))
+#define bFM3_MFS4_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x42708234UL))
+#define bFM3_MFS4_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x42708238UL))
+#define bFM3_MFS4_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270823CUL))
+#define bFM3_MFS4_I2C_FCR_FE1                  *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR_FE2                  *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR_FSET                 *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR_FLD                  *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR_FLST                 *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR_FTST0                *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR_FTST1                *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x42708280UL))
+#define bFM3_MFS4_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x42708284UL))
+#define bFM3_MFS4_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x42708288UL))
+#define bFM3_MFS4_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270828CUL))
+#define bFM3_MFS4_I2C_FCR0_FSET                *((volatile unsigned int*)(0x42708290UL))
+#define bFM3_MFS4_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x42708294UL))
+#define bFM3_MFS4_I2C_FCR0_FLST                *((volatile unsigned int*)(0x42708298UL))
+#define bFM3_MFS4_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x427082A0UL))
+#define bFM3_MFS4_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x427082A4UL))
+#define bFM3_MFS4_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x427082A8UL))
+#define bFM3_MFS4_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x427082ACUL))
+#define bFM3_MFS4_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x427082B0UL))
+#define bFM3_MFS4_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x427082B8UL))
+#define bFM3_MFS4_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x427082BCUL))
+#define bFM3_MFS4_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270833CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x42708300UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x42708304UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x42708308UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270830CUL))
+#define bFM3_MFS4_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x42708310UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x42708314UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x42708318UL))
+#define bFM3_MFS4_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270831CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x42708320UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x42708324UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x42708328UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270832CUL))
+#define bFM3_MFS4_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x42708330UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x42708334UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x42708338UL))
+#define bFM3_MFS4_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270833CUL))
+
+/* UART asynchronous channel 5 registers */
+#define bFM3_MFS5_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_UART_ESCR_P                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_UART_ESCR_INV                *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_UART_SSR_PE                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_UART_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_UART_RDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_TDR_AD                  *((volatile unsigned int*)(0x4270A120UL))
+#define bFM3_MFS5_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART synchronous channel 5 registers */
+#define bFM3_MFS5_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270A004UL))
+#define bFM3_MFS5_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART LIN channel 5 registers */
+#define bFM3_MFS5_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270A000UL))
+#define bFM3_MFS5_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270A1BCUL))
+#define bFM3_MFS5_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* I2C channel 5 registers */
+#define bFM3_MFS5_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270A008UL))
+#define bFM3_MFS5_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270A00CUL))
+#define bFM3_MFS5_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270A010UL))
+#define bFM3_MFS5_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270A020UL))
+#define bFM3_MFS5_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270A024UL))
+#define bFM3_MFS5_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270A028UL))
+#define bFM3_MFS5_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270A02CUL))
+#define bFM3_MFS5_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270A030UL))
+#define bFM3_MFS5_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270A034UL))
+#define bFM3_MFS5_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270A038UL))
+#define bFM3_MFS5_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270A03CUL))
+#define bFM3_MFS5_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270A080UL))
+#define bFM3_MFS5_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270A084UL))
+#define bFM3_MFS5_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270A088UL))
+#define bFM3_MFS5_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270A08CUL))
+#define bFM3_MFS5_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270A090UL))
+#define bFM3_MFS5_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270A094UL))
+#define bFM3_MFS5_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270A098UL))
+#define bFM3_MFS5_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270A09CUL))
+#define bFM3_MFS5_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270A0A0UL))
+#define bFM3_MFS5_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270A0A4UL))
+#define bFM3_MFS5_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270A0A8UL))
+#define bFM3_MFS5_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270A0ACUL))
+#define bFM3_MFS5_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270A0B0UL))
+#define bFM3_MFS5_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270A0B4UL))
+#define bFM3_MFS5_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270A0B8UL))
+#define bFM3_MFS5_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270A0BCUL))
+#define bFM3_MFS5_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270A200UL))
+#define bFM3_MFS5_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270A204UL))
+#define bFM3_MFS5_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270A208UL))
+#define bFM3_MFS5_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270A20CUL))
+#define bFM3_MFS5_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270A210UL))
+#define bFM3_MFS5_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270A214UL))
+#define bFM3_MFS5_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270A218UL))
+#define bFM3_MFS5_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270A21CUL))
+#define bFM3_MFS5_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270A220UL))
+#define bFM3_MFS5_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270A224UL))
+#define bFM3_MFS5_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270A228UL))
+#define bFM3_MFS5_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270A22CUL))
+#define bFM3_MFS5_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270A230UL))
+#define bFM3_MFS5_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270A234UL))
+#define bFM3_MFS5_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270A238UL))
+#define bFM3_MFS5_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270A23CUL))
+#define bFM3_MFS5_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270A280UL))
+#define bFM3_MFS5_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270A284UL))
+#define bFM3_MFS5_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270A288UL))
+#define bFM3_MFS5_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270A28CUL))
+#define bFM3_MFS5_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270A290UL))
+#define bFM3_MFS5_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270A294UL))
+#define bFM3_MFS5_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270A298UL))
+#define bFM3_MFS5_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270A2A0UL))
+#define bFM3_MFS5_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270A2A4UL))
+#define bFM3_MFS5_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270A2A8UL))
+#define bFM3_MFS5_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270A2ACUL))
+#define bFM3_MFS5_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270A2B0UL))
+#define bFM3_MFS5_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270A2B8UL))
+#define bFM3_MFS5_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270A2BCUL))
+#define bFM3_MFS5_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270A33CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270A300UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270A304UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270A308UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270A30CUL))
+#define bFM3_MFS5_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270A310UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270A314UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270A318UL))
+#define bFM3_MFS5_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270A31CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270A320UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270A324UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270A328UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270A32CUL))
+#define bFM3_MFS5_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270A330UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270A334UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270A338UL))
+#define bFM3_MFS5_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270A33CUL))
+
+/* UART asynchronous channel 6 registers */
+#define bFM3_MFS6_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_UART_ESCR_P                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_UART_ESCR_INV                *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_UART_SSR_PE                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_UART_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_UART_RDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_TDR_AD                  *((volatile unsigned int*)(0x4270C120UL))
+#define bFM3_MFS6_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART synchronous channel 6 registers */
+#define bFM3_MFS6_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270C004UL))
+#define bFM3_MFS6_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART LIN channel 6 registers */
+#define bFM3_MFS6_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270C000UL))
+#define bFM3_MFS6_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270C1BCUL))
+#define bFM3_MFS6_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* I2C channel 6 registers */
+#define bFM3_MFS6_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270C008UL))
+#define bFM3_MFS6_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270C00CUL))
+#define bFM3_MFS6_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270C010UL))
+#define bFM3_MFS6_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270C020UL))
+#define bFM3_MFS6_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270C024UL))
+#define bFM3_MFS6_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270C028UL))
+#define bFM3_MFS6_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270C02CUL))
+#define bFM3_MFS6_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270C030UL))
+#define bFM3_MFS6_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270C034UL))
+#define bFM3_MFS6_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270C038UL))
+#define bFM3_MFS6_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270C03CUL))
+#define bFM3_MFS6_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270C080UL))
+#define bFM3_MFS6_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270C084UL))
+#define bFM3_MFS6_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270C088UL))
+#define bFM3_MFS6_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270C08CUL))
+#define bFM3_MFS6_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270C090UL))
+#define bFM3_MFS6_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270C094UL))
+#define bFM3_MFS6_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270C098UL))
+#define bFM3_MFS6_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270C09CUL))
+#define bFM3_MFS6_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270C0A0UL))
+#define bFM3_MFS6_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270C0A4UL))
+#define bFM3_MFS6_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270C0A8UL))
+#define bFM3_MFS6_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270C0ACUL))
+#define bFM3_MFS6_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270C0B0UL))
+#define bFM3_MFS6_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270C0B4UL))
+#define bFM3_MFS6_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270C0B8UL))
+#define bFM3_MFS6_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270C0BCUL))
+#define bFM3_MFS6_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270C200UL))
+#define bFM3_MFS6_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270C204UL))
+#define bFM3_MFS6_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270C208UL))
+#define bFM3_MFS6_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270C20CUL))
+#define bFM3_MFS6_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270C210UL))
+#define bFM3_MFS6_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270C214UL))
+#define bFM3_MFS6_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270C218UL))
+#define bFM3_MFS6_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270C21CUL))
+#define bFM3_MFS6_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270C220UL))
+#define bFM3_MFS6_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270C224UL))
+#define bFM3_MFS6_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270C228UL))
+#define bFM3_MFS6_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270C22CUL))
+#define bFM3_MFS6_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270C230UL))
+#define bFM3_MFS6_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270C234UL))
+#define bFM3_MFS6_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270C238UL))
+#define bFM3_MFS6_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270C23CUL))
+#define bFM3_MFS6_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270C280UL))
+#define bFM3_MFS6_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270C284UL))
+#define bFM3_MFS6_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270C288UL))
+#define bFM3_MFS6_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270C28CUL))
+#define bFM3_MFS6_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270C290UL))
+#define bFM3_MFS6_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270C294UL))
+#define bFM3_MFS6_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270C298UL))
+#define bFM3_MFS6_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270C2A0UL))
+#define bFM3_MFS6_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270C2A4UL))
+#define bFM3_MFS6_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270C2A8UL))
+#define bFM3_MFS6_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270C2ACUL))
+#define bFM3_MFS6_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270C2B0UL))
+#define bFM3_MFS6_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270C2B8UL))
+#define bFM3_MFS6_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270C2BCUL))
+#define bFM3_MFS6_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270C33CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270C300UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270C304UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270C308UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270C30CUL))
+#define bFM3_MFS6_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270C310UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270C314UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270C318UL))
+#define bFM3_MFS6_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270C31CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270C320UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270C324UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270C328UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270C32CUL))
+#define bFM3_MFS6_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270C330UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270C334UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270C338UL))
+#define bFM3_MFS6_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270C33CUL))
+
+/* UART asynchronous channel 7 registers */
+#define bFM3_MFS7_UART_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_UART_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_UART_SMR_SBL                 *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_UART_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_UART_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_UART_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_UART_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_UART_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_UART_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_UART_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_UART_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_UART_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_UART_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_UART_ESCR_P                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_UART_ESCR_PEN                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_UART_ESCR_INV                *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_UART_ESCR_ESBL               *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_UART_ESCR_FLWEN              *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_UART_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_UART_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_UART_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_UART_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_UART_SSR_FRE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_UART_SSR_PE                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_UART_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_UART_RDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_TDR_AD                  *((volatile unsigned int*)(0x4270E120UL))
+#define bFM3_MFS7_UART_BGR_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_BGR1_EXT                *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_UART_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_UART_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_UART_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_UART_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_UART_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_UART_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_UART_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_UART_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_UART_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_UART_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_UART_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_UART_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_UART_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_UART_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_UART_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_UART_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_UART_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_UART_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_UART_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_UART_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_UART_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_UART_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_UART_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_UART_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_UART_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_UART_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_UART_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_UART_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_UART_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART synchronous channel 7 registers */
+#define bFM3_MFS7_CSIO_SMR_SOE                 *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_CSIO_SMR_SCKE                *((volatile unsigned int*)(0x4270E004UL))
+#define bFM3_MFS7_CSIO_SMR_BDS                 *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_CSIO_SMR_SCINV               *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_CSIO_SMR_WUCR                *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_CSIO_SCR_TXE                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_CSIO_SCR_RXE                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_CSIO_SCR_TBIE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_CSIO_SCR_TIE                 *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_CSIO_SCR_RIE                 *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_CSIO_SCR_SPI                 *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_CSIO_SCR_MS                  *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_CSIO_SCR_UPCL                *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_CSIO_ESCR_L0                 *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_CSIO_ESCR_L1                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_CSIO_ESCR_L2                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_CSIO_ESCR_WT0                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_CSIO_ESCR_WT1                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_CSIO_ESCR_SOP                *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_CSIO_SSR_TBI                 *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_CSIO_SSR_TDRE                *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_CSIO_SSR_RDRF                *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_CSIO_SSR_ORE                 *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_CSIO_SSR_REC                 *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_CSIO_FCR_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FCR0_FE1                *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_CSIO_FCR0_FE2                *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL1               *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_CSIO_FCR0_FCL2               *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_CSIO_FCR0_FSET               *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_CSIO_FCR0_FLD                *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_CSIO_FCR0_FLST               *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_CSIO_FCR1_FSEL               *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTIE               *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_CSIO_FCR1_FDRQ               *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_CSIO_FCR1_FRIE               *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_CSIO_FCR1_FLSTE              *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST0              *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_CSIO_FCR1_FTST1              *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD0              *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD1              *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD2              *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD3              *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD4              *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD5              *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD6              *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_CSIO_FBYTE1_FD7              *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD8              *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD9              *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD10             *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD11             *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD12             *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD13             *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD14             *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_CSIO_FBYTE2_FD15             *((volatile unsigned int*)(0x4270E33CUL))
+
+/* UART LIN channel 7 registers */
+#define bFM3_MFS7_LIN_SMR_SOE                  *((volatile unsigned int*)(0x4270E000UL))
+#define bFM3_MFS7_LIN_SMR_SBL                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_LIN_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_LIN_SCR_TXE                  *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_LIN_SCR_RXE                  *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_LIN_SCR_TBIE                 *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_LIN_SCR_TIE                  *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_LIN_SCR_RIE                  *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_LIN_SCR_LBR                  *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_LIN_SCR_MS                   *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_LIN_SCR_UPCL                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_LIN_ESCR_DEL0                *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_LIN_ESCR_DEL1                *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_LIN_ESCR_LBL0                *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_LIN_ESCR_LBL1                *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_LIN_ESCR_LBIE                *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_LIN_ESCR_ESBL                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_LIN_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_LIN_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_LIN_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_LIN_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_LIN_SSR_FRE                  *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_LIN_SSR_LBD                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_LIN_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_LIN_BGR_EXT                  *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_BGR1_EXT                 *((volatile unsigned int*)(0x4270E1BCUL))
+#define bFM3_MFS7_LIN_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_LIN_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_LIN_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_LIN_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_LIN_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_LIN_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_LIN_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_LIN_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_LIN_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_LIN_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_LIN_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_LIN_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_LIN_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_LIN_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_LIN_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_LIN_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_LIN_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_LIN_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_LIN_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* I2C channel 7 registers */
+#define bFM3_MFS7_I2C_SMR_TIE                  *((volatile unsigned int*)(0x4270E008UL))
+#define bFM3_MFS7_I2C_SMR_RIE                  *((volatile unsigned int*)(0x4270E00CUL))
+#define bFM3_MFS7_I2C_SMR_WUCR                 *((volatile unsigned int*)(0x4270E010UL))
+#define bFM3_MFS7_I2C_IBCR_INT                 *((volatile unsigned int*)(0x4270E020UL))
+#define bFM3_MFS7_I2C_IBCR_BER                 *((volatile unsigned int*)(0x4270E024UL))
+#define bFM3_MFS7_I2C_IBCR_INTE                *((volatile unsigned int*)(0x4270E028UL))
+#define bFM3_MFS7_I2C_IBCR_CNDE                *((volatile unsigned int*)(0x4270E02CUL))
+#define bFM3_MFS7_I2C_IBCR_WSEL                *((volatile unsigned int*)(0x4270E030UL))
+#define bFM3_MFS7_I2C_IBCR_ACKE                *((volatile unsigned int*)(0x4270E034UL))
+#define bFM3_MFS7_I2C_IBCR_ACT                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_SCC                 *((volatile unsigned int*)(0x4270E038UL))
+#define bFM3_MFS7_I2C_IBCR_MSS                 *((volatile unsigned int*)(0x4270E03CUL))
+#define bFM3_MFS7_I2C_IBSR_BB                  *((volatile unsigned int*)(0x4270E080UL))
+#define bFM3_MFS7_I2C_IBSR_SPC                 *((volatile unsigned int*)(0x4270E084UL))
+#define bFM3_MFS7_I2C_IBSR_RSC                 *((volatile unsigned int*)(0x4270E088UL))
+#define bFM3_MFS7_I2C_IBSR_AL                  *((volatile unsigned int*)(0x4270E08CUL))
+#define bFM3_MFS7_I2C_IBSR_TRX                 *((volatile unsigned int*)(0x4270E090UL))
+#define bFM3_MFS7_I2C_IBSR_RSA                 *((volatile unsigned int*)(0x4270E094UL))
+#define bFM3_MFS7_I2C_IBSR_RACK                *((volatile unsigned int*)(0x4270E098UL))
+#define bFM3_MFS7_I2C_IBSR_FBT                 *((volatile unsigned int*)(0x4270E09CUL))
+#define bFM3_MFS7_I2C_SSR_TBI                  *((volatile unsigned int*)(0x4270E0A0UL))
+#define bFM3_MFS7_I2C_SSR_TDRE                 *((volatile unsigned int*)(0x4270E0A4UL))
+#define bFM3_MFS7_I2C_SSR_RDRF                 *((volatile unsigned int*)(0x4270E0A8UL))
+#define bFM3_MFS7_I2C_SSR_ORE                  *((volatile unsigned int*)(0x4270E0ACUL))
+#define bFM3_MFS7_I2C_SSR_TBIE                 *((volatile unsigned int*)(0x4270E0B0UL))
+#define bFM3_MFS7_I2C_SSR_DMA                  *((volatile unsigned int*)(0x4270E0B4UL))
+#define bFM3_MFS7_I2C_SSR_TSET                 *((volatile unsigned int*)(0x4270E0B8UL))
+#define bFM3_MFS7_I2C_SSR_REC                  *((volatile unsigned int*)(0x4270E0BCUL))
+#define bFM3_MFS7_I2C_ISBA_SA0                 *((volatile unsigned int*)(0x4270E200UL))
+#define bFM3_MFS7_I2C_ISBA_SA1                 *((volatile unsigned int*)(0x4270E204UL))
+#define bFM3_MFS7_I2C_ISBA_SA2                 *((volatile unsigned int*)(0x4270E208UL))
+#define bFM3_MFS7_I2C_ISBA_SA3                 *((volatile unsigned int*)(0x4270E20CUL))
+#define bFM3_MFS7_I2C_ISBA_SA4                 *((volatile unsigned int*)(0x4270E210UL))
+#define bFM3_MFS7_I2C_ISBA_SA5                 *((volatile unsigned int*)(0x4270E214UL))
+#define bFM3_MFS7_I2C_ISBA_SA6                 *((volatile unsigned int*)(0x4270E218UL))
+#define bFM3_MFS7_I2C_ISBA_SAEN                *((volatile unsigned int*)(0x4270E21CUL))
+#define bFM3_MFS7_I2C_ISMK_SM0                 *((volatile unsigned int*)(0x4270E220UL))
+#define bFM3_MFS7_I2C_ISMK_SM1                 *((volatile unsigned int*)(0x4270E224UL))
+#define bFM3_MFS7_I2C_ISMK_SM2                 *((volatile unsigned int*)(0x4270E228UL))
+#define bFM3_MFS7_I2C_ISMK_SM3                 *((volatile unsigned int*)(0x4270E22CUL))
+#define bFM3_MFS7_I2C_ISMK_SM4                 *((volatile unsigned int*)(0x4270E230UL))
+#define bFM3_MFS7_I2C_ISMK_SM5                 *((volatile unsigned int*)(0x4270E234UL))
+#define bFM3_MFS7_I2C_ISMK_SM6                 *((volatile unsigned int*)(0x4270E238UL))
+#define bFM3_MFS7_I2C_ISMK_EN                  *((volatile unsigned int*)(0x4270E23CUL))
+#define bFM3_MFS7_I2C_FCR_FE1                  *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR_FE2                  *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR_FCL1                 *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR_FCL2                 *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR_FSET                 *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR_FLD                  *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR_FLST                 *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR_FSEL                 *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR_FTIE                 *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR_FDRQ                 *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR_FRIE                 *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR_FLSTE                *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR_FTST0                *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR_FTST1                *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FCR0_FE1                 *((volatile unsigned int*)(0x4270E280UL))
+#define bFM3_MFS7_I2C_FCR0_FE2                 *((volatile unsigned int*)(0x4270E284UL))
+#define bFM3_MFS7_I2C_FCR0_FCL1                *((volatile unsigned int*)(0x4270E288UL))
+#define bFM3_MFS7_I2C_FCR0_FCL2                *((volatile unsigned int*)(0x4270E28CUL))
+#define bFM3_MFS7_I2C_FCR0_FSET                *((volatile unsigned int*)(0x4270E290UL))
+#define bFM3_MFS7_I2C_FCR0_FLD                 *((volatile unsigned int*)(0x4270E294UL))
+#define bFM3_MFS7_I2C_FCR0_FLST                *((volatile unsigned int*)(0x4270E298UL))
+#define bFM3_MFS7_I2C_FCR1_FSEL                *((volatile unsigned int*)(0x4270E2A0UL))
+#define bFM3_MFS7_I2C_FCR1_FTIE                *((volatile unsigned int*)(0x4270E2A4UL))
+#define bFM3_MFS7_I2C_FCR1_FDRQ                *((volatile unsigned int*)(0x4270E2A8UL))
+#define bFM3_MFS7_I2C_FCR1_FRIE                *((volatile unsigned int*)(0x4270E2ACUL))
+#define bFM3_MFS7_I2C_FCR1_FLSTE               *((volatile unsigned int*)(0x4270E2B0UL))
+#define bFM3_MFS7_I2C_FCR1_FTST0               *((volatile unsigned int*)(0x4270E2B8UL))
+#define bFM3_MFS7_I2C_FCR1_FTST1               *((volatile unsigned int*)(0x4270E2BCUL))
+#define bFM3_MFS7_I2C_FBYTE_FD0                *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE_FD1                *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE_FD2                *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE_FD3                *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD4                *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE_FD5                *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE_FD6                *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE_FD7                *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD8                *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE_FD9                *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE_FD10               *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE_FD11               *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE_FD12               *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE_FD13               *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE_FD14               *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE_FD15               *((volatile unsigned int*)(0x4270E33CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD0               *((volatile unsigned int*)(0x4270E300UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD1               *((volatile unsigned int*)(0x4270E304UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD2               *((volatile unsigned int*)(0x4270E308UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD3               *((volatile unsigned int*)(0x4270E30CUL))
+#define bFM3_MFS7_I2C_FBYTE1_FD4               *((volatile unsigned int*)(0x4270E310UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD5               *((volatile unsigned int*)(0x4270E314UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD6               *((volatile unsigned int*)(0x4270E318UL))
+#define bFM3_MFS7_I2C_FBYTE1_FD7               *((volatile unsigned int*)(0x4270E31CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD8               *((volatile unsigned int*)(0x4270E320UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD9               *((volatile unsigned int*)(0x4270E324UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD10              *((volatile unsigned int*)(0x4270E328UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD11              *((volatile unsigned int*)(0x4270E32CUL))
+#define bFM3_MFS7_I2C_FBYTE2_FD12              *((volatile unsigned int*)(0x4270E330UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD13              *((volatile unsigned int*)(0x4270E334UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD14              *((volatile unsigned int*)(0x4270E338UL))
+#define bFM3_MFS7_I2C_FBYTE2_FD15              *((volatile unsigned int*)(0x4270E33CUL))
+
+/* MFS Noise Filter Control registers */
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF00           *((volatile unsigned int*)(0x42710000UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF01           *((volatile unsigned int*)(0x42710004UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF10           *((volatile unsigned int*)(0x42710008UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF11           *((volatile unsigned int*)(0x4271000CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF20           *((volatile unsigned int*)(0x42710010UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF21           *((volatile unsigned int*)(0x42710014UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF30           *((volatile unsigned int*)(0x42710018UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF31           *((volatile unsigned int*)(0x4271001CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF40           *((volatile unsigned int*)(0x42710020UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF41           *((volatile unsigned int*)(0x42710024UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF50           *((volatile unsigned int*)(0x42710028UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF51           *((volatile unsigned int*)(0x4271002CUL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF60           *((volatile unsigned int*)(0x42710030UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF61           *((volatile unsigned int*)(0x42710034UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF70           *((volatile unsigned int*)(0x42710038UL))
+#define bFM3_MFS_NFC_I2CDNF_I2CDNF71           *((volatile unsigned int*)(0x4271003CUL))
+
+/* CRC registers */
+#define bFM3_CRC_CRCCR_INIT                    *((volatile unsigned int*)(0x42720000UL))
+#define bFM3_CRC_CRCCR_CRC32                   *((volatile unsigned int*)(0x42720004UL))
+#define bFM3_CRC_CRCCR_LTLEND                  *((volatile unsigned int*)(0x42720008UL))
+#define bFM3_CRC_CRCCR_LSBFST                  *((volatile unsigned int*)(0x4272000CUL))
+#define bFM3_CRC_CRCCR_CRCLTE                  *((volatile unsigned int*)(0x42720010UL))
+#define bFM3_CRC_CRCCR_CRCLSF                  *((volatile unsigned int*)(0x42720014UL))
+#define bFM3_CRC_CRCCR_FXOR                    *((volatile unsigned int*)(0x42720018UL))
+
+/* Watch counter registers */
+#define bFM3_WC_WCRD_CTR0                      *((volatile unsigned int*)(0x42740000UL))
+#define bFM3_WC_WCRD_CTR1                      *((volatile unsigned int*)(0x42740004UL))
+#define bFM3_WC_WCRD_CTR2                      *((volatile unsigned int*)(0x42740008UL))
+#define bFM3_WC_WCRD_CTR3                      *((volatile unsigned int*)(0x4274000CUL))
+#define bFM3_WC_WCRD_CTR4                      *((volatile unsigned int*)(0x42740010UL))
+#define bFM3_WC_WCRD_CTR5                      *((volatile unsigned int*)(0x42740014UL))
+#define bFM3_WC_WCRL_RLC0                      *((volatile unsigned int*)(0x42740020UL))
+#define bFM3_WC_WCRL_RLC1                      *((volatile unsigned int*)(0x42740024UL))
+#define bFM3_WC_WCRL_RLC2                      *((volatile unsigned int*)(0x42740028UL))
+#define bFM3_WC_WCRL_RLC3                      *((volatile unsigned int*)(0x4274002CUL))
+#define bFM3_WC_WCRL_RLC4                      *((volatile unsigned int*)(0x42740030UL))
+#define bFM3_WC_WCRL_RLC5                      *((volatile unsigned int*)(0x42740034UL))
+#define bFM3_WC_WCCR_WCIF                      *((volatile unsigned int*)(0x42740040UL))
+#define bFM3_WC_WCCR_WCIE                      *((volatile unsigned int*)(0x42740044UL))
+#define bFM3_WC_WCCR_CS0                       *((volatile unsigned int*)(0x42740048UL))
+#define bFM3_WC_WCCR_CS1                       *((volatile unsigned int*)(0x4274004CUL))
+#define bFM3_WC_WCCR_WCOP                      *((volatile unsigned int*)(0x42740058UL))
+#define bFM3_WC_WCCR_WCEN                      *((volatile unsigned int*)(0x4274005CUL))
+#define bFM3_WC_CLK_SEL_SEL_IN                 *((volatile unsigned int*)(0x42740200UL))
+#define bFM3_WC_CLK_SEL_SEL_OUT                *((volatile unsigned int*)(0x42740220UL))
+#define bFM3_WC_CLK_EN_CLK_EN                  *((volatile unsigned int*)(0x42740280UL))
+#define bFM3_WC_CLK_EN_CLK_EN_R                *((volatile unsigned int*)(0x42740284UL))
+
+/* External bus interface registers */
+#define bFM3_EXBUS_MODE0_WDTH0                 *((volatile unsigned int*)(0x427E0000UL))
+#define bFM3_EXBUS_MODE0_WDTH1                 *((volatile unsigned int*)(0x427E0004UL))
+#define bFM3_EXBUS_MODE0_RBMON                 *((volatile unsigned int*)(0x427E0008UL))
+#define bFM3_EXBUS_MODE0_WEOFF                 *((volatile unsigned int*)(0x427E000CUL))
+#define bFM3_EXBUS_MODE0_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE0_PAGE                  *((volatile unsigned int*)(0x427E0014UL))
+#define bFM3_EXBUS_MODE0_RDY                   *((volatile unsigned int*)(0x427E0018UL))
+#define bFM3_EXBUS_MODE0_SHRTDOUT              *((volatile unsigned int*)(0x427E001CUL))
+#define bFM3_EXBUS_MODE0_MPXMODE               *((volatile unsigned int*)(0x427E0020UL))
+#define bFM3_EXBUS_MODE0_ALEINV                *((volatile unsigned int*)(0x427E0024UL))
+#define bFM3_EXBUS_MODE0_MPXDOFF               *((volatile unsigned int*)(0x427E002CUL))
+#define bFM3_EXBUS_MODE0_MPXCSOF               *((volatile unsigned int*)(0x427E0030UL))
+#define bFM3_EXBUS_MODE0_MOEXEUP               *((volatile unsigned int*)(0x427E0034UL))
+#define bFM3_EXBUS_MODE1_WDTH0                 *((volatile unsigned int*)(0x427E0080UL))
+#define bFM3_EXBUS_MODE1_WDTH1                 *((volatile unsigned int*)(0x427E0084UL))
+#define bFM3_EXBUS_MODE1_RBMON                 *((volatile unsigned int*)(0x427E0088UL))
+#define bFM3_EXBUS_MODE1_WEOFF                 *((volatile unsigned int*)(0x427E008CUL))
+#define bFM3_EXBUS_MODE1_NAND                  *((volatile unsigned int*)(0x427E0090UL))
+#define bFM3_EXBUS_MODE1_PAGE                  *((volatile unsigned int*)(0x427E0094UL))
+#define bFM3_EXBUS_MODE1_RDY                   *((volatile unsigned int*)(0x427E0098UL))
+#define bFM3_EXBUS_MODE1_SHRTDOUT              *((volatile unsigned int*)(0x427E009CUL))
+#define bFM3_EXBUS_MODE1_MPXMODE               *((volatile unsigned int*)(0x427E00A0UL))
+#define bFM3_EXBUS_MODE1_ALEINV                *((volatile unsigned int*)(0x427E00A4UL))
+#define bFM3_EXBUS_MODE1_MPXDOFF               *((volatile unsigned int*)(0x427E00ACUL))
+#define bFM3_EXBUS_MODE1_MPXCSOF               *((volatile unsigned int*)(0x427E00B0UL))
+#define bFM3_EXBUS_MODE1_MOEXEUP               *((volatile unsigned int*)(0x427E00B4UL))
+#define bFM3_EXBUS_MODE2_WDTH0                 *((volatile unsigned int*)(0x427E0100UL))
+#define bFM3_EXBUS_MODE2_WDTH1                 *((volatile unsigned int*)(0x427E0104UL))
+#define bFM3_EXBUS_MODE2_RBMON                 *((volatile unsigned int*)(0x427E0108UL))
+#define bFM3_EXBUS_MODE2_WEOFF                 *((volatile unsigned int*)(0x427E010CUL))
+#define bFM3_EXBUS_MODE2_NAND                  *((volatile unsigned int*)(0x427E0110UL))
+#define bFM3_EXBUS_MODE2_PAGE                  *((volatile unsigned int*)(0x427E0114UL))
+#define bFM3_EXBUS_MODE2_RDY                   *((volatile unsigned int*)(0x427E0118UL))
+#define bFM3_EXBUS_MODE2_SHRTDOUT              *((volatile unsigned int*)(0x427E011CUL))
+#define bFM3_EXBUS_MODE2_MPXMODE               *((volatile unsigned int*)(0x427E0120UL))
+#define bFM3_EXBUS_MODE2_ALEINV                *((volatile unsigned int*)(0x427E0124UL))
+#define bFM3_EXBUS_MODE2_MPXDOFF               *((volatile unsigned int*)(0x427E012CUL))
+#define bFM3_EXBUS_MODE2_MPXCSOF               *((volatile unsigned int*)(0x427E0130UL))
+#define bFM3_EXBUS_MODE2_MOEXEUP               *((volatile unsigned int*)(0x427E0134UL))
+#define bFM3_EXBUS_MODE3_WDTH0                 *((volatile unsigned int*)(0x427E0180UL))
+#define bFM3_EXBUS_MODE3_WDTH1                 *((volatile unsigned int*)(0x427E0184UL))
+#define bFM3_EXBUS_MODE3_RBMON                 *((volatile unsigned int*)(0x427E0188UL))
+#define bFM3_EXBUS_MODE3_WEOFF                 *((volatile unsigned int*)(0x427E018CUL))
+#define bFM3_EXBUS_MODE3_NAND                  *((volatile unsigned int*)(0x427E0190UL))
+#define bFM3_EXBUS_MODE3_PAGE                  *((volatile unsigned int*)(0x427E0194UL))
+#define bFM3_EXBUS_MODE3_RDY                   *((volatile unsigned int*)(0x427E0198UL))
+#define bFM3_EXBUS_MODE3_SHRTDOUT              *((volatile unsigned int*)(0x427E019CUL))
+#define bFM3_EXBUS_MODE3_MPXMODE               *((volatile unsigned int*)(0x427E01A0UL))
+#define bFM3_EXBUS_MODE3_ALEINV                *((volatile unsigned int*)(0x427E01A4UL))
+#define bFM3_EXBUS_MODE3_MPXDOFF               *((volatile unsigned int*)(0x427E01ACUL))
+#define bFM3_EXBUS_MODE3_MPXCSOF               *((volatile unsigned int*)(0x427E01B0UL))
+#define bFM3_EXBUS_MODE3_MOEXEUP               *((volatile unsigned int*)(0x427E01B4UL))
+#define bFM3_EXBUS_MODE4_WDTH0                 *((volatile unsigned int*)(0x427E0200UL))
+#define bFM3_EXBUS_MODE4_WDTH1                 *((volatile unsigned int*)(0x427E0204UL))
+#define bFM3_EXBUS_MODE4_RBMON                 *((volatile unsigned int*)(0x427E0208UL))
+#define bFM3_EXBUS_MODE4_WEOFF                 *((volatile unsigned int*)(0x427E020CUL))
+#define bFM3_EXBUS_MODE4_NAND                  *((volatile unsigned int*)(0x427E0210UL))
+#define bFM3_EXBUS_MODE4_PAGE                  *((volatile unsigned int*)(0x427E0214UL))
+#define bFM3_EXBUS_MODE4_RDY                   *((volatile unsigned int*)(0x427E0218UL))
+#define bFM3_EXBUS_MODE4_SHRTDOUT              *((volatile unsigned int*)(0x427E021CUL))
+#define bFM3_EXBUS_MODE4_MPXMODE               *((volatile unsigned int*)(0x427E0220UL))
+#define bFM3_EXBUS_MODE4_ALEINV                *((volatile unsigned int*)(0x427E0224UL))
+#define bFM3_EXBUS_MODE4_MPXDOFF               *((volatile unsigned int*)(0x427E022CUL))
+#define bFM3_EXBUS_MODE4_MPXCSOF               *((volatile unsigned int*)(0x427E0230UL))
+#define bFM3_EXBUS_MODE4_MOEXEUP               *((volatile unsigned int*)(0x427E0234UL))
+#define bFM3_EXBUS_MODE5_WDTH0                 *((volatile unsigned int*)(0x427E0280UL))
+#define bFM3_EXBUS_MODE5_WDTH1                 *((volatile unsigned int*)(0x427E0284UL))
+#define bFM3_EXBUS_MODE5_RBMON                 *((volatile unsigned int*)(0x427E0288UL))
+#define bFM3_EXBUS_MODE5_WEOFF                 *((volatile unsigned int*)(0x427E028CUL))
+#define bFM3_EXBUS_MODE5_NAND                  *((volatile unsigned int*)(0x427E0290UL))
+#define bFM3_EXBUS_MODE5_PAGE                  *((volatile unsigned int*)(0x427E0294UL))
+#define bFM3_EXBUS_MODE5_RDY                   *((volatile unsigned int*)(0x427E0298UL))
+#define bFM3_EXBUS_MODE5_SHRTDOUT              *((volatile unsigned int*)(0x427E029CUL))
+#define bFM3_EXBUS_MODE5_MPXMODE               *((volatile unsigned int*)(0x427E02A0UL))
+#define bFM3_EXBUS_MODE5_ALEINV                *((volatile unsigned int*)(0x427E02A4UL))
+#define bFM3_EXBUS_MODE5_MPXDOFF               *((volatile unsigned int*)(0x427E02ACUL))
+#define bFM3_EXBUS_MODE5_MPXCSOF               *((volatile unsigned int*)(0x427E02B0UL))
+#define bFM3_EXBUS_MODE5_MOEXEUP               *((volatile unsigned int*)(0x427E02B4UL))
+#define bFM3_EXBUS_MODE6_WDTH0                 *((volatile unsigned int*)(0x427E0300UL))
+#define bFM3_EXBUS_MODE6_WDTH1                 *((volatile unsigned int*)(0x427E0304UL))
+#define bFM3_EXBUS_MODE6_RBMON                 *((volatile unsigned int*)(0x427E0308UL))
+#define bFM3_EXBUS_MODE6_WEOFF                 *((volatile unsigned int*)(0x427E030CUL))
+#define bFM3_EXBUS_MODE6_NAND                  *((volatile unsigned int*)(0x427E0310UL))
+#define bFM3_EXBUS_MODE6_PAGE                  *((volatile unsigned int*)(0x427E0314UL))
+#define bFM3_EXBUS_MODE6_RDY                   *((volatile unsigned int*)(0x427E0318UL))
+#define bFM3_EXBUS_MODE6_SHRTDOUT              *((volatile unsigned int*)(0x427E031CUL))
+#define bFM3_EXBUS_MODE6_MPXMODE               *((volatile unsigned int*)(0x427E0320UL))
+#define bFM3_EXBUS_MODE6_ALEINV                *((volatile unsigned int*)(0x427E0324UL))
+#define bFM3_EXBUS_MODE6_MPXDOFF               *((volatile unsigned int*)(0x427E032CUL))
+#define bFM3_EXBUS_MODE6_MPXCSOF               *((volatile unsigned int*)(0x427E0330UL))
+#define bFM3_EXBUS_MODE6_MOEXEUP               *((volatile unsigned int*)(0x427E0334UL))
+#define bFM3_EXBUS_MODE7_WDTH0                 *((volatile unsigned int*)(0x427E0380UL))
+#define bFM3_EXBUS_MODE7_WDTH1                 *((volatile unsigned int*)(0x427E0384UL))
+#define bFM3_EXBUS_MODE7_RBMON                 *((volatile unsigned int*)(0x427E0388UL))
+#define bFM3_EXBUS_MODE7_WEOFF                 *((volatile unsigned int*)(0x427E038CUL))
+#define bFM3_EXBUS_MODE7_NAND                  *((volatile unsigned int*)(0x427E0390UL))
+#define bFM3_EXBUS_MODE7_PAGE                  *((volatile unsigned int*)(0x427E0394UL))
+#define bFM3_EXBUS_MODE7_RDY                   *((volatile unsigned int*)(0x427E0398UL))
+#define bFM3_EXBUS_MODE7_SHRTDOUT              *((volatile unsigned int*)(0x427E039CUL))
+#define bFM3_EXBUS_MODE7_MPXMODE               *((volatile unsigned int*)(0x427E03A0UL))
+#define bFM3_EXBUS_MODE7_ALEINV                *((volatile unsigned int*)(0x427E03A4UL))
+#define bFM3_EXBUS_MODE7_MPXDOFF               *((volatile unsigned int*)(0x427E03ACUL))
+#define bFM3_EXBUS_MODE7_MPXCSOF               *((volatile unsigned int*)(0x427E03B0UL))
+#define bFM3_EXBUS_MODE7_MOEXEUP               *((volatile unsigned int*)(0x427E03B4UL))
+#define bFM3_EXBUS_TIM0_RACC0                  *((volatile unsigned int*)(0x427E0400UL))
+#define bFM3_EXBUS_TIM0_RACC1                  *((volatile unsigned int*)(0x427E0404UL))
+#define bFM3_EXBUS_TIM0_RACC2                  *((volatile unsigned int*)(0x427E0408UL))
+#define bFM3_EXBUS_TIM0_RACC3                  *((volatile unsigned int*)(0x427E040CUL))
+#define bFM3_EXBUS_TIM0_RADC0                  *((volatile unsigned int*)(0x427E0410UL))
+#define bFM3_EXBUS_TIM0_RADC1                  *((volatile unsigned int*)(0x427E0414UL))
+#define bFM3_EXBUS_TIM0_RADC2                  *((volatile unsigned int*)(0x427E0418UL))
+#define bFM3_EXBUS_TIM0_RADC3                  *((volatile unsigned int*)(0x427E041CUL))
+#define bFM3_EXBUS_TIM0_FRADC0                 *((volatile unsigned int*)(0x427E0420UL))
+#define bFM3_EXBUS_TIM0_FRADC1                 *((volatile unsigned int*)(0x427E0424UL))
+#define bFM3_EXBUS_TIM0_FRADC2                 *((volatile unsigned int*)(0x427E0428UL))
+#define bFM3_EXBUS_TIM0_FRADC3                 *((volatile unsigned int*)(0x427E042CUL))
+#define bFM3_EXBUS_TIM0_RIDLC0                 *((volatile unsigned int*)(0x427E0430UL))
+#define bFM3_EXBUS_TIM0_RIDLC1                 *((volatile unsigned int*)(0x427E0434UL))
+#define bFM3_EXBUS_TIM0_RIDLC2                 *((volatile unsigned int*)(0x427E0438UL))
+#define bFM3_EXBUS_TIM0_RIDLC3                 *((volatile unsigned int*)(0x427E043CUL))
+#define bFM3_EXBUS_TIM0_WACC0                  *((volatile unsigned int*)(0x427E0440UL))
+#define bFM3_EXBUS_TIM0_WACC1                  *((volatile unsigned int*)(0x427E0444UL))
+#define bFM3_EXBUS_TIM0_WACC2                  *((volatile unsigned int*)(0x427E0448UL))
+#define bFM3_EXBUS_TIM0_WACC3                  *((volatile unsigned int*)(0x427E044CUL))
+#define bFM3_EXBUS_TIM0_WADC0                  *((volatile unsigned int*)(0x427E0450UL))
+#define bFM3_EXBUS_TIM0_WADC1                  *((volatile unsigned int*)(0x427E0454UL))
+#define bFM3_EXBUS_TIM0_WADC2                  *((volatile unsigned int*)(0x427E0458UL))
+#define bFM3_EXBUS_TIM0_WADC3                  *((volatile unsigned int*)(0x427E045CUL))
+#define bFM3_EXBUS_TIM0_WWEC0                  *((volatile unsigned int*)(0x427E0460UL))
+#define bFM3_EXBUS_TIM0_WWEC1                  *((volatile unsigned int*)(0x427E0464UL))
+#define bFM3_EXBUS_TIM0_WWEC2                  *((volatile unsigned int*)(0x427E0468UL))
+#define bFM3_EXBUS_TIM0_WWEC3                  *((volatile unsigned int*)(0x427E046CUL))
+#define bFM3_EXBUS_TIM0_WIDLC0                 *((volatile unsigned int*)(0x427E0470UL))
+#define bFM3_EXBUS_TIM0_WIDLC1                 *((volatile unsigned int*)(0x427E0474UL))
+#define bFM3_EXBUS_TIM0_WIDLC2                 *((volatile unsigned int*)(0x427E0478UL))
+#define bFM3_EXBUS_TIM0_WIDLC3                 *((volatile unsigned int*)(0x427E047CUL))
+#define bFM3_EXBUS_TIM1_RACC0                  *((volatile unsigned int*)(0x427E0480UL))
+#define bFM3_EXBUS_TIM1_RACC1                  *((volatile unsigned int*)(0x427E0484UL))
+#define bFM3_EXBUS_TIM1_RACC2                  *((volatile unsigned int*)(0x427E0488UL))
+#define bFM3_EXBUS_TIM1_RACC3                  *((volatile unsigned int*)(0x427E048CUL))
+#define bFM3_EXBUS_TIM1_RADC0                  *((volatile unsigned int*)(0x427E0490UL))
+#define bFM3_EXBUS_TIM1_RADC1                  *((volatile unsigned int*)(0x427E0494UL))
+#define bFM3_EXBUS_TIM1_RADC2                  *((volatile unsigned int*)(0x427E0498UL))
+#define bFM3_EXBUS_TIM1_RADC3                  *((volatile unsigned int*)(0x427E049CUL))
+#define bFM3_EXBUS_TIM1_FRADC0                 *((volatile unsigned int*)(0x427E04A0UL))
+#define bFM3_EXBUS_TIM1_FRADC1                 *((volatile unsigned int*)(0x427E04A4UL))
+#define bFM3_EXBUS_TIM1_FRADC2                 *((volatile unsigned int*)(0x427E04A8UL))
+#define bFM3_EXBUS_TIM1_FRADC3                 *((volatile unsigned int*)(0x427E04ACUL))
+#define bFM3_EXBUS_TIM1_RIDLC0                 *((volatile unsigned int*)(0x427E04B0UL))
+#define bFM3_EXBUS_TIM1_RIDLC1                 *((volatile unsigned int*)(0x427E04B4UL))
+#define bFM3_EXBUS_TIM1_RIDLC2                 *((volatile unsigned int*)(0x427E04B8UL))
+#define bFM3_EXBUS_TIM1_RIDLC3                 *((volatile unsigned int*)(0x427E04BCUL))
+#define bFM3_EXBUS_TIM1_WACC0                  *((volatile unsigned int*)(0x427E04C0UL))
+#define bFM3_EXBUS_TIM1_WACC1                  *((volatile unsigned int*)(0x427E04C4UL))
+#define bFM3_EXBUS_TIM1_WACC2                  *((volatile unsigned int*)(0x427E04C8UL))
+#define bFM3_EXBUS_TIM1_WACC3                  *((volatile unsigned int*)(0x427E04CCUL))
+#define bFM3_EXBUS_TIM1_WADC0                  *((volatile unsigned int*)(0x427E04D0UL))
+#define bFM3_EXBUS_TIM1_WADC1                  *((volatile unsigned int*)(0x427E04D4UL))
+#define bFM3_EXBUS_TIM1_WADC2                  *((volatile unsigned int*)(0x427E04D8UL))
+#define bFM3_EXBUS_TIM1_WADC3                  *((volatile unsigned int*)(0x427E04DCUL))
+#define bFM3_EXBUS_TIM1_WWEC0                  *((volatile unsigned int*)(0x427E04E0UL))
+#define bFM3_EXBUS_TIM1_WWEC1                  *((volatile unsigned int*)(0x427E04E4UL))
+#define bFM3_EXBUS_TIM1_WWEC2                  *((volatile unsigned int*)(0x427E04E8UL))
+#define bFM3_EXBUS_TIM1_WWEC3                  *((volatile unsigned int*)(0x427E04ECUL))
+#define bFM3_EXBUS_TIM1_WIDLC0                 *((volatile unsigned int*)(0x427E04F0UL))
+#define bFM3_EXBUS_TIM1_WIDLC1                 *((volatile unsigned int*)(0x427E04F4UL))
+#define bFM3_EXBUS_TIM1_WIDLC2                 *((volatile unsigned int*)(0x427E04F8UL))
+#define bFM3_EXBUS_TIM1_WIDLC3                 *((volatile unsigned int*)(0x427E04FCUL))
+#define bFM3_EXBUS_TIM2_RACC0                  *((volatile unsigned int*)(0x427E0500UL))
+#define bFM3_EXBUS_TIM2_RACC1                  *((volatile unsigned int*)(0x427E0504UL))
+#define bFM3_EXBUS_TIM2_RACC2                  *((volatile unsigned int*)(0x427E0508UL))
+#define bFM3_EXBUS_TIM2_RACC3                  *((volatile unsigned int*)(0x427E050CUL))
+#define bFM3_EXBUS_TIM2_RADC0                  *((volatile unsigned int*)(0x427E0510UL))
+#define bFM3_EXBUS_TIM2_RADC1                  *((volatile unsigned int*)(0x427E0514UL))
+#define bFM3_EXBUS_TIM2_RADC2                  *((volatile unsigned int*)(0x427E0518UL))
+#define bFM3_EXBUS_TIM2_RADC3                  *((volatile unsigned int*)(0x427E051CUL))
+#define bFM3_EXBUS_TIM2_FRADC0                 *((volatile unsigned int*)(0x427E0520UL))
+#define bFM3_EXBUS_TIM2_FRADC1                 *((volatile unsigned int*)(0x427E0524UL))
+#define bFM3_EXBUS_TIM2_FRADC2                 *((volatile unsigned int*)(0x427E0528UL))
+#define bFM3_EXBUS_TIM2_FRADC3                 *((volatile unsigned int*)(0x427E052CUL))
+#define bFM3_EXBUS_TIM2_RIDLC0                 *((volatile unsigned int*)(0x427E0530UL))
+#define bFM3_EXBUS_TIM2_RIDLC1                 *((volatile unsigned int*)(0x427E0534UL))
+#define bFM3_EXBUS_TIM2_RIDLC2                 *((volatile unsigned int*)(0x427E0538UL))
+#define bFM3_EXBUS_TIM2_RIDLC3                 *((volatile unsigned int*)(0x427E053CUL))
+#define bFM3_EXBUS_TIM2_WACC0                  *((volatile unsigned int*)(0x427E0540UL))
+#define bFM3_EXBUS_TIM2_WACC1                  *((volatile unsigned int*)(0x427E0544UL))
+#define bFM3_EXBUS_TIM2_WACC2                  *((volatile unsigned int*)(0x427E0548UL))
+#define bFM3_EXBUS_TIM2_WACC3                  *((volatile unsigned int*)(0x427E054CUL))
+#define bFM3_EXBUS_TIM2_WADC0                  *((volatile unsigned int*)(0x427E0550UL))
+#define bFM3_EXBUS_TIM2_WADC1                  *((volatile unsigned int*)(0x427E0554UL))
+#define bFM3_EXBUS_TIM2_WADC2                  *((volatile unsigned int*)(0x427E0558UL))
+#define bFM3_EXBUS_TIM2_WADC3                  *((volatile unsigned int*)(0x427E055CUL))
+#define bFM3_EXBUS_TIM2_WWEC0                  *((volatile unsigned int*)(0x427E0560UL))
+#define bFM3_EXBUS_TIM2_WWEC1                  *((volatile unsigned int*)(0x427E0564UL))
+#define bFM3_EXBUS_TIM2_WWEC2                  *((volatile unsigned int*)(0x427E0568UL))
+#define bFM3_EXBUS_TIM2_WWEC3                  *((volatile unsigned int*)(0x427E056CUL))
+#define bFM3_EXBUS_TIM2_WIDLC0                 *((volatile unsigned int*)(0x427E0570UL))
+#define bFM3_EXBUS_TIM2_WIDLC1                 *((volatile unsigned int*)(0x427E0574UL))
+#define bFM3_EXBUS_TIM2_WIDLC2                 *((volatile unsigned int*)(0x427E0578UL))
+#define bFM3_EXBUS_TIM2_WIDLC3                 *((volatile unsigned int*)(0x427E057CUL))
+#define bFM3_EXBUS_TIM3_RACC0                  *((volatile unsigned int*)(0x427E0580UL))
+#define bFM3_EXBUS_TIM3_RACC1                  *((volatile unsigned int*)(0x427E0584UL))
+#define bFM3_EXBUS_TIM3_RACC2                  *((volatile unsigned int*)(0x427E0588UL))
+#define bFM3_EXBUS_TIM3_RACC3                  *((volatile unsigned int*)(0x427E058CUL))
+#define bFM3_EXBUS_TIM3_RADC0                  *((volatile unsigned int*)(0x427E0590UL))
+#define bFM3_EXBUS_TIM3_RADC1                  *((volatile unsigned int*)(0x427E0594UL))
+#define bFM3_EXBUS_TIM3_RADC2                  *((volatile unsigned int*)(0x427E0598UL))
+#define bFM3_EXBUS_TIM3_RADC3                  *((volatile unsigned int*)(0x427E059CUL))
+#define bFM3_EXBUS_TIM3_FRADC0                 *((volatile unsigned int*)(0x427E05A0UL))
+#define bFM3_EXBUS_TIM3_FRADC1                 *((volatile unsigned int*)(0x427E05A4UL))
+#define bFM3_EXBUS_TIM3_FRADC2                 *((volatile unsigned int*)(0x427E05A8UL))
+#define bFM3_EXBUS_TIM3_FRADC3                 *((volatile unsigned int*)(0x427E05ACUL))
+#define bFM3_EXBUS_TIM3_RIDLC0                 *((volatile unsigned int*)(0x427E05B0UL))
+#define bFM3_EXBUS_TIM3_RIDLC1                 *((volatile unsigned int*)(0x427E05B4UL))
+#define bFM3_EXBUS_TIM3_RIDLC2                 *((volatile unsigned int*)(0x427E05B8UL))
+#define bFM3_EXBUS_TIM3_RIDLC3                 *((volatile unsigned int*)(0x427E05BCUL))
+#define bFM3_EXBUS_TIM3_WACC0                  *((volatile unsigned int*)(0x427E05C0UL))
+#define bFM3_EXBUS_TIM3_WACC1                  *((volatile unsigned int*)(0x427E05C4UL))
+#define bFM3_EXBUS_TIM3_WACC2                  *((volatile unsigned int*)(0x427E05C8UL))
+#define bFM3_EXBUS_TIM3_WACC3                  *((volatile unsigned int*)(0x427E05CCUL))
+#define bFM3_EXBUS_TIM3_WADC0                  *((volatile unsigned int*)(0x427E05D0UL))
+#define bFM3_EXBUS_TIM3_WADC1                  *((volatile unsigned int*)(0x427E05D4UL))
+#define bFM3_EXBUS_TIM3_WADC2                  *((volatile unsigned int*)(0x427E05D8UL))
+#define bFM3_EXBUS_TIM3_WADC3                  *((volatile unsigned int*)(0x427E05DCUL))
+#define bFM3_EXBUS_TIM3_WWEC0                  *((volatile unsigned int*)(0x427E05E0UL))
+#define bFM3_EXBUS_TIM3_WWEC1                  *((volatile unsigned int*)(0x427E05E4UL))
+#define bFM3_EXBUS_TIM3_WWEC2                  *((volatile unsigned int*)(0x427E05E8UL))
+#define bFM3_EXBUS_TIM3_WWEC3                  *((volatile unsigned int*)(0x427E05ECUL))
+#define bFM3_EXBUS_TIM3_WIDLC0                 *((volatile unsigned int*)(0x427E05F0UL))
+#define bFM3_EXBUS_TIM3_WIDLC1                 *((volatile unsigned int*)(0x427E05F4UL))
+#define bFM3_EXBUS_TIM3_WIDLC2                 *((volatile unsigned int*)(0x427E05F8UL))
+#define bFM3_EXBUS_TIM3_WIDLC3                 *((volatile unsigned int*)(0x427E05FCUL))
+#define bFM3_EXBUS_TIM4_RACC0                  *((volatile unsigned int*)(0x427E0600UL))
+#define bFM3_EXBUS_TIM4_RACC1                  *((volatile unsigned int*)(0x427E0604UL))
+#define bFM3_EXBUS_TIM4_RACC2                  *((volatile unsigned int*)(0x427E0608UL))
+#define bFM3_EXBUS_TIM4_RACC3                  *((volatile unsigned int*)(0x427E060CUL))
+#define bFM3_EXBUS_TIM4_RADC0                  *((volatile unsigned int*)(0x427E0610UL))
+#define bFM3_EXBUS_TIM4_RADC1                  *((volatile unsigned int*)(0x427E0614UL))
+#define bFM3_EXBUS_TIM4_RADC2                  *((volatile unsigned int*)(0x427E0618UL))
+#define bFM3_EXBUS_TIM4_RADC3                  *((volatile unsigned int*)(0x427E061CUL))
+#define bFM3_EXBUS_TIM4_FRADC0                 *((volatile unsigned int*)(0x427E0620UL))
+#define bFM3_EXBUS_TIM4_FRADC1                 *((volatile unsigned int*)(0x427E0624UL))
+#define bFM3_EXBUS_TIM4_FRADC2                 *((volatile unsigned int*)(0x427E0628UL))
+#define bFM3_EXBUS_TIM4_FRADC3                 *((volatile unsigned int*)(0x427E062CUL))
+#define bFM3_EXBUS_TIM4_RIDLC0                 *((volatile unsigned int*)(0x427E0630UL))
+#define bFM3_EXBUS_TIM4_RIDLC1                 *((volatile unsigned int*)(0x427E0634UL))
+#define bFM3_EXBUS_TIM4_RIDLC2                 *((volatile unsigned int*)(0x427E0638UL))
+#define bFM3_EXBUS_TIM4_RIDLC3                 *((volatile unsigned int*)(0x427E063CUL))
+#define bFM3_EXBUS_TIM4_WACC0                  *((volatile unsigned int*)(0x427E0640UL))
+#define bFM3_EXBUS_TIM4_WACC1                  *((volatile unsigned int*)(0x427E0644UL))
+#define bFM3_EXBUS_TIM4_WACC2                  *((volatile unsigned int*)(0x427E0648UL))
+#define bFM3_EXBUS_TIM4_WACC3                  *((volatile unsigned int*)(0x427E064CUL))
+#define bFM3_EXBUS_TIM4_WADC0                  *((volatile unsigned int*)(0x427E0650UL))
+#define bFM3_EXBUS_TIM4_WADC1                  *((volatile unsigned int*)(0x427E0654UL))
+#define bFM3_EXBUS_TIM4_WADC2                  *((volatile unsigned int*)(0x427E0658UL))
+#define bFM3_EXBUS_TIM4_WADC3                  *((volatile unsigned int*)(0x427E065CUL))
+#define bFM3_EXBUS_TIM4_WWEC0                  *((volatile unsigned int*)(0x427E0660UL))
+#define bFM3_EXBUS_TIM4_WWEC1                  *((volatile unsigned int*)(0x427E0664UL))
+#define bFM3_EXBUS_TIM4_WWEC2                  *((volatile unsigned int*)(0x427E0668UL))
+#define bFM3_EXBUS_TIM4_WWEC3                  *((volatile unsigned int*)(0x427E066CUL))
+#define bFM3_EXBUS_TIM4_WIDLC0                 *((volatile unsigned int*)(0x427E0670UL))
+#define bFM3_EXBUS_TIM4_WIDLC1                 *((volatile unsigned int*)(0x427E0674UL))
+#define bFM3_EXBUS_TIM4_WIDLC2                 *((volatile unsigned int*)(0x427E0678UL))
+#define bFM3_EXBUS_TIM4_WIDLC3                 *((volatile unsigned int*)(0x427E067CUL))
+#define bFM3_EXBUS_TIM5_RACC0                  *((volatile unsigned int*)(0x427E0680UL))
+#define bFM3_EXBUS_TIM5_RACC1                  *((volatile unsigned int*)(0x427E0684UL))
+#define bFM3_EXBUS_TIM5_RACC2                  *((volatile unsigned int*)(0x427E0688UL))
+#define bFM3_EXBUS_TIM5_RACC3                  *((volatile unsigned int*)(0x427E068CUL))
+#define bFM3_EXBUS_TIM5_RADC0                  *((volatile unsigned int*)(0x427E0690UL))
+#define bFM3_EXBUS_TIM5_RADC1                  *((volatile unsigned int*)(0x427E0694UL))
+#define bFM3_EXBUS_TIM5_RADC2                  *((volatile unsigned int*)(0x427E0698UL))
+#define bFM3_EXBUS_TIM5_RADC3                  *((volatile unsigned int*)(0x427E069CUL))
+#define bFM3_EXBUS_TIM5_FRADC0                 *((volatile unsigned int*)(0x427E06A0UL))
+#define bFM3_EXBUS_TIM5_FRADC1                 *((volatile unsigned int*)(0x427E06A4UL))
+#define bFM3_EXBUS_TIM5_FRADC2                 *((volatile unsigned int*)(0x427E06A8UL))
+#define bFM3_EXBUS_TIM5_FRADC3                 *((volatile unsigned int*)(0x427E06ACUL))
+#define bFM3_EXBUS_TIM5_RIDLC0                 *((volatile unsigned int*)(0x427E06B0UL))
+#define bFM3_EXBUS_TIM5_RIDLC1                 *((volatile unsigned int*)(0x427E06B4UL))
+#define bFM3_EXBUS_TIM5_RIDLC2                 *((volatile unsigned int*)(0x427E06B8UL))
+#define bFM3_EXBUS_TIM5_RIDLC3                 *((volatile unsigned int*)(0x427E06BCUL))
+#define bFM3_EXBUS_TIM5_WACC0                  *((volatile unsigned int*)(0x427E06C0UL))
+#define bFM3_EXBUS_TIM5_WACC1                  *((volatile unsigned int*)(0x427E06C4UL))
+#define bFM3_EXBUS_TIM5_WACC2                  *((volatile unsigned int*)(0x427E06C8UL))
+#define bFM3_EXBUS_TIM5_WACC3                  *((volatile unsigned int*)(0x427E06CCUL))
+#define bFM3_EXBUS_TIM5_WADC0                  *((volatile unsigned int*)(0x427E06D0UL))
+#define bFM3_EXBUS_TIM5_WADC1                  *((volatile unsigned int*)(0x427E06D4UL))
+#define bFM3_EXBUS_TIM5_WADC2                  *((volatile unsigned int*)(0x427E06D8UL))
+#define bFM3_EXBUS_TIM5_WADC3                  *((volatile unsigned int*)(0x427E06DCUL))
+#define bFM3_EXBUS_TIM5_WWEC0                  *((volatile unsigned int*)(0x427E06E0UL))
+#define bFM3_EXBUS_TIM5_WWEC1                  *((volatile unsigned int*)(0x427E06E4UL))
+#define bFM3_EXBUS_TIM5_WWEC2                  *((volatile unsigned int*)(0x427E06E8UL))
+#define bFM3_EXBUS_TIM5_WWEC3                  *((volatile unsigned int*)(0x427E06ECUL))
+#define bFM3_EXBUS_TIM5_WIDLC0                 *((volatile unsigned int*)(0x427E06F0UL))
+#define bFM3_EXBUS_TIM5_WIDLC1                 *((volatile unsigned int*)(0x427E06F4UL))
+#define bFM3_EXBUS_TIM5_WIDLC2                 *((volatile unsigned int*)(0x427E06F8UL))
+#define bFM3_EXBUS_TIM5_WIDLC3                 *((volatile unsigned int*)(0x427E06FCUL))
+#define bFM3_EXBUS_TIM6_RACC0                  *((volatile unsigned int*)(0x427E0700UL))
+#define bFM3_EXBUS_TIM6_RACC1                  *((volatile unsigned int*)(0x427E0704UL))
+#define bFM3_EXBUS_TIM6_RACC2                  *((volatile unsigned int*)(0x427E0708UL))
+#define bFM3_EXBUS_TIM6_RACC3                  *((volatile unsigned int*)(0x427E070CUL))
+#define bFM3_EXBUS_TIM6_RADC0                  *((volatile unsigned int*)(0x427E0710UL))
+#define bFM3_EXBUS_TIM6_RADC1                  *((volatile unsigned int*)(0x427E0714UL))
+#define bFM3_EXBUS_TIM6_RADC2                  *((volatile unsigned int*)(0x427E0718UL))
+#define bFM3_EXBUS_TIM6_RADC3                  *((volatile unsigned int*)(0x427E071CUL))
+#define bFM3_EXBUS_TIM6_FRADC0                 *((volatile unsigned int*)(0x427E0720UL))
+#define bFM3_EXBUS_TIM6_FRADC1                 *((volatile unsigned int*)(0x427E0724UL))
+#define bFM3_EXBUS_TIM6_FRADC2                 *((volatile unsigned int*)(0x427E0728UL))
+#define bFM3_EXBUS_TIM6_FRADC3                 *((volatile unsigned int*)(0x427E072CUL))
+#define bFM3_EXBUS_TIM6_RIDLC0                 *((volatile unsigned int*)(0x427E0730UL))
+#define bFM3_EXBUS_TIM6_RIDLC1                 *((volatile unsigned int*)(0x427E0734UL))
+#define bFM3_EXBUS_TIM6_RIDLC2                 *((volatile unsigned int*)(0x427E0738UL))
+#define bFM3_EXBUS_TIM6_RIDLC3                 *((volatile unsigned int*)(0x427E073CUL))
+#define bFM3_EXBUS_TIM6_WACC0                  *((volatile unsigned int*)(0x427E0740UL))
+#define bFM3_EXBUS_TIM6_WACC1                  *((volatile unsigned int*)(0x427E0744UL))
+#define bFM3_EXBUS_TIM6_WACC2                  *((volatile unsigned int*)(0x427E0748UL))
+#define bFM3_EXBUS_TIM6_WACC3                  *((volatile unsigned int*)(0x427E074CUL))
+#define bFM3_EXBUS_TIM6_WADC0                  *((volatile unsigned int*)(0x427E0750UL))
+#define bFM3_EXBUS_TIM6_WADC1                  *((volatile unsigned int*)(0x427E0754UL))
+#define bFM3_EXBUS_TIM6_WADC2                  *((volatile unsigned int*)(0x427E0758UL))
+#define bFM3_EXBUS_TIM6_WADC3                  *((volatile unsigned int*)(0x427E075CUL))
+#define bFM3_EXBUS_TIM6_WWEC0                  *((volatile unsigned int*)(0x427E0760UL))
+#define bFM3_EXBUS_TIM6_WWEC1                  *((volatile unsigned int*)(0x427E0764UL))
+#define bFM3_EXBUS_TIM6_WWEC2                  *((volatile unsigned int*)(0x427E0768UL))
+#define bFM3_EXBUS_TIM6_WWEC3                  *((volatile unsigned int*)(0x427E076CUL))
+#define bFM3_EXBUS_TIM6_WIDLC0                 *((volatile unsigned int*)(0x427E0770UL))
+#define bFM3_EXBUS_TIM6_WIDLC1                 *((volatile unsigned int*)(0x427E0774UL))
+#define bFM3_EXBUS_TIM6_WIDLC2                 *((volatile unsigned int*)(0x427E0778UL))
+#define bFM3_EXBUS_TIM6_WIDLC3                 *((volatile unsigned int*)(0x427E077CUL))
+#define bFM3_EXBUS_TIM7_RACC0                  *((volatile unsigned int*)(0x427E0780UL))
+#define bFM3_EXBUS_TIM7_RACC1                  *((volatile unsigned int*)(0x427E0784UL))
+#define bFM3_EXBUS_TIM7_RACC2                  *((volatile unsigned int*)(0x427E0788UL))
+#define bFM3_EXBUS_TIM7_RACC3                  *((volatile unsigned int*)(0x427E078CUL))
+#define bFM3_EXBUS_TIM7_RADC0                  *((volatile unsigned int*)(0x427E0790UL))
+#define bFM3_EXBUS_TIM7_RADC1                  *((volatile unsigned int*)(0x427E0794UL))
+#define bFM3_EXBUS_TIM7_RADC2                  *((volatile unsigned int*)(0x427E0798UL))
+#define bFM3_EXBUS_TIM7_RADC3                  *((volatile unsigned int*)(0x427E079CUL))
+#define bFM3_EXBUS_TIM7_FRADC0                 *((volatile unsigned int*)(0x427E07A0UL))
+#define bFM3_EXBUS_TIM7_FRADC1                 *((volatile unsigned int*)(0x427E07A4UL))
+#define bFM3_EXBUS_TIM7_FRADC2                 *((volatile unsigned int*)(0x427E07A8UL))
+#define bFM3_EXBUS_TIM7_FRADC3                 *((volatile unsigned int*)(0x427E07ACUL))
+#define bFM3_EXBUS_TIM7_RIDLC0                 *((volatile unsigned int*)(0x427E07B0UL))
+#define bFM3_EXBUS_TIM7_RIDLC1                 *((volatile unsigned int*)(0x427E07B4UL))
+#define bFM3_EXBUS_TIM7_RIDLC2                 *((volatile unsigned int*)(0x427E07B8UL))
+#define bFM3_EXBUS_TIM7_RIDLC3                 *((volatile unsigned int*)(0x427E07BCUL))
+#define bFM3_EXBUS_TIM7_WACC0                  *((volatile unsigned int*)(0x427E07C0UL))
+#define bFM3_EXBUS_TIM7_WACC1                  *((volatile unsigned int*)(0x427E07C4UL))
+#define bFM3_EXBUS_TIM7_WACC2                  *((volatile unsigned int*)(0x427E07C8UL))
+#define bFM3_EXBUS_TIM7_WACC3                  *((volatile unsigned int*)(0x427E07CCUL))
+#define bFM3_EXBUS_TIM7_WADC0                  *((volatile unsigned int*)(0x427E07D0UL))
+#define bFM3_EXBUS_TIM7_WADC1                  *((volatile unsigned int*)(0x427E07D4UL))
+#define bFM3_EXBUS_TIM7_WADC2                  *((volatile unsigned int*)(0x427E07D8UL))
+#define bFM3_EXBUS_TIM7_WADC3                  *((volatile unsigned int*)(0x427E07DCUL))
+#define bFM3_EXBUS_TIM7_WWEC0                  *((volatile unsigned int*)(0x427E07E0UL))
+#define bFM3_EXBUS_TIM7_WWEC1                  *((volatile unsigned int*)(0x427E07E4UL))
+#define bFM3_EXBUS_TIM7_WWEC2                  *((volatile unsigned int*)(0x427E07E8UL))
+#define bFM3_EXBUS_TIM7_WWEC3                  *((volatile unsigned int*)(0x427E07ECUL))
+#define bFM3_EXBUS_TIM7_WIDLC0                 *((volatile unsigned int*)(0x427E07F0UL))
+#define bFM3_EXBUS_TIM7_WIDLC1                 *((volatile unsigned int*)(0x427E07F4UL))
+#define bFM3_EXBUS_TIM7_WIDLC2                 *((volatile unsigned int*)(0x427E07F8UL))
+#define bFM3_EXBUS_TIM7_WIDLC3                 *((volatile unsigned int*)(0x427E07FCUL))
+#define bFM3_EXBUS_AREA0_ADDR0                 *((volatile unsigned int*)(0x427E0800UL))
+#define bFM3_EXBUS_AREA0_ADDR1                 *((volatile unsigned int*)(0x427E0804UL))
+#define bFM3_EXBUS_AREA0_ADDR2                 *((volatile unsigned int*)(0x427E0808UL))
+#define bFM3_EXBUS_AREA0_ADDR3                 *((volatile unsigned int*)(0x427E080CUL))
+#define bFM3_EXBUS_AREA0_ADDR4                 *((volatile unsigned int*)(0x427E0810UL))
+#define bFM3_EXBUS_AREA0_ADDR5                 *((volatile unsigned int*)(0x427E0814UL))
+#define bFM3_EXBUS_AREA0_ADDR6                 *((volatile unsigned int*)(0x427E0818UL))
+#define bFM3_EXBUS_AREA0_ADDR7                 *((volatile unsigned int*)(0x427E081CUL))
+#define bFM3_EXBUS_AREA0_MASK0                 *((volatile unsigned int*)(0x427E0840UL))
+#define bFM3_EXBUS_AREA0_MASK1                 *((volatile unsigned int*)(0x427E0844UL))
+#define bFM3_EXBUS_AREA0_MASK2                 *((volatile unsigned int*)(0x427E0848UL))
+#define bFM3_EXBUS_AREA0_MASK3                 *((volatile unsigned int*)(0x427E084CUL))
+#define bFM3_EXBUS_AREA0_MASK4                 *((volatile unsigned int*)(0x427E0850UL))
+#define bFM3_EXBUS_AREA0_MASK5                 *((volatile unsigned int*)(0x427E0854UL))
+#define bFM3_EXBUS_AREA0_MASK6                 *((volatile unsigned int*)(0x427E0858UL))
+#define bFM3_EXBUS_AREA1_ADDR0                 *((volatile unsigned int*)(0x427E0880UL))
+#define bFM3_EXBUS_AREA1_ADDR1                 *((volatile unsigned int*)(0x427E0884UL))
+#define bFM3_EXBUS_AREA1_ADDR2                 *((volatile unsigned int*)(0x427E0888UL))
+#define bFM3_EXBUS_AREA1_ADDR3                 *((volatile unsigned int*)(0x427E088CUL))
+#define bFM3_EXBUS_AREA1_ADDR4                 *((volatile unsigned int*)(0x427E0890UL))
+#define bFM3_EXBUS_AREA1_ADDR5                 *((volatile unsigned int*)(0x427E0894UL))
+#define bFM3_EXBUS_AREA1_ADDR6                 *((volatile unsigned int*)(0x427E0898UL))
+#define bFM3_EXBUS_AREA1_ADDR7                 *((volatile unsigned int*)(0x427E089CUL))
+#define bFM3_EXBUS_AREA1_MASK0                 *((volatile unsigned int*)(0x427E08C0UL))
+#define bFM3_EXBUS_AREA1_MASK1                 *((volatile unsigned int*)(0x427E08C4UL))
+#define bFM3_EXBUS_AREA1_MASK2                 *((volatile unsigned int*)(0x427E08C8UL))
+#define bFM3_EXBUS_AREA1_MASK3                 *((volatile unsigned int*)(0x427E08CCUL))
+#define bFM3_EXBUS_AREA1_MASK4                 *((volatile unsigned int*)(0x427E08D0UL))
+#define bFM3_EXBUS_AREA1_MASK5                 *((volatile unsigned int*)(0x427E08D4UL))
+#define bFM3_EXBUS_AREA1_MASK6                 *((volatile unsigned int*)(0x427E08D8UL))
+#define bFM3_EXBUS_AREA2_ADDR0                 *((volatile unsigned int*)(0x427E0900UL))
+#define bFM3_EXBUS_AREA2_ADDR1                 *((volatile unsigned int*)(0x427E0904UL))
+#define bFM3_EXBUS_AREA2_ADDR2                 *((volatile unsigned int*)(0x427E0908UL))
+#define bFM3_EXBUS_AREA2_ADDR3                 *((volatile unsigned int*)(0x427E090CUL))
+#define bFM3_EXBUS_AREA2_ADDR4                 *((volatile unsigned int*)(0x427E0910UL))
+#define bFM3_EXBUS_AREA2_ADDR5                 *((volatile unsigned int*)(0x427E0914UL))
+#define bFM3_EXBUS_AREA2_ADDR6                 *((volatile unsigned int*)(0x427E0918UL))
+#define bFM3_EXBUS_AREA2_ADDR7                 *((volatile unsigned int*)(0x427E091CUL))
+#define bFM3_EXBUS_AREA2_MASK0                 *((volatile unsigned int*)(0x427E0940UL))
+#define bFM3_EXBUS_AREA2_MASK1                 *((volatile unsigned int*)(0x427E0944UL))
+#define bFM3_EXBUS_AREA2_MASK2                 *((volatile unsigned int*)(0x427E0948UL))
+#define bFM3_EXBUS_AREA2_MASK3                 *((volatile unsigned int*)(0x427E094CUL))
+#define bFM3_EXBUS_AREA2_MASK4                 *((volatile unsigned int*)(0x427E0950UL))
+#define bFM3_EXBUS_AREA2_MASK5                 *((volatile unsigned int*)(0x427E0954UL))
+#define bFM3_EXBUS_AREA2_MASK6                 *((volatile unsigned int*)(0x427E0958UL))
+#define bFM3_EXBUS_AREA3_ADDR0                 *((volatile unsigned int*)(0x427E0980UL))
+#define bFM3_EXBUS_AREA3_ADDR1                 *((volatile unsigned int*)(0x427E0984UL))
+#define bFM3_EXBUS_AREA3_ADDR2                 *((volatile unsigned int*)(0x427E0988UL))
+#define bFM3_EXBUS_AREA3_ADDR3                 *((volatile unsigned int*)(0x427E098CUL))
+#define bFM3_EXBUS_AREA3_ADDR4                 *((volatile unsigned int*)(0x427E0990UL))
+#define bFM3_EXBUS_AREA3_ADDR5                 *((volatile unsigned int*)(0x427E0994UL))
+#define bFM3_EXBUS_AREA3_ADDR6                 *((volatile unsigned int*)(0x427E0998UL))
+#define bFM3_EXBUS_AREA3_ADDR7                 *((volatile unsigned int*)(0x427E099CUL))
+#define bFM3_EXBUS_AREA3_MASK0                 *((volatile unsigned int*)(0x427E09C0UL))
+#define bFM3_EXBUS_AREA3_MASK1                 *((volatile unsigned int*)(0x427E09C4UL))
+#define bFM3_EXBUS_AREA3_MASK2                 *((volatile unsigned int*)(0x427E09C8UL))
+#define bFM3_EXBUS_AREA3_MASK3                 *((volatile unsigned int*)(0x427E09CCUL))
+#define bFM3_EXBUS_AREA3_MASK4                 *((volatile unsigned int*)(0x427E09D0UL))
+#define bFM3_EXBUS_AREA3_MASK5                 *((volatile unsigned int*)(0x427E09D4UL))
+#define bFM3_EXBUS_AREA3_MASK6                 *((volatile unsigned int*)(0x427E09D8UL))
+#define bFM3_EXBUS_AREA4_ADDR0                 *((volatile unsigned int*)(0x427E0A00UL))
+#define bFM3_EXBUS_AREA4_ADDR1                 *((volatile unsigned int*)(0x427E0A04UL))
+#define bFM3_EXBUS_AREA4_ADDR2                 *((volatile unsigned int*)(0x427E0A08UL))
+#define bFM3_EXBUS_AREA4_ADDR3                 *((volatile unsigned int*)(0x427E0A0CUL))
+#define bFM3_EXBUS_AREA4_ADDR4                 *((volatile unsigned int*)(0x427E0A10UL))
+#define bFM3_EXBUS_AREA4_ADDR5                 *((volatile unsigned int*)(0x427E0A14UL))
+#define bFM3_EXBUS_AREA4_ADDR6                 *((volatile unsigned int*)(0x427E0A18UL))
+#define bFM3_EXBUS_AREA4_ADDR7                 *((volatile unsigned int*)(0x427E0A1CUL))
+#define bFM3_EXBUS_AREA4_MASK0                 *((volatile unsigned int*)(0x427E0A40UL))
+#define bFM3_EXBUS_AREA4_MASK1                 *((volatile unsigned int*)(0x427E0A44UL))
+#define bFM3_EXBUS_AREA4_MASK2                 *((volatile unsigned int*)(0x427E0A48UL))
+#define bFM3_EXBUS_AREA4_MASK3                 *((volatile unsigned int*)(0x427E0A4CUL))
+#define bFM3_EXBUS_AREA4_MASK4                 *((volatile unsigned int*)(0x427E0A50UL))
+#define bFM3_EXBUS_AREA4_MASK5                 *((volatile unsigned int*)(0x427E0A54UL))
+#define bFM3_EXBUS_AREA4_MASK6                 *((volatile unsigned int*)(0x427E0A58UL))
+#define bFM3_EXBUS_AREA5_ADDR0                 *((volatile unsigned int*)(0x427E0A80UL))
+#define bFM3_EXBUS_AREA5_ADDR1                 *((volatile unsigned int*)(0x427E0A84UL))
+#define bFM3_EXBUS_AREA5_ADDR2                 *((volatile unsigned int*)(0x427E0A88UL))
+#define bFM3_EXBUS_AREA5_ADDR3                 *((volatile unsigned int*)(0x427E0A8CUL))
+#define bFM3_EXBUS_AREA5_ADDR4                 *((volatile unsigned int*)(0x427E0A90UL))
+#define bFM3_EXBUS_AREA5_ADDR5                 *((volatile unsigned int*)(0x427E0A94UL))
+#define bFM3_EXBUS_AREA5_ADDR6                 *((volatile unsigned int*)(0x427E0A98UL))
+#define bFM3_EXBUS_AREA5_ADDR7                 *((volatile unsigned int*)(0x427E0A9CUL))
+#define bFM3_EXBUS_AREA5_MASK0                 *((volatile unsigned int*)(0x427E0AC0UL))
+#define bFM3_EXBUS_AREA5_MASK1                 *((volatile unsigned int*)(0x427E0AC4UL))
+#define bFM3_EXBUS_AREA5_MASK2                 *((volatile unsigned int*)(0x427E0AC8UL))
+#define bFM3_EXBUS_AREA5_MASK3                 *((volatile unsigned int*)(0x427E0ACCUL))
+#define bFM3_EXBUS_AREA5_MASK4                 *((volatile unsigned int*)(0x427E0AD0UL))
+#define bFM3_EXBUS_AREA5_MASK5                 *((volatile unsigned int*)(0x427E0AD4UL))
+#define bFM3_EXBUS_AREA5_MASK6                 *((volatile unsigned int*)(0x427E0AD8UL))
+#define bFM3_EXBUS_AREA6_ADDR0                 *((volatile unsigned int*)(0x427E0B00UL))
+#define bFM3_EXBUS_AREA6_ADDR1                 *((volatile unsigned int*)(0x427E0B04UL))
+#define bFM3_EXBUS_AREA6_ADDR2                 *((volatile unsigned int*)(0x427E0B08UL))
+#define bFM3_EXBUS_AREA6_ADDR3                 *((volatile unsigned int*)(0x427E0B0CUL))
+#define bFM3_EXBUS_AREA6_ADDR4                 *((volatile unsigned int*)(0x427E0B10UL))
+#define bFM3_EXBUS_AREA6_ADDR5                 *((volatile unsigned int*)(0x427E0B14UL))
+#define bFM3_EXBUS_AREA6_ADDR6                 *((volatile unsigned int*)(0x427E0B18UL))
+#define bFM3_EXBUS_AREA6_ADDR7                 *((volatile unsigned int*)(0x427E0B1CUL))
+#define bFM3_EXBUS_AREA6_MASK0                 *((volatile unsigned int*)(0x427E0B40UL))
+#define bFM3_EXBUS_AREA6_MASK1                 *((volatile unsigned int*)(0x427E0B44UL))
+#define bFM3_EXBUS_AREA6_MASK2                 *((volatile unsigned int*)(0x427E0B48UL))
+#define bFM3_EXBUS_AREA6_MASK3                 *((volatile unsigned int*)(0x427E0B4CUL))
+#define bFM3_EXBUS_AREA6_MASK4                 *((volatile unsigned int*)(0x427E0B50UL))
+#define bFM3_EXBUS_AREA6_MASK5                 *((volatile unsigned int*)(0x427E0B54UL))
+#define bFM3_EXBUS_AREA6_MASK6                 *((volatile unsigned int*)(0x427E0B58UL))
+#define bFM3_EXBUS_AREA7_ADDR0                 *((volatile unsigned int*)(0x427E0B80UL))
+#define bFM3_EXBUS_AREA7_ADDR1                 *((volatile unsigned int*)(0x427E0B84UL))
+#define bFM3_EXBUS_AREA7_ADDR2                 *((volatile unsigned int*)(0x427E0B88UL))
+#define bFM3_EXBUS_AREA7_ADDR3                 *((volatile unsigned int*)(0x427E0B8CUL))
+#define bFM3_EXBUS_AREA7_ADDR4                 *((volatile unsigned int*)(0x427E0B90UL))
+#define bFM3_EXBUS_AREA7_ADDR5                 *((volatile unsigned int*)(0x427E0B94UL))
+#define bFM3_EXBUS_AREA7_ADDR6                 *((volatile unsigned int*)(0x427E0B98UL))
+#define bFM3_EXBUS_AREA7_ADDR7                 *((volatile unsigned int*)(0x427E0B9CUL))
+#define bFM3_EXBUS_AREA7_MASK0                 *((volatile unsigned int*)(0x427E0BC0UL))
+#define bFM3_EXBUS_AREA7_MASK1                 *((volatile unsigned int*)(0x427E0BC4UL))
+#define bFM3_EXBUS_AREA7_MASK2                 *((volatile unsigned int*)(0x427E0BC8UL))
+#define bFM3_EXBUS_AREA7_MASK3                 *((volatile unsigned int*)(0x427E0BCCUL))
+#define bFM3_EXBUS_AREA7_MASK4                 *((volatile unsigned int*)(0x427E0BD0UL))
+#define bFM3_EXBUS_AREA7_MASK5                 *((volatile unsigned int*)(0x427E0BD4UL))
+#define bFM3_EXBUS_AREA7_MASK6                 *((volatile unsigned int*)(0x427E0BD8UL))
+#define bFM3_EXBUS_ATIM0_ALC0                  *((volatile unsigned int*)(0x427E0C00UL))
+#define bFM3_EXBUS_ATIM0_ALC1                  *((volatile unsigned int*)(0x427E0C04UL))
+#define bFM3_EXBUS_ATIM0_ALC2                  *((volatile unsigned int*)(0x427E0C08UL))
+#define bFM3_EXBUS_ATIM0_ALC3                  *((volatile unsigned int*)(0x427E0C0CUL))
+#define bFM3_EXBUS_ATIM0_ALES0                 *((volatile unsigned int*)(0x427E0C10UL))
+#define bFM3_EXBUS_ATIM0_ALES1                 *((volatile unsigned int*)(0x427E0C14UL))
+#define bFM3_EXBUS_ATIM0_ALES2                 *((volatile unsigned int*)(0x427E0C18UL))
+#define bFM3_EXBUS_ATIM0_ALES3                 *((volatile unsigned int*)(0x427E0C1CUL))
+#define bFM3_EXBUS_ATIM0_ALEW0                 *((volatile unsigned int*)(0x427E0C20UL))
+#define bFM3_EXBUS_ATIM0_ALEW1                 *((volatile unsigned int*)(0x427E0C24UL))
+#define bFM3_EXBUS_ATIM0_ALEW2                 *((volatile unsigned int*)(0x427E0C28UL))
+#define bFM3_EXBUS_ATIM0_ALEW3                 *((volatile unsigned int*)(0x427E0C2CUL))
+#define bFM3_EXBUS_ATIM1_ALC0                  *((volatile unsigned int*)(0x427E0C80UL))
+#define bFM3_EXBUS_ATIM1_ALC1                  *((volatile unsigned int*)(0x427E0C84UL))
+#define bFM3_EXBUS_ATIM1_ALC2                  *((volatile unsigned int*)(0x427E0C88UL))
+#define bFM3_EXBUS_ATIM1_ALC3                  *((volatile unsigned int*)(0x427E0C8CUL))
+#define bFM3_EXBUS_ATIM1_ALES0                 *((volatile unsigned int*)(0x427E0C90UL))
+#define bFM3_EXBUS_ATIM1_ALES1                 *((volatile unsigned int*)(0x427E0C94UL))
+#define bFM3_EXBUS_ATIM1_ALES2                 *((volatile unsigned int*)(0x427E0C98UL))
+#define bFM3_EXBUS_ATIM1_ALES3                 *((volatile unsigned int*)(0x427E0C9CUL))
+#define bFM3_EXBUS_ATIM1_ALEW0                 *((volatile unsigned int*)(0x427E0CA0UL))
+#define bFM3_EXBUS_ATIM1_ALEW1                 *((volatile unsigned int*)(0x427E0CA4UL))
+#define bFM3_EXBUS_ATIM1_ALEW2                 *((volatile unsigned int*)(0x427E0CA8UL))
+#define bFM3_EXBUS_ATIM1_ALEW3                 *((volatile unsigned int*)(0x427E0CACUL))
+#define bFM3_EXBUS_ATIM2_ALC0                  *((volatile unsigned int*)(0x427E0D00UL))
+#define bFM3_EXBUS_ATIM2_ALC1                  *((volatile unsigned int*)(0x427E0D04UL))
+#define bFM3_EXBUS_ATIM2_ALC2                  *((volatile unsigned int*)(0x427E0D08UL))
+#define bFM3_EXBUS_ATIM2_ALC3                  *((volatile unsigned int*)(0x427E0D0CUL))
+#define bFM3_EXBUS_ATIM2_ALES0                 *((volatile unsigned int*)(0x427E0D10UL))
+#define bFM3_EXBUS_ATIM2_ALES1                 *((volatile unsigned int*)(0x427E0D14UL))
+#define bFM3_EXBUS_ATIM2_ALES2                 *((volatile unsigned int*)(0x427E0D18UL))
+#define bFM3_EXBUS_ATIM2_ALES3                 *((volatile unsigned int*)(0x427E0D1CUL))
+#define bFM3_EXBUS_ATIM2_ALEW0                 *((volatile unsigned int*)(0x427E0D20UL))
+#define bFM3_EXBUS_ATIM2_ALEW1                 *((volatile unsigned int*)(0x427E0D24UL))
+#define bFM3_EXBUS_ATIM2_ALEW2                 *((volatile unsigned int*)(0x427E0D28UL))
+#define bFM3_EXBUS_ATIM2_ALEW3                 *((volatile unsigned int*)(0x427E0D2CUL))
+#define bFM3_EXBUS_ATIM3_ALC0                  *((volatile unsigned int*)(0x427E0D80UL))
+#define bFM3_EXBUS_ATIM3_ALC1                  *((volatile unsigned int*)(0x427E0D84UL))
+#define bFM3_EXBUS_ATIM3_ALC2                  *((volatile unsigned int*)(0x427E0D88UL))
+#define bFM3_EXBUS_ATIM3_ALC3                  *((volatile unsigned int*)(0x427E0D8CUL))
+#define bFM3_EXBUS_ATIM3_ALES0                 *((volatile unsigned int*)(0x427E0D90UL))
+#define bFM3_EXBUS_ATIM3_ALES1                 *((volatile unsigned int*)(0x427E0D94UL))
+#define bFM3_EXBUS_ATIM3_ALES2                 *((volatile unsigned int*)(0x427E0D98UL))
+#define bFM3_EXBUS_ATIM3_ALES3                 *((volatile unsigned int*)(0x427E0D9CUL))
+#define bFM3_EXBUS_ATIM3_ALEW0                 *((volatile unsigned int*)(0x427E0DA0UL))
+#define bFM3_EXBUS_ATIM3_ALEW1                 *((volatile unsigned int*)(0x427E0DA4UL))
+#define bFM3_EXBUS_ATIM3_ALEW2                 *((volatile unsigned int*)(0x427E0DA8UL))
+#define bFM3_EXBUS_ATIM3_ALEW3                 *((volatile unsigned int*)(0x427E0DACUL))
+#define bFM3_EXBUS_ATIM4_ALC0                  *((volatile unsigned int*)(0x427E0E00UL))
+#define bFM3_EXBUS_ATIM4_ALC1                  *((volatile unsigned int*)(0x427E0E04UL))
+#define bFM3_EXBUS_ATIM4_ALC2                  *((volatile unsigned int*)(0x427E0E08UL))
+#define bFM3_EXBUS_ATIM4_ALC3                  *((volatile unsigned int*)(0x427E0E0CUL))
+#define bFM3_EXBUS_ATIM4_ALES0                 *((volatile unsigned int*)(0x427E0E10UL))
+#define bFM3_EXBUS_ATIM4_ALES1                 *((volatile unsigned int*)(0x427E0E14UL))
+#define bFM3_EXBUS_ATIM4_ALES2                 *((volatile unsigned int*)(0x427E0E18UL))
+#define bFM3_EXBUS_ATIM4_ALES3                 *((volatile unsigned int*)(0x427E0E1CUL))
+#define bFM3_EXBUS_ATIM4_ALEW0                 *((volatile unsigned int*)(0x427E0E20UL))
+#define bFM3_EXBUS_ATIM4_ALEW1                 *((volatile unsigned int*)(0x427E0E24UL))
+#define bFM3_EXBUS_ATIM4_ALEW2                 *((volatile unsigned int*)(0x427E0E28UL))
+#define bFM3_EXBUS_ATIM4_ALEW3                 *((volatile unsigned int*)(0x427E0E2CUL))
+#define bFM3_EXBUS_ATIM5_ALC0                  *((volatile unsigned int*)(0x427E0E80UL))
+#define bFM3_EXBUS_ATIM5_ALC1                  *((volatile unsigned int*)(0x427E0E84UL))
+#define bFM3_EXBUS_ATIM5_ALC2                  *((volatile unsigned int*)(0x427E0E88UL))
+#define bFM3_EXBUS_ATIM5_ALC3                  *((volatile unsigned int*)(0x427E0E8CUL))
+#define bFM3_EXBUS_ATIM5_ALES0                 *((volatile unsigned int*)(0x427E0E90UL))
+#define bFM3_EXBUS_ATIM5_ALES1                 *((volatile unsigned int*)(0x427E0E94UL))
+#define bFM3_EXBUS_ATIM5_ALES2                 *((volatile unsigned int*)(0x427E0E98UL))
+#define bFM3_EXBUS_ATIM5_ALES3                 *((volatile unsigned int*)(0x427E0E9CUL))
+#define bFM3_EXBUS_ATIM5_ALEW0                 *((volatile unsigned int*)(0x427E0EA0UL))
+#define bFM3_EXBUS_ATIM5_ALEW1                 *((volatile unsigned int*)(0x427E0EA4UL))
+#define bFM3_EXBUS_ATIM5_ALEW2                 *((volatile unsigned int*)(0x427E0EA8UL))
+#define bFM3_EXBUS_ATIM5_ALEW3                 *((volatile unsigned int*)(0x427E0EACUL))
+#define bFM3_EXBUS_ATIM6_ALC0                  *((volatile unsigned int*)(0x427E0F00UL))
+#define bFM3_EXBUS_ATIM6_ALC1                  *((volatile unsigned int*)(0x427E0F04UL))
+#define bFM3_EXBUS_ATIM6_ALC2                  *((volatile unsigned int*)(0x427E0F08UL))
+#define bFM3_EXBUS_ATIM6_ALC3                  *((volatile unsigned int*)(0x427E0F0CUL))
+#define bFM3_EXBUS_ATIM6_ALES0                 *((volatile unsigned int*)(0x427E0F10UL))
+#define bFM3_EXBUS_ATIM6_ALES1                 *((volatile unsigned int*)(0x427E0F14UL))
+#define bFM3_EXBUS_ATIM6_ALES2                 *((volatile unsigned int*)(0x427E0F18UL))
+#define bFM3_EXBUS_ATIM6_ALES3                 *((volatile unsigned int*)(0x427E0F1CUL))
+#define bFM3_EXBUS_ATIM6_ALEW0                 *((volatile unsigned int*)(0x427E0F20UL))
+#define bFM3_EXBUS_ATIM6_ALEW1                 *((volatile unsigned int*)(0x427E0F24UL))
+#define bFM3_EXBUS_ATIM6_ALEW2                 *((volatile unsigned int*)(0x427E0F28UL))
+#define bFM3_EXBUS_ATIM6_ALEW3                 *((volatile unsigned int*)(0x427E0F2CUL))
+#define bFM3_EXBUS_ATIM7_ALC0                  *((volatile unsigned int*)(0x427E0F80UL))
+#define bFM3_EXBUS_ATIM7_ALC1                  *((volatile unsigned int*)(0x427E0F84UL))
+#define bFM3_EXBUS_ATIM7_ALC2                  *((volatile unsigned int*)(0x427E0F88UL))
+#define bFM3_EXBUS_ATIM7_ALC3                  *((volatile unsigned int*)(0x427E0F8CUL))
+#define bFM3_EXBUS_ATIM7_ALES0                 *((volatile unsigned int*)(0x427E0F90UL))
+#define bFM3_EXBUS_ATIM7_ALES1                 *((volatile unsigned int*)(0x427E0F94UL))
+#define bFM3_EXBUS_ATIM7_ALES2                 *((volatile unsigned int*)(0x427E0F98UL))
+#define bFM3_EXBUS_ATIM7_ALES3                 *((volatile unsigned int*)(0x427E0F9CUL))
+#define bFM3_EXBUS_ATIM7_ALEW0                 *((volatile unsigned int*)(0x427E0FA0UL))
+#define bFM3_EXBUS_ATIM7_ALEW1                 *((volatile unsigned int*)(0x427E0FA4UL))
+#define bFM3_EXBUS_ATIM7_ALEW2                 *((volatile unsigned int*)(0x427E0FA8UL))
+#define bFM3_EXBUS_ATIM7_ALEW3                 *((volatile unsigned int*)(0x427E0FACUL))
+#define bFM3_EXBUS_DCLKR_MDIV0                 *((volatile unsigned int*)(0x427E6000UL))
+#define bFM3_EXBUS_DCLKR_MDIV1                 *((volatile unsigned int*)(0x427E6004UL))
+#define bFM3_EXBUS_DCLKR_MDIV2                 *((volatile unsigned int*)(0x427E6008UL))
+#define bFM3_EXBUS_DCLKR_MDIV3                 *((volatile unsigned int*)(0x427E600CUL))
+#define bFM3_EXBUS_DCLKR_MCLKON                *((volatile unsigned int*)(0x427E6010UL))
+
+/* USB channel 0 registers */
+#define bFM3_USB0_HCNT_HOST                    *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT_URST                    *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT_DIRE                    *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT_URIRE                   *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT_RWKIRE                  *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT_RETRY                   *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT_CANCEL                  *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HCNT0_HOST                   *((volatile unsigned int*)(0x42842000UL))
+#define bFM3_USB0_HCNT0_URST                   *((volatile unsigned int*)(0x42842004UL))
+#define bFM3_USB0_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42842008UL))
+#define bFM3_USB0_HCNT0_DIRE                   *((volatile unsigned int*)(0x4284200CUL))
+#define bFM3_USB0_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42842010UL))
+#define bFM3_USB0_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42842014UL))
+#define bFM3_USB0_HCNT0_URIRE                  *((volatile unsigned int*)(0x42842018UL))
+#define bFM3_USB0_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x4284201CUL))
+#define bFM3_USB0_HCNT1_RETRY                  *((volatile unsigned int*)(0x42842020UL))
+#define bFM3_USB0_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42842024UL))
+#define bFM3_USB0_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42842028UL))
+#define bFM3_USB0_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42842080UL))
+#define bFM3_USB0_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42842084UL))
+#define bFM3_USB0_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42842088UL))
+#define bFM3_USB0_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x4284208CUL))
+#define bFM3_USB0_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42842090UL))
+#define bFM3_USB0_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42842094UL))
+#define bFM3_USB0_HIRQ_TCAN                    *((volatile unsigned int*)(0x4284209CUL))
+#define bFM3_USB0_HERR_HS0                     *((volatile unsigned int*)(0x428420A0UL))
+#define bFM3_USB0_HERR_HS1                     *((volatile unsigned int*)(0x428420A4UL))
+#define bFM3_USB0_HERR_STUFF                   *((volatile unsigned int*)(0x428420A8UL))
+#define bFM3_USB0_HERR_TGERR                   *((volatile unsigned int*)(0x428420ACUL))
+#define bFM3_USB0_HERR_CRC                     *((volatile unsigned int*)(0x428420B0UL))
+#define bFM3_USB0_HERR_TOUT                    *((volatile unsigned int*)(0x428420B4UL))
+#define bFM3_USB0_HERR_RERR                    *((volatile unsigned int*)(0x428420B8UL))
+#define bFM3_USB0_HERR_LSTOF                   *((volatile unsigned int*)(0x428420BCUL))
+#define bFM3_USB0_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42842100UL))
+#define bFM3_USB0_HSTATE_TMODE                 *((volatile unsigned int*)(0x42842104UL))
+#define bFM3_USB0_HSTATE_SUSP                  *((volatile unsigned int*)(0x42842108UL))
+#define bFM3_USB0_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x4284210CUL))
+#define bFM3_USB0_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42842110UL))
+#define bFM3_USB0_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42842114UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42842120UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42842124UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42842128UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x4284212CUL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42842130UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42842134UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42842138UL))
+#define bFM3_USB0_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x4284213CUL))
+#define bFM3_USB0_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42842180UL))
+#define bFM3_USB0_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42842184UL))
+#define bFM3_USB0_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42842188UL))
+#define bFM3_USB0_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x4284218CUL))
+#define bFM3_USB0_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42842190UL))
+#define bFM3_USB0_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42842194UL))
+#define bFM3_USB0_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42842198UL))
+#define bFM3_USB0_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x4284219CUL))
+#define bFM3_USB0_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x428421A0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x428421A4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x428421A8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x428421ACUL))
+#define bFM3_USB0_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x428421B0UL))
+#define bFM3_USB0_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x428421B4UL))
+#define bFM3_USB0_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x428421B8UL))
+#define bFM3_USB0_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x428421BCUL))
+#define bFM3_USB0_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42842200UL))
+#define bFM3_USB0_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42842204UL))
+#define bFM3_USB0_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42842208UL))
+#define bFM3_USB0_HADR_ADDRESS0                *((volatile unsigned int*)(0x42842220UL))
+#define bFM3_USB0_HADR_ADDRESS1                *((volatile unsigned int*)(0x42842224UL))
+#define bFM3_USB0_HADR_ADDRESS2                *((volatile unsigned int*)(0x42842228UL))
+#define bFM3_USB0_HADR_ADDRESS3                *((volatile unsigned int*)(0x4284222CUL))
+#define bFM3_USB0_HADR_ADDRESS4                *((volatile unsigned int*)(0x42842230UL))
+#define bFM3_USB0_HADR_ADDRESS5                *((volatile unsigned int*)(0x42842234UL))
+#define bFM3_USB0_HADR_ADDRESS6                *((volatile unsigned int*)(0x42842238UL))
+#define bFM3_USB0_HEOF_EOF0                    *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF_EOF1                    *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF_EOF2                    *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF_EOF3                    *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF_EOF4                    *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF_EOF5                    *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF_EOF6                    *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF_EOF7                    *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF_EOF8                    *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF_EOF9                    *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF_EOF10                   *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF_EOF11                   *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF_EOF12                   *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF_EOF13                   *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HEOF_EOF14                   *((volatile unsigned int*)(0x428422B8UL))
+#define bFM3_USB0_HEOF_EOF15                   *((volatile unsigned int*)(0x428422BCUL))
+#define bFM3_USB0_HEOF0_EOF00                  *((volatile unsigned int*)(0x42842280UL))
+#define bFM3_USB0_HEOF0_EOF01                  *((volatile unsigned int*)(0x42842284UL))
+#define bFM3_USB0_HEOF0_EOF02                  *((volatile unsigned int*)(0x42842288UL))
+#define bFM3_USB0_HEOF0_EOF03                  *((volatile unsigned int*)(0x4284228CUL))
+#define bFM3_USB0_HEOF0_EOF04                  *((volatile unsigned int*)(0x42842290UL))
+#define bFM3_USB0_HEOF0_EOF05                  *((volatile unsigned int*)(0x42842294UL))
+#define bFM3_USB0_HEOF0_EOF06                  *((volatile unsigned int*)(0x42842298UL))
+#define bFM3_USB0_HEOF0_EOF07                  *((volatile unsigned int*)(0x4284229CUL))
+#define bFM3_USB0_HEOF1_EOF10                  *((volatile unsigned int*)(0x428422A0UL))
+#define bFM3_USB0_HEOF1_EOF11                  *((volatile unsigned int*)(0x428422A4UL))
+#define bFM3_USB0_HEOF1_EOF12                  *((volatile unsigned int*)(0x428422A8UL))
+#define bFM3_USB0_HEOF1_EOF13                  *((volatile unsigned int*)(0x428422ACUL))
+#define bFM3_USB0_HEOF1_EOF14                  *((volatile unsigned int*)(0x428422B0UL))
+#define bFM3_USB0_HEOF1_EOF15                  *((volatile unsigned int*)(0x428422B4UL))
+#define bFM3_USB0_HFRAME_FRAME0                *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME_FRAME1                *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME_FRAME2                *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME_FRAME3                *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME_FRAME4                *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME_FRAME5                *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME_FRAME6                *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME_FRAME7                *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME_FRAME8                *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME_FRAME9                *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME_FRAME10               *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42842300UL))
+#define bFM3_USB0_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42842304UL))
+#define bFM3_USB0_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42842308UL))
+#define bFM3_USB0_HFRAME0_FRAME03              *((volatile unsigned int*)(0x4284230CUL))
+#define bFM3_USB0_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42842310UL))
+#define bFM3_USB0_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42842314UL))
+#define bFM3_USB0_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42842318UL))
+#define bFM3_USB0_HFRAME0_FRAME07              *((volatile unsigned int*)(0x4284231CUL))
+#define bFM3_USB0_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42842320UL))
+#define bFM3_USB0_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42842324UL))
+#define bFM3_USB0_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42842328UL))
+#define bFM3_USB0_HFRAME1_FRAME13              *((volatile unsigned int*)(0x4284232CUL))
+#define bFM3_USB0_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42842380UL))
+#define bFM3_USB0_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42842384UL))
+#define bFM3_USB0_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42842388UL))
+#define bFM3_USB0_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x4284238CUL))
+#define bFM3_USB0_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42842390UL))
+#define bFM3_USB0_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42842394UL))
+#define bFM3_USB0_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42842398UL))
+#define bFM3_USB0_HTOKEN_TGGL                  *((volatile unsigned int*)(0x4284239CUL))
+#define bFM3_USB0_UDCC_PWC                     *((volatile unsigned int*)(0x42842400UL))
+#define bFM3_USB0_UDCC_RFBK                    *((volatile unsigned int*)(0x42842404UL))
+#define bFM3_USB0_UDCC_STALCLREN               *((volatile unsigned int*)(0x4284240CUL))
+#define bFM3_USB0_UDCC_USTP                    *((volatile unsigned int*)(0x42842410UL))
+#define bFM3_USB0_UDCC_HCONX                   *((volatile unsigned int*)(0x42842414UL))
+#define bFM3_USB0_UDCC_RESUM                   *((volatile unsigned int*)(0x42842418UL))
+#define bFM3_USB0_UDCC_RST                     *((volatile unsigned int*)(0x4284241CUL))
+#define bFM3_USB0_EP0C_PKS00                   *((volatile unsigned int*)(0x42842480UL))
+#define bFM3_USB0_EP0C_PKS01                   *((volatile unsigned int*)(0x42842484UL))
+#define bFM3_USB0_EP0C_PKS02                   *((volatile unsigned int*)(0x42842488UL))
+#define bFM3_USB0_EP0C_PKS03                   *((volatile unsigned int*)(0x4284248CUL))
+#define bFM3_USB0_EP0C_PKS04                   *((volatile unsigned int*)(0x42842490UL))
+#define bFM3_USB0_EP0C_PKS05                   *((volatile unsigned int*)(0x42842494UL))
+#define bFM3_USB0_EP0C_PKS06                   *((volatile unsigned int*)(0x42842498UL))
+#define bFM3_USB0_EP0C_STAL                    *((volatile unsigned int*)(0x428424A4UL))
+#define bFM3_USB0_EP1C_PKS10                   *((volatile unsigned int*)(0x42842500UL))
+#define bFM3_USB0_EP1C_PKS11                   *((volatile unsigned int*)(0x42842504UL))
+#define bFM3_USB0_EP1C_PKS12                   *((volatile unsigned int*)(0x42842508UL))
+#define bFM3_USB0_EP1C_PKS13                   *((volatile unsigned int*)(0x4284250CUL))
+#define bFM3_USB0_EP1C_PKS14                   *((volatile unsigned int*)(0x42842510UL))
+#define bFM3_USB0_EP1C_PKS15                   *((volatile unsigned int*)(0x42842514UL))
+#define bFM3_USB0_EP1C_PKS16                   *((volatile unsigned int*)(0x42842518UL))
+#define bFM3_USB0_EP1C_PKS17                   *((volatile unsigned int*)(0x4284251CUL))
+#define bFM3_USB0_EP1C_PKS18                   *((volatile unsigned int*)(0x42842520UL))
+#define bFM3_USB0_EP1C_STAL                    *((volatile unsigned int*)(0x42842524UL))
+#define bFM3_USB0_EP1C_NULE                    *((volatile unsigned int*)(0x42842528UL))
+#define bFM3_USB0_EP1C_DMAE                    *((volatile unsigned int*)(0x4284252CUL))
+#define bFM3_USB0_EP1C_DIR                     *((volatile unsigned int*)(0x42842530UL))
+#define bFM3_USB0_EP1C_TYPE0                   *((volatile unsigned int*)(0x42842534UL))
+#define bFM3_USB0_EP1C_TYPE1                   *((volatile unsigned int*)(0x42842538UL))
+#define bFM3_USB0_EP1C_EPEN                    *((volatile unsigned int*)(0x4284253CUL))
+#define bFM3_USB0_EP2C_PKS20                   *((volatile unsigned int*)(0x42842580UL))
+#define bFM3_USB0_EP2C_PKS21                   *((volatile unsigned int*)(0x42842584UL))
+#define bFM3_USB0_EP2C_PKS22                   *((volatile unsigned int*)(0x42842588UL))
+#define bFM3_USB0_EP2C_PKS23                   *((volatile unsigned int*)(0x4284258CUL))
+#define bFM3_USB0_EP2C_PKS24                   *((volatile unsigned int*)(0x42842590UL))
+#define bFM3_USB0_EP2C_PKS25                   *((volatile unsigned int*)(0x42842594UL))
+#define bFM3_USB0_EP2C_PKS26                   *((volatile unsigned int*)(0x42842598UL))
+#define bFM3_USB0_EP2C_STAL                    *((volatile unsigned int*)(0x428425A4UL))
+#define bFM3_USB0_EP2C_NULE                    *((volatile unsigned int*)(0x428425A8UL))
+#define bFM3_USB0_EP2C_DMAE                    *((volatile unsigned int*)(0x428425ACUL))
+#define bFM3_USB0_EP2C_DIR                     *((volatile unsigned int*)(0x428425B0UL))
+#define bFM3_USB0_EP2C_TYPE0                   *((volatile unsigned int*)(0x428425B4UL))
+#define bFM3_USB0_EP2C_TYPE1                   *((volatile unsigned int*)(0x428425B8UL))
+#define bFM3_USB0_EP2C_EPEN                    *((volatile unsigned int*)(0x428425BCUL))
+#define bFM3_USB0_EP3C_PKS30                   *((volatile unsigned int*)(0x42842600UL))
+#define bFM3_USB0_EP3C_PKS31                   *((volatile unsigned int*)(0x42842604UL))
+#define bFM3_USB0_EP3C_PKS32                   *((volatile unsigned int*)(0x42842608UL))
+#define bFM3_USB0_EP3C_PKS33                   *((volatile unsigned int*)(0x4284260CUL))
+#define bFM3_USB0_EP3C_PKS34                   *((volatile unsigned int*)(0x42842610UL))
+#define bFM3_USB0_EP3C_PKS35                   *((volatile unsigned int*)(0x42842614UL))
+#define bFM3_USB0_EP3C_PKS36                   *((volatile unsigned int*)(0x42842618UL))
+#define bFM3_USB0_EP3C_STAL                    *((volatile unsigned int*)(0x42842624UL))
+#define bFM3_USB0_EP3C_NULE                    *((volatile unsigned int*)(0x42842628UL))
+#define bFM3_USB0_EP3C_DMAE                    *((volatile unsigned int*)(0x4284262CUL))
+#define bFM3_USB0_EP3C_DIR                     *((volatile unsigned int*)(0x42842630UL))
+#define bFM3_USB0_EP3C_TYPE0                   *((volatile unsigned int*)(0x42842634UL))
+#define bFM3_USB0_EP3C_TYPE1                   *((volatile unsigned int*)(0x42842638UL))
+#define bFM3_USB0_EP3C_EPEN                    *((volatile unsigned int*)(0x4284263CUL))
+#define bFM3_USB0_EP4C_PKS40                   *((volatile unsigned int*)(0x42842680UL))
+#define bFM3_USB0_EP4C_PKS41                   *((volatile unsigned int*)(0x42842684UL))
+#define bFM3_USB0_EP4C_PKS42                   *((volatile unsigned int*)(0x42842688UL))
+#define bFM3_USB0_EP4C_PKS43                   *((volatile unsigned int*)(0x4284268CUL))
+#define bFM3_USB0_EP4C_PKS44                   *((volatile unsigned int*)(0x42842690UL))
+#define bFM3_USB0_EP4C_PKS45                   *((volatile unsigned int*)(0x42842694UL))
+#define bFM3_USB0_EP4C_PKS46                   *((volatile unsigned int*)(0x42842698UL))
+#define bFM3_USB0_EP4C_STAL                    *((volatile unsigned int*)(0x428426A4UL))
+#define bFM3_USB0_EP4C_NULE                    *((volatile unsigned int*)(0x428426A8UL))
+#define bFM3_USB0_EP4C_DMAE                    *((volatile unsigned int*)(0x428426ACUL))
+#define bFM3_USB0_EP4C_DIR                     *((volatile unsigned int*)(0x428426B0UL))
+#define bFM3_USB0_EP4C_TYPE0                   *((volatile unsigned int*)(0x428426B4UL))
+#define bFM3_USB0_EP4C_TYPE1                   *((volatile unsigned int*)(0x428426B8UL))
+#define bFM3_USB0_EP4C_EPEN                    *((volatile unsigned int*)(0x428426BCUL))
+#define bFM3_USB0_EP5C_PKS50                   *((volatile unsigned int*)(0x42842700UL))
+#define bFM3_USB0_EP5C_PKS51                   *((volatile unsigned int*)(0x42842704UL))
+#define bFM3_USB0_EP5C_PKS52                   *((volatile unsigned int*)(0x42842708UL))
+#define bFM3_USB0_EP5C_PKS53                   *((volatile unsigned int*)(0x4284270CUL))
+#define bFM3_USB0_EP5C_PKS54                   *((volatile unsigned int*)(0x42842710UL))
+#define bFM3_USB0_EP5C_PKS55                   *((volatile unsigned int*)(0x42842714UL))
+#define bFM3_USB0_EP5C_PKS56                   *((volatile unsigned int*)(0x42842718UL))
+#define bFM3_USB0_EP5C_STAL                    *((volatile unsigned int*)(0x42842724UL))
+#define bFM3_USB0_EP5C_NULE                    *((volatile unsigned int*)(0x42842728UL))
+#define bFM3_USB0_EP5C_DMAE                    *((volatile unsigned int*)(0x4284272CUL))
+#define bFM3_USB0_EP5C_DIR                     *((volatile unsigned int*)(0x42842730UL))
+#define bFM3_USB0_EP5C_TYPE0                   *((volatile unsigned int*)(0x42842734UL))
+#define bFM3_USB0_EP5C_TYPE1                   *((volatile unsigned int*)(0x42842738UL))
+#define bFM3_USB0_EP5C_EPEN                    *((volatile unsigned int*)(0x4284273CUL))
+#define bFM3_USB0_TMSP_TMSP0                   *((volatile unsigned int*)(0x42842780UL))
+#define bFM3_USB0_TMSP_TMSP1                   *((volatile unsigned int*)(0x42842784UL))
+#define bFM3_USB0_TMSP_TMSP2                   *((volatile unsigned int*)(0x42842788UL))
+#define bFM3_USB0_TMSP_TMSP3                   *((volatile unsigned int*)(0x4284278CUL))
+#define bFM3_USB0_TMSP_TMSP4                   *((volatile unsigned int*)(0x42842790UL))
+#define bFM3_USB0_TMSP_TMSP5                   *((volatile unsigned int*)(0x42842794UL))
+#define bFM3_USB0_TMSP_TMSP6                   *((volatile unsigned int*)(0x42842798UL))
+#define bFM3_USB0_TMSP_TMSP7                   *((volatile unsigned int*)(0x4284279CUL))
+#define bFM3_USB0_TMSP_TMSP8                   *((volatile unsigned int*)(0x428427A0UL))
+#define bFM3_USB0_TMSP_TMSP9                   *((volatile unsigned int*)(0x428427A4UL))
+#define bFM3_USB0_TMSP_TMSP10                  *((volatile unsigned int*)(0x428427A8UL))
+#define bFM3_USB0_UDCS_CONF                    *((volatile unsigned int*)(0x42842800UL))
+#define bFM3_USB0_UDCS_SETP                    *((volatile unsigned int*)(0x42842804UL))
+#define bFM3_USB0_UDCS_WKUP                    *((volatile unsigned int*)(0x42842808UL))
+#define bFM3_USB0_UDCS_BRST                    *((volatile unsigned int*)(0x4284280CUL))
+#define bFM3_USB0_UDCS_SOF                     *((volatile unsigned int*)(0x42842810UL))
+#define bFM3_USB0_UDCS_SUSP                    *((volatile unsigned int*)(0x42842814UL))
+#define bFM3_USB0_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42842820UL))
+#define bFM3_USB0_UDCIE_CONFN                  *((volatile unsigned int*)(0x42842824UL))
+#define bFM3_USB0_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42842828UL))
+#define bFM3_USB0_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x4284282CUL))
+#define bFM3_USB0_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42842830UL))
+#define bFM3_USB0_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42842834UL))
+#define bFM3_USB0_EP0IS_DRQI                   *((volatile unsigned int*)(0x428428A8UL))
+#define bFM3_USB0_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x428428B8UL))
+#define bFM3_USB0_EP0IS_BFINI                  *((volatile unsigned int*)(0x428428BCUL))
+#define bFM3_USB0_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42842900UL))
+#define bFM3_USB0_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42842904UL))
+#define bFM3_USB0_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42842908UL))
+#define bFM3_USB0_EP0OS_SIZE3                  *((volatile unsigned int*)(0x4284290CUL))
+#define bFM3_USB0_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42842910UL))
+#define bFM3_USB0_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42842914UL))
+#define bFM3_USB0_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42842918UL))
+#define bFM3_USB0_EP0OS_SPK                    *((volatile unsigned int*)(0x42842924UL))
+#define bFM3_USB0_EP0OS_DRQO                   *((volatile unsigned int*)(0x42842928UL))
+#define bFM3_USB0_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42842934UL))
+#define bFM3_USB0_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42842938UL))
+#define bFM3_USB0_EP0OS_BFINI                  *((volatile unsigned int*)(0x4284293CUL))
+#define bFM3_USB0_EP1S_SIZE10                  *((volatile unsigned int*)(0x42842980UL))
+#define bFM3_USB0_EP1S_SIZE11                  *((volatile unsigned int*)(0x42842984UL))
+#define bFM3_USB0_EP1S_SIZE12                  *((volatile unsigned int*)(0x42842988UL))
+#define bFM3_USB0_EP1S_SIZE13                  *((volatile unsigned int*)(0x4284298CUL))
+#define bFM3_USB0_EP1S_SIZE14                  *((volatile unsigned int*)(0x42842990UL))
+#define bFM3_USB0_EP1S_SIZE15                  *((volatile unsigned int*)(0x42842994UL))
+#define bFM3_USB0_EP1S_SIZE16                  *((volatile unsigned int*)(0x42842998UL))
+#define bFM3_USB0_EP1S_SIZE17                  *((volatile unsigned int*)(0x4284299CUL))
+#define bFM3_USB0_EP1S_SIZE18                  *((volatile unsigned int*)(0x428429A0UL))
+#define bFM3_USB0_EP1S_SPK                     *((volatile unsigned int*)(0x428429A4UL))
+#define bFM3_USB0_EP1S_DRQ                     *((volatile unsigned int*)(0x428429A8UL))
+#define bFM3_USB0_EP1S_BUSY                    *((volatile unsigned int*)(0x428429ACUL))
+#define bFM3_USB0_EP1S_SPKIE                   *((volatile unsigned int*)(0x428429B4UL))
+#define bFM3_USB0_EP1S_DRQIE                   *((volatile unsigned int*)(0x428429B8UL))
+#define bFM3_USB0_EP1S_BFINI                   *((volatile unsigned int*)(0x428429BCUL))
+#define bFM3_USB0_EP2S_SIZE20                  *((volatile unsigned int*)(0x42842A00UL))
+#define bFM3_USB0_EP2S_SIZE21                  *((volatile unsigned int*)(0x42842A04UL))
+#define bFM3_USB0_EP2S_SIZE22                  *((volatile unsigned int*)(0x42842A08UL))
+#define bFM3_USB0_EP2S_SIZE23                  *((volatile unsigned int*)(0x42842A0CUL))
+#define bFM3_USB0_EP2S_SIZE24                  *((volatile unsigned int*)(0x42842A10UL))
+#define bFM3_USB0_EP2S_SIZE25                  *((volatile unsigned int*)(0x42842A14UL))
+#define bFM3_USB0_EP2S_SIZE26                  *((volatile unsigned int*)(0x42842A18UL))
+#define bFM3_USB0_EP2S_SPK                     *((volatile unsigned int*)(0x42842A24UL))
+#define bFM3_USB0_EP2S_DRQ                     *((volatile unsigned int*)(0x42842A28UL))
+#define bFM3_USB0_EP2S_BUSY                    *((volatile unsigned int*)(0x42842A2CUL))
+#define bFM3_USB0_EP2S_SPKIE                   *((volatile unsigned int*)(0x42842A34UL))
+#define bFM3_USB0_EP2S_DRQIE                   *((volatile unsigned int*)(0x42842A38UL))
+#define bFM3_USB0_EP2S_BFINI                   *((volatile unsigned int*)(0x42842A3CUL))
+#define bFM3_USB0_EP3S_SIZE30                  *((volatile unsigned int*)(0x42842A80UL))
+#define bFM3_USB0_EP3S_SIZE31                  *((volatile unsigned int*)(0x42842A84UL))
+#define bFM3_USB0_EP3S_SIZE32                  *((volatile unsigned int*)(0x42842A88UL))
+#define bFM3_USB0_EP3S_SIZE33                  *((volatile unsigned int*)(0x42842A8CUL))
+#define bFM3_USB0_EP3S_SIZE34                  *((volatile unsigned int*)(0x42842A90UL))
+#define bFM3_USB0_EP3S_SIZE35                  *((volatile unsigned int*)(0x42842A94UL))
+#define bFM3_USB0_EP3S_SIZE36                  *((volatile unsigned int*)(0x42842A98UL))
+#define bFM3_USB0_EP3S_SPK                     *((volatile unsigned int*)(0x42842AA4UL))
+#define bFM3_USB0_EP3S_DRQ                     *((volatile unsigned int*)(0x42842AA8UL))
+#define bFM3_USB0_EP3S_BUSY                    *((volatile unsigned int*)(0x42842AACUL))
+#define bFM3_USB0_EP3S_SPKIE                   *((volatile unsigned int*)(0x42842AB4UL))
+#define bFM3_USB0_EP3S_DRQIE                   *((volatile unsigned int*)(0x42842AB8UL))
+#define bFM3_USB0_EP3S_BFINI                   *((volatile unsigned int*)(0x42842ABCUL))
+#define bFM3_USB0_EP4S_SIZE40                  *((volatile unsigned int*)(0x42842B00UL))
+#define bFM3_USB0_EP4S_SIZE41                  *((volatile unsigned int*)(0x42842B04UL))
+#define bFM3_USB0_EP4S_SIZE42                  *((volatile unsigned int*)(0x42842B08UL))
+#define bFM3_USB0_EP4S_SIZE43                  *((volatile unsigned int*)(0x42842B0CUL))
+#define bFM3_USB0_EP4S_SIZE44                  *((volatile unsigned int*)(0x42842B10UL))
+#define bFM3_USB0_EP4S_SIZE45                  *((volatile unsigned int*)(0x42842B14UL))
+#define bFM3_USB0_EP4S_SIZE46                  *((volatile unsigned int*)(0x42842B18UL))
+#define bFM3_USB0_EP4S_SPK                     *((volatile unsigned int*)(0x42842B24UL))
+#define bFM3_USB0_EP4S_DRQ                     *((volatile unsigned int*)(0x42842B28UL))
+#define bFM3_USB0_EP4S_BUSY                    *((volatile unsigned int*)(0x42842B2CUL))
+#define bFM3_USB0_EP4S_SPKIE                   *((volatile unsigned int*)(0x42842B34UL))
+#define bFM3_USB0_EP4S_DRQIE                   *((volatile unsigned int*)(0x42842B38UL))
+#define bFM3_USB0_EP4S_BFINI                   *((volatile unsigned int*)(0x42842B3CUL))
+#define bFM3_USB0_EP5S_SIZE50                  *((volatile unsigned int*)(0x42842B80UL))
+#define bFM3_USB0_EP5S_SIZE51                  *((volatile unsigned int*)(0x42842B84UL))
+#define bFM3_USB0_EP5S_SIZE52                  *((volatile unsigned int*)(0x42842B88UL))
+#define bFM3_USB0_EP5S_SIZE53                  *((volatile unsigned int*)(0x42842B8CUL))
+#define bFM3_USB0_EP5S_SIZE54                  *((volatile unsigned int*)(0x42842B90UL))
+#define bFM3_USB0_EP5S_SIZE55                  *((volatile unsigned int*)(0x42842B94UL))
+#define bFM3_USB0_EP5S_SIZE56                  *((volatile unsigned int*)(0x42842B98UL))
+#define bFM3_USB0_EP5S_SPK                     *((volatile unsigned int*)(0x42842BA4UL))
+#define bFM3_USB0_EP5S_DRQ                     *((volatile unsigned int*)(0x42842BA8UL))
+#define bFM3_USB0_EP5S_BUSY                    *((volatile unsigned int*)(0x42842BACUL))
+#define bFM3_USB0_EP5S_SPKIE                   *((volatile unsigned int*)(0x42842BB4UL))
+#define bFM3_USB0_EP5S_DRQIE                   *((volatile unsigned int*)(0x42842BB8UL))
+#define bFM3_USB0_EP5S_BFINI                   *((volatile unsigned int*)(0x42842BBCUL))
+
+/* USB channel 1 registers */
+#define bFM3_USB1_HCNT_HOST                    *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT_URST                    *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT_SOFIRE                  *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT_DIRE                    *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT_CNNIRE                  *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT_CMPIRE                  *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT_URIRE                   *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT_RWKIRE                  *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT_RETRY                   *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT_CANCEL                  *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT_SOFSTEP                 *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HCNT0_HOST                   *((volatile unsigned int*)(0x42A42000UL))
+#define bFM3_USB1_HCNT0_URST                   *((volatile unsigned int*)(0x42A42004UL))
+#define bFM3_USB1_HCNT0_SOFIRE                 *((volatile unsigned int*)(0x42A42008UL))
+#define bFM3_USB1_HCNT0_DIRE                   *((volatile unsigned int*)(0x42A4200CUL))
+#define bFM3_USB1_HCNT0_CNNIRE                 *((volatile unsigned int*)(0x42A42010UL))
+#define bFM3_USB1_HCNT0_CMPIRE                 *((volatile unsigned int*)(0x42A42014UL))
+#define bFM3_USB1_HCNT0_URIRE                  *((volatile unsigned int*)(0x42A42018UL))
+#define bFM3_USB1_HCNT0_RWKIRE                 *((volatile unsigned int*)(0x42A4201CUL))
+#define bFM3_USB1_HCNT1_RETRY                  *((volatile unsigned int*)(0x42A42020UL))
+#define bFM3_USB1_HCNT1_CANCEL                 *((volatile unsigned int*)(0x42A42024UL))
+#define bFM3_USB1_HCNT1_SOFSTEP                *((volatile unsigned int*)(0x42A42028UL))
+#define bFM3_USB1_HIRQ_SOFIRQ                  *((volatile unsigned int*)(0x42A42080UL))
+#define bFM3_USB1_HIRQ_DIRQ                    *((volatile unsigned int*)(0x42A42084UL))
+#define bFM3_USB1_HIRQ_CNNIRQ                  *((volatile unsigned int*)(0x42A42088UL))
+#define bFM3_USB1_HIRQ_CMPIRQ                  *((volatile unsigned int*)(0x42A4208CUL))
+#define bFM3_USB1_HIRQ_URIRQ                   *((volatile unsigned int*)(0x42A42090UL))
+#define bFM3_USB1_HIRQ_RWKIRQ                  *((volatile unsigned int*)(0x42A42094UL))
+#define bFM3_USB1_HIRQ_TCAN                    *((volatile unsigned int*)(0x42A4209CUL))
+#define bFM3_USB1_HERR_HS0                     *((volatile unsigned int*)(0x42A420A0UL))
+#define bFM3_USB1_HERR_HS1                     *((volatile unsigned int*)(0x42A420A4UL))
+#define bFM3_USB1_HERR_STUFF                   *((volatile unsigned int*)(0x42A420A8UL))
+#define bFM3_USB1_HERR_TGERR                   *((volatile unsigned int*)(0x42A420ACUL))
+#define bFM3_USB1_HERR_CRC                     *((volatile unsigned int*)(0x42A420B0UL))
+#define bFM3_USB1_HERR_TOUT                    *((volatile unsigned int*)(0x42A420B4UL))
+#define bFM3_USB1_HERR_RERR                    *((volatile unsigned int*)(0x42A420B8UL))
+#define bFM3_USB1_HERR_LSTOF                   *((volatile unsigned int*)(0x42A420BCUL))
+#define bFM3_USB1_HSTATE_CSTAT                 *((volatile unsigned int*)(0x42A42100UL))
+#define bFM3_USB1_HSTATE_TMODE                 *((volatile unsigned int*)(0x42A42104UL))
+#define bFM3_USB1_HSTATE_SUSP                  *((volatile unsigned int*)(0x42A42108UL))
+#define bFM3_USB1_HSTATE_SOFBUSY               *((volatile unsigned int*)(0x42A4210CUL))
+#define bFM3_USB1_HSTATE_CLKSEL                *((volatile unsigned int*)(0x42A42110UL))
+#define bFM3_USB1_HSTATE_ALIVE                 *((volatile unsigned int*)(0x42A42114UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP0            *((volatile unsigned int*)(0x42A42120UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP1            *((volatile unsigned int*)(0x42A42124UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP2            *((volatile unsigned int*)(0x42A42128UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP3            *((volatile unsigned int*)(0x42A4212CUL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP4            *((volatile unsigned int*)(0x42A42130UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP5            *((volatile unsigned int*)(0x42A42134UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP6            *((volatile unsigned int*)(0x42A42138UL))
+#define bFM3_USB1_HFCOMP_FRAMECOMP7            *((volatile unsigned int*)(0x42A4213CUL))
+#define bFM3_USB1_HRTIMER_RTIMER0              *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER_RTIMER1              *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER_RTIMER2              *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER_RTIMER3              *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER_RTIMER4              *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER_RTIMER5              *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER_RTIMER6              *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER_RTIMER7              *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER_RTIMER8              *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER_RTIMER9              *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER_RTIMER10             *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER_RTIMER11             *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER_RTIMER12             *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER_RTIMER13             *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER_RTIMER14             *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER_RTIMER15             *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER0_RTIMER00            *((volatile unsigned int*)(0x42A42180UL))
+#define bFM3_USB1_HRTIMER0_RTIMER01            *((volatile unsigned int*)(0x42A42184UL))
+#define bFM3_USB1_HRTIMER0_RTIMER02            *((volatile unsigned int*)(0x42A42188UL))
+#define bFM3_USB1_HRTIMER0_RTIMER03            *((volatile unsigned int*)(0x42A4218CUL))
+#define bFM3_USB1_HRTIMER0_RTIMER04            *((volatile unsigned int*)(0x42A42190UL))
+#define bFM3_USB1_HRTIMER0_RTIMER05            *((volatile unsigned int*)(0x42A42194UL))
+#define bFM3_USB1_HRTIMER0_RTIMER06            *((volatile unsigned int*)(0x42A42198UL))
+#define bFM3_USB1_HRTIMER0_RTIMER07            *((volatile unsigned int*)(0x42A4219CUL))
+#define bFM3_USB1_HRTIMER1_RTIMER10            *((volatile unsigned int*)(0x42A421A0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER11            *((volatile unsigned int*)(0x42A421A4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER12            *((volatile unsigned int*)(0x42A421A8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER13            *((volatile unsigned int*)(0x42A421ACUL))
+#define bFM3_USB1_HRTIMER1_RTIMER14            *((volatile unsigned int*)(0x42A421B0UL))
+#define bFM3_USB1_HRTIMER1_RTIMER15            *((volatile unsigned int*)(0x42A421B4UL))
+#define bFM3_USB1_HRTIMER1_RTIMER16            *((volatile unsigned int*)(0x42A421B8UL))
+#define bFM3_USB1_HRTIMER1_RTIMER17            *((volatile unsigned int*)(0x42A421BCUL))
+#define bFM3_USB1_HRTIMER2_RTIMER20            *((volatile unsigned int*)(0x42A42200UL))
+#define bFM3_USB1_HRTIMER2_RTIMER21            *((volatile unsigned int*)(0x42A42204UL))
+#define bFM3_USB1_HRTIMER2_RTIMER22            *((volatile unsigned int*)(0x42A42208UL))
+#define bFM3_USB1_HADR_ADDRESS0                *((volatile unsigned int*)(0x42A42220UL))
+#define bFM3_USB1_HADR_ADDRESS1                *((volatile unsigned int*)(0x42A42224UL))
+#define bFM3_USB1_HADR_ADDRESS2                *((volatile unsigned int*)(0x42A42228UL))
+#define bFM3_USB1_HADR_ADDRESS3                *((volatile unsigned int*)(0x42A4222CUL))
+#define bFM3_USB1_HADR_ADDRESS4                *((volatile unsigned int*)(0x42A42230UL))
+#define bFM3_USB1_HADR_ADDRESS5                *((volatile unsigned int*)(0x42A42234UL))
+#define bFM3_USB1_HADR_ADDRESS6                *((volatile unsigned int*)(0x42A42238UL))
+#define bFM3_USB1_HEOF_EOF0                    *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF_EOF1                    *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF_EOF2                    *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF_EOF3                    *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF_EOF4                    *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF_EOF5                    *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF_EOF6                    *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF_EOF7                    *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF_EOF8                    *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF_EOF9                    *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF_EOF10                   *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF_EOF11                   *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF_EOF12                   *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF_EOF13                   *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HEOF_EOF14                   *((volatile unsigned int*)(0x42A422B8UL))
+#define bFM3_USB1_HEOF_EOF15                   *((volatile unsigned int*)(0x42A422BCUL))
+#define bFM3_USB1_HEOF0_EOF00                  *((volatile unsigned int*)(0x42A42280UL))
+#define bFM3_USB1_HEOF0_EOF01                  *((volatile unsigned int*)(0x42A42284UL))
+#define bFM3_USB1_HEOF0_EOF02                  *((volatile unsigned int*)(0x42A42288UL))
+#define bFM3_USB1_HEOF0_EOF03                  *((volatile unsigned int*)(0x42A4228CUL))
+#define bFM3_USB1_HEOF0_EOF04                  *((volatile unsigned int*)(0x42A42290UL))
+#define bFM3_USB1_HEOF0_EOF05                  *((volatile unsigned int*)(0x42A42294UL))
+#define bFM3_USB1_HEOF0_EOF06                  *((volatile unsigned int*)(0x42A42298UL))
+#define bFM3_USB1_HEOF0_EOF07                  *((volatile unsigned int*)(0x42A4229CUL))
+#define bFM3_USB1_HEOF1_EOF10                  *((volatile unsigned int*)(0x42A422A0UL))
+#define bFM3_USB1_HEOF1_EOF11                  *((volatile unsigned int*)(0x42A422A4UL))
+#define bFM3_USB1_HEOF1_EOF12                  *((volatile unsigned int*)(0x42A422A8UL))
+#define bFM3_USB1_HEOF1_EOF13                  *((volatile unsigned int*)(0x42A422ACUL))
+#define bFM3_USB1_HEOF1_EOF14                  *((volatile unsigned int*)(0x42A422B0UL))
+#define bFM3_USB1_HEOF1_EOF15                  *((volatile unsigned int*)(0x42A422B4UL))
+#define bFM3_USB1_HFRAME_FRAME0                *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME_FRAME1                *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME_FRAME2                *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME_FRAME3                *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME_FRAME4                *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME_FRAME5                *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME_FRAME6                *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME_FRAME7                *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME_FRAME8                *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME_FRAME9                *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME_FRAME10               *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME0_FRAME00              *((volatile unsigned int*)(0x42A42300UL))
+#define bFM3_USB1_HFRAME0_FRAME01              *((volatile unsigned int*)(0x42A42304UL))
+#define bFM3_USB1_HFRAME0_FRAME02              *((volatile unsigned int*)(0x42A42308UL))
+#define bFM3_USB1_HFRAME0_FRAME03              *((volatile unsigned int*)(0x42A4230CUL))
+#define bFM3_USB1_HFRAME0_FRAME04              *((volatile unsigned int*)(0x42A42310UL))
+#define bFM3_USB1_HFRAME0_FRAME05              *((volatile unsigned int*)(0x42A42314UL))
+#define bFM3_USB1_HFRAME0_FRAME06              *((volatile unsigned int*)(0x42A42318UL))
+#define bFM3_USB1_HFRAME0_FRAME07              *((volatile unsigned int*)(0x42A4231CUL))
+#define bFM3_USB1_HFRAME1_FRAME10              *((volatile unsigned int*)(0x42A42320UL))
+#define bFM3_USB1_HFRAME1_FRAME11              *((volatile unsigned int*)(0x42A42324UL))
+#define bFM3_USB1_HFRAME1_FRAME12              *((volatile unsigned int*)(0x42A42328UL))
+#define bFM3_USB1_HFRAME1_FRAME13              *((volatile unsigned int*)(0x42A4232CUL))
+#define bFM3_USB1_HTOKEN_ENDPT0                *((volatile unsigned int*)(0x42A42380UL))
+#define bFM3_USB1_HTOKEN_ENDPT1                *((volatile unsigned int*)(0x42A42384UL))
+#define bFM3_USB1_HTOKEN_ENDPT2                *((volatile unsigned int*)(0x42A42388UL))
+#define bFM3_USB1_HTOKEN_ENDPT3                *((volatile unsigned int*)(0x42A4238CUL))
+#define bFM3_USB1_HTOKEN_TKNEN0                *((volatile unsigned int*)(0x42A42390UL))
+#define bFM3_USB1_HTOKEN_TKNEN1                *((volatile unsigned int*)(0x42A42394UL))
+#define bFM3_USB1_HTOKEN_TKNEN2                *((volatile unsigned int*)(0x42A42398UL))
+#define bFM3_USB1_HTOKEN_TGGL                  *((volatile unsigned int*)(0x42A4239CUL))
+#define bFM3_USB1_UDCC_PWC                     *((volatile unsigned int*)(0x42A42400UL))
+#define bFM3_USB1_UDCC_RFBK                    *((volatile unsigned int*)(0x42A42404UL))
+#define bFM3_USB1_UDCC_STALCLREN               *((volatile unsigned int*)(0x42A4240CUL))
+#define bFM3_USB1_UDCC_USTP                    *((volatile unsigned int*)(0x42A42410UL))
+#define bFM3_USB1_UDCC_HCONX                   *((volatile unsigned int*)(0x42A42414UL))
+#define bFM3_USB1_UDCC_RESUM                   *((volatile unsigned int*)(0x42A42418UL))
+#define bFM3_USB1_UDCC_RST                     *((volatile unsigned int*)(0x42A4241CUL))
+#define bFM3_USB1_EP0C_PKS00                   *((volatile unsigned int*)(0x42A42480UL))
+#define bFM3_USB1_EP0C_PKS01                   *((volatile unsigned int*)(0x42A42484UL))
+#define bFM3_USB1_EP0C_PKS02                   *((volatile unsigned int*)(0x42A42488UL))
+#define bFM3_USB1_EP0C_PKS03                   *((volatile unsigned int*)(0x42A4248CUL))
+#define bFM3_USB1_EP0C_PKS04                   *((volatile unsigned int*)(0x42A42490UL))
+#define bFM3_USB1_EP0C_PKS05                   *((volatile unsigned int*)(0x42A42494UL))
+#define bFM3_USB1_EP0C_PKS06                   *((volatile unsigned int*)(0x42A42498UL))
+#define bFM3_USB1_EP0C_STAL                    *((volatile unsigned int*)(0x42A424A4UL))
+#define bFM3_USB1_EP1C_PKS10                   *((volatile unsigned int*)(0x42A42500UL))
+#define bFM3_USB1_EP1C_PKS11                   *((volatile unsigned int*)(0x42A42504UL))
+#define bFM3_USB1_EP1C_PKS12                   *((volatile unsigned int*)(0x42A42508UL))
+#define bFM3_USB1_EP1C_PKS13                   *((volatile unsigned int*)(0x42A4250CUL))
+#define bFM3_USB1_EP1C_PKS14                   *((volatile unsigned int*)(0x42A42510UL))
+#define bFM3_USB1_EP1C_PKS15                   *((volatile unsigned int*)(0x42A42514UL))
+#define bFM3_USB1_EP1C_PKS16                   *((volatile unsigned int*)(0x42A42518UL))
+#define bFM3_USB1_EP1C_PKS17                   *((volatile unsigned int*)(0x42A4251CUL))
+#define bFM3_USB1_EP1C_PKS18                   *((volatile unsigned int*)(0x42A42520UL))
+#define bFM3_USB1_EP1C_STAL                    *((volatile unsigned int*)(0x42A42524UL))
+#define bFM3_USB1_EP1C_NULE                    *((volatile unsigned int*)(0x42A42528UL))
+#define bFM3_USB1_EP1C_DMAE                    *((volatile unsigned int*)(0x42A4252CUL))
+#define bFM3_USB1_EP1C_DIR                     *((volatile unsigned int*)(0x42A42530UL))
+#define bFM3_USB1_EP1C_TYPE0                   *((volatile unsigned int*)(0x42A42534UL))
+#define bFM3_USB1_EP1C_TYPE1                   *((volatile unsigned int*)(0x42A42538UL))
+#define bFM3_USB1_EP1C_EPEN                    *((volatile unsigned int*)(0x42A4253CUL))
+#define bFM3_USB1_EP2C_PKS20                   *((volatile unsigned int*)(0x42A42580UL))
+#define bFM3_USB1_EP2C_PKS21                   *((volatile unsigned int*)(0x42A42584UL))
+#define bFM3_USB1_EP2C_PKS22                   *((volatile unsigned int*)(0x42A42588UL))
+#define bFM3_USB1_EP2C_PKS23                   *((volatile unsigned int*)(0x42A4258CUL))
+#define bFM3_USB1_EP2C_PKS24                   *((volatile unsigned int*)(0x42A42590UL))
+#define bFM3_USB1_EP2C_PKS25                   *((volatile unsigned int*)(0x42A42594UL))
+#define bFM3_USB1_EP2C_PKS26                   *((volatile unsigned int*)(0x42A42598UL))
+#define bFM3_USB1_EP2C_STAL                    *((volatile unsigned int*)(0x42A425A4UL))
+#define bFM3_USB1_EP2C_NULE                    *((volatile unsigned int*)(0x42A425A8UL))
+#define bFM3_USB1_EP2C_DMAE                    *((volatile unsigned int*)(0x42A425ACUL))
+#define bFM3_USB1_EP2C_DIR                     *((volatile unsigned int*)(0x42A425B0UL))
+#define bFM3_USB1_EP2C_TYPE0                   *((volatile unsigned int*)(0x42A425B4UL))
+#define bFM3_USB1_EP2C_TYPE1                   *((volatile unsigned int*)(0x42A425B8UL))
+#define bFM3_USB1_EP2C_EPEN                    *((volatile unsigned int*)(0x42A425BCUL))
+#define bFM3_USB1_EP3C_PKS30                   *((volatile unsigned int*)(0x42A42600UL))
+#define bFM3_USB1_EP3C_PKS31                   *((volatile unsigned int*)(0x42A42604UL))
+#define bFM3_USB1_EP3C_PKS32                   *((volatile unsigned int*)(0x42A42608UL))
+#define bFM3_USB1_EP3C_PKS33                   *((volatile unsigned int*)(0x42A4260CUL))
+#define bFM3_USB1_EP3C_PKS34                   *((volatile unsigned int*)(0x42A42610UL))
+#define bFM3_USB1_EP3C_PKS35                   *((volatile unsigned int*)(0x42A42614UL))
+#define bFM3_USB1_EP3C_PKS36                   *((volatile unsigned int*)(0x42A42618UL))
+#define bFM3_USB1_EP3C_STAL                    *((volatile unsigned int*)(0x42A42624UL))
+#define bFM3_USB1_EP3C_NULE                    *((volatile unsigned int*)(0x42A42628UL))
+#define bFM3_USB1_EP3C_DMAE                    *((volatile unsigned int*)(0x42A4262CUL))
+#define bFM3_USB1_EP3C_DIR                     *((volatile unsigned int*)(0x42A42630UL))
+#define bFM3_USB1_EP3C_TYPE0                   *((volatile unsigned int*)(0x42A42634UL))
+#define bFM3_USB1_EP3C_TYPE1                   *((volatile unsigned int*)(0x42A42638UL))
+#define bFM3_USB1_EP3C_EPEN                    *((volatile unsigned int*)(0x42A4263CUL))
+#define bFM3_USB1_EP4C_PKS40                   *((volatile unsigned int*)(0x42A42680UL))
+#define bFM3_USB1_EP4C_PKS41                   *((volatile unsigned int*)(0x42A42684UL))
+#define bFM3_USB1_EP4C_PKS42                   *((volatile unsigned int*)(0x42A42688UL))
+#define bFM3_USB1_EP4C_PKS43                   *((volatile unsigned int*)(0x42A4268CUL))
+#define bFM3_USB1_EP4C_PKS44                   *((volatile unsigned int*)(0x42A42690UL))
+#define bFM3_USB1_EP4C_PKS45                   *((volatile unsigned int*)(0x42A42694UL))
+#define bFM3_USB1_EP4C_PKS46                   *((volatile unsigned int*)(0x42A42698UL))
+#define bFM3_USB1_EP4C_STAL                    *((volatile unsigned int*)(0x42A426A4UL))
+#define bFM3_USB1_EP4C_NULE                    *((volatile unsigned int*)(0x42A426A8UL))
+#define bFM3_USB1_EP4C_DMAE                    *((volatile unsigned int*)(0x42A426ACUL))
+#define bFM3_USB1_EP4C_DIR                     *((volatile unsigned int*)(0x42A426B0UL))
+#define bFM3_USB1_EP4C_TYPE0                   *((volatile unsigned int*)(0x42A426B4UL))
+#define bFM3_USB1_EP4C_TYPE1                   *((volatile unsigned int*)(0x42A426B8UL))
+#define bFM3_USB1_EP4C_EPEN                    *((volatile unsigned int*)(0x42A426BCUL))
+#define bFM3_USB1_EP5C_PKS50                   *((volatile unsigned int*)(0x42A42700UL))
+#define bFM3_USB1_EP5C_PKS51                   *((volatile unsigned int*)(0x42A42704UL))
+#define bFM3_USB1_EP5C_PKS52                   *((volatile unsigned int*)(0x42A42708UL))
+#define bFM3_USB1_EP5C_PKS53                   *((volatile unsigned int*)(0x42A4270CUL))
+#define bFM3_USB1_EP5C_PKS54                   *((volatile unsigned int*)(0x42A42710UL))
+#define bFM3_USB1_EP5C_PKS55                   *((volatile unsigned int*)(0x42A42714UL))
+#define bFM3_USB1_EP5C_PKS56                   *((volatile unsigned int*)(0x42A42718UL))
+#define bFM3_USB1_EP5C_STAL                    *((volatile unsigned int*)(0x42A42724UL))
+#define bFM3_USB1_EP5C_NULE                    *((volatile unsigned int*)(0x42A42728UL))
+#define bFM3_USB1_EP5C_DMAE                    *((volatile unsigned int*)(0x42A4272CUL))
+#define bFM3_USB1_EP5C_DIR                     *((volatile unsigned int*)(0x42A42730UL))
+#define bFM3_USB1_EP5C_TYPE0                   *((volatile unsigned int*)(0x42A42734UL))
+#define bFM3_USB1_EP5C_TYPE1                   *((volatile unsigned int*)(0x42A42738UL))
+#define bFM3_USB1_EP5C_EPEN                    *((volatile unsigned int*)(0x42A4273CUL))
+#define bFM3_USB1_TMSP_TMSP0                   *((volatile unsigned int*)(0x42A42780UL))
+#define bFM3_USB1_TMSP_TMSP1                   *((volatile unsigned int*)(0x42A42784UL))
+#define bFM3_USB1_TMSP_TMSP2                   *((volatile unsigned int*)(0x42A42788UL))
+#define bFM3_USB1_TMSP_TMSP3                   *((volatile unsigned int*)(0x42A4278CUL))
+#define bFM3_USB1_TMSP_TMSP4                   *((volatile unsigned int*)(0x42A42790UL))
+#define bFM3_USB1_TMSP_TMSP5                   *((volatile unsigned int*)(0x42A42794UL))
+#define bFM3_USB1_TMSP_TMSP6                   *((volatile unsigned int*)(0x42A42798UL))
+#define bFM3_USB1_TMSP_TMSP7                   *((volatile unsigned int*)(0x42A4279CUL))
+#define bFM3_USB1_TMSP_TMSP8                   *((volatile unsigned int*)(0x42A427A0UL))
+#define bFM3_USB1_TMSP_TMSP9                   *((volatile unsigned int*)(0x42A427A4UL))
+#define bFM3_USB1_TMSP_TMSP10                  *((volatile unsigned int*)(0x42A427A8UL))
+#define bFM3_USB1_UDCS_CONF                    *((volatile unsigned int*)(0x42A42800UL))
+#define bFM3_USB1_UDCS_SETP                    *((volatile unsigned int*)(0x42A42804UL))
+#define bFM3_USB1_UDCS_WKUP                    *((volatile unsigned int*)(0x42A42808UL))
+#define bFM3_USB1_UDCS_BRST                    *((volatile unsigned int*)(0x42A4280CUL))
+#define bFM3_USB1_UDCS_SOF                     *((volatile unsigned int*)(0x42A42810UL))
+#define bFM3_USB1_UDCS_SUSP                    *((volatile unsigned int*)(0x42A42814UL))
+#define bFM3_USB1_UDCIE_CONFIE                 *((volatile unsigned int*)(0x42A42820UL))
+#define bFM3_USB1_UDCIE_CONFN                  *((volatile unsigned int*)(0x42A42824UL))
+#define bFM3_USB1_UDCIE_WKUPIE                 *((volatile unsigned int*)(0x42A42828UL))
+#define bFM3_USB1_UDCIE_BRSTIE                 *((volatile unsigned int*)(0x42A4282CUL))
+#define bFM3_USB1_UDCIE_SOFIE                  *((volatile unsigned int*)(0x42A42830UL))
+#define bFM3_USB1_UDCIE_SUSPIE                 *((volatile unsigned int*)(0x42A42834UL))
+#define bFM3_USB1_EP0IS_DRQI                   *((volatile unsigned int*)(0x42A428A8UL))
+#define bFM3_USB1_EP0IS_DRQIIE                 *((volatile unsigned int*)(0x42A428B8UL))
+#define bFM3_USB1_EP0IS_BFINI                  *((volatile unsigned int*)(0x42A428BCUL))
+#define bFM3_USB1_EP0OS_SIZE0                  *((volatile unsigned int*)(0x42A42900UL))
+#define bFM3_USB1_EP0OS_SIZE1                  *((volatile unsigned int*)(0x42A42904UL))
+#define bFM3_USB1_EP0OS_SIZE2                  *((volatile unsigned int*)(0x42A42908UL))
+#define bFM3_USB1_EP0OS_SIZE3                  *((volatile unsigned int*)(0x42A4290CUL))
+#define bFM3_USB1_EP0OS_SIZE4                  *((volatile unsigned int*)(0x42A42910UL))
+#define bFM3_USB1_EP0OS_SIZE5                  *((volatile unsigned int*)(0x42A42914UL))
+#define bFM3_USB1_EP0OS_SIZE6                  *((volatile unsigned int*)(0x42A42918UL))
+#define bFM3_USB1_EP0OS_SPK                    *((volatile unsigned int*)(0x42A42924UL))
+#define bFM3_USB1_EP0OS_DRQO                   *((volatile unsigned int*)(0x42A42928UL))
+#define bFM3_USB1_EP0OS_SPKIE                  *((volatile unsigned int*)(0x42A42934UL))
+#define bFM3_USB1_EP0OS_DRQOIE                 *((volatile unsigned int*)(0x42A42938UL))
+#define bFM3_USB1_EP0OS_BFINI                  *((volatile unsigned int*)(0x42A4293CUL))
+#define bFM3_USB1_EP1S_SIZE10                  *((volatile unsigned int*)(0x42A42980UL))
+#define bFM3_USB1_EP1S_SIZE11                  *((volatile unsigned int*)(0x42A42984UL))
+#define bFM3_USB1_EP1S_SIZE12                  *((volatile unsigned int*)(0x42A42988UL))
+#define bFM3_USB1_EP1S_SIZE13                  *((volatile unsigned int*)(0x42A4298CUL))
+#define bFM3_USB1_EP1S_SIZE14                  *((volatile unsigned int*)(0x42A42990UL))
+#define bFM3_USB1_EP1S_SIZE15                  *((volatile unsigned int*)(0x42A42994UL))
+#define bFM3_USB1_EP1S_SIZE16                  *((volatile unsigned int*)(0x42A42998UL))
+#define bFM3_USB1_EP1S_SIZE17                  *((volatile unsigned int*)(0x42A4299CUL))
+#define bFM3_USB1_EP1S_SIZE18                  *((volatile unsigned int*)(0x42A429A0UL))
+#define bFM3_USB1_EP1S_SPK                     *((volatile unsigned int*)(0x42A429A4UL))
+#define bFM3_USB1_EP1S_DRQ                     *((volatile unsigned int*)(0x42A429A8UL))
+#define bFM3_USB1_EP1S_BUSY                    *((volatile unsigned int*)(0x42A429ACUL))
+#define bFM3_USB1_EP1S_SPKIE                   *((volatile unsigned int*)(0x42A429B4UL))
+#define bFM3_USB1_EP1S_DRQIE                   *((volatile unsigned int*)(0x42A429B8UL))
+#define bFM3_USB1_EP1S_BFINI                   *((volatile unsigned int*)(0x42A429BCUL))
+#define bFM3_USB1_EP2S_SIZE20                  *((volatile unsigned int*)(0x42A42A00UL))
+#define bFM3_USB1_EP2S_SIZE21                  *((volatile unsigned int*)(0x42A42A04UL))
+#define bFM3_USB1_EP2S_SIZE22                  *((volatile unsigned int*)(0x42A42A08UL))
+#define bFM3_USB1_EP2S_SIZE23                  *((volatile unsigned int*)(0x42A42A0CUL))
+#define bFM3_USB1_EP2S_SIZE24                  *((volatile unsigned int*)(0x42A42A10UL))
+#define bFM3_USB1_EP2S_SIZE25                  *((volatile unsigned int*)(0x42A42A14UL))
+#define bFM3_USB1_EP2S_SIZE26                  *((volatile unsigned int*)(0x42A42A18UL))
+#define bFM3_USB1_EP2S_SPK                     *((volatile unsigned int*)(0x42A42A24UL))
+#define bFM3_USB1_EP2S_DRQ                     *((volatile unsigned int*)(0x42A42A28UL))
+#define bFM3_USB1_EP2S_BUSY                    *((volatile unsigned int*)(0x42A42A2CUL))
+#define bFM3_USB1_EP2S_SPKIE                   *((volatile unsigned int*)(0x42A42A34UL))
+#define bFM3_USB1_EP2S_DRQIE                   *((volatile unsigned int*)(0x42A42A38UL))
+#define bFM3_USB1_EP2S_BFINI                   *((volatile unsigned int*)(0x42A42A3CUL))
+#define bFM3_USB1_EP3S_SIZE30                  *((volatile unsigned int*)(0x42A42A80UL))
+#define bFM3_USB1_EP3S_SIZE31                  *((volatile unsigned int*)(0x42A42A84UL))
+#define bFM3_USB1_EP3S_SIZE32                  *((volatile unsigned int*)(0x42A42A88UL))
+#define bFM3_USB1_EP3S_SIZE33                  *((volatile unsigned int*)(0x42A42A8CUL))
+#define bFM3_USB1_EP3S_SIZE34                  *((volatile unsigned int*)(0x42A42A90UL))
+#define bFM3_USB1_EP3S_SIZE35                  *((volatile unsigned int*)(0x42A42A94UL))
+#define bFM3_USB1_EP3S_SIZE36                  *((volatile unsigned int*)(0x42A42A98UL))
+#define bFM3_USB1_EP3S_SPK                     *((volatile unsigned int*)(0x42A42AA4UL))
+#define bFM3_USB1_EP3S_DRQ                     *((volatile unsigned int*)(0x42A42AA8UL))
+#define bFM3_USB1_EP3S_BUSY                    *((volatile unsigned int*)(0x42A42AACUL))
+#define bFM3_USB1_EP3S_SPKIE                   *((volatile unsigned int*)(0x42A42AB4UL))
+#define bFM3_USB1_EP3S_DRQIE                   *((volatile unsigned int*)(0x42A42AB8UL))
+#define bFM3_USB1_EP3S_BFINI                   *((volatile unsigned int*)(0x42A42ABCUL))
+#define bFM3_USB1_EP4S_SIZE40                  *((volatile unsigned int*)(0x42A42B00UL))
+#define bFM3_USB1_EP4S_SIZE41                  *((volatile unsigned int*)(0x42A42B04UL))
+#define bFM3_USB1_EP4S_SIZE42                  *((volatile unsigned int*)(0x42A42B08UL))
+#define bFM3_USB1_EP4S_SIZE43                  *((volatile unsigned int*)(0x42A42B0CUL))
+#define bFM3_USB1_EP4S_SIZE44                  *((volatile unsigned int*)(0x42A42B10UL))
+#define bFM3_USB1_EP4S_SIZE45                  *((volatile unsigned int*)(0x42A42B14UL))
+#define bFM3_USB1_EP4S_SIZE46                  *((volatile unsigned int*)(0x42A42B18UL))
+#define bFM3_USB1_EP4S_SPK                     *((volatile unsigned int*)(0x42A42B24UL))
+#define bFM3_USB1_EP4S_DRQ                     *((volatile unsigned int*)(0x42A42B28UL))
+#define bFM3_USB1_EP4S_BUSY                    *((volatile unsigned int*)(0x42A42B2CUL))
+#define bFM3_USB1_EP4S_SPKIE                   *((volatile unsigned int*)(0x42A42B34UL))
+#define bFM3_USB1_EP4S_DRQIE                   *((volatile unsigned int*)(0x42A42B38UL))
+#define bFM3_USB1_EP4S_BFINI                   *((volatile unsigned int*)(0x42A42B3CUL))
+#define bFM3_USB1_EP5S_SIZE50                  *((volatile unsigned int*)(0x42A42B80UL))
+#define bFM3_USB1_EP5S_SIZE51                  *((volatile unsigned int*)(0x42A42B84UL))
+#define bFM3_USB1_EP5S_SIZE52                  *((volatile unsigned int*)(0x42A42B88UL))
+#define bFM3_USB1_EP5S_SIZE53                  *((volatile unsigned int*)(0x42A42B8CUL))
+#define bFM3_USB1_EP5S_SIZE54                  *((volatile unsigned int*)(0x42A42B90UL))
+#define bFM3_USB1_EP5S_SIZE55                  *((volatile unsigned int*)(0x42A42B94UL))
+#define bFM3_USB1_EP5S_SIZE56                  *((volatile unsigned int*)(0x42A42B98UL))
+#define bFM3_USB1_EP5S_SPK                     *((volatile unsigned int*)(0x42A42BA4UL))
+#define bFM3_USB1_EP5S_DRQ                     *((volatile unsigned int*)(0x42A42BA8UL))
+#define bFM3_USB1_EP5S_BUSY                    *((volatile unsigned int*)(0x42A42BACUL))
+#define bFM3_USB1_EP5S_SPKIE                   *((volatile unsigned int*)(0x42A42BB4UL))
+#define bFM3_USB1_EP5S_DRQIE                   *((volatile unsigned int*)(0x42A42BB8UL))
+#define bFM3_USB1_EP5S_BFINI                   *((volatile unsigned int*)(0x42A42BBCUL))
+
+/* DMA controller */
+#define bFM3_DMAC_DMACR_DH0                    *((volatile unsigned int*)(0x42C00060UL))
+#define bFM3_DMAC_DMACR_DH1                    *((volatile unsigned int*)(0x42C00064UL))
+#define bFM3_DMAC_DMACR_DH2                    *((volatile unsigned int*)(0x42C00068UL))
+#define bFM3_DMAC_DMACR_DH3                    *((volatile unsigned int*)(0x42C0006CUL))
+#define bFM3_DMAC_DMACR_PR                     *((volatile unsigned int*)(0x42C00070UL))
+#define bFM3_DMAC_DMACR_DS                     *((volatile unsigned int*)(0x42C00078UL))
+#define bFM3_DMAC_DMACR_DE                     *((volatile unsigned int*)(0x42C0007CUL))
+#define bFM3_DMAC_DMACA0_TC0                   *((volatile unsigned int*)(0x42C00200UL))
+#define bFM3_DMAC_DMACA0_TC1                   *((volatile unsigned int*)(0x42C00204UL))
+#define bFM3_DMAC_DMACA0_TC2                   *((volatile unsigned int*)(0x42C00208UL))
+#define bFM3_DMAC_DMACA0_TC3                   *((volatile unsigned int*)(0x42C0020CUL))
+#define bFM3_DMAC_DMACA0_TC4                   *((volatile unsigned int*)(0x42C00210UL))
+#define bFM3_DMAC_DMACA0_TC5                   *((volatile unsigned int*)(0x42C00214UL))
+#define bFM3_DMAC_DMACA0_TC6                   *((volatile unsigned int*)(0x42C00218UL))
+#define bFM3_DMAC_DMACA0_TC7                   *((volatile unsigned int*)(0x42C0021CUL))
+#define bFM3_DMAC_DMACA0_TC8                   *((volatile unsigned int*)(0x42C00220UL))
+#define bFM3_DMAC_DMACA0_TC9                   *((volatile unsigned int*)(0x42C00224UL))
+#define bFM3_DMAC_DMACA0_TC10                  *((volatile unsigned int*)(0x42C00228UL))
+#define bFM3_DMAC_DMACA0_TC11                  *((volatile unsigned int*)(0x42C0022CUL))
+#define bFM3_DMAC_DMACA0_TC12                  *((volatile unsigned int*)(0x42C00230UL))
+#define bFM3_DMAC_DMACA0_TC13                  *((volatile unsigned int*)(0x42C00234UL))
+#define bFM3_DMAC_DMACA0_TC14                  *((volatile unsigned int*)(0x42C00238UL))
+#define bFM3_DMAC_DMACA0_TC15                  *((volatile unsigned int*)(0x42C0023CUL))
+#define bFM3_DMAC_DMACA0_BC0                   *((volatile unsigned int*)(0x42C00240UL))
+#define bFM3_DMAC_DMACA0_BC1                   *((volatile unsigned int*)(0x42C00244UL))
+#define bFM3_DMAC_DMACA0_BC2                   *((volatile unsigned int*)(0x42C00248UL))
+#define bFM3_DMAC_DMACA0_BC3                   *((volatile unsigned int*)(0x42C0024CUL))
+#define bFM3_DMAC_DMACA0_IS0                   *((volatile unsigned int*)(0x42C0025CUL))
+#define bFM3_DMAC_DMACA0_IS1                   *((volatile unsigned int*)(0x42C00260UL))
+#define bFM3_DMAC_DMACA0_IS2                   *((volatile unsigned int*)(0x42C00264UL))
+#define bFM3_DMAC_DMACA0_IS3                   *((volatile unsigned int*)(0x42C00268UL))
+#define bFM3_DMAC_DMACA0_IS4                   *((volatile unsigned int*)(0x42C0026CUL))
+#define bFM3_DMAC_DMACA0_IS5                   *((volatile unsigned int*)(0x42C00270UL))
+#define bFM3_DMAC_DMACA0_ST                    *((volatile unsigned int*)(0x42C00274UL))
+#define bFM3_DMAC_DMACA0_PB                    *((volatile unsigned int*)(0x42C00278UL))
+#define bFM3_DMAC_DMACA0_EB                    *((volatile unsigned int*)(0x42C0027CUL))
+#define bFM3_DMAC_DMACB0_EM                    *((volatile unsigned int*)(0x42C00280UL))
+#define bFM3_DMAC_DMACB0_SS0                   *((volatile unsigned int*)(0x42C002C0UL))
+#define bFM3_DMAC_DMACB0_SS1                   *((volatile unsigned int*)(0x42C002C4UL))
+#define bFM3_DMAC_DMACB0_SS2                   *((volatile unsigned int*)(0x42C002C8UL))
+#define bFM3_DMAC_DMACB0_CI                    *((volatile unsigned int*)(0x42C002CCUL))
+#define bFM3_DMAC_DMACB0_EI                    *((volatile unsigned int*)(0x42C002D0UL))
+#define bFM3_DMAC_DMACB0_RD                    *((volatile unsigned int*)(0x42C002D4UL))
+#define bFM3_DMAC_DMACB0_RS                    *((volatile unsigned int*)(0x42C002D8UL))
+#define bFM3_DMAC_DMACB0_RC                    *((volatile unsigned int*)(0x42C002DCUL))
+#define bFM3_DMAC_DMACB0_FD                    *((volatile unsigned int*)(0x42C002E0UL))
+#define bFM3_DMAC_DMACB0_FS                    *((volatile unsigned int*)(0x42C002E4UL))
+#define bFM3_DMAC_DMACB0_TW0                   *((volatile unsigned int*)(0x42C002E8UL))
+#define bFM3_DMAC_DMACB0_TW1                   *((volatile unsigned int*)(0x42C002ECUL))
+#define bFM3_DMAC_DMACB0_MS0                   *((volatile unsigned int*)(0x42C002F0UL))
+#define bFM3_DMAC_DMACB0_MS1                   *((volatile unsigned int*)(0x42C002F4UL))
+#define bFM3_DMAC_DMACA1_TC0                   *((volatile unsigned int*)(0x42C00400UL))
+#define bFM3_DMAC_DMACA1_TC1                   *((volatile unsigned int*)(0x42C00404UL))
+#define bFM3_DMAC_DMACA1_TC2                   *((volatile unsigned int*)(0x42C00408UL))
+#define bFM3_DMAC_DMACA1_TC3                   *((volatile unsigned int*)(0x42C0040CUL))
+#define bFM3_DMAC_DMACA1_TC4                   *((volatile unsigned int*)(0x42C00410UL))
+#define bFM3_DMAC_DMACA1_TC5                   *((volatile unsigned int*)(0x42C00414UL))
+#define bFM3_DMAC_DMACA1_TC6                   *((volatile unsigned int*)(0x42C00418UL))
+#define bFM3_DMAC_DMACA1_TC7                   *((volatile unsigned int*)(0x42C0041CUL))
+#define bFM3_DMAC_DMACA1_TC8                   *((volatile unsigned int*)(0x42C00420UL))
+#define bFM3_DMAC_DMACA1_TC9                   *((volatile unsigned int*)(0x42C00424UL))
+#define bFM3_DMAC_DMACA1_TC10                  *((volatile unsigned int*)(0x42C00428UL))
+#define bFM3_DMAC_DMACA1_TC11                  *((volatile unsigned int*)(0x42C0042CUL))
+#define bFM3_DMAC_DMACA1_TC12                  *((volatile unsigned int*)(0x42C00430UL))
+#define bFM3_DMAC_DMACA1_TC13                  *((volatile unsigned int*)(0x42C00434UL))
+#define bFM3_DMAC_DMACA1_TC14                  *((volatile unsigned int*)(0x42C00438UL))
+#define bFM3_DMAC_DMACA1_TC15                  *((volatile unsigned int*)(0x42C0043CUL))
+#define bFM3_DMAC_DMACA1_BC0                   *((volatile unsigned int*)(0x42C00440UL))
+#define bFM3_DMAC_DMACA1_BC1                   *((volatile unsigned int*)(0x42C00444UL))
+#define bFM3_DMAC_DMACA1_BC2                   *((volatile unsigned int*)(0x42C00448UL))
+#define bFM3_DMAC_DMACA1_BC3                   *((volatile unsigned int*)(0x42C0044CUL))
+#define bFM3_DMAC_DMACA1_IS0                   *((volatile unsigned int*)(0x42C0045CUL))
+#define bFM3_DMAC_DMACA1_IS1                   *((volatile unsigned int*)(0x42C00460UL))
+#define bFM3_DMAC_DMACA1_IS2                   *((volatile unsigned int*)(0x42C00464UL))
+#define bFM3_DMAC_DMACA1_IS3                   *((volatile unsigned int*)(0x42C00468UL))
+#define bFM3_DMAC_DMACA1_IS4                   *((volatile unsigned int*)(0x42C0046CUL))
+#define bFM3_DMAC_DMACA1_IS5                   *((volatile unsigned int*)(0x42C00470UL))
+#define bFM3_DMAC_DMACA1_ST                    *((volatile unsigned int*)(0x42C00474UL))
+#define bFM3_DMAC_DMACA1_PB                    *((volatile unsigned int*)(0x42C00478UL))
+#define bFM3_DMAC_DMACA1_EB                    *((volatile unsigned int*)(0x42C0047CUL))
+#define bFM3_DMAC_DMACB1_EM                    *((volatile unsigned int*)(0x42C00480UL))
+#define bFM3_DMAC_DMACB1_SS0                   *((volatile unsigned int*)(0x42C004C0UL))
+#define bFM3_DMAC_DMACB1_SS1                   *((volatile unsigned int*)(0x42C004C4UL))
+#define bFM3_DMAC_DMACB1_SS2                   *((volatile unsigned int*)(0x42C004C8UL))
+#define bFM3_DMAC_DMACB1_CI                    *((volatile unsigned int*)(0x42C004CCUL))
+#define bFM3_DMAC_DMACB1_EI                    *((volatile unsigned int*)(0x42C004D0UL))
+#define bFM3_DMAC_DMACB1_RD                    *((volatile unsigned int*)(0x42C004D4UL))
+#define bFM3_DMAC_DMACB1_RS                    *((volatile unsigned int*)(0x42C004D8UL))
+#define bFM3_DMAC_DMACB1_RC                    *((volatile unsigned int*)(0x42C004DCUL))
+#define bFM3_DMAC_DMACB1_FD                    *((volatile unsigned int*)(0x42C004E0UL))
+#define bFM3_DMAC_DMACB1_FS                    *((volatile unsigned int*)(0x42C004E4UL))
+#define bFM3_DMAC_DMACB1_TW0                   *((volatile unsigned int*)(0x42C004E8UL))
+#define bFM3_DMAC_DMACB1_TW1                   *((volatile unsigned int*)(0x42C004ECUL))
+#define bFM3_DMAC_DMACB1_MS0                   *((volatile unsigned int*)(0x42C004F0UL))
+#define bFM3_DMAC_DMACB1_MS1                   *((volatile unsigned int*)(0x42C004F4UL))
+#define bFM3_DMAC_DMACA2_TC0                   *((volatile unsigned int*)(0x42C00600UL))
+#define bFM3_DMAC_DMACA2_TC1                   *((volatile unsigned int*)(0x42C00604UL))
+#define bFM3_DMAC_DMACA2_TC2                   *((volatile unsigned int*)(0x42C00608UL))
+#define bFM3_DMAC_DMACA2_TC3                   *((volatile unsigned int*)(0x42C0060CUL))
+#define bFM3_DMAC_DMACA2_TC4                   *((volatile unsigned int*)(0x42C00610UL))
+#define bFM3_DMAC_DMACA2_TC5                   *((volatile unsigned int*)(0x42C00614UL))
+#define bFM3_DMAC_DMACA2_TC6                   *((volatile unsigned int*)(0x42C00618UL))
+#define bFM3_DMAC_DMACA2_TC7                   *((volatile unsigned int*)(0x42C0061CUL))
+#define bFM3_DMAC_DMACA2_TC8                   *((volatile unsigned int*)(0x42C00620UL))
+#define bFM3_DMAC_DMACA2_TC9                   *((volatile unsigned int*)(0x42C00624UL))
+#define bFM3_DMAC_DMACA2_TC10                  *((volatile unsigned int*)(0x42C00628UL))
+#define bFM3_DMAC_DMACA2_TC11                  *((volatile unsigned int*)(0x42C0062CUL))
+#define bFM3_DMAC_DMACA2_TC12                  *((volatile unsigned int*)(0x42C00630UL))
+#define bFM3_DMAC_DMACA2_TC13                  *((volatile unsigned int*)(0x42C00634UL))
+#define bFM3_DMAC_DMACA2_TC14                  *((volatile unsigned int*)(0x42C00638UL))
+#define bFM3_DMAC_DMACA2_TC15                  *((volatile unsigned int*)(0x42C0063CUL))
+#define bFM3_DMAC_DMACA2_BC0                   *((volatile unsigned int*)(0x42C00640UL))
+#define bFM3_DMAC_DMACA2_BC1                   *((volatile unsigned int*)(0x42C00644UL))
+#define bFM3_DMAC_DMACA2_BC2                   *((volatile unsigned int*)(0x42C00648UL))
+#define bFM3_DMAC_DMACA2_BC3                   *((volatile unsigned int*)(0x42C0064CUL))
+#define bFM3_DMAC_DMACA2_IS0                   *((volatile unsigned int*)(0x42C0065CUL))
+#define bFM3_DMAC_DMACA2_IS1                   *((volatile unsigned int*)(0x42C00660UL))
+#define bFM3_DMAC_DMACA2_IS2                   *((volatile unsigned int*)(0x42C00664UL))
+#define bFM3_DMAC_DMACA2_IS3                   *((volatile unsigned int*)(0x42C00668UL))
+#define bFM3_DMAC_DMACA2_IS4                   *((volatile unsigned int*)(0x42C0066CUL))
+#define bFM3_DMAC_DMACA2_IS5                   *((volatile unsigned int*)(0x42C00670UL))
+#define bFM3_DMAC_DMACA2_ST                    *((volatile unsigned int*)(0x42C00674UL))
+#define bFM3_DMAC_DMACA2_PB                    *((volatile unsigned int*)(0x42C00678UL))
+#define bFM3_DMAC_DMACA2_EB                    *((volatile unsigned int*)(0x42C0067CUL))
+#define bFM3_DMAC_DMACB2_EM                    *((volatile unsigned int*)(0x42C00680UL))
+#define bFM3_DMAC_DMACB2_SS0                   *((volatile unsigned int*)(0x42C006C0UL))
+#define bFM3_DMAC_DMACB2_SS1                   *((volatile unsigned int*)(0x42C006C4UL))
+#define bFM3_DMAC_DMACB2_SS2                   *((volatile unsigned int*)(0x42C006C8UL))
+#define bFM3_DMAC_DMACB2_CI                    *((volatile unsigned int*)(0x42C006CCUL))
+#define bFM3_DMAC_DMACB2_EI                    *((volatile unsigned int*)(0x42C006D0UL))
+#define bFM3_DMAC_DMACB2_RD                    *((volatile unsigned int*)(0x42C006D4UL))
+#define bFM3_DMAC_DMACB2_RS                    *((volatile unsigned int*)(0x42C006D8UL))
+#define bFM3_DMAC_DMACB2_RC                    *((volatile unsigned int*)(0x42C006DCUL))
+#define bFM3_DMAC_DMACB2_FD                    *((volatile unsigned int*)(0x42C006E0UL))
+#define bFM3_DMAC_DMACB2_FS                    *((volatile unsigned int*)(0x42C006E4UL))
+#define bFM3_DMAC_DMACB2_TW0                   *((volatile unsigned int*)(0x42C006E8UL))
+#define bFM3_DMAC_DMACB2_TW1                   *((volatile unsigned int*)(0x42C006ECUL))
+#define bFM3_DMAC_DMACB2_MS0                   *((volatile unsigned int*)(0x42C006F0UL))
+#define bFM3_DMAC_DMACB2_MS1                   *((volatile unsigned int*)(0x42C006F4UL))
+#define bFM3_DMAC_DMACA3_TC0                   *((volatile unsigned int*)(0x42C00800UL))
+#define bFM3_DMAC_DMACA3_TC1                   *((volatile unsigned int*)(0x42C00804UL))
+#define bFM3_DMAC_DMACA3_TC2                   *((volatile unsigned int*)(0x42C00808UL))
+#define bFM3_DMAC_DMACA3_TC3                   *((volatile unsigned int*)(0x42C0080CUL))
+#define bFM3_DMAC_DMACA3_TC4                   *((volatile unsigned int*)(0x42C00810UL))
+#define bFM3_DMAC_DMACA3_TC5                   *((volatile unsigned int*)(0x42C00814UL))
+#define bFM3_DMAC_DMACA3_TC6                   *((volatile unsigned int*)(0x42C00818UL))
+#define bFM3_DMAC_DMACA3_TC7                   *((volatile unsigned int*)(0x42C0081CUL))
+#define bFM3_DMAC_DMACA3_TC8                   *((volatile unsigned int*)(0x42C00820UL))
+#define bFM3_DMAC_DMACA3_TC9                   *((volatile unsigned int*)(0x42C00824UL))
+#define bFM3_DMAC_DMACA3_TC10                  *((volatile unsigned int*)(0x42C00828UL))
+#define bFM3_DMAC_DMACA3_TC11                  *((volatile unsigned int*)(0x42C0082CUL))
+#define bFM3_DMAC_DMACA3_TC12                  *((volatile unsigned int*)(0x42C00830UL))
+#define bFM3_DMAC_DMACA3_TC13                  *((volatile unsigned int*)(0x42C00834UL))
+#define bFM3_DMAC_DMACA3_TC14                  *((volatile unsigned int*)(0x42C00838UL))
+#define bFM3_DMAC_DMACA3_TC15                  *((volatile unsigned int*)(0x42C0083CUL))
+#define bFM3_DMAC_DMACA3_BC0                   *((volatile unsigned int*)(0x42C00840UL))
+#define bFM3_DMAC_DMACA3_BC1                   *((volatile unsigned int*)(0x42C00844UL))
+#define bFM3_DMAC_DMACA3_BC2                   *((volatile unsigned int*)(0x42C00848UL))
+#define bFM3_DMAC_DMACA3_BC3                   *((volatile unsigned int*)(0x42C0084CUL))
+#define bFM3_DMAC_DMACA3_IS0                   *((volatile unsigned int*)(0x42C0085CUL))
+#define bFM3_DMAC_DMACA3_IS1                   *((volatile unsigned int*)(0x42C00860UL))
+#define bFM3_DMAC_DMACA3_IS2                   *((volatile unsigned int*)(0x42C00864UL))
+#define bFM3_DMAC_DMACA3_IS3                   *((volatile unsigned int*)(0x42C00868UL))
+#define bFM3_DMAC_DMACA3_IS4                   *((volatile unsigned int*)(0x42C0086CUL))
+#define bFM3_DMAC_DMACA3_IS5                   *((volatile unsigned int*)(0x42C00870UL))
+#define bFM3_DMAC_DMACA3_ST                    *((volatile unsigned int*)(0x42C00874UL))
+#define bFM3_DMAC_DMACA3_PB                    *((volatile unsigned int*)(0x42C00878UL))
+#define bFM3_DMAC_DMACA3_EB                    *((volatile unsigned int*)(0x42C0087CUL))
+#define bFM3_DMAC_DMACB3_EM                    *((volatile unsigned int*)(0x42C00880UL))
+#define bFM3_DMAC_DMACB3_SS0                   *((volatile unsigned int*)(0x42C008C0UL))
+#define bFM3_DMAC_DMACB3_SS1                   *((volatile unsigned int*)(0x42C008C4UL))
+#define bFM3_DMAC_DMACB3_SS2                   *((volatile unsigned int*)(0x42C008C8UL))
+#define bFM3_DMAC_DMACB3_CI                    *((volatile unsigned int*)(0x42C008CCUL))
+#define bFM3_DMAC_DMACB3_EI                    *((volatile unsigned int*)(0x42C008D0UL))
+#define bFM3_DMAC_DMACB3_RD                    *((volatile unsigned int*)(0x42C008D4UL))
+#define bFM3_DMAC_DMACB3_RS                    *((volatile unsigned int*)(0x42C008D8UL))
+#define bFM3_DMAC_DMACB3_RC                    *((volatile unsigned int*)(0x42C008DCUL))
+#define bFM3_DMAC_DMACB3_FD                    *((volatile unsigned int*)(0x42C008E0UL))
+#define bFM3_DMAC_DMACB3_FS                    *((volatile unsigned int*)(0x42C008E4UL))
+#define bFM3_DMAC_DMACB3_TW0                   *((volatile unsigned int*)(0x42C008E8UL))
+#define bFM3_DMAC_DMACB3_TW1                   *((volatile unsigned int*)(0x42C008ECUL))
+#define bFM3_DMAC_DMACB3_MS0                   *((volatile unsigned int*)(0x42C008F0UL))
+#define bFM3_DMAC_DMACB3_MS1                   *((volatile unsigned int*)(0x42C008F4UL))
+#define bFM3_DMAC_DMACA4_TC0                   *((volatile unsigned int*)(0x42C00A00UL))
+#define bFM3_DMAC_DMACA4_TC1                   *((volatile unsigned int*)(0x42C00A04UL))
+#define bFM3_DMAC_DMACA4_TC2                   *((volatile unsigned int*)(0x42C00A08UL))
+#define bFM3_DMAC_DMACA4_TC3                   *((volatile unsigned int*)(0x42C00A0CUL))
+#define bFM3_DMAC_DMACA4_TC4                   *((volatile unsigned int*)(0x42C00A10UL))
+#define bFM3_DMAC_DMACA4_TC5                   *((volatile unsigned int*)(0x42C00A14UL))
+#define bFM3_DMAC_DMACA4_TC6                   *((volatile unsigned int*)(0x42C00A18UL))
+#define bFM3_DMAC_DMACA4_TC7                   *((volatile unsigned int*)(0x42C00A1CUL))
+#define bFM3_DMAC_DMACA4_TC8                   *((volatile unsigned int*)(0x42C00A20UL))
+#define bFM3_DMAC_DMACA4_TC9                   *((volatile unsigned int*)(0x42C00A24UL))
+#define bFM3_DMAC_DMACA4_TC10                  *((volatile unsigned int*)(0x42C00A28UL))
+#define bFM3_DMAC_DMACA4_TC11                  *((volatile unsigned int*)(0x42C00A2CUL))
+#define bFM3_DMAC_DMACA4_TC12                  *((volatile unsigned int*)(0x42C00A30UL))
+#define bFM3_DMAC_DMACA4_TC13                  *((volatile unsigned int*)(0x42C00A34UL))
+#define bFM3_DMAC_DMACA4_TC14                  *((volatile unsigned int*)(0x42C00A38UL))
+#define bFM3_DMAC_DMACA4_TC15                  *((volatile unsigned int*)(0x42C00A3CUL))
+#define bFM3_DMAC_DMACA4_BC0                   *((volatile unsigned int*)(0x42C00A40UL))
+#define bFM3_DMAC_DMACA4_BC1                   *((volatile unsigned int*)(0x42C00A44UL))
+#define bFM3_DMAC_DMACA4_BC2                   *((volatile unsigned int*)(0x42C00A48UL))
+#define bFM3_DMAC_DMACA4_BC3                   *((volatile unsigned int*)(0x42C00A4CUL))
+#define bFM3_DMAC_DMACA4_IS0                   *((volatile unsigned int*)(0x42C00A5CUL))
+#define bFM3_DMAC_DMACA4_IS1                   *((volatile unsigned int*)(0x42C00A60UL))
+#define bFM3_DMAC_DMACA4_IS2                   *((volatile unsigned int*)(0x42C00A64UL))
+#define bFM3_DMAC_DMACA4_IS3                   *((volatile unsigned int*)(0x42C00A68UL))
+#define bFM3_DMAC_DMACA4_IS4                   *((volatile unsigned int*)(0x42C00A6CUL))
+#define bFM3_DMAC_DMACA4_IS5                   *((volatile unsigned int*)(0x42C00A70UL))
+#define bFM3_DMAC_DMACA4_ST                    *((volatile unsigned int*)(0x42C00A74UL))
+#define bFM3_DMAC_DMACA4_PB                    *((volatile unsigned int*)(0x42C00A78UL))
+#define bFM3_DMAC_DMACA4_EB                    *((volatile unsigned int*)(0x42C00A7CUL))
+#define bFM3_DMAC_DMACB4_EM                    *((volatile unsigned int*)(0x42C00A80UL))
+#define bFM3_DMAC_DMACB4_SS0                   *((volatile unsigned int*)(0x42C00AC0UL))
+#define bFM3_DMAC_DMACB4_SS1                   *((volatile unsigned int*)(0x42C00AC4UL))
+#define bFM3_DMAC_DMACB4_SS2                   *((volatile unsigned int*)(0x42C00AC8UL))
+#define bFM3_DMAC_DMACB4_CI                    *((volatile unsigned int*)(0x42C00ACCUL))
+#define bFM3_DMAC_DMACB4_EI                    *((volatile unsigned int*)(0x42C00AD0UL))
+#define bFM3_DMAC_DMACB4_RD                    *((volatile unsigned int*)(0x42C00AD4UL))
+#define bFM3_DMAC_DMACB4_RS                    *((volatile unsigned int*)(0x42C00AD8UL))
+#define bFM3_DMAC_DMACB4_RC                    *((volatile unsigned int*)(0x42C00ADCUL))
+#define bFM3_DMAC_DMACB4_FD                    *((volatile unsigned int*)(0x42C00AE0UL))
+#define bFM3_DMAC_DMACB4_FS                    *((volatile unsigned int*)(0x42C00AE4UL))
+#define bFM3_DMAC_DMACB4_TW0                   *((volatile unsigned int*)(0x42C00AE8UL))
+#define bFM3_DMAC_DMACB4_TW1                   *((volatile unsigned int*)(0x42C00AECUL))
+#define bFM3_DMAC_DMACB4_MS0                   *((volatile unsigned int*)(0x42C00AF0UL))
+#define bFM3_DMAC_DMACB4_MS1                   *((volatile unsigned int*)(0x42C00AF4UL))
+#define bFM3_DMAC_DMACA5_TC0                   *((volatile unsigned int*)(0x42C00C00UL))
+#define bFM3_DMAC_DMACA5_TC1                   *((volatile unsigned int*)(0x42C00C04UL))
+#define bFM3_DMAC_DMACA5_TC2                   *((volatile unsigned int*)(0x42C00C08UL))
+#define bFM3_DMAC_DMACA5_TC3                   *((volatile unsigned int*)(0x42C00C0CUL))
+#define bFM3_DMAC_DMACA5_TC4                   *((volatile unsigned int*)(0x42C00C10UL))
+#define bFM3_DMAC_DMACA5_TC5                   *((volatile unsigned int*)(0x42C00C14UL))
+#define bFM3_DMAC_DMACA5_TC6                   *((volatile unsigned int*)(0x42C00C18UL))
+#define bFM3_DMAC_DMACA5_TC7                   *((volatile unsigned int*)(0x42C00C1CUL))
+#define bFM3_DMAC_DMACA5_TC8                   *((volatile unsigned int*)(0x42C00C20UL))
+#define bFM3_DMAC_DMACA5_TC9                   *((volatile unsigned int*)(0x42C00C24UL))
+#define bFM3_DMAC_DMACA5_TC10                  *((volatile unsigned int*)(0x42C00C28UL))
+#define bFM3_DMAC_DMACA5_TC11                  *((volatile unsigned int*)(0x42C00C2CUL))
+#define bFM3_DMAC_DMACA5_TC12                  *((volatile unsigned int*)(0x42C00C30UL))
+#define bFM3_DMAC_DMACA5_TC13                  *((volatile unsigned int*)(0x42C00C34UL))
+#define bFM3_DMAC_DMACA5_TC14                  *((volatile unsigned int*)(0x42C00C38UL))
+#define bFM3_DMAC_DMACA5_TC15                  *((volatile unsigned int*)(0x42C00C3CUL))
+#define bFM3_DMAC_DMACA5_BC0                   *((volatile unsigned int*)(0x42C00C40UL))
+#define bFM3_DMAC_DMACA5_BC1                   *((volatile unsigned int*)(0x42C00C44UL))
+#define bFM3_DMAC_DMACA5_BC2                   *((volatile unsigned int*)(0x42C00C48UL))
+#define bFM3_DMAC_DMACA5_BC3                   *((volatile unsigned int*)(0x42C00C4CUL))
+#define bFM3_DMAC_DMACA5_IS0                   *((volatile unsigned int*)(0x42C00C5CUL))
+#define bFM3_DMAC_DMACA5_IS1                   *((volatile unsigned int*)(0x42C00C60UL))
+#define bFM3_DMAC_DMACA5_IS2                   *((volatile unsigned int*)(0x42C00C64UL))
+#define bFM3_DMAC_DMACA5_IS3                   *((volatile unsigned int*)(0x42C00C68UL))
+#define bFM3_DMAC_DMACA5_IS4                   *((volatile unsigned int*)(0x42C00C6CUL))
+#define bFM3_DMAC_DMACA5_IS5                   *((volatile unsigned int*)(0x42C00C70UL))
+#define bFM3_DMAC_DMACA5_ST                    *((volatile unsigned int*)(0x42C00C74UL))
+#define bFM3_DMAC_DMACA5_PB                    *((volatile unsigned int*)(0x42C00C78UL))
+#define bFM3_DMAC_DMACA5_EB                    *((volatile unsigned int*)(0x42C00C7CUL))
+#define bFM3_DMAC_DMACB5_EM                    *((volatile unsigned int*)(0x42C00C80UL))
+#define bFM3_DMAC_DMACB5_SS0                   *((volatile unsigned int*)(0x42C00CC0UL))
+#define bFM3_DMAC_DMACB5_SS1                   *((volatile unsigned int*)(0x42C00CC4UL))
+#define bFM3_DMAC_DMACB5_SS2                   *((volatile unsigned int*)(0x42C00CC8UL))
+#define bFM3_DMAC_DMACB5_CI                    *((volatile unsigned int*)(0x42C00CCCUL))
+#define bFM3_DMAC_DMACB5_EI                    *((volatile unsigned int*)(0x42C00CD0UL))
+#define bFM3_DMAC_DMACB5_RD                    *((volatile unsigned int*)(0x42C00CD4UL))
+#define bFM3_DMAC_DMACB5_RS                    *((volatile unsigned int*)(0x42C00CD8UL))
+#define bFM3_DMAC_DMACB5_RC                    *((volatile unsigned int*)(0x42C00CDCUL))
+#define bFM3_DMAC_DMACB5_FD                    *((volatile unsigned int*)(0x42C00CE0UL))
+#define bFM3_DMAC_DMACB5_FS                    *((volatile unsigned int*)(0x42C00CE4UL))
+#define bFM3_DMAC_DMACB5_TW0                   *((volatile unsigned int*)(0x42C00CE8UL))
+#define bFM3_DMAC_DMACB5_TW1                   *((volatile unsigned int*)(0x42C00CECUL))
+#define bFM3_DMAC_DMACB5_MS0                   *((volatile unsigned int*)(0x42C00CF0UL))
+#define bFM3_DMAC_DMACB5_MS1                   *((volatile unsigned int*)(0x42C00CF4UL))
+#define bFM3_DMAC_DMACA6_TC0                   *((volatile unsigned int*)(0x42C00E00UL))
+#define bFM3_DMAC_DMACA6_TC1                   *((volatile unsigned int*)(0x42C00E04UL))
+#define bFM3_DMAC_DMACA6_TC2                   *((volatile unsigned int*)(0x42C00E08UL))
+#define bFM3_DMAC_DMACA6_TC3                   *((volatile unsigned int*)(0x42C00E0CUL))
+#define bFM3_DMAC_DMACA6_TC4                   *((volatile unsigned int*)(0x42C00E10UL))
+#define bFM3_DMAC_DMACA6_TC5                   *((volatile unsigned int*)(0x42C00E14UL))
+#define bFM3_DMAC_DMACA6_TC6                   *((volatile unsigned int*)(0x42C00E18UL))
+#define bFM3_DMAC_DMACA6_TC7                   *((volatile unsigned int*)(0x42C00E1CUL))
+#define bFM3_DMAC_DMACA6_TC8                   *((volatile unsigned int*)(0x42C00E20UL))
+#define bFM3_DMAC_DMACA6_TC9                   *((volatile unsigned int*)(0x42C00E24UL))
+#define bFM3_DMAC_DMACA6_TC10                  *((volatile unsigned int*)(0x42C00E28UL))
+#define bFM3_DMAC_DMACA6_TC11                  *((volatile unsigned int*)(0x42C00E2CUL))
+#define bFM3_DMAC_DMACA6_TC12                  *((volatile unsigned int*)(0x42C00E30UL))
+#define bFM3_DMAC_DMACA6_TC13                  *((volatile unsigned int*)(0x42C00E34UL))
+#define bFM3_DMAC_DMACA6_TC14                  *((volatile unsigned int*)(0x42C00E38UL))
+#define bFM3_DMAC_DMACA6_TC15                  *((volatile unsigned int*)(0x42C00E3CUL))
+#define bFM3_DMAC_DMACA6_BC0                   *((volatile unsigned int*)(0x42C00E40UL))
+#define bFM3_DMAC_DMACA6_BC1                   *((volatile unsigned int*)(0x42C00E44UL))
+#define bFM3_DMAC_DMACA6_BC2                   *((volatile unsigned int*)(0x42C00E48UL))
+#define bFM3_DMAC_DMACA6_BC3                   *((volatile unsigned int*)(0x42C00E4CUL))
+#define bFM3_DMAC_DMACA6_IS0                   *((volatile unsigned int*)(0x42C00E5CUL))
+#define bFM3_DMAC_DMACA6_IS1                   *((volatile unsigned int*)(0x42C00E60UL))
+#define bFM3_DMAC_DMACA6_IS2                   *((volatile unsigned int*)(0x42C00E64UL))
+#define bFM3_DMAC_DMACA6_IS3                   *((volatile unsigned int*)(0x42C00E68UL))
+#define bFM3_DMAC_DMACA6_IS4                   *((volatile unsigned int*)(0x42C00E6CUL))
+#define bFM3_DMAC_DMACA6_IS5                   *((volatile unsigned int*)(0x42C00E70UL))
+#define bFM3_DMAC_DMACA6_ST                    *((volatile unsigned int*)(0x42C00E74UL))
+#define bFM3_DMAC_DMACA6_PB                    *((volatile unsigned int*)(0x42C00E78UL))
+#define bFM3_DMAC_DMACA6_EB                    *((volatile unsigned int*)(0x42C00E7CUL))
+#define bFM3_DMAC_DMACB6_EM                    *((volatile unsigned int*)(0x42C00E80UL))
+#define bFM3_DMAC_DMACB6_SS0                   *((volatile unsigned int*)(0x42C00EC0UL))
+#define bFM3_DMAC_DMACB6_SS1                   *((volatile unsigned int*)(0x42C00EC4UL))
+#define bFM3_DMAC_DMACB6_SS2                   *((volatile unsigned int*)(0x42C00EC8UL))
+#define bFM3_DMAC_DMACB6_CI                    *((volatile unsigned int*)(0x42C00ECCUL))
+#define bFM3_DMAC_DMACB6_EI                    *((volatile unsigned int*)(0x42C00ED0UL))
+#define bFM3_DMAC_DMACB6_RD                    *((volatile unsigned int*)(0x42C00ED4UL))
+#define bFM3_DMAC_DMACB6_RS                    *((volatile unsigned int*)(0x42C00ED8UL))
+#define bFM3_DMAC_DMACB6_RC                    *((volatile unsigned int*)(0x42C00EDCUL))
+#define bFM3_DMAC_DMACB6_FD                    *((volatile unsigned int*)(0x42C00EE0UL))
+#define bFM3_DMAC_DMACB6_FS                    *((volatile unsigned int*)(0x42C00EE4UL))
+#define bFM3_DMAC_DMACB6_TW0                   *((volatile unsigned int*)(0x42C00EE8UL))
+#define bFM3_DMAC_DMACB6_TW1                   *((volatile unsigned int*)(0x42C00EECUL))
+#define bFM3_DMAC_DMACB6_MS0                   *((volatile unsigned int*)(0x42C00EF0UL))
+#define bFM3_DMAC_DMACB6_MS1                   *((volatile unsigned int*)(0x42C00EF4UL))
+#define bFM3_DMAC_DMACA7_TC0                   *((volatile unsigned int*)(0x42C01000UL))
+#define bFM3_DMAC_DMACA7_TC1                   *((volatile unsigned int*)(0x42C01004UL))
+#define bFM3_DMAC_DMACA7_TC2                   *((volatile unsigned int*)(0x42C01008UL))
+#define bFM3_DMAC_DMACA7_TC3                   *((volatile unsigned int*)(0x42C0100CUL))
+#define bFM3_DMAC_DMACA7_TC4                   *((volatile unsigned int*)(0x42C01010UL))
+#define bFM3_DMAC_DMACA7_TC5                   *((volatile unsigned int*)(0x42C01014UL))
+#define bFM3_DMAC_DMACA7_TC6                   *((volatile unsigned int*)(0x42C01018UL))
+#define bFM3_DMAC_DMACA7_TC7                   *((volatile unsigned int*)(0x42C0101CUL))
+#define bFM3_DMAC_DMACA7_TC8                   *((volatile unsigned int*)(0x42C01020UL))
+#define bFM3_DMAC_DMACA7_TC9                   *((volatile unsigned int*)(0x42C01024UL))
+#define bFM3_DMAC_DMACA7_TC10                  *((volatile unsigned int*)(0x42C01028UL))
+#define bFM3_DMAC_DMACA7_TC11                  *((volatile unsigned int*)(0x42C0102CUL))
+#define bFM3_DMAC_DMACA7_TC12                  *((volatile unsigned int*)(0x42C01030UL))
+#define bFM3_DMAC_DMACA7_TC13                  *((volatile unsigned int*)(0x42C01034UL))
+#define bFM3_DMAC_DMACA7_TC14                  *((volatile unsigned int*)(0x42C01038UL))
+#define bFM3_DMAC_DMACA7_TC15                  *((volatile unsigned int*)(0x42C0103CUL))
+#define bFM3_DMAC_DMACA7_BC0                   *((volatile unsigned int*)(0x42C01040UL))
+#define bFM3_DMAC_DMACA7_BC1                   *((volatile unsigned int*)(0x42C01044UL))
+#define bFM3_DMAC_DMACA7_BC2                   *((volatile unsigned int*)(0x42C01048UL))
+#define bFM3_DMAC_DMACA7_BC3                   *((volatile unsigned int*)(0x42C0104CUL))
+#define bFM3_DMAC_DMACA7_IS0                   *((volatile unsigned int*)(0x42C0105CUL))
+#define bFM3_DMAC_DMACA7_IS1                   *((volatile unsigned int*)(0x42C01060UL))
+#define bFM3_DMAC_DMACA7_IS2                   *((volatile unsigned int*)(0x42C01064UL))
+#define bFM3_DMAC_DMACA7_IS3                   *((volatile unsigned int*)(0x42C01068UL))
+#define bFM3_DMAC_DMACA7_IS4                   *((volatile unsigned int*)(0x42C0106CUL))
+#define bFM3_DMAC_DMACA7_IS5                   *((volatile unsigned int*)(0x42C01070UL))
+#define bFM3_DMAC_DMACA7_ST                    *((volatile unsigned int*)(0x42C01074UL))
+#define bFM3_DMAC_DMACA7_PB                    *((volatile unsigned int*)(0x42C01078UL))
+#define bFM3_DMAC_DMACA7_EB                    *((volatile unsigned int*)(0x42C0107CUL))
+#define bFM3_DMAC_DMACB7_EM                    *((volatile unsigned int*)(0x42C01080UL))
+#define bFM3_DMAC_DMACB7_SS0                   *((volatile unsigned int*)(0x42C010C0UL))
+#define bFM3_DMAC_DMACB7_SS1                   *((volatile unsigned int*)(0x42C010C4UL))
+#define bFM3_DMAC_DMACB7_SS2                   *((volatile unsigned int*)(0x42C010C8UL))
+#define bFM3_DMAC_DMACB7_CI                    *((volatile unsigned int*)(0x42C010CCUL))
+#define bFM3_DMAC_DMACB7_EI                    *((volatile unsigned int*)(0x42C010D0UL))
+#define bFM3_DMAC_DMACB7_RD                    *((volatile unsigned int*)(0x42C010D4UL))
+#define bFM3_DMAC_DMACB7_RS                    *((volatile unsigned int*)(0x42C010D8UL))
+#define bFM3_DMAC_DMACB7_RC                    *((volatile unsigned int*)(0x42C010DCUL))
+#define bFM3_DMAC_DMACB7_FD                    *((volatile unsigned int*)(0x42C010E0UL))
+#define bFM3_DMAC_DMACB7_FS                    *((volatile unsigned int*)(0x42C010E4UL))
+#define bFM3_DMAC_DMACB7_TW0                   *((volatile unsigned int*)(0x42C010E8UL))
+#define bFM3_DMAC_DMACB7_TW1                   *((volatile unsigned int*)(0x42C010ECUL))
+#define bFM3_DMAC_DMACB7_MS0                   *((volatile unsigned int*)(0x42C010F0UL))
+#define bFM3_DMAC_DMACB7_MS1                   *((volatile unsigned int*)(0x42C010F4UL))
+
+/* ETHERNET-MAC0 registers*/
+#define bFM3_ETHERNET_MAC0_MCR_RE              *((volatile unsigned int*)(0x42C80008UL))
+#define bFM3_ETHERNET_MAC0_MCR_TE              *((volatile unsigned int*)(0x42C8000CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DC              *((volatile unsigned int*)(0x42C80010UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL0             *((volatile unsigned int*)(0x42C80014UL))
+#define bFM3_ETHERNET_MAC0_MCR_BL1             *((volatile unsigned int*)(0x42C80018UL))
+#define bFM3_ETHERNET_MAC0_MCR_ACS             *((volatile unsigned int*)(0x42C8001CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LUD             *((volatile unsigned int*)(0x42C80020UL))
+#define bFM3_ETHERNET_MAC0_MCR_DR              *((volatile unsigned int*)(0x42C80024UL))
+#define bFM3_ETHERNET_MAC0_MCR_IPC             *((volatile unsigned int*)(0x42C80028UL))
+#define bFM3_ETHERNET_MAC0_MCR_DM              *((volatile unsigned int*)(0x42C8002CUL))
+#define bFM3_ETHERNET_MAC0_MCR_LM              *((volatile unsigned int*)(0x42C80030UL))
+#define bFM3_ETHERNET_MAC0_MCR_DO              *((volatile unsigned int*)(0x42C80034UL))
+#define bFM3_ETHERNET_MAC0_MCR_FES             *((volatile unsigned int*)(0x42C80038UL))
+#define bFM3_ETHERNET_MAC0_MCR_PS              *((volatile unsigned int*)(0x42C8003CUL))
+#define bFM3_ETHERNET_MAC0_MCR_DCRS            *((volatile unsigned int*)(0x42C80040UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG0            *((volatile unsigned int*)(0x42C80044UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG1            *((volatile unsigned int*)(0x42C80048UL))
+#define bFM3_ETHERNET_MAC0_MCR_IFG2            *((volatile unsigned int*)(0x42C8004CUL))
+#define bFM3_ETHERNET_MAC0_MCR_JE              *((volatile unsigned int*)(0x42C80050UL))
+#define bFM3_ETHERNET_MAC0_MCR_BE              *((volatile unsigned int*)(0x42C80054UL))
+#define bFM3_ETHERNET_MAC0_MCR_JD              *((volatile unsigned int*)(0x42C80058UL))
+#define bFM3_ETHERNET_MAC0_MCR_WD              *((volatile unsigned int*)(0x42C8005CUL))
+#define bFM3_ETHERNET_MAC0_MCR_TC              *((volatile unsigned int*)(0x42C80060UL))
+#define bFM3_ETHERNET_MAC0_MCR_CST             *((volatile unsigned int*)(0x42C80064UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PR             *((volatile unsigned int*)(0x42C80080UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HUC            *((volatile unsigned int*)(0x42C80084UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HMC            *((volatile unsigned int*)(0x42C80088UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DAIF           *((volatile unsigned int*)(0x42C8008CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_PM             *((volatile unsigned int*)(0x42C80090UL))
+#define bFM3_ETHERNET_MAC0_MFFR_DB             *((volatile unsigned int*)(0x42C80094UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF0           *((volatile unsigned int*)(0x42C80098UL))
+#define bFM3_ETHERNET_MAC0_MFFR_PCF1           *((volatile unsigned int*)(0x42C8009CUL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAIF           *((volatile unsigned int*)(0x42C800A0UL))
+#define bFM3_ETHERNET_MAC0_MFFR_SAF            *((volatile unsigned int*)(0x42C800A4UL))
+#define bFM3_ETHERNET_MAC0_MFFR_HPF            *((volatile unsigned int*)(0x42C800A8UL))
+#define bFM3_ETHERNET_MAC0_MFFR_RA             *((volatile unsigned int*)(0x42C800FCUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH0          *((volatile unsigned int*)(0x42C80100UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH1          *((volatile unsigned int*)(0x42C80104UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH2          *((volatile unsigned int*)(0x42C80108UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH3          *((volatile unsigned int*)(0x42C8010CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH4          *((volatile unsigned int*)(0x42C80110UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH5          *((volatile unsigned int*)(0x42C80114UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH6          *((volatile unsigned int*)(0x42C80118UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH7          *((volatile unsigned int*)(0x42C8011CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH8          *((volatile unsigned int*)(0x42C80120UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH9          *((volatile unsigned int*)(0x42C80124UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH10         *((volatile unsigned int*)(0x42C80128UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH11         *((volatile unsigned int*)(0x42C8012CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH12         *((volatile unsigned int*)(0x42C80130UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH13         *((volatile unsigned int*)(0x42C80134UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH14         *((volatile unsigned int*)(0x42C80138UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH15         *((volatile unsigned int*)(0x42C8013CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH16         *((volatile unsigned int*)(0x42C80140UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH17         *((volatile unsigned int*)(0x42C80144UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH18         *((volatile unsigned int*)(0x42C80148UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH19         *((volatile unsigned int*)(0x42C8014CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH20         *((volatile unsigned int*)(0x42C80150UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH21         *((volatile unsigned int*)(0x42C80154UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH22         *((volatile unsigned int*)(0x42C80158UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH23         *((volatile unsigned int*)(0x42C8015CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH24         *((volatile unsigned int*)(0x42C80160UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH25         *((volatile unsigned int*)(0x42C80164UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH26         *((volatile unsigned int*)(0x42C80168UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH27         *((volatile unsigned int*)(0x42C8016CUL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH28         *((volatile unsigned int*)(0x42C80170UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH29         *((volatile unsigned int*)(0x42C80174UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH30         *((volatile unsigned int*)(0x42C80178UL))
+#define bFM3_ETHERNET_MAC0_MHTRH_HTH31         *((volatile unsigned int*)(0x42C8017CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL0          *((volatile unsigned int*)(0x42C80180UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL1          *((volatile unsigned int*)(0x42C80184UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL2          *((volatile unsigned int*)(0x42C80188UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL3          *((volatile unsigned int*)(0x42C8018CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL4          *((volatile unsigned int*)(0x42C80190UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL5          *((volatile unsigned int*)(0x42C80194UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL6          *((volatile unsigned int*)(0x42C80198UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL7          *((volatile unsigned int*)(0x42C8019CUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL8          *((volatile unsigned int*)(0x42C801A0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL9          *((volatile unsigned int*)(0x42C801A4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL10         *((volatile unsigned int*)(0x42C801A8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL11         *((volatile unsigned int*)(0x42C801ACUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL12         *((volatile unsigned int*)(0x42C801B0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL13         *((volatile unsigned int*)(0x42C801B4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL14         *((volatile unsigned int*)(0x42C801B8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL15         *((volatile unsigned int*)(0x42C801BCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL16         *((volatile unsigned int*)(0x42C801C0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL17         *((volatile unsigned int*)(0x42C801C4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL18         *((volatile unsigned int*)(0x42C801C8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL19         *((volatile unsigned int*)(0x42C801CCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL20         *((volatile unsigned int*)(0x42C801D0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL21         *((volatile unsigned int*)(0x42C801D4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL22         *((volatile unsigned int*)(0x42C801D8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL23         *((volatile unsigned int*)(0x42C801DCUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL24         *((volatile unsigned int*)(0x42C801E0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL25         *((volatile unsigned int*)(0x42C801E4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL26         *((volatile unsigned int*)(0x42C801E8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL27         *((volatile unsigned int*)(0x42C801ECUL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL28         *((volatile unsigned int*)(0x42C801F0UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL29         *((volatile unsigned int*)(0x42C801F4UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL30         *((volatile unsigned int*)(0x42C801F8UL))
+#define bFM3_ETHERNET_MAC0_MHTRL_HTL31         *((volatile unsigned int*)(0x42C801FCUL))
+#define bFM3_ETHERNET_MAC0_GAR_GB              *((volatile unsigned int*)(0x42C80200UL))
+#define bFM3_ETHERNET_MAC0_GAR_GW              *((volatile unsigned int*)(0x42C80204UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR0             *((volatile unsigned int*)(0x42C80208UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR1             *((volatile unsigned int*)(0x42C8020CUL))
+#define bFM3_ETHERNET_MAC0_GAR_CR2             *((volatile unsigned int*)(0x42C80210UL))
+#define bFM3_ETHERNET_MAC0_GAR_CR3             *((volatile unsigned int*)(0x42C80214UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR0             *((volatile unsigned int*)(0x42C80218UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR1             *((volatile unsigned int*)(0x42C8021CUL))
+#define bFM3_ETHERNET_MAC0_GAR_GR2             *((volatile unsigned int*)(0x42C80220UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR3             *((volatile unsigned int*)(0x42C80224UL))
+#define bFM3_ETHERNET_MAC0_GAR_GR4             *((volatile unsigned int*)(0x42C80228UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA0             *((volatile unsigned int*)(0x42C8022CUL))
+#define bFM3_ETHERNET_MAC0_GAR_PA1             *((volatile unsigned int*)(0x42C80230UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA2             *((volatile unsigned int*)(0x42C80234UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA3             *((volatile unsigned int*)(0x42C80238UL))
+#define bFM3_ETHERNET_MAC0_GAR_PA4             *((volatile unsigned int*)(0x42C8023CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD0             *((volatile unsigned int*)(0x42C80280UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD1             *((volatile unsigned int*)(0x42C80284UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD2             *((volatile unsigned int*)(0x42C80288UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD3             *((volatile unsigned int*)(0x42C8028CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD4             *((volatile unsigned int*)(0x42C80290UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD5             *((volatile unsigned int*)(0x42C80294UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD6             *((volatile unsigned int*)(0x42C80298UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD7             *((volatile unsigned int*)(0x42C8029CUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD8             *((volatile unsigned int*)(0x42C802A0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD9             *((volatile unsigned int*)(0x42C802A4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD10            *((volatile unsigned int*)(0x42C802A8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD11            *((volatile unsigned int*)(0x42C802ACUL))
+#define bFM3_ETHERNET_MAC0_GDR_GD12            *((volatile unsigned int*)(0x42C802B0UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD13            *((volatile unsigned int*)(0x42C802B4UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD14            *((volatile unsigned int*)(0x42C802B8UL))
+#define bFM3_ETHERNET_MAC0_GDR_GD15            *((volatile unsigned int*)(0x42C802BCUL))
+#define bFM3_ETHERNET_MAC0_FCR_FCB_BPA         *((volatile unsigned int*)(0x42C80300UL))
+#define bFM3_ETHERNET_MAC0_FCR_TFE             *((volatile unsigned int*)(0x42C80304UL))
+#define bFM3_ETHERNET_MAC0_FCR_RFE             *((volatile unsigned int*)(0x42C80308UL))
+#define bFM3_ETHERNET_MAC0_FCR_UP              *((volatile unsigned int*)(0x42C8030CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT0            *((volatile unsigned int*)(0x42C80310UL))
+#define bFM3_ETHERNET_MAC0_FCR_PLT1            *((volatile unsigned int*)(0x42C80314UL))
+#define bFM3_ETHERNET_MAC0_FCR_DZPQ            *((volatile unsigned int*)(0x42C8031CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT0             *((volatile unsigned int*)(0x42C80340UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT1             *((volatile unsigned int*)(0x42C80344UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT2             *((volatile unsigned int*)(0x42C80348UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT3             *((volatile unsigned int*)(0x42C8034CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT4             *((volatile unsigned int*)(0x42C80350UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT5             *((volatile unsigned int*)(0x42C80354UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT6             *((volatile unsigned int*)(0x42C80358UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT7             *((volatile unsigned int*)(0x42C8035CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT8             *((volatile unsigned int*)(0x42C80360UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT9             *((volatile unsigned int*)(0x42C80364UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT10            *((volatile unsigned int*)(0x42C80368UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT11            *((volatile unsigned int*)(0x42C8036CUL))
+#define bFM3_ETHERNET_MAC0_FCR_PT12            *((volatile unsigned int*)(0x42C80370UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT13            *((volatile unsigned int*)(0x42C80374UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT14            *((volatile unsigned int*)(0x42C80378UL))
+#define bFM3_ETHERNET_MAC0_FCR_PT15            *((volatile unsigned int*)(0x42C8037CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL0             *((volatile unsigned int*)(0x42C80380UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL1             *((volatile unsigned int*)(0x42C80384UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL2             *((volatile unsigned int*)(0x42C80388UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL3             *((volatile unsigned int*)(0x42C8038CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL4             *((volatile unsigned int*)(0x42C80390UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL5             *((volatile unsigned int*)(0x42C80394UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL6             *((volatile unsigned int*)(0x42C80398UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL7             *((volatile unsigned int*)(0x42C8039CUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL8             *((volatile unsigned int*)(0x42C803A0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL9             *((volatile unsigned int*)(0x42C803A4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL10            *((volatile unsigned int*)(0x42C803A8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL11            *((volatile unsigned int*)(0x42C803ACUL))
+#define bFM3_ETHERNET_MAC0_VTR_VL12            *((volatile unsigned int*)(0x42C803B0UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL13            *((volatile unsigned int*)(0x42C803B4UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL14            *((volatile unsigned int*)(0x42C803B8UL))
+#define bFM3_ETHERNET_MAC0_VTR_VL15            *((volatile unsigned int*)(0x42C803BCUL))
+#define bFM3_ETHERNET_MAC0_VTR_ETV             *((volatile unsigned int*)(0x42C803C0UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42C80500UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42C80504UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42C80508UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42C8050CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42C80510UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42C80514UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42C80518UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42C8051CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42C80520UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42C80524UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42C80528UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42C8052CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42C80530UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42C80534UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42C80538UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42C8053CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42C80540UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42C80544UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42C80548UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42C8054CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42C80550UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42C80554UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42C80558UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42C8055CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42C80560UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42C80564UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42C80568UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42C8056CUL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42C80570UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42C80574UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42C80578UL))
+#define bFM3_ETHERNET_MAC0_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42C8057CUL))
+#define bFM3_ETHERNET_MAC0_PMTR_PD             *((volatile unsigned int*)(0x42C80580UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPE            *((volatile unsigned int*)(0x42C80584UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WFE            *((volatile unsigned int*)(0x42C80588UL))
+#define bFM3_ETHERNET_MAC0_PMTR_MPR            *((volatile unsigned int*)(0x42C80594UL))
+#define bFM3_ETHERNET_MAC0_PMTR_WPR            *((volatile unsigned int*)(0x42C80598UL))
+#define bFM3_ETHERNET_MAC0_PMTR_GU             *((volatile unsigned int*)(0x42C805A4UL))
+#define bFM3_ETHERNET_MAC0_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42C805FCUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42C80600UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42C80604UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42C80608UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42C8060CUL))
+#define bFM3_ETHERNET_MAC0_LPICSR_TLPIST       *((volatile unsigned int*)(0x42C80620UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_RLPIST       *((volatile unsigned int*)(0x42C80624UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPIEN        *((volatile unsigned int*)(0x42C80640UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLS          *((volatile unsigned int*)(0x42C80644UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_PLSEN        *((volatile unsigned int*)(0x42C80648UL))
+#define bFM3_ETHERNET_MAC0_LPICSR_LPITXA       *((volatile unsigned int*)(0x42C8064CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT0         *((volatile unsigned int*)(0x42C80680UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT1         *((volatile unsigned int*)(0x42C80684UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT2         *((volatile unsigned int*)(0x42C80688UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT3         *((volatile unsigned int*)(0x42C8068CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT4         *((volatile unsigned int*)(0x42C80690UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT5         *((volatile unsigned int*)(0x42C80694UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT6         *((volatile unsigned int*)(0x42C80698UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT7         *((volatile unsigned int*)(0x42C8069CUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT8         *((volatile unsigned int*)(0x42C806A0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT9         *((volatile unsigned int*)(0x42C806A4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT10        *((volatile unsigned int*)(0x42C806A8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT11        *((volatile unsigned int*)(0x42C806ACUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT12        *((volatile unsigned int*)(0x42C806B0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT13        *((volatile unsigned int*)(0x42C806B4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT14        *((volatile unsigned int*)(0x42C806B8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_TWT15        *((volatile unsigned int*)(0x42C806BCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT0         *((volatile unsigned int*)(0x42C806C0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT1         *((volatile unsigned int*)(0x42C806C4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT2         *((volatile unsigned int*)(0x42C806C8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT3         *((volatile unsigned int*)(0x42C806CCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT4         *((volatile unsigned int*)(0x42C806D0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT5         *((volatile unsigned int*)(0x42C806D4UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT6         *((volatile unsigned int*)(0x42C806D8UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT7         *((volatile unsigned int*)(0x42C806DCUL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT8         *((volatile unsigned int*)(0x42C806E0UL))
+#define bFM3_ETHERNET_MAC0_LPITCR_LIT9         *((volatile unsigned int*)(0x42C806E4UL))
+#define bFM3_ETHERNET_MAC0_ISR_RGIS            *((volatile unsigned int*)(0x42C80700UL))
+#define bFM3_ETHERNET_MAC0_ISR_PIS             *((volatile unsigned int*)(0x42C8070CUL))
+#define bFM3_ETHERNET_MAC0_ISR_MIS             *((volatile unsigned int*)(0x42C80710UL))
+#define bFM3_ETHERNET_MAC0_ISR_RIS             *((volatile unsigned int*)(0x42C80714UL))
+#define bFM3_ETHERNET_MAC0_ISR_TIS             *((volatile unsigned int*)(0x42C80718UL))
+#define bFM3_ETHERNET_MAC0_ISR_COIS            *((volatile unsigned int*)(0x42C8071CUL))
+#define bFM3_ETHERNET_MAC0_ISR_TSIS            *((volatile unsigned int*)(0x42C80724UL))
+#define bFM3_ETHERNET_MAC0_ISR_LPIIS           *((volatile unsigned int*)(0x42C80728UL))
+#define bFM3_ETHERNET_MAC0_IMR_RGIM            *((volatile unsigned int*)(0x42C80780UL))
+#define bFM3_ETHERNET_MAC0_IMR_PIM             *((volatile unsigned int*)(0x42C8078CUL))
+#define bFM3_ETHERNET_MAC0_IMR_TSIM            *((volatile unsigned int*)(0x42C80794UL))
+#define bFM3_ETHERNET_MAC0_IMR_LPIIM           *((volatile unsigned int*)(0x42C80798UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A32           *((volatile unsigned int*)(0x42C80800UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A33           *((volatile unsigned int*)(0x42C80804UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A34           *((volatile unsigned int*)(0x42C80808UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A35           *((volatile unsigned int*)(0x42C8080CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A36           *((volatile unsigned int*)(0x42C80810UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A37           *((volatile unsigned int*)(0x42C80814UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A38           *((volatile unsigned int*)(0x42C80818UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A39           *((volatile unsigned int*)(0x42C8081CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A40           *((volatile unsigned int*)(0x42C80820UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A41           *((volatile unsigned int*)(0x42C80824UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A42           *((volatile unsigned int*)(0x42C80828UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A43           *((volatile unsigned int*)(0x42C8082CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A44           *((volatile unsigned int*)(0x42C80830UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A45           *((volatile unsigned int*)(0x42C80834UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A46           *((volatile unsigned int*)(0x42C80838UL))
+#define bFM3_ETHERNET_MAC0_MAR0H_A47           *((volatile unsigned int*)(0x42C8083CUL))
+#define bFM3_ETHERNET_MAC0_MAR0H_MO            *((volatile unsigned int*)(0x42C8087CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A0            *((volatile unsigned int*)(0x42C80880UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A1            *((volatile unsigned int*)(0x42C80884UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A2            *((volatile unsigned int*)(0x42C80888UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A3            *((volatile unsigned int*)(0x42C8088CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A4            *((volatile unsigned int*)(0x42C80890UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A5            *((volatile unsigned int*)(0x42C80894UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A6            *((volatile unsigned int*)(0x42C80898UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A7            *((volatile unsigned int*)(0x42C8089CUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A8            *((volatile unsigned int*)(0x42C808A0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A9            *((volatile unsigned int*)(0x42C808A4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A10           *((volatile unsigned int*)(0x42C808A8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A11           *((volatile unsigned int*)(0x42C808ACUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A12           *((volatile unsigned int*)(0x42C808B0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A13           *((volatile unsigned int*)(0x42C808B4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A14           *((volatile unsigned int*)(0x42C808B8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A15           *((volatile unsigned int*)(0x42C808BCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A16           *((volatile unsigned int*)(0x42C808C0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A17           *((volatile unsigned int*)(0x42C808C4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A18           *((volatile unsigned int*)(0x42C808C8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A19           *((volatile unsigned int*)(0x42C808CCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A20           *((volatile unsigned int*)(0x42C808D0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A21           *((volatile unsigned int*)(0x42C808D4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A22           *((volatile unsigned int*)(0x42C808D8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A23           *((volatile unsigned int*)(0x42C808DCUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A24           *((volatile unsigned int*)(0x42C808E0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A25           *((volatile unsigned int*)(0x42C808E4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A26           *((volatile unsigned int*)(0x42C808E8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A27           *((volatile unsigned int*)(0x42C808ECUL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A28           *((volatile unsigned int*)(0x42C808F0UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A29           *((volatile unsigned int*)(0x42C808F4UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A30           *((volatile unsigned int*)(0x42C808F8UL))
+#define bFM3_ETHERNET_MAC0_MAR0L_A31           *((volatile unsigned int*)(0x42C808FCUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A32           *((volatile unsigned int*)(0x42C80900UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A33           *((volatile unsigned int*)(0x42C80904UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A34           *((volatile unsigned int*)(0x42C80908UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A35           *((volatile unsigned int*)(0x42C8090CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A36           *((volatile unsigned int*)(0x42C80910UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A37           *((volatile unsigned int*)(0x42C80914UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A38           *((volatile unsigned int*)(0x42C80918UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A39           *((volatile unsigned int*)(0x42C8091CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A40           *((volatile unsigned int*)(0x42C80920UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A41           *((volatile unsigned int*)(0x42C80924UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A42           *((volatile unsigned int*)(0x42C80928UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A43           *((volatile unsigned int*)(0x42C8092CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A44           *((volatile unsigned int*)(0x42C80930UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A45           *((volatile unsigned int*)(0x42C80934UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A46           *((volatile unsigned int*)(0x42C80938UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_A47           *((volatile unsigned int*)(0x42C8093CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC0          *((volatile unsigned int*)(0x42C80960UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC1          *((volatile unsigned int*)(0x42C80964UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC2          *((volatile unsigned int*)(0x42C80968UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC3          *((volatile unsigned int*)(0x42C8096CUL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC4          *((volatile unsigned int*)(0x42C80970UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_MBC5          *((volatile unsigned int*)(0x42C80974UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_SA            *((volatile unsigned int*)(0x42C80978UL))
+#define bFM3_ETHERNET_MAC0_MAR1H_AE            *((volatile unsigned int*)(0x42C8097CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A0            *((volatile unsigned int*)(0x42C80980UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A1            *((volatile unsigned int*)(0x42C80984UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A2            *((volatile unsigned int*)(0x42C80988UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A3            *((volatile unsigned int*)(0x42C8098CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A4            *((volatile unsigned int*)(0x42C80990UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A5            *((volatile unsigned int*)(0x42C80994UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A6            *((volatile unsigned int*)(0x42C80998UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A7            *((volatile unsigned int*)(0x42C8099CUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A8            *((volatile unsigned int*)(0x42C809A0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A9            *((volatile unsigned int*)(0x42C809A4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A10           *((volatile unsigned int*)(0x42C809A8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A11           *((volatile unsigned int*)(0x42C809ACUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A12           *((volatile unsigned int*)(0x42C809B0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A13           *((volatile unsigned int*)(0x42C809B4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A14           *((volatile unsigned int*)(0x42C809B8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A15           *((volatile unsigned int*)(0x42C809BCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A16           *((volatile unsigned int*)(0x42C809C0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A17           *((volatile unsigned int*)(0x42C809C4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A18           *((volatile unsigned int*)(0x42C809C8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A19           *((volatile unsigned int*)(0x42C809CCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A20           *((volatile unsigned int*)(0x42C809D0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A21           *((volatile unsigned int*)(0x42C809D4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A22           *((volatile unsigned int*)(0x42C809D8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A23           *((volatile unsigned int*)(0x42C809DCUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A24           *((volatile unsigned int*)(0x42C809E0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A25           *((volatile unsigned int*)(0x42C809E4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A26           *((volatile unsigned int*)(0x42C809E8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A27           *((volatile unsigned int*)(0x42C809ECUL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A28           *((volatile unsigned int*)(0x42C809F0UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A29           *((volatile unsigned int*)(0x42C809F4UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A30           *((volatile unsigned int*)(0x42C809F8UL))
+#define bFM3_ETHERNET_MAC0_MAR1L_A31           *((volatile unsigned int*)(0x42C809FCUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A32           *((volatile unsigned int*)(0x42C80A00UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A33           *((volatile unsigned int*)(0x42C80A04UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A34           *((volatile unsigned int*)(0x42C80A08UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A35           *((volatile unsigned int*)(0x42C80A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A36           *((volatile unsigned int*)(0x42C80A10UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A37           *((volatile unsigned int*)(0x42C80A14UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A38           *((volatile unsigned int*)(0x42C80A18UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A39           *((volatile unsigned int*)(0x42C80A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A40           *((volatile unsigned int*)(0x42C80A20UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A41           *((volatile unsigned int*)(0x42C80A24UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A42           *((volatile unsigned int*)(0x42C80A28UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A43           *((volatile unsigned int*)(0x42C80A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A44           *((volatile unsigned int*)(0x42C80A30UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A45           *((volatile unsigned int*)(0x42C80A34UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A46           *((volatile unsigned int*)(0x42C80A38UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_A47           *((volatile unsigned int*)(0x42C80A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC0          *((volatile unsigned int*)(0x42C80A60UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC1          *((volatile unsigned int*)(0x42C80A64UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC2          *((volatile unsigned int*)(0x42C80A68UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC3          *((volatile unsigned int*)(0x42C80A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC4          *((volatile unsigned int*)(0x42C80A70UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_MBC5          *((volatile unsigned int*)(0x42C80A74UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_SA            *((volatile unsigned int*)(0x42C80A78UL))
+#define bFM3_ETHERNET_MAC0_MAR2H_AE            *((volatile unsigned int*)(0x42C80A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A0            *((volatile unsigned int*)(0x42C80A80UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A1            *((volatile unsigned int*)(0x42C80A84UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A2            *((volatile unsigned int*)(0x42C80A88UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A3            *((volatile unsigned int*)(0x42C80A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A4            *((volatile unsigned int*)(0x42C80A90UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A5            *((volatile unsigned int*)(0x42C80A94UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A6            *((volatile unsigned int*)(0x42C80A98UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A7            *((volatile unsigned int*)(0x42C80A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A8            *((volatile unsigned int*)(0x42C80AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A9            *((volatile unsigned int*)(0x42C80AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A10           *((volatile unsigned int*)(0x42C80AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A11           *((volatile unsigned int*)(0x42C80AACUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A12           *((volatile unsigned int*)(0x42C80AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A13           *((volatile unsigned int*)(0x42C80AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A14           *((volatile unsigned int*)(0x42C80AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A15           *((volatile unsigned int*)(0x42C80ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A16           *((volatile unsigned int*)(0x42C80AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A17           *((volatile unsigned int*)(0x42C80AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A18           *((volatile unsigned int*)(0x42C80AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A19           *((volatile unsigned int*)(0x42C80ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A20           *((volatile unsigned int*)(0x42C80AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A21           *((volatile unsigned int*)(0x42C80AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A22           *((volatile unsigned int*)(0x42C80AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A23           *((volatile unsigned int*)(0x42C80ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A24           *((volatile unsigned int*)(0x42C80AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A25           *((volatile unsigned int*)(0x42C80AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A26           *((volatile unsigned int*)(0x42C80AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A27           *((volatile unsigned int*)(0x42C80AECUL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A28           *((volatile unsigned int*)(0x42C80AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A29           *((volatile unsigned int*)(0x42C80AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A30           *((volatile unsigned int*)(0x42C80AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR2L_A31           *((volatile unsigned int*)(0x42C80AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A32           *((volatile unsigned int*)(0x42C80B00UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A33           *((volatile unsigned int*)(0x42C80B04UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A34           *((volatile unsigned int*)(0x42C80B08UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A35           *((volatile unsigned int*)(0x42C80B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A36           *((volatile unsigned int*)(0x42C80B10UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A37           *((volatile unsigned int*)(0x42C80B14UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A38           *((volatile unsigned int*)(0x42C80B18UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A39           *((volatile unsigned int*)(0x42C80B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A40           *((volatile unsigned int*)(0x42C80B20UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A41           *((volatile unsigned int*)(0x42C80B24UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A42           *((volatile unsigned int*)(0x42C80B28UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A43           *((volatile unsigned int*)(0x42C80B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A44           *((volatile unsigned int*)(0x42C80B30UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A45           *((volatile unsigned int*)(0x42C80B34UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A46           *((volatile unsigned int*)(0x42C80B38UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_A47           *((volatile unsigned int*)(0x42C80B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC0          *((volatile unsigned int*)(0x42C80B60UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC1          *((volatile unsigned int*)(0x42C80B64UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC2          *((volatile unsigned int*)(0x42C80B68UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC3          *((volatile unsigned int*)(0x42C80B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC4          *((volatile unsigned int*)(0x42C80B70UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_MBC5          *((volatile unsigned int*)(0x42C80B74UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_SA            *((volatile unsigned int*)(0x42C80B78UL))
+#define bFM3_ETHERNET_MAC0_MAR3H_AE            *((volatile unsigned int*)(0x42C80B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A0            *((volatile unsigned int*)(0x42C80B80UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A1            *((volatile unsigned int*)(0x42C80B84UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A2            *((volatile unsigned int*)(0x42C80B88UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A3            *((volatile unsigned int*)(0x42C80B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A4            *((volatile unsigned int*)(0x42C80B90UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A5            *((volatile unsigned int*)(0x42C80B94UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A6            *((volatile unsigned int*)(0x42C80B98UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A7            *((volatile unsigned int*)(0x42C80B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A8            *((volatile unsigned int*)(0x42C80BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A9            *((volatile unsigned int*)(0x42C80BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A10           *((volatile unsigned int*)(0x42C80BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A11           *((volatile unsigned int*)(0x42C80BACUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A12           *((volatile unsigned int*)(0x42C80BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A13           *((volatile unsigned int*)(0x42C80BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A14           *((volatile unsigned int*)(0x42C80BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A15           *((volatile unsigned int*)(0x42C80BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A16           *((volatile unsigned int*)(0x42C80BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A17           *((volatile unsigned int*)(0x42C80BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A18           *((volatile unsigned int*)(0x42C80BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A19           *((volatile unsigned int*)(0x42C80BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A20           *((volatile unsigned int*)(0x42C80BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A21           *((volatile unsigned int*)(0x42C80BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A22           *((volatile unsigned int*)(0x42C80BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A23           *((volatile unsigned int*)(0x42C80BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A24           *((volatile unsigned int*)(0x42C80BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A25           *((volatile unsigned int*)(0x42C80BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A26           *((volatile unsigned int*)(0x42C80BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A27           *((volatile unsigned int*)(0x42C80BECUL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A28           *((volatile unsigned int*)(0x42C80BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A29           *((volatile unsigned int*)(0x42C80BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A30           *((volatile unsigned int*)(0x42C80BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR3L_A31           *((volatile unsigned int*)(0x42C80BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A32           *((volatile unsigned int*)(0x42C80C00UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A33           *((volatile unsigned int*)(0x42C80C04UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A34           *((volatile unsigned int*)(0x42C80C08UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A35           *((volatile unsigned int*)(0x42C80C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A36           *((volatile unsigned int*)(0x42C80C10UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A37           *((volatile unsigned int*)(0x42C80C14UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A38           *((volatile unsigned int*)(0x42C80C18UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A39           *((volatile unsigned int*)(0x42C80C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A40           *((volatile unsigned int*)(0x42C80C20UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A41           *((volatile unsigned int*)(0x42C80C24UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A42           *((volatile unsigned int*)(0x42C80C28UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A43           *((volatile unsigned int*)(0x42C80C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A44           *((volatile unsigned int*)(0x42C80C30UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A45           *((volatile unsigned int*)(0x42C80C34UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A46           *((volatile unsigned int*)(0x42C80C38UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_A47           *((volatile unsigned int*)(0x42C80C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC0          *((volatile unsigned int*)(0x42C80C60UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC1          *((volatile unsigned int*)(0x42C80C64UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC2          *((volatile unsigned int*)(0x42C80C68UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC3          *((volatile unsigned int*)(0x42C80C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC4          *((volatile unsigned int*)(0x42C80C70UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_MBC5          *((volatile unsigned int*)(0x42C80C74UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_SA            *((volatile unsigned int*)(0x42C80C78UL))
+#define bFM3_ETHERNET_MAC0_MAR4H_AE            *((volatile unsigned int*)(0x42C80C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A0            *((volatile unsigned int*)(0x42C80C80UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A1            *((volatile unsigned int*)(0x42C80C84UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A2            *((volatile unsigned int*)(0x42C80C88UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A3            *((volatile unsigned int*)(0x42C80C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A4            *((volatile unsigned int*)(0x42C80C90UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A5            *((volatile unsigned int*)(0x42C80C94UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A6            *((volatile unsigned int*)(0x42C80C98UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A7            *((volatile unsigned int*)(0x42C80C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A8            *((volatile unsigned int*)(0x42C80CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A9            *((volatile unsigned int*)(0x42C80CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A10           *((volatile unsigned int*)(0x42C80CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A11           *((volatile unsigned int*)(0x42C80CACUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A12           *((volatile unsigned int*)(0x42C80CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A13           *((volatile unsigned int*)(0x42C80CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A14           *((volatile unsigned int*)(0x42C80CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A15           *((volatile unsigned int*)(0x42C80CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A16           *((volatile unsigned int*)(0x42C80CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A17           *((volatile unsigned int*)(0x42C80CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A18           *((volatile unsigned int*)(0x42C80CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A19           *((volatile unsigned int*)(0x42C80CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A20           *((volatile unsigned int*)(0x42C80CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A21           *((volatile unsigned int*)(0x42C80CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A22           *((volatile unsigned int*)(0x42C80CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A23           *((volatile unsigned int*)(0x42C80CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A24           *((volatile unsigned int*)(0x42C80CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A25           *((volatile unsigned int*)(0x42C80CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A26           *((volatile unsigned int*)(0x42C80CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A27           *((volatile unsigned int*)(0x42C80CECUL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A28           *((volatile unsigned int*)(0x42C80CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A29           *((volatile unsigned int*)(0x42C80CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A30           *((volatile unsigned int*)(0x42C80CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR4L_A31           *((volatile unsigned int*)(0x42C80CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A32           *((volatile unsigned int*)(0x42C80D00UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A33           *((volatile unsigned int*)(0x42C80D04UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A34           *((volatile unsigned int*)(0x42C80D08UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A35           *((volatile unsigned int*)(0x42C80D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A36           *((volatile unsigned int*)(0x42C80D10UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A37           *((volatile unsigned int*)(0x42C80D14UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A38           *((volatile unsigned int*)(0x42C80D18UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A39           *((volatile unsigned int*)(0x42C80D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A40           *((volatile unsigned int*)(0x42C80D20UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A41           *((volatile unsigned int*)(0x42C80D24UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A42           *((volatile unsigned int*)(0x42C80D28UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A43           *((volatile unsigned int*)(0x42C80D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A44           *((volatile unsigned int*)(0x42C80D30UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A45           *((volatile unsigned int*)(0x42C80D34UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A46           *((volatile unsigned int*)(0x42C80D38UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_A47           *((volatile unsigned int*)(0x42C80D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC0          *((volatile unsigned int*)(0x42C80D60UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC1          *((volatile unsigned int*)(0x42C80D64UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC2          *((volatile unsigned int*)(0x42C80D68UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC3          *((volatile unsigned int*)(0x42C80D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC4          *((volatile unsigned int*)(0x42C80D70UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_MBC5          *((volatile unsigned int*)(0x42C80D74UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_SA            *((volatile unsigned int*)(0x42C80D78UL))
+#define bFM3_ETHERNET_MAC0_MAR5H_AE            *((volatile unsigned int*)(0x42C80D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A0            *((volatile unsigned int*)(0x42C80D80UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A1            *((volatile unsigned int*)(0x42C80D84UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A2            *((volatile unsigned int*)(0x42C80D88UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A3            *((volatile unsigned int*)(0x42C80D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A4            *((volatile unsigned int*)(0x42C80D90UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A5            *((volatile unsigned int*)(0x42C80D94UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A6            *((volatile unsigned int*)(0x42C80D98UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A7            *((volatile unsigned int*)(0x42C80D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A8            *((volatile unsigned int*)(0x42C80DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A9            *((volatile unsigned int*)(0x42C80DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A10           *((volatile unsigned int*)(0x42C80DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A11           *((volatile unsigned int*)(0x42C80DACUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A12           *((volatile unsigned int*)(0x42C80DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A13           *((volatile unsigned int*)(0x42C80DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A14           *((volatile unsigned int*)(0x42C80DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A15           *((volatile unsigned int*)(0x42C80DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A16           *((volatile unsigned int*)(0x42C80DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A17           *((volatile unsigned int*)(0x42C80DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A18           *((volatile unsigned int*)(0x42C80DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A19           *((volatile unsigned int*)(0x42C80DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A20           *((volatile unsigned int*)(0x42C80DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A21           *((volatile unsigned int*)(0x42C80DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A22           *((volatile unsigned int*)(0x42C80DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A23           *((volatile unsigned int*)(0x42C80DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A24           *((volatile unsigned int*)(0x42C80DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A25           *((volatile unsigned int*)(0x42C80DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A26           *((volatile unsigned int*)(0x42C80DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A27           *((volatile unsigned int*)(0x42C80DECUL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A28           *((volatile unsigned int*)(0x42C80DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A29           *((volatile unsigned int*)(0x42C80DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A30           *((volatile unsigned int*)(0x42C80DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR5L_A31           *((volatile unsigned int*)(0x42C80DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A32           *((volatile unsigned int*)(0x42C80E00UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A33           *((volatile unsigned int*)(0x42C80E04UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A34           *((volatile unsigned int*)(0x42C80E08UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A35           *((volatile unsigned int*)(0x42C80E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A36           *((volatile unsigned int*)(0x42C80E10UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A37           *((volatile unsigned int*)(0x42C80E14UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A38           *((volatile unsigned int*)(0x42C80E18UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A39           *((volatile unsigned int*)(0x42C80E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A40           *((volatile unsigned int*)(0x42C80E20UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A41           *((volatile unsigned int*)(0x42C80E24UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A42           *((volatile unsigned int*)(0x42C80E28UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A43           *((volatile unsigned int*)(0x42C80E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A44           *((volatile unsigned int*)(0x42C80E30UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A45           *((volatile unsigned int*)(0x42C80E34UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A46           *((volatile unsigned int*)(0x42C80E38UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_A47           *((volatile unsigned int*)(0x42C80E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC0          *((volatile unsigned int*)(0x42C80E60UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC1          *((volatile unsigned int*)(0x42C80E64UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC2          *((volatile unsigned int*)(0x42C80E68UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC3          *((volatile unsigned int*)(0x42C80E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC4          *((volatile unsigned int*)(0x42C80E70UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_MBC5          *((volatile unsigned int*)(0x42C80E74UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_SA            *((volatile unsigned int*)(0x42C80E78UL))
+#define bFM3_ETHERNET_MAC0_MAR6H_AE            *((volatile unsigned int*)(0x42C80E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A0            *((volatile unsigned int*)(0x42C80E80UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A1            *((volatile unsigned int*)(0x42C80E84UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A2            *((volatile unsigned int*)(0x42C80E88UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A3            *((volatile unsigned int*)(0x42C80E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A4            *((volatile unsigned int*)(0x42C80E90UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A5            *((volatile unsigned int*)(0x42C80E94UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A6            *((volatile unsigned int*)(0x42C80E98UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A7            *((volatile unsigned int*)(0x42C80E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A8            *((volatile unsigned int*)(0x42C80EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A9            *((volatile unsigned int*)(0x42C80EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A10           *((volatile unsigned int*)(0x42C80EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A11           *((volatile unsigned int*)(0x42C80EACUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A12           *((volatile unsigned int*)(0x42C80EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A13           *((volatile unsigned int*)(0x42C80EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A14           *((volatile unsigned int*)(0x42C80EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A15           *((volatile unsigned int*)(0x42C80EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A16           *((volatile unsigned int*)(0x42C80EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A17           *((volatile unsigned int*)(0x42C80EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A18           *((volatile unsigned int*)(0x42C80EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A19           *((volatile unsigned int*)(0x42C80ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A20           *((volatile unsigned int*)(0x42C80ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A21           *((volatile unsigned int*)(0x42C80ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A22           *((volatile unsigned int*)(0x42C80ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A23           *((volatile unsigned int*)(0x42C80EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A24           *((volatile unsigned int*)(0x42C80EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A25           *((volatile unsigned int*)(0x42C80EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A26           *((volatile unsigned int*)(0x42C80EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A27           *((volatile unsigned int*)(0x42C80EECUL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A28           *((volatile unsigned int*)(0x42C80EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A29           *((volatile unsigned int*)(0x42C80EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A30           *((volatile unsigned int*)(0x42C80EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR6L_A31           *((volatile unsigned int*)(0x42C80EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A32           *((volatile unsigned int*)(0x42C80F00UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A33           *((volatile unsigned int*)(0x42C80F04UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A34           *((volatile unsigned int*)(0x42C80F08UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A35           *((volatile unsigned int*)(0x42C80F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A36           *((volatile unsigned int*)(0x42C80F10UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A37           *((volatile unsigned int*)(0x42C80F14UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A38           *((volatile unsigned int*)(0x42C80F18UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A39           *((volatile unsigned int*)(0x42C80F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A40           *((volatile unsigned int*)(0x42C80F20UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A41           *((volatile unsigned int*)(0x42C80F24UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A42           *((volatile unsigned int*)(0x42C80F28UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A43           *((volatile unsigned int*)(0x42C80F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A44           *((volatile unsigned int*)(0x42C80F30UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A45           *((volatile unsigned int*)(0x42C80F34UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A46           *((volatile unsigned int*)(0x42C80F38UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_A47           *((volatile unsigned int*)(0x42C80F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC0          *((volatile unsigned int*)(0x42C80F60UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC1          *((volatile unsigned int*)(0x42C80F64UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC2          *((volatile unsigned int*)(0x42C80F68UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC3          *((volatile unsigned int*)(0x42C80F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC4          *((volatile unsigned int*)(0x42C80F70UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_MBC5          *((volatile unsigned int*)(0x42C80F74UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_SA            *((volatile unsigned int*)(0x42C80F78UL))
+#define bFM3_ETHERNET_MAC0_MAR7H_AE            *((volatile unsigned int*)(0x42C80F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A0            *((volatile unsigned int*)(0x42C80F80UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A1            *((volatile unsigned int*)(0x42C80F84UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A2            *((volatile unsigned int*)(0x42C80F88UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A3            *((volatile unsigned int*)(0x42C80F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A4            *((volatile unsigned int*)(0x42C80F90UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A5            *((volatile unsigned int*)(0x42C80F94UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A6            *((volatile unsigned int*)(0x42C80F98UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A7            *((volatile unsigned int*)(0x42C80F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A8            *((volatile unsigned int*)(0x42C80FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A9            *((volatile unsigned int*)(0x42C80FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A10           *((volatile unsigned int*)(0x42C80FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A11           *((volatile unsigned int*)(0x42C80FACUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A12           *((volatile unsigned int*)(0x42C80FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A13           *((volatile unsigned int*)(0x42C80FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A14           *((volatile unsigned int*)(0x42C80FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A15           *((volatile unsigned int*)(0x42C80FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A16           *((volatile unsigned int*)(0x42C80FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A17           *((volatile unsigned int*)(0x42C80FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A18           *((volatile unsigned int*)(0x42C80FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A19           *((volatile unsigned int*)(0x42C80FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A20           *((volatile unsigned int*)(0x42C80FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A21           *((volatile unsigned int*)(0x42C80FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A22           *((volatile unsigned int*)(0x42C80FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A23           *((volatile unsigned int*)(0x42C80FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A24           *((volatile unsigned int*)(0x42C80FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A25           *((volatile unsigned int*)(0x42C80FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A26           *((volatile unsigned int*)(0x42C80FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A27           *((volatile unsigned int*)(0x42C80FECUL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A28           *((volatile unsigned int*)(0x42C80FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A29           *((volatile unsigned int*)(0x42C80FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A30           *((volatile unsigned int*)(0x42C80FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR7L_A31           *((volatile unsigned int*)(0x42C80FFCUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A32           *((volatile unsigned int*)(0x42C81000UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A33           *((volatile unsigned int*)(0x42C81004UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A34           *((volatile unsigned int*)(0x42C81008UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A35           *((volatile unsigned int*)(0x42C8100CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A36           *((volatile unsigned int*)(0x42C81010UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A37           *((volatile unsigned int*)(0x42C81014UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A38           *((volatile unsigned int*)(0x42C81018UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A39           *((volatile unsigned int*)(0x42C8101CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A40           *((volatile unsigned int*)(0x42C81020UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A41           *((volatile unsigned int*)(0x42C81024UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A42           *((volatile unsigned int*)(0x42C81028UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A43           *((volatile unsigned int*)(0x42C8102CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A44           *((volatile unsigned int*)(0x42C81030UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A45           *((volatile unsigned int*)(0x42C81034UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A46           *((volatile unsigned int*)(0x42C81038UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_A47           *((volatile unsigned int*)(0x42C8103CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC0          *((volatile unsigned int*)(0x42C81060UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC1          *((volatile unsigned int*)(0x42C81064UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC2          *((volatile unsigned int*)(0x42C81068UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC3          *((volatile unsigned int*)(0x42C8106CUL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC4          *((volatile unsigned int*)(0x42C81070UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_MBC5          *((volatile unsigned int*)(0x42C81074UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_SA            *((volatile unsigned int*)(0x42C81078UL))
+#define bFM3_ETHERNET_MAC0_MAR8H_AE            *((volatile unsigned int*)(0x42C8107CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A0            *((volatile unsigned int*)(0x42C81080UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A1            *((volatile unsigned int*)(0x42C81084UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A2            *((volatile unsigned int*)(0x42C81088UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A3            *((volatile unsigned int*)(0x42C8108CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A4            *((volatile unsigned int*)(0x42C81090UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A5            *((volatile unsigned int*)(0x42C81094UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A6            *((volatile unsigned int*)(0x42C81098UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A7            *((volatile unsigned int*)(0x42C8109CUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A8            *((volatile unsigned int*)(0x42C810A0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A9            *((volatile unsigned int*)(0x42C810A4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A10           *((volatile unsigned int*)(0x42C810A8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A11           *((volatile unsigned int*)(0x42C810ACUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A12           *((volatile unsigned int*)(0x42C810B0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A13           *((volatile unsigned int*)(0x42C810B4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A14           *((volatile unsigned int*)(0x42C810B8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A15           *((volatile unsigned int*)(0x42C810BCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A16           *((volatile unsigned int*)(0x42C810C0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A17           *((volatile unsigned int*)(0x42C810C4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A18           *((volatile unsigned int*)(0x42C810C8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A19           *((volatile unsigned int*)(0x42C810CCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A20           *((volatile unsigned int*)(0x42C810D0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A21           *((volatile unsigned int*)(0x42C810D4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A22           *((volatile unsigned int*)(0x42C810D8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A23           *((volatile unsigned int*)(0x42C810DCUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A24           *((volatile unsigned int*)(0x42C810E0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A25           *((volatile unsigned int*)(0x42C810E4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A26           *((volatile unsigned int*)(0x42C810E8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A27           *((volatile unsigned int*)(0x42C810ECUL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A28           *((volatile unsigned int*)(0x42C810F0UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A29           *((volatile unsigned int*)(0x42C810F4UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A30           *((volatile unsigned int*)(0x42C810F8UL))
+#define bFM3_ETHERNET_MAC0_MAR8L_A31           *((volatile unsigned int*)(0x42C810FCUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A32           *((volatile unsigned int*)(0x42C81100UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A33           *((volatile unsigned int*)(0x42C81104UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A34           *((volatile unsigned int*)(0x42C81108UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A35           *((volatile unsigned int*)(0x42C8110CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A36           *((volatile unsigned int*)(0x42C81110UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A37           *((volatile unsigned int*)(0x42C81114UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A38           *((volatile unsigned int*)(0x42C81118UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A39           *((volatile unsigned int*)(0x42C8111CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A40           *((volatile unsigned int*)(0x42C81120UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A41           *((volatile unsigned int*)(0x42C81124UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A42           *((volatile unsigned int*)(0x42C81128UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A43           *((volatile unsigned int*)(0x42C8112CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A44           *((volatile unsigned int*)(0x42C81130UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A45           *((volatile unsigned int*)(0x42C81134UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A46           *((volatile unsigned int*)(0x42C81138UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_A47           *((volatile unsigned int*)(0x42C8113CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC0          *((volatile unsigned int*)(0x42C81160UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC1          *((volatile unsigned int*)(0x42C81164UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC2          *((volatile unsigned int*)(0x42C81168UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC3          *((volatile unsigned int*)(0x42C8116CUL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC4          *((volatile unsigned int*)(0x42C81170UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_MBC5          *((volatile unsigned int*)(0x42C81174UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_SA            *((volatile unsigned int*)(0x42C81178UL))
+#define bFM3_ETHERNET_MAC0_MAR9H_AE            *((volatile unsigned int*)(0x42C8117CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A0            *((volatile unsigned int*)(0x42C81180UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A1            *((volatile unsigned int*)(0x42C81184UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A2            *((volatile unsigned int*)(0x42C81188UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A3            *((volatile unsigned int*)(0x42C8118CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A4            *((volatile unsigned int*)(0x42C81190UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A5            *((volatile unsigned int*)(0x42C81194UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A6            *((volatile unsigned int*)(0x42C81198UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A7            *((volatile unsigned int*)(0x42C8119CUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A8            *((volatile unsigned int*)(0x42C811A0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A9            *((volatile unsigned int*)(0x42C811A4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A10           *((volatile unsigned int*)(0x42C811A8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A11           *((volatile unsigned int*)(0x42C811ACUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A12           *((volatile unsigned int*)(0x42C811B0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A13           *((volatile unsigned int*)(0x42C811B4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A14           *((volatile unsigned int*)(0x42C811B8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A15           *((volatile unsigned int*)(0x42C811BCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A16           *((volatile unsigned int*)(0x42C811C0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A17           *((volatile unsigned int*)(0x42C811C4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A18           *((volatile unsigned int*)(0x42C811C8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A19           *((volatile unsigned int*)(0x42C811CCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A20           *((volatile unsigned int*)(0x42C811D0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A21           *((volatile unsigned int*)(0x42C811D4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A22           *((volatile unsigned int*)(0x42C811D8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A23           *((volatile unsigned int*)(0x42C811DCUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A24           *((volatile unsigned int*)(0x42C811E0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A25           *((volatile unsigned int*)(0x42C811E4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A26           *((volatile unsigned int*)(0x42C811E8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A27           *((volatile unsigned int*)(0x42C811ECUL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A28           *((volatile unsigned int*)(0x42C811F0UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A29           *((volatile unsigned int*)(0x42C811F4UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A30           *((volatile unsigned int*)(0x42C811F8UL))
+#define bFM3_ETHERNET_MAC0_MAR9L_A31           *((volatile unsigned int*)(0x42C811FCUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A32          *((volatile unsigned int*)(0x42C81200UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A33          *((volatile unsigned int*)(0x42C81204UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A34          *((volatile unsigned int*)(0x42C81208UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A35          *((volatile unsigned int*)(0x42C8120CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A36          *((volatile unsigned int*)(0x42C81210UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A37          *((volatile unsigned int*)(0x42C81214UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A38          *((volatile unsigned int*)(0x42C81218UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A39          *((volatile unsigned int*)(0x42C8121CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A40          *((volatile unsigned int*)(0x42C81220UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A41          *((volatile unsigned int*)(0x42C81224UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A42          *((volatile unsigned int*)(0x42C81228UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A43          *((volatile unsigned int*)(0x42C8122CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A44          *((volatile unsigned int*)(0x42C81230UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A45          *((volatile unsigned int*)(0x42C81234UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A46          *((volatile unsigned int*)(0x42C81238UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_A47          *((volatile unsigned int*)(0x42C8123CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC0         *((volatile unsigned int*)(0x42C81260UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC1         *((volatile unsigned int*)(0x42C81264UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC2         *((volatile unsigned int*)(0x42C81268UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC3         *((volatile unsigned int*)(0x42C8126CUL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC4         *((volatile unsigned int*)(0x42C81270UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_MBC5         *((volatile unsigned int*)(0x42C81274UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_SA           *((volatile unsigned int*)(0x42C81278UL))
+#define bFM3_ETHERNET_MAC0_MAR10H_AE           *((volatile unsigned int*)(0x42C8127CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A0           *((volatile unsigned int*)(0x42C81280UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A1           *((volatile unsigned int*)(0x42C81284UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A2           *((volatile unsigned int*)(0x42C81288UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A3           *((volatile unsigned int*)(0x42C8128CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A4           *((volatile unsigned int*)(0x42C81290UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A5           *((volatile unsigned int*)(0x42C81294UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A6           *((volatile unsigned int*)(0x42C81298UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A7           *((volatile unsigned int*)(0x42C8129CUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A8           *((volatile unsigned int*)(0x42C812A0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A9           *((volatile unsigned int*)(0x42C812A4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A10          *((volatile unsigned int*)(0x42C812A8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A11          *((volatile unsigned int*)(0x42C812ACUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A12          *((volatile unsigned int*)(0x42C812B0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A13          *((volatile unsigned int*)(0x42C812B4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A14          *((volatile unsigned int*)(0x42C812B8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A15          *((volatile unsigned int*)(0x42C812BCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A16          *((volatile unsigned int*)(0x42C812C0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A17          *((volatile unsigned int*)(0x42C812C4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A18          *((volatile unsigned int*)(0x42C812C8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A19          *((volatile unsigned int*)(0x42C812CCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A20          *((volatile unsigned int*)(0x42C812D0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A21          *((volatile unsigned int*)(0x42C812D4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A22          *((volatile unsigned int*)(0x42C812D8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A23          *((volatile unsigned int*)(0x42C812DCUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A24          *((volatile unsigned int*)(0x42C812E0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A25          *((volatile unsigned int*)(0x42C812E4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A26          *((volatile unsigned int*)(0x42C812E8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A27          *((volatile unsigned int*)(0x42C812ECUL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A28          *((volatile unsigned int*)(0x42C812F0UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A29          *((volatile unsigned int*)(0x42C812F4UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A30          *((volatile unsigned int*)(0x42C812F8UL))
+#define bFM3_ETHERNET_MAC0_MAR10L_A31          *((volatile unsigned int*)(0x42C812FCUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A32          *((volatile unsigned int*)(0x42C81300UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A33          *((volatile unsigned int*)(0x42C81304UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A34          *((volatile unsigned int*)(0x42C81308UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A35          *((volatile unsigned int*)(0x42C8130CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A36          *((volatile unsigned int*)(0x42C81310UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A37          *((volatile unsigned int*)(0x42C81314UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A38          *((volatile unsigned int*)(0x42C81318UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A39          *((volatile unsigned int*)(0x42C8131CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A40          *((volatile unsigned int*)(0x42C81320UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A41          *((volatile unsigned int*)(0x42C81324UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A42          *((volatile unsigned int*)(0x42C81328UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A43          *((volatile unsigned int*)(0x42C8132CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A44          *((volatile unsigned int*)(0x42C81330UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A45          *((volatile unsigned int*)(0x42C81334UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A46          *((volatile unsigned int*)(0x42C81338UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_A47          *((volatile unsigned int*)(0x42C8133CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC0         *((volatile unsigned int*)(0x42C81360UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC1         *((volatile unsigned int*)(0x42C81364UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC2         *((volatile unsigned int*)(0x42C81368UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC3         *((volatile unsigned int*)(0x42C8136CUL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC4         *((volatile unsigned int*)(0x42C81370UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_MBC5         *((volatile unsigned int*)(0x42C81374UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_SA           *((volatile unsigned int*)(0x42C81378UL))
+#define bFM3_ETHERNET_MAC0_MAR11H_AE           *((volatile unsigned int*)(0x42C8137CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A0           *((volatile unsigned int*)(0x42C81380UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A1           *((volatile unsigned int*)(0x42C81384UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A2           *((volatile unsigned int*)(0x42C81388UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A3           *((volatile unsigned int*)(0x42C8138CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A4           *((volatile unsigned int*)(0x42C81390UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A5           *((volatile unsigned int*)(0x42C81394UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A6           *((volatile unsigned int*)(0x42C81398UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A7           *((volatile unsigned int*)(0x42C8139CUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A8           *((volatile unsigned int*)(0x42C813A0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A9           *((volatile unsigned int*)(0x42C813A4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A10          *((volatile unsigned int*)(0x42C813A8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A11          *((volatile unsigned int*)(0x42C813ACUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A12          *((volatile unsigned int*)(0x42C813B0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A13          *((volatile unsigned int*)(0x42C813B4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A14          *((volatile unsigned int*)(0x42C813B8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A15          *((volatile unsigned int*)(0x42C813BCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A16          *((volatile unsigned int*)(0x42C813C0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A17          *((volatile unsigned int*)(0x42C813C4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A18          *((volatile unsigned int*)(0x42C813C8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A19          *((volatile unsigned int*)(0x42C813CCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A20          *((volatile unsigned int*)(0x42C813D0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A21          *((volatile unsigned int*)(0x42C813D4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A22          *((volatile unsigned int*)(0x42C813D8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A23          *((volatile unsigned int*)(0x42C813DCUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A24          *((volatile unsigned int*)(0x42C813E0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A25          *((volatile unsigned int*)(0x42C813E4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A26          *((volatile unsigned int*)(0x42C813E8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A27          *((volatile unsigned int*)(0x42C813ECUL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A28          *((volatile unsigned int*)(0x42C813F0UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A29          *((volatile unsigned int*)(0x42C813F4UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A30          *((volatile unsigned int*)(0x42C813F8UL))
+#define bFM3_ETHERNET_MAC0_MAR11L_A31          *((volatile unsigned int*)(0x42C813FCUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A32          *((volatile unsigned int*)(0x42C81400UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A33          *((volatile unsigned int*)(0x42C81404UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A34          *((volatile unsigned int*)(0x42C81408UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A35          *((volatile unsigned int*)(0x42C8140CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A36          *((volatile unsigned int*)(0x42C81410UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A37          *((volatile unsigned int*)(0x42C81414UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A38          *((volatile unsigned int*)(0x42C81418UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A39          *((volatile unsigned int*)(0x42C8141CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A40          *((volatile unsigned int*)(0x42C81420UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A41          *((volatile unsigned int*)(0x42C81424UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A42          *((volatile unsigned int*)(0x42C81428UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A43          *((volatile unsigned int*)(0x42C8142CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A44          *((volatile unsigned int*)(0x42C81430UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A45          *((volatile unsigned int*)(0x42C81434UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A46          *((volatile unsigned int*)(0x42C81438UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_A47          *((volatile unsigned int*)(0x42C8143CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC0         *((volatile unsigned int*)(0x42C81460UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC1         *((volatile unsigned int*)(0x42C81464UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC2         *((volatile unsigned int*)(0x42C81468UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC3         *((volatile unsigned int*)(0x42C8146CUL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC4         *((volatile unsigned int*)(0x42C81470UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_MBC5         *((volatile unsigned int*)(0x42C81474UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_SA           *((volatile unsigned int*)(0x42C81478UL))
+#define bFM3_ETHERNET_MAC0_MAR12H_AE           *((volatile unsigned int*)(0x42C8147CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A0           *((volatile unsigned int*)(0x42C81480UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A1           *((volatile unsigned int*)(0x42C81484UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A2           *((volatile unsigned int*)(0x42C81488UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A3           *((volatile unsigned int*)(0x42C8148CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A4           *((volatile unsigned int*)(0x42C81490UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A5           *((volatile unsigned int*)(0x42C81494UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A6           *((volatile unsigned int*)(0x42C81498UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A7           *((volatile unsigned int*)(0x42C8149CUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A8           *((volatile unsigned int*)(0x42C814A0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A9           *((volatile unsigned int*)(0x42C814A4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A10          *((volatile unsigned int*)(0x42C814A8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A11          *((volatile unsigned int*)(0x42C814ACUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A12          *((volatile unsigned int*)(0x42C814B0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A13          *((volatile unsigned int*)(0x42C814B4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A14          *((volatile unsigned int*)(0x42C814B8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A15          *((volatile unsigned int*)(0x42C814BCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A16          *((volatile unsigned int*)(0x42C814C0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A17          *((volatile unsigned int*)(0x42C814C4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A18          *((volatile unsigned int*)(0x42C814C8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A19          *((volatile unsigned int*)(0x42C814CCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A20          *((volatile unsigned int*)(0x42C814D0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A21          *((volatile unsigned int*)(0x42C814D4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A22          *((volatile unsigned int*)(0x42C814D8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A23          *((volatile unsigned int*)(0x42C814DCUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A24          *((volatile unsigned int*)(0x42C814E0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A25          *((volatile unsigned int*)(0x42C814E4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A26          *((volatile unsigned int*)(0x42C814E8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A27          *((volatile unsigned int*)(0x42C814ECUL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A28          *((volatile unsigned int*)(0x42C814F0UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A29          *((volatile unsigned int*)(0x42C814F4UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A30          *((volatile unsigned int*)(0x42C814F8UL))
+#define bFM3_ETHERNET_MAC0_MAR12L_A31          *((volatile unsigned int*)(0x42C814FCUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A32          *((volatile unsigned int*)(0x42C81500UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A33          *((volatile unsigned int*)(0x42C81504UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A34          *((volatile unsigned int*)(0x42C81508UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A35          *((volatile unsigned int*)(0x42C8150CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A36          *((volatile unsigned int*)(0x42C81510UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A37          *((volatile unsigned int*)(0x42C81514UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A38          *((volatile unsigned int*)(0x42C81518UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A39          *((volatile unsigned int*)(0x42C8151CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A40          *((volatile unsigned int*)(0x42C81520UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A41          *((volatile unsigned int*)(0x42C81524UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A42          *((volatile unsigned int*)(0x42C81528UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A43          *((volatile unsigned int*)(0x42C8152CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A44          *((volatile unsigned int*)(0x42C81530UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A45          *((volatile unsigned int*)(0x42C81534UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A46          *((volatile unsigned int*)(0x42C81538UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_A47          *((volatile unsigned int*)(0x42C8153CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC0         *((volatile unsigned int*)(0x42C81560UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC1         *((volatile unsigned int*)(0x42C81564UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC2         *((volatile unsigned int*)(0x42C81568UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC3         *((volatile unsigned int*)(0x42C8156CUL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC4         *((volatile unsigned int*)(0x42C81570UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_MBC5         *((volatile unsigned int*)(0x42C81574UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_SA           *((volatile unsigned int*)(0x42C81578UL))
+#define bFM3_ETHERNET_MAC0_MAR13H_AE           *((volatile unsigned int*)(0x42C8157CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A0           *((volatile unsigned int*)(0x42C81580UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A1           *((volatile unsigned int*)(0x42C81584UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A2           *((volatile unsigned int*)(0x42C81588UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A3           *((volatile unsigned int*)(0x42C8158CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A4           *((volatile unsigned int*)(0x42C81590UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A5           *((volatile unsigned int*)(0x42C81594UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A6           *((volatile unsigned int*)(0x42C81598UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A7           *((volatile unsigned int*)(0x42C8159CUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A8           *((volatile unsigned int*)(0x42C815A0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A9           *((volatile unsigned int*)(0x42C815A4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A10          *((volatile unsigned int*)(0x42C815A8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A11          *((volatile unsigned int*)(0x42C815ACUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A12          *((volatile unsigned int*)(0x42C815B0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A13          *((volatile unsigned int*)(0x42C815B4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A14          *((volatile unsigned int*)(0x42C815B8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A15          *((volatile unsigned int*)(0x42C815BCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A16          *((volatile unsigned int*)(0x42C815C0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A17          *((volatile unsigned int*)(0x42C815C4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A18          *((volatile unsigned int*)(0x42C815C8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A19          *((volatile unsigned int*)(0x42C815CCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A20          *((volatile unsigned int*)(0x42C815D0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A21          *((volatile unsigned int*)(0x42C815D4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A22          *((volatile unsigned int*)(0x42C815D8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A23          *((volatile unsigned int*)(0x42C815DCUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A24          *((volatile unsigned int*)(0x42C815E0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A25          *((volatile unsigned int*)(0x42C815E4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A26          *((volatile unsigned int*)(0x42C815E8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A27          *((volatile unsigned int*)(0x42C815ECUL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A28          *((volatile unsigned int*)(0x42C815F0UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A29          *((volatile unsigned int*)(0x42C815F4UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A30          *((volatile unsigned int*)(0x42C815F8UL))
+#define bFM3_ETHERNET_MAC0_MAR13L_A31          *((volatile unsigned int*)(0x42C815FCUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A32          *((volatile unsigned int*)(0x42C81600UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A33          *((volatile unsigned int*)(0x42C81604UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A34          *((volatile unsigned int*)(0x42C81608UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A35          *((volatile unsigned int*)(0x42C8160CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A36          *((volatile unsigned int*)(0x42C81610UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A37          *((volatile unsigned int*)(0x42C81614UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A38          *((volatile unsigned int*)(0x42C81618UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A39          *((volatile unsigned int*)(0x42C8161CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A40          *((volatile unsigned int*)(0x42C81620UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A41          *((volatile unsigned int*)(0x42C81624UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A42          *((volatile unsigned int*)(0x42C81628UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A43          *((volatile unsigned int*)(0x42C8162CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A44          *((volatile unsigned int*)(0x42C81630UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A45          *((volatile unsigned int*)(0x42C81634UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A46          *((volatile unsigned int*)(0x42C81638UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_A47          *((volatile unsigned int*)(0x42C8163CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC0         *((volatile unsigned int*)(0x42C81660UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC1         *((volatile unsigned int*)(0x42C81664UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC2         *((volatile unsigned int*)(0x42C81668UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC3         *((volatile unsigned int*)(0x42C8166CUL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC4         *((volatile unsigned int*)(0x42C81670UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_MBC5         *((volatile unsigned int*)(0x42C81674UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_SA           *((volatile unsigned int*)(0x42C81678UL))
+#define bFM3_ETHERNET_MAC0_MAR14H_AE           *((volatile unsigned int*)(0x42C8167CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A0           *((volatile unsigned int*)(0x42C81680UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A1           *((volatile unsigned int*)(0x42C81684UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A2           *((volatile unsigned int*)(0x42C81688UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A3           *((volatile unsigned int*)(0x42C8168CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A4           *((volatile unsigned int*)(0x42C81690UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A5           *((volatile unsigned int*)(0x42C81694UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A6           *((volatile unsigned int*)(0x42C81698UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A7           *((volatile unsigned int*)(0x42C8169CUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A8           *((volatile unsigned int*)(0x42C816A0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A9           *((volatile unsigned int*)(0x42C816A4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A10          *((volatile unsigned int*)(0x42C816A8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A11          *((volatile unsigned int*)(0x42C816ACUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A12          *((volatile unsigned int*)(0x42C816B0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A13          *((volatile unsigned int*)(0x42C816B4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A14          *((volatile unsigned int*)(0x42C816B8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A15          *((volatile unsigned int*)(0x42C816BCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A16          *((volatile unsigned int*)(0x42C816C0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A17          *((volatile unsigned int*)(0x42C816C4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A18          *((volatile unsigned int*)(0x42C816C8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A19          *((volatile unsigned int*)(0x42C816CCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A20          *((volatile unsigned int*)(0x42C816D0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A21          *((volatile unsigned int*)(0x42C816D4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A22          *((volatile unsigned int*)(0x42C816D8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A23          *((volatile unsigned int*)(0x42C816DCUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A24          *((volatile unsigned int*)(0x42C816E0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A25          *((volatile unsigned int*)(0x42C816E4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A26          *((volatile unsigned int*)(0x42C816E8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A27          *((volatile unsigned int*)(0x42C816ECUL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A28          *((volatile unsigned int*)(0x42C816F0UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A29          *((volatile unsigned int*)(0x42C816F4UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A30          *((volatile unsigned int*)(0x42C816F8UL))
+#define bFM3_ETHERNET_MAC0_MAR14L_A31          *((volatile unsigned int*)(0x42C816FCUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A32          *((volatile unsigned int*)(0x42C81700UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A33          *((volatile unsigned int*)(0x42C81704UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A34          *((volatile unsigned int*)(0x42C81708UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A35          *((volatile unsigned int*)(0x42C8170CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A36          *((volatile unsigned int*)(0x42C81710UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A37          *((volatile unsigned int*)(0x42C81714UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A38          *((volatile unsigned int*)(0x42C81718UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A39          *((volatile unsigned int*)(0x42C8171CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A40          *((volatile unsigned int*)(0x42C81720UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A41          *((volatile unsigned int*)(0x42C81724UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A42          *((volatile unsigned int*)(0x42C81728UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A43          *((volatile unsigned int*)(0x42C8172CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A44          *((volatile unsigned int*)(0x42C81730UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A45          *((volatile unsigned int*)(0x42C81734UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A46          *((volatile unsigned int*)(0x42C81738UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_A47          *((volatile unsigned int*)(0x42C8173CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC0         *((volatile unsigned int*)(0x42C81760UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC1         *((volatile unsigned int*)(0x42C81764UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC2         *((volatile unsigned int*)(0x42C81768UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC3         *((volatile unsigned int*)(0x42C8176CUL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC4         *((volatile unsigned int*)(0x42C81770UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_MBC5         *((volatile unsigned int*)(0x42C81774UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_SA           *((volatile unsigned int*)(0x42C81778UL))
+#define bFM3_ETHERNET_MAC0_MAR15H_AE           *((volatile unsigned int*)(0x42C8177CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A0           *((volatile unsigned int*)(0x42C81780UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A1           *((volatile unsigned int*)(0x42C81784UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A2           *((volatile unsigned int*)(0x42C81788UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A3           *((volatile unsigned int*)(0x42C8178CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A4           *((volatile unsigned int*)(0x42C81790UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A5           *((volatile unsigned int*)(0x42C81794UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A6           *((volatile unsigned int*)(0x42C81798UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A7           *((volatile unsigned int*)(0x42C8179CUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A8           *((volatile unsigned int*)(0x42C817A0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A9           *((volatile unsigned int*)(0x42C817A4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A10          *((volatile unsigned int*)(0x42C817A8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A11          *((volatile unsigned int*)(0x42C817ACUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A12          *((volatile unsigned int*)(0x42C817B0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A13          *((volatile unsigned int*)(0x42C817B4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A14          *((volatile unsigned int*)(0x42C817B8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A15          *((volatile unsigned int*)(0x42C817BCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A16          *((volatile unsigned int*)(0x42C817C0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A17          *((volatile unsigned int*)(0x42C817C4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A18          *((volatile unsigned int*)(0x42C817C8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A19          *((volatile unsigned int*)(0x42C817CCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A20          *((volatile unsigned int*)(0x42C817D0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A21          *((volatile unsigned int*)(0x42C817D4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A22          *((volatile unsigned int*)(0x42C817D8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A23          *((volatile unsigned int*)(0x42C817DCUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A24          *((volatile unsigned int*)(0x42C817E0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A25          *((volatile unsigned int*)(0x42C817E4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A26          *((volatile unsigned int*)(0x42C817E8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A27          *((volatile unsigned int*)(0x42C817ECUL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A28          *((volatile unsigned int*)(0x42C817F0UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A29          *((volatile unsigned int*)(0x42C817F4UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A30          *((volatile unsigned int*)(0x42C817F8UL))
+#define bFM3_ETHERNET_MAC0_MAR15L_A31          *((volatile unsigned int*)(0x42C817FCUL))
+#define bFM3_ETHERNET_MAC0_RGSR_LM             *((volatile unsigned int*)(0x42C81B00UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP0           *((volatile unsigned int*)(0x42C81B04UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LSP1           *((volatile unsigned int*)(0x42C81B08UL))
+#define bFM3_ETHERNET_MAC0_RGSR_LS             *((volatile unsigned int*)(0x42C81B0CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSE            *((volatile unsigned int*)(0x42C8E000UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TFCU           *((volatile unsigned int*)(0x42C8E004UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSI            *((volatile unsigned int*)(0x42C8E008UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSU            *((volatile unsigned int*)(0x42C8E00CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TITE           *((volatile unsigned int*)(0x42C8E010UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TARU           *((volatile unsigned int*)(0x42C8E014UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSEA           *((volatile unsigned int*)(0x42C8E020UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSDB           *((volatile unsigned int*)(0x42C8E024UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSV2E          *((volatile unsigned int*)(0x42C8E028UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSP          *((volatile unsigned int*)(0x42C8E02CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP6E         *((volatile unsigned int*)(0x42C8E030UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSIP4E         *((volatile unsigned int*)(0x42C8E034UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TETSEM         *((volatile unsigned int*)(0x42C8E038UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSMRM          *((volatile unsigned int*)(0x42C8E03CUL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS0          *((volatile unsigned int*)(0x42C8E040UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSPS1          *((volatile unsigned int*)(0x42C8E044UL))
+#define bFM3_ETHERNET_MAC0_TSCR_TSENMF         *((volatile unsigned int*)(0x42C8E048UL))
+#define bFM3_ETHERNET_MAC0_TSCR_ATSFC          *((volatile unsigned int*)(0x42C8E060UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC0         *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC1         *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC2         *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC3         *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC4         *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC5         *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC6         *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_SSIR_SSINC7         *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS0           *((volatile unsigned int*)(0x42C8E100UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS1           *((volatile unsigned int*)(0x42C8E104UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS2           *((volatile unsigned int*)(0x42C8E108UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS3           *((volatile unsigned int*)(0x42C8E10CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS4           *((volatile unsigned int*)(0x42C8E110UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS5           *((volatile unsigned int*)(0x42C8E114UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS6           *((volatile unsigned int*)(0x42C8E118UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS7           *((volatile unsigned int*)(0x42C8E11CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS8           *((volatile unsigned int*)(0x42C8E120UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS9           *((volatile unsigned int*)(0x42C8E124UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS10          *((volatile unsigned int*)(0x42C8E128UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS11          *((volatile unsigned int*)(0x42C8E12CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS12          *((volatile unsigned int*)(0x42C8E130UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS13          *((volatile unsigned int*)(0x42C8E134UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS14          *((volatile unsigned int*)(0x42C8E138UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS15          *((volatile unsigned int*)(0x42C8E13CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS16          *((volatile unsigned int*)(0x42C8E140UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS17          *((volatile unsigned int*)(0x42C8E144UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS18          *((volatile unsigned int*)(0x42C8E148UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS19          *((volatile unsigned int*)(0x42C8E14CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS20          *((volatile unsigned int*)(0x42C8E150UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS21          *((volatile unsigned int*)(0x42C8E154UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS22          *((volatile unsigned int*)(0x42C8E158UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS23          *((volatile unsigned int*)(0x42C8E15CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS24          *((volatile unsigned int*)(0x42C8E160UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS25          *((volatile unsigned int*)(0x42C8E164UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS26          *((volatile unsigned int*)(0x42C8E168UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS27          *((volatile unsigned int*)(0x42C8E16CUL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS28          *((volatile unsigned int*)(0x42C8E170UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS29          *((volatile unsigned int*)(0x42C8E174UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS30          *((volatile unsigned int*)(0x42C8E178UL))
+#define bFM3_ETHERNET_MAC0_STSR_TSS31          *((volatile unsigned int*)(0x42C8E17CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS0          *((volatile unsigned int*)(0x42C8E080UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS1          *((volatile unsigned int*)(0x42C8E084UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS2          *((volatile unsigned int*)(0x42C8E088UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS3          *((volatile unsigned int*)(0x42C8E08CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS4          *((volatile unsigned int*)(0x42C8E090UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS5          *((volatile unsigned int*)(0x42C8E094UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS6          *((volatile unsigned int*)(0x42C8E098UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS7          *((volatile unsigned int*)(0x42C8E09CUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS8          *((volatile unsigned int*)(0x42C8E0A0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS9          *((volatile unsigned int*)(0x42C8E0A4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS10         *((volatile unsigned int*)(0x42C8E0A8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS11         *((volatile unsigned int*)(0x42C8E0ACUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS12         *((volatile unsigned int*)(0x42C8E0B0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS13         *((volatile unsigned int*)(0x42C8E0B4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS14         *((volatile unsigned int*)(0x42C8E0B8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS15         *((volatile unsigned int*)(0x42C8E0BCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS16         *((volatile unsigned int*)(0x42C8E0C0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS17         *((volatile unsigned int*)(0x42C8E0C4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS18         *((volatile unsigned int*)(0x42C8E0C8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS19         *((volatile unsigned int*)(0x42C8E0CCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS20         *((volatile unsigned int*)(0x42C8E0D0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS21         *((volatile unsigned int*)(0x42C8E0D4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS22         *((volatile unsigned int*)(0x42C8E0D8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS23         *((volatile unsigned int*)(0x42C8E0DCUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS24         *((volatile unsigned int*)(0x42C8E0E0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS25         *((volatile unsigned int*)(0x42C8E0E4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS26         *((volatile unsigned int*)(0x42C8E0E8UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS27         *((volatile unsigned int*)(0x42C8E0ECUL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS28         *((volatile unsigned int*)(0x42C8E0F0UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS29         *((volatile unsigned int*)(0x42C8E0F4UL))
+#define bFM3_ETHERNET_MAC0_STNR_TSSS30         *((volatile unsigned int*)(0x42C8E0F8UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS0          *((volatile unsigned int*)(0x42C8E200UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS1          *((volatile unsigned int*)(0x42C8E204UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS2          *((volatile unsigned int*)(0x42C8E208UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS3          *((volatile unsigned int*)(0x42C8E20CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS4          *((volatile unsigned int*)(0x42C8E210UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS5          *((volatile unsigned int*)(0x42C8E214UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS6          *((volatile unsigned int*)(0x42C8E218UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS7          *((volatile unsigned int*)(0x42C8E21CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS8          *((volatile unsigned int*)(0x42C8E220UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS9          *((volatile unsigned int*)(0x42C8E224UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS10         *((volatile unsigned int*)(0x42C8E228UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS11         *((volatile unsigned int*)(0x42C8E22CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS12         *((volatile unsigned int*)(0x42C8E230UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS13         *((volatile unsigned int*)(0x42C8E234UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS14         *((volatile unsigned int*)(0x42C8E238UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS15         *((volatile unsigned int*)(0x42C8E23CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS16         *((volatile unsigned int*)(0x42C8E240UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS17         *((volatile unsigned int*)(0x42C8E244UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS18         *((volatile unsigned int*)(0x42C8E248UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS19         *((volatile unsigned int*)(0x42C8E24CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS20         *((volatile unsigned int*)(0x42C8E250UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS21         *((volatile unsigned int*)(0x42C8E254UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS22         *((volatile unsigned int*)(0x42C8E258UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS23         *((volatile unsigned int*)(0x42C8E25CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS24         *((volatile unsigned int*)(0x42C8E260UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS25         *((volatile unsigned int*)(0x42C8E264UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS26         *((volatile unsigned int*)(0x42C8E268UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS27         *((volatile unsigned int*)(0x42C8E26CUL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS28         *((volatile unsigned int*)(0x42C8E270UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS29         *((volatile unsigned int*)(0x42C8E274UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS30         *((volatile unsigned int*)(0x42C8E278UL))
+#define bFM3_ETHERNET_MAC0_STSUR_TSS31         *((volatile unsigned int*)(0x42C8E27CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS0         *((volatile unsigned int*)(0x42C8E280UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS1         *((volatile unsigned int*)(0x42C8E284UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS2         *((volatile unsigned int*)(0x42C8E288UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS3         *((volatile unsigned int*)(0x42C8E28CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS4         *((volatile unsigned int*)(0x42C8E290UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS5         *((volatile unsigned int*)(0x42C8E294UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS6         *((volatile unsigned int*)(0x42C8E298UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS7         *((volatile unsigned int*)(0x42C8E29CUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS8         *((volatile unsigned int*)(0x42C8E2A0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS9         *((volatile unsigned int*)(0x42C8E2A4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS10        *((volatile unsigned int*)(0x42C8E2A8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS11        *((volatile unsigned int*)(0x42C8E2ACUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS12        *((volatile unsigned int*)(0x42C8E2B0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS13        *((volatile unsigned int*)(0x42C8E2B4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS14        *((volatile unsigned int*)(0x42C8E2B8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS15        *((volatile unsigned int*)(0x42C8E2BCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS16        *((volatile unsigned int*)(0x42C8E2C0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS17        *((volatile unsigned int*)(0x42C8E2C4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS18        *((volatile unsigned int*)(0x42C8E2C8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS19        *((volatile unsigned int*)(0x42C8E2CCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS20        *((volatile unsigned int*)(0x42C8E2D0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS21        *((volatile unsigned int*)(0x42C8E2D4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS22        *((volatile unsigned int*)(0x42C8E2D8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS23        *((volatile unsigned int*)(0x42C8E2DCUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS24        *((volatile unsigned int*)(0x42C8E2E0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS25        *((volatile unsigned int*)(0x42C8E2E4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS26        *((volatile unsigned int*)(0x42C8E2E8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS27        *((volatile unsigned int*)(0x42C8E2ECUL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS28        *((volatile unsigned int*)(0x42C8E2F0UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS29        *((volatile unsigned int*)(0x42C8E2F4UL))
+#define bFM3_ETHERNET_MAC0_STNUR_TSSS30        *((volatile unsigned int*)(0x42C8E2F8UL))
+#define bFM3_ETHERNET_MAC0_STNUR_ADDSUB        *((volatile unsigned int*)(0x42C8E2FCUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR0          *((volatile unsigned int*)(0x42C8E300UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR1          *((volatile unsigned int*)(0x42C8E304UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR2          *((volatile unsigned int*)(0x42C8E308UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR3          *((volatile unsigned int*)(0x42C8E30CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR4          *((volatile unsigned int*)(0x42C8E310UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR5          *((volatile unsigned int*)(0x42C8E314UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR6          *((volatile unsigned int*)(0x42C8E318UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR7          *((volatile unsigned int*)(0x42C8E31CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR8          *((volatile unsigned int*)(0x42C8E320UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR9          *((volatile unsigned int*)(0x42C8E324UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR10         *((volatile unsigned int*)(0x42C8E328UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR11         *((volatile unsigned int*)(0x42C8E32CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR12         *((volatile unsigned int*)(0x42C8E330UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR13         *((volatile unsigned int*)(0x42C8E334UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR14         *((volatile unsigned int*)(0x42C8E338UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR15         *((volatile unsigned int*)(0x42C8E33CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR16         *((volatile unsigned int*)(0x42C8E340UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR17         *((volatile unsigned int*)(0x42C8E344UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR18         *((volatile unsigned int*)(0x42C8E348UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR19         *((volatile unsigned int*)(0x42C8E34CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR20         *((volatile unsigned int*)(0x42C8E350UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR21         *((volatile unsigned int*)(0x42C8E354UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR22         *((volatile unsigned int*)(0x42C8E358UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR23         *((volatile unsigned int*)(0x42C8E35CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR24         *((volatile unsigned int*)(0x42C8E360UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR25         *((volatile unsigned int*)(0x42C8E364UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR26         *((volatile unsigned int*)(0x42C8E368UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR27         *((volatile unsigned int*)(0x42C8E36CUL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR28         *((volatile unsigned int*)(0x42C8E370UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR29         *((volatile unsigned int*)(0x42C8E374UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR30         *((volatile unsigned int*)(0x42C8E378UL))
+#define bFM3_ETHERNET_MAC0_TSAR_TSAR31         *((volatile unsigned int*)(0x42C8E37CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR0          *((volatile unsigned int*)(0x42C8E380UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR1          *((volatile unsigned int*)(0x42C8E384UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR2          *((volatile unsigned int*)(0x42C8E388UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR3          *((volatile unsigned int*)(0x42C8E38CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR4          *((volatile unsigned int*)(0x42C8E390UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR5          *((volatile unsigned int*)(0x42C8E394UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR6          *((volatile unsigned int*)(0x42C8E398UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR7          *((volatile unsigned int*)(0x42C8E39CUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR8          *((volatile unsigned int*)(0x42C8E3A0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR9          *((volatile unsigned int*)(0x42C8E3A4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR10         *((volatile unsigned int*)(0x42C8E3A8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR11         *((volatile unsigned int*)(0x42C8E3ACUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR12         *((volatile unsigned int*)(0x42C8E3B0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR13         *((volatile unsigned int*)(0x42C8E3B4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR14         *((volatile unsigned int*)(0x42C8E3B8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR15         *((volatile unsigned int*)(0x42C8E3BCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR16         *((volatile unsigned int*)(0x42C8E3C0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR17         *((volatile unsigned int*)(0x42C8E3C4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR18         *((volatile unsigned int*)(0x42C8E3C8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR19         *((volatile unsigned int*)(0x42C8E3CCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR20         *((volatile unsigned int*)(0x42C8E3D0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR21         *((volatile unsigned int*)(0x42C8E3D4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR22         *((volatile unsigned int*)(0x42C8E3D8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR23         *((volatile unsigned int*)(0x42C8E3DCUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR24         *((volatile unsigned int*)(0x42C8E3E0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR25         *((volatile unsigned int*)(0x42C8E3E4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR26         *((volatile unsigned int*)(0x42C8E3E8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR27         *((volatile unsigned int*)(0x42C8E3ECUL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR28         *((volatile unsigned int*)(0x42C8E3F0UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR29         *((volatile unsigned int*)(0x42C8E3F4UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR30         *((volatile unsigned int*)(0x42C8E3F8UL))
+#define bFM3_ETHERNET_MAC0_TTSR_TSTR31         *((volatile unsigned int*)(0x42C8E3FCUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR0          *((volatile unsigned int*)(0x42C8E400UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR1          *((volatile unsigned int*)(0x42C8E404UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR2          *((volatile unsigned int*)(0x42C8E408UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR3          *((volatile unsigned int*)(0x42C8E40CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR4          *((volatile unsigned int*)(0x42C8E410UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR5          *((volatile unsigned int*)(0x42C8E414UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR6          *((volatile unsigned int*)(0x42C8E418UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR7          *((volatile unsigned int*)(0x42C8E41CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR8          *((volatile unsigned int*)(0x42C8E420UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR9          *((volatile unsigned int*)(0x42C8E424UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR10         *((volatile unsigned int*)(0x42C8E428UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR11         *((volatile unsigned int*)(0x42C8E42CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR12         *((volatile unsigned int*)(0x42C8E430UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR13         *((volatile unsigned int*)(0x42C8E434UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR14         *((volatile unsigned int*)(0x42C8E438UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR15         *((volatile unsigned int*)(0x42C8E43CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR16         *((volatile unsigned int*)(0x42C8E440UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR17         *((volatile unsigned int*)(0x42C8E444UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR18         *((volatile unsigned int*)(0x42C8E448UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR19         *((volatile unsigned int*)(0x42C8E44CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR20         *((volatile unsigned int*)(0x42C8E450UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR21         *((volatile unsigned int*)(0x42C8E454UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR22         *((volatile unsigned int*)(0x42C8E458UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR23         *((volatile unsigned int*)(0x42C8E45CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR24         *((volatile unsigned int*)(0x42C8E460UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR25         *((volatile unsigned int*)(0x42C8E464UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR26         *((volatile unsigned int*)(0x42C8E468UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR27         *((volatile unsigned int*)(0x42C8E46CUL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR28         *((volatile unsigned int*)(0x42C8E470UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR29         *((volatile unsigned int*)(0x42C8E474UL))
+#define bFM3_ETHERNET_MAC0_TTNR_TSTR30         *((volatile unsigned int*)(0x42C8E478UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42C8E480UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42C8E484UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42C8E488UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42C8E48CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42C8E490UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42C8E494UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42C8E498UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42C8E49CUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42C8E4A0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42C8E4A4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42C8E4A8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42C8E4ACUL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42C8E4B0UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42C8E4B4UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42C8E4B8UL))
+#define bFM3_ETHERNET_MAC0_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42C8E4BCUL))
+#define bFM3_ETHERNET_MAC0_TSR_TSSOVF          *((volatile unsigned int*)(0x42C8E500UL))
+#define bFM3_ETHERNET_MAC0_TSR_TSTART          *((volatile unsigned int*)(0x42C8E504UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSTS           *((volatile unsigned int*)(0x42C8E508UL))
+#define bFM3_ETHERNET_MAC0_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSSTM          *((volatile unsigned int*)(0x42C8E560UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS0          *((volatile unsigned int*)(0x42C8E564UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS1          *((volatile unsigned int*)(0x42C8E568UL))
+#define bFM3_ETHERNET_MAC0_TSR_ATSNS2          *((volatile unsigned int*)(0x42C8E56CUL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42C8E580UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42C8E584UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42C8E588UL))
+#define bFM3_ETHERNET_MAC0_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42C8E58CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN0           *((volatile unsigned int*)(0x42C8E600UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN1           *((volatile unsigned int*)(0x42C8E604UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN2           *((volatile unsigned int*)(0x42C8E608UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN3           *((volatile unsigned int*)(0x42C8E60CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN4           *((volatile unsigned int*)(0x42C8E610UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN5           *((volatile unsigned int*)(0x42C8E614UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN6           *((volatile unsigned int*)(0x42C8E618UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN7           *((volatile unsigned int*)(0x42C8E61CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN8           *((volatile unsigned int*)(0x42C8E620UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN9           *((volatile unsigned int*)(0x42C8E624UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN10          *((volatile unsigned int*)(0x42C8E628UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN11          *((volatile unsigned int*)(0x42C8E62CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN12          *((volatile unsigned int*)(0x42C8E630UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN13          *((volatile unsigned int*)(0x42C8E634UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN14          *((volatile unsigned int*)(0x42C8E638UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN15          *((volatile unsigned int*)(0x42C8E63CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN16          *((volatile unsigned int*)(0x42C8E640UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN17          *((volatile unsigned int*)(0x42C8E644UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN18          *((volatile unsigned int*)(0x42C8E648UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN19          *((volatile unsigned int*)(0x42C8E64CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN20          *((volatile unsigned int*)(0x42C8E650UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN21          *((volatile unsigned int*)(0x42C8E654UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN22          *((volatile unsigned int*)(0x42C8E658UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN23          *((volatile unsigned int*)(0x42C8E65CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN24          *((volatile unsigned int*)(0x42C8E660UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN25          *((volatile unsigned int*)(0x42C8E664UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN26          *((volatile unsigned int*)(0x42C8E668UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN27          *((volatile unsigned int*)(0x42C8E66CUL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN28          *((volatile unsigned int*)(0x42C8E670UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN29          *((volatile unsigned int*)(0x42C8E674UL))
+#define bFM3_ETHERNET_MAC0_ATNR_ATN30          *((volatile unsigned int*)(0x42C8E678UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS0           *((volatile unsigned int*)(0x42C8E680UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS1           *((volatile unsigned int*)(0x42C8E684UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS2           *((volatile unsigned int*)(0x42C8E688UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS3           *((volatile unsigned int*)(0x42C8E68CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS4           *((volatile unsigned int*)(0x42C8E690UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS5           *((volatile unsigned int*)(0x42C8E694UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS6           *((volatile unsigned int*)(0x42C8E698UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS7           *((volatile unsigned int*)(0x42C8E69CUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS8           *((volatile unsigned int*)(0x42C8E6A0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS9           *((volatile unsigned int*)(0x42C8E6A4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS10          *((volatile unsigned int*)(0x42C8E6A8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS11          *((volatile unsigned int*)(0x42C8E6ACUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS12          *((volatile unsigned int*)(0x42C8E6B0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS13          *((volatile unsigned int*)(0x42C8E6B4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS14          *((volatile unsigned int*)(0x42C8E6B8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS15          *((volatile unsigned int*)(0x42C8E6BCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS16          *((volatile unsigned int*)(0x42C8E6C0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS17          *((volatile unsigned int*)(0x42C8E6C4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS18          *((volatile unsigned int*)(0x42C8E6C8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS19          *((volatile unsigned int*)(0x42C8E6CCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS20          *((volatile unsigned int*)(0x42C8E6D0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS21          *((volatile unsigned int*)(0x42C8E6D4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS22          *((volatile unsigned int*)(0x42C8E6D8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS23          *((volatile unsigned int*)(0x42C8E6DCUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS24          *((volatile unsigned int*)(0x42C8E6E0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS25          *((volatile unsigned int*)(0x42C8E6E4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS26          *((volatile unsigned int*)(0x42C8E6E8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS27          *((volatile unsigned int*)(0x42C8E6ECUL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS28          *((volatile unsigned int*)(0x42C8E6F0UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS29          *((volatile unsigned int*)(0x42C8E6F4UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS30          *((volatile unsigned int*)(0x42C8E6F8UL))
+#define bFM3_ETHERNET_MAC0_ATSR_ATS31          *((volatile unsigned int*)(0x42C8E6FCUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A32          *((volatile unsigned int*)(0x42C90000UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A33          *((volatile unsigned int*)(0x42C90004UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A34          *((volatile unsigned int*)(0x42C90008UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A35          *((volatile unsigned int*)(0x42C9000CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A36          *((volatile unsigned int*)(0x42C90010UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A37          *((volatile unsigned int*)(0x42C90014UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A38          *((volatile unsigned int*)(0x42C90018UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A39          *((volatile unsigned int*)(0x42C9001CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A40          *((volatile unsigned int*)(0x42C90020UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A41          *((volatile unsigned int*)(0x42C90024UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A42          *((volatile unsigned int*)(0x42C90028UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A43          *((volatile unsigned int*)(0x42C9002CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A44          *((volatile unsigned int*)(0x42C90030UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A45          *((volatile unsigned int*)(0x42C90034UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A46          *((volatile unsigned int*)(0x42C90038UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_A47          *((volatile unsigned int*)(0x42C9003CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC0         *((volatile unsigned int*)(0x42C90060UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC1         *((volatile unsigned int*)(0x42C90064UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC2         *((volatile unsigned int*)(0x42C90068UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC3         *((volatile unsigned int*)(0x42C9006CUL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC4         *((volatile unsigned int*)(0x42C90070UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_MBC5         *((volatile unsigned int*)(0x42C90074UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_SA           *((volatile unsigned int*)(0x42C90078UL))
+#define bFM3_ETHERNET_MAC0_MAR16H_AE           *((volatile unsigned int*)(0x42C9007CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A0           *((volatile unsigned int*)(0x42C90080UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A1           *((volatile unsigned int*)(0x42C90084UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A2           *((volatile unsigned int*)(0x42C90088UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A3           *((volatile unsigned int*)(0x42C9008CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A4           *((volatile unsigned int*)(0x42C90090UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A5           *((volatile unsigned int*)(0x42C90094UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A6           *((volatile unsigned int*)(0x42C90098UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A7           *((volatile unsigned int*)(0x42C9009CUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A8           *((volatile unsigned int*)(0x42C900A0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A9           *((volatile unsigned int*)(0x42C900A4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A10          *((volatile unsigned int*)(0x42C900A8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A11          *((volatile unsigned int*)(0x42C900ACUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A12          *((volatile unsigned int*)(0x42C900B0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A13          *((volatile unsigned int*)(0x42C900B4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A14          *((volatile unsigned int*)(0x42C900B8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A15          *((volatile unsigned int*)(0x42C900BCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A16          *((volatile unsigned int*)(0x42C900C0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A17          *((volatile unsigned int*)(0x42C900C4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A18          *((volatile unsigned int*)(0x42C900C8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A19          *((volatile unsigned int*)(0x42C900CCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A20          *((volatile unsigned int*)(0x42C900D0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A21          *((volatile unsigned int*)(0x42C900D4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A22          *((volatile unsigned int*)(0x42C900D8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A23          *((volatile unsigned int*)(0x42C900DCUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A24          *((volatile unsigned int*)(0x42C900E0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A25          *((volatile unsigned int*)(0x42C900E4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A26          *((volatile unsigned int*)(0x42C900E8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A27          *((volatile unsigned int*)(0x42C900ECUL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A28          *((volatile unsigned int*)(0x42C900F0UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A29          *((volatile unsigned int*)(0x42C900F4UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A30          *((volatile unsigned int*)(0x42C900F8UL))
+#define bFM3_ETHERNET_MAC0_MAR16L_A31          *((volatile unsigned int*)(0x42C900FCUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A32          *((volatile unsigned int*)(0x42C90100UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A33          *((volatile unsigned int*)(0x42C90104UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A34          *((volatile unsigned int*)(0x42C90108UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A35          *((volatile unsigned int*)(0x42C9010CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A36          *((volatile unsigned int*)(0x42C90110UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A37          *((volatile unsigned int*)(0x42C90114UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A38          *((volatile unsigned int*)(0x42C90118UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A39          *((volatile unsigned int*)(0x42C9011CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A40          *((volatile unsigned int*)(0x42C90120UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A41          *((volatile unsigned int*)(0x42C90124UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A42          *((volatile unsigned int*)(0x42C90128UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A43          *((volatile unsigned int*)(0x42C9012CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A44          *((volatile unsigned int*)(0x42C90130UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A45          *((volatile unsigned int*)(0x42C90134UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A46          *((volatile unsigned int*)(0x42C90138UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_A47          *((volatile unsigned int*)(0x42C9013CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC0         *((volatile unsigned int*)(0x42C90160UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC1         *((volatile unsigned int*)(0x42C90164UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC2         *((volatile unsigned int*)(0x42C90168UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC3         *((volatile unsigned int*)(0x42C9016CUL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC4         *((volatile unsigned int*)(0x42C90170UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_MBC5         *((volatile unsigned int*)(0x42C90174UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_SA           *((volatile unsigned int*)(0x42C90178UL))
+#define bFM3_ETHERNET_MAC0_MAR17H_AE           *((volatile unsigned int*)(0x42C9017CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A0           *((volatile unsigned int*)(0x42C90180UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A1           *((volatile unsigned int*)(0x42C90184UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A2           *((volatile unsigned int*)(0x42C90188UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A3           *((volatile unsigned int*)(0x42C9018CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A4           *((volatile unsigned int*)(0x42C90190UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A5           *((volatile unsigned int*)(0x42C90194UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A6           *((volatile unsigned int*)(0x42C90198UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A7           *((volatile unsigned int*)(0x42C9019CUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A8           *((volatile unsigned int*)(0x42C901A0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A9           *((volatile unsigned int*)(0x42C901A4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A10          *((volatile unsigned int*)(0x42C901A8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A11          *((volatile unsigned int*)(0x42C901ACUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A12          *((volatile unsigned int*)(0x42C901B0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A13          *((volatile unsigned int*)(0x42C901B4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A14          *((volatile unsigned int*)(0x42C901B8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A15          *((volatile unsigned int*)(0x42C901BCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A16          *((volatile unsigned int*)(0x42C901C0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A17          *((volatile unsigned int*)(0x42C901C4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A18          *((volatile unsigned int*)(0x42C901C8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A19          *((volatile unsigned int*)(0x42C901CCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A20          *((volatile unsigned int*)(0x42C901D0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A21          *((volatile unsigned int*)(0x42C901D4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A22          *((volatile unsigned int*)(0x42C901D8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A23          *((volatile unsigned int*)(0x42C901DCUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A24          *((volatile unsigned int*)(0x42C901E0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A25          *((volatile unsigned int*)(0x42C901E4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A26          *((volatile unsigned int*)(0x42C901E8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A27          *((volatile unsigned int*)(0x42C901ECUL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A28          *((volatile unsigned int*)(0x42C901F0UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A29          *((volatile unsigned int*)(0x42C901F4UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A30          *((volatile unsigned int*)(0x42C901F8UL))
+#define bFM3_ETHERNET_MAC0_MAR17L_A31          *((volatile unsigned int*)(0x42C901FCUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A32          *((volatile unsigned int*)(0x42C90200UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A33          *((volatile unsigned int*)(0x42C90204UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A34          *((volatile unsigned int*)(0x42C90208UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A35          *((volatile unsigned int*)(0x42C9020CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A36          *((volatile unsigned int*)(0x42C90210UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A37          *((volatile unsigned int*)(0x42C90214UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A38          *((volatile unsigned int*)(0x42C90218UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A39          *((volatile unsigned int*)(0x42C9021CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A40          *((volatile unsigned int*)(0x42C90220UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A41          *((volatile unsigned int*)(0x42C90224UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A42          *((volatile unsigned int*)(0x42C90228UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A43          *((volatile unsigned int*)(0x42C9022CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A44          *((volatile unsigned int*)(0x42C90230UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A45          *((volatile unsigned int*)(0x42C90234UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A46          *((volatile unsigned int*)(0x42C90238UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_A47          *((volatile unsigned int*)(0x42C9023CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC0         *((volatile unsigned int*)(0x42C90260UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC1         *((volatile unsigned int*)(0x42C90264UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC2         *((volatile unsigned int*)(0x42C90268UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC3         *((volatile unsigned int*)(0x42C9026CUL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC4         *((volatile unsigned int*)(0x42C90270UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_MBC5         *((volatile unsigned int*)(0x42C90274UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_SA           *((volatile unsigned int*)(0x42C90278UL))
+#define bFM3_ETHERNET_MAC0_MAR18H_AE           *((volatile unsigned int*)(0x42C9027CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A0           *((volatile unsigned int*)(0x42C90280UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A1           *((volatile unsigned int*)(0x42C90284UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A2           *((volatile unsigned int*)(0x42C90288UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A3           *((volatile unsigned int*)(0x42C9028CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A4           *((volatile unsigned int*)(0x42C90290UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A5           *((volatile unsigned int*)(0x42C90294UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A6           *((volatile unsigned int*)(0x42C90298UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A7           *((volatile unsigned int*)(0x42C9029CUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A8           *((volatile unsigned int*)(0x42C902A0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A9           *((volatile unsigned int*)(0x42C902A4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A10          *((volatile unsigned int*)(0x42C902A8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A11          *((volatile unsigned int*)(0x42C902ACUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A12          *((volatile unsigned int*)(0x42C902B0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A13          *((volatile unsigned int*)(0x42C902B4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A14          *((volatile unsigned int*)(0x42C902B8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A15          *((volatile unsigned int*)(0x42C902BCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A16          *((volatile unsigned int*)(0x42C902C0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A17          *((volatile unsigned int*)(0x42C902C4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A18          *((volatile unsigned int*)(0x42C902C8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A19          *((volatile unsigned int*)(0x42C902CCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A20          *((volatile unsigned int*)(0x42C902D0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A21          *((volatile unsigned int*)(0x42C902D4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A22          *((volatile unsigned int*)(0x42C902D8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A23          *((volatile unsigned int*)(0x42C902DCUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A24          *((volatile unsigned int*)(0x42C902E0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A25          *((volatile unsigned int*)(0x42C902E4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A26          *((volatile unsigned int*)(0x42C902E8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A27          *((volatile unsigned int*)(0x42C902ECUL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A28          *((volatile unsigned int*)(0x42C902F0UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A29          *((volatile unsigned int*)(0x42C902F4UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A30          *((volatile unsigned int*)(0x42C902F8UL))
+#define bFM3_ETHERNET_MAC0_MAR18L_A31          *((volatile unsigned int*)(0x42C902FCUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A32          *((volatile unsigned int*)(0x42C90300UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A33          *((volatile unsigned int*)(0x42C90304UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A34          *((volatile unsigned int*)(0x42C90308UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A35          *((volatile unsigned int*)(0x42C9030CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A36          *((volatile unsigned int*)(0x42C90310UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A37          *((volatile unsigned int*)(0x42C90314UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A38          *((volatile unsigned int*)(0x42C90318UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A39          *((volatile unsigned int*)(0x42C9031CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A40          *((volatile unsigned int*)(0x42C90320UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A41          *((volatile unsigned int*)(0x42C90324UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A42          *((volatile unsigned int*)(0x42C90328UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A43          *((volatile unsigned int*)(0x42C9032CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A44          *((volatile unsigned int*)(0x42C90330UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A45          *((volatile unsigned int*)(0x42C90334UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A46          *((volatile unsigned int*)(0x42C90338UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_A47          *((volatile unsigned int*)(0x42C9033CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC0         *((volatile unsigned int*)(0x42C90360UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC1         *((volatile unsigned int*)(0x42C90364UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC2         *((volatile unsigned int*)(0x42C90368UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC3         *((volatile unsigned int*)(0x42C9036CUL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC4         *((volatile unsigned int*)(0x42C90370UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_MBC5         *((volatile unsigned int*)(0x42C90374UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_SA           *((volatile unsigned int*)(0x42C90378UL))
+#define bFM3_ETHERNET_MAC0_MAR19H_AE           *((volatile unsigned int*)(0x42C9037CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A0           *((volatile unsigned int*)(0x42C90380UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A1           *((volatile unsigned int*)(0x42C90384UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A2           *((volatile unsigned int*)(0x42C90388UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A3           *((volatile unsigned int*)(0x42C9038CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A4           *((volatile unsigned int*)(0x42C90390UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A5           *((volatile unsigned int*)(0x42C90394UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A6           *((volatile unsigned int*)(0x42C90398UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A7           *((volatile unsigned int*)(0x42C9039CUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A8           *((volatile unsigned int*)(0x42C903A0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A9           *((volatile unsigned int*)(0x42C903A4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A10          *((volatile unsigned int*)(0x42C903A8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A11          *((volatile unsigned int*)(0x42C903ACUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A12          *((volatile unsigned int*)(0x42C903B0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A13          *((volatile unsigned int*)(0x42C903B4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A14          *((volatile unsigned int*)(0x42C903B8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A15          *((volatile unsigned int*)(0x42C903BCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A16          *((volatile unsigned int*)(0x42C903C0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A17          *((volatile unsigned int*)(0x42C903C4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A18          *((volatile unsigned int*)(0x42C903C8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A19          *((volatile unsigned int*)(0x42C903CCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A20          *((volatile unsigned int*)(0x42C903D0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A21          *((volatile unsigned int*)(0x42C903D4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A22          *((volatile unsigned int*)(0x42C903D8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A23          *((volatile unsigned int*)(0x42C903DCUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A24          *((volatile unsigned int*)(0x42C903E0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A25          *((volatile unsigned int*)(0x42C903E4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A26          *((volatile unsigned int*)(0x42C903E8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A27          *((volatile unsigned int*)(0x42C903ECUL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A28          *((volatile unsigned int*)(0x42C903F0UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A29          *((volatile unsigned int*)(0x42C903F4UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A30          *((volatile unsigned int*)(0x42C903F8UL))
+#define bFM3_ETHERNET_MAC0_MAR19L_A31          *((volatile unsigned int*)(0x42C903FCUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A32          *((volatile unsigned int*)(0x42C90400UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A33          *((volatile unsigned int*)(0x42C90404UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A34          *((volatile unsigned int*)(0x42C90408UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A35          *((volatile unsigned int*)(0x42C9040CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A36          *((volatile unsigned int*)(0x42C90410UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A37          *((volatile unsigned int*)(0x42C90414UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A38          *((volatile unsigned int*)(0x42C90418UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A39          *((volatile unsigned int*)(0x42C9041CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A40          *((volatile unsigned int*)(0x42C90420UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A41          *((volatile unsigned int*)(0x42C90424UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A42          *((volatile unsigned int*)(0x42C90428UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A43          *((volatile unsigned int*)(0x42C9042CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A44          *((volatile unsigned int*)(0x42C90430UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A45          *((volatile unsigned int*)(0x42C90434UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A46          *((volatile unsigned int*)(0x42C90438UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_A47          *((volatile unsigned int*)(0x42C9043CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC0         *((volatile unsigned int*)(0x42C90460UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC1         *((volatile unsigned int*)(0x42C90464UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC2         *((volatile unsigned int*)(0x42C90468UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC3         *((volatile unsigned int*)(0x42C9046CUL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC4         *((volatile unsigned int*)(0x42C90470UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_MBC5         *((volatile unsigned int*)(0x42C90474UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_SA           *((volatile unsigned int*)(0x42C90478UL))
+#define bFM3_ETHERNET_MAC0_MAR20H_AE           *((volatile unsigned int*)(0x42C9047CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A0           *((volatile unsigned int*)(0x42C90480UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A1           *((volatile unsigned int*)(0x42C90484UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A2           *((volatile unsigned int*)(0x42C90488UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A3           *((volatile unsigned int*)(0x42C9048CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A4           *((volatile unsigned int*)(0x42C90490UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A5           *((volatile unsigned int*)(0x42C90494UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A6           *((volatile unsigned int*)(0x42C90498UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A7           *((volatile unsigned int*)(0x42C9049CUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A8           *((volatile unsigned int*)(0x42C904A0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A9           *((volatile unsigned int*)(0x42C904A4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A10          *((volatile unsigned int*)(0x42C904A8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A11          *((volatile unsigned int*)(0x42C904ACUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A12          *((volatile unsigned int*)(0x42C904B0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A13          *((volatile unsigned int*)(0x42C904B4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A14          *((volatile unsigned int*)(0x42C904B8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A15          *((volatile unsigned int*)(0x42C904BCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A16          *((volatile unsigned int*)(0x42C904C0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A17          *((volatile unsigned int*)(0x42C904C4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A18          *((volatile unsigned int*)(0x42C904C8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A19          *((volatile unsigned int*)(0x42C904CCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A20          *((volatile unsigned int*)(0x42C904D0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A21          *((volatile unsigned int*)(0x42C904D4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A22          *((volatile unsigned int*)(0x42C904D8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A23          *((volatile unsigned int*)(0x42C904DCUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A24          *((volatile unsigned int*)(0x42C904E0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A25          *((volatile unsigned int*)(0x42C904E4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A26          *((volatile unsigned int*)(0x42C904E8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A27          *((volatile unsigned int*)(0x42C904ECUL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A28          *((volatile unsigned int*)(0x42C904F0UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A29          *((volatile unsigned int*)(0x42C904F4UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A30          *((volatile unsigned int*)(0x42C904F8UL))
+#define bFM3_ETHERNET_MAC0_MAR20L_A31          *((volatile unsigned int*)(0x42C904FCUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A32          *((volatile unsigned int*)(0x42C90500UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A33          *((volatile unsigned int*)(0x42C90504UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A34          *((volatile unsigned int*)(0x42C90508UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A35          *((volatile unsigned int*)(0x42C9050CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A36          *((volatile unsigned int*)(0x42C90510UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A37          *((volatile unsigned int*)(0x42C90514UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A38          *((volatile unsigned int*)(0x42C90518UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A39          *((volatile unsigned int*)(0x42C9051CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A40          *((volatile unsigned int*)(0x42C90520UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A41          *((volatile unsigned int*)(0x42C90524UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A42          *((volatile unsigned int*)(0x42C90528UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A43          *((volatile unsigned int*)(0x42C9052CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A44          *((volatile unsigned int*)(0x42C90530UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A45          *((volatile unsigned int*)(0x42C90534UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A46          *((volatile unsigned int*)(0x42C90538UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_A47          *((volatile unsigned int*)(0x42C9053CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC0         *((volatile unsigned int*)(0x42C90560UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC1         *((volatile unsigned int*)(0x42C90564UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC2         *((volatile unsigned int*)(0x42C90568UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC3         *((volatile unsigned int*)(0x42C9056CUL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC4         *((volatile unsigned int*)(0x42C90570UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_MBC5         *((volatile unsigned int*)(0x42C90574UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_SA           *((volatile unsigned int*)(0x42C90578UL))
+#define bFM3_ETHERNET_MAC0_MAR21H_AE           *((volatile unsigned int*)(0x42C9057CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A0           *((volatile unsigned int*)(0x42C90580UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A1           *((volatile unsigned int*)(0x42C90584UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A2           *((volatile unsigned int*)(0x42C90588UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A3           *((volatile unsigned int*)(0x42C9058CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A4           *((volatile unsigned int*)(0x42C90590UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A5           *((volatile unsigned int*)(0x42C90594UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A6           *((volatile unsigned int*)(0x42C90598UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A7           *((volatile unsigned int*)(0x42C9059CUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A8           *((volatile unsigned int*)(0x42C905A0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A9           *((volatile unsigned int*)(0x42C905A4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A10          *((volatile unsigned int*)(0x42C905A8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A11          *((volatile unsigned int*)(0x42C905ACUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A12          *((volatile unsigned int*)(0x42C905B0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A13          *((volatile unsigned int*)(0x42C905B4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A14          *((volatile unsigned int*)(0x42C905B8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A15          *((volatile unsigned int*)(0x42C905BCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A16          *((volatile unsigned int*)(0x42C905C0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A17          *((volatile unsigned int*)(0x42C905C4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A18          *((volatile unsigned int*)(0x42C905C8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A19          *((volatile unsigned int*)(0x42C905CCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A20          *((volatile unsigned int*)(0x42C905D0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A21          *((volatile unsigned int*)(0x42C905D4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A22          *((volatile unsigned int*)(0x42C905D8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A23          *((volatile unsigned int*)(0x42C905DCUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A24          *((volatile unsigned int*)(0x42C905E0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A25          *((volatile unsigned int*)(0x42C905E4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A26          *((volatile unsigned int*)(0x42C905E8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A27          *((volatile unsigned int*)(0x42C905ECUL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A28          *((volatile unsigned int*)(0x42C905F0UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A29          *((volatile unsigned int*)(0x42C905F4UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A30          *((volatile unsigned int*)(0x42C905F8UL))
+#define bFM3_ETHERNET_MAC0_MAR21L_A31          *((volatile unsigned int*)(0x42C905FCUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A32          *((volatile unsigned int*)(0x42C90600UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A33          *((volatile unsigned int*)(0x42C90604UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A34          *((volatile unsigned int*)(0x42C90608UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A35          *((volatile unsigned int*)(0x42C9060CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A36          *((volatile unsigned int*)(0x42C90610UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A37          *((volatile unsigned int*)(0x42C90614UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A38          *((volatile unsigned int*)(0x42C90618UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A39          *((volatile unsigned int*)(0x42C9061CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A40          *((volatile unsigned int*)(0x42C90620UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A41          *((volatile unsigned int*)(0x42C90624UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A42          *((volatile unsigned int*)(0x42C90628UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A43          *((volatile unsigned int*)(0x42C9062CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A44          *((volatile unsigned int*)(0x42C90630UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A45          *((volatile unsigned int*)(0x42C90634UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A46          *((volatile unsigned int*)(0x42C90638UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_A47          *((volatile unsigned int*)(0x42C9063CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC0         *((volatile unsigned int*)(0x42C90660UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC1         *((volatile unsigned int*)(0x42C90664UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC2         *((volatile unsigned int*)(0x42C90668UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC3         *((volatile unsigned int*)(0x42C9066CUL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC4         *((volatile unsigned int*)(0x42C90670UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_MBC5         *((volatile unsigned int*)(0x42C90674UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_SA           *((volatile unsigned int*)(0x42C90678UL))
+#define bFM3_ETHERNET_MAC0_MAR22H_AE           *((volatile unsigned int*)(0x42C9067CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A0           *((volatile unsigned int*)(0x42C90680UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A1           *((volatile unsigned int*)(0x42C90684UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A2           *((volatile unsigned int*)(0x42C90688UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A3           *((volatile unsigned int*)(0x42C9068CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A4           *((volatile unsigned int*)(0x42C90690UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A5           *((volatile unsigned int*)(0x42C90694UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A6           *((volatile unsigned int*)(0x42C90698UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A7           *((volatile unsigned int*)(0x42C9069CUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A8           *((volatile unsigned int*)(0x42C906A0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A9           *((volatile unsigned int*)(0x42C906A4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A10          *((volatile unsigned int*)(0x42C906A8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A11          *((volatile unsigned int*)(0x42C906ACUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A12          *((volatile unsigned int*)(0x42C906B0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A13          *((volatile unsigned int*)(0x42C906B4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A14          *((volatile unsigned int*)(0x42C906B8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A15          *((volatile unsigned int*)(0x42C906BCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A16          *((volatile unsigned int*)(0x42C906C0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A17          *((volatile unsigned int*)(0x42C906C4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A18          *((volatile unsigned int*)(0x42C906C8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A19          *((volatile unsigned int*)(0x42C906CCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A20          *((volatile unsigned int*)(0x42C906D0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A21          *((volatile unsigned int*)(0x42C906D4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A22          *((volatile unsigned int*)(0x42C906D8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A23          *((volatile unsigned int*)(0x42C906DCUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A24          *((volatile unsigned int*)(0x42C906E0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A25          *((volatile unsigned int*)(0x42C906E4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A26          *((volatile unsigned int*)(0x42C906E8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A27          *((volatile unsigned int*)(0x42C906ECUL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A28          *((volatile unsigned int*)(0x42C906F0UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A29          *((volatile unsigned int*)(0x42C906F4UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A30          *((volatile unsigned int*)(0x42C906F8UL))
+#define bFM3_ETHERNET_MAC0_MAR22L_A31          *((volatile unsigned int*)(0x42C906FCUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A32          *((volatile unsigned int*)(0x42C90700UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A33          *((volatile unsigned int*)(0x42C90704UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A34          *((volatile unsigned int*)(0x42C90708UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A35          *((volatile unsigned int*)(0x42C9070CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A36          *((volatile unsigned int*)(0x42C90710UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A37          *((volatile unsigned int*)(0x42C90714UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A38          *((volatile unsigned int*)(0x42C90718UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A39          *((volatile unsigned int*)(0x42C9071CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A40          *((volatile unsigned int*)(0x42C90720UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A41          *((volatile unsigned int*)(0x42C90724UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A42          *((volatile unsigned int*)(0x42C90728UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A43          *((volatile unsigned int*)(0x42C9072CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A44          *((volatile unsigned int*)(0x42C90730UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A45          *((volatile unsigned int*)(0x42C90734UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A46          *((volatile unsigned int*)(0x42C90738UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_A47          *((volatile unsigned int*)(0x42C9073CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC0         *((volatile unsigned int*)(0x42C90760UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC1         *((volatile unsigned int*)(0x42C90764UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC2         *((volatile unsigned int*)(0x42C90768UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC3         *((volatile unsigned int*)(0x42C9076CUL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC4         *((volatile unsigned int*)(0x42C90770UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_MBC5         *((volatile unsigned int*)(0x42C90774UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_SA           *((volatile unsigned int*)(0x42C90778UL))
+#define bFM3_ETHERNET_MAC0_MAR23H_AE           *((volatile unsigned int*)(0x42C9077CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A0           *((volatile unsigned int*)(0x42C90780UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A1           *((volatile unsigned int*)(0x42C90784UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A2           *((volatile unsigned int*)(0x42C90788UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A3           *((volatile unsigned int*)(0x42C9078CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A4           *((volatile unsigned int*)(0x42C90790UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A5           *((volatile unsigned int*)(0x42C90794UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A6           *((volatile unsigned int*)(0x42C90798UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A7           *((volatile unsigned int*)(0x42C9079CUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A8           *((volatile unsigned int*)(0x42C907A0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A9           *((volatile unsigned int*)(0x42C907A4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A10          *((volatile unsigned int*)(0x42C907A8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A11          *((volatile unsigned int*)(0x42C907ACUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A12          *((volatile unsigned int*)(0x42C907B0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A13          *((volatile unsigned int*)(0x42C907B4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A14          *((volatile unsigned int*)(0x42C907B8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A15          *((volatile unsigned int*)(0x42C907BCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A16          *((volatile unsigned int*)(0x42C907C0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A17          *((volatile unsigned int*)(0x42C907C4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A18          *((volatile unsigned int*)(0x42C907C8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A19          *((volatile unsigned int*)(0x42C907CCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A20          *((volatile unsigned int*)(0x42C907D0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A21          *((volatile unsigned int*)(0x42C907D4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A22          *((volatile unsigned int*)(0x42C907D8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A23          *((volatile unsigned int*)(0x42C907DCUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A24          *((volatile unsigned int*)(0x42C907E0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A25          *((volatile unsigned int*)(0x42C907E4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A26          *((volatile unsigned int*)(0x42C907E8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A27          *((volatile unsigned int*)(0x42C907ECUL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A28          *((volatile unsigned int*)(0x42C907F0UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A29          *((volatile unsigned int*)(0x42C907F4UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A30          *((volatile unsigned int*)(0x42C907F8UL))
+#define bFM3_ETHERNET_MAC0_MAR23L_A31          *((volatile unsigned int*)(0x42C907FCUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A32          *((volatile unsigned int*)(0x42C90800UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A33          *((volatile unsigned int*)(0x42C90804UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A34          *((volatile unsigned int*)(0x42C90808UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A35          *((volatile unsigned int*)(0x42C9080CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A36          *((volatile unsigned int*)(0x42C90810UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A37          *((volatile unsigned int*)(0x42C90814UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A38          *((volatile unsigned int*)(0x42C90818UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A39          *((volatile unsigned int*)(0x42C9081CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A40          *((volatile unsigned int*)(0x42C90820UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A41          *((volatile unsigned int*)(0x42C90824UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A42          *((volatile unsigned int*)(0x42C90828UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A43          *((volatile unsigned int*)(0x42C9082CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A44          *((volatile unsigned int*)(0x42C90830UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A45          *((volatile unsigned int*)(0x42C90834UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A46          *((volatile unsigned int*)(0x42C90838UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_A47          *((volatile unsigned int*)(0x42C9083CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC0         *((volatile unsigned int*)(0x42C90860UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC1         *((volatile unsigned int*)(0x42C90864UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC2         *((volatile unsigned int*)(0x42C90868UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC3         *((volatile unsigned int*)(0x42C9086CUL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC4         *((volatile unsigned int*)(0x42C90870UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_MBC5         *((volatile unsigned int*)(0x42C90874UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_SA           *((volatile unsigned int*)(0x42C90878UL))
+#define bFM3_ETHERNET_MAC0_MAR24H_AE           *((volatile unsigned int*)(0x42C9087CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A0           *((volatile unsigned int*)(0x42C90880UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A1           *((volatile unsigned int*)(0x42C90884UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A2           *((volatile unsigned int*)(0x42C90888UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A3           *((volatile unsigned int*)(0x42C9088CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A4           *((volatile unsigned int*)(0x42C90890UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A5           *((volatile unsigned int*)(0x42C90894UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A6           *((volatile unsigned int*)(0x42C90898UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A7           *((volatile unsigned int*)(0x42C9089CUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A8           *((volatile unsigned int*)(0x42C908A0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A9           *((volatile unsigned int*)(0x42C908A4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A10          *((volatile unsigned int*)(0x42C908A8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A11          *((volatile unsigned int*)(0x42C908ACUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A12          *((volatile unsigned int*)(0x42C908B0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A13          *((volatile unsigned int*)(0x42C908B4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A14          *((volatile unsigned int*)(0x42C908B8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A15          *((volatile unsigned int*)(0x42C908BCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A16          *((volatile unsigned int*)(0x42C908C0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A17          *((volatile unsigned int*)(0x42C908C4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A18          *((volatile unsigned int*)(0x42C908C8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A19          *((volatile unsigned int*)(0x42C908CCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A20          *((volatile unsigned int*)(0x42C908D0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A21          *((volatile unsigned int*)(0x42C908D4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A22          *((volatile unsigned int*)(0x42C908D8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A23          *((volatile unsigned int*)(0x42C908DCUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A24          *((volatile unsigned int*)(0x42C908E0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A25          *((volatile unsigned int*)(0x42C908E4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A26          *((volatile unsigned int*)(0x42C908E8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A27          *((volatile unsigned int*)(0x42C908ECUL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A28          *((volatile unsigned int*)(0x42C908F0UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A29          *((volatile unsigned int*)(0x42C908F4UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A30          *((volatile unsigned int*)(0x42C908F8UL))
+#define bFM3_ETHERNET_MAC0_MAR24L_A31          *((volatile unsigned int*)(0x42C908FCUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A32          *((volatile unsigned int*)(0x42C90900UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A33          *((volatile unsigned int*)(0x42C90904UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A34          *((volatile unsigned int*)(0x42C90908UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A35          *((volatile unsigned int*)(0x42C9090CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A36          *((volatile unsigned int*)(0x42C90910UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A37          *((volatile unsigned int*)(0x42C90914UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A38          *((volatile unsigned int*)(0x42C90918UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A39          *((volatile unsigned int*)(0x42C9091CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A40          *((volatile unsigned int*)(0x42C90920UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A41          *((volatile unsigned int*)(0x42C90924UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A42          *((volatile unsigned int*)(0x42C90928UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A43          *((volatile unsigned int*)(0x42C9092CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A44          *((volatile unsigned int*)(0x42C90930UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A45          *((volatile unsigned int*)(0x42C90934UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A46          *((volatile unsigned int*)(0x42C90938UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_A47          *((volatile unsigned int*)(0x42C9093CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC0         *((volatile unsigned int*)(0x42C90960UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC1         *((volatile unsigned int*)(0x42C90964UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC2         *((volatile unsigned int*)(0x42C90968UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC3         *((volatile unsigned int*)(0x42C9096CUL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC4         *((volatile unsigned int*)(0x42C90970UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_MBC5         *((volatile unsigned int*)(0x42C90974UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_SA           *((volatile unsigned int*)(0x42C90978UL))
+#define bFM3_ETHERNET_MAC0_MAR25H_AE           *((volatile unsigned int*)(0x42C9097CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A0           *((volatile unsigned int*)(0x42C90980UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A1           *((volatile unsigned int*)(0x42C90984UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A2           *((volatile unsigned int*)(0x42C90988UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A3           *((volatile unsigned int*)(0x42C9098CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A4           *((volatile unsigned int*)(0x42C90990UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A5           *((volatile unsigned int*)(0x42C90994UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A6           *((volatile unsigned int*)(0x42C90998UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A7           *((volatile unsigned int*)(0x42C9099CUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A8           *((volatile unsigned int*)(0x42C909A0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A9           *((volatile unsigned int*)(0x42C909A4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A10          *((volatile unsigned int*)(0x42C909A8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A11          *((volatile unsigned int*)(0x42C909ACUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A12          *((volatile unsigned int*)(0x42C909B0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A13          *((volatile unsigned int*)(0x42C909B4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A14          *((volatile unsigned int*)(0x42C909B8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A15          *((volatile unsigned int*)(0x42C909BCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A16          *((volatile unsigned int*)(0x42C909C0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A17          *((volatile unsigned int*)(0x42C909C4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A18          *((volatile unsigned int*)(0x42C909C8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A19          *((volatile unsigned int*)(0x42C909CCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A20          *((volatile unsigned int*)(0x42C909D0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A21          *((volatile unsigned int*)(0x42C909D4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A22          *((volatile unsigned int*)(0x42C909D8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A23          *((volatile unsigned int*)(0x42C909DCUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A24          *((volatile unsigned int*)(0x42C909E0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A25          *((volatile unsigned int*)(0x42C909E4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A26          *((volatile unsigned int*)(0x42C909E8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A27          *((volatile unsigned int*)(0x42C909ECUL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A28          *((volatile unsigned int*)(0x42C909F0UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A29          *((volatile unsigned int*)(0x42C909F4UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A30          *((volatile unsigned int*)(0x42C909F8UL))
+#define bFM3_ETHERNET_MAC0_MAR25L_A31          *((volatile unsigned int*)(0x42C909FCUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A32          *((volatile unsigned int*)(0x42C90A00UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A33          *((volatile unsigned int*)(0x42C90A04UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A34          *((volatile unsigned int*)(0x42C90A08UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A35          *((volatile unsigned int*)(0x42C90A0CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A36          *((volatile unsigned int*)(0x42C90A10UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A37          *((volatile unsigned int*)(0x42C90A14UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A38          *((volatile unsigned int*)(0x42C90A18UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A39          *((volatile unsigned int*)(0x42C90A1CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A40          *((volatile unsigned int*)(0x42C90A20UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A41          *((volatile unsigned int*)(0x42C90A24UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A42          *((volatile unsigned int*)(0x42C90A28UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A43          *((volatile unsigned int*)(0x42C90A2CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A44          *((volatile unsigned int*)(0x42C90A30UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A45          *((volatile unsigned int*)(0x42C90A34UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A46          *((volatile unsigned int*)(0x42C90A38UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_A47          *((volatile unsigned int*)(0x42C90A3CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC0         *((volatile unsigned int*)(0x42C90A60UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC1         *((volatile unsigned int*)(0x42C90A64UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC2         *((volatile unsigned int*)(0x42C90A68UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC3         *((volatile unsigned int*)(0x42C90A6CUL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC4         *((volatile unsigned int*)(0x42C90A70UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_MBC5         *((volatile unsigned int*)(0x42C90A74UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_SA           *((volatile unsigned int*)(0x42C90A78UL))
+#define bFM3_ETHERNET_MAC0_MAR26H_AE           *((volatile unsigned int*)(0x42C90A7CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A0           *((volatile unsigned int*)(0x42C90A80UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A1           *((volatile unsigned int*)(0x42C90A84UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A2           *((volatile unsigned int*)(0x42C90A88UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A3           *((volatile unsigned int*)(0x42C90A8CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A4           *((volatile unsigned int*)(0x42C90A90UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A5           *((volatile unsigned int*)(0x42C90A94UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A6           *((volatile unsigned int*)(0x42C90A98UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A7           *((volatile unsigned int*)(0x42C90A9CUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A8           *((volatile unsigned int*)(0x42C90AA0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A9           *((volatile unsigned int*)(0x42C90AA4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A10          *((volatile unsigned int*)(0x42C90AA8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A11          *((volatile unsigned int*)(0x42C90AACUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A12          *((volatile unsigned int*)(0x42C90AB0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A13          *((volatile unsigned int*)(0x42C90AB4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A14          *((volatile unsigned int*)(0x42C90AB8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A15          *((volatile unsigned int*)(0x42C90ABCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A16          *((volatile unsigned int*)(0x42C90AC0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A17          *((volatile unsigned int*)(0x42C90AC4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A18          *((volatile unsigned int*)(0x42C90AC8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A19          *((volatile unsigned int*)(0x42C90ACCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A20          *((volatile unsigned int*)(0x42C90AD0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A21          *((volatile unsigned int*)(0x42C90AD4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A22          *((volatile unsigned int*)(0x42C90AD8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A23          *((volatile unsigned int*)(0x42C90ADCUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A24          *((volatile unsigned int*)(0x42C90AE0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A25          *((volatile unsigned int*)(0x42C90AE4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A26          *((volatile unsigned int*)(0x42C90AE8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A27          *((volatile unsigned int*)(0x42C90AECUL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A28          *((volatile unsigned int*)(0x42C90AF0UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A29          *((volatile unsigned int*)(0x42C90AF4UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A30          *((volatile unsigned int*)(0x42C90AF8UL))
+#define bFM3_ETHERNET_MAC0_MAR26L_A31          *((volatile unsigned int*)(0x42C90AFCUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A32          *((volatile unsigned int*)(0x42C90B00UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A33          *((volatile unsigned int*)(0x42C90B04UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A34          *((volatile unsigned int*)(0x42C90B08UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A35          *((volatile unsigned int*)(0x42C90B0CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A36          *((volatile unsigned int*)(0x42C90B10UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A37          *((volatile unsigned int*)(0x42C90B14UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A38          *((volatile unsigned int*)(0x42C90B18UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A39          *((volatile unsigned int*)(0x42C90B1CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A40          *((volatile unsigned int*)(0x42C90B20UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A41          *((volatile unsigned int*)(0x42C90B24UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A42          *((volatile unsigned int*)(0x42C90B28UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A43          *((volatile unsigned int*)(0x42C90B2CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A44          *((volatile unsigned int*)(0x42C90B30UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A45          *((volatile unsigned int*)(0x42C90B34UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A46          *((volatile unsigned int*)(0x42C90B38UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_A47          *((volatile unsigned int*)(0x42C90B3CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC0         *((volatile unsigned int*)(0x42C90B60UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC1         *((volatile unsigned int*)(0x42C90B64UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC2         *((volatile unsigned int*)(0x42C90B68UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC3         *((volatile unsigned int*)(0x42C90B6CUL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC4         *((volatile unsigned int*)(0x42C90B70UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_MBC5         *((volatile unsigned int*)(0x42C90B74UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_SA           *((volatile unsigned int*)(0x42C90B78UL))
+#define bFM3_ETHERNET_MAC0_MAR27H_AE           *((volatile unsigned int*)(0x42C90B7CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A0           *((volatile unsigned int*)(0x42C90B80UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A1           *((volatile unsigned int*)(0x42C90B84UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A2           *((volatile unsigned int*)(0x42C90B88UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A3           *((volatile unsigned int*)(0x42C90B8CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A4           *((volatile unsigned int*)(0x42C90B90UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A5           *((volatile unsigned int*)(0x42C90B94UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A6           *((volatile unsigned int*)(0x42C90B98UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A7           *((volatile unsigned int*)(0x42C90B9CUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A8           *((volatile unsigned int*)(0x42C90BA0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A9           *((volatile unsigned int*)(0x42C90BA4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A10          *((volatile unsigned int*)(0x42C90BA8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A11          *((volatile unsigned int*)(0x42C90BACUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A12          *((volatile unsigned int*)(0x42C90BB0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A13          *((volatile unsigned int*)(0x42C90BB4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A14          *((volatile unsigned int*)(0x42C90BB8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A15          *((volatile unsigned int*)(0x42C90BBCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A16          *((volatile unsigned int*)(0x42C90BC0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A17          *((volatile unsigned int*)(0x42C90BC4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A18          *((volatile unsigned int*)(0x42C90BC8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A19          *((volatile unsigned int*)(0x42C90BCCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A20          *((volatile unsigned int*)(0x42C90BD0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A21          *((volatile unsigned int*)(0x42C90BD4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A22          *((volatile unsigned int*)(0x42C90BD8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A23          *((volatile unsigned int*)(0x42C90BDCUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A24          *((volatile unsigned int*)(0x42C90BE0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A25          *((volatile unsigned int*)(0x42C90BE4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A26          *((volatile unsigned int*)(0x42C90BE8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A27          *((volatile unsigned int*)(0x42C90BECUL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A28          *((volatile unsigned int*)(0x42C90BF0UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A29          *((volatile unsigned int*)(0x42C90BF4UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A30          *((volatile unsigned int*)(0x42C90BF8UL))
+#define bFM3_ETHERNET_MAC0_MAR27L_A31          *((volatile unsigned int*)(0x42C90BFCUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A32          *((volatile unsigned int*)(0x42C90C00UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A33          *((volatile unsigned int*)(0x42C90C04UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A34          *((volatile unsigned int*)(0x42C90C08UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A35          *((volatile unsigned int*)(0x42C90C0CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A36          *((volatile unsigned int*)(0x42C90C10UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A37          *((volatile unsigned int*)(0x42C90C14UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A38          *((volatile unsigned int*)(0x42C90C18UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A39          *((volatile unsigned int*)(0x42C90C1CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A40          *((volatile unsigned int*)(0x42C90C20UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A41          *((volatile unsigned int*)(0x42C90C24UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A42          *((volatile unsigned int*)(0x42C90C28UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A43          *((volatile unsigned int*)(0x42C90C2CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A44          *((volatile unsigned int*)(0x42C90C30UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A45          *((volatile unsigned int*)(0x42C90C34UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A46          *((volatile unsigned int*)(0x42C90C38UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_A47          *((volatile unsigned int*)(0x42C90C3CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC0         *((volatile unsigned int*)(0x42C90C60UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC1         *((volatile unsigned int*)(0x42C90C64UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC2         *((volatile unsigned int*)(0x42C90C68UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC3         *((volatile unsigned int*)(0x42C90C6CUL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC4         *((volatile unsigned int*)(0x42C90C70UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_MBC5         *((volatile unsigned int*)(0x42C90C74UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_SA           *((volatile unsigned int*)(0x42C90C78UL))
+#define bFM3_ETHERNET_MAC0_MAR28H_AE           *((volatile unsigned int*)(0x42C90C7CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A0           *((volatile unsigned int*)(0x42C90C80UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A1           *((volatile unsigned int*)(0x42C90C84UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A2           *((volatile unsigned int*)(0x42C90C88UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A3           *((volatile unsigned int*)(0x42C90C8CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A4           *((volatile unsigned int*)(0x42C90C90UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A5           *((volatile unsigned int*)(0x42C90C94UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A6           *((volatile unsigned int*)(0x42C90C98UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A7           *((volatile unsigned int*)(0x42C90C9CUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A8           *((volatile unsigned int*)(0x42C90CA0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A9           *((volatile unsigned int*)(0x42C90CA4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A10          *((volatile unsigned int*)(0x42C90CA8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A11          *((volatile unsigned int*)(0x42C90CACUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A12          *((volatile unsigned int*)(0x42C90CB0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A13          *((volatile unsigned int*)(0x42C90CB4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A14          *((volatile unsigned int*)(0x42C90CB8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A15          *((volatile unsigned int*)(0x42C90CBCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A16          *((volatile unsigned int*)(0x42C90CC0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A17          *((volatile unsigned int*)(0x42C90CC4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A18          *((volatile unsigned int*)(0x42C90CC8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A19          *((volatile unsigned int*)(0x42C90CCCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A20          *((volatile unsigned int*)(0x42C90CD0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A21          *((volatile unsigned int*)(0x42C90CD4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A22          *((volatile unsigned int*)(0x42C90CD8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A23          *((volatile unsigned int*)(0x42C90CDCUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A24          *((volatile unsigned int*)(0x42C90CE0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A25          *((volatile unsigned int*)(0x42C90CE4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A26          *((volatile unsigned int*)(0x42C90CE8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A27          *((volatile unsigned int*)(0x42C90CECUL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A28          *((volatile unsigned int*)(0x42C90CF0UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A29          *((volatile unsigned int*)(0x42C90CF4UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A30          *((volatile unsigned int*)(0x42C90CF8UL))
+#define bFM3_ETHERNET_MAC0_MAR28L_A31          *((volatile unsigned int*)(0x42C90CFCUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A32          *((volatile unsigned int*)(0x42C90D00UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A33          *((volatile unsigned int*)(0x42C90D04UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A34          *((volatile unsigned int*)(0x42C90D08UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A35          *((volatile unsigned int*)(0x42C90D0CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A36          *((volatile unsigned int*)(0x42C90D10UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A37          *((volatile unsigned int*)(0x42C90D14UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A38          *((volatile unsigned int*)(0x42C90D18UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A39          *((volatile unsigned int*)(0x42C90D1CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A40          *((volatile unsigned int*)(0x42C90D20UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A41          *((volatile unsigned int*)(0x42C90D24UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A42          *((volatile unsigned int*)(0x42C90D28UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A43          *((volatile unsigned int*)(0x42C90D2CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A44          *((volatile unsigned int*)(0x42C90D30UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A45          *((volatile unsigned int*)(0x42C90D34UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A46          *((volatile unsigned int*)(0x42C90D38UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_A47          *((volatile unsigned int*)(0x42C90D3CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC0         *((volatile unsigned int*)(0x42C90D60UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC1         *((volatile unsigned int*)(0x42C90D64UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC2         *((volatile unsigned int*)(0x42C90D68UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC3         *((volatile unsigned int*)(0x42C90D6CUL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC4         *((volatile unsigned int*)(0x42C90D70UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_MBC5         *((volatile unsigned int*)(0x42C90D74UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_SA           *((volatile unsigned int*)(0x42C90D78UL))
+#define bFM3_ETHERNET_MAC0_MAR29H_AE           *((volatile unsigned int*)(0x42C90D7CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A0           *((volatile unsigned int*)(0x42C90D80UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A1           *((volatile unsigned int*)(0x42C90D84UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A2           *((volatile unsigned int*)(0x42C90D88UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A3           *((volatile unsigned int*)(0x42C90D8CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A4           *((volatile unsigned int*)(0x42C90D90UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A5           *((volatile unsigned int*)(0x42C90D94UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A6           *((volatile unsigned int*)(0x42C90D98UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A7           *((volatile unsigned int*)(0x42C90D9CUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A8           *((volatile unsigned int*)(0x42C90DA0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A9           *((volatile unsigned int*)(0x42C90DA4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A10          *((volatile unsigned int*)(0x42C90DA8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A11          *((volatile unsigned int*)(0x42C90DACUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A12          *((volatile unsigned int*)(0x42C90DB0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A13          *((volatile unsigned int*)(0x42C90DB4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A14          *((volatile unsigned int*)(0x42C90DB8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A15          *((volatile unsigned int*)(0x42C90DBCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A16          *((volatile unsigned int*)(0x42C90DC0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A17          *((volatile unsigned int*)(0x42C90DC4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A18          *((volatile unsigned int*)(0x42C90DC8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A19          *((volatile unsigned int*)(0x42C90DCCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A20          *((volatile unsigned int*)(0x42C90DD0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A21          *((volatile unsigned int*)(0x42C90DD4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A22          *((volatile unsigned int*)(0x42C90DD8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A23          *((volatile unsigned int*)(0x42C90DDCUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A24          *((volatile unsigned int*)(0x42C90DE0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A25          *((volatile unsigned int*)(0x42C90DE4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A26          *((volatile unsigned int*)(0x42C90DE8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A27          *((volatile unsigned int*)(0x42C90DECUL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A28          *((volatile unsigned int*)(0x42C90DF0UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A29          *((volatile unsigned int*)(0x42C90DF4UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A30          *((volatile unsigned int*)(0x42C90DF8UL))
+#define bFM3_ETHERNET_MAC0_MAR29L_A31          *((volatile unsigned int*)(0x42C90DFCUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A32          *((volatile unsigned int*)(0x42C90E00UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A33          *((volatile unsigned int*)(0x42C90E04UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A34          *((volatile unsigned int*)(0x42C90E08UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A35          *((volatile unsigned int*)(0x42C90E0CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A36          *((volatile unsigned int*)(0x42C90E10UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A37          *((volatile unsigned int*)(0x42C90E14UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A38          *((volatile unsigned int*)(0x42C90E18UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A39          *((volatile unsigned int*)(0x42C90E1CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A40          *((volatile unsigned int*)(0x42C90E20UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A41          *((volatile unsigned int*)(0x42C90E24UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A42          *((volatile unsigned int*)(0x42C90E28UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A43          *((volatile unsigned int*)(0x42C90E2CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A44          *((volatile unsigned int*)(0x42C90E30UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A45          *((volatile unsigned int*)(0x42C90E34UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A46          *((volatile unsigned int*)(0x42C90E38UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_A47          *((volatile unsigned int*)(0x42C90E3CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC0         *((volatile unsigned int*)(0x42C90E60UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC1         *((volatile unsigned int*)(0x42C90E64UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC2         *((volatile unsigned int*)(0x42C90E68UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC3         *((volatile unsigned int*)(0x42C90E6CUL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC4         *((volatile unsigned int*)(0x42C90E70UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_MBC5         *((volatile unsigned int*)(0x42C90E74UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_SA           *((volatile unsigned int*)(0x42C90E78UL))
+#define bFM3_ETHERNET_MAC0_MAR30H_AE           *((volatile unsigned int*)(0x42C90E7CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A0           *((volatile unsigned int*)(0x42C90E80UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A1           *((volatile unsigned int*)(0x42C90E84UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A2           *((volatile unsigned int*)(0x42C90E88UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A3           *((volatile unsigned int*)(0x42C90E8CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A4           *((volatile unsigned int*)(0x42C90E90UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A5           *((volatile unsigned int*)(0x42C90E94UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A6           *((volatile unsigned int*)(0x42C90E98UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A7           *((volatile unsigned int*)(0x42C90E9CUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A8           *((volatile unsigned int*)(0x42C90EA0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A9           *((volatile unsigned int*)(0x42C90EA4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A10          *((volatile unsigned int*)(0x42C90EA8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A11          *((volatile unsigned int*)(0x42C90EACUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A12          *((volatile unsigned int*)(0x42C90EB0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A13          *((volatile unsigned int*)(0x42C90EB4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A14          *((volatile unsigned int*)(0x42C90EB8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A15          *((volatile unsigned int*)(0x42C90EBCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A16          *((volatile unsigned int*)(0x42C90EC0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A17          *((volatile unsigned int*)(0x42C90EC4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A18          *((volatile unsigned int*)(0x42C90EC8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A19          *((volatile unsigned int*)(0x42C90ECCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A20          *((volatile unsigned int*)(0x42C90ED0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A21          *((volatile unsigned int*)(0x42C90ED4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A22          *((volatile unsigned int*)(0x42C90ED8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A23          *((volatile unsigned int*)(0x42C90EDCUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A24          *((volatile unsigned int*)(0x42C90EE0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A25          *((volatile unsigned int*)(0x42C90EE4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A26          *((volatile unsigned int*)(0x42C90EE8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A27          *((volatile unsigned int*)(0x42C90EECUL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A28          *((volatile unsigned int*)(0x42C90EF0UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A29          *((volatile unsigned int*)(0x42C90EF4UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A30          *((volatile unsigned int*)(0x42C90EF8UL))
+#define bFM3_ETHERNET_MAC0_MAR30L_A31          *((volatile unsigned int*)(0x42C90EFCUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A32          *((volatile unsigned int*)(0x42C90F00UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A33          *((volatile unsigned int*)(0x42C90F04UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A34          *((volatile unsigned int*)(0x42C90F08UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A35          *((volatile unsigned int*)(0x42C90F0CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A36          *((volatile unsigned int*)(0x42C90F10UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A37          *((volatile unsigned int*)(0x42C90F14UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A38          *((volatile unsigned int*)(0x42C90F18UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A39          *((volatile unsigned int*)(0x42C90F1CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A40          *((volatile unsigned int*)(0x42C90F20UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A41          *((volatile unsigned int*)(0x42C90F24UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A42          *((volatile unsigned int*)(0x42C90F28UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A43          *((volatile unsigned int*)(0x42C90F2CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A44          *((volatile unsigned int*)(0x42C90F30UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A45          *((volatile unsigned int*)(0x42C90F34UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A46          *((volatile unsigned int*)(0x42C90F38UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_A47          *((volatile unsigned int*)(0x42C90F3CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC0         *((volatile unsigned int*)(0x42C90F60UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC1         *((volatile unsigned int*)(0x42C90F64UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC2         *((volatile unsigned int*)(0x42C90F68UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC3         *((volatile unsigned int*)(0x42C90F6CUL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC4         *((volatile unsigned int*)(0x42C90F70UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_MBC5         *((volatile unsigned int*)(0x42C90F74UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_SA           *((volatile unsigned int*)(0x42C90F78UL))
+#define bFM3_ETHERNET_MAC0_MAR31H_AE           *((volatile unsigned int*)(0x42C90F7CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A0           *((volatile unsigned int*)(0x42C90F80UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A1           *((volatile unsigned int*)(0x42C90F84UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A2           *((volatile unsigned int*)(0x42C90F88UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A3           *((volatile unsigned int*)(0x42C90F8CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A4           *((volatile unsigned int*)(0x42C90F90UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A5           *((volatile unsigned int*)(0x42C90F94UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A6           *((volatile unsigned int*)(0x42C90F98UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A7           *((volatile unsigned int*)(0x42C90F9CUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A8           *((volatile unsigned int*)(0x42C90FA0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A9           *((volatile unsigned int*)(0x42C90FA4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A10          *((volatile unsigned int*)(0x42C90FA8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A11          *((volatile unsigned int*)(0x42C90FACUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A12          *((volatile unsigned int*)(0x42C90FB0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A13          *((volatile unsigned int*)(0x42C90FB4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A14          *((volatile unsigned int*)(0x42C90FB8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A15          *((volatile unsigned int*)(0x42C90FBCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A16          *((volatile unsigned int*)(0x42C90FC0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A17          *((volatile unsigned int*)(0x42C90FC4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A18          *((volatile unsigned int*)(0x42C90FC8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A19          *((volatile unsigned int*)(0x42C90FCCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A20          *((volatile unsigned int*)(0x42C90FD0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A21          *((volatile unsigned int*)(0x42C90FD4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A22          *((volatile unsigned int*)(0x42C90FD8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A23          *((volatile unsigned int*)(0x42C90FDCUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A24          *((volatile unsigned int*)(0x42C90FE0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A25          *((volatile unsigned int*)(0x42C90FE4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A26          *((volatile unsigned int*)(0x42C90FE8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A27          *((volatile unsigned int*)(0x42C90FECUL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A28          *((volatile unsigned int*)(0x42C90FF0UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A29          *((volatile unsigned int*)(0x42C90FF4UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A30          *((volatile unsigned int*)(0x42C90FF8UL))
+#define bFM3_ETHERNET_MAC0_MAR31L_A31          *((volatile unsigned int*)(0x42C90FFCUL))
+#define bFM3_ETHERNET_MAC0_BMR_SWR             *((volatile unsigned int*)(0x42CA0000UL))
+#define bFM3_ETHERNET_MAC0_BMR_DA              *((volatile unsigned int*)(0x42CA0004UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL0            *((volatile unsigned int*)(0x42CA0008UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL1            *((volatile unsigned int*)(0x42CA000CUL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL2            *((volatile unsigned int*)(0x42CA0010UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL3            *((volatile unsigned int*)(0x42CA0014UL))
+#define bFM3_ETHERNET_MAC0_BMR_DSL4            *((volatile unsigned int*)(0x42CA0018UL))
+#define bFM3_ETHERNET_MAC0_BMR_ATDS            *((volatile unsigned int*)(0x42CA001CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL0            *((volatile unsigned int*)(0x42CA0020UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL1            *((volatile unsigned int*)(0x42CA0024UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL2            *((volatile unsigned int*)(0x42CA0028UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL3            *((volatile unsigned int*)(0x42CA002CUL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL4            *((volatile unsigned int*)(0x42CA0030UL))
+#define bFM3_ETHERNET_MAC0_BMR_PBL5            *((volatile unsigned int*)(0x42CA0034UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR0             *((volatile unsigned int*)(0x42CA0038UL))
+#define bFM3_ETHERNET_MAC0_BMR_PR1             *((volatile unsigned int*)(0x42CA003CUL))
+#define bFM3_ETHERNET_MAC0_BMR_FB              *((volatile unsigned int*)(0x42CA0040UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL0           *((volatile unsigned int*)(0x42CA0044UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL1           *((volatile unsigned int*)(0x42CA0048UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL2           *((volatile unsigned int*)(0x42CA004CUL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL3           *((volatile unsigned int*)(0x42CA0050UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL4           *((volatile unsigned int*)(0x42CA0054UL))
+#define bFM3_ETHERNET_MAC0_BMR_RPBL5           *((volatile unsigned int*)(0x42CA0058UL))
+#define bFM3_ETHERNET_MAC0_BMR_USP             *((volatile unsigned int*)(0x42CA005CUL))
+#define bFM3_ETHERNET_MAC0_BMR_8XPBL           *((volatile unsigned int*)(0x42CA0060UL))
+#define bFM3_ETHERNET_MAC0_BMR_AAL             *((volatile unsigned int*)(0x42CA0064UL))
+#define bFM3_ETHERNET_MAC0_BMR_MB              *((volatile unsigned int*)(0x42CA0068UL))
+#define bFM3_ETHERNET_MAC0_BMR_TXPR            *((volatile unsigned int*)(0x42CA006CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD0           *((volatile unsigned int*)(0x42CA0080UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD1           *((volatile unsigned int*)(0x42CA0084UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD2           *((volatile unsigned int*)(0x42CA0088UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD3           *((volatile unsigned int*)(0x42CA008CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD4           *((volatile unsigned int*)(0x42CA0090UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD5           *((volatile unsigned int*)(0x42CA0094UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD6           *((volatile unsigned int*)(0x42CA0098UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD7           *((volatile unsigned int*)(0x42CA009CUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD8           *((volatile unsigned int*)(0x42CA00A0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD9           *((volatile unsigned int*)(0x42CA00A4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD10          *((volatile unsigned int*)(0x42CA00A8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD11          *((volatile unsigned int*)(0x42CA00ACUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD12          *((volatile unsigned int*)(0x42CA00B0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD13          *((volatile unsigned int*)(0x42CA00B4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD14          *((volatile unsigned int*)(0x42CA00B8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD15          *((volatile unsigned int*)(0x42CA00BCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD16          *((volatile unsigned int*)(0x42CA00C0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD17          *((volatile unsigned int*)(0x42CA00C4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD18          *((volatile unsigned int*)(0x42CA00C8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD19          *((volatile unsigned int*)(0x42CA00CCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD20          *((volatile unsigned int*)(0x42CA00D0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD21          *((volatile unsigned int*)(0x42CA00D4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD22          *((volatile unsigned int*)(0x42CA00D8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD23          *((volatile unsigned int*)(0x42CA00DCUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD24          *((volatile unsigned int*)(0x42CA00E0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD25          *((volatile unsigned int*)(0x42CA00E4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD26          *((volatile unsigned int*)(0x42CA00E8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD27          *((volatile unsigned int*)(0x42CA00ECUL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD28          *((volatile unsigned int*)(0x42CA00F0UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD29          *((volatile unsigned int*)(0x42CA00F4UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD30          *((volatile unsigned int*)(0x42CA00F8UL))
+#define bFM3_ETHERNET_MAC0_TPDR_TPD31          *((volatile unsigned int*)(0x42CA00FCUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD0           *((volatile unsigned int*)(0x42CA0100UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD1           *((volatile unsigned int*)(0x42CA0104UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD2           *((volatile unsigned int*)(0x42CA0108UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD3           *((volatile unsigned int*)(0x42CA010CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD4           *((volatile unsigned int*)(0x42CA0110UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD5           *((volatile unsigned int*)(0x42CA0114UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD6           *((volatile unsigned int*)(0x42CA0118UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD7           *((volatile unsigned int*)(0x42CA011CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD8           *((volatile unsigned int*)(0x42CA0120UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD9           *((volatile unsigned int*)(0x42CA0124UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD10          *((volatile unsigned int*)(0x42CA0128UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD11          *((volatile unsigned int*)(0x42CA012CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD12          *((volatile unsigned int*)(0x42CA0130UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD13          *((volatile unsigned int*)(0x42CA0134UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD14          *((volatile unsigned int*)(0x42CA0138UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD15          *((volatile unsigned int*)(0x42CA013CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD16          *((volatile unsigned int*)(0x42CA0140UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD17          *((volatile unsigned int*)(0x42CA0144UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD18          *((volatile unsigned int*)(0x42CA0148UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD19          *((volatile unsigned int*)(0x42CA014CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD20          *((volatile unsigned int*)(0x42CA0150UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD21          *((volatile unsigned int*)(0x42CA0154UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD22          *((volatile unsigned int*)(0x42CA0158UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD23          *((volatile unsigned int*)(0x42CA015CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD24          *((volatile unsigned int*)(0x42CA0160UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD25          *((volatile unsigned int*)(0x42CA0164UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD26          *((volatile unsigned int*)(0x42CA0168UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD27          *((volatile unsigned int*)(0x42CA016CUL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD28          *((volatile unsigned int*)(0x42CA0170UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD29          *((volatile unsigned int*)(0x42CA0174UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD30          *((volatile unsigned int*)(0x42CA0178UL))
+#define bFM3_ETHERNET_MAC0_RPDR_RPD31          *((volatile unsigned int*)(0x42CA017CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL2          *((volatile unsigned int*)(0x42CA0188UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL3          *((volatile unsigned int*)(0x42CA018CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL4          *((volatile unsigned int*)(0x42CA0190UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL5          *((volatile unsigned int*)(0x42CA0194UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL6          *((volatile unsigned int*)(0x42CA0198UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL7          *((volatile unsigned int*)(0x42CA019CUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL8          *((volatile unsigned int*)(0x42CA01A0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL9          *((volatile unsigned int*)(0x42CA01A4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL10         *((volatile unsigned int*)(0x42CA01A8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL11         *((volatile unsigned int*)(0x42CA01ACUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL12         *((volatile unsigned int*)(0x42CA01B0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL13         *((volatile unsigned int*)(0x42CA01B4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL14         *((volatile unsigned int*)(0x42CA01B8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL15         *((volatile unsigned int*)(0x42CA01BCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL16         *((volatile unsigned int*)(0x42CA01C0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL17         *((volatile unsigned int*)(0x42CA01C4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL18         *((volatile unsigned int*)(0x42CA01C8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL19         *((volatile unsigned int*)(0x42CA01CCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL20         *((volatile unsigned int*)(0x42CA01D0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL21         *((volatile unsigned int*)(0x42CA01D4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL22         *((volatile unsigned int*)(0x42CA01D8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL23         *((volatile unsigned int*)(0x42CA01DCUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL24         *((volatile unsigned int*)(0x42CA01E0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL25         *((volatile unsigned int*)(0x42CA01E4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL26         *((volatile unsigned int*)(0x42CA01E8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL27         *((volatile unsigned int*)(0x42CA01ECUL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL28         *((volatile unsigned int*)(0x42CA01F0UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL29         *((volatile unsigned int*)(0x42CA01F4UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL30         *((volatile unsigned int*)(0x42CA01F8UL))
+#define bFM3_ETHERNET_MAC0_RDLAR_SRL31         *((volatile unsigned int*)(0x42CA01FCUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL2          *((volatile unsigned int*)(0x42CA0208UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL3          *((volatile unsigned int*)(0x42CA020CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL4          *((volatile unsigned int*)(0x42CA0210UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL5          *((volatile unsigned int*)(0x42CA0214UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL6          *((volatile unsigned int*)(0x42CA0218UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL7          *((volatile unsigned int*)(0x42CA021CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL8          *((volatile unsigned int*)(0x42CA0220UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL9          *((volatile unsigned int*)(0x42CA0224UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL10         *((volatile unsigned int*)(0x42CA0228UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL11         *((volatile unsigned int*)(0x42CA022CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL12         *((volatile unsigned int*)(0x42CA0230UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL13         *((volatile unsigned int*)(0x42CA0234UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL14         *((volatile unsigned int*)(0x42CA0238UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL15         *((volatile unsigned int*)(0x42CA023CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL16         *((volatile unsigned int*)(0x42CA0240UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL17         *((volatile unsigned int*)(0x42CA0244UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL18         *((volatile unsigned int*)(0x42CA0248UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL19         *((volatile unsigned int*)(0x42CA024CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL20         *((volatile unsigned int*)(0x42CA0250UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL21         *((volatile unsigned int*)(0x42CA0254UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL22         *((volatile unsigned int*)(0x42CA0258UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL23         *((volatile unsigned int*)(0x42CA025CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL24         *((volatile unsigned int*)(0x42CA0260UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL25         *((volatile unsigned int*)(0x42CA0264UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL26         *((volatile unsigned int*)(0x42CA0268UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL27         *((volatile unsigned int*)(0x42CA026CUL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL28         *((volatile unsigned int*)(0x42CA0270UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL29         *((volatile unsigned int*)(0x42CA0274UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL30         *((volatile unsigned int*)(0x42CA0278UL))
+#define bFM3_ETHERNET_MAC0_TDLAR_STL31         *((volatile unsigned int*)(0x42CA027CUL))
+#define bFM3_ETHERNET_MAC0_SR_TI               *((volatile unsigned int*)(0x42CA0280UL))
+#define bFM3_ETHERNET_MAC0_SR_TPS              *((volatile unsigned int*)(0x42CA0284UL))
+#define bFM3_ETHERNET_MAC0_SR_TU               *((volatile unsigned int*)(0x42CA0288UL))
+#define bFM3_ETHERNET_MAC0_SR_TJT              *((volatile unsigned int*)(0x42CA028CUL))
+#define bFM3_ETHERNET_MAC0_SR_OVF              *((volatile unsigned int*)(0x42CA0290UL))
+#define bFM3_ETHERNET_MAC0_SR_UNF              *((volatile unsigned int*)(0x42CA0294UL))
+#define bFM3_ETHERNET_MAC0_SR_RI               *((volatile unsigned int*)(0x42CA0298UL))
+#define bFM3_ETHERNET_MAC0_SR_RU               *((volatile unsigned int*)(0x42CA029CUL))
+#define bFM3_ETHERNET_MAC0_SR_RPS              *((volatile unsigned int*)(0x42CA02A0UL))
+#define bFM3_ETHERNET_MAC0_SR_RWT              *((volatile unsigned int*)(0x42CA02A4UL))
+#define bFM3_ETHERNET_MAC0_SR_ETI              *((volatile unsigned int*)(0x42CA02A8UL))
+#define bFM3_ETHERNET_MAC0_SR_FBI              *((volatile unsigned int*)(0x42CA02B4UL))
+#define bFM3_ETHERNET_MAC0_SR_ERI              *((volatile unsigned int*)(0x42CA02B8UL))
+#define bFM3_ETHERNET_MAC0_SR_AIS              *((volatile unsigned int*)(0x42CA02BCUL))
+#define bFM3_ETHERNET_MAC0_SR_NIS              *((volatile unsigned int*)(0x42CA02C0UL))
+#define bFM3_ETHERNET_MAC0_SR_RS0              *((volatile unsigned int*)(0x42CA02C4UL))
+#define bFM3_ETHERNET_MAC0_SR_RS1              *((volatile unsigned int*)(0x42CA02C8UL))
+#define bFM3_ETHERNET_MAC0_SR_RS2              *((volatile unsigned int*)(0x42CA02CCUL))
+#define bFM3_ETHERNET_MAC0_SR_TS0              *((volatile unsigned int*)(0x42CA02D0UL))
+#define bFM3_ETHERNET_MAC0_SR_TS1              *((volatile unsigned int*)(0x42CA02D4UL))
+#define bFM3_ETHERNET_MAC0_SR_TS2              *((volatile unsigned int*)(0x42CA02D8UL))
+#define bFM3_ETHERNET_MAC0_SR_EB0              *((volatile unsigned int*)(0x42CA02DCUL))
+#define bFM3_ETHERNET_MAC0_SR_EB1              *((volatile unsigned int*)(0x42CA02E0UL))
+#define bFM3_ETHERNET_MAC0_SR_EB2              *((volatile unsigned int*)(0x42CA02E4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLI              *((volatile unsigned int*)(0x42CA02E8UL))
+#define bFM3_ETHERNET_MAC0_SR_GMI              *((volatile unsigned int*)(0x42CA02ECUL))
+#define bFM3_ETHERNET_MAC0_SR_GPI              *((volatile unsigned int*)(0x42CA02F0UL))
+#define bFM3_ETHERNET_MAC0_SR_TTI              *((volatile unsigned int*)(0x42CA02F4UL))
+#define bFM3_ETHERNET_MAC0_SR_GLPII            *((volatile unsigned int*)(0x42CA02F8UL))
+#define bFM3_ETHERNET_MAC0_OMR_SR              *((volatile unsigned int*)(0x42CA0304UL))
+#define bFM3_ETHERNET_MAC0_OMR_OSF             *((volatile unsigned int*)(0x42CA0308UL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC0            *((volatile unsigned int*)(0x42CA030CUL))
+#define bFM3_ETHERNET_MAC0_OMR_RTC1            *((volatile unsigned int*)(0x42CA0310UL))
+#define bFM3_ETHERNET_MAC0_OMR_FUF             *((volatile unsigned int*)(0x42CA0318UL))
+#define bFM3_ETHERNET_MAC0_OMR_FEF             *((volatile unsigned int*)(0x42CA031CUL))
+#define bFM3_ETHERNET_MAC0_OMR_ST              *((volatile unsigned int*)(0x42CA0334UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC0            *((volatile unsigned int*)(0x42CA0338UL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC1            *((volatile unsigned int*)(0x42CA033CUL))
+#define bFM3_ETHERNET_MAC0_OMR_TTC2            *((volatile unsigned int*)(0x42CA0340UL))
+#define bFM3_ETHERNET_MAC0_OMR_FTF             *((volatile unsigned int*)(0x42CA0350UL))
+#define bFM3_ETHERNET_MAC0_OMR_TSF             *((volatile unsigned int*)(0x42CA0354UL))
+#define bFM3_ETHERNET_MAC0_OMR_DFF             *((volatile unsigned int*)(0x42CA0360UL))
+#define bFM3_ETHERNET_MAC0_OMR_RSF             *((volatile unsigned int*)(0x42CA0364UL))
+#define bFM3_ETHERNET_MAC0_OMR_DT              *((volatile unsigned int*)(0x42CA0368UL))
+#define bFM3_ETHERNET_MAC0_IER_TIE             *((volatile unsigned int*)(0x42CA0380UL))
+#define bFM3_ETHERNET_MAC0_IER_TSE             *((volatile unsigned int*)(0x42CA0384UL))
+#define bFM3_ETHERNET_MAC0_IER_TUE             *((volatile unsigned int*)(0x42CA0388UL))
+#define bFM3_ETHERNET_MAC0_IER_TJE             *((volatile unsigned int*)(0x42CA038CUL))
+#define bFM3_ETHERNET_MAC0_IER_OVE             *((volatile unsigned int*)(0x42CA0390UL))
+#define bFM3_ETHERNET_MAC0_IER_UNE             *((volatile unsigned int*)(0x42CA0394UL))
+#define bFM3_ETHERNET_MAC0_IER_RIE             *((volatile unsigned int*)(0x42CA0398UL))
+#define bFM3_ETHERNET_MAC0_IER_RUE             *((volatile unsigned int*)(0x42CA039CUL))
+#define bFM3_ETHERNET_MAC0_IER_RSE             *((volatile unsigned int*)(0x42CA03A0UL))
+#define bFM3_ETHERNET_MAC0_IER_RWE             *((volatile unsigned int*)(0x42CA03A4UL))
+#define bFM3_ETHERNET_MAC0_IER_ETE             *((volatile unsigned int*)(0x42CA03A8UL))
+#define bFM3_ETHERNET_MAC0_IER_FBE             *((volatile unsigned int*)(0x42CA03B4UL))
+#define bFM3_ETHERNET_MAC0_IER_ERE             *((volatile unsigned int*)(0x42CA03B8UL))
+#define bFM3_ETHERNET_MAC0_IER_AIE             *((volatile unsigned int*)(0x42CA03BCUL))
+#define bFM3_ETHERNET_MAC0_IER_NIE             *((volatile unsigned int*)(0x42CA03C0UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42CA0400UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42CA0404UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42CA0408UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42CA040CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42CA0410UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42CA0414UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42CA0418UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42CA041CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42CA0420UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42CA0424UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42CA0428UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42CA042CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42CA0430UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42CA0434UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42CA0438UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42CA043CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42CA0440UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42CA0444UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42CA0448UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42CA044CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42CA0450UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42CA0454UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42CA0458UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42CA045CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42CA0460UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42CA0464UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42CA0468UL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42CA046CUL))
+#define bFM3_ETHERNET_MAC0_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42CA0470UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT0         *((volatile unsigned int*)(0x42CA0480UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT1         *((volatile unsigned int*)(0x42CA0484UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT2         *((volatile unsigned int*)(0x42CA0488UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT3         *((volatile unsigned int*)(0x42CA048CUL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT4         *((volatile unsigned int*)(0x42CA0490UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT5         *((volatile unsigned int*)(0x42CA0494UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT6         *((volatile unsigned int*)(0x42CA0498UL))
+#define bFM3_ETHERNET_MAC0_RIWTR_RIWT7         *((volatile unsigned int*)(0x42CA049CUL))
+#define bFM3_ETHERNET_MAC0_AHBSR_AHBS          *((volatile unsigned int*)(0x42CA0580UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42CA0900UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42CA0904UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42CA0908UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42CA090CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42CA0910UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42CA0914UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42CA0918UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42CA091CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42CA0920UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42CA0924UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42CA0928UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42CA092CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42CA0930UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42CA0934UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42CA0938UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42CA093CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42CA0940UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42CA0944UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42CA0948UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42CA094CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42CA0950UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42CA0954UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42CA0958UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42CA095CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42CA0960UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42CA0964UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42CA0968UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42CA096CUL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42CA0970UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42CA0974UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42CA0978UL))
+#define bFM3_ETHERNET_MAC0_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42CA097CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42CA0980UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42CA0984UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42CA0988UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42CA098CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42CA0990UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42CA0994UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42CA0998UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42CA099CUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42CA09A0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42CA09A4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42CA09A8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42CA09ACUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42CA09B0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42CA09B4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42CA09B8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42CA09BCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42CA09C0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42CA09C4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42CA09C8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42CA09CCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42CA09D0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42CA09D4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42CA09D8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42CA09DCUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42CA09E0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42CA09E4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42CA09E8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42CA09ECUL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42CA09F0UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42CA09F4UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42CA09F8UL))
+#define bFM3_ETHERNET_MAC0_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42CA09FCUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42CA0A00UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42CA0A04UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42CA0A08UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42CA0A0CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42CA0A10UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42CA0A14UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42CA0A18UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42CA0A1CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42CA0A20UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42CA0A24UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42CA0A28UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42CA0A2CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42CA0A30UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42CA0A34UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42CA0A38UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42CA0A3CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42CA0A40UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42CA0A44UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42CA0A48UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42CA0A4CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42CA0A50UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42CA0A54UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42CA0A58UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42CA0A5CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42CA0A60UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42CA0A64UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42CA0A68UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42CA0A6CUL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42CA0A70UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42CA0A74UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42CA0A78UL))
+#define bFM3_ETHERNET_MAC0_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42CA0A7CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42CA0A80UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42CA0A84UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42CA0A88UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42CA0A8CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42CA0A90UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42CA0A94UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42CA0A98UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42CA0A9CUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42CA0AA0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42CA0AA4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42CA0AA8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42CA0AACUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42CA0AB0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42CA0AB4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42CA0AB8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42CA0ABCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42CA0AC0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42CA0AC4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42CA0AC8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42CA0ACCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42CA0AD0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42CA0AD4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42CA0AD8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42CA0ADCUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42CA0AE0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42CA0AE4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42CA0AE8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42CA0AECUL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42CA0AF0UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42CA0AF4UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42CA0AF8UL))
+#define bFM3_ETHERNET_MAC0_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42CA0AFCUL))
+
+/* ETHERNET-MAC-CONTROL registers */
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_IFMODE  *((volatile unsigned int*)(0x42CC0000UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST0    *((volatile unsigned int*)(0x42CC0020UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_RST1    *((volatile unsigned int*)(0x42CC0024UL))
+#define bFM3_ETHERNET_CONTROL_ETH_MODE_PPSSEL  *((volatile unsigned int*)(0x42CC0070UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN0  *((volatile unsigned int*)(0x42CC0100UL))
+#define bFM3_ETHERNET_CONTROL_ETH_CLKG_MACEN1  *((volatile unsigned int*)(0x42CC0104UL))
+
+/* ETHERNET-MAC1 registers*/
+#define bFM3_ETHERNET_MAC1_MCR_RE              *((volatile unsigned int*)(0x42CE0008UL))
+#define bFM3_ETHERNET_MAC1_MCR_TE              *((volatile unsigned int*)(0x42CE000CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DC              *((volatile unsigned int*)(0x42CE0010UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL0             *((volatile unsigned int*)(0x42CE0014UL))
+#define bFM3_ETHERNET_MAC1_MCR_BL1             *((volatile unsigned int*)(0x42CE0018UL))
+#define bFM3_ETHERNET_MAC1_MCR_ACS             *((volatile unsigned int*)(0x42CE001CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LUD             *((volatile unsigned int*)(0x42CE0020UL))
+#define bFM3_ETHERNET_MAC1_MCR_DR              *((volatile unsigned int*)(0x42CE0024UL))
+#define bFM3_ETHERNET_MAC1_MCR_IPC             *((volatile unsigned int*)(0x42CE0028UL))
+#define bFM3_ETHERNET_MAC1_MCR_DM              *((volatile unsigned int*)(0x42CE002CUL))
+#define bFM3_ETHERNET_MAC1_MCR_LM              *((volatile unsigned int*)(0x42CE0030UL))
+#define bFM3_ETHERNET_MAC1_MCR_DO              *((volatile unsigned int*)(0x42CE0034UL))
+#define bFM3_ETHERNET_MAC1_MCR_FES             *((volatile unsigned int*)(0x42CE0038UL))
+#define bFM3_ETHERNET_MAC1_MCR_PS              *((volatile unsigned int*)(0x42CE003CUL))
+#define bFM3_ETHERNET_MAC1_MCR_DCRS            *((volatile unsigned int*)(0x42CE0040UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG0            *((volatile unsigned int*)(0x42CE0044UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG1            *((volatile unsigned int*)(0x42CE0048UL))
+#define bFM3_ETHERNET_MAC1_MCR_IFG2            *((volatile unsigned int*)(0x42CE004CUL))
+#define bFM3_ETHERNET_MAC1_MCR_JE              *((volatile unsigned int*)(0x42CE0050UL))
+#define bFM3_ETHERNET_MAC1_MCR_BE              *((volatile unsigned int*)(0x42CE0054UL))
+#define bFM3_ETHERNET_MAC1_MCR_JD              *((volatile unsigned int*)(0x42CE0058UL))
+#define bFM3_ETHERNET_MAC1_MCR_WD              *((volatile unsigned int*)(0x42CE005CUL))
+#define bFM3_ETHERNET_MAC1_MCR_TC              *((volatile unsigned int*)(0x42CE0060UL))
+#define bFM3_ETHERNET_MAC1_MCR_CST             *((volatile unsigned int*)(0x42CE0064UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PR             *((volatile unsigned int*)(0x42CE0080UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HUC            *((volatile unsigned int*)(0x42CE0084UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HMC            *((volatile unsigned int*)(0x42CE0088UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DAIF           *((volatile unsigned int*)(0x42CE008CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_PM             *((volatile unsigned int*)(0x42CE0090UL))
+#define bFM3_ETHERNET_MAC1_MFFR_DB             *((volatile unsigned int*)(0x42CE0094UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF0           *((volatile unsigned int*)(0x42CE0098UL))
+#define bFM3_ETHERNET_MAC1_MFFR_PCF1           *((volatile unsigned int*)(0x42CE009CUL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAIF           *((volatile unsigned int*)(0x42CE00A0UL))
+#define bFM3_ETHERNET_MAC1_MFFR_SAF            *((volatile unsigned int*)(0x42CE00A4UL))
+#define bFM3_ETHERNET_MAC1_MFFR_HPF            *((volatile unsigned int*)(0x42CE00A8UL))
+#define bFM3_ETHERNET_MAC1_MFFR_RA             *((volatile unsigned int*)(0x42CE00FCUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH0          *((volatile unsigned int*)(0x42CE0100UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH1          *((volatile unsigned int*)(0x42CE0104UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH2          *((volatile unsigned int*)(0x42CE0108UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH3          *((volatile unsigned int*)(0x42CE010CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH4          *((volatile unsigned int*)(0x42CE0110UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH5          *((volatile unsigned int*)(0x42CE0114UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH6          *((volatile unsigned int*)(0x42CE0118UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH7          *((volatile unsigned int*)(0x42CE011CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH8          *((volatile unsigned int*)(0x42CE0120UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH9          *((volatile unsigned int*)(0x42CE0124UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH10         *((volatile unsigned int*)(0x42CE0128UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH11         *((volatile unsigned int*)(0x42CE012CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH12         *((volatile unsigned int*)(0x42CE0130UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH13         *((volatile unsigned int*)(0x42CE0134UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH14         *((volatile unsigned int*)(0x42CE0138UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH15         *((volatile unsigned int*)(0x42CE013CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH16         *((volatile unsigned int*)(0x42CE0140UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH17         *((volatile unsigned int*)(0x42CE0144UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH18         *((volatile unsigned int*)(0x42CE0148UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH19         *((volatile unsigned int*)(0x42CE014CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH20         *((volatile unsigned int*)(0x42CE0150UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH21         *((volatile unsigned int*)(0x42CE0154UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH22         *((volatile unsigned int*)(0x42CE0158UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH23         *((volatile unsigned int*)(0x42CE015CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH24         *((volatile unsigned int*)(0x42CE0160UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH25         *((volatile unsigned int*)(0x42CE0164UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH26         *((volatile unsigned int*)(0x42CE0168UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH27         *((volatile unsigned int*)(0x42CE016CUL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH28         *((volatile unsigned int*)(0x42CE0170UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH29         *((volatile unsigned int*)(0x42CE0174UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH30         *((volatile unsigned int*)(0x42CE0178UL))
+#define bFM3_ETHERNET_MAC1_MHTRH_HTH31         *((volatile unsigned int*)(0x42CE017CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL0          *((volatile unsigned int*)(0x42CE0180UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL1          *((volatile unsigned int*)(0x42CE0184UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL2          *((volatile unsigned int*)(0x42CE0188UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL3          *((volatile unsigned int*)(0x42CE018CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL4          *((volatile unsigned int*)(0x42CE0190UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL5          *((volatile unsigned int*)(0x42CE0194UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL6          *((volatile unsigned int*)(0x42CE0198UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL7          *((volatile unsigned int*)(0x42CE019CUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL8          *((volatile unsigned int*)(0x42CE01A0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL9          *((volatile unsigned int*)(0x42CE01A4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL10         *((volatile unsigned int*)(0x42CE01A8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL11         *((volatile unsigned int*)(0x42CE01ACUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL12         *((volatile unsigned int*)(0x42CE01B0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL13         *((volatile unsigned int*)(0x42CE01B4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL14         *((volatile unsigned int*)(0x42CE01B8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL15         *((volatile unsigned int*)(0x42CE01BCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL16         *((volatile unsigned int*)(0x42CE01C0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL17         *((volatile unsigned int*)(0x42CE01C4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL18         *((volatile unsigned int*)(0x42CE01C8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL19         *((volatile unsigned int*)(0x42CE01CCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL20         *((volatile unsigned int*)(0x42CE01D0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL21         *((volatile unsigned int*)(0x42CE01D4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL22         *((volatile unsigned int*)(0x42CE01D8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL23         *((volatile unsigned int*)(0x42CE01DCUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL24         *((volatile unsigned int*)(0x42CE01E0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL25         *((volatile unsigned int*)(0x42CE01E4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL26         *((volatile unsigned int*)(0x42CE01E8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL27         *((volatile unsigned int*)(0x42CE01ECUL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL28         *((volatile unsigned int*)(0x42CE01F0UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL29         *((volatile unsigned int*)(0x42CE01F4UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL30         *((volatile unsigned int*)(0x42CE01F8UL))
+#define bFM3_ETHERNET_MAC1_MHTRL_HTL31         *((volatile unsigned int*)(0x42CE01FCUL))
+#define bFM3_ETHERNET_MAC1_GAR_GB              *((volatile unsigned int*)(0x42CE0200UL))
+#define bFM3_ETHERNET_MAC1_GAR_GW              *((volatile unsigned int*)(0x42CE0204UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR0             *((volatile unsigned int*)(0x42CE0208UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR1             *((volatile unsigned int*)(0x42CE020CUL))
+#define bFM3_ETHERNET_MAC1_GAR_CR2             *((volatile unsigned int*)(0x42CE0210UL))
+#define bFM3_ETHERNET_MAC1_GAR_CR3             *((volatile unsigned int*)(0x42CE0214UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR0             *((volatile unsigned int*)(0x42CE0218UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR1             *((volatile unsigned int*)(0x42CE021CUL))
+#define bFM3_ETHERNET_MAC1_GAR_GR2             *((volatile unsigned int*)(0x42CE0220UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR3             *((volatile unsigned int*)(0x42CE0224UL))
+#define bFM3_ETHERNET_MAC1_GAR_GR4             *((volatile unsigned int*)(0x42CE0228UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA0             *((volatile unsigned int*)(0x42CE022CUL))
+#define bFM3_ETHERNET_MAC1_GAR_PA1             *((volatile unsigned int*)(0x42CE0230UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA2             *((volatile unsigned int*)(0x42CE0234UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA3             *((volatile unsigned int*)(0x42CE0238UL))
+#define bFM3_ETHERNET_MAC1_GAR_PA4             *((volatile unsigned int*)(0x42CE023CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD0             *((volatile unsigned int*)(0x42CE0280UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD1             *((volatile unsigned int*)(0x42CE0284UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD2             *((volatile unsigned int*)(0x42CE0288UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD3             *((volatile unsigned int*)(0x42CE028CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD4             *((volatile unsigned int*)(0x42CE0290UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD5             *((volatile unsigned int*)(0x42CE0294UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD6             *((volatile unsigned int*)(0x42CE0298UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD7             *((volatile unsigned int*)(0x42CE029CUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD8             *((volatile unsigned int*)(0x42CE02A0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD9             *((volatile unsigned int*)(0x42CE02A4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD10            *((volatile unsigned int*)(0x42CE02A8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD11            *((volatile unsigned int*)(0x42CE02ACUL))
+#define bFM3_ETHERNET_MAC1_GDR_GD12            *((volatile unsigned int*)(0x42CE02B0UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD13            *((volatile unsigned int*)(0x42CE02B4UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD14            *((volatile unsigned int*)(0x42CE02B8UL))
+#define bFM3_ETHERNET_MAC1_GDR_GD15            *((volatile unsigned int*)(0x42CE02BCUL))
+#define bFM3_ETHERNET_MAC1_FCR_FCB_BPA         *((volatile unsigned int*)(0x42CE0300UL))
+#define bFM3_ETHERNET_MAC1_FCR_TFE             *((volatile unsigned int*)(0x42CE0304UL))
+#define bFM3_ETHERNET_MAC1_FCR_RFE             *((volatile unsigned int*)(0x42CE0308UL))
+#define bFM3_ETHERNET_MAC1_FCR_UP              *((volatile unsigned int*)(0x42CE030CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT0            *((volatile unsigned int*)(0x42CE0310UL))
+#define bFM3_ETHERNET_MAC1_FCR_PLT1            *((volatile unsigned int*)(0x42CE0314UL))
+#define bFM3_ETHERNET_MAC1_FCR_DZPQ            *((volatile unsigned int*)(0x42CE031CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT0             *((volatile unsigned int*)(0x42CE0340UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT1             *((volatile unsigned int*)(0x42CE0344UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT2             *((volatile unsigned int*)(0x42CE0348UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT3             *((volatile unsigned int*)(0x42CE034CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT4             *((volatile unsigned int*)(0x42CE0350UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT5             *((volatile unsigned int*)(0x42CE0354UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT6             *((volatile unsigned int*)(0x42CE0358UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT7             *((volatile unsigned int*)(0x42CE035CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT8             *((volatile unsigned int*)(0x42CE0360UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT9             *((volatile unsigned int*)(0x42CE0364UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT10            *((volatile unsigned int*)(0x42CE0368UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT11            *((volatile unsigned int*)(0x42CE036CUL))
+#define bFM3_ETHERNET_MAC1_FCR_PT12            *((volatile unsigned int*)(0x42CE0370UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT13            *((volatile unsigned int*)(0x42CE0374UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT14            *((volatile unsigned int*)(0x42CE0378UL))
+#define bFM3_ETHERNET_MAC1_FCR_PT15            *((volatile unsigned int*)(0x42CE037CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL0             *((volatile unsigned int*)(0x42CE0380UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL1             *((volatile unsigned int*)(0x42CE0384UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL2             *((volatile unsigned int*)(0x42CE0388UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL3             *((volatile unsigned int*)(0x42CE038CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL4             *((volatile unsigned int*)(0x42CE0390UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL5             *((volatile unsigned int*)(0x42CE0394UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL6             *((volatile unsigned int*)(0x42CE0398UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL7             *((volatile unsigned int*)(0x42CE039CUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL8             *((volatile unsigned int*)(0x42CE03A0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL9             *((volatile unsigned int*)(0x42CE03A4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL10            *((volatile unsigned int*)(0x42CE03A8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL11            *((volatile unsigned int*)(0x42CE03ACUL))
+#define bFM3_ETHERNET_MAC1_VTR_VL12            *((volatile unsigned int*)(0x42CE03B0UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL13            *((volatile unsigned int*)(0x42CE03B4UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL14            *((volatile unsigned int*)(0x42CE03B8UL))
+#define bFM3_ETHERNET_MAC1_VTR_VL15            *((volatile unsigned int*)(0x42CE03BCUL))
+#define bFM3_ETHERNET_MAC1_VTR_ETV             *((volatile unsigned int*)(0x42CE03C0UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR0        *((volatile unsigned int*)(0x42CE0500UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR1        *((volatile unsigned int*)(0x42CE0504UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR2        *((volatile unsigned int*)(0x42CE0508UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR3        *((volatile unsigned int*)(0x42CE050CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR4        *((volatile unsigned int*)(0x42CE0510UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR5        *((volatile unsigned int*)(0x42CE0514UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR6        *((volatile unsigned int*)(0x42CE0518UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR7        *((volatile unsigned int*)(0x42CE051CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR8        *((volatile unsigned int*)(0x42CE0520UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR9        *((volatile unsigned int*)(0x42CE0524UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR10       *((volatile unsigned int*)(0x42CE0528UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR11       *((volatile unsigned int*)(0x42CE052CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR12       *((volatile unsigned int*)(0x42CE0530UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR13       *((volatile unsigned int*)(0x42CE0534UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR14       *((volatile unsigned int*)(0x42CE0538UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR15       *((volatile unsigned int*)(0x42CE053CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR16       *((volatile unsigned int*)(0x42CE0540UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR17       *((volatile unsigned int*)(0x42CE0544UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR18       *((volatile unsigned int*)(0x42CE0548UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR19       *((volatile unsigned int*)(0x42CE054CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR20       *((volatile unsigned int*)(0x42CE0550UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR21       *((volatile unsigned int*)(0x42CE0554UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR22       *((volatile unsigned int*)(0x42CE0558UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR23       *((volatile unsigned int*)(0x42CE055CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR24       *((volatile unsigned int*)(0x42CE0560UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR25       *((volatile unsigned int*)(0x42CE0564UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR26       *((volatile unsigned int*)(0x42CE0568UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR27       *((volatile unsigned int*)(0x42CE056CUL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR28       *((volatile unsigned int*)(0x42CE0570UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR29       *((volatile unsigned int*)(0x42CE0574UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR30       *((volatile unsigned int*)(0x42CE0578UL))
+#define bFM3_ETHERNET_MAC1_RWFFR_RWFFR31       *((volatile unsigned int*)(0x42CE057CUL))
+#define bFM3_ETHERNET_MAC1_PMTR_PD             *((volatile unsigned int*)(0x42CE0580UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPE            *((volatile unsigned int*)(0x42CE0584UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WFE            *((volatile unsigned int*)(0x42CE0588UL))
+#define bFM3_ETHERNET_MAC1_PMTR_MPR            *((volatile unsigned int*)(0x42CE0594UL))
+#define bFM3_ETHERNET_MAC1_PMTR_WPR            *((volatile unsigned int*)(0x42CE0598UL))
+#define bFM3_ETHERNET_MAC1_PMTR_GU             *((volatile unsigned int*)(0x42CE05A4UL))
+#define bFM3_ETHERNET_MAC1_PMTR_RWFFRPR        *((volatile unsigned int*)(0x42CE05FCUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEN       *((volatile unsigned int*)(0x42CE0600UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIEX       *((volatile unsigned int*)(0x42CE0604UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEN       *((volatile unsigned int*)(0x42CE0608UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIEX       *((volatile unsigned int*)(0x42CE060CUL))
+#define bFM3_ETHERNET_MAC1_LPICSR_TLPIST       *((volatile unsigned int*)(0x42CE0620UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_RLPIST       *((volatile unsigned int*)(0x42CE0624UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPIEN        *((volatile unsigned int*)(0x42CE0640UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLS          *((volatile unsigned int*)(0x42CE0644UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_PLSEN        *((volatile unsigned int*)(0x42CE0648UL))
+#define bFM3_ETHERNET_MAC1_LPICSR_LPITXA       *((volatile unsigned int*)(0x42CE064CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT0         *((volatile unsigned int*)(0x42CE0680UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT1         *((volatile unsigned int*)(0x42CE0684UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT2         *((volatile unsigned int*)(0x42CE0688UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT3         *((volatile unsigned int*)(0x42CE068CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT4         *((volatile unsigned int*)(0x42CE0690UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT5         *((volatile unsigned int*)(0x42CE0694UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT6         *((volatile unsigned int*)(0x42CE0698UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT7         *((volatile unsigned int*)(0x42CE069CUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT8         *((volatile unsigned int*)(0x42CE06A0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT9         *((volatile unsigned int*)(0x42CE06A4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT10        *((volatile unsigned int*)(0x42CE06A8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT11        *((volatile unsigned int*)(0x42CE06ACUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT12        *((volatile unsigned int*)(0x42CE06B0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT13        *((volatile unsigned int*)(0x42CE06B4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT14        *((volatile unsigned int*)(0x42CE06B8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_TWT15        *((volatile unsigned int*)(0x42CE06BCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT0         *((volatile unsigned int*)(0x42CE06C0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT1         *((volatile unsigned int*)(0x42CE06C4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT2         *((volatile unsigned int*)(0x42CE06C8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT3         *((volatile unsigned int*)(0x42CE06CCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT4         *((volatile unsigned int*)(0x42CE06D0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT5         *((volatile unsigned int*)(0x42CE06D4UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT6         *((volatile unsigned int*)(0x42CE06D8UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT7         *((volatile unsigned int*)(0x42CE06DCUL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT8         *((volatile unsigned int*)(0x42CE06E0UL))
+#define bFM3_ETHERNET_MAC1_LPITCR_LIT9         *((volatile unsigned int*)(0x42CE06E4UL))
+#define bFM3_ETHERNET_MAC1_ISR_RGIS            *((volatile unsigned int*)(0x42CE0700UL))
+#define bFM3_ETHERNET_MAC1_ISR_PIS             *((volatile unsigned int*)(0x42CE070CUL))
+#define bFM3_ETHERNET_MAC1_ISR_MIS             *((volatile unsigned int*)(0x42CE0710UL))
+#define bFM3_ETHERNET_MAC1_ISR_RIS             *((volatile unsigned int*)(0x42CE0714UL))
+#define bFM3_ETHERNET_MAC1_ISR_TIS             *((volatile unsigned int*)(0x42CE0718UL))
+#define bFM3_ETHERNET_MAC1_ISR_COIS            *((volatile unsigned int*)(0x42CE071CUL))
+#define bFM3_ETHERNET_MAC1_ISR_TSIS            *((volatile unsigned int*)(0x42CE0724UL))
+#define bFM3_ETHERNET_MAC1_ISR_LPIIS           *((volatile unsigned int*)(0x42CE0728UL))
+#define bFM3_ETHERNET_MAC1_IMR_RGIM            *((volatile unsigned int*)(0x42CE0780UL))
+#define bFM3_ETHERNET_MAC1_IMR_PIM             *((volatile unsigned int*)(0x42CE078CUL))
+#define bFM3_ETHERNET_MAC1_IMR_TSIM            *((volatile unsigned int*)(0x42CE0794UL))
+#define bFM3_ETHERNET_MAC1_IMR_LPIIM           *((volatile unsigned int*)(0x42CE0798UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A32           *((volatile unsigned int*)(0x42CE0800UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A33           *((volatile unsigned int*)(0x42CE0804UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A34           *((volatile unsigned int*)(0x42CE0808UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A35           *((volatile unsigned int*)(0x42CE080CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A36           *((volatile unsigned int*)(0x42CE0810UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A37           *((volatile unsigned int*)(0x42CE0814UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A38           *((volatile unsigned int*)(0x42CE0818UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A39           *((volatile unsigned int*)(0x42CE081CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A40           *((volatile unsigned int*)(0x42CE0820UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A41           *((volatile unsigned int*)(0x42CE0824UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A42           *((volatile unsigned int*)(0x42CE0828UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A43           *((volatile unsigned int*)(0x42CE082CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A44           *((volatile unsigned int*)(0x42CE0830UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A45           *((volatile unsigned int*)(0x42CE0834UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A46           *((volatile unsigned int*)(0x42CE0838UL))
+#define bFM3_ETHERNET_MAC1_MAR0H_A47           *((volatile unsigned int*)(0x42CE083CUL))
+#define bFM3_ETHERNET_MAC1_MAR0H_MO            *((volatile unsigned int*)(0x42CE087CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A0            *((volatile unsigned int*)(0x42CE0880UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A1            *((volatile unsigned int*)(0x42CE0884UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A2            *((volatile unsigned int*)(0x42CE0888UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A3            *((volatile unsigned int*)(0x42CE088CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A4            *((volatile unsigned int*)(0x42CE0890UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A5            *((volatile unsigned int*)(0x42CE0894UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A6            *((volatile unsigned int*)(0x42CE0898UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A7            *((volatile unsigned int*)(0x42CE089CUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A8            *((volatile unsigned int*)(0x42CE08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A9            *((volatile unsigned int*)(0x42CE08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A10           *((volatile unsigned int*)(0x42CE08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A11           *((volatile unsigned int*)(0x42CE08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A12           *((volatile unsigned int*)(0x42CE08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A13           *((volatile unsigned int*)(0x42CE08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A14           *((volatile unsigned int*)(0x42CE08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A15           *((volatile unsigned int*)(0x42CE08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A16           *((volatile unsigned int*)(0x42CE08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A17           *((volatile unsigned int*)(0x42CE08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A18           *((volatile unsigned int*)(0x42CE08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A19           *((volatile unsigned int*)(0x42CE08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A20           *((volatile unsigned int*)(0x42CE08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A21           *((volatile unsigned int*)(0x42CE08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A22           *((volatile unsigned int*)(0x42CE08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A23           *((volatile unsigned int*)(0x42CE08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A24           *((volatile unsigned int*)(0x42CE08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A25           *((volatile unsigned int*)(0x42CE08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A26           *((volatile unsigned int*)(0x42CE08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A27           *((volatile unsigned int*)(0x42CE08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A28           *((volatile unsigned int*)(0x42CE08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A29           *((volatile unsigned int*)(0x42CE08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A30           *((volatile unsigned int*)(0x42CE08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR0L_A31           *((volatile unsigned int*)(0x42CE08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A32           *((volatile unsigned int*)(0x42CE0900UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A33           *((volatile unsigned int*)(0x42CE0904UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A34           *((volatile unsigned int*)(0x42CE0908UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A35           *((volatile unsigned int*)(0x42CE090CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A36           *((volatile unsigned int*)(0x42CE0910UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A37           *((volatile unsigned int*)(0x42CE0914UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A38           *((volatile unsigned int*)(0x42CE0918UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A39           *((volatile unsigned int*)(0x42CE091CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A40           *((volatile unsigned int*)(0x42CE0920UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A41           *((volatile unsigned int*)(0x42CE0924UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A42           *((volatile unsigned int*)(0x42CE0928UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A43           *((volatile unsigned int*)(0x42CE092CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A44           *((volatile unsigned int*)(0x42CE0930UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A45           *((volatile unsigned int*)(0x42CE0934UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A46           *((volatile unsigned int*)(0x42CE0938UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_A47           *((volatile unsigned int*)(0x42CE093CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC0          *((volatile unsigned int*)(0x42CE0960UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC1          *((volatile unsigned int*)(0x42CE0964UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC2          *((volatile unsigned int*)(0x42CE0968UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC3          *((volatile unsigned int*)(0x42CE096CUL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC4          *((volatile unsigned int*)(0x42CE0970UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_MBC5          *((volatile unsigned int*)(0x42CE0974UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_SA            *((volatile unsigned int*)(0x42CE0978UL))
+#define bFM3_ETHERNET_MAC1_MAR1H_AE            *((volatile unsigned int*)(0x42CE097CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A0            *((volatile unsigned int*)(0x42CE0980UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A1            *((volatile unsigned int*)(0x42CE0984UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A2            *((volatile unsigned int*)(0x42CE0988UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A3            *((volatile unsigned int*)(0x42CE098CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A4            *((volatile unsigned int*)(0x42CE0990UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A5            *((volatile unsigned int*)(0x42CE0994UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A6            *((volatile unsigned int*)(0x42CE0998UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A7            *((volatile unsigned int*)(0x42CE099CUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A8            *((volatile unsigned int*)(0x42CE09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A9            *((volatile unsigned int*)(0x42CE09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A10           *((volatile unsigned int*)(0x42CE09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A11           *((volatile unsigned int*)(0x42CE09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A12           *((volatile unsigned int*)(0x42CE09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A13           *((volatile unsigned int*)(0x42CE09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A14           *((volatile unsigned int*)(0x42CE09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A15           *((volatile unsigned int*)(0x42CE09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A16           *((volatile unsigned int*)(0x42CE09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A17           *((volatile unsigned int*)(0x42CE09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A18           *((volatile unsigned int*)(0x42CE09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A19           *((volatile unsigned int*)(0x42CE09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A20           *((volatile unsigned int*)(0x42CE09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A21           *((volatile unsigned int*)(0x42CE09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A22           *((volatile unsigned int*)(0x42CE09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A23           *((volatile unsigned int*)(0x42CE09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A24           *((volatile unsigned int*)(0x42CE09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A25           *((volatile unsigned int*)(0x42CE09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A26           *((volatile unsigned int*)(0x42CE09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A27           *((volatile unsigned int*)(0x42CE09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A28           *((volatile unsigned int*)(0x42CE09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A29           *((volatile unsigned int*)(0x42CE09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A30           *((volatile unsigned int*)(0x42CE09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR1L_A31           *((volatile unsigned int*)(0x42CE09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A32           *((volatile unsigned int*)(0x42CE0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A33           *((volatile unsigned int*)(0x42CE0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A34           *((volatile unsigned int*)(0x42CE0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A35           *((volatile unsigned int*)(0x42CE0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A36           *((volatile unsigned int*)(0x42CE0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A37           *((volatile unsigned int*)(0x42CE0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A38           *((volatile unsigned int*)(0x42CE0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A39           *((volatile unsigned int*)(0x42CE0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A40           *((volatile unsigned int*)(0x42CE0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A41           *((volatile unsigned int*)(0x42CE0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A42           *((volatile unsigned int*)(0x42CE0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A43           *((volatile unsigned int*)(0x42CE0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A44           *((volatile unsigned int*)(0x42CE0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A45           *((volatile unsigned int*)(0x42CE0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A46           *((volatile unsigned int*)(0x42CE0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_A47           *((volatile unsigned int*)(0x42CE0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC0          *((volatile unsigned int*)(0x42CE0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC1          *((volatile unsigned int*)(0x42CE0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC2          *((volatile unsigned int*)(0x42CE0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC3          *((volatile unsigned int*)(0x42CE0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC4          *((volatile unsigned int*)(0x42CE0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_MBC5          *((volatile unsigned int*)(0x42CE0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_SA            *((volatile unsigned int*)(0x42CE0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR2H_AE            *((volatile unsigned int*)(0x42CE0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A0            *((volatile unsigned int*)(0x42CE0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A1            *((volatile unsigned int*)(0x42CE0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A2            *((volatile unsigned int*)(0x42CE0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A3            *((volatile unsigned int*)(0x42CE0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A4            *((volatile unsigned int*)(0x42CE0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A5            *((volatile unsigned int*)(0x42CE0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A6            *((volatile unsigned int*)(0x42CE0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A7            *((volatile unsigned int*)(0x42CE0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A8            *((volatile unsigned int*)(0x42CE0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A9            *((volatile unsigned int*)(0x42CE0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A10           *((volatile unsigned int*)(0x42CE0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A11           *((volatile unsigned int*)(0x42CE0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A12           *((volatile unsigned int*)(0x42CE0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A13           *((volatile unsigned int*)(0x42CE0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A14           *((volatile unsigned int*)(0x42CE0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A15           *((volatile unsigned int*)(0x42CE0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A16           *((volatile unsigned int*)(0x42CE0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A17           *((volatile unsigned int*)(0x42CE0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A18           *((volatile unsigned int*)(0x42CE0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A19           *((volatile unsigned int*)(0x42CE0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A20           *((volatile unsigned int*)(0x42CE0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A21           *((volatile unsigned int*)(0x42CE0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A22           *((volatile unsigned int*)(0x42CE0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A23           *((volatile unsigned int*)(0x42CE0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A24           *((volatile unsigned int*)(0x42CE0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A25           *((volatile unsigned int*)(0x42CE0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A26           *((volatile unsigned int*)(0x42CE0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A27           *((volatile unsigned int*)(0x42CE0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A28           *((volatile unsigned int*)(0x42CE0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A29           *((volatile unsigned int*)(0x42CE0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A30           *((volatile unsigned int*)(0x42CE0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR2L_A31           *((volatile unsigned int*)(0x42CE0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A32           *((volatile unsigned int*)(0x42CE0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A33           *((volatile unsigned int*)(0x42CE0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A34           *((volatile unsigned int*)(0x42CE0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A35           *((volatile unsigned int*)(0x42CE0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A36           *((volatile unsigned int*)(0x42CE0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A37           *((volatile unsigned int*)(0x42CE0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A38           *((volatile unsigned int*)(0x42CE0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A39           *((volatile unsigned int*)(0x42CE0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A40           *((volatile unsigned int*)(0x42CE0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A41           *((volatile unsigned int*)(0x42CE0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A42           *((volatile unsigned int*)(0x42CE0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A43           *((volatile unsigned int*)(0x42CE0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A44           *((volatile unsigned int*)(0x42CE0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A45           *((volatile unsigned int*)(0x42CE0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A46           *((volatile unsigned int*)(0x42CE0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_A47           *((volatile unsigned int*)(0x42CE0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC0          *((volatile unsigned int*)(0x42CE0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC1          *((volatile unsigned int*)(0x42CE0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC2          *((volatile unsigned int*)(0x42CE0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC3          *((volatile unsigned int*)(0x42CE0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC4          *((volatile unsigned int*)(0x42CE0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_MBC5          *((volatile unsigned int*)(0x42CE0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_SA            *((volatile unsigned int*)(0x42CE0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR3H_AE            *((volatile unsigned int*)(0x42CE0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A0            *((volatile unsigned int*)(0x42CE0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A1            *((volatile unsigned int*)(0x42CE0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A2            *((volatile unsigned int*)(0x42CE0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A3            *((volatile unsigned int*)(0x42CE0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A4            *((volatile unsigned int*)(0x42CE0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A5            *((volatile unsigned int*)(0x42CE0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A6            *((volatile unsigned int*)(0x42CE0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A7            *((volatile unsigned int*)(0x42CE0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A8            *((volatile unsigned int*)(0x42CE0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A9            *((volatile unsigned int*)(0x42CE0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A10           *((volatile unsigned int*)(0x42CE0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A11           *((volatile unsigned int*)(0x42CE0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A12           *((volatile unsigned int*)(0x42CE0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A13           *((volatile unsigned int*)(0x42CE0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A14           *((volatile unsigned int*)(0x42CE0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A15           *((volatile unsigned int*)(0x42CE0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A16           *((volatile unsigned int*)(0x42CE0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A17           *((volatile unsigned int*)(0x42CE0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A18           *((volatile unsigned int*)(0x42CE0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A19           *((volatile unsigned int*)(0x42CE0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A20           *((volatile unsigned int*)(0x42CE0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A21           *((volatile unsigned int*)(0x42CE0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A22           *((volatile unsigned int*)(0x42CE0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A23           *((volatile unsigned int*)(0x42CE0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A24           *((volatile unsigned int*)(0x42CE0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A25           *((volatile unsigned int*)(0x42CE0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A26           *((volatile unsigned int*)(0x42CE0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A27           *((volatile unsigned int*)(0x42CE0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A28           *((volatile unsigned int*)(0x42CE0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A29           *((volatile unsigned int*)(0x42CE0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A30           *((volatile unsigned int*)(0x42CE0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR3L_A31           *((volatile unsigned int*)(0x42CE0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A32           *((volatile unsigned int*)(0x42CE0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A33           *((volatile unsigned int*)(0x42CE0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A34           *((volatile unsigned int*)(0x42CE0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A35           *((volatile unsigned int*)(0x42CE0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A36           *((volatile unsigned int*)(0x42CE0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A37           *((volatile unsigned int*)(0x42CE0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A38           *((volatile unsigned int*)(0x42CE0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A39           *((volatile unsigned int*)(0x42CE0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A40           *((volatile unsigned int*)(0x42CE0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A41           *((volatile unsigned int*)(0x42CE0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A42           *((volatile unsigned int*)(0x42CE0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A43           *((volatile unsigned int*)(0x42CE0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A44           *((volatile unsigned int*)(0x42CE0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A45           *((volatile unsigned int*)(0x42CE0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A46           *((volatile unsigned int*)(0x42CE0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_A47           *((volatile unsigned int*)(0x42CE0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC0          *((volatile unsigned int*)(0x42CE0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC1          *((volatile unsigned int*)(0x42CE0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC2          *((volatile unsigned int*)(0x42CE0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC3          *((volatile unsigned int*)(0x42CE0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC4          *((volatile unsigned int*)(0x42CE0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_MBC5          *((volatile unsigned int*)(0x42CE0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_SA            *((volatile unsigned int*)(0x42CE0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR4H_AE            *((volatile unsigned int*)(0x42CE0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A0            *((volatile unsigned int*)(0x42CE0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A1            *((volatile unsigned int*)(0x42CE0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A2            *((volatile unsigned int*)(0x42CE0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A3            *((volatile unsigned int*)(0x42CE0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A4            *((volatile unsigned int*)(0x42CE0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A5            *((volatile unsigned int*)(0x42CE0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A6            *((volatile unsigned int*)(0x42CE0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A7            *((volatile unsigned int*)(0x42CE0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A8            *((volatile unsigned int*)(0x42CE0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A9            *((volatile unsigned int*)(0x42CE0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A10           *((volatile unsigned int*)(0x42CE0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A11           *((volatile unsigned int*)(0x42CE0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A12           *((volatile unsigned int*)(0x42CE0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A13           *((volatile unsigned int*)(0x42CE0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A14           *((volatile unsigned int*)(0x42CE0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A15           *((volatile unsigned int*)(0x42CE0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A16           *((volatile unsigned int*)(0x42CE0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A17           *((volatile unsigned int*)(0x42CE0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A18           *((volatile unsigned int*)(0x42CE0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A19           *((volatile unsigned int*)(0x42CE0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A20           *((volatile unsigned int*)(0x42CE0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A21           *((volatile unsigned int*)(0x42CE0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A22           *((volatile unsigned int*)(0x42CE0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A23           *((volatile unsigned int*)(0x42CE0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A24           *((volatile unsigned int*)(0x42CE0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A25           *((volatile unsigned int*)(0x42CE0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A26           *((volatile unsigned int*)(0x42CE0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A27           *((volatile unsigned int*)(0x42CE0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A28           *((volatile unsigned int*)(0x42CE0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A29           *((volatile unsigned int*)(0x42CE0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A30           *((volatile unsigned int*)(0x42CE0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR4L_A31           *((volatile unsigned int*)(0x42CE0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A32           *((volatile unsigned int*)(0x42CE0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A33           *((volatile unsigned int*)(0x42CE0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A34           *((volatile unsigned int*)(0x42CE0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A35           *((volatile unsigned int*)(0x42CE0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A36           *((volatile unsigned int*)(0x42CE0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A37           *((volatile unsigned int*)(0x42CE0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A38           *((volatile unsigned int*)(0x42CE0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A39           *((volatile unsigned int*)(0x42CE0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A40           *((volatile unsigned int*)(0x42CE0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A41           *((volatile unsigned int*)(0x42CE0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A42           *((volatile unsigned int*)(0x42CE0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A43           *((volatile unsigned int*)(0x42CE0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A44           *((volatile unsigned int*)(0x42CE0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A45           *((volatile unsigned int*)(0x42CE0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A46           *((volatile unsigned int*)(0x42CE0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_A47           *((volatile unsigned int*)(0x42CE0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC0          *((volatile unsigned int*)(0x42CE0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC1          *((volatile unsigned int*)(0x42CE0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC2          *((volatile unsigned int*)(0x42CE0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC3          *((volatile unsigned int*)(0x42CE0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC4          *((volatile unsigned int*)(0x42CE0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_MBC5          *((volatile unsigned int*)(0x42CE0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_SA            *((volatile unsigned int*)(0x42CE0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR5H_AE            *((volatile unsigned int*)(0x42CE0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A0            *((volatile unsigned int*)(0x42CE0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A1            *((volatile unsigned int*)(0x42CE0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A2            *((volatile unsigned int*)(0x42CE0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A3            *((volatile unsigned int*)(0x42CE0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A4            *((volatile unsigned int*)(0x42CE0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A5            *((volatile unsigned int*)(0x42CE0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A6            *((volatile unsigned int*)(0x42CE0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A7            *((volatile unsigned int*)(0x42CE0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A8            *((volatile unsigned int*)(0x42CE0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A9            *((volatile unsigned int*)(0x42CE0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A10           *((volatile unsigned int*)(0x42CE0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A11           *((volatile unsigned int*)(0x42CE0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A12           *((volatile unsigned int*)(0x42CE0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A13           *((volatile unsigned int*)(0x42CE0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A14           *((volatile unsigned int*)(0x42CE0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A15           *((volatile unsigned int*)(0x42CE0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A16           *((volatile unsigned int*)(0x42CE0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A17           *((volatile unsigned int*)(0x42CE0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A18           *((volatile unsigned int*)(0x42CE0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A19           *((volatile unsigned int*)(0x42CE0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A20           *((volatile unsigned int*)(0x42CE0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A21           *((volatile unsigned int*)(0x42CE0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A22           *((volatile unsigned int*)(0x42CE0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A23           *((volatile unsigned int*)(0x42CE0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A24           *((volatile unsigned int*)(0x42CE0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A25           *((volatile unsigned int*)(0x42CE0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A26           *((volatile unsigned int*)(0x42CE0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A27           *((volatile unsigned int*)(0x42CE0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A28           *((volatile unsigned int*)(0x42CE0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A29           *((volatile unsigned int*)(0x42CE0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A30           *((volatile unsigned int*)(0x42CE0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR5L_A31           *((volatile unsigned int*)(0x42CE0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A32           *((volatile unsigned int*)(0x42CE0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A33           *((volatile unsigned int*)(0x42CE0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A34           *((volatile unsigned int*)(0x42CE0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A35           *((volatile unsigned int*)(0x42CE0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A36           *((volatile unsigned int*)(0x42CE0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A37           *((volatile unsigned int*)(0x42CE0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A38           *((volatile unsigned int*)(0x42CE0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A39           *((volatile unsigned int*)(0x42CE0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A40           *((volatile unsigned int*)(0x42CE0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A41           *((volatile unsigned int*)(0x42CE0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A42           *((volatile unsigned int*)(0x42CE0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A43           *((volatile unsigned int*)(0x42CE0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A44           *((volatile unsigned int*)(0x42CE0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A45           *((volatile unsigned int*)(0x42CE0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A46           *((volatile unsigned int*)(0x42CE0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_A47           *((volatile unsigned int*)(0x42CE0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC0          *((volatile unsigned int*)(0x42CE0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC1          *((volatile unsigned int*)(0x42CE0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC2          *((volatile unsigned int*)(0x42CE0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC3          *((volatile unsigned int*)(0x42CE0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC4          *((volatile unsigned int*)(0x42CE0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_MBC5          *((volatile unsigned int*)(0x42CE0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_SA            *((volatile unsigned int*)(0x42CE0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR6H_AE            *((volatile unsigned int*)(0x42CE0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A0            *((volatile unsigned int*)(0x42CE0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A1            *((volatile unsigned int*)(0x42CE0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A2            *((volatile unsigned int*)(0x42CE0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A3            *((volatile unsigned int*)(0x42CE0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A4            *((volatile unsigned int*)(0x42CE0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A5            *((volatile unsigned int*)(0x42CE0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A6            *((volatile unsigned int*)(0x42CE0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A7            *((volatile unsigned int*)(0x42CE0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A8            *((volatile unsigned int*)(0x42CE0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A9            *((volatile unsigned int*)(0x42CE0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A10           *((volatile unsigned int*)(0x42CE0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A11           *((volatile unsigned int*)(0x42CE0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A12           *((volatile unsigned int*)(0x42CE0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A13           *((volatile unsigned int*)(0x42CE0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A14           *((volatile unsigned int*)(0x42CE0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A15           *((volatile unsigned int*)(0x42CE0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A16           *((volatile unsigned int*)(0x42CE0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A17           *((volatile unsigned int*)(0x42CE0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A18           *((volatile unsigned int*)(0x42CE0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A19           *((volatile unsigned int*)(0x42CE0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A20           *((volatile unsigned int*)(0x42CE0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A21           *((volatile unsigned int*)(0x42CE0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A22           *((volatile unsigned int*)(0x42CE0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A23           *((volatile unsigned int*)(0x42CE0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A24           *((volatile unsigned int*)(0x42CE0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A25           *((volatile unsigned int*)(0x42CE0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A26           *((volatile unsigned int*)(0x42CE0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A27           *((volatile unsigned int*)(0x42CE0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A28           *((volatile unsigned int*)(0x42CE0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A29           *((volatile unsigned int*)(0x42CE0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A30           *((volatile unsigned int*)(0x42CE0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR6L_A31           *((volatile unsigned int*)(0x42CE0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A32           *((volatile unsigned int*)(0x42CE0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A33           *((volatile unsigned int*)(0x42CE0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A34           *((volatile unsigned int*)(0x42CE0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A35           *((volatile unsigned int*)(0x42CE0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A36           *((volatile unsigned int*)(0x42CE0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A37           *((volatile unsigned int*)(0x42CE0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A38           *((volatile unsigned int*)(0x42CE0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A39           *((volatile unsigned int*)(0x42CE0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A40           *((volatile unsigned int*)(0x42CE0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A41           *((volatile unsigned int*)(0x42CE0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A42           *((volatile unsigned int*)(0x42CE0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A43           *((volatile unsigned int*)(0x42CE0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A44           *((volatile unsigned int*)(0x42CE0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A45           *((volatile unsigned int*)(0x42CE0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A46           *((volatile unsigned int*)(0x42CE0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_A47           *((volatile unsigned int*)(0x42CE0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC0          *((volatile unsigned int*)(0x42CE0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC1          *((volatile unsigned int*)(0x42CE0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC2          *((volatile unsigned int*)(0x42CE0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC3          *((volatile unsigned int*)(0x42CE0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC4          *((volatile unsigned int*)(0x42CE0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_MBC5          *((volatile unsigned int*)(0x42CE0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_SA            *((volatile unsigned int*)(0x42CE0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR7H_AE            *((volatile unsigned int*)(0x42CE0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A0            *((volatile unsigned int*)(0x42CE0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A1            *((volatile unsigned int*)(0x42CE0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A2            *((volatile unsigned int*)(0x42CE0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A3            *((volatile unsigned int*)(0x42CE0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A4            *((volatile unsigned int*)(0x42CE0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A5            *((volatile unsigned int*)(0x42CE0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A6            *((volatile unsigned int*)(0x42CE0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A7            *((volatile unsigned int*)(0x42CE0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A8            *((volatile unsigned int*)(0x42CE0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A9            *((volatile unsigned int*)(0x42CE0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A10           *((volatile unsigned int*)(0x42CE0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A11           *((volatile unsigned int*)(0x42CE0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A12           *((volatile unsigned int*)(0x42CE0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A13           *((volatile unsigned int*)(0x42CE0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A14           *((volatile unsigned int*)(0x42CE0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A15           *((volatile unsigned int*)(0x42CE0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A16           *((volatile unsigned int*)(0x42CE0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A17           *((volatile unsigned int*)(0x42CE0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A18           *((volatile unsigned int*)(0x42CE0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A19           *((volatile unsigned int*)(0x42CE0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A20           *((volatile unsigned int*)(0x42CE0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A21           *((volatile unsigned int*)(0x42CE0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A22           *((volatile unsigned int*)(0x42CE0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A23           *((volatile unsigned int*)(0x42CE0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A24           *((volatile unsigned int*)(0x42CE0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A25           *((volatile unsigned int*)(0x42CE0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A26           *((volatile unsigned int*)(0x42CE0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A27           *((volatile unsigned int*)(0x42CE0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A28           *((volatile unsigned int*)(0x42CE0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A29           *((volatile unsigned int*)(0x42CE0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A30           *((volatile unsigned int*)(0x42CE0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR7L_A31           *((volatile unsigned int*)(0x42CE0FFCUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A32           *((volatile unsigned int*)(0x42CE1000UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A33           *((volatile unsigned int*)(0x42CE1004UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A34           *((volatile unsigned int*)(0x42CE1008UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A35           *((volatile unsigned int*)(0x42CE100CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A36           *((volatile unsigned int*)(0x42CE1010UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A37           *((volatile unsigned int*)(0x42CE1014UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A38           *((volatile unsigned int*)(0x42CE1018UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A39           *((volatile unsigned int*)(0x42CE101CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A40           *((volatile unsigned int*)(0x42CE1020UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A41           *((volatile unsigned int*)(0x42CE1024UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A42           *((volatile unsigned int*)(0x42CE1028UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A43           *((volatile unsigned int*)(0x42CE102CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A44           *((volatile unsigned int*)(0x42CE1030UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A45           *((volatile unsigned int*)(0x42CE1034UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A46           *((volatile unsigned int*)(0x42CE1038UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_A47           *((volatile unsigned int*)(0x42CE103CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC0          *((volatile unsigned int*)(0x42CE1060UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC1          *((volatile unsigned int*)(0x42CE1064UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC2          *((volatile unsigned int*)(0x42CE1068UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC3          *((volatile unsigned int*)(0x42CE106CUL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC4          *((volatile unsigned int*)(0x42CE1070UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_MBC5          *((volatile unsigned int*)(0x42CE1074UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_SA            *((volatile unsigned int*)(0x42CE1078UL))
+#define bFM3_ETHERNET_MAC1_MAR8H_AE            *((volatile unsigned int*)(0x42CE107CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A0            *((volatile unsigned int*)(0x42CE1080UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A1            *((volatile unsigned int*)(0x42CE1084UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A2            *((volatile unsigned int*)(0x42CE1088UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A3            *((volatile unsigned int*)(0x42CE108CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A4            *((volatile unsigned int*)(0x42CE1090UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A5            *((volatile unsigned int*)(0x42CE1094UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A6            *((volatile unsigned int*)(0x42CE1098UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A7            *((volatile unsigned int*)(0x42CE109CUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A8            *((volatile unsigned int*)(0x42CE10A0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A9            *((volatile unsigned int*)(0x42CE10A4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A10           *((volatile unsigned int*)(0x42CE10A8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A11           *((volatile unsigned int*)(0x42CE10ACUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A12           *((volatile unsigned int*)(0x42CE10B0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A13           *((volatile unsigned int*)(0x42CE10B4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A14           *((volatile unsigned int*)(0x42CE10B8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A15           *((volatile unsigned int*)(0x42CE10BCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A16           *((volatile unsigned int*)(0x42CE10C0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A17           *((volatile unsigned int*)(0x42CE10C4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A18           *((volatile unsigned int*)(0x42CE10C8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A19           *((volatile unsigned int*)(0x42CE10CCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A20           *((volatile unsigned int*)(0x42CE10D0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A21           *((volatile unsigned int*)(0x42CE10D4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A22           *((volatile unsigned int*)(0x42CE10D8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A23           *((volatile unsigned int*)(0x42CE10DCUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A24           *((volatile unsigned int*)(0x42CE10E0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A25           *((volatile unsigned int*)(0x42CE10E4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A26           *((volatile unsigned int*)(0x42CE10E8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A27           *((volatile unsigned int*)(0x42CE10ECUL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A28           *((volatile unsigned int*)(0x42CE10F0UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A29           *((volatile unsigned int*)(0x42CE10F4UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A30           *((volatile unsigned int*)(0x42CE10F8UL))
+#define bFM3_ETHERNET_MAC1_MAR8L_A31           *((volatile unsigned int*)(0x42CE10FCUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A32           *((volatile unsigned int*)(0x42CE1100UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A33           *((volatile unsigned int*)(0x42CE1104UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A34           *((volatile unsigned int*)(0x42CE1108UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A35           *((volatile unsigned int*)(0x42CE110CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A36           *((volatile unsigned int*)(0x42CE1110UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A37           *((volatile unsigned int*)(0x42CE1114UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A38           *((volatile unsigned int*)(0x42CE1118UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A39           *((volatile unsigned int*)(0x42CE111CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A40           *((volatile unsigned int*)(0x42CE1120UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A41           *((volatile unsigned int*)(0x42CE1124UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A42           *((volatile unsigned int*)(0x42CE1128UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A43           *((volatile unsigned int*)(0x42CE112CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A44           *((volatile unsigned int*)(0x42CE1130UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A45           *((volatile unsigned int*)(0x42CE1134UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A46           *((volatile unsigned int*)(0x42CE1138UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_A47           *((volatile unsigned int*)(0x42CE113CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC0          *((volatile unsigned int*)(0x42CE1160UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC1          *((volatile unsigned int*)(0x42CE1164UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC2          *((volatile unsigned int*)(0x42CE1168UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC3          *((volatile unsigned int*)(0x42CE116CUL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC4          *((volatile unsigned int*)(0x42CE1170UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_MBC5          *((volatile unsigned int*)(0x42CE1174UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_SA            *((volatile unsigned int*)(0x42CE1178UL))
+#define bFM3_ETHERNET_MAC1_MAR9H_AE            *((volatile unsigned int*)(0x42CE117CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A0            *((volatile unsigned int*)(0x42CE1180UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A1            *((volatile unsigned int*)(0x42CE1184UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A2            *((volatile unsigned int*)(0x42CE1188UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A3            *((volatile unsigned int*)(0x42CE118CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A4            *((volatile unsigned int*)(0x42CE1190UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A5            *((volatile unsigned int*)(0x42CE1194UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A6            *((volatile unsigned int*)(0x42CE1198UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A7            *((volatile unsigned int*)(0x42CE119CUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A8            *((volatile unsigned int*)(0x42CE11A0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A9            *((volatile unsigned int*)(0x42CE11A4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A10           *((volatile unsigned int*)(0x42CE11A8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A11           *((volatile unsigned int*)(0x42CE11ACUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A12           *((volatile unsigned int*)(0x42CE11B0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A13           *((volatile unsigned int*)(0x42CE11B4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A14           *((volatile unsigned int*)(0x42CE11B8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A15           *((volatile unsigned int*)(0x42CE11BCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A16           *((volatile unsigned int*)(0x42CE11C0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A17           *((volatile unsigned int*)(0x42CE11C4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A18           *((volatile unsigned int*)(0x42CE11C8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A19           *((volatile unsigned int*)(0x42CE11CCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A20           *((volatile unsigned int*)(0x42CE11D0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A21           *((volatile unsigned int*)(0x42CE11D4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A22           *((volatile unsigned int*)(0x42CE11D8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A23           *((volatile unsigned int*)(0x42CE11DCUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A24           *((volatile unsigned int*)(0x42CE11E0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A25           *((volatile unsigned int*)(0x42CE11E4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A26           *((volatile unsigned int*)(0x42CE11E8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A27           *((volatile unsigned int*)(0x42CE11ECUL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A28           *((volatile unsigned int*)(0x42CE11F0UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A29           *((volatile unsigned int*)(0x42CE11F4UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A30           *((volatile unsigned int*)(0x42CE11F8UL))
+#define bFM3_ETHERNET_MAC1_MAR9L_A31           *((volatile unsigned int*)(0x42CE11FCUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A32          *((volatile unsigned int*)(0x42CE1200UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A33          *((volatile unsigned int*)(0x42CE1204UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A34          *((volatile unsigned int*)(0x42CE1208UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A35          *((volatile unsigned int*)(0x42CE120CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A36          *((volatile unsigned int*)(0x42CE1210UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A37          *((volatile unsigned int*)(0x42CE1214UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A38          *((volatile unsigned int*)(0x42CE1218UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A39          *((volatile unsigned int*)(0x42CE121CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A40          *((volatile unsigned int*)(0x42CE1220UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A41          *((volatile unsigned int*)(0x42CE1224UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A42          *((volatile unsigned int*)(0x42CE1228UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A43          *((volatile unsigned int*)(0x42CE122CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A44          *((volatile unsigned int*)(0x42CE1230UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A45          *((volatile unsigned int*)(0x42CE1234UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A46          *((volatile unsigned int*)(0x42CE1238UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_A47          *((volatile unsigned int*)(0x42CE123CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC0         *((volatile unsigned int*)(0x42CE1260UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC1         *((volatile unsigned int*)(0x42CE1264UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC2         *((volatile unsigned int*)(0x42CE1268UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC3         *((volatile unsigned int*)(0x42CE126CUL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC4         *((volatile unsigned int*)(0x42CE1270UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_MBC5         *((volatile unsigned int*)(0x42CE1274UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_SA           *((volatile unsigned int*)(0x42CE1278UL))
+#define bFM3_ETHERNET_MAC1_MAR10H_AE           *((volatile unsigned int*)(0x42CE127CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A0           *((volatile unsigned int*)(0x42CE1280UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A1           *((volatile unsigned int*)(0x42CE1284UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A2           *((volatile unsigned int*)(0x42CE1288UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A3           *((volatile unsigned int*)(0x42CE128CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A4           *((volatile unsigned int*)(0x42CE1290UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A5           *((volatile unsigned int*)(0x42CE1294UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A6           *((volatile unsigned int*)(0x42CE1298UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A7           *((volatile unsigned int*)(0x42CE129CUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A8           *((volatile unsigned int*)(0x42CE12A0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A9           *((volatile unsigned int*)(0x42CE12A4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A10          *((volatile unsigned int*)(0x42CE12A8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A11          *((volatile unsigned int*)(0x42CE12ACUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A12          *((volatile unsigned int*)(0x42CE12B0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A13          *((volatile unsigned int*)(0x42CE12B4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A14          *((volatile unsigned int*)(0x42CE12B8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A15          *((volatile unsigned int*)(0x42CE12BCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A16          *((volatile unsigned int*)(0x42CE12C0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A17          *((volatile unsigned int*)(0x42CE12C4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A18          *((volatile unsigned int*)(0x42CE12C8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A19          *((volatile unsigned int*)(0x42CE12CCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A20          *((volatile unsigned int*)(0x42CE12D0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A21          *((volatile unsigned int*)(0x42CE12D4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A22          *((volatile unsigned int*)(0x42CE12D8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A23          *((volatile unsigned int*)(0x42CE12DCUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A24          *((volatile unsigned int*)(0x42CE12E0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A25          *((volatile unsigned int*)(0x42CE12E4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A26          *((volatile unsigned int*)(0x42CE12E8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A27          *((volatile unsigned int*)(0x42CE12ECUL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A28          *((volatile unsigned int*)(0x42CE12F0UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A29          *((volatile unsigned int*)(0x42CE12F4UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A30          *((volatile unsigned int*)(0x42CE12F8UL))
+#define bFM3_ETHERNET_MAC1_MAR10L_A31          *((volatile unsigned int*)(0x42CE12FCUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A32          *((volatile unsigned int*)(0x42CE1300UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A33          *((volatile unsigned int*)(0x42CE1304UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A34          *((volatile unsigned int*)(0x42CE1308UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A35          *((volatile unsigned int*)(0x42CE130CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A36          *((volatile unsigned int*)(0x42CE1310UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A37          *((volatile unsigned int*)(0x42CE1314UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A38          *((volatile unsigned int*)(0x42CE1318UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A39          *((volatile unsigned int*)(0x42CE131CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A40          *((volatile unsigned int*)(0x42CE1320UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A41          *((volatile unsigned int*)(0x42CE1324UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A42          *((volatile unsigned int*)(0x42CE1328UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A43          *((volatile unsigned int*)(0x42CE132CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A44          *((volatile unsigned int*)(0x42CE1330UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A45          *((volatile unsigned int*)(0x42CE1334UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A46          *((volatile unsigned int*)(0x42CE1338UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_A47          *((volatile unsigned int*)(0x42CE133CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC0         *((volatile unsigned int*)(0x42CE1360UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC1         *((volatile unsigned int*)(0x42CE1364UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC2         *((volatile unsigned int*)(0x42CE1368UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC3         *((volatile unsigned int*)(0x42CE136CUL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC4         *((volatile unsigned int*)(0x42CE1370UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_MBC5         *((volatile unsigned int*)(0x42CE1374UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_SA           *((volatile unsigned int*)(0x42CE1378UL))
+#define bFM3_ETHERNET_MAC1_MAR11H_AE           *((volatile unsigned int*)(0x42CE137CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A0           *((volatile unsigned int*)(0x42CE1380UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A1           *((volatile unsigned int*)(0x42CE1384UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A2           *((volatile unsigned int*)(0x42CE1388UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A3           *((volatile unsigned int*)(0x42CE138CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A4           *((volatile unsigned int*)(0x42CE1390UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A5           *((volatile unsigned int*)(0x42CE1394UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A6           *((volatile unsigned int*)(0x42CE1398UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A7           *((volatile unsigned int*)(0x42CE139CUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A8           *((volatile unsigned int*)(0x42CE13A0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A9           *((volatile unsigned int*)(0x42CE13A4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A10          *((volatile unsigned int*)(0x42CE13A8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A11          *((volatile unsigned int*)(0x42CE13ACUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A12          *((volatile unsigned int*)(0x42CE13B0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A13          *((volatile unsigned int*)(0x42CE13B4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A14          *((volatile unsigned int*)(0x42CE13B8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A15          *((volatile unsigned int*)(0x42CE13BCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A16          *((volatile unsigned int*)(0x42CE13C0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A17          *((volatile unsigned int*)(0x42CE13C4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A18          *((volatile unsigned int*)(0x42CE13C8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A19          *((volatile unsigned int*)(0x42CE13CCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A20          *((volatile unsigned int*)(0x42CE13D0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A21          *((volatile unsigned int*)(0x42CE13D4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A22          *((volatile unsigned int*)(0x42CE13D8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A23          *((volatile unsigned int*)(0x42CE13DCUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A24          *((volatile unsigned int*)(0x42CE13E0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A25          *((volatile unsigned int*)(0x42CE13E4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A26          *((volatile unsigned int*)(0x42CE13E8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A27          *((volatile unsigned int*)(0x42CE13ECUL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A28          *((volatile unsigned int*)(0x42CE13F0UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A29          *((volatile unsigned int*)(0x42CE13F4UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A30          *((volatile unsigned int*)(0x42CE13F8UL))
+#define bFM3_ETHERNET_MAC1_MAR11L_A31          *((volatile unsigned int*)(0x42CE13FCUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A32          *((volatile unsigned int*)(0x42CE1400UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A33          *((volatile unsigned int*)(0x42CE1404UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A34          *((volatile unsigned int*)(0x42CE1408UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A35          *((volatile unsigned int*)(0x42CE140CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A36          *((volatile unsigned int*)(0x42CE1410UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A37          *((volatile unsigned int*)(0x42CE1414UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A38          *((volatile unsigned int*)(0x42CE1418UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A39          *((volatile unsigned int*)(0x42CE141CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A40          *((volatile unsigned int*)(0x42CE1420UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A41          *((volatile unsigned int*)(0x42CE1424UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A42          *((volatile unsigned int*)(0x42CE1428UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A43          *((volatile unsigned int*)(0x42CE142CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A44          *((volatile unsigned int*)(0x42CE1430UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A45          *((volatile unsigned int*)(0x42CE1434UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A46          *((volatile unsigned int*)(0x42CE1438UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_A47          *((volatile unsigned int*)(0x42CE143CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC0         *((volatile unsigned int*)(0x42CE1460UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC1         *((volatile unsigned int*)(0x42CE1464UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC2         *((volatile unsigned int*)(0x42CE1468UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC3         *((volatile unsigned int*)(0x42CE146CUL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC4         *((volatile unsigned int*)(0x42CE1470UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_MBC5         *((volatile unsigned int*)(0x42CE1474UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_SA           *((volatile unsigned int*)(0x42CE1478UL))
+#define bFM3_ETHERNET_MAC1_MAR12H_AE           *((volatile unsigned int*)(0x42CE147CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A0           *((volatile unsigned int*)(0x42CE1480UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A1           *((volatile unsigned int*)(0x42CE1484UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A2           *((volatile unsigned int*)(0x42CE1488UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A3           *((volatile unsigned int*)(0x42CE148CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A4           *((volatile unsigned int*)(0x42CE1490UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A5           *((volatile unsigned int*)(0x42CE1494UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A6           *((volatile unsigned int*)(0x42CE1498UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A7           *((volatile unsigned int*)(0x42CE149CUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A8           *((volatile unsigned int*)(0x42CE14A0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A9           *((volatile unsigned int*)(0x42CE14A4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A10          *((volatile unsigned int*)(0x42CE14A8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A11          *((volatile unsigned int*)(0x42CE14ACUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A12          *((volatile unsigned int*)(0x42CE14B0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A13          *((volatile unsigned int*)(0x42CE14B4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A14          *((volatile unsigned int*)(0x42CE14B8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A15          *((volatile unsigned int*)(0x42CE14BCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A16          *((volatile unsigned int*)(0x42CE14C0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A17          *((volatile unsigned int*)(0x42CE14C4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A18          *((volatile unsigned int*)(0x42CE14C8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A19          *((volatile unsigned int*)(0x42CE14CCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A20          *((volatile unsigned int*)(0x42CE14D0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A21          *((volatile unsigned int*)(0x42CE14D4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A22          *((volatile unsigned int*)(0x42CE14D8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A23          *((volatile unsigned int*)(0x42CE14DCUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A24          *((volatile unsigned int*)(0x42CE14E0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A25          *((volatile unsigned int*)(0x42CE14E4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A26          *((volatile unsigned int*)(0x42CE14E8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A27          *((volatile unsigned int*)(0x42CE14ECUL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A28          *((volatile unsigned int*)(0x42CE14F0UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A29          *((volatile unsigned int*)(0x42CE14F4UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A30          *((volatile unsigned int*)(0x42CE14F8UL))
+#define bFM3_ETHERNET_MAC1_MAR12L_A31          *((volatile unsigned int*)(0x42CE14FCUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A32          *((volatile unsigned int*)(0x42CE1500UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A33          *((volatile unsigned int*)(0x42CE1504UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A34          *((volatile unsigned int*)(0x42CE1508UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A35          *((volatile unsigned int*)(0x42CE150CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A36          *((volatile unsigned int*)(0x42CE1510UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A37          *((volatile unsigned int*)(0x42CE1514UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A38          *((volatile unsigned int*)(0x42CE1518UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A39          *((volatile unsigned int*)(0x42CE151CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A40          *((volatile unsigned int*)(0x42CE1520UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A41          *((volatile unsigned int*)(0x42CE1524UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A42          *((volatile unsigned int*)(0x42CE1528UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A43          *((volatile unsigned int*)(0x42CE152CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A44          *((volatile unsigned int*)(0x42CE1530UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A45          *((volatile unsigned int*)(0x42CE1534UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A46          *((volatile unsigned int*)(0x42CE1538UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_A47          *((volatile unsigned int*)(0x42CE153CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC0         *((volatile unsigned int*)(0x42CE1560UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC1         *((volatile unsigned int*)(0x42CE1564UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC2         *((volatile unsigned int*)(0x42CE1568UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC3         *((volatile unsigned int*)(0x42CE156CUL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC4         *((volatile unsigned int*)(0x42CE1570UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_MBC5         *((volatile unsigned int*)(0x42CE1574UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_SA           *((volatile unsigned int*)(0x42CE1578UL))
+#define bFM3_ETHERNET_MAC1_MAR13H_AE           *((volatile unsigned int*)(0x42CE157CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A0           *((volatile unsigned int*)(0x42CE1580UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A1           *((volatile unsigned int*)(0x42CE1584UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A2           *((volatile unsigned int*)(0x42CE1588UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A3           *((volatile unsigned int*)(0x42CE158CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A4           *((volatile unsigned int*)(0x42CE1590UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A5           *((volatile unsigned int*)(0x42CE1594UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A6           *((volatile unsigned int*)(0x42CE1598UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A7           *((volatile unsigned int*)(0x42CE159CUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A8           *((volatile unsigned int*)(0x42CE15A0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A9           *((volatile unsigned int*)(0x42CE15A4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A10          *((volatile unsigned int*)(0x42CE15A8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A11          *((volatile unsigned int*)(0x42CE15ACUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A12          *((volatile unsigned int*)(0x42CE15B0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A13          *((volatile unsigned int*)(0x42CE15B4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A14          *((volatile unsigned int*)(0x42CE15B8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A15          *((volatile unsigned int*)(0x42CE15BCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A16          *((volatile unsigned int*)(0x42CE15C0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A17          *((volatile unsigned int*)(0x42CE15C4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A18          *((volatile unsigned int*)(0x42CE15C8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A19          *((volatile unsigned int*)(0x42CE15CCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A20          *((volatile unsigned int*)(0x42CE15D0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A21          *((volatile unsigned int*)(0x42CE15D4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A22          *((volatile unsigned int*)(0x42CE15D8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A23          *((volatile unsigned int*)(0x42CE15DCUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A24          *((volatile unsigned int*)(0x42CE15E0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A25          *((volatile unsigned int*)(0x42CE15E4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A26          *((volatile unsigned int*)(0x42CE15E8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A27          *((volatile unsigned int*)(0x42CE15ECUL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A28          *((volatile unsigned int*)(0x42CE15F0UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A29          *((volatile unsigned int*)(0x42CE15F4UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A30          *((volatile unsigned int*)(0x42CE15F8UL))
+#define bFM3_ETHERNET_MAC1_MAR13L_A31          *((volatile unsigned int*)(0x42CE15FCUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A32          *((volatile unsigned int*)(0x42CE1600UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A33          *((volatile unsigned int*)(0x42CE1604UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A34          *((volatile unsigned int*)(0x42CE1608UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A35          *((volatile unsigned int*)(0x42CE160CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A36          *((volatile unsigned int*)(0x42CE1610UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A37          *((volatile unsigned int*)(0x42CE1614UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A38          *((volatile unsigned int*)(0x42CE1618UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A39          *((volatile unsigned int*)(0x42CE161CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A40          *((volatile unsigned int*)(0x42CE1620UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A41          *((volatile unsigned int*)(0x42CE1624UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A42          *((volatile unsigned int*)(0x42CE1628UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A43          *((volatile unsigned int*)(0x42CE162CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A44          *((volatile unsigned int*)(0x42CE1630UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A45          *((volatile unsigned int*)(0x42CE1634UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A46          *((volatile unsigned int*)(0x42CE1638UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_A47          *((volatile unsigned int*)(0x42CE163CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC0         *((volatile unsigned int*)(0x42CE1660UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC1         *((volatile unsigned int*)(0x42CE1664UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC2         *((volatile unsigned int*)(0x42CE1668UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC3         *((volatile unsigned int*)(0x42CE166CUL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC4         *((volatile unsigned int*)(0x42CE1670UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_MBC5         *((volatile unsigned int*)(0x42CE1674UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_SA           *((volatile unsigned int*)(0x42CE1678UL))
+#define bFM3_ETHERNET_MAC1_MAR14H_AE           *((volatile unsigned int*)(0x42CE167CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A0           *((volatile unsigned int*)(0x42CE1680UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A1           *((volatile unsigned int*)(0x42CE1684UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A2           *((volatile unsigned int*)(0x42CE1688UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A3           *((volatile unsigned int*)(0x42CE168CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A4           *((volatile unsigned int*)(0x42CE1690UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A5           *((volatile unsigned int*)(0x42CE1694UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A6           *((volatile unsigned int*)(0x42CE1698UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A7           *((volatile unsigned int*)(0x42CE169CUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A8           *((volatile unsigned int*)(0x42CE16A0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A9           *((volatile unsigned int*)(0x42CE16A4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A10          *((volatile unsigned int*)(0x42CE16A8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A11          *((volatile unsigned int*)(0x42CE16ACUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A12          *((volatile unsigned int*)(0x42CE16B0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A13          *((volatile unsigned int*)(0x42CE16B4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A14          *((volatile unsigned int*)(0x42CE16B8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A15          *((volatile unsigned int*)(0x42CE16BCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A16          *((volatile unsigned int*)(0x42CE16C0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A17          *((volatile unsigned int*)(0x42CE16C4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A18          *((volatile unsigned int*)(0x42CE16C8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A19          *((volatile unsigned int*)(0x42CE16CCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A20          *((volatile unsigned int*)(0x42CE16D0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A21          *((volatile unsigned int*)(0x42CE16D4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A22          *((volatile unsigned int*)(0x42CE16D8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A23          *((volatile unsigned int*)(0x42CE16DCUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A24          *((volatile unsigned int*)(0x42CE16E0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A25          *((volatile unsigned int*)(0x42CE16E4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A26          *((volatile unsigned int*)(0x42CE16E8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A27          *((volatile unsigned int*)(0x42CE16ECUL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A28          *((volatile unsigned int*)(0x42CE16F0UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A29          *((volatile unsigned int*)(0x42CE16F4UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A30          *((volatile unsigned int*)(0x42CE16F8UL))
+#define bFM3_ETHERNET_MAC1_MAR14L_A31          *((volatile unsigned int*)(0x42CE16FCUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A32          *((volatile unsigned int*)(0x42CE1700UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A33          *((volatile unsigned int*)(0x42CE1704UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A34          *((volatile unsigned int*)(0x42CE1708UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A35          *((volatile unsigned int*)(0x42CE170CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A36          *((volatile unsigned int*)(0x42CE1710UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A37          *((volatile unsigned int*)(0x42CE1714UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A38          *((volatile unsigned int*)(0x42CE1718UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A39          *((volatile unsigned int*)(0x42CE171CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A40          *((volatile unsigned int*)(0x42CE1720UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A41          *((volatile unsigned int*)(0x42CE1724UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A42          *((volatile unsigned int*)(0x42CE1728UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A43          *((volatile unsigned int*)(0x42CE172CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A44          *((volatile unsigned int*)(0x42CE1730UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A45          *((volatile unsigned int*)(0x42CE1734UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A46          *((volatile unsigned int*)(0x42CE1738UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_A47          *((volatile unsigned int*)(0x42CE173CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC0         *((volatile unsigned int*)(0x42CE1760UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC1         *((volatile unsigned int*)(0x42CE1764UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC2         *((volatile unsigned int*)(0x42CE1768UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC3         *((volatile unsigned int*)(0x42CE176CUL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC4         *((volatile unsigned int*)(0x42CE1770UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_MBC5         *((volatile unsigned int*)(0x42CE1774UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_SA           *((volatile unsigned int*)(0x42CE1778UL))
+#define bFM3_ETHERNET_MAC1_MAR15H_AE           *((volatile unsigned int*)(0x42CE177CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A0           *((volatile unsigned int*)(0x42CE1780UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A1           *((volatile unsigned int*)(0x42CE1784UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A2           *((volatile unsigned int*)(0x42CE1788UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A3           *((volatile unsigned int*)(0x42CE178CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A4           *((volatile unsigned int*)(0x42CE1790UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A5           *((volatile unsigned int*)(0x42CE1794UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A6           *((volatile unsigned int*)(0x42CE1798UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A7           *((volatile unsigned int*)(0x42CE179CUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A8           *((volatile unsigned int*)(0x42CE17A0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A9           *((volatile unsigned int*)(0x42CE17A4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A10          *((volatile unsigned int*)(0x42CE17A8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A11          *((volatile unsigned int*)(0x42CE17ACUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A12          *((volatile unsigned int*)(0x42CE17B0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A13          *((volatile unsigned int*)(0x42CE17B4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A14          *((volatile unsigned int*)(0x42CE17B8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A15          *((volatile unsigned int*)(0x42CE17BCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A16          *((volatile unsigned int*)(0x42CE17C0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A17          *((volatile unsigned int*)(0x42CE17C4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A18          *((volatile unsigned int*)(0x42CE17C8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A19          *((volatile unsigned int*)(0x42CE17CCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A20          *((volatile unsigned int*)(0x42CE17D0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A21          *((volatile unsigned int*)(0x42CE17D4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A22          *((volatile unsigned int*)(0x42CE17D8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A23          *((volatile unsigned int*)(0x42CE17DCUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A24          *((volatile unsigned int*)(0x42CE17E0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A25          *((volatile unsigned int*)(0x42CE17E4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A26          *((volatile unsigned int*)(0x42CE17E8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A27          *((volatile unsigned int*)(0x42CE17ECUL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A28          *((volatile unsigned int*)(0x42CE17F0UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A29          *((volatile unsigned int*)(0x42CE17F4UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A30          *((volatile unsigned int*)(0x42CE17F8UL))
+#define bFM3_ETHERNET_MAC1_MAR15L_A31          *((volatile unsigned int*)(0x42CE17FCUL))
+#define bFM3_ETHERNET_MAC1_RGSR_LM             *((volatile unsigned int*)(0x42CE1B00UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP0           *((volatile unsigned int*)(0x42CE1B04UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LSP1           *((volatile unsigned int*)(0x42CE1B08UL))
+#define bFM3_ETHERNET_MAC1_RGSR_LS             *((volatile unsigned int*)(0x42CE1B0CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSE            *((volatile unsigned int*)(0x42CEE000UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TFCU           *((volatile unsigned int*)(0x42CEE004UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSI            *((volatile unsigned int*)(0x42CEE008UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSU            *((volatile unsigned int*)(0x42CEE00CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TITE           *((volatile unsigned int*)(0x42CEE010UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TARU           *((volatile unsigned int*)(0x42CEE014UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSEA           *((volatile unsigned int*)(0x42CEE020UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSDB           *((volatile unsigned int*)(0x42CEE024UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSV2E          *((volatile unsigned int*)(0x42CEE028UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSP          *((volatile unsigned int*)(0x42CEE02CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP6E         *((volatile unsigned int*)(0x42CEE030UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSIP4E         *((volatile unsigned int*)(0x42CEE034UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TETSEM         *((volatile unsigned int*)(0x42CEE038UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSMRM          *((volatile unsigned int*)(0x42CEE03CUL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS0          *((volatile unsigned int*)(0x42CEE040UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSPS1          *((volatile unsigned int*)(0x42CEE044UL))
+#define bFM3_ETHERNET_MAC1_TSCR_TSENMF         *((volatile unsigned int*)(0x42CEE048UL))
+#define bFM3_ETHERNET_MAC1_TSCR_ATSFC          *((volatile unsigned int*)(0x42CEE060UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC0         *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC1         *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC2         *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC3         *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC4         *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC5         *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC6         *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_SSIR_SSINC7         *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS0           *((volatile unsigned int*)(0x42CEE100UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS1           *((volatile unsigned int*)(0x42CEE104UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS2           *((volatile unsigned int*)(0x42CEE108UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS3           *((volatile unsigned int*)(0x42CEE10CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS4           *((volatile unsigned int*)(0x42CEE110UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS5           *((volatile unsigned int*)(0x42CEE114UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS6           *((volatile unsigned int*)(0x42CEE118UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS7           *((volatile unsigned int*)(0x42CEE11CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS8           *((volatile unsigned int*)(0x42CEE120UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS9           *((volatile unsigned int*)(0x42CEE124UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS10          *((volatile unsigned int*)(0x42CEE128UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS11          *((volatile unsigned int*)(0x42CEE12CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS12          *((volatile unsigned int*)(0x42CEE130UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS13          *((volatile unsigned int*)(0x42CEE134UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS14          *((volatile unsigned int*)(0x42CEE138UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS15          *((volatile unsigned int*)(0x42CEE13CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS16          *((volatile unsigned int*)(0x42CEE140UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS17          *((volatile unsigned int*)(0x42CEE144UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS18          *((volatile unsigned int*)(0x42CEE148UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS19          *((volatile unsigned int*)(0x42CEE14CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS20          *((volatile unsigned int*)(0x42CEE150UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS21          *((volatile unsigned int*)(0x42CEE154UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS22          *((volatile unsigned int*)(0x42CEE158UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS23          *((volatile unsigned int*)(0x42CEE15CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS24          *((volatile unsigned int*)(0x42CEE160UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS25          *((volatile unsigned int*)(0x42CEE164UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS26          *((volatile unsigned int*)(0x42CEE168UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS27          *((volatile unsigned int*)(0x42CEE16CUL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS28          *((volatile unsigned int*)(0x42CEE170UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS29          *((volatile unsigned int*)(0x42CEE174UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS30          *((volatile unsigned int*)(0x42CEE178UL))
+#define bFM3_ETHERNET_MAC1_STSR_TSS31          *((volatile unsigned int*)(0x42CEE17CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS0          *((volatile unsigned int*)(0x42CEE080UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS1          *((volatile unsigned int*)(0x42CEE084UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS2          *((volatile unsigned int*)(0x42CEE088UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS3          *((volatile unsigned int*)(0x42CEE08CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS4          *((volatile unsigned int*)(0x42CEE090UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS5          *((volatile unsigned int*)(0x42CEE094UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS6          *((volatile unsigned int*)(0x42CEE098UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS7          *((volatile unsigned int*)(0x42CEE09CUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS8          *((volatile unsigned int*)(0x42CEE0A0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS9          *((volatile unsigned int*)(0x42CEE0A4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS10         *((volatile unsigned int*)(0x42CEE0A8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS11         *((volatile unsigned int*)(0x42CEE0ACUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS12         *((volatile unsigned int*)(0x42CEE0B0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS13         *((volatile unsigned int*)(0x42CEE0B4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS14         *((volatile unsigned int*)(0x42CEE0B8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS15         *((volatile unsigned int*)(0x42CEE0BCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS16         *((volatile unsigned int*)(0x42CEE0C0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS17         *((volatile unsigned int*)(0x42CEE0C4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS18         *((volatile unsigned int*)(0x42CEE0C8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS19         *((volatile unsigned int*)(0x42CEE0CCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS20         *((volatile unsigned int*)(0x42CEE0D0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS21         *((volatile unsigned int*)(0x42CEE0D4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS22         *((volatile unsigned int*)(0x42CEE0D8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS23         *((volatile unsigned int*)(0x42CEE0DCUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS24         *((volatile unsigned int*)(0x42CEE0E0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS25         *((volatile unsigned int*)(0x42CEE0E4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS26         *((volatile unsigned int*)(0x42CEE0E8UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS27         *((volatile unsigned int*)(0x42CEE0ECUL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS28         *((volatile unsigned int*)(0x42CEE0F0UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS29         *((volatile unsigned int*)(0x42CEE0F4UL))
+#define bFM3_ETHERNET_MAC1_STNR_TSSS30         *((volatile unsigned int*)(0x42CEE0F8UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS0          *((volatile unsigned int*)(0x42CEE200UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS1          *((volatile unsigned int*)(0x42CEE204UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS2          *((volatile unsigned int*)(0x42CEE208UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS3          *((volatile unsigned int*)(0x42CEE20CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS4          *((volatile unsigned int*)(0x42CEE210UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS5          *((volatile unsigned int*)(0x42CEE214UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS6          *((volatile unsigned int*)(0x42CEE218UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS7          *((volatile unsigned int*)(0x42CEE21CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS8          *((volatile unsigned int*)(0x42CEE220UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS9          *((volatile unsigned int*)(0x42CEE224UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS10         *((volatile unsigned int*)(0x42CEE228UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS11         *((volatile unsigned int*)(0x42CEE22CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS12         *((volatile unsigned int*)(0x42CEE230UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS13         *((volatile unsigned int*)(0x42CEE234UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS14         *((volatile unsigned int*)(0x42CEE238UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS15         *((volatile unsigned int*)(0x42CEE23CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS16         *((volatile unsigned int*)(0x42CEE240UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS17         *((volatile unsigned int*)(0x42CEE244UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS18         *((volatile unsigned int*)(0x42CEE248UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS19         *((volatile unsigned int*)(0x42CEE24CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS20         *((volatile unsigned int*)(0x42CEE250UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS21         *((volatile unsigned int*)(0x42CEE254UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS22         *((volatile unsigned int*)(0x42CEE258UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS23         *((volatile unsigned int*)(0x42CEE25CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS24         *((volatile unsigned int*)(0x42CEE260UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS25         *((volatile unsigned int*)(0x42CEE264UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS26         *((volatile unsigned int*)(0x42CEE268UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS27         *((volatile unsigned int*)(0x42CEE26CUL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS28         *((volatile unsigned int*)(0x42CEE270UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS29         *((volatile unsigned int*)(0x42CEE274UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS30         *((volatile unsigned int*)(0x42CEE278UL))
+#define bFM3_ETHERNET_MAC1_STSUR_TSS31         *((volatile unsigned int*)(0x42CEE27CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS0         *((volatile unsigned int*)(0x42CEE280UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS1         *((volatile unsigned int*)(0x42CEE284UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS2         *((volatile unsigned int*)(0x42CEE288UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS3         *((volatile unsigned int*)(0x42CEE28CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS4         *((volatile unsigned int*)(0x42CEE290UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS5         *((volatile unsigned int*)(0x42CEE294UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS6         *((volatile unsigned int*)(0x42CEE298UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS7         *((volatile unsigned int*)(0x42CEE29CUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS8         *((volatile unsigned int*)(0x42CEE2A0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS9         *((volatile unsigned int*)(0x42CEE2A4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS10        *((volatile unsigned int*)(0x42CEE2A8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS11        *((volatile unsigned int*)(0x42CEE2ACUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS12        *((volatile unsigned int*)(0x42CEE2B0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS13        *((volatile unsigned int*)(0x42CEE2B4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS14        *((volatile unsigned int*)(0x42CEE2B8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS15        *((volatile unsigned int*)(0x42CEE2BCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS16        *((volatile unsigned int*)(0x42CEE2C0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS17        *((volatile unsigned int*)(0x42CEE2C4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS18        *((volatile unsigned int*)(0x42CEE2C8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS19        *((volatile unsigned int*)(0x42CEE2CCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS20        *((volatile unsigned int*)(0x42CEE2D0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS21        *((volatile unsigned int*)(0x42CEE2D4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS22        *((volatile unsigned int*)(0x42CEE2D8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS23        *((volatile unsigned int*)(0x42CEE2DCUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS24        *((volatile unsigned int*)(0x42CEE2E0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS25        *((volatile unsigned int*)(0x42CEE2E4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS26        *((volatile unsigned int*)(0x42CEE2E8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS27        *((volatile unsigned int*)(0x42CEE2ECUL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS28        *((volatile unsigned int*)(0x42CEE2F0UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS29        *((volatile unsigned int*)(0x42CEE2F4UL))
+#define bFM3_ETHERNET_MAC1_STNUR_TSSS30        *((volatile unsigned int*)(0x42CEE2F8UL))
+#define bFM3_ETHERNET_MAC1_STNUR_ADDSUB        *((volatile unsigned int*)(0x42CEE2FCUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR0          *((volatile unsigned int*)(0x42CEE300UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR1          *((volatile unsigned int*)(0x42CEE304UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR2          *((volatile unsigned int*)(0x42CEE308UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR3          *((volatile unsigned int*)(0x42CEE30CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR4          *((volatile unsigned int*)(0x42CEE310UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR5          *((volatile unsigned int*)(0x42CEE314UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR6          *((volatile unsigned int*)(0x42CEE318UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR7          *((volatile unsigned int*)(0x42CEE31CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR8          *((volatile unsigned int*)(0x42CEE320UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR9          *((volatile unsigned int*)(0x42CEE324UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR10         *((volatile unsigned int*)(0x42CEE328UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR11         *((volatile unsigned int*)(0x42CEE32CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR12         *((volatile unsigned int*)(0x42CEE330UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR13         *((volatile unsigned int*)(0x42CEE334UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR14         *((volatile unsigned int*)(0x42CEE338UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR15         *((volatile unsigned int*)(0x42CEE33CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR16         *((volatile unsigned int*)(0x42CEE340UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR17         *((volatile unsigned int*)(0x42CEE344UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR18         *((volatile unsigned int*)(0x42CEE348UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR19         *((volatile unsigned int*)(0x42CEE34CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR20         *((volatile unsigned int*)(0x42CEE350UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR21         *((volatile unsigned int*)(0x42CEE354UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR22         *((volatile unsigned int*)(0x42CEE358UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR23         *((volatile unsigned int*)(0x42CEE35CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR24         *((volatile unsigned int*)(0x42CEE360UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR25         *((volatile unsigned int*)(0x42CEE364UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR26         *((volatile unsigned int*)(0x42CEE368UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR27         *((volatile unsigned int*)(0x42CEE36CUL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR28         *((volatile unsigned int*)(0x42CEE370UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR29         *((volatile unsigned int*)(0x42CEE374UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR30         *((volatile unsigned int*)(0x42CEE378UL))
+#define bFM3_ETHERNET_MAC1_TSAR_TSAR31         *((volatile unsigned int*)(0x42CEE37CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR0          *((volatile unsigned int*)(0x42CEE380UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR1          *((volatile unsigned int*)(0x42CEE384UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR2          *((volatile unsigned int*)(0x42CEE388UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR3          *((volatile unsigned int*)(0x42CEE38CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR4          *((volatile unsigned int*)(0x42CEE390UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR5          *((volatile unsigned int*)(0x42CEE394UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR6          *((volatile unsigned int*)(0x42CEE398UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR7          *((volatile unsigned int*)(0x42CEE39CUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR8          *((volatile unsigned int*)(0x42CEE3A0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR9          *((volatile unsigned int*)(0x42CEE3A4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR10         *((volatile unsigned int*)(0x42CEE3A8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR11         *((volatile unsigned int*)(0x42CEE3ACUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR12         *((volatile unsigned int*)(0x42CEE3B0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR13         *((volatile unsigned int*)(0x42CEE3B4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR14         *((volatile unsigned int*)(0x42CEE3B8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR15         *((volatile unsigned int*)(0x42CEE3BCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR16         *((volatile unsigned int*)(0x42CEE3C0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR17         *((volatile unsigned int*)(0x42CEE3C4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR18         *((volatile unsigned int*)(0x42CEE3C8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR19         *((volatile unsigned int*)(0x42CEE3CCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR20         *((volatile unsigned int*)(0x42CEE3D0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR21         *((volatile unsigned int*)(0x42CEE3D4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR22         *((volatile unsigned int*)(0x42CEE3D8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR23         *((volatile unsigned int*)(0x42CEE3DCUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR24         *((volatile unsigned int*)(0x42CEE3E0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR25         *((volatile unsigned int*)(0x42CEE3E4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR26         *((volatile unsigned int*)(0x42CEE3E8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR27         *((volatile unsigned int*)(0x42CEE3ECUL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR28         *((volatile unsigned int*)(0x42CEE3F0UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR29         *((volatile unsigned int*)(0x42CEE3F4UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR30         *((volatile unsigned int*)(0x42CEE3F8UL))
+#define bFM3_ETHERNET_MAC1_TTSR_TSTR31         *((volatile unsigned int*)(0x42CEE3FCUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR0          *((volatile unsigned int*)(0x42CEE400UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR1          *((volatile unsigned int*)(0x42CEE404UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR2          *((volatile unsigned int*)(0x42CEE408UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR3          *((volatile unsigned int*)(0x42CEE40CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR4          *((volatile unsigned int*)(0x42CEE410UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR5          *((volatile unsigned int*)(0x42CEE414UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR6          *((volatile unsigned int*)(0x42CEE418UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR7          *((volatile unsigned int*)(0x42CEE41CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR8          *((volatile unsigned int*)(0x42CEE420UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR9          *((volatile unsigned int*)(0x42CEE424UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR10         *((volatile unsigned int*)(0x42CEE428UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR11         *((volatile unsigned int*)(0x42CEE42CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR12         *((volatile unsigned int*)(0x42CEE430UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR13         *((volatile unsigned int*)(0x42CEE434UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR14         *((volatile unsigned int*)(0x42CEE438UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR15         *((volatile unsigned int*)(0x42CEE43CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR16         *((volatile unsigned int*)(0x42CEE440UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR17         *((volatile unsigned int*)(0x42CEE444UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR18         *((volatile unsigned int*)(0x42CEE448UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR19         *((volatile unsigned int*)(0x42CEE44CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR20         *((volatile unsigned int*)(0x42CEE450UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR21         *((volatile unsigned int*)(0x42CEE454UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR22         *((volatile unsigned int*)(0x42CEE458UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR23         *((volatile unsigned int*)(0x42CEE45CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR24         *((volatile unsigned int*)(0x42CEE460UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR25         *((volatile unsigned int*)(0x42CEE464UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR26         *((volatile unsigned int*)(0x42CEE468UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR27         *((volatile unsigned int*)(0x42CEE46CUL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR28         *((volatile unsigned int*)(0x42CEE470UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR29         *((volatile unsigned int*)(0x42CEE474UL))
+#define bFM3_ETHERNET_MAC1_TTNR_TSTR30         *((volatile unsigned int*)(0x42CEE478UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR0       *((volatile unsigned int*)(0x42CEE480UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR1       *((volatile unsigned int*)(0x42CEE484UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR2       *((volatile unsigned int*)(0x42CEE488UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR3       *((volatile unsigned int*)(0x42CEE48CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR4       *((volatile unsigned int*)(0x42CEE490UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR5       *((volatile unsigned int*)(0x42CEE494UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR6       *((volatile unsigned int*)(0x42CEE498UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR7       *((volatile unsigned int*)(0x42CEE49CUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR8       *((volatile unsigned int*)(0x42CEE4A0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR9       *((volatile unsigned int*)(0x42CEE4A4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR10      *((volatile unsigned int*)(0x42CEE4A8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR11      *((volatile unsigned int*)(0x42CEE4ACUL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR12      *((volatile unsigned int*)(0x42CEE4B0UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR13      *((volatile unsigned int*)(0x42CEE4B4UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR14      *((volatile unsigned int*)(0x42CEE4B8UL))
+#define bFM3_ETHERNET_MAC1_STHWSR_TSHWR15      *((volatile unsigned int*)(0x42CEE4BCUL))
+#define bFM3_ETHERNET_MAC1_TSR_TSSOVF          *((volatile unsigned int*)(0x42CEE500UL))
+#define bFM3_ETHERNET_MAC1_TSR_TSTART          *((volatile unsigned int*)(0x42CEE504UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSTS           *((volatile unsigned int*)(0x42CEE508UL))
+#define bFM3_ETHERNET_MAC1_TSR_TRGTER          *((volatile unsigned int*)(0x42C8E50CUL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSSTM          *((volatile unsigned int*)(0x42CEE560UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS0          *((volatile unsigned int*)(0x42CEE564UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS1          *((volatile unsigned int*)(0x42CEE568UL))
+#define bFM3_ETHERNET_MAC1_TSR_ATSNS2          *((volatile unsigned int*)(0x42CEE56CUL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL0      *((volatile unsigned int*)(0x42CEE580UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL1      *((volatile unsigned int*)(0x42CEE584UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL2      *((volatile unsigned int*)(0x42CEE588UL))
+#define bFM3_ETHERNET_MAC1_PPSCR_PPSCTRL3      *((volatile unsigned int*)(0x42CEE58CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN0           *((volatile unsigned int*)(0x42CEE600UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN1           *((volatile unsigned int*)(0x42CEE604UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN2           *((volatile unsigned int*)(0x42CEE608UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN3           *((volatile unsigned int*)(0x42CEE60CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN4           *((volatile unsigned int*)(0x42CEE610UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN5           *((volatile unsigned int*)(0x42CEE614UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN6           *((volatile unsigned int*)(0x42CEE618UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN7           *((volatile unsigned int*)(0x42CEE61CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN8           *((volatile unsigned int*)(0x42CEE620UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN9           *((volatile unsigned int*)(0x42CEE624UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN10          *((volatile unsigned int*)(0x42CEE628UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN11          *((volatile unsigned int*)(0x42CEE62CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN12          *((volatile unsigned int*)(0x42CEE630UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN13          *((volatile unsigned int*)(0x42CEE634UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN14          *((volatile unsigned int*)(0x42CEE638UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN15          *((volatile unsigned int*)(0x42CEE63CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN16          *((volatile unsigned int*)(0x42CEE640UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN17          *((volatile unsigned int*)(0x42CEE644UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN18          *((volatile unsigned int*)(0x42CEE648UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN19          *((volatile unsigned int*)(0x42CEE64CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN20          *((volatile unsigned int*)(0x42CEE650UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN21          *((volatile unsigned int*)(0x42CEE654UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN22          *((volatile unsigned int*)(0x42CEE658UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN23          *((volatile unsigned int*)(0x42CEE65CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN24          *((volatile unsigned int*)(0x42CEE660UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN25          *((volatile unsigned int*)(0x42CEE664UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN26          *((volatile unsigned int*)(0x42CEE668UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN27          *((volatile unsigned int*)(0x42CEE66CUL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN28          *((volatile unsigned int*)(0x42CEE670UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN29          *((volatile unsigned int*)(0x42CEE674UL))
+#define bFM3_ETHERNET_MAC1_ATNR_ATN30          *((volatile unsigned int*)(0x42CEE678UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS0           *((volatile unsigned int*)(0x42CEE680UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS1           *((volatile unsigned int*)(0x42CEE684UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS2           *((volatile unsigned int*)(0x42CEE688UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS3           *((volatile unsigned int*)(0x42CEE68CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS4           *((volatile unsigned int*)(0x42CEE690UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS5           *((volatile unsigned int*)(0x42CEE694UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS6           *((volatile unsigned int*)(0x42CEE698UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS7           *((volatile unsigned int*)(0x42CEE69CUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS8           *((volatile unsigned int*)(0x42CEE6A0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS9           *((volatile unsigned int*)(0x42CEE6A4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS10          *((volatile unsigned int*)(0x42CEE6A8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS11          *((volatile unsigned int*)(0x42CEE6ACUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS12          *((volatile unsigned int*)(0x42CEE6B0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS13          *((volatile unsigned int*)(0x42CEE6B4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS14          *((volatile unsigned int*)(0x42CEE6B8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS15          *((volatile unsigned int*)(0x42CEE6BCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS16          *((volatile unsigned int*)(0x42CEE6C0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS17          *((volatile unsigned int*)(0x42CEE6C4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS18          *((volatile unsigned int*)(0x42CEE6C8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS19          *((volatile unsigned int*)(0x42CEE6CCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS20          *((volatile unsigned int*)(0x42CEE6D0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS21          *((volatile unsigned int*)(0x42CEE6D4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS22          *((volatile unsigned int*)(0x42CEE6D8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS23          *((volatile unsigned int*)(0x42CEE6DCUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS24          *((volatile unsigned int*)(0x42CEE6E0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS25          *((volatile unsigned int*)(0x42CEE6E4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS26          *((volatile unsigned int*)(0x42CEE6E8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS27          *((volatile unsigned int*)(0x42CEE6ECUL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS28          *((volatile unsigned int*)(0x42CEE6F0UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS29          *((volatile unsigned int*)(0x42CEE6F4UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS30          *((volatile unsigned int*)(0x42CEE6F8UL))
+#define bFM3_ETHERNET_MAC1_ATSR_ATS31          *((volatile unsigned int*)(0x42CEE6FCUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A32          *((volatile unsigned int*)(0x42CF0000UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A33          *((volatile unsigned int*)(0x42CF0004UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A34          *((volatile unsigned int*)(0x42CF0008UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A35          *((volatile unsigned int*)(0x42CF000CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A36          *((volatile unsigned int*)(0x42CF0010UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A37          *((volatile unsigned int*)(0x42CF0014UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A38          *((volatile unsigned int*)(0x42CF0018UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A39          *((volatile unsigned int*)(0x42CF001CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A40          *((volatile unsigned int*)(0x42CF0020UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A41          *((volatile unsigned int*)(0x42CF0024UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A42          *((volatile unsigned int*)(0x42CF0028UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A43          *((volatile unsigned int*)(0x42CF002CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A44          *((volatile unsigned int*)(0x42CF0030UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A45          *((volatile unsigned int*)(0x42CF0034UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A46          *((volatile unsigned int*)(0x42CF0038UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_A47          *((volatile unsigned int*)(0x42CF003CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC0         *((volatile unsigned int*)(0x42CF0060UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC1         *((volatile unsigned int*)(0x42CF0064UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC2         *((volatile unsigned int*)(0x42CF0068UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC3         *((volatile unsigned int*)(0x42CF006CUL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC4         *((volatile unsigned int*)(0x42CF0070UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_MBC5         *((volatile unsigned int*)(0x42CF0074UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_SA           *((volatile unsigned int*)(0x42CF0078UL))
+#define bFM3_ETHERNET_MAC1_MAR16H_AE           *((volatile unsigned int*)(0x42CF007CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A0           *((volatile unsigned int*)(0x42CF0080UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A1           *((volatile unsigned int*)(0x42CF0084UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A2           *((volatile unsigned int*)(0x42CF0088UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A3           *((volatile unsigned int*)(0x42CF008CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A4           *((volatile unsigned int*)(0x42CF0090UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A5           *((volatile unsigned int*)(0x42CF0094UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A6           *((volatile unsigned int*)(0x42CF0098UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A7           *((volatile unsigned int*)(0x42CF009CUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A8           *((volatile unsigned int*)(0x42CF00A0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A9           *((volatile unsigned int*)(0x42CF00A4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A10          *((volatile unsigned int*)(0x42CF00A8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A11          *((volatile unsigned int*)(0x42CF00ACUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A12          *((volatile unsigned int*)(0x42CF00B0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A13          *((volatile unsigned int*)(0x42CF00B4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A14          *((volatile unsigned int*)(0x42CF00B8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A15          *((volatile unsigned int*)(0x42CF00BCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A16          *((volatile unsigned int*)(0x42CF00C0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A17          *((volatile unsigned int*)(0x42CF00C4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A18          *((volatile unsigned int*)(0x42CF00C8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A19          *((volatile unsigned int*)(0x42CF00CCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A20          *((volatile unsigned int*)(0x42CF00D0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A21          *((volatile unsigned int*)(0x42CF00D4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A22          *((volatile unsigned int*)(0x42CF00D8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A23          *((volatile unsigned int*)(0x42CF00DCUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A24          *((volatile unsigned int*)(0x42CF00E0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A25          *((volatile unsigned int*)(0x42CF00E4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A26          *((volatile unsigned int*)(0x42CF00E8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A27          *((volatile unsigned int*)(0x42CF00ECUL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A28          *((volatile unsigned int*)(0x42CF00F0UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A29          *((volatile unsigned int*)(0x42CF00F4UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A30          *((volatile unsigned int*)(0x42CF00F8UL))
+#define bFM3_ETHERNET_MAC1_MAR16L_A31          *((volatile unsigned int*)(0x42CF00FCUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A32          *((volatile unsigned int*)(0x42CF0100UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A33          *((volatile unsigned int*)(0x42CF0104UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A34          *((volatile unsigned int*)(0x42CF0108UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A35          *((volatile unsigned int*)(0x42CF010CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A36          *((volatile unsigned int*)(0x42CF0110UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A37          *((volatile unsigned int*)(0x42CF0114UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A38          *((volatile unsigned int*)(0x42CF0118UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A39          *((volatile unsigned int*)(0x42CF011CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A40          *((volatile unsigned int*)(0x42CF0120UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A41          *((volatile unsigned int*)(0x42CF0124UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A42          *((volatile unsigned int*)(0x42CF0128UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A43          *((volatile unsigned int*)(0x42CF012CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A44          *((volatile unsigned int*)(0x42CF0130UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A45          *((volatile unsigned int*)(0x42CF0134UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A46          *((volatile unsigned int*)(0x42CF0138UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_A47          *((volatile unsigned int*)(0x42CF013CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC0         *((volatile unsigned int*)(0x42CF0160UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC1         *((volatile unsigned int*)(0x42CF0164UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC2         *((volatile unsigned int*)(0x42CF0168UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC3         *((volatile unsigned int*)(0x42CF016CUL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC4         *((volatile unsigned int*)(0x42CF0170UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_MBC5         *((volatile unsigned int*)(0x42CF0174UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_SA           *((volatile unsigned int*)(0x42CF0178UL))
+#define bFM3_ETHERNET_MAC1_MAR17H_AE           *((volatile unsigned int*)(0x42CF017CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A0           *((volatile unsigned int*)(0x42CF0180UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A1           *((volatile unsigned int*)(0x42CF0184UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A2           *((volatile unsigned int*)(0x42CF0188UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A3           *((volatile unsigned int*)(0x42CF018CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A4           *((volatile unsigned int*)(0x42CF0190UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A5           *((volatile unsigned int*)(0x42CF0194UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A6           *((volatile unsigned int*)(0x42CF0198UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A7           *((volatile unsigned int*)(0x42CF019CUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A8           *((volatile unsigned int*)(0x42CF01A0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A9           *((volatile unsigned int*)(0x42CF01A4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A10          *((volatile unsigned int*)(0x42CF01A8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A11          *((volatile unsigned int*)(0x42CF01ACUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A12          *((volatile unsigned int*)(0x42CF01B0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A13          *((volatile unsigned int*)(0x42CF01B4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A14          *((volatile unsigned int*)(0x42CF01B8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A15          *((volatile unsigned int*)(0x42CF01BCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A16          *((volatile unsigned int*)(0x42CF01C0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A17          *((volatile unsigned int*)(0x42CF01C4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A18          *((volatile unsigned int*)(0x42CF01C8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A19          *((volatile unsigned int*)(0x42CF01CCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A20          *((volatile unsigned int*)(0x42CF01D0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A21          *((volatile unsigned int*)(0x42CF01D4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A22          *((volatile unsigned int*)(0x42CF01D8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A23          *((volatile unsigned int*)(0x42CF01DCUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A24          *((volatile unsigned int*)(0x42CF01E0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A25          *((volatile unsigned int*)(0x42CF01E4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A26          *((volatile unsigned int*)(0x42CF01E8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A27          *((volatile unsigned int*)(0x42CF01ECUL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A28          *((volatile unsigned int*)(0x42CF01F0UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A29          *((volatile unsigned int*)(0x42CF01F4UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A30          *((volatile unsigned int*)(0x42CF01F8UL))
+#define bFM3_ETHERNET_MAC1_MAR17L_A31          *((volatile unsigned int*)(0x42CF01FCUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A32          *((volatile unsigned int*)(0x42CF0200UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A33          *((volatile unsigned int*)(0x42CF0204UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A34          *((volatile unsigned int*)(0x42CF0208UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A35          *((volatile unsigned int*)(0x42CF020CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A36          *((volatile unsigned int*)(0x42CF0210UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A37          *((volatile unsigned int*)(0x42CF0214UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A38          *((volatile unsigned int*)(0x42CF0218UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A39          *((volatile unsigned int*)(0x42CF021CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A40          *((volatile unsigned int*)(0x42CF0220UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A41          *((volatile unsigned int*)(0x42CF0224UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A42          *((volatile unsigned int*)(0x42CF0228UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A43          *((volatile unsigned int*)(0x42CF022CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A44          *((volatile unsigned int*)(0x42CF0230UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A45          *((volatile unsigned int*)(0x42CF0234UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A46          *((volatile unsigned int*)(0x42CF0238UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_A47          *((volatile unsigned int*)(0x42CF023CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC0         *((volatile unsigned int*)(0x42CF0260UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC1         *((volatile unsigned int*)(0x42CF0264UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC2         *((volatile unsigned int*)(0x42CF0268UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC3         *((volatile unsigned int*)(0x42CF026CUL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC4         *((volatile unsigned int*)(0x42CF0270UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_MBC5         *((volatile unsigned int*)(0x42CF0274UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_SA           *((volatile unsigned int*)(0x42CF0278UL))
+#define bFM3_ETHERNET_MAC1_MAR18H_AE           *((volatile unsigned int*)(0x42CF027CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A0           *((volatile unsigned int*)(0x42CF0280UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A1           *((volatile unsigned int*)(0x42CF0284UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A2           *((volatile unsigned int*)(0x42CF0288UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A3           *((volatile unsigned int*)(0x42CF028CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A4           *((volatile unsigned int*)(0x42CF0290UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A5           *((volatile unsigned int*)(0x42CF0294UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A6           *((volatile unsigned int*)(0x42CF0298UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A7           *((volatile unsigned int*)(0x42CF029CUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A8           *((volatile unsigned int*)(0x42CF02A0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A9           *((volatile unsigned int*)(0x42CF02A4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A10          *((volatile unsigned int*)(0x42CF02A8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A11          *((volatile unsigned int*)(0x42CF02ACUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A12          *((volatile unsigned int*)(0x42CF02B0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A13          *((volatile unsigned int*)(0x42CF02B4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A14          *((volatile unsigned int*)(0x42CF02B8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A15          *((volatile unsigned int*)(0x42CF02BCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A16          *((volatile unsigned int*)(0x42CF02C0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A17          *((volatile unsigned int*)(0x42CF02C4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A18          *((volatile unsigned int*)(0x42CF02C8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A19          *((volatile unsigned int*)(0x42CF02CCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A20          *((volatile unsigned int*)(0x42CF02D0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A21          *((volatile unsigned int*)(0x42CF02D4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A22          *((volatile unsigned int*)(0x42CF02D8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A23          *((volatile unsigned int*)(0x42CF02DCUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A24          *((volatile unsigned int*)(0x42CF02E0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A25          *((volatile unsigned int*)(0x42CF02E4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A26          *((volatile unsigned int*)(0x42CF02E8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A27          *((volatile unsigned int*)(0x42CF02ECUL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A28          *((volatile unsigned int*)(0x42CF02F0UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A29          *((volatile unsigned int*)(0x42CF02F4UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A30          *((volatile unsigned int*)(0x42CF02F8UL))
+#define bFM3_ETHERNET_MAC1_MAR18L_A31          *((volatile unsigned int*)(0x42CF02FCUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A32          *((volatile unsigned int*)(0x42CF0300UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A33          *((volatile unsigned int*)(0x42CF0304UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A34          *((volatile unsigned int*)(0x42CF0308UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A35          *((volatile unsigned int*)(0x42CF030CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A36          *((volatile unsigned int*)(0x42CF0310UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A37          *((volatile unsigned int*)(0x42CF0314UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A38          *((volatile unsigned int*)(0x42CF0318UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A39          *((volatile unsigned int*)(0x42CF031CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A40          *((volatile unsigned int*)(0x42CF0320UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A41          *((volatile unsigned int*)(0x42CF0324UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A42          *((volatile unsigned int*)(0x42CF0328UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A43          *((volatile unsigned int*)(0x42CF032CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A44          *((volatile unsigned int*)(0x42CF0330UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A45          *((volatile unsigned int*)(0x42CF0334UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A46          *((volatile unsigned int*)(0x42CF0338UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_A47          *((volatile unsigned int*)(0x42CF033CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC0         *((volatile unsigned int*)(0x42CF0360UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC1         *((volatile unsigned int*)(0x42CF0364UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC2         *((volatile unsigned int*)(0x42CF0368UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC3         *((volatile unsigned int*)(0x42CF036CUL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC4         *((volatile unsigned int*)(0x42CF0370UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_MBC5         *((volatile unsigned int*)(0x42CF0374UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_SA           *((volatile unsigned int*)(0x42CF0378UL))
+#define bFM3_ETHERNET_MAC1_MAR19H_AE           *((volatile unsigned int*)(0x42CF037CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A0           *((volatile unsigned int*)(0x42CF0380UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A1           *((volatile unsigned int*)(0x42CF0384UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A2           *((volatile unsigned int*)(0x42CF0388UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A3           *((volatile unsigned int*)(0x42CF038CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A4           *((volatile unsigned int*)(0x42CF0390UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A5           *((volatile unsigned int*)(0x42CF0394UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A6           *((volatile unsigned int*)(0x42CF0398UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A7           *((volatile unsigned int*)(0x42CF039CUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A8           *((volatile unsigned int*)(0x42CF03A0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A9           *((volatile unsigned int*)(0x42CF03A4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A10          *((volatile unsigned int*)(0x42CF03A8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A11          *((volatile unsigned int*)(0x42CF03ACUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A12          *((volatile unsigned int*)(0x42CF03B0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A13          *((volatile unsigned int*)(0x42CF03B4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A14          *((volatile unsigned int*)(0x42CF03B8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A15          *((volatile unsigned int*)(0x42CF03BCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A16          *((volatile unsigned int*)(0x42CF03C0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A17          *((volatile unsigned int*)(0x42CF03C4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A18          *((volatile unsigned int*)(0x42CF03C8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A19          *((volatile unsigned int*)(0x42CF03CCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A20          *((volatile unsigned int*)(0x42CF03D0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A21          *((volatile unsigned int*)(0x42CF03D4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A22          *((volatile unsigned int*)(0x42CF03D8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A23          *((volatile unsigned int*)(0x42CF03DCUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A24          *((volatile unsigned int*)(0x42CF03E0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A25          *((volatile unsigned int*)(0x42CF03E4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A26          *((volatile unsigned int*)(0x42CF03E8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A27          *((volatile unsigned int*)(0x42CF03ECUL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A28          *((volatile unsigned int*)(0x42CF03F0UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A29          *((volatile unsigned int*)(0x42CF03F4UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A30          *((volatile unsigned int*)(0x42CF03F8UL))
+#define bFM3_ETHERNET_MAC1_MAR19L_A31          *((volatile unsigned int*)(0x42CF03FCUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A32          *((volatile unsigned int*)(0x42CF0400UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A33          *((volatile unsigned int*)(0x42CF0404UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A34          *((volatile unsigned int*)(0x42CF0408UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A35          *((volatile unsigned int*)(0x42CF040CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A36          *((volatile unsigned int*)(0x42CF0410UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A37          *((volatile unsigned int*)(0x42CF0414UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A38          *((volatile unsigned int*)(0x42CF0418UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A39          *((volatile unsigned int*)(0x42CF041CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A40          *((volatile unsigned int*)(0x42CF0420UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A41          *((volatile unsigned int*)(0x42CF0424UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A42          *((volatile unsigned int*)(0x42CF0428UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A43          *((volatile unsigned int*)(0x42CF042CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A44          *((volatile unsigned int*)(0x42CF0430UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A45          *((volatile unsigned int*)(0x42CF0434UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A46          *((volatile unsigned int*)(0x42CF0438UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_A47          *((volatile unsigned int*)(0x42CF043CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC0         *((volatile unsigned int*)(0x42CF0460UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC1         *((volatile unsigned int*)(0x42CF0464UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC2         *((volatile unsigned int*)(0x42CF0468UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC3         *((volatile unsigned int*)(0x42CF046CUL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC4         *((volatile unsigned int*)(0x42CF0470UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_MBC5         *((volatile unsigned int*)(0x42CF0474UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_SA           *((volatile unsigned int*)(0x42CF0478UL))
+#define bFM3_ETHERNET_MAC1_MAR20H_AE           *((volatile unsigned int*)(0x42CF047CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A0           *((volatile unsigned int*)(0x42CF0480UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A1           *((volatile unsigned int*)(0x42CF0484UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A2           *((volatile unsigned int*)(0x42CF0488UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A3           *((volatile unsigned int*)(0x42CF048CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A4           *((volatile unsigned int*)(0x42CF0490UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A5           *((volatile unsigned int*)(0x42CF0494UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A6           *((volatile unsigned int*)(0x42CF0498UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A7           *((volatile unsigned int*)(0x42CF049CUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A8           *((volatile unsigned int*)(0x42CF04A0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A9           *((volatile unsigned int*)(0x42CF04A4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A10          *((volatile unsigned int*)(0x42CF04A8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A11          *((volatile unsigned int*)(0x42CF04ACUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A12          *((volatile unsigned int*)(0x42CF04B0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A13          *((volatile unsigned int*)(0x42CF04B4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A14          *((volatile unsigned int*)(0x42CF04B8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A15          *((volatile unsigned int*)(0x42CF04BCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A16          *((volatile unsigned int*)(0x42CF04C0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A17          *((volatile unsigned int*)(0x42CF04C4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A18          *((volatile unsigned int*)(0x42CF04C8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A19          *((volatile unsigned int*)(0x42CF04CCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A20          *((volatile unsigned int*)(0x42CF04D0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A21          *((volatile unsigned int*)(0x42CF04D4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A22          *((volatile unsigned int*)(0x42CF04D8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A23          *((volatile unsigned int*)(0x42CF04DCUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A24          *((volatile unsigned int*)(0x42CF04E0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A25          *((volatile unsigned int*)(0x42CF04E4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A26          *((volatile unsigned int*)(0x42CF04E8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A27          *((volatile unsigned int*)(0x42CF04ECUL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A28          *((volatile unsigned int*)(0x42CF04F0UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A29          *((volatile unsigned int*)(0x42CF04F4UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A30          *((volatile unsigned int*)(0x42CF04F8UL))
+#define bFM3_ETHERNET_MAC1_MAR20L_A31          *((volatile unsigned int*)(0x42CF04FCUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A32          *((volatile unsigned int*)(0x42CF0500UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A33          *((volatile unsigned int*)(0x42CF0504UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A34          *((volatile unsigned int*)(0x42CF0508UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A35          *((volatile unsigned int*)(0x42CF050CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A36          *((volatile unsigned int*)(0x42CF0510UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A37          *((volatile unsigned int*)(0x42CF0514UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A38          *((volatile unsigned int*)(0x42CF0518UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A39          *((volatile unsigned int*)(0x42CF051CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A40          *((volatile unsigned int*)(0x42CF0520UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A41          *((volatile unsigned int*)(0x42CF0524UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A42          *((volatile unsigned int*)(0x42CF0528UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A43          *((volatile unsigned int*)(0x42CF052CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A44          *((volatile unsigned int*)(0x42CF0530UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A45          *((volatile unsigned int*)(0x42CF0534UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A46          *((volatile unsigned int*)(0x42CF0538UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_A47          *((volatile unsigned int*)(0x42CF053CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC0         *((volatile unsigned int*)(0x42CF0560UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC1         *((volatile unsigned int*)(0x42CF0564UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC2         *((volatile unsigned int*)(0x42CF0568UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC3         *((volatile unsigned int*)(0x42CF056CUL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC4         *((volatile unsigned int*)(0x42CF0570UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_MBC5         *((volatile unsigned int*)(0x42CF0574UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_SA           *((volatile unsigned int*)(0x42CF0578UL))
+#define bFM3_ETHERNET_MAC1_MAR21H_AE           *((volatile unsigned int*)(0x42CF057CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A0           *((volatile unsigned int*)(0x42CF0580UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A1           *((volatile unsigned int*)(0x42CF0584UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A2           *((volatile unsigned int*)(0x42CF0588UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A3           *((volatile unsigned int*)(0x42CF058CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A4           *((volatile unsigned int*)(0x42CF0590UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A5           *((volatile unsigned int*)(0x42CF0594UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A6           *((volatile unsigned int*)(0x42CF0598UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A7           *((volatile unsigned int*)(0x42CF059CUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A8           *((volatile unsigned int*)(0x42CF05A0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A9           *((volatile unsigned int*)(0x42CF05A4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A10          *((volatile unsigned int*)(0x42CF05A8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A11          *((volatile unsigned int*)(0x42CF05ACUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A12          *((volatile unsigned int*)(0x42CF05B0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A13          *((volatile unsigned int*)(0x42CF05B4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A14          *((volatile unsigned int*)(0x42CF05B8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A15          *((volatile unsigned int*)(0x42CF05BCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A16          *((volatile unsigned int*)(0x42CF05C0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A17          *((volatile unsigned int*)(0x42CF05C4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A18          *((volatile unsigned int*)(0x42CF05C8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A19          *((volatile unsigned int*)(0x42CF05CCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A20          *((volatile unsigned int*)(0x42CF05D0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A21          *((volatile unsigned int*)(0x42CF05D4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A22          *((volatile unsigned int*)(0x42CF05D8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A23          *((volatile unsigned int*)(0x42CF05DCUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A24          *((volatile unsigned int*)(0x42CF05E0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A25          *((volatile unsigned int*)(0x42CF05E4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A26          *((volatile unsigned int*)(0x42CF05E8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A27          *((volatile unsigned int*)(0x42CF05ECUL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A28          *((volatile unsigned int*)(0x42CF05F0UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A29          *((volatile unsigned int*)(0x42CF05F4UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A30          *((volatile unsigned int*)(0x42CF05F8UL))
+#define bFM3_ETHERNET_MAC1_MAR21L_A31          *((volatile unsigned int*)(0x42CF05FCUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A32          *((volatile unsigned int*)(0x42CF0600UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A33          *((volatile unsigned int*)(0x42CF0604UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A34          *((volatile unsigned int*)(0x42CF0608UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A35          *((volatile unsigned int*)(0x42CF060CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A36          *((volatile unsigned int*)(0x42CF0610UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A37          *((volatile unsigned int*)(0x42CF0614UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A38          *((volatile unsigned int*)(0x42CF0618UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A39          *((volatile unsigned int*)(0x42CF061CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A40          *((volatile unsigned int*)(0x42CF0620UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A41          *((volatile unsigned int*)(0x42CF0624UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A42          *((volatile unsigned int*)(0x42CF0628UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A43          *((volatile unsigned int*)(0x42CF062CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A44          *((volatile unsigned int*)(0x42CF0630UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A45          *((volatile unsigned int*)(0x42CF0634UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A46          *((volatile unsigned int*)(0x42CF0638UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_A47          *((volatile unsigned int*)(0x42CF063CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC0         *((volatile unsigned int*)(0x42CF0660UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC1         *((volatile unsigned int*)(0x42CF0664UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC2         *((volatile unsigned int*)(0x42CF0668UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC3         *((volatile unsigned int*)(0x42CF066CUL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC4         *((volatile unsigned int*)(0x42CF0670UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_MBC5         *((volatile unsigned int*)(0x42CF0674UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_SA           *((volatile unsigned int*)(0x42CF0678UL))
+#define bFM3_ETHERNET_MAC1_MAR22H_AE           *((volatile unsigned int*)(0x42CF067CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A0           *((volatile unsigned int*)(0x42CF0680UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A1           *((volatile unsigned int*)(0x42CF0684UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A2           *((volatile unsigned int*)(0x42CF0688UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A3           *((volatile unsigned int*)(0x42CF068CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A4           *((volatile unsigned int*)(0x42CF0690UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A5           *((volatile unsigned int*)(0x42CF0694UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A6           *((volatile unsigned int*)(0x42CF0698UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A7           *((volatile unsigned int*)(0x42CF069CUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A8           *((volatile unsigned int*)(0x42CF06A0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A9           *((volatile unsigned int*)(0x42CF06A4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A10          *((volatile unsigned int*)(0x42CF06A8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A11          *((volatile unsigned int*)(0x42CF06ACUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A12          *((volatile unsigned int*)(0x42CF06B0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A13          *((volatile unsigned int*)(0x42CF06B4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A14          *((volatile unsigned int*)(0x42CF06B8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A15          *((volatile unsigned int*)(0x42CF06BCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A16          *((volatile unsigned int*)(0x42CF06C0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A17          *((volatile unsigned int*)(0x42CF06C4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A18          *((volatile unsigned int*)(0x42CF06C8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A19          *((volatile unsigned int*)(0x42CF06CCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A20          *((volatile unsigned int*)(0x42CF06D0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A21          *((volatile unsigned int*)(0x42CF06D4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A22          *((volatile unsigned int*)(0x42CF06D8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A23          *((volatile unsigned int*)(0x42CF06DCUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A24          *((volatile unsigned int*)(0x42CF06E0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A25          *((volatile unsigned int*)(0x42CF06E4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A26          *((volatile unsigned int*)(0x42CF06E8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A27          *((volatile unsigned int*)(0x42CF06ECUL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A28          *((volatile unsigned int*)(0x42CF06F0UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A29          *((volatile unsigned int*)(0x42CF06F4UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A30          *((volatile unsigned int*)(0x42CF06F8UL))
+#define bFM3_ETHERNET_MAC1_MAR22L_A31          *((volatile unsigned int*)(0x42CF06FCUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A32          *((volatile unsigned int*)(0x42CF0700UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A33          *((volatile unsigned int*)(0x42CF0704UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A34          *((volatile unsigned int*)(0x42CF0708UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A35          *((volatile unsigned int*)(0x42CF070CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A36          *((volatile unsigned int*)(0x42CF0710UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A37          *((volatile unsigned int*)(0x42CF0714UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A38          *((volatile unsigned int*)(0x42CF0718UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A39          *((volatile unsigned int*)(0x42CF071CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A40          *((volatile unsigned int*)(0x42CF0720UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A41          *((volatile unsigned int*)(0x42CF0724UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A42          *((volatile unsigned int*)(0x42CF0728UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A43          *((volatile unsigned int*)(0x42CF072CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A44          *((volatile unsigned int*)(0x42CF0730UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A45          *((volatile unsigned int*)(0x42CF0734UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A46          *((volatile unsigned int*)(0x42CF0738UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_A47          *((volatile unsigned int*)(0x42CF073CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC0         *((volatile unsigned int*)(0x42CF0760UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC1         *((volatile unsigned int*)(0x42CF0764UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC2         *((volatile unsigned int*)(0x42CF0768UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC3         *((volatile unsigned int*)(0x42CF076CUL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC4         *((volatile unsigned int*)(0x42CF0770UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_MBC5         *((volatile unsigned int*)(0x42CF0774UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_SA           *((volatile unsigned int*)(0x42CF0778UL))
+#define bFM3_ETHERNET_MAC1_MAR23H_AE           *((volatile unsigned int*)(0x42CF077CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A0           *((volatile unsigned int*)(0x42CF0780UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A1           *((volatile unsigned int*)(0x42CF0784UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A2           *((volatile unsigned int*)(0x42CF0788UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A3           *((volatile unsigned int*)(0x42CF078CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A4           *((volatile unsigned int*)(0x42CF0790UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A5           *((volatile unsigned int*)(0x42CF0794UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A6           *((volatile unsigned int*)(0x42CF0798UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A7           *((volatile unsigned int*)(0x42CF079CUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A8           *((volatile unsigned int*)(0x42CF07A0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A9           *((volatile unsigned int*)(0x42CF07A4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A10          *((volatile unsigned int*)(0x42CF07A8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A11          *((volatile unsigned int*)(0x42CF07ACUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A12          *((volatile unsigned int*)(0x42CF07B0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A13          *((volatile unsigned int*)(0x42CF07B4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A14          *((volatile unsigned int*)(0x42CF07B8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A15          *((volatile unsigned int*)(0x42CF07BCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A16          *((volatile unsigned int*)(0x42CF07C0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A17          *((volatile unsigned int*)(0x42CF07C4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A18          *((volatile unsigned int*)(0x42CF07C8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A19          *((volatile unsigned int*)(0x42CF07CCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A20          *((volatile unsigned int*)(0x42CF07D0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A21          *((volatile unsigned int*)(0x42CF07D4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A22          *((volatile unsigned int*)(0x42CF07D8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A23          *((volatile unsigned int*)(0x42CF07DCUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A24          *((volatile unsigned int*)(0x42CF07E0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A25          *((volatile unsigned int*)(0x42CF07E4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A26          *((volatile unsigned int*)(0x42CF07E8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A27          *((volatile unsigned int*)(0x42CF07ECUL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A28          *((volatile unsigned int*)(0x42CF07F0UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A29          *((volatile unsigned int*)(0x42CF07F4UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A30          *((volatile unsigned int*)(0x42CF07F8UL))
+#define bFM3_ETHERNET_MAC1_MAR23L_A31          *((volatile unsigned int*)(0x42CF07FCUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A32          *((volatile unsigned int*)(0x42CF0800UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A33          *((volatile unsigned int*)(0x42CF0804UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A34          *((volatile unsigned int*)(0x42CF0808UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A35          *((volatile unsigned int*)(0x42CF080CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A36          *((volatile unsigned int*)(0x42CF0810UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A37          *((volatile unsigned int*)(0x42CF0814UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A38          *((volatile unsigned int*)(0x42CF0818UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A39          *((volatile unsigned int*)(0x42CF081CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A40          *((volatile unsigned int*)(0x42CF0820UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A41          *((volatile unsigned int*)(0x42CF0824UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A42          *((volatile unsigned int*)(0x42CF0828UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A43          *((volatile unsigned int*)(0x42CF082CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A44          *((volatile unsigned int*)(0x42CF0830UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A45          *((volatile unsigned int*)(0x42CF0834UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A46          *((volatile unsigned int*)(0x42CF0838UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_A47          *((volatile unsigned int*)(0x42CF083CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC0         *((volatile unsigned int*)(0x42CF0860UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC1         *((volatile unsigned int*)(0x42CF0864UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC2         *((volatile unsigned int*)(0x42CF0868UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC3         *((volatile unsigned int*)(0x42CF086CUL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC4         *((volatile unsigned int*)(0x42CF0870UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_MBC5         *((volatile unsigned int*)(0x42CF0874UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_SA           *((volatile unsigned int*)(0x42CF0878UL))
+#define bFM3_ETHERNET_MAC1_MAR24H_AE           *((volatile unsigned int*)(0x42CF087CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A0           *((volatile unsigned int*)(0x42CF0880UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A1           *((volatile unsigned int*)(0x42CF0884UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A2           *((volatile unsigned int*)(0x42CF0888UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A3           *((volatile unsigned int*)(0x42CF088CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A4           *((volatile unsigned int*)(0x42CF0890UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A5           *((volatile unsigned int*)(0x42CF0894UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A6           *((volatile unsigned int*)(0x42CF0898UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A7           *((volatile unsigned int*)(0x42CF089CUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A8           *((volatile unsigned int*)(0x42CF08A0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A9           *((volatile unsigned int*)(0x42CF08A4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A10          *((volatile unsigned int*)(0x42CF08A8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A11          *((volatile unsigned int*)(0x42CF08ACUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A12          *((volatile unsigned int*)(0x42CF08B0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A13          *((volatile unsigned int*)(0x42CF08B4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A14          *((volatile unsigned int*)(0x42CF08B8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A15          *((volatile unsigned int*)(0x42CF08BCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A16          *((volatile unsigned int*)(0x42CF08C0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A17          *((volatile unsigned int*)(0x42CF08C4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A18          *((volatile unsigned int*)(0x42CF08C8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A19          *((volatile unsigned int*)(0x42CF08CCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A20          *((volatile unsigned int*)(0x42CF08D0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A21          *((volatile unsigned int*)(0x42CF08D4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A22          *((volatile unsigned int*)(0x42CF08D8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A23          *((volatile unsigned int*)(0x42CF08DCUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A24          *((volatile unsigned int*)(0x42CF08E0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A25          *((volatile unsigned int*)(0x42CF08E4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A26          *((volatile unsigned int*)(0x42CF08E8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A27          *((volatile unsigned int*)(0x42CF08ECUL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A28          *((volatile unsigned int*)(0x42CF08F0UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A29          *((volatile unsigned int*)(0x42CF08F4UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A30          *((volatile unsigned int*)(0x42CF08F8UL))
+#define bFM3_ETHERNET_MAC1_MAR24L_A31          *((volatile unsigned int*)(0x42CF08FCUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A32          *((volatile unsigned int*)(0x42CF0900UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A33          *((volatile unsigned int*)(0x42CF0904UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A34          *((volatile unsigned int*)(0x42CF0908UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A35          *((volatile unsigned int*)(0x42CF090CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A36          *((volatile unsigned int*)(0x42CF0910UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A37          *((volatile unsigned int*)(0x42CF0914UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A38          *((volatile unsigned int*)(0x42CF0918UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A39          *((volatile unsigned int*)(0x42CF091CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A40          *((volatile unsigned int*)(0x42CF0920UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A41          *((volatile unsigned int*)(0x42CF0924UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A42          *((volatile unsigned int*)(0x42CF0928UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A43          *((volatile unsigned int*)(0x42CF092CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A44          *((volatile unsigned int*)(0x42CF0930UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A45          *((volatile unsigned int*)(0x42CF0934UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A46          *((volatile unsigned int*)(0x42CF0938UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_A47          *((volatile unsigned int*)(0x42CF093CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC0         *((volatile unsigned int*)(0x42CF0960UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC1         *((volatile unsigned int*)(0x42CF0964UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC2         *((volatile unsigned int*)(0x42CF0968UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC3         *((volatile unsigned int*)(0x42CF096CUL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC4         *((volatile unsigned int*)(0x42CF0970UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_MBC5         *((volatile unsigned int*)(0x42CF0974UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_SA           *((volatile unsigned int*)(0x42CF0978UL))
+#define bFM3_ETHERNET_MAC1_MAR25H_AE           *((volatile unsigned int*)(0x42CF097CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A0           *((volatile unsigned int*)(0x42CF0980UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A1           *((volatile unsigned int*)(0x42CF0984UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A2           *((volatile unsigned int*)(0x42CF0988UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A3           *((volatile unsigned int*)(0x42CF098CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A4           *((volatile unsigned int*)(0x42CF0990UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A5           *((volatile unsigned int*)(0x42CF0994UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A6           *((volatile unsigned int*)(0x42CF0998UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A7           *((volatile unsigned int*)(0x42CF099CUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A8           *((volatile unsigned int*)(0x42CF09A0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A9           *((volatile unsigned int*)(0x42CF09A4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A10          *((volatile unsigned int*)(0x42CF09A8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A11          *((volatile unsigned int*)(0x42CF09ACUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A12          *((volatile unsigned int*)(0x42CF09B0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A13          *((volatile unsigned int*)(0x42CF09B4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A14          *((volatile unsigned int*)(0x42CF09B8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A15          *((volatile unsigned int*)(0x42CF09BCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A16          *((volatile unsigned int*)(0x42CF09C0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A17          *((volatile unsigned int*)(0x42CF09C4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A18          *((volatile unsigned int*)(0x42CF09C8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A19          *((volatile unsigned int*)(0x42CF09CCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A20          *((volatile unsigned int*)(0x42CF09D0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A21          *((volatile unsigned int*)(0x42CF09D4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A22          *((volatile unsigned int*)(0x42CF09D8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A23          *((volatile unsigned int*)(0x42CF09DCUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A24          *((volatile unsigned int*)(0x42CF09E0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A25          *((volatile unsigned int*)(0x42CF09E4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A26          *((volatile unsigned int*)(0x42CF09E8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A27          *((volatile unsigned int*)(0x42CF09ECUL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A28          *((volatile unsigned int*)(0x42CF09F0UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A29          *((volatile unsigned int*)(0x42CF09F4UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A30          *((volatile unsigned int*)(0x42CF09F8UL))
+#define bFM3_ETHERNET_MAC1_MAR25L_A31          *((volatile unsigned int*)(0x42CF09FCUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A32          *((volatile unsigned int*)(0x42CF0A00UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A33          *((volatile unsigned int*)(0x42CF0A04UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A34          *((volatile unsigned int*)(0x42CF0A08UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A35          *((volatile unsigned int*)(0x42CF0A0CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A36          *((volatile unsigned int*)(0x42CF0A10UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A37          *((volatile unsigned int*)(0x42CF0A14UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A38          *((volatile unsigned int*)(0x42CF0A18UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A39          *((volatile unsigned int*)(0x42CF0A1CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A40          *((volatile unsigned int*)(0x42CF0A20UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A41          *((volatile unsigned int*)(0x42CF0A24UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A42          *((volatile unsigned int*)(0x42CF0A28UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A43          *((volatile unsigned int*)(0x42CF0A2CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A44          *((volatile unsigned int*)(0x42CF0A30UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A45          *((volatile unsigned int*)(0x42CF0A34UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A46          *((volatile unsigned int*)(0x42CF0A38UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_A47          *((volatile unsigned int*)(0x42CF0A3CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC0         *((volatile unsigned int*)(0x42CF0A60UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC1         *((volatile unsigned int*)(0x42CF0A64UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC2         *((volatile unsigned int*)(0x42CF0A68UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC3         *((volatile unsigned int*)(0x42CF0A6CUL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC4         *((volatile unsigned int*)(0x42CF0A70UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_MBC5         *((volatile unsigned int*)(0x42CF0A74UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_SA           *((volatile unsigned int*)(0x42CF0A78UL))
+#define bFM3_ETHERNET_MAC1_MAR26H_AE           *((volatile unsigned int*)(0x42CF0A7CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A0           *((volatile unsigned int*)(0x42CF0A80UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A1           *((volatile unsigned int*)(0x42CF0A84UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A2           *((volatile unsigned int*)(0x42CF0A88UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A3           *((volatile unsigned int*)(0x42CF0A8CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A4           *((volatile unsigned int*)(0x42CF0A90UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A5           *((volatile unsigned int*)(0x42CF0A94UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A6           *((volatile unsigned int*)(0x42CF0A98UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A7           *((volatile unsigned int*)(0x42CF0A9CUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A8           *((volatile unsigned int*)(0x42CF0AA0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A9           *((volatile unsigned int*)(0x42CF0AA4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A10          *((volatile unsigned int*)(0x42CF0AA8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A11          *((volatile unsigned int*)(0x42CF0AACUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A12          *((volatile unsigned int*)(0x42CF0AB0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A13          *((volatile unsigned int*)(0x42CF0AB4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A14          *((volatile unsigned int*)(0x42CF0AB8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A15          *((volatile unsigned int*)(0x42CF0ABCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A16          *((volatile unsigned int*)(0x42CF0AC0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A17          *((volatile unsigned int*)(0x42CF0AC4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A18          *((volatile unsigned int*)(0x42CF0AC8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A19          *((volatile unsigned int*)(0x42CF0ACCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A20          *((volatile unsigned int*)(0x42CF0AD0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A21          *((volatile unsigned int*)(0x42CF0AD4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A22          *((volatile unsigned int*)(0x42CF0AD8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A23          *((volatile unsigned int*)(0x42CF0ADCUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A24          *((volatile unsigned int*)(0x42CF0AE0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A25          *((volatile unsigned int*)(0x42CF0AE4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A26          *((volatile unsigned int*)(0x42CF0AE8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A27          *((volatile unsigned int*)(0x42CF0AECUL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A28          *((volatile unsigned int*)(0x42CF0AF0UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A29          *((volatile unsigned int*)(0x42CF0AF4UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A30          *((volatile unsigned int*)(0x42CF0AF8UL))
+#define bFM3_ETHERNET_MAC1_MAR26L_A31          *((volatile unsigned int*)(0x42CF0AFCUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A32          *((volatile unsigned int*)(0x42CF0B00UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A33          *((volatile unsigned int*)(0x42CF0B04UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A34          *((volatile unsigned int*)(0x42CF0B08UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A35          *((volatile unsigned int*)(0x42CF0B0CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A36          *((volatile unsigned int*)(0x42CF0B10UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A37          *((volatile unsigned int*)(0x42CF0B14UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A38          *((volatile unsigned int*)(0x42CF0B18UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A39          *((volatile unsigned int*)(0x42CF0B1CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A40          *((volatile unsigned int*)(0x42CF0B20UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A41          *((volatile unsigned int*)(0x42CF0B24UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A42          *((volatile unsigned int*)(0x42CF0B28UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A43          *((volatile unsigned int*)(0x42CF0B2CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A44          *((volatile unsigned int*)(0x42CF0B30UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A45          *((volatile unsigned int*)(0x42CF0B34UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A46          *((volatile unsigned int*)(0x42CF0B38UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_A47          *((volatile unsigned int*)(0x42CF0B3CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC0         *((volatile unsigned int*)(0x42CF0B60UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC1         *((volatile unsigned int*)(0x42CF0B64UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC2         *((volatile unsigned int*)(0x42CF0B68UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC3         *((volatile unsigned int*)(0x42CF0B6CUL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC4         *((volatile unsigned int*)(0x42CF0B70UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_MBC5         *((volatile unsigned int*)(0x42CF0B74UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_SA           *((volatile unsigned int*)(0x42CF0B78UL))
+#define bFM3_ETHERNET_MAC1_MAR27H_AE           *((volatile unsigned int*)(0x42CF0B7CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A0           *((volatile unsigned int*)(0x42CF0B80UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A1           *((volatile unsigned int*)(0x42CF0B84UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A2           *((volatile unsigned int*)(0x42CF0B88UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A3           *((volatile unsigned int*)(0x42CF0B8CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A4           *((volatile unsigned int*)(0x42CF0B90UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A5           *((volatile unsigned int*)(0x42CF0B94UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A6           *((volatile unsigned int*)(0x42CF0B98UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A7           *((volatile unsigned int*)(0x42CF0B9CUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A8           *((volatile unsigned int*)(0x42CF0BA0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A9           *((volatile unsigned int*)(0x42CF0BA4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A10          *((volatile unsigned int*)(0x42CF0BA8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A11          *((volatile unsigned int*)(0x42CF0BACUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A12          *((volatile unsigned int*)(0x42CF0BB0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A13          *((volatile unsigned int*)(0x42CF0BB4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A14          *((volatile unsigned int*)(0x42CF0BB8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A15          *((volatile unsigned int*)(0x42CF0BBCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A16          *((volatile unsigned int*)(0x42CF0BC0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A17          *((volatile unsigned int*)(0x42CF0BC4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A18          *((volatile unsigned int*)(0x42CF0BC8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A19          *((volatile unsigned int*)(0x42CF0BCCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A20          *((volatile unsigned int*)(0x42CF0BD0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A21          *((volatile unsigned int*)(0x42CF0BD4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A22          *((volatile unsigned int*)(0x42CF0BD8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A23          *((volatile unsigned int*)(0x42CF0BDCUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A24          *((volatile unsigned int*)(0x42CF0BE0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A25          *((volatile unsigned int*)(0x42CF0BE4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A26          *((volatile unsigned int*)(0x42CF0BE8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A27          *((volatile unsigned int*)(0x42CF0BECUL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A28          *((volatile unsigned int*)(0x42CF0BF0UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A29          *((volatile unsigned int*)(0x42CF0BF4UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A30          *((volatile unsigned int*)(0x42CF0BF8UL))
+#define bFM3_ETHERNET_MAC1_MAR27L_A31          *((volatile unsigned int*)(0x42CF0BFCUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A32          *((volatile unsigned int*)(0x42CF0C00UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A33          *((volatile unsigned int*)(0x42CF0C04UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A34          *((volatile unsigned int*)(0x42CF0C08UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A35          *((volatile unsigned int*)(0x42CF0C0CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A36          *((volatile unsigned int*)(0x42CF0C10UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A37          *((volatile unsigned int*)(0x42CF0C14UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A38          *((volatile unsigned int*)(0x42CF0C18UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A39          *((volatile unsigned int*)(0x42CF0C1CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A40          *((volatile unsigned int*)(0x42CF0C20UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A41          *((volatile unsigned int*)(0x42CF0C24UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A42          *((volatile unsigned int*)(0x42CF0C28UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A43          *((volatile unsigned int*)(0x42CF0C2CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A44          *((volatile unsigned int*)(0x42CF0C30UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A45          *((volatile unsigned int*)(0x42CF0C34UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A46          *((volatile unsigned int*)(0x42CF0C38UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_A47          *((volatile unsigned int*)(0x42CF0C3CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC0         *((volatile unsigned int*)(0x42CF0C60UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC1         *((volatile unsigned int*)(0x42CF0C64UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC2         *((volatile unsigned int*)(0x42CF0C68UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC3         *((volatile unsigned int*)(0x42CF0C6CUL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC4         *((volatile unsigned int*)(0x42CF0C70UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_MBC5         *((volatile unsigned int*)(0x42CF0C74UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_SA           *((volatile unsigned int*)(0x42CF0C78UL))
+#define bFM3_ETHERNET_MAC1_MAR28H_AE           *((volatile unsigned int*)(0x42CF0C7CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A0           *((volatile unsigned int*)(0x42CF0C80UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A1           *((volatile unsigned int*)(0x42CF0C84UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A2           *((volatile unsigned int*)(0x42CF0C88UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A3           *((volatile unsigned int*)(0x42CF0C8CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A4           *((volatile unsigned int*)(0x42CF0C90UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A5           *((volatile unsigned int*)(0x42CF0C94UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A6           *((volatile unsigned int*)(0x42CF0C98UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A7           *((volatile unsigned int*)(0x42CF0C9CUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A8           *((volatile unsigned int*)(0x42CF0CA0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A9           *((volatile unsigned int*)(0x42CF0CA4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A10          *((volatile unsigned int*)(0x42CF0CA8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A11          *((volatile unsigned int*)(0x42CF0CACUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A12          *((volatile unsigned int*)(0x42CF0CB0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A13          *((volatile unsigned int*)(0x42CF0CB4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A14          *((volatile unsigned int*)(0x42CF0CB8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A15          *((volatile unsigned int*)(0x42CF0CBCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A16          *((volatile unsigned int*)(0x42CF0CC0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A17          *((volatile unsigned int*)(0x42CF0CC4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A18          *((volatile unsigned int*)(0x42CF0CC8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A19          *((volatile unsigned int*)(0x42CF0CCCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A20          *((volatile unsigned int*)(0x42CF0CD0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A21          *((volatile unsigned int*)(0x42CF0CD4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A22          *((volatile unsigned int*)(0x42CF0CD8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A23          *((volatile unsigned int*)(0x42CF0CDCUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A24          *((volatile unsigned int*)(0x42CF0CE0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A25          *((volatile unsigned int*)(0x42CF0CE4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A26          *((volatile unsigned int*)(0x42CF0CE8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A27          *((volatile unsigned int*)(0x42CF0CECUL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A28          *((volatile unsigned int*)(0x42CF0CF0UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A29          *((volatile unsigned int*)(0x42CF0CF4UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A30          *((volatile unsigned int*)(0x42CF0CF8UL))
+#define bFM3_ETHERNET_MAC1_MAR28L_A31          *((volatile unsigned int*)(0x42CF0CFCUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A32          *((volatile unsigned int*)(0x42CF0D00UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A33          *((volatile unsigned int*)(0x42CF0D04UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A34          *((volatile unsigned int*)(0x42CF0D08UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A35          *((volatile unsigned int*)(0x42CF0D0CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A36          *((volatile unsigned int*)(0x42CF0D10UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A37          *((volatile unsigned int*)(0x42CF0D14UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A38          *((volatile unsigned int*)(0x42CF0D18UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A39          *((volatile unsigned int*)(0x42CF0D1CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A40          *((volatile unsigned int*)(0x42CF0D20UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A41          *((volatile unsigned int*)(0x42CF0D24UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A42          *((volatile unsigned int*)(0x42CF0D28UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A43          *((volatile unsigned int*)(0x42CF0D2CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A44          *((volatile unsigned int*)(0x42CF0D30UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A45          *((volatile unsigned int*)(0x42CF0D34UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A46          *((volatile unsigned int*)(0x42CF0D38UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_A47          *((volatile unsigned int*)(0x42CF0D3CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC0         *((volatile unsigned int*)(0x42CF0D60UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC1         *((volatile unsigned int*)(0x42CF0D64UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC2         *((volatile unsigned int*)(0x42CF0D68UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC3         *((volatile unsigned int*)(0x42CF0D6CUL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC4         *((volatile unsigned int*)(0x42CF0D70UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_MBC5         *((volatile unsigned int*)(0x42CF0D74UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_SA           *((volatile unsigned int*)(0x42CF0D78UL))
+#define bFM3_ETHERNET_MAC1_MAR29H_AE           *((volatile unsigned int*)(0x42CF0D7CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A0           *((volatile unsigned int*)(0x42CF0D80UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A1           *((volatile unsigned int*)(0x42CF0D84UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A2           *((volatile unsigned int*)(0x42CF0D88UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A3           *((volatile unsigned int*)(0x42CF0D8CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A4           *((volatile unsigned int*)(0x42CF0D90UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A5           *((volatile unsigned int*)(0x42CF0D94UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A6           *((volatile unsigned int*)(0x42CF0D98UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A7           *((volatile unsigned int*)(0x42CF0D9CUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A8           *((volatile unsigned int*)(0x42CF0DA0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A9           *((volatile unsigned int*)(0x42CF0DA4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A10          *((volatile unsigned int*)(0x42CF0DA8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A11          *((volatile unsigned int*)(0x42CF0DACUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A12          *((volatile unsigned int*)(0x42CF0DB0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A13          *((volatile unsigned int*)(0x42CF0DB4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A14          *((volatile unsigned int*)(0x42CF0DB8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A15          *((volatile unsigned int*)(0x42CF0DBCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A16          *((volatile unsigned int*)(0x42CF0DC0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A17          *((volatile unsigned int*)(0x42CF0DC4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A18          *((volatile unsigned int*)(0x42CF0DC8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A19          *((volatile unsigned int*)(0x42CF0DCCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A20          *((volatile unsigned int*)(0x42CF0DD0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A21          *((volatile unsigned int*)(0x42CF0DD4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A22          *((volatile unsigned int*)(0x42CF0DD8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A23          *((volatile unsigned int*)(0x42CF0DDCUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A24          *((volatile unsigned int*)(0x42CF0DE0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A25          *((volatile unsigned int*)(0x42CF0DE4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A26          *((volatile unsigned int*)(0x42CF0DE8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A27          *((volatile unsigned int*)(0x42CF0DECUL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A28          *((volatile unsigned int*)(0x42CF0DF0UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A29          *((volatile unsigned int*)(0x42CF0DF4UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A30          *((volatile unsigned int*)(0x42CF0DF8UL))
+#define bFM3_ETHERNET_MAC1_MAR29L_A31          *((volatile unsigned int*)(0x42CF0DFCUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A32          *((volatile unsigned int*)(0x42CF0E00UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A33          *((volatile unsigned int*)(0x42CF0E04UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A34          *((volatile unsigned int*)(0x42CF0E08UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A35          *((volatile unsigned int*)(0x42CF0E0CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A36          *((volatile unsigned int*)(0x42CF0E10UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A37          *((volatile unsigned int*)(0x42CF0E14UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A38          *((volatile unsigned int*)(0x42CF0E18UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A39          *((volatile unsigned int*)(0x42CF0E1CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A40          *((volatile unsigned int*)(0x42CF0E20UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A41          *((volatile unsigned int*)(0x42CF0E24UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A42          *((volatile unsigned int*)(0x42CF0E28UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A43          *((volatile unsigned int*)(0x42CF0E2CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A44          *((volatile unsigned int*)(0x42CF0E30UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A45          *((volatile unsigned int*)(0x42CF0E34UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A46          *((volatile unsigned int*)(0x42CF0E38UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_A47          *((volatile unsigned int*)(0x42CF0E3CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC0         *((volatile unsigned int*)(0x42CF0E60UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC1         *((volatile unsigned int*)(0x42CF0E64UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC2         *((volatile unsigned int*)(0x42CF0E68UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC3         *((volatile unsigned int*)(0x42CF0E6CUL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC4         *((volatile unsigned int*)(0x42CF0E70UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_MBC5         *((volatile unsigned int*)(0x42CF0E74UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_SA           *((volatile unsigned int*)(0x42CF0E78UL))
+#define bFM3_ETHERNET_MAC1_MAR30H_AE           *((volatile unsigned int*)(0x42CF0E7CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A0           *((volatile unsigned int*)(0x42CF0E80UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A1           *((volatile unsigned int*)(0x42CF0E84UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A2           *((volatile unsigned int*)(0x42CF0E88UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A3           *((volatile unsigned int*)(0x42CF0E8CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A4           *((volatile unsigned int*)(0x42CF0E90UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A5           *((volatile unsigned int*)(0x42CF0E94UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A6           *((volatile unsigned int*)(0x42CF0E98UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A7           *((volatile unsigned int*)(0x42CF0E9CUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A8           *((volatile unsigned int*)(0x42CF0EA0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A9           *((volatile unsigned int*)(0x42CF0EA4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A10          *((volatile unsigned int*)(0x42CF0EA8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A11          *((volatile unsigned int*)(0x42CF0EACUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A12          *((volatile unsigned int*)(0x42CF0EB0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A13          *((volatile unsigned int*)(0x42CF0EB4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A14          *((volatile unsigned int*)(0x42CF0EB8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A15          *((volatile unsigned int*)(0x42CF0EBCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A16          *((volatile unsigned int*)(0x42CF0EC0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A17          *((volatile unsigned int*)(0x42CF0EC4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A18          *((volatile unsigned int*)(0x42CF0EC8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A19          *((volatile unsigned int*)(0x42CF0ECCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A20          *((volatile unsigned int*)(0x42CF0ED0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A21          *((volatile unsigned int*)(0x42CF0ED4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A22          *((volatile unsigned int*)(0x42CF0ED8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A23          *((volatile unsigned int*)(0x42CF0EDCUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A24          *((volatile unsigned int*)(0x42CF0EE0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A25          *((volatile unsigned int*)(0x42CF0EE4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A26          *((volatile unsigned int*)(0x42CF0EE8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A27          *((volatile unsigned int*)(0x42CF0EECUL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A28          *((volatile unsigned int*)(0x42CF0EF0UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A29          *((volatile unsigned int*)(0x42CF0EF4UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A30          *((volatile unsigned int*)(0x42CF0EF8UL))
+#define bFM3_ETHERNET_MAC1_MAR30L_A31          *((volatile unsigned int*)(0x42CF0EFCUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A32          *((volatile unsigned int*)(0x42CF0F00UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A33          *((volatile unsigned int*)(0x42CF0F04UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A34          *((volatile unsigned int*)(0x42CF0F08UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A35          *((volatile unsigned int*)(0x42CF0F0CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A36          *((volatile unsigned int*)(0x42CF0F10UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A37          *((volatile unsigned int*)(0x42CF0F14UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A38          *((volatile unsigned int*)(0x42CF0F18UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A39          *((volatile unsigned int*)(0x42CF0F1CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A40          *((volatile unsigned int*)(0x42CF0F20UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A41          *((volatile unsigned int*)(0x42CF0F24UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A42          *((volatile unsigned int*)(0x42CF0F28UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A43          *((volatile unsigned int*)(0x42CF0F2CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A44          *((volatile unsigned int*)(0x42CF0F30UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A45          *((volatile unsigned int*)(0x42CF0F34UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A46          *((volatile unsigned int*)(0x42CF0F38UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_A47          *((volatile unsigned int*)(0x42CF0F3CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC0         *((volatile unsigned int*)(0x42CF0F60UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC1         *((volatile unsigned int*)(0x42CF0F64UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC2         *((volatile unsigned int*)(0x42CF0F68UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC3         *((volatile unsigned int*)(0x42CF0F6CUL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC4         *((volatile unsigned int*)(0x42CF0F70UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_MBC5         *((volatile unsigned int*)(0x42CF0F74UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_SA           *((volatile unsigned int*)(0x42CF0F78UL))
+#define bFM3_ETHERNET_MAC1_MAR31H_AE           *((volatile unsigned int*)(0x42CF0F7CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A0           *((volatile unsigned int*)(0x42CF0F80UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A1           *((volatile unsigned int*)(0x42CF0F84UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A2           *((volatile unsigned int*)(0x42CF0F88UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A3           *((volatile unsigned int*)(0x42CF0F8CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A4           *((volatile unsigned int*)(0x42CF0F90UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A5           *((volatile unsigned int*)(0x42CF0F94UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A6           *((volatile unsigned int*)(0x42CF0F98UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A7           *((volatile unsigned int*)(0x42CF0F9CUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A8           *((volatile unsigned int*)(0x42CF0FA0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A9           *((volatile unsigned int*)(0x42CF0FA4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A10          *((volatile unsigned int*)(0x42CF0FA8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A11          *((volatile unsigned int*)(0x42CF0FACUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A12          *((volatile unsigned int*)(0x42CF0FB0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A13          *((volatile unsigned int*)(0x42CF0FB4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A14          *((volatile unsigned int*)(0x42CF0FB8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A15          *((volatile unsigned int*)(0x42CF0FBCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A16          *((volatile unsigned int*)(0x42CF0FC0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A17          *((volatile unsigned int*)(0x42CF0FC4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A18          *((volatile unsigned int*)(0x42CF0FC8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A19          *((volatile unsigned int*)(0x42CF0FCCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A20          *((volatile unsigned int*)(0x42CF0FD0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A21          *((volatile unsigned int*)(0x42CF0FD4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A22          *((volatile unsigned int*)(0x42CF0FD8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A23          *((volatile unsigned int*)(0x42CF0FDCUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A24          *((volatile unsigned int*)(0x42CF0FE0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A25          *((volatile unsigned int*)(0x42CF0FE4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A26          *((volatile unsigned int*)(0x42CF0FE8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A27          *((volatile unsigned int*)(0x42CF0FECUL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A28          *((volatile unsigned int*)(0x42CF0FF0UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A29          *((volatile unsigned int*)(0x42CF0FF4UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A30          *((volatile unsigned int*)(0x42CF0FF8UL))
+#define bFM3_ETHERNET_MAC1_MAR31L_A31          *((volatile unsigned int*)(0x42CF0FFCUL))
+#define bFM3_ETHERNET_MAC1_BMR_SWR             *((volatile unsigned int*)(0x42D00000UL))
+#define bFM3_ETHERNET_MAC1_BMR_DA              *((volatile unsigned int*)(0x42D00004UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL0            *((volatile unsigned int*)(0x42D00008UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL1            *((volatile unsigned int*)(0x42D0000CUL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL2            *((volatile unsigned int*)(0x42D00010UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL3            *((volatile unsigned int*)(0x42D00014UL))
+#define bFM3_ETHERNET_MAC1_BMR_DSL4            *((volatile unsigned int*)(0x42D00018UL))
+#define bFM3_ETHERNET_MAC1_BMR_ATDS            *((volatile unsigned int*)(0x42D0001CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL0            *((volatile unsigned int*)(0x42D00020UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL1            *((volatile unsigned int*)(0x42D00024UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL2            *((volatile unsigned int*)(0x42D00028UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL3            *((volatile unsigned int*)(0x42D0002CUL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL4            *((volatile unsigned int*)(0x42D00030UL))
+#define bFM3_ETHERNET_MAC1_BMR_PBL5            *((volatile unsigned int*)(0x42D00034UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR0             *((volatile unsigned int*)(0x42D00038UL))
+#define bFM3_ETHERNET_MAC1_BMR_PR1             *((volatile unsigned int*)(0x42D0003CUL))
+#define bFM3_ETHERNET_MAC1_BMR_FB              *((volatile unsigned int*)(0x42D00040UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL0           *((volatile unsigned int*)(0x42D00044UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL1           *((volatile unsigned int*)(0x42D00048UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL2           *((volatile unsigned int*)(0x42D0004CUL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL3           *((volatile unsigned int*)(0x42D00050UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL4           *((volatile unsigned int*)(0x42D00054UL))
+#define bFM3_ETHERNET_MAC1_BMR_RPBL5           *((volatile unsigned int*)(0x42D00058UL))
+#define bFM3_ETHERNET_MAC1_BMR_USP             *((volatile unsigned int*)(0x42D0005CUL))
+#define bFM3_ETHERNET_MAC1_BMR_8XPBL           *((volatile unsigned int*)(0x42D00060UL))
+#define bFM3_ETHERNET_MAC1_BMR_AAL             *((volatile unsigned int*)(0x42D00064UL))
+#define bFM3_ETHERNET_MAC1_BMR_MB              *((volatile unsigned int*)(0x42D00068UL))
+#define bFM3_ETHERNET_MAC1_BMR_TXPR            *((volatile unsigned int*)(0x42D0006CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD0           *((volatile unsigned int*)(0x42D00080UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD1           *((volatile unsigned int*)(0x42D00084UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD2           *((volatile unsigned int*)(0x42D00088UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD3           *((volatile unsigned int*)(0x42D0008CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD4           *((volatile unsigned int*)(0x42D00090UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD5           *((volatile unsigned int*)(0x42D00094UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD6           *((volatile unsigned int*)(0x42D00098UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD7           *((volatile unsigned int*)(0x42D0009CUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD8           *((volatile unsigned int*)(0x42D000A0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD9           *((volatile unsigned int*)(0x42D000A4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD10          *((volatile unsigned int*)(0x42D000A8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD11          *((volatile unsigned int*)(0x42D000ACUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD12          *((volatile unsigned int*)(0x42D000B0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD13          *((volatile unsigned int*)(0x42D000B4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD14          *((volatile unsigned int*)(0x42D000B8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD15          *((volatile unsigned int*)(0x42D000BCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD16          *((volatile unsigned int*)(0x42D000C0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD17          *((volatile unsigned int*)(0x42D000C4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD18          *((volatile unsigned int*)(0x42D000C8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD19          *((volatile unsigned int*)(0x42D000CCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD20          *((volatile unsigned int*)(0x42D000D0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD21          *((volatile unsigned int*)(0x42D000D4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD22          *((volatile unsigned int*)(0x42D000D8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD23          *((volatile unsigned int*)(0x42D000DCUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD24          *((volatile unsigned int*)(0x42D000E0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD25          *((volatile unsigned int*)(0x42D000E4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD26          *((volatile unsigned int*)(0x42D000E8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD27          *((volatile unsigned int*)(0x42D000ECUL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD28          *((volatile unsigned int*)(0x42D000F0UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD29          *((volatile unsigned int*)(0x42D000F4UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD30          *((volatile unsigned int*)(0x42D000F8UL))
+#define bFM3_ETHERNET_MAC1_TPDR_TPD31          *((volatile unsigned int*)(0x42D000FCUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD0           *((volatile unsigned int*)(0x42D00100UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD1           *((volatile unsigned int*)(0x42D00104UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD2           *((volatile unsigned int*)(0x42D00108UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD3           *((volatile unsigned int*)(0x42D0010CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD4           *((volatile unsigned int*)(0x42D00110UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD5           *((volatile unsigned int*)(0x42D00114UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD6           *((volatile unsigned int*)(0x42D00118UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD7           *((volatile unsigned int*)(0x42D0011CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD8           *((volatile unsigned int*)(0x42D00120UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD9           *((volatile unsigned int*)(0x42D00124UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD10          *((volatile unsigned int*)(0x42D00128UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD11          *((volatile unsigned int*)(0x42D0012CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD12          *((volatile unsigned int*)(0x42D00130UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD13          *((volatile unsigned int*)(0x42D00134UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD14          *((volatile unsigned int*)(0x42D00138UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD15          *((volatile unsigned int*)(0x42D0013CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD16          *((volatile unsigned int*)(0x42D00140UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD17          *((volatile unsigned int*)(0x42D00144UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD18          *((volatile unsigned int*)(0x42D00148UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD19          *((volatile unsigned int*)(0x42D0014CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD20          *((volatile unsigned int*)(0x42D00150UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD21          *((volatile unsigned int*)(0x42D00154UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD22          *((volatile unsigned int*)(0x42D00158UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD23          *((volatile unsigned int*)(0x42D0015CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD24          *((volatile unsigned int*)(0x42D00160UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD25          *((volatile unsigned int*)(0x42D00164UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD26          *((volatile unsigned int*)(0x42D00168UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD27          *((volatile unsigned int*)(0x42D0016CUL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD28          *((volatile unsigned int*)(0x42D00170UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD29          *((volatile unsigned int*)(0x42D00174UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD30          *((volatile unsigned int*)(0x42D00178UL))
+#define bFM3_ETHERNET_MAC1_RPDR_RPD31          *((volatile unsigned int*)(0x42D0017CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL2          *((volatile unsigned int*)(0x42D00188UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL3          *((volatile unsigned int*)(0x42D0018CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL4          *((volatile unsigned int*)(0x42D00190UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL5          *((volatile unsigned int*)(0x42D00194UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL6          *((volatile unsigned int*)(0x42D00198UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL7          *((volatile unsigned int*)(0x42D0019CUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL8          *((volatile unsigned int*)(0x42D001A0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL9          *((volatile unsigned int*)(0x42D001A4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL10         *((volatile unsigned int*)(0x42D001A8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL11         *((volatile unsigned int*)(0x42D001ACUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL12         *((volatile unsigned int*)(0x42D001B0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL13         *((volatile unsigned int*)(0x42D001B4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL14         *((volatile unsigned int*)(0x42D001B8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL15         *((volatile unsigned int*)(0x42D001BCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL16         *((volatile unsigned int*)(0x42D001C0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL17         *((volatile unsigned int*)(0x42D001C4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL18         *((volatile unsigned int*)(0x42D001C8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL19         *((volatile unsigned int*)(0x42D001CCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL20         *((volatile unsigned int*)(0x42D001D0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL21         *((volatile unsigned int*)(0x42D001D4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL22         *((volatile unsigned int*)(0x42D001D8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL23         *((volatile unsigned int*)(0x42D001DCUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL24         *((volatile unsigned int*)(0x42D001E0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL25         *((volatile unsigned int*)(0x42D001E4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL26         *((volatile unsigned int*)(0x42D001E8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL27         *((volatile unsigned int*)(0x42D001ECUL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL28         *((volatile unsigned int*)(0x42D001F0UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL29         *((volatile unsigned int*)(0x42D001F4UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL30         *((volatile unsigned int*)(0x42D001F8UL))
+#define bFM3_ETHERNET_MAC1_RDLAR_SRL31         *((volatile unsigned int*)(0x42D001FCUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL2          *((volatile unsigned int*)(0x42D00208UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL3          *((volatile unsigned int*)(0x42D0020CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL4          *((volatile unsigned int*)(0x42D00210UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL5          *((volatile unsigned int*)(0x42D00214UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL6          *((volatile unsigned int*)(0x42D00218UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL7          *((volatile unsigned int*)(0x42D0021CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL8          *((volatile unsigned int*)(0x42D00220UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL9          *((volatile unsigned int*)(0x42D00224UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL10         *((volatile unsigned int*)(0x42D00228UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL11         *((volatile unsigned int*)(0x42D0022CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL12         *((volatile unsigned int*)(0x42D00230UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL13         *((volatile unsigned int*)(0x42D00234UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL14         *((volatile unsigned int*)(0x42D00238UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL15         *((volatile unsigned int*)(0x42D0023CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL16         *((volatile unsigned int*)(0x42D00240UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL17         *((volatile unsigned int*)(0x42D00244UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL18         *((volatile unsigned int*)(0x42D00248UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL19         *((volatile unsigned int*)(0x42D0024CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL20         *((volatile unsigned int*)(0x42D00250UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL21         *((volatile unsigned int*)(0x42D00254UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL22         *((volatile unsigned int*)(0x42D00258UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL23         *((volatile unsigned int*)(0x42D0025CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL24         *((volatile unsigned int*)(0x42D00260UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL25         *((volatile unsigned int*)(0x42D00264UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL26         *((volatile unsigned int*)(0x42D00268UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL27         *((volatile unsigned int*)(0x42D0026CUL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL28         *((volatile unsigned int*)(0x42D00270UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL29         *((volatile unsigned int*)(0x42D00274UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL30         *((volatile unsigned int*)(0x42D00278UL))
+#define bFM3_ETHERNET_MAC1_TDLAR_STL31         *((volatile unsigned int*)(0x42D0027CUL))
+#define bFM3_ETHERNET_MAC1_SR_TI               *((volatile unsigned int*)(0x42D00280UL))
+#define bFM3_ETHERNET_MAC1_SR_TPS              *((volatile unsigned int*)(0x42D00284UL))
+#define bFM3_ETHERNET_MAC1_SR_TU               *((volatile unsigned int*)(0x42D00288UL))
+#define bFM3_ETHERNET_MAC1_SR_TJT              *((volatile unsigned int*)(0x42D0028CUL))
+#define bFM3_ETHERNET_MAC1_SR_OVF              *((volatile unsigned int*)(0x42D00290UL))
+#define bFM3_ETHERNET_MAC1_SR_UNF              *((volatile unsigned int*)(0x42D00294UL))
+#define bFM3_ETHERNET_MAC1_SR_RI               *((volatile unsigned int*)(0x42D00298UL))
+#define bFM3_ETHERNET_MAC1_SR_RU               *((volatile unsigned int*)(0x42D0029CUL))
+#define bFM3_ETHERNET_MAC1_SR_RPS              *((volatile unsigned int*)(0x42D002A0UL))
+#define bFM3_ETHERNET_MAC1_SR_RWT              *((volatile unsigned int*)(0x42D002A4UL))
+#define bFM3_ETHERNET_MAC1_SR_ETI              *((volatile unsigned int*)(0x42D002A8UL))
+#define bFM3_ETHERNET_MAC1_SR_FBI              *((volatile unsigned int*)(0x42D002B4UL))
+#define bFM3_ETHERNET_MAC1_SR_ERI              *((volatile unsigned int*)(0x42D002B8UL))
+#define bFM3_ETHERNET_MAC1_SR_AIS              *((volatile unsigned int*)(0x42D002BCUL))
+#define bFM3_ETHERNET_MAC1_SR_NIS              *((volatile unsigned int*)(0x42D002C0UL))
+#define bFM3_ETHERNET_MAC1_SR_RS0              *((volatile unsigned int*)(0x42D002C4UL))
+#define bFM3_ETHERNET_MAC1_SR_RS1              *((volatile unsigned int*)(0x42D002C8UL))
+#define bFM3_ETHERNET_MAC1_SR_RS2              *((volatile unsigned int*)(0x42D002CCUL))
+#define bFM3_ETHERNET_MAC1_SR_TS0              *((volatile unsigned int*)(0x42D002D0UL))
+#define bFM3_ETHERNET_MAC1_SR_TS1              *((volatile unsigned int*)(0x42D002D4UL))
+#define bFM3_ETHERNET_MAC1_SR_TS2              *((volatile unsigned int*)(0x42D002D8UL))
+#define bFM3_ETHERNET_MAC1_SR_EB0              *((volatile unsigned int*)(0x42D002DCUL))
+#define bFM3_ETHERNET_MAC1_SR_EB1              *((volatile unsigned int*)(0x42D002E0UL))
+#define bFM3_ETHERNET_MAC1_SR_EB2              *((volatile unsigned int*)(0x42D002E4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLI              *((volatile unsigned int*)(0x42D002E8UL))
+#define bFM3_ETHERNET_MAC1_SR_GMI              *((volatile unsigned int*)(0x42D002ECUL))
+#define bFM3_ETHERNET_MAC1_SR_GPI              *((volatile unsigned int*)(0x42D002F0UL))
+#define bFM3_ETHERNET_MAC1_SR_TTI              *((volatile unsigned int*)(0x42D002F4UL))
+#define bFM3_ETHERNET_MAC1_SR_GLPII            *((volatile unsigned int*)(0x42D002F8UL))
+#define bFM3_ETHERNET_MAC1_OMR_SR              *((volatile unsigned int*)(0x42D00304UL))
+#define bFM3_ETHERNET_MAC1_OMR_OSF             *((volatile unsigned int*)(0x42D00308UL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC0            *((volatile unsigned int*)(0x42D0030CUL))
+#define bFM3_ETHERNET_MAC1_OMR_RTC1            *((volatile unsigned int*)(0x42D00310UL))
+#define bFM3_ETHERNET_MAC1_OMR_FUF             *((volatile unsigned int*)(0x42D00318UL))
+#define bFM3_ETHERNET_MAC1_OMR_FEF             *((volatile unsigned int*)(0x42D0031CUL))
+#define bFM3_ETHERNET_MAC1_OMR_ST              *((volatile unsigned int*)(0x42D00334UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC0            *((volatile unsigned int*)(0x42D00338UL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC1            *((volatile unsigned int*)(0x42D0033CUL))
+#define bFM3_ETHERNET_MAC1_OMR_TTC2            *((volatile unsigned int*)(0x42D00340UL))
+#define bFM3_ETHERNET_MAC1_OMR_FTF             *((volatile unsigned int*)(0x42D00350UL))
+#define bFM3_ETHERNET_MAC1_OMR_TSF             *((volatile unsigned int*)(0x42D00354UL))
+#define bFM3_ETHERNET_MAC1_OMR_DFF             *((volatile unsigned int*)(0x42D00360UL))
+#define bFM3_ETHERNET_MAC1_OMR_RSF             *((volatile unsigned int*)(0x42D00364UL))
+#define bFM3_ETHERNET_MAC1_OMR_DT              *((volatile unsigned int*)(0x42D00368UL))
+#define bFM3_ETHERNET_MAC1_IER_TIE             *((volatile unsigned int*)(0x42D00380UL))
+#define bFM3_ETHERNET_MAC1_IER_TSE             *((volatile unsigned int*)(0x42D00384UL))
+#define bFM3_ETHERNET_MAC1_IER_TUE             *((volatile unsigned int*)(0x42D00388UL))
+#define bFM3_ETHERNET_MAC1_IER_TJE             *((volatile unsigned int*)(0x42D0038CUL))
+#define bFM3_ETHERNET_MAC1_IER_OVE             *((volatile unsigned int*)(0x42D00390UL))
+#define bFM3_ETHERNET_MAC1_IER_UNE             *((volatile unsigned int*)(0x42D00394UL))
+#define bFM3_ETHERNET_MAC1_IER_RIE             *((volatile unsigned int*)(0x42D00398UL))
+#define bFM3_ETHERNET_MAC1_IER_RUE             *((volatile unsigned int*)(0x42D0039CUL))
+#define bFM3_ETHERNET_MAC1_IER_RSE             *((volatile unsigned int*)(0x42D003A0UL))
+#define bFM3_ETHERNET_MAC1_IER_RWE             *((volatile unsigned int*)(0x42D003A4UL))
+#define bFM3_ETHERNET_MAC1_IER_ETE             *((volatile unsigned int*)(0x42D003A8UL))
+#define bFM3_ETHERNET_MAC1_IER_FBE             *((volatile unsigned int*)(0x42D003B4UL))
+#define bFM3_ETHERNET_MAC1_IER_ERE             *((volatile unsigned int*)(0x42D003B8UL))
+#define bFM3_ETHERNET_MAC1_IER_AIE             *((volatile unsigned int*)(0x42D003BCUL))
+#define bFM3_ETHERNET_MAC1_IER_NIE             *((volatile unsigned int*)(0x42D003C0UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH0        *((volatile unsigned int*)(0x42D00400UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH1        *((volatile unsigned int*)(0x42D00404UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH2        *((volatile unsigned int*)(0x42D00408UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH3        *((volatile unsigned int*)(0x42D0040CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH4        *((volatile unsigned int*)(0x42D00410UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH5        *((volatile unsigned int*)(0x42D00414UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH6        *((volatile unsigned int*)(0x42D00418UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH7        *((volatile unsigned int*)(0x42D0041CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH8        *((volatile unsigned int*)(0x42D00420UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH9        *((volatile unsigned int*)(0x42D00424UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH10       *((volatile unsigned int*)(0x42D00428UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH11       *((volatile unsigned int*)(0x42D0042CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH12       *((volatile unsigned int*)(0x42D00430UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH13       *((volatile unsigned int*)(0x42D00434UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH14       *((volatile unsigned int*)(0x42D00438UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFH15       *((volatile unsigned int*)(0x42D0043CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFH        *((volatile unsigned int*)(0x42D00440UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF0        *((volatile unsigned int*)(0x42D00444UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF1        *((volatile unsigned int*)(0x42D00448UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF2        *((volatile unsigned int*)(0x42D0044CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF3        *((volatile unsigned int*)(0x42D00450UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF4        *((volatile unsigned int*)(0x42D00454UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF5        *((volatile unsigned int*)(0x42D00458UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF6        *((volatile unsigned int*)(0x42D0045CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF7        *((volatile unsigned int*)(0x42D00460UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF8        *((volatile unsigned int*)(0x42D00464UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF9        *((volatile unsigned int*)(0x42D00468UL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_NMFF10       *((volatile unsigned int*)(0x42D0046CUL))
+#define bFM3_ETHERNET_MAC1_MFBOCR_ONMFF        *((volatile unsigned int*)(0x42D00470UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT0         *((volatile unsigned int*)(0x42D00480UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT1         *((volatile unsigned int*)(0x42D00484UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT2         *((volatile unsigned int*)(0x42D00488UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT3         *((volatile unsigned int*)(0x42D0048CUL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT4         *((volatile unsigned int*)(0x42D00490UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT5         *((volatile unsigned int*)(0x42D00494UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT6         *((volatile unsigned int*)(0x42D00498UL))
+#define bFM3_ETHERNET_MAC1_RIWTR_RIWT7         *((volatile unsigned int*)(0x42D0049CUL))
+#define bFM3_ETHERNET_MAC1_AHBSR_AHBS          *((volatile unsigned int*)(0x42D00580UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP0        *((volatile unsigned int*)(0x42D00900UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP1        *((volatile unsigned int*)(0x42D00904UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP2        *((volatile unsigned int*)(0x42D00908UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP3        *((volatile unsigned int*)(0x42D0090CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP4        *((volatile unsigned int*)(0x42D00910UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP5        *((volatile unsigned int*)(0x42D00914UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP6        *((volatile unsigned int*)(0x42D00918UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP7        *((volatile unsigned int*)(0x42D0091CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP8        *((volatile unsigned int*)(0x42D00920UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP9        *((volatile unsigned int*)(0x42D00924UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP10       *((volatile unsigned int*)(0x42D00928UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP11       *((volatile unsigned int*)(0x42D0092CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP12       *((volatile unsigned int*)(0x42D00930UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP13       *((volatile unsigned int*)(0x42D00934UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP14       *((volatile unsigned int*)(0x42D00938UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP15       *((volatile unsigned int*)(0x42D0093CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP16       *((volatile unsigned int*)(0x42D00940UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP17       *((volatile unsigned int*)(0x42D00944UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP18       *((volatile unsigned int*)(0x42D00948UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP19       *((volatile unsigned int*)(0x42D0094CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP20       *((volatile unsigned int*)(0x42D00950UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP21       *((volatile unsigned int*)(0x42D00954UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP22       *((volatile unsigned int*)(0x42D00958UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP23       *((volatile unsigned int*)(0x42D0095CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP24       *((volatile unsigned int*)(0x42D00960UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP25       *((volatile unsigned int*)(0x42D00964UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP26       *((volatile unsigned int*)(0x42D00968UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP27       *((volatile unsigned int*)(0x42D0096CUL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP28       *((volatile unsigned int*)(0x42D00970UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP29       *((volatile unsigned int*)(0x42D00974UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP30       *((volatile unsigned int*)(0x42D00978UL))
+#define bFM3_ETHERNET_MAC1_CHTDR_HTDAP31       *((volatile unsigned int*)(0x42D0097CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP0        *((volatile unsigned int*)(0x42D00980UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP1        *((volatile unsigned int*)(0x42D00984UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP2        *((volatile unsigned int*)(0x42D00988UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP3        *((volatile unsigned int*)(0x42D0098CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP4        *((volatile unsigned int*)(0x42D00990UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP5        *((volatile unsigned int*)(0x42D00994UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP6        *((volatile unsigned int*)(0x42D00998UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP7        *((volatile unsigned int*)(0x42D0099CUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP8        *((volatile unsigned int*)(0x42D009A0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP9        *((volatile unsigned int*)(0x42D009A4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP10       *((volatile unsigned int*)(0x42D009A8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP11       *((volatile unsigned int*)(0x42D009ACUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP12       *((volatile unsigned int*)(0x42D009B0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP13       *((volatile unsigned int*)(0x42D009B4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP14       *((volatile unsigned int*)(0x42D009B8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP15       *((volatile unsigned int*)(0x42D009BCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP16       *((volatile unsigned int*)(0x42D009C0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP17       *((volatile unsigned int*)(0x42D009C4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP18       *((volatile unsigned int*)(0x42D009C8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP19       *((volatile unsigned int*)(0x42D009CCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP20       *((volatile unsigned int*)(0x42D009D0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP21       *((volatile unsigned int*)(0x42D009D4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP22       *((volatile unsigned int*)(0x42D009D8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP23       *((volatile unsigned int*)(0x42D009DCUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP24       *((volatile unsigned int*)(0x42D009E0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP25       *((volatile unsigned int*)(0x42D009E4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP26       *((volatile unsigned int*)(0x42D009E8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP27       *((volatile unsigned int*)(0x42D009ECUL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP28       *((volatile unsigned int*)(0x42D009F0UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP29       *((volatile unsigned int*)(0x42D009F4UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP30       *((volatile unsigned int*)(0x42D009F8UL))
+#define bFM3_ETHERNET_MAC1_CHRDR_HRDAP31       *((volatile unsigned int*)(0x42D009FCUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR0       *((volatile unsigned int*)(0x42D00A00UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR1       *((volatile unsigned int*)(0x42D00A04UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR2       *((volatile unsigned int*)(0x42D00A08UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR3       *((volatile unsigned int*)(0x42D00A0CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR4       *((volatile unsigned int*)(0x42D00A10UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR5       *((volatile unsigned int*)(0x42D00A14UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR6       *((volatile unsigned int*)(0x42D00A18UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR7       *((volatile unsigned int*)(0x42D00A1CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR8       *((volatile unsigned int*)(0x42D00A20UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR9       *((volatile unsigned int*)(0x42D00A24UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR10      *((volatile unsigned int*)(0x42D00A28UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR11      *((volatile unsigned int*)(0x42D00A2CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR12      *((volatile unsigned int*)(0x42D00A30UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR13      *((volatile unsigned int*)(0x42D00A34UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR14      *((volatile unsigned int*)(0x42D00A38UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR15      *((volatile unsigned int*)(0x42D00A3CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR16      *((volatile unsigned int*)(0x42D00A40UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR17      *((volatile unsigned int*)(0x42D00A44UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR18      *((volatile unsigned int*)(0x42D00A48UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR19      *((volatile unsigned int*)(0x42D00A4CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR20      *((volatile unsigned int*)(0x42D00A50UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR21      *((volatile unsigned int*)(0x42D00A54UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR22      *((volatile unsigned int*)(0x42D00A58UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR23      *((volatile unsigned int*)(0x42D00A5CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR24      *((volatile unsigned int*)(0x42D00A60UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR25      *((volatile unsigned int*)(0x42D00A64UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR26      *((volatile unsigned int*)(0x42D00A68UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR27      *((volatile unsigned int*)(0x42D00A6CUL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR28      *((volatile unsigned int*)(0x42D00A70UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR29      *((volatile unsigned int*)(0x42D00A74UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR30      *((volatile unsigned int*)(0x42D00A78UL))
+#define bFM3_ETHERNET_MAC1_CHTBAR_HTBAR31      *((volatile unsigned int*)(0x42D00A7CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR0       *((volatile unsigned int*)(0x42D00A80UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR1       *((volatile unsigned int*)(0x42D00A84UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR2       *((volatile unsigned int*)(0x42D00A88UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR3       *((volatile unsigned int*)(0x42D00A8CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR4       *((volatile unsigned int*)(0x42D00A90UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR5       *((volatile unsigned int*)(0x42D00A94UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR6       *((volatile unsigned int*)(0x42D00A98UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR7       *((volatile unsigned int*)(0x42D00A9CUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR8       *((volatile unsigned int*)(0x42D00AA0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR9       *((volatile unsigned int*)(0x42D00AA4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR10      *((volatile unsigned int*)(0x42D00AA8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR11      *((volatile unsigned int*)(0x42D00AACUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR12      *((volatile unsigned int*)(0x42D00AB0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR13      *((volatile unsigned int*)(0x42D00AB4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR14      *((volatile unsigned int*)(0x42D00AB8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR15      *((volatile unsigned int*)(0x42D00ABCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR16      *((volatile unsigned int*)(0x42D00AC0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR17      *((volatile unsigned int*)(0x42D00AC4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR18      *((volatile unsigned int*)(0x42D00AC8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR19      *((volatile unsigned int*)(0x42D00ACCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR20      *((volatile unsigned int*)(0x42D00AD0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR21      *((volatile unsigned int*)(0x42D00AD4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR22      *((volatile unsigned int*)(0x42D00AD8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR23      *((volatile unsigned int*)(0x42D00ADCUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR24      *((volatile unsigned int*)(0x42D00AE0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR25      *((volatile unsigned int*)(0x42D00AE4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR26      *((volatile unsigned int*)(0x42D00AE8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR27      *((volatile unsigned int*)(0x42D00AECUL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR28      *((volatile unsigned int*)(0x42D00AF0UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR29      *((volatile unsigned int*)(0x42D00AF4UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR30      *((volatile unsigned int*)(0x42D00AF8UL))
+#define bFM3_ETHERNET_MAC1_CHRBAR_HRBAR31      *((volatile unsigned int*)(0x42D00AFCUL))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MB9B610T_H_ */
+

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S

@@ -0,0 +1,333 @@
+;/************************************************************************/
+;/*               (C) Fujitsu Semiconductor Europe GmbH                  */
+;/*                                                                      */
+;/* The following software deliverable is intended for and must only be  */
+;/* used for reference and in an evaluation laboratory environment.      */
+;/* It is provided on an as-is basis without charge and is subject to    */
+;/* alterations.                                                         */
+;/* It is the user’s obligation to fully test the software in its        */
+;/* environment and to ensure proper functionality, qualification and    */
+;/* compliance with component specifications.                            */
+;/*                                                                      */
+;/* In the event the software deliverable includes the use of open       */
+;/* source components, the provisions of the governing open source       */
+;/* license agreement shall apply with respect to such software          */
+;/* deliverable.                                                         */
+;/* FSEU does not warrant that the deliverables do not infringe any      */
+;/* third party intellectual property right (IPR). In the event that     */
+;/* the deliverables infringe a third party IPR it is the sole           */
+;/* responsibility of the customer to obtain necessary licenses to       */
+;/* continue the usage of the deliverable.                               */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not       */
+;/* limited to, warranties of merchantability and fitness for a          */
+;/* particular purpose for which the deliverable is not designated.      */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */
+;/* is restricted to intention and gross negligence.                     */
+;/* FSEU is not liable for consequential damages.                        */
+;/*                                                                      */
+;/* (V1.4)                                                               */
+;/************************************************************************/
+;/*  Startup for ARM                                                     */
+;/*  Version     V1.02                                                   */
+;/*  Date        2011-07-25                                              */
+;/*  Target-mcu  MB9B61x                                                 */
+;/************************************************************************/
+
+; Stack Configuration
+;  Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+;  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+
+Heap_Size       EQU     0x00000000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                DCD     CSV_Handler               ; 0: Clock Super Visor
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer
+                DCD     LVD_Handler               ; 2: Low Voltage Detector
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7
+                DCD     INT8_31_Handler           ; 5: External Interrupt Request ch.8 to ch.31
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7
+                DCD     PPG_Handler               ; 23: PPG
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter
+                DCD     ADC0_IRQHandler           ; 25: ADC0
+                DCD     ADC1_IRQHandler           ; 26: ADC1
+                DCD     ADC2_IRQHandler           ; 27: ADC2
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare
+                DCD     BT0_7_IRQHandler          ; 31: Base Timer ch.0 to ch.7
+                DCD     ETHER_MAC0_IRQHandler     ; 32: Ethernet MAC ch.0
+                DCD     ETHER_MAC1_IRQHandler     ; 33: Ethernet MAC ch.1
+                DCD     USB0F_Handler             ; 34: USB0 Function
+                DCD     USB0_Handler              ; 35: USB0 Function / USB0 HOST
+                DCD     USB1F_Handler             ; 36: USB1 Function
+                DCD     USB1_Handler              ; 37: USB1 Function / USB1 HOST
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7
+                DCD     BT8_15_IRQHandler         ; 46: Base Timer ch.8 to ch.15
+                DCD     DummyHandler              ; 47: Reserved
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  CSV_Handler	          [WEAK]
+                EXPORT  SWDT_Handler              [WEAK]
+                EXPORT  LVD_Handler               [WEAK]
+                EXPORT  MFT_WG_IRQHandler         [WEAK]
+                EXPORT  INT0_7_Handler            [WEAK]
+                EXPORT  INT8_31_Handler           [WEAK]
+                EXPORT  DT_Handler                [WEAK]
+                EXPORT  MFS0RX_IRQHandler         [WEAK]
+                EXPORT  MFS0TX_IRQHandler         [WEAK]
+                EXPORT  MFS1RX_IRQHandler         [WEAK]
+                EXPORT  MFS1TX_IRQHandler         [WEAK]
+                EXPORT  MFS2RX_IRQHandler         [WEAK]
+                EXPORT  MFS2TX_IRQHandler         [WEAK]
+                EXPORT  MFS3RX_IRQHandler         [WEAK]
+                EXPORT  MFS3TX_IRQHandler         [WEAK]
+                EXPORT  MFS4RX_IRQHandler         [WEAK]
+                EXPORT  MFS4TX_IRQHandler         [WEAK]
+                EXPORT  MFS5RX_IRQHandler         [WEAK]
+                EXPORT  MFS5TX_IRQHandler         [WEAK]
+                EXPORT  MFS6RX_IRQHandler         [WEAK]
+                EXPORT  MFS6TX_IRQHandler         [WEAK]
+                EXPORT  MFS7RX_IRQHandler         [WEAK]
+                EXPORT  MFS7TX_IRQHandler         [WEAK]
+                EXPORT  PPG_Handler               [WEAK]
+                EXPORT  TIM_IRQHandler            [WEAK]
+                EXPORT  ADC0_IRQHandler           [WEAK]
+                EXPORT  ADC1_IRQHandler           [WEAK]
+                EXPORT  ADC2_IRQHandler           [WEAK]
+                EXPORT  MFT_FRT_IRQHandler        [WEAK]
+                EXPORT  MFT_IPC_IRQHandler        [WEAK]
+                EXPORT  MFT_OPC_IRQHandler        [WEAK]
+                EXPORT  BT0_7_IRQHandler          [WEAK]
+                EXPORT  ETHER_MAC0_IRQHandler     [WEAK]
+                EXPORT  ETHER_MAC1_IRQHandler     [WEAK]
+                EXPORT  USB0F_Handler             [WEAK]
+                EXPORT  USB0_Handler              [WEAK]
+                EXPORT  USB1F_Handler             [WEAK]
+                EXPORT  USB1_Handler              [WEAK]
+                EXPORT  DMAC0_Handler             [WEAK]
+                EXPORT  DMAC1_Handler             [WEAK]
+                EXPORT  DMAC2_Handler             [WEAK]
+                EXPORT  DMAC3_Handler             [WEAK]
+                EXPORT  DMAC4_Handler             [WEAK]
+                EXPORT  DMAC5_Handler             [WEAK]
+                EXPORT  DMAC6_Handler             [WEAK]
+                EXPORT  DMAC7_Handler             [WEAK]
+                EXPORT  BT8_15_IRQHandler         [WEAK]
+                EXPORT  DummyHandler              [WEAK]
+
+CSV_Handler
+SWDT_Handler
+LVD_Handler
+MFT_WG_IRQHandler
+INT0_7_Handler
+INT8_31_Handler
+DT_Handler
+MFS0RX_IRQHandler
+MFS0TX_IRQHandler
+MFS1RX_IRQHandler
+MFS1TX_IRQHandler
+MFS2RX_IRQHandler
+MFS2TX_IRQHandler
+MFS3RX_IRQHandler
+MFS3TX_IRQHandler
+MFS4RX_IRQHandler
+MFS4TX_IRQHandler
+MFS5RX_IRQHandler
+MFS5TX_IRQHandler
+MFS6RX_IRQHandler
+MFS6TX_IRQHandler
+MFS7RX_IRQHandler
+MFS7TX_IRQHandler
+PPG_Handler
+TIM_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+ADC2_IRQHandler
+MFT_FRT_IRQHandler
+MFT_IPC_IRQHandler
+MFT_OPC_IRQHandler
+BT0_7_IRQHandler
+DMAC0_Handler
+DMAC1_Handler
+DMAC2_Handler
+DMAC3_Handler
+DMAC4_Handler
+DMAC5_Handler
+DMAC6_Handler
+DMAC7_Handler
+ETHER_MAC0_IRQHandler
+ETHER_MAC1_IRQHandler
+USB0F_Handler
+USB0_Handler
+USB1F_Handler
+USB1_Handler
+BT8_15_IRQHandler
+DummyHandler
+
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+                
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                
+                ELSE
+                
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c

@@ -0,0 +1,244 @@
+/*
+ ****************************************************************************
+**
+**  File        : startup_mb9bf61x.c
+**
+**  Abstract    : This file contains interrupt vector and startup code.
+**
+**  Functions   : Reset_Handler
+**
+**  Target      : Fujitsu FM3 microcontrollers
+**
+**  Environment : Atollic TrueSTUDIO(R)
+**
+**  Distribution: The file is distributed “as is,” without any warranty
+**                of any kind.
+**
+**  (c)Copyright Atollic AB.
+**  You may use this file as-is or modify it according to the needs of your
+**  project. Distribution of this file (unmodified or modified) is not
+**  permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the
+**  rights to distribute the assembled, compiled & linked contents of this
+**  file as part of an application binary file, provided that it is built
+**  using the Atollic TrueSTUDIO(R) toolchain.
+**
+ ****************************************************************************
+*/
+
+/**
+**===========================================================================
+**  Revisions
+**===========================================================================
+**       Date        Modification
+**       2011-08-18  First issue.
+**===========================================================================
+*/
+
+/**
+**===========================================================================
+**  External declarations
+**===========================================================================
+*/
+extern unsigned long _sdata, _edata, _sidata, _sbss, _ebss, _isr_vector;
+extern unsigned long _estack;
+extern void __libc_init_array();
+extern void SystemInit();
+extern void main();
+
+/**
+**===========================================================================
+**  Default interrupt handler
+**===========================================================================
+*/
+void Default_Handler()
+{
+	/* Hang here */
+	while(1)
+	{
+	}
+}
+
+/**
+**===========================================================================
+**  Reset handler
+**===========================================================================
+*/
+__attribute__((naked)) void Reset_Handler()
+{
+	/* Data and BSS variables */
+	unsigned long *srcdata, *dstdata, *sbss;
+
+	/* Set up the stack pointer */
+	asm("ldr sp,=_estack\n\t");
+
+    /* Set up vector table offset register */
+	dstdata = (unsigned long *)0xe000ed08;
+	*dstdata = (unsigned long)&_isr_vector;
+
+	srcdata = &_sidata;
+	dstdata = &_sdata;
+	sbss = &_sbss;
+
+	/* Copy data */
+	while(dstdata != &_edata)
+	{
+		*(dstdata++) = *(srcdata++);
+	}
+
+	/* Clear BSS */
+	while(sbss != &_ebss)
+	{
+		*(sbss++) = '\0';
+	}
+
+	/* Run static constructors */
+	//__libc_init_array();
+
+	/* Call the clock system initialization function.*/
+	SystemInit();
+
+	/* Jump to main */
+	main();
+
+	/* In case main returns, use default handler */
+	Default_Handler();
+}
+
+/**
+**===========================================================================
+**  Weak definitions of handlers point to Default_Handler if not implemented
+**===========================================================================
+*/
+void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MemManage_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void BusFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void UsageFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DebugMonitor_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
+
+void CSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SWDT_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void LVD_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_WG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void INT0_7_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void INT8_31_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DT_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS0RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS0TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS1RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS1TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS2RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS2TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS3RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS3TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS4RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS4TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS5RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS5TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS6RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS6TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS7RX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFS7TX_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PPG_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void TIM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_FRT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_IPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MFT_OPC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void BT0_7_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ETHER_MAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ETHER_MAC1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void USB0F_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB0_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB1F_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void USB1_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC0_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC1_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC2_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC3_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC4_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC5_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC6_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void DMAC7_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void BT8_15_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+
+
+/**
+**===========================================================================
+**  Interrupt Vector Table
+**===========================================================================
+*/
+void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) = {
+		/* Processor exceptions */
+		(void (*)(void))&_estack, /* 0 - Stack pointer */
+		Reset_Handler,            /* 1 - Reset */
+		NMI_Handler,              /* 2 - NMI  */
+		HardFault_Handler,        /* 3 - Hard fault */
+		MemManage_Handler,        /* 4 - Memory management fault */
+		BusFault_Handler,         /* 5 - Bus fault */
+		UsageFault_Handler,       /* 6 - Usage fault */
+		0,                        /* 7 - Reserved */
+		0,                        /* 8 - Reserved */
+		0,                        /* 9 - Reserved */
+		0,                        /* 10 - Reserved */
+		SVC_Handler,              /* 11 - SVCall */
+		DebugMonitor_Handler,     /* 12 - Reserved for Debug */
+		0,                        /* 13 - Reserved */
+		PendSV_Handler,           /* 14 - PendSV */
+		SysTick_Handler,          /* 15 - Systick */
+
+		/* External Interrupts */
+		CSV_Handler,              /* 0: Clock Super Visor */
+		SWDT_Handler,             /* 1: Software Watchdog Timer */
+		LVD_Handler,              /* 2: Low Voltage Detector */
+		MFT_WG_IRQHandler,        /* 3: Wave Form Generator / DTIF */
+		INT0_7_Handler,           /* 4: External Interrupt Request ch.0 to ch.7 */
+		INT8_31_Handler,          /* 5: External Interrupt Request ch.8 to ch.31 */
+		DT_Handler,               /* 6: Dual Timer / Quad Decoder */
+		MFS0RX_IRQHandler,        /* 7: MultiFunction Serial ch.0 */
+		MFS0TX_IRQHandler,        /* 8: MultiFunction Serial ch.0 */
+		MFS1RX_IRQHandler,        /* 9: MultiFunction Serial ch.1 */
+		MFS1TX_IRQHandler,        /* 10: MultiFunction Serial ch.1 */
+		MFS2RX_IRQHandler,        /* 11: MultiFunction Serial ch.2 */
+		MFS2TX_IRQHandler,        /* 12: MultiFunction Serial ch.2 */
+		MFS3RX_IRQHandler,        /* 13: MultiFunction Serial ch.3 */
+		MFS3TX_IRQHandler,        /* 14: MultiFunction Serial ch.3 */
+		MFS4RX_IRQHandler,        /* 15: MultiFunction Serial ch.4 */
+		MFS4TX_IRQHandler,        /* 16: MultiFunction Serial ch.4 */
+		MFS5RX_IRQHandler,        /* 17: MultiFunction Serial ch.5 */
+		MFS5TX_IRQHandler,        /* 18: MultiFunction Serial ch.5 */
+		MFS6RX_IRQHandler,        /* 19: MultiFunction Serial ch.6 */
+		MFS6TX_IRQHandler,        /* 20: MultiFunction Serial ch.6 */
+		MFS7RX_IRQHandler,        /* 21: MultiFunction Serial ch.7 */
+		MFS7TX_IRQHandler,        /* 22: MultiFunction Serial ch.7 */
+		PPG_Handler,              /* 23: PPG */
+		TIM_IRQHandler,           /* 24: OSC / PLL / Watch Counter */
+		ADC0_IRQHandler,          /* 25: ADC0 */
+		ADC1_IRQHandler,          /* 26: ADC1 */
+		ADC2_IRQHandler,          /* 27: ADC2 */
+		MFT_FRT_IRQHandler,       /* 28: Free-run Timer */
+		MFT_IPC_IRQHandler,       /* 29: Input Capture */
+		MFT_OPC_IRQHandler,       /* 30: Output Compare */
+		BT0_7_IRQHandler,         /* 31: Base Timer ch.0 to ch.7 */
+		ETHER_MAC0_IRQHandler,    /* 32: Ethernet MAC ch.0 */
+		ETHER_MAC1_IRQHandler,    /* 33: Ethernet MAC ch.1 */
+		USB0F_Handler,            /* 34: USB0 Function */
+		USB0_Handler,             /* 35: USB0 Function / USB0 HOST */
+		USB1F_Handler,            /* 36: USB1 Function */
+		USB1_Handler,             /* 37: USB1 Function / USB1 HOST */
+		DMAC0_Handler,            /* 38: DMAC ch.0 */
+		DMAC1_Handler,            /* 39: DMAC ch.1 */
+		DMAC2_Handler,            /* 40: DMAC ch.2 */
+		DMAC3_Handler,            /* 41: DMAC ch.3 */
+		DMAC4_Handler,            /* 42: DMAC ch.4 */
+		DMAC5_Handler,            /* 43: DMAC ch.5 */
+		DMAC6_Handler,            /* 44: DMAC ch.6 */
+		DMAC7_Handler,            /* 45: DMAC ch.7 */
+		BT8_15_IRQHandler,        /* 46: Base Timer ch.8 to ch.15 */
+		Default_Handler           /* 47: Reserved */
+};

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S

@@ -0,0 +1,417 @@
+;/************************************************************************/
+;/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+;/*                                                                      */
+;/* The following software deliverable is intended for and must only be  */
+;/* used for reference and in an evaluation laboratory environment.      */
+;/* It is provided on an as-is basis without charge and is subject to    */
+;/* alterations.                                                         */
+;/* It is the user's obligation to fully test the software in its        */
+;/* environment and to ensure proper functionality, qualification and    */
+;/* compliance with component specifications.                            */
+;/*                                                                      */
+;/* In the event the software deliverable includes the use of open       */
+;/* source components, the provisions of the governing open source       */
+;/* license agreement shall apply with respect to such software          */
+;/* deliverable.                                                         */
+;/* FSEU does not warrant that the deliverables do not infringe any      */
+;/* third party intellectual property right (IPR). In the event that     */
+;/* the deliverables infringe a third party IPR it is the sole           */
+;/* responsibility of the customer to obtain necessary licenses to       */
+;/* continue the usage of the deliverable.                               */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law FSEU disclaims all */
+;/* warranties, whether express or implied, in particular, but not       */
+;/* limited to, warranties of merchantability and fitness for a          */
+;/* particular purpose for which the deliverable is not designated.      */
+;/*                                                                      */
+;/* To the maximum extent permitted by applicable law, FSEU's liability  */
+;/* is restricted to intentional misconduct and gross negligence.        */
+;/* FSEU is not liable for consequential damages.                        */
+;/*                                                                      */
+;/* (V1.5)                                                               */
+;/************************************************************************/
+;/*  Startup for IAR                                                     */
+;/*  Version     V1.00                                                   */
+;/*  Date        2011-07-25                                              */
+;/*  Target-mcu  MB9B610                                                 */
+;/************************************************************************/
+
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)               ; Top of Stack
+		        DCD     Reset_Handler             ; Reset
+                DCD     NMI_Handler               ; NMI
+                DCD     HardFault_Handler         ; Hard Fault
+                DCD     MemManage_Handler         ; MPU Fault
+                DCD     BusFault_Handler          ; Bus Fault
+                DCD     UsageFault_Handler        ; Usage Fault
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall
+                DCD     DebugMon_Handler          ; Debug Monitor
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV
+                DCD     SysTick_Handler           ; SysTick
+
+                DCD     CSV_Handler               ; 0: Clock Super Visor
+                DCD     SWDT_Handler              ; 1: Software Watchdog Timer
+                DCD     LVD_Handler               ; 2: Low Voltage Detector
+                DCD     MFT_WG_IRQHandler         ; 3: Wave Form Generator / DTIF
+                DCD     INT0_7_Handler            ; 4: External Interrupt Request ch.0 to ch.7
+                DCD     INT8_31_Handler           ; 5: External Interrupt Request ch.8 to ch.31
+                DCD     DT_Handler                ; 6: Dual Timer / Quad Decoder
+                DCD     MFS0RX_IRQHandler         ; 7: MultiFunction Serial ch.0
+                DCD     MFS0TX_IRQHandler         ; 8: MultiFunction Serial ch.0
+                DCD     MFS1RX_IRQHandler         ; 9: MultiFunction Serial ch.1
+                DCD     MFS1TX_IRQHandler         ; 10: MultiFunction Serial ch.1
+                DCD     MFS2RX_IRQHandler         ; 11: MultiFunction Serial ch.2
+                DCD     MFS2TX_IRQHandler         ; 12: MultiFunction Serial ch.2
+                DCD     MFS3RX_IRQHandler         ; 13: MultiFunction Serial ch.3
+                DCD     MFS3TX_IRQHandler         ; 14: MultiFunction Serial ch.3
+                DCD     MFS4RX_IRQHandler         ; 15: MultiFunction Serial ch.4
+                DCD     MFS4TX_IRQHandler         ; 16: MultiFunction Serial ch.4
+                DCD     MFS5RX_IRQHandler         ; 17: MultiFunction Serial ch.5
+                DCD     MFS5TX_IRQHandler         ; 18: MultiFunction Serial ch.5
+                DCD     MFS6RX_IRQHandler         ; 19: MultiFunction Serial ch.6
+                DCD     MFS6TX_IRQHandler         ; 20: MultiFunction Serial ch.6
+                DCD     MFS7RX_IRQHandler         ; 21: MultiFunction Serial ch.7
+                DCD     MFS7TX_IRQHandler         ; 22: MultiFunction Serial ch.7
+                DCD     PPG_Handler               ; 23: PPG
+                DCD     TIM_IRQHandler            ; 24: OSC / PLL / Watch Counter
+                DCD     ADC0_IRQHandler           ; 25: ADC0
+                DCD     ADC1_IRQHandler           ; 26: ADC1
+                DCD     ADC2_IRQHandler           ; 27: ADC2
+                DCD     MFT_FRT_IRQHandler        ; 28: Free-run Timer
+                DCD     MFT_IPC_IRQHandler        ; 29: Input Capture
+                DCD     MFT_OPC_IRQHandler        ; 30: Output Compare
+                DCD     BT0_7_IRQHandler          ; 31: Base Timer ch.0 to ch.7
+                DCD     ETHER_MAC0_IRQHandler     ; 32: Ethernet MAC ch.0
+                DCD     ETHER_MAC1_IRQHandler     ; 33: Ethernet MAC ch.1
+                DCD     USB0F_Handler             ; 34: USB0 Function
+                DCD     USB0_Handler              ; 35: USB0 Function / USB0 HOST
+                DCD     USB1F_Handler             ; 36: USB1 Function
+                DCD     USB1_Handler              ; 37: USB1 Function / USB1 HOST
+                DCD     DMAC0_Handler             ; 38: DMAC ch.0
+                DCD     DMAC1_Handler             ; 39: DMAC ch.1
+                DCD     DMAC2_Handler             ; 40: DMAC ch.2
+                DCD     DMAC3_Handler             ; 41: DMAC ch.3
+                DCD     DMAC4_Handler             ; 42: DMAC ch.4
+                DCD     DMAC5_Handler             ; 43: DMAC ch.5
+                DCD     DMAC6_Handler             ; 44: DMAC ch.6
+                DCD     DMAC7_Handler             ; 45: DMAC ch.7
+                DCD     BT8_15_IRQHandler         ; 46: Base Timer ch.8 to ch.15
+                DCD     DummyHandler              ; 47: Reserved
+
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK MemManage_Handler
+                SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER(1)
+SVC_Handler
+                B       SVC_Handler
+
+                PUBWEAK DebugMon_Handler
+                SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+                B       DebugMon_Handler
+
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+                B       PendSV_Handler
+
+                PUBWEAK SysTick_Handler
+                SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+                B       SysTick_Handler
+
+
+
+                PUBWEAK CSV_Handler
+                SECTION .text:CODE:REORDER(1)
+CSV_Handler
+                B       CSV_Handler
+
+                PUBWEAK SWDT_Handler
+                SECTION .text:CODE:REORDER(1)
+SWDT_Handler
+                B       SWDT_Handler
+
+                PUBWEAK LVD_Handler
+                SECTION .text:CODE:REORDER(1)
+LVD_Handler
+                B       LVD_Handler
+
+                PUBWEAK MFT_WG_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_WG_IRQHandler
+                B       MFT_WG_IRQHandler
+                
+                PUBWEAK INT0_7_Handler
+                SECTION .text:CODE:REORDER(1)
+INT0_7_Handler
+                B       INT0_7_Handler
+
+                PUBWEAK INT8_31_Handler
+                SECTION .text:CODE:REORDER(1)
+INT8_31_Handler
+                B       INT8_31_Handler
+                
+                PUBWEAK DT_Handler
+                SECTION .text:CODE:REORDER(1)
+DT_Handler
+                B       DT_Handler
+
+                PUBWEAK MFS0RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS0RX_IRQHandler
+                B       MFS0RX_IRQHandler
+
+                PUBWEAK MFS0TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS0TX_IRQHandler
+                B       MFS0TX_IRQHandler
+
+                PUBWEAK MFS1RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS1RX_IRQHandler
+                B       MFS1RX_IRQHandler
+
+                PUBWEAK MFS1TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS1TX_IRQHandler
+                B       MFS1TX_IRQHandler
+
+                PUBWEAK MFS2RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS2RX_IRQHandler
+                B       MFS2RX_IRQHandler
+
+                PUBWEAK MFS2TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS2TX_IRQHandler
+                B       MFS2TX_IRQHandler
+
+                PUBWEAK MFS3RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS3RX_IRQHandler
+                B       MFS3RX_IRQHandler
+
+                PUBWEAK MFS3TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS3TX_IRQHandler
+                B       MFS3TX_IRQHandler
+
+                PUBWEAK MFS4RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS4RX_IRQHandler
+                B       MFS4RX_IRQHandler
+
+                PUBWEAK MFS4TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS4TX_IRQHandler
+                B       MFS4TX_IRQHandler
+
+                PUBWEAK MFS5RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS5RX_IRQHandler
+                B       MFS5RX_IRQHandler
+
+                PUBWEAK MFS5TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS5TX_IRQHandler
+                B       MFS5TX_IRQHandler
+
+                PUBWEAK MFS6RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS6RX_IRQHandler
+                B       MFS6RX_IRQHandler
+
+                PUBWEAK MFS6TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS6TX_IRQHandler
+                B       MFS6TX_IRQHandler
+
+                PUBWEAK MFS7RX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS7RX_IRQHandler
+                B       MFS7RX_IRQHandler
+
+                PUBWEAK MFS7TX_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFS7TX_IRQHandler
+                B       MFS7TX_IRQHandler
+
+                PUBWEAK PPG_Handler
+                SECTION .text:CODE:REORDER(1)
+PPG_Handler
+                B       PPG_Handler
+
+                PUBWEAK TIM_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+TIM_IRQHandler
+                B       TIM_IRQHandler
+
+                PUBWEAK ADC0_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC0_IRQHandler
+                B       ADC0_IRQHandler
+
+                PUBWEAK ADC1_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC1_IRQHandler
+                B       ADC1_IRQHandler
+
+                PUBWEAK ADC2_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ADC2_IRQHandler
+                B       ADC2_IRQHandler
+
+                PUBWEAK MFT_FRT_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_FRT_IRQHandler
+                B       MFT_FRT_IRQHandler
+
+                PUBWEAK MFT_IPC_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_IPC_IRQHandler
+                B       MFT_IPC_IRQHandler
+
+                PUBWEAK MFT_OPC_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+MFT_OPC_IRQHandler
+                B       MFT_OPC_IRQHandler
+
+                PUBWEAK BT0_7_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+BT0_7_IRQHandler
+                B       BT0_7_IRQHandler
+
+                PUBWEAK ETHER_MAC0_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ETHER_MAC0_IRQHandler
+                B       ETHER_MAC0_IRQHandler
+
+                PUBWEAK ETHER_MAC1_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+ETHER_MAC1_IRQHandler
+                B       ETHER_MAC1_IRQHandler
+
+                PUBWEAK USB0F_Handler
+                SECTION .text:CODE:REORDER(1)
+USB0F_Handler
+                B       USB0F_Handler
+
+                PUBWEAK USB0_Handler
+                SECTION .text:CODE:REORDER(1)
+USB0_Handler
+                B       USB0_Handler
+
+                PUBWEAK USB1F_Handler
+                SECTION .text:CODE:REORDER(1)
+USB1F_Handler
+                B       USB1F_Handler
+
+                PUBWEAK USB1_Handler
+                SECTION .text:CODE:REORDER(1)
+USB1_Handler
+                B       USB1_Handler
+
+                PUBWEAK DMAC0_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC0_Handler
+                B       DMAC0_Handler
+
+
+                PUBWEAK DMAC1_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC1_Handler
+                B       DMAC1_Handler
+
+                PUBWEAK DMAC2_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC2_Handler
+                B       DMAC2_Handler
+
+                PUBWEAK DMAC3_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC3_Handler
+                B       DMAC3_Handler
+
+                PUBWEAK DMAC4_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC4_Handler
+                B       DMAC4_Handler
+
+                PUBWEAK DMAC5_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC5_Handler
+                B       DMAC5_Handler
+
+                PUBWEAK DMAC6_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC6_Handler
+                B       DMAC6_Handler
+
+                PUBWEAK DMAC7_Handler
+                SECTION .text:CODE:REORDER(1)
+DMAC7_Handler
+                B       DMAC7_Handler
+
+                PUBWEAK BT8_15_IRQHandler
+                SECTION .text:CODE:REORDER(1)
+BT8_15_IRQHandler
+                B       BT8_15_IRQHandler
+
+                PUBWEAK DummyHandler
+                SECTION .text:CODE:REORDER(1)
+DummyHandler
+                B       DummyHandler
+
+                END

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.c

@@ -0,0 +1,206 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+
+#include "board.h"
+
+/** \file system_mb9bf61x.c
+ **
+ ** FM3 system initialization functions
+ ** All adjustments can be done in belonging header file.
+ **
+ ** History:
+ ** 2011-07-07 V1.0 MWi original version
+ ******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** System Clock Frequency (Core Clock) Variable according CMSIS
+ ******************************************************************************/
+uint32_t SystemCoreClock = __HCLK;
+
+/**
+ ******************************************************************************
+ ** \brief  Update the System Core Clock with current core Clock retrieved from
+ ** cpu registers.
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemCoreClockUpdate (void) {
+  uint32_t masterClk;
+  uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
+
+  switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
+    case 0:                                 /* internal High-speed Cr osc.    */
+      masterClk = __CLKHC;
+      break;
+
+    case 1:                                 /* external main osc.             */
+      masterClk = __CLKMO;
+      break;
+
+    case 2:                                 /* PLL clock                      */
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violation:
+  //   "Unordered accesses to a volatile location"
+      u32RegisterRead = (__CLKMO  * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
+      masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
+      break;
+
+    case 4:                                 /* internal Low-speed CR osc.     */
+      masterClk = __CLKLC;
+      break;
+
+    case 5:                                 /* external Sub osc.              */
+      masterClk = __CLKSO;
+      break;
+
+    default:
+      masterClk = 0Ul;
+      break;
+  }
+
+  switch (FM3_CRG->BSC_PSR & 0x07) {
+    case 0:
+      SystemCoreClock = masterClk;
+      break;
+
+    case 1:
+      SystemCoreClock = masterClk / 2;
+      break;
+
+    case 2:
+      SystemCoreClock = masterClk / 3;
+      break;
+
+    case 3:
+      SystemCoreClock = masterClk / 4;
+      break;
+
+    case 4:
+      SystemCoreClock = masterClk / 6;
+      break;
+
+    case 5:
+      SystemCoreClock = masterClk /8;
+      break;
+
+    case 6:
+      SystemCoreClock = masterClk /16;
+      break;
+
+    default:
+      SystemCoreClock = 0Ul;
+      break;
+  }
+
+}
+
+/**
+ ******************************************************************************
+ ** \brief  Setup the microcontroller system. Initialize the System and update
+ ** the SystemCoreClock variable.
+ **
+ ** \param  none
+ ** \return none
+ ******************************************************************************/
+void SystemInit (void) {
+
+  static uint32_t u32IoRegisterRead;  // Workaround variable for MISRA C rule conformance
+
+#if (HWWD_DISABLE)                                 /* HW Watchdog Disable */
+  FM3_HWWDT->WDG_LCK = 0x1ACCE551;                 /* HW Watchdog Unlock */
+  FM3_HWWDT->WDG_LCK = 0xE5331AAE;
+  FM3_HWWDT->WDG_CTL = 0;                          /* HW Watchdog stop */
+#endif
+
+#if (CLOCK_SETUP)                                   /* Clock Setup */
+  FM3_CRG->BSC_PSR   = BSC_PSR_Val;                /* set System Clock presacaler */
+  FM3_CRG->APBC0_PSR = APBC0_PSR_Val;              /* set APB0 presacaler */
+  FM3_CRG->APBC1_PSR = APBC1_PSR_Val;              /* set APB1 presacaler */
+  FM3_CRG->APBC2_PSR = APBC2_PSR_Val;              /* set APB2 presacaler */
+  FM3_CRG->SWC_PSR   = SWC_PSR_Val | (1UL << 7);   /* set SW Watchdog presacaler */
+  FM3_CRG->TTC_PSR   = TTC_PSR_Val;                /* set Trace Clock presacaler */
+
+  FM3_CRG->CSW_TMR   = CSW_TMR_Val;                /* set oscillation stabilization wait time */
+
+  if (SCM_CTL_Val & (1UL << 1)) {                    /* Main clock oscillator enabled ? */
+    FM3_CRG->SCM_CTL |= (1UL << 1);                /* enable main oscillator */
+    while (!(FM3_CRG->SCM_STR & (1UL << 1)));      /* wait for Main clock oscillation stable */
+  }
+
+  if (SCM_CTL_Val & (1UL << 3)) {                    /* Sub clock oscillator enabled ? */
+    FM3_CRG->SCM_CTL |= (1UL << 3);                /* enable sub oscillator */
+    while (!(FM3_CRG->SCM_STR & (1UL << 3)));      /* wait for Sub clock oscillation stable */
+  }
+
+  FM3_CRG->PSW_TMR   = PSW_TMR_Val;                /* set PLL stabilization wait time */
+  FM3_CRG->PLL_CTL1  = PLL_CTL1_Val;               /* set PLLM and PLLK */
+  FM3_CRG->PLL_CTL2  = PLL_CTL2_Val;               /* set PLLN          */
+
+  if (SCM_CTL_Val & (1UL << 4)) {                    /* PLL enabled ? */
+    FM3_CRG->SCM_CTL  |= (1UL << 4);               /* enable PLL */
+    while (!(FM3_CRG->SCM_STR & (1UL << 4)));      /* wait for PLL stable */
+  }
+
+  FM3_CRG->SCM_CTL  |= (SCM_CTL_Val & 0xE0);       /* Set Master Clock switch */
+
+  {
+      volatile unsigned int i;
+      for(i=0;i<200000;i++);
+  }
+  // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
+  // violations:
+  //   "Unordered reads and writes to or from same location" and
+  //   "Unordered accesses to a volatile location"
+  do
+  {
+    u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
+  }while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
+#endif // (CLOCK_SETUP)
+
+#if (CR_TRIM_SETUP)
+  /* CR Trimming Data  */
+  if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
+  {
+    /* UnLock (MCR_FTRM) */
+    FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
+    /* Set MCR_FTRM */
+    FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
+    /* Lock (MCR_FTRM) */
+    FM3_CRTRIM->MCR_RLR = 0x00000000;
+  }
+#endif // (CR_TRIM_SETUP)
+}
+
+
+

bsp/mb9bf618s/CMSIS/DeviceSupport/fujitsu/mb9bf61x/system_mb9bf61x.h

@@ -0,0 +1,678 @@
+/************************************************************************/
+/*               (C) Fujitsu Semiconductor Europe GmbH (FSEU)           */
+/*                                                                      */
+/* The following software deliverable is intended for and must only be  */
+/* used for reference and in an evaluation laboratory environment.      */
+/* It is provided on an as-is basis without charge and is subject to    */
+/* alterations.                                                         */
+/* It is the user's obligation to fully test the software in its        */
+/* environment and to ensure proper functionality, qualification and    */
+/* compliance with component specifications.                            */
+/*                                                                      */
+/* In the event the software deliverable includes the use of open       */
+/* source components, the provisions of the governing open source       */
+/* license agreement shall apply with respect to such software          */
+/* deliverable.                                                         */
+/* FSEU does not warrant that the deliverables do not infringe any      */
+/* third party intellectual property right (IPR). In the event that     */
+/* the deliverables infringe a third party IPR it is the sole           */
+/* responsibility of the customer to obtain necessary licenses to       */
+/* continue the usage of the deliverable.                               */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law FSEU disclaims all */
+/* warranties, whether express or implied, in particular, but not       */
+/* limited to, warranties of merchantability and fitness for a          */
+/* particular purpose for which the deliverable is not designated.      */
+/*                                                                      */
+/* To the maximum extent permitted by applicable law, FSEU's liability  */
+/* is restricted to intentional misconduct and gross negligence.        */
+/* FSEU is not liable for consequential damages.                        */
+/*                                                                      */
+/* (V1.5)                                                               */
+/************************************************************************/
+/** \file system_mb9bf61x.h
+ **
+ ** Headerfile for FM3 system parameters
+ **
+ ** User clock definitions can be done for the following clock settings:
+ ** - CLOCK_SETUP : Execute the clock settings form the settings below in
+ **                 SystemInit()
+ ** - __CLKMO : External clock frequency for main oscillion
+ ** - __CLKSO : External clock frequency for sub oscillion
+ ** - SCM_CTL : System Clock Mode Control Register
+ ** - BSC_PSR : Base Clock Prescaler Register
+ ** - APBC0_PSR : APB0 Prescaler Register
+ ** - APBC1_PSR : APB1 Prescaler Register
+ ** - APBC2_PSR : APB2 Prescaler Register
+ ** - SWC_PSR : Software Watchdog Clock Prescaler Register
+ ** - TTC_PSR : Trace Clock Prescaler Register
+ ** - CSW_TMR : Clock Stabilization Wait Time Register
+ ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register
+ ** - PLL_CTL1 : PLL Control Register 1
+ ** - PLL_CTL2 : PLL Control Register 2
+ **
+ ** The register settings are check for correct values of reserved bits.
+ ** Otherwise a preprocessor error is output and stops the build process.
+ ** Furthermore the 'master clock' is retrieved from the register settings
+ ** and the system clock (HCLK) is calculated from the Base Clock Prescaler
+ ** Register (BSC_PSR). This value is used for the global CMSIS variable
+ ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is
+ ** is checked. Note that not all possible wrong setting are checked! The
+ ** user has to take care to fulfill the settings stated in the according
+ ** device's data sheet!
+ **
+ ** User definition for Hardware Watchdog:
+ ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()
+ **
+ ** User definition for CR Trimming:
+ ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()
+ **
+ ** History:
+ ** 2011-05-16 V1.0 MWi original version
+ *****************************************************************************/
+
+#ifndef _SYSTEM_MB9BF61X_H_
+#define _SYSTEM_MB9BF61X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/******************************************************************************/
+/* Include files                                                              */
+/******************************************************************************/
+   
+#include <stdint.h>
+
+/******************************************************************************/
+/* Global pre-processor symbols/macros ('define')                             */
+/******************************************************************************/
+   
+/******************************************************************************/
+/*                                                                            */
+/*                      START OF USER SETTINGS HERE                           */
+/*                      ===========================                           */   
+/*                                                                            */
+/*                 All lines with '<<<' can be set by user.                   */
+/*                                                                            */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Clock Setup Enable
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = No clock setup done by system_mb9xfxxx.c
+ ** - 1 = Clock setup done by system_mb9xfxxx.c
+ ******************************************************************************/ 
+#define CLOCK_SETUP               1   // <<< Define clock setup here
+
+/**
+ ******************************************************************************
+ ** \brief External Main Clock Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/    
+#define __CLKMO        ( 4000000UL)   // <<< External   4MHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief External Sub Clock Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/  
+#define __CLKSO        (   32768UL)   // <<<  External  32KHz Crystal
+
+/**
+ ******************************************************************************
+ ** \brief System Clock Mode Control Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** SCM_CTL
+ **
+ ** Bit#7-5 : RCS[2:0]
+ ** - 0 = Internal high-speed CR oscillation (default)
+ ** - 1 = Main oscillation clock
+ ** - 2 = PLL oscillation clock
+ ** - 3 = (not allowed)
+ ** - 4 = Internal low-speed CR oscillation
+ ** - 5 = Sub clock oscillation
+ ** - 6 = (not allowed)
+ ** - 7 = (not allowed)
+ **
+ ** Bit#4 : PLLE
+ ** - 0 = Disable PLL (default)
+ ** - 1 = Enable PLL
+ **
+ ** Bit#3 : SOSCE
+ ** - 0 = Disable sub oscillation (default)
+ ** - 1 = Enable sub oscillation
+ **
+ ** Bit#2 : (reserved)
+ **
+ ** Bit#1 : MOSCE
+ ** - 0 = Disable main oscillation (default)
+ ** - 1 = Enable main oscillation  
+ **
+ ** Bit#0 : (reserved)  
+ ******************************************************************************/ 
+#define SCM_CTL_Val           0x00000052    // <<< Define SCM_CTL here
+
+/**
+ ******************************************************************************
+ ** \brief Base Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** BSC_PSR
+ **
+ ** Bit#7-3 : (reserved)
+ **
+ ** Bit#2-0 : BSR[2:0]
+ ** - 0 = HCLK = Master Clock
+ ** - 1 = HCLK = Master Clock / 2
+ ** - 2 = HCLK = Master Clock / 3
+ ** - 3 = HCLK = Master Clock / 4
+ ** - 4 = HCLK = Master Clock / 6
+ ** - 5 = HCLK = Master Clock / 8
+ ** - 6 = HCLK = Master Clock / 16
+ ** - 7 = (reserved)
+ ******************************************************************************/    
+#define BSC_PSR_Val           0x00000000    // <<< Define BSC_PSR here
+ 
+/**
+ ******************************************************************************
+ ** \brief APB0 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC0_PSR
+ **
+ ** Bit#7-2 : (reserved)
+ **
+ ** Bit#1-0 : BSR[2:0] 
+ ** - 0 = PCLK0 = HCLK
+ ** - 1 = PCLK0 = HCLK / 2
+ ** - 2 = PCLK0 = HCLK / 4
+ ** - 3 = PCLK0 = HCLK / 8
+ ******************************************************************************/    
+#define APBC0_PSR_Val         0x00000001     // <<< Define APBC0_PSR here
+   
+/**
+ ******************************************************************************
+ ** \brief APB1 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC1_PSR
+ **
+ ** Bit#7 : APBC1EN
+ ** - 0 = Disable PCLK1 output
+ ** - 1 = Enables PCLK1 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ **
+ ** Bit#4 : APBC1RST
+ ** - 0 = APB1 bus reset, inactive (default)
+ ** - 1 = APB1 bus reset, active  
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC1[2:0]
+ ** - 0 = PCLK1 = HCLK
+ ** - 1 = PCLK1 = HCLK / 2
+ ** - 2 = PCLK1 = HCLK / 4
+ ** - 3 = PCLK1 = HCLK / 8
+ ******************************************************************************/     
+#define APBC1_PSR_Val         0x00000081    // <<< Define APBC1_PSR here
+   
+/**
+ ******************************************************************************
+ ** \brief APB2 Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** APBC2_PSR
+ **
+ ** Bit#7 : APBC2EN
+ ** - 0 = Disable PCLK2 output
+ ** - 1 = Enables PCLK2 (default)
+ **
+ ** Bit#6-5 : (reserved)
+ ** 
+ ** Bit#4 : APBC2RST
+ ** - 0 = APB2 bus reset, inactive (default)
+ ** - 1 = APB2 bus reset, active  
+ **
+ ** Bit#3-2 : (reserved)
+ **
+ ** Bit#1-0 : APBC2[1:0]
+ ** - 0 = PCLK2 = HCLK
+ ** - 1 = PCLK2 = HCLK / 2
+ ** - 2 = PCLK2 = HCLK / 4
+ ** - 3 = PCLK2 = HCLK / 8
+ ******************************************************************************/    
+#define APBC2_PSR_Val         0x00000081    // <<< Define APBC2_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Software Watchdog Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** SWC_PSR
+ **
+ ** Bit#7 : TESTB
+ ** - 0 = (not allowed)
+ ** - 1 = (always write "1" to this bit)
+ **
+ ** Bit#6-2 : (reserved)
+ **
+ ** Bit#1-0 : SWDS[2:0]
+ ** - 0 = SWDGOGCLK = PCLK0
+ ** - 1 = SWDGOGCLK = PCLK0 / 2
+ ** - 2 = SWDGOGCLK = PCLK0 / 4
+ ** - 3 = SWDGOGCLK = PCLK0 / 8
+ ******************************************************************************/  
+#define SWC_PSR_Val           0x00000003    // <<< Define SWC_PSR here
+
+/**
+ ******************************************************************************
+ ** \brief Trace Clock Prescaler Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** TTC_PSR
+ **
+ ** Bit#7-1 : (reserved)
+ **
+ ** Bit#0 : TTC
+ ** - 0 = TPIUCLK = HCLK
+ ** - 1 = TPIUCLK = HCLK / 2
+ ******************************************************************************/  
+#define TTC_PSR_Val           0x00000000    // <<< Define TTC_PSR here
+ 
+/**
+ ******************************************************************************
+ ** \brief Clock Stabilization Wait Time Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** CSW_TMR
+ **
+ ** Bit#7 : (reserved)
+ **
+ ** Bit#6-4 : SOWT[2:0]
+ ** - 0 = ~10.3 ms (default)
+ ** - 1 = ~20.5 ms
+ ** - 2 = ~41 ms
+ ** - 3 = ~82 ms
+ ** - 4 = ~164 ms
+ ** - 5 = ~327 ms
+ ** - 6 = ~655 ms
+ ** - 7 = ~1.31 s 
+ **
+ ** Bit#3-0 : MOWT[3:0]
+ ** - 0 = ~500 ns (default)
+ ** - 1 = ~8 us
+ ** - 2 = ~16 us
+ ** - 3 = ~32 us
+ ** - 4 = ~64 us
+ ** - 5 = ~128 us
+ ** - 6 = ~256 us
+ ** - 7 = ~512 us
+ ** - 8 = ~1.0 ms
+ ** - 9 = ~2.0 ms
+ ** - 10 = ~4.0 ms
+ ** - 11 = ~8.0 ms
+ ** - 12 = ~33.0 ms
+ ** - 13 = ~131 ms
+ ** - 14 = ~524 ms
+ ** - 15 = ~2.0 s
+ ******************************************************************************/     
+#define CSW_TMR_Val           0x0000005C    // <<< Define CSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Clock Stabilization Wait Time Setup Register value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PSW_TMR
+ **
+ ** Bit#7-5 : (reserved)
+ **
+ ** Bit#4 : PINC
+ ** - 0 = Selects CLKMO (main oscillation) (default)
+ ** - 1 = (setting diabled)
+ **
+ ** Bit#3 : (reserved)
+ **
+ ** Bit#2-0 : POWT[2:0]
+ ** - 0 = ~128 us (default) 
+ ** - 1 = ~256 us
+ ** - 2 = ~512 us
+ ** - 3 = ~1.02 ms
+ ** - 4 = ~2.05 ms
+ ** - 5 = ~4.10 ms
+ ** - 6 = ~8.20 ms
+ ** - 7 = ~16.40 ms
+ ******************************************************************************/    
+#define PSW_TMR_Val           0x00000000    // <<< Define PSW_TMR here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 1 value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PLL_CTL1
+ **
+ ** Bit#7-4 : PLLK[3:0]
+ ** - 0 = Division(PLLK) = 1/1 (default)
+ ** - 1 = Division(PLLK) = 1/2
+ ** - 2 = Division(PLLK) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLK) = 1/16
+ **
+ ** Bit#3-0 : PLLM[3:0]
+ ** - 0 = Division(PLLM) = 1/1 (default)
+ ** - 1 = Division(PLLM) = 1/2
+ ** - 2 = Division(PLLM) = 1/3
+ ** - . . .
+ ** - 15 = Division(PLLM) = 1/16
+ ******************************************************************************/    
+#define PLL_CTL1_Val          0x00000001    // <<< Define PLL_CTL1 here
+
+/**
+ ******************************************************************************
+ ** \brief PLL Control Register 2 value definition
+ **        <i>(USER SETTING)</i>
+ ** 
+ ** PLL_CTL2
+ **
+ ** Bit#7-6 : (reserved)
+ **
+ ** Bit#5-0 : PLLN[5:0]
+ ** - 0 = Division(PLLN) = 1/1 (default)
+ ** - 1 = Division(PLLN) = 1/2
+ ** - 2 = Division(PLLN) = 1/3
+ ** - . . .
+ ** - 63 = Division(PLLN) = 1/64
+ ******************************************************************************/    
+#define PLL_CTL2_Val          0x00000023    // <<< Define PLL_CTL2 here
+   
+/**
+ ******************************************************************************
+ ** \brief Hardware Watchdog disable definition
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = Hardware Watchdog enable
+ ** - 1 = Hardware Watchdog disable
+ ******************************************************************************/  
+#define HWWD_DISABLE          1   // <<< Define HW Watach dog enable here
+
+/**
+ ******************************************************************************
+ ** \brief Trimming CR
+ **        <i>(USER SETTING)</i>
+ **
+ ** - 0 = CR is not trimmed at startup
+ ** - 1 = CR is trimmed at startup
+ ******************************************************************************/  
+#define CR_TRIM_SETUP         1   // <<< Define CR trimming at startup enable here
+
+   
+/******************************************************************************/
+/*                                                                            */
+/*                         END OF USER SETTINGS HERE                          */
+/*                         =========================                          */ 
+/*                                                                            */
+/******************************************************************************/
+
+/******************************************************************************/
+/* Device dependent System Clock absolute maximum ranges                      */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/    
+#define __CLKHC        ( 4000000UL)         /* Internal   4MHz CR Oscillator  */
+   
+/**
+ ******************************************************************************
+ ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)
+ **        <i>(USER SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKLC        (  100000UL)         /* Internal 100KHz CR Oscillator  */  
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKMOMIN    (  4000000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Maximum Main Clock frequency using external clock
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKMOMAX    ( 50000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Any case minimum Sub Clock frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKSOMIN    (    32000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Maximum Sub Clock frequency using external clock
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __CLKSOMAX    (   100000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL input frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKINMIN (  4000000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL input frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKINMAX ( 16000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute minimum PLL oscillation frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKMIN   (200000000UL)
+   
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum PLL oscillation  frequency
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __PLLCLKMAX   (300000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Absolute maximum System Clock frequency (HCLK)
+ **        <i>(DEVICE DEPENDENT SETTING)</i>
+ ******************************************************************************/ 
+#define __HCLKMAX     (144000000UL)
+
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking range (clock settings)
+ ******************************************************************************/ 
+#define CHECK_RANGE(val, min, max)                ((val < min) || (val > max))
+   
+/**
+ ******************************************************************************
+ ** \brief Preprocessor macro for checking bits with mask (clock settings)
+ ******************************************************************************/ 
+#define CHECK_RSVD(val, mask)                     (val & mask)
+
+
+/******************************************************************************/
+/* Check register settings                                                    */
+/******************************************************************************/
+#if (CHECK_RSVD((SCM_CTL_Val),    ~0x000000FA))
+   #error "SCM_CTL: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
+   #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
+#endif
+
+#if (CHECK_RSVD((CSW_TMR_Val),    ~0x0000007F))
+   #error "CSW_TMR: Invalid values of reserved bits!"
+#endif
+
+#if ((SCM_CTL_Val & 0x10))       /* if PLL is used */
+  #if (CHECK_RSVD((PSW_TMR_val),  ~0x00000007))
+     #error "PSW_TMR: Invalid values of reserved bits!"
+  #endif
+
+  #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
+     #error "PLL_CTL1: Invalid values of reserved bits!"
+  #endif
+
+  #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))
+    #error "PLL_CTL2: Invalid values of reserved bits!"
+  #endif
+#endif
+
+#if (CHECK_RSVD((BSC_PSR_Val),    ~0x00000007))
+  #error "BSC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC0_PSR_Val),  ~0x00000003))
+  #error "APBC0_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC1_PSR_Val),  ~0x00000083))
+  #error "APBC1_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((APBC2_PSR_Val),  ~0x00000083))
+  #error "APBC2_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((SWC_PSR_Val),    ~0x00000003))
+  #error "SWC_PSR: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((TTC_PSR_Val),    ~0x00000001))
+  #error "TTC_PSR: Invalid values of reserved bits!"
+#endif
+
+/******************************************************************************/
+/* Define clocks with checking settings                                       */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL K factor from settings
+ ******************************************************************************/
+#define __PLLK         (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL N factor from settings
+ ******************************************************************************/
+#define __PLLN         (((PLL_CTL2_Val     ) & 0x3F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL M factor from settings
+ ******************************************************************************/
+#define __PLLM         (((PLL_CTL1_Val     ) & 0x0F) + 1)
+
+/**
+ ******************************************************************************
+ ** \brief Calculate PLL output frequency from settings
+ ******************************************************************************/
+#define __PLLCLK       ((__CLKMO  * __PLLN) / __PLLK)
+
+/******************************************************************************/
+/* Determine core clock frequency according to settings                       */
+/******************************************************************************/
+
+/**
+ ******************************************************************************
+ ** \brief Define Master Clock from settings
+ ******************************************************************************/
+#if   (((SCM_CTL_Val >> 5) & 0x07) == 0)
+  #define __MASTERCLK     (__CLKHC)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
+  #define __MASTERCLK     (__CLKMO)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
+  #define __MASTERCLK     (__PLLCLK)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
+  #define __MASTERCLK     (__CLKLC)
+#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
+  #define __MASTERCLK     (__CLKSO)
+#else
+  #define __MASTERCLK     (0UL)
+#endif
+
+/**
+ ******************************************************************************
+ ** \brief Define System Clock Frequency (Core Clock) from settings
+ ******************************************************************************/
+#if   ((BSC_PSR_Val & 0x07) == 0)
+  #define __HCLK         (__MASTERCLK / 1)
+#elif ((BSC_PSR_Val & 0x07) == 1)
+  #define __HCLK         (__MASTERCLK / 2)
+#elif ((BSC_PSR_Val & 0x07) == 2)
+  #define __HCLK         (__MASTERCLK / 3)
+#elif ((BSC_PSR_Val & 0x07) == 3)
+  #define __HCLK         (__MASTERCLK / 4)
+#elif ((BSC_PSR_Val & 0x07) == 4)
+  #define __HCLK         (__MASTERCLK / 6)
+#elif ((BSC_PSR_Val & 0x07) == 5)
+  #define __HCLK         (__MASTERCLK / 8)
+#elif ((BSC_PSR_Val & 0x07) == 6)
+  #define __HCLK         (__MASTERCLK /16)
+#else
+  #define __HCLK         (0UL)
+#endif
+
+/******************************************************************************/
+/* HCLK range check                                                           */
+/******************************************************************************/
+#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)
+  #error "Main Oscillator Clock (CLKMO) out of range!"
+#endif   
+
+#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)
+  #error "Sub Oscillator Clock (CLKMO) out of range!"
+#endif   
+
+#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)
+  #error "PLL input frequency out of range!"
+#endif  
+
+#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)
+  #error "PLL oscillation frequency out of range!"
+#endif  
+   
+#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)
+  #error "System Clock (HCLK) out of range!"
+#endif
+   
+/******************************************************************************/
+/* Global function prototypes ('extern', definition in C source)              */
+/******************************************************************************/
+
+extern uint32_t SystemCoreClock;          // System Clock Frequency (Core Clock)
+   
+extern void SystemInit (void);            // Initialize the system
+
+extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_MB9BF61X_H */

bsp/mb9bf618s/CMSIS/Include/arm_common_tables.h

@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_common_tables.h
+*
+* Description:  This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/mb9bf618s/CMSIS/Include/arm_const_structs.h

@@ -0,0 +1,85 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_const_structs.h
+*
+* Description:  This file has constant structs that are initialized for
+*               user convenience.  For example, some can be given as
+*               arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
+      16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
+      32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
+      64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
+      128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
+      256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
+      512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
+      1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
+      2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
+   };
+
+   const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
+      4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
+   };
+
+#endif

bsp/mb9bf618s/CMSIS/Include/arm_math.h

@@ -0,0 +1,7306 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date:        17. January 2013
+* $Revision:    V1.4.1
+*
+* Project:      CMSIS DSP Library
+* Title:        arm_math.h
+*
+* Description:  Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * <b>Introduction</b>
+   *
+   * This user manual describes the CMSIS DSP software library,
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of functions each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values.
+   *
+   * <b>Using the Library</b>
+   *
+   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+   * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or
+   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+   *
+   * <b>Examples</b>
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * <b>Toolchain Support</b>
+   *
+   * The library has been developed and tested with MDK-ARM version 4.60.
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * <b>Building the Library</b>
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * <b>Pre-processor Macros</b>
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * - UNALIGNED_SUPPORT_DISABLE:
+   *
+   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+   *
+   * - ARM_MATH_BIG_ENDIAN:
+   *
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * - ARM_MATH_MATRIX_CHECK:
+   *
+   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+   *
+   * - ARM_MATH_ROUNDING:
+   *
+   * Define macro ARM_MATH_ROUNDING for rounding on support functions
+   *
+   * - ARM_MATH_CMx:
+   *
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+   *
+   * - __FPU_PRESENT:
+   *
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+   *
+   * <b>Copyright Notice</b>
+   *
+   * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ *     pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * <pre>
+ *     ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ *     ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ *     ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#ifndef PI
+#define PI					3.14159265358979f
+#endif
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+  /**
+   * @brief Macro for Unaligned Support
+   */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+    #define ALIGN4
+#else
+  #if defined  (__GNUC__)
+    #define ALIGN4 __attribute__((aligned(4)))
+  #else
+    #define ALIGN4 __align(4)
+  #endif
+#endif	/*	#ifndef UNALIGNED_SUPPORT_DISABLE	*/
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+  {
+    ARM_MATH_SUCCESS = 0,                /**< No error */
+    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */
+    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */
+    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */
+    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */
+    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */
+  } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr)  (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))
+
+#define __SIMD64(addr)  (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+#define __PKHTB(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0xFFFF0000) | \
+                                         (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+  q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+  q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+  q63_t x,
+  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(
+  q31_t data)
+  {
+    uint32_t count = 0;
+    uint32_t mask = 0x80000000;
+
+    while((data & mask) == 0)
+    {
+      count += 1u;
+      mask = mask >> 1u;
+    }
+
+    return (count);
+
+  }
+
+#endif
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+  q31_t in,
+  q31_t * dst,
+  q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 1;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 1;
+    }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+    {
+      tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+      tempVal = 0x7FFFFFFF - tempVal;
+      /*      1.31 with exp 1 */
+      //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+      out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+  q15_t in,
+  q15_t * dst,
+  q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+    {
+      signBits = __CLZ(in) - 17;
+    }
+    else
+    {
+      signBits = __CLZ(-in) - 17;
+    }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+    {
+      tempVal = (q15_t) (((q31_t) in * out) >> 15);
+      tempVal = 0x7FFF - tempVal;
+      /*      1.15 with exp 1 */
+      out = (q15_t) (((q31_t) out * tempVal) >> 14);
+    }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+  static __INLINE q31_t __SSAT(
+  q31_t x,
+  uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+    {
+      posMax = posMax * 2;
+    }
+
+    if(x > 0)
+    {
+      posMax = (posMax - 1);
+
+      if(x > posMax)
+      {
+        x = posMax;
+      }
+    }
+    else
+    {
+      negMin = -posMax;
+
+      if(x < negMin)
+      {
+        x = negMin;
+      }
+    }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum =
+      (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (q7_t) x;
+    s = (q7_t) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+                                                                0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum =
+      ((sum +
+        clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+  q31_t x,
+  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) -
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+  q31_t x,
+  q31_t y)
+  {
+
+    return ((q31_t) (((short) x * (short) (y >> 16)) +
+                     ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+  q31_t x,
+  q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+  q31_t x,
+  q31_t y,
+  q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+  q31_t x,
+  q31_t y,
+  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+  q31_t x,
+  q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+  /*
+   * @brief C custom defined SXTB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SXTB16(
+  q31_t x)
+  {
+
+    return ((((x << 24) >> 24) & 0x0000FFFF) |
+            (((x << 8) >> 8) & 0xFFFF0000));
+  }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * <code>numTaps</code> is not a supported value.
+   */
+
+  arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>
+   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0;    /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+    q15_t A1;
+    q15_t A2;
+#else
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag);
+
+
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;           /**< nValues */
+    float32_t x1;               /**< x1 */
+    float32_t xSpacing;         /**< xSpacing */
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    float32_t *pData;   /**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q31_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q15_t *pData;       /**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;   /**< number of rows in the data table. */
+    uint16_t numCols;   /**< number of columns in the data table. */
+    q7_t *pData;                /**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                     /**< points to the Sin twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q15;
+
+  arm_status arm_cfft_radix2_init_q15(
+  arm_cfft_radix2_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q15(
+  const arm_cfft_radix2_instance_q15 * S,
+  q15_t * pSrc);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                     /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix2_instance_q31;
+
+  arm_status arm_cfft_radix2_init_q31(
+  arm_cfft_radix2_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  void arm_cfft_radix2_q31(
+  const arm_cfft_radix2_instance_q31 * S,
+  q31_t * pSrc);
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                 /**< length of the FFT. */
+    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */
+    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+
+  void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc);
+
+  arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix2_init_f32(
+  arm_cfft_radix2_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix2_f32(
+  const arm_cfft_radix2_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */
+    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */
+    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+    float32_t onebyfftLen;                 /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+  arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+/* Deprecated */
+  void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc);
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t fftLen;                   /**< length of the FFT. */
+    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */
+    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */
+    uint16_t bitRevLength;             /**< bit reversal table length. */
+  } arm_cfft_instance_f32;
+
+  void arm_cfft_f32(
+  const arm_cfft_instance_f32 * S,
+  float32_t * p1,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                      /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */
+    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;          /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst);
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                        /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */
+    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint16_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag);
+
+  void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+typedef struct
+  {
+    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */
+    uint16_t fftLenRFFT;                        /**< length of the real sequence */
+	float32_t * pTwiddleRFFT;					/**< Twiddle factors real stage  */
+  } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+	arm_rfft_fast_instance_f32 * S,
+	uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+  arm_rfft_fast_instance_f32 * S,
+  float32_t * p, float32_t * pOut,
+  uint8_t ifftFlag);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+  float32_t * pSrc,
+  float32_t scale,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+  q7_t * pSrc,
+  q7_t scaleFract,
+  int8_t shift,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+  q15_t * pSrc,
+  q15_t scaleFract,
+  int8_t shift,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+  q31_t * pSrc,
+  q31_t scaleFract,
+  int8_t shift,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t blockSize,
+  float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+  q7_t * pSrcA,
+  q7_t * pSrcB,
+  uint32_t blockSize,
+  q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t blockSize,
+  q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+  q7_t * pSrc,
+  int8_t shiftBits,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+  q15_t * pSrc,
+  int8_t shiftBits,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+  q31_t * pSrc,
+  int8_t shiftBits,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+  float32_t * pSrc,
+  float32_t offset,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+  q7_t * pSrc,
+  q7_t offset,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+  q15_t * pSrc,
+  q15_t offset,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+  q31_t * pSrc,
+  q31_t offset,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector.
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector.
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+  /**
+   * @brief Convolution of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+
+  void arm_conv_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+  void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+    /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_conv_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+    /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]       * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]       * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q7 sequences
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+/**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * <code>blockSize</code> is not a multiple of <code>M</code>.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst);
+
+
+   /**
+   * @brief Correlation of Q15 sequences
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+  void arm_correlate_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @return none.
+   */
+
+  void arm_correlate_fast_opt_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  q15_t * pScratch);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst);
+
+
+
+ /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @param[in]  *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+   * @param[in]  *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+   * @return none.
+   */
+
+  void arm_correlate_opt_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  q15_t * pScratch1,
+  q15_t * pScratch2);
+
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst);
+
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cos output.
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees
+   * @param[out] *pSinVal points to the processed sine output.
+   * @param[out] *pCosVal points to the processed cosine output.
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * <pre>
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  </pre>
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   *
+   * \par
+   * \image html PID.gif "Proportional Integral Derivative Controller"
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.
+   * The proportional value determines the reaction to the current error,
+   * the integral value determines the reaction based on the sum of recent errors,
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+   * A separate instance structure must be defined for each PID Controller.
+   * There are separate instance structure declarations for each of the 3 supported data types.
+   *
+   * \par Reset Functions
+   * There is also an associated reset function for each data type which clears the state array.
+   *
+   * \par Initialization Functions
+   * There is also an associated initialization function for each data type.
+   * The initialization function performs the following operations:
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.
+   *
+   * \par
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+   *
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the fixed-point versions of the PID Controller functions.
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+  arm_pid_instance_f32 * S,
+  float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 64-bit accumulator.
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+   * Thus, if the accumulator result overflows it wraps around rather than clip.
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+  arm_pid_instance_q31 * S,
+  q31_t in)
+  {
+    q63_t acc;
+    q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using a 64-bit internal accumulator.
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+  arm_pid_instance_q15 * S,
+  q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+    __SIMD32_TYPE *vstate;
+
+    /* Implementation of PID controller */
+
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    vstate = __SIMD32_CONST(S->state);
+    acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+    /* acc = A0 * x[n]  */
+    acc = ((q31_t) S->A0) * in;
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc += (q31_t) S->A1 * S->state[0];
+    acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * src,
+  arm_matrix_instance_f32 * dst);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+   * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+  float32_t Ia,
+  float32_t Ib,
+  float32_t * pIalpha,
+  float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta =
+      ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate <code>a</code>
+   * @param[in]       Ib       input three-phase coordinate <code>b</code>
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+  q31_t Ia,
+  q31_t Ib,
+  q31_t * pIalpha,
+  q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pIa,
+  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate <code>a</code>
+   * @param[out]      *pIb    points to output three-phase coordinate <code>b</code>
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pIa,
+  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+   * from the stationary to the moving reference frame and control the spatial relationship between
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+  float32_t Ialpha,
+  float32_t Ibeta,
+  float32_t * pId,
+  float32_t * pIq,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+  q31_t Ialpha,
+  q31_t Ibeta,
+  q31_t * pId,
+  q31_t * pIq,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output.
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+  float32_t Id,
+  float32_t Iq,
+  float32_t * pIalpha,
+  float32_t * pIbeta,
+  float32_t sinVal,
+  float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * <b>Scaling and Overflow Behavior:</b>
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+  q31_t Id,
+  q31_t Iq,
+  q31_t * pIalpha,
+  q31_t * pIbeta,
+  q31_t sinVal,
+  q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * <pre>
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * </pre>
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+   * <code>x</code> is the input sample value. The functions returns the output value.
+   *
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table
+   * if x is below input range and returns last value of table if x is above range.
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+  arm_linear_interp_instance_f32 * S,
+  float32_t x)
+  {
+
+    float32_t y;
+    float32_t x0, x1;                            /* Nearest input values */
+    float32_t y0, y1;                            /* Nearest output values */
+    float32_t xSpacing = S->xSpacing;            /* spacing between input values */
+    int32_t i;                                   /* Index variable */
+    float32_t *pYData = S->pYData;               /* pointer to output table */
+
+    /* Calculation of index */
+    i = (int32_t) ((x - S->x1) / xSpacing);
+
+    if(i < 0)
+    {
+      /* Iniatilize output for below specified range as least output value of table */
+      y = pYData[0];
+    }
+    else if((uint32_t)i >= S->nValues)
+    {
+      /* Iniatilize output for above specified range as last output value of table */
+      y = pYData[S->nValues - 1];
+    }
+    else
+    {
+      /* Calculation of nearest input values */
+      x0 = S->x1 + i * xSpacing;
+      x1 = S->x1 + (i + 1) * xSpacing;
+
+      /* Read of nearest output values */
+      y0 = pYData[i];
+      y1 = pYData[i + 1];
+
+      /* Calculation of output */
+      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+    }
+
+    /* returns output value */
+    return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(
+  q31_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* shift left by 11 to keep fract in 1.31 format */
+      fract = (x & 0x000FFFFF) << 11;
+
+      /* Read two nearest output values from the index in 1.31(q31) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+      y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+      /* Convert y to 1.31 format */
+      return (y << 1u);
+
+    }
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(
+  q15_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q63_t y;                                     /* output */
+    q15_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                               /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+    if(index >= (int32_t)(nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else if(index < 0)
+    {
+      return (pYData[0]);
+    }
+    else
+    {
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+      y = ((q63_t) y0 * (0xFFFFF - fract));
+
+      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+      y += ((q63_t) y1 * (fract));
+
+      /* convert y to 1.15 format */
+      return (y >> 20);
+    }
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(
+  q7_t * pYData,
+  q31_t x,
+  uint32_t nValues)
+  {
+    q31_t y;                                     /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    uint32_t index;                              /* Index to read nearest output values */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    if (x < 0)
+    {
+      return (pYData[0]);
+    }
+    index = (x >> 20) & 0xfff;
+
+
+    if(index >= (nValues - 1))
+    {
+      return (pYData[nValues - 1]);
+    }
+    else
+    {
+
+      /* 20 bits for the fractional part */
+      /* fract is in 12.20 format */
+      fract = (x & 0x000FFFFF);
+
+      /* Read two nearest output values from the index and are in 1.7(q7) format */
+      y0 = pYData[index];
+      y1 = pYData[index + 1u];
+
+      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+      y = ((y0 * (0xFFFFF - fract)));
+
+      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+      y += (y1 * fract);
+
+      /* convert y to 1.7(q7) format */
+      return (y >> 20u);
+
+    }
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+  float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+  q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+  float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+  q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+  q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * <pre>
+   *      x1 = x0 - f(x0)/f'(x0)
+   * </pre>
+   * where <code>x1</code> is the current estimate,
+   * <code>x0</code> is the previous estimate, and
+   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+   * For the square root function, the algorithm reduces to:
+   * <pre>
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * </pre>
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status arm_sqrt_f32(
+  float32_t in,
+  float32_t * pOut)
+  {
+    if(in > 0)
+    {
+
+//      #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM   )
+      *pOut = __sqrtf(in);
+#else
+      *pOut = sqrtf(in);
+#endif
+
+      return (ARM_MATH_SUCCESS);
+    }
+    else
+    {
+      *pOut = 0.0f;
+      return (ARM_MATH_ARGUMENT_ERROR);
+    }
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * <code>in</code> is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const int32_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+  int32_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  int32_t * dst,
+  int32_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (int32_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value  */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q15_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+  q15_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q15_t * dst,
+  q15_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q15_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  uint16_t * writeOffset,
+  int32_t bufferInc,
+  const q7_t * src,
+  int32_t srcInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the input sample to the circular buffer */
+      circBuffer[wOffset] = *src;
+
+      /* Update the input pointer */
+      src += srcInc;
+
+      /* Circularly update wOffset.  Watch out for positive and negative value */
+      wOffset += bufferInc;
+      if(wOffset >= L)
+        wOffset -= L;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+  q7_t * circBuffer,
+  int32_t L,
+  int32_t * readOffset,
+  int32_t bufferInc,
+  q7_t * dst,
+  q7_t * dst_base,
+  int32_t dst_length,
+  int32_t dstInc,
+  uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+    {
+      /* copy the sample from the circular buffer to the destination buffer */
+      *dst = circBuffer[rOffset];
+
+      /* Update the input pointer */
+      dst += dstInc;
+
+      if(dst == (q7_t *) dst_end)
+      {
+        dst = dst_base;
+      }
+
+      /* Circularly update rOffset.  Watch out for positive and negative value */
+      rOffset += bufferInc;
+
+      if(rOffset >= L)
+      {
+        rOffset -= L;
+      }
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * result,
+  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return none.
+   */
+  void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector.
+   * @param[in]       *pSrc points to the floating-point input vector
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector
+   * @return          none
+   */
+  void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * <b>Algorithm</b>
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * <pre>
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * </pre>
+   *
+   * \par
+   * where <code>numRows</code> specifies the number of rows in the table;
+   * <code>numCols</code> specifies the number of columns in the table;
+   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+   *
+   * \par
+   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:
+   * <pre>
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * </pre>
+   * \par
+   * The interpolated output point is computed as:
+   * <pre>
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * </pre>
+   * Note that the coordinates (x, y) contain integer and fractional components.
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+
+  static __INLINE float32_t arm_bilinear_interp_f32(
+  const arm_bilinear_interp_instance_f32 * S,
+  float32_t X,
+  float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+       || yIndex > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+  arm_bilinear_interp_instance_q31 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+  arm_bilinear_interp_instance_q15 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                              /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+  arm_bilinear_interp_instance_q7 * S,
+  q31_t X,
+  q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                              /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+    /* Care taken for table outside boundary */
+    /* Returns zero output when values are outside table boundary */
+    if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+    {
+      return (0);
+    }
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+#if   defined ( __CC_ARM ) //Keil
+//SMMLAR
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("push")         \
+     _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT \
+     _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+  #define LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+     _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+  #define multAcc_32x32_keep32_R(a, x, y) \
+  a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+  #define multSub_32x32_keep32_R(a, x, y) \
+  a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+  #define mult_32x32_keep32_R(a, x, y) \
+  a = (q31_t) (((q63_t) x * y ) >> 32)
+
+  #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+  #define LOW_OPTIMIZATION_EXIT
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */

bsp/mb9bf618s/CMSIS/Include/core_cm0.h

@@ -0,0 +1,682 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/Include/core_cm0plus.h

@@ -0,0 +1,793 @@
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex-M0+
+  @{
+ */
+
+/*  CMSIS CM0P definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)                                /*!< [31:16] CMSIS HAL main version   */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x20)                                /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+#if (__VTOR_PRESENT == 1)
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+#else
+       uint32_t RESERVED0;
+#endif
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if (__VTOR_PRESENT == 1)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0+ Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/Include/core_cm3.h

@@ -0,0 +1,1627 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M3
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM3_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/Include/core_cm4.h

@@ -0,0 +1,1772 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM4_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM4_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x04)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+#include <core_cm4_simd.h>               /* Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+    \brief      Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/Include/core_cm4_simd.h

@@ -0,0 +1,673 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_iar.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+#include <cmsis_ccs.h>
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/Include/core_cmFunc.h

@@ -0,0 +1,636 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

bsp/mb9bf618s/CMSIS/Include/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/mb9bf618s/CMSIS/Include/core_sc000.h

@@ -0,0 +1,813 @@
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC000
+  @{
+ */
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (0)                                       /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED0[1];
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+       uint32_t RESERVED1[154];
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Register                            */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/* SCB Security Features Register Definitions */
+#define SCB_SFCR_UNIBRTIMING_Pos            0                                             /*!< SCB SFCR: UNIBRTIMING Position */
+#define SCB_SFCR_UNIBRTIMING_Msk           (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SFCR: UNIBRTIMING Mask */
+
+#define SCB_SFCR_SECKEY_Pos                16                                             /*!< SCB SFCR: SECKEY Position */
+#define SCB_SFCR_SECKEY_Msk               (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos)        /*!< SCB SFCR: SECKEY Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of SC000 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/Include/core_sc300.h

@@ -0,0 +1,1598 @@
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup SC3000
+  @{
+ */
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (0x20)                                   /*!< [15:0]  CMSIS HAL sub version  */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16) | \
+                                      __SC300_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
+
+#define __CORTEX_SC                (300)                                     /*!< Cortex secure core             */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
+#include <core_cmFunc.h>                 /* Core Function Access                            */
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+    \brief      Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+       uint32_t RESERVED1[1];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+    \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];
+  __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
+  __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];
+  __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
+  __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];
+  __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+    \brief      Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
+  __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
+  __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
+  __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
+  __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
+  __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
+  __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
+  __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
+  __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
+  __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
+  __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
+       uint32_t RESERVED0[1];
+  __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
+  __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
+  __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
+       uint32_t RESERVED1[1];
+  __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
+  __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
+  __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
+       uint32_t RESERVED2[1];
+  __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
+  __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
+  __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+    \brief      Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/** \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
+  __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+       uint32_t RESERVED0[2];
+  __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+       uint32_t RESERVED1[55];
+  __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+       uint32_t RESERVED2[131];
+  __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+       uint32_t RESERVED3[759];
+  __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+       uint32_t RESERVED4[1];
+  __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+       uint32_t RESERVED5[39];
+  __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+       uint32_t RESERVED7[8];
+  __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+    \brief      Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Type definitions for the Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  The function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+    \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    The function reads the active register in NVIC and returns the active bit.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not active.
+    \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    The function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value, and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+
+    \param [in]     PriorityGroup  Used priority group.
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+    \param [in]       SubPriority  Subpriority value (starting from 0).
+    \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    The function decodes an interrupt priority value with a given priority group to
+    preemptive priority value and subpriority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+    \param [in]     PriorityGroup  Used priority group.
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+    \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
+
+  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions ITM Functions
+    \brief   Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief  ITM Send Character
+
+    The function transmits a character via the ITM channel 0, and
+    \li Just returns when no debugger is connected that has booked the output.
+    \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+    \param [in]     ch  Character to transmit.
+
+    \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+    \return             Received character.
+    \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+    \return          0  No character available.
+    \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif

bsp/mb9bf618s/CMSIS/README.txt

@@ -0,0 +1,37 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011-2013 ARM Limited. All rights reserved.  
+* 
+* Date:        18 March 2013  
+* Revision:    V3.20 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Libraries.
+
+RTOS                    - CMSIS RTOS API template header file.
+
+SVD                     - CMSIS SVD Schema files and Conversion Utility.

bsp/mb9bf618s/CMSIS/SConscript

@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('DeviceSupport/fujitsu/mb9bf61x/*.c')
+
+CPPPATH = [cwd + '/Include', cwd + '/DeviceSupport/fujitsu/mb9bf61x/']
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/gcc/startup_mb9bf61x.c']
+elif rtconfig.CROSS_TOOL == 'keil':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/arm/startup_mb9bf61x.S']
+elif rtconfig.CROSS_TOOL == 'iar':
+	src += ['DeviceSupport/fujitsu/mb9bf61x/startup/iar/startup_mb9bf61x.S']
+
+CPPDEFINES = [rtconfig.FM3_TYPE]
+group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/mb9bf618s/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/mb9bf618s/SConstruct

@@ -0,0 +1,34 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+	env.Replace(ARFLAGS = '')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/mb9bf618s/applications/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf618s/applications/application.c

@@ -0,0 +1,58 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-24     Bernard      the first version
+ */
+
+/**
+ * @addtogroup FM3
+ */
+/*@{*/
+
+#include <rtthread.h>
+#include "board.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+void rt_init_thread_entry(void *parameter)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    /* initialization RT-Thread Components */
+    rt_components_init();
+#endif
+
+#ifdef  RT_USING_FINSH
+    finsh_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif  /* RT_USING_FINSH */
+
+    /**< init led device */
+    {
+        extern void rt_led_hw_init(void);
+        rt_led_hw_init();
+    }
+
+}
+
+int rt_application_init()
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("init",
+                           rt_init_thread_entry, RT_NULL,
+                           2048, 8, 20);
+    if (tid != RT_NULL) rt_thread_startup(tid);
+
+    return 0;
+}
+
+/*@}*/

bsp/mb9bf618s/applications/startup.c

@@ -0,0 +1,88 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+/**
+ * @addtogroup FM3
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+    /* init board */
+    rt_hw_board_init();
+
+    /* show version */
+    rt_show_version();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END);
+#else
+    /* init memory system */
+    rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END);
+#endif
+#endif
+
+    /* init scheduler system */
+    rt_system_scheduler_init();
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+    /* init application */
+    rt_application_init();
+
+    /* init idle thread */
+    rt_thread_idle_init();
+
+    /* start scheduler */
+    rt_system_scheduler_start();
+
+    /* never reach here */
+    return ;
+}
+
+int main(void)
+{
+    /* disable interrupt first */
+    rt_hw_interrupt_disable();
+
+    /* startup RT-Thread RTOS */
+    rtthread_startup();
+
+    return 0;
+}
+
+/*@}*/

bsp/mb9bf618s/drivers/SConscript

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mb9bf618s/drivers/board.c

@@ -0,0 +1,100 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-02-24     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include "serial.h"
+
+#ifdef  RT_USING_COMPONENTS_INIT
+#include <components.h>
+#endif  /* RT_USING_COMPONENTS_INIT */
+
+/**
+ * @addtogroup FM3
+ */
+
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This fucntion returns milliseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_millisecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_MS (1000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_MS + (SysTick->LOAD - SysTick->VAL) * TICK_MS / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+ * This fucntion returns microseconds since system passed
+ */
+rt_uint32_t rt_hw_tick_get_microsecond(void)
+{
+    rt_tick_t tick;
+    rt_uint32_t value;
+
+#define TICK_US	(1000000/RT_TICK_PER_SECOND)
+
+    tick = rt_tick_get();
+    value = tick * TICK_US + (SysTick->LOAD - SysTick->VAL) * TICK_US / SysTick->LOAD;
+
+    return value;
+}
+
+/**
+* This function will initial FM3 Easy Kit board.
+ */
+void rt_hw_board_init(void)
+{
+    /* disable all analog input. */
+    FM3_GPIO->ADE = 0;
+
+    /* init systick */
+    SysTick_Config(SystemCoreClock/RT_TICK_PER_SECOND);
+
+    /* initialize UART device */
+    rt_hw_serial_init();
+    /* set console as UART device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/*@}*/

bsp/mb9bf618s/drivers/board.h

@@ -0,0 +1,50 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2011-03-04     lgnq         add board.h to FM3 bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#if   defined MB9B610S
+#   include <mb9b610s.h>
+#elif defined MB9B610T
+#   include <mb9b610t.h>
+#else
+#   warning "you must define CPU type. e.g: MB9B610S or MB9B610T"
+#   warning "define MB9B610S default"
+#   define MB9B610S /* default: MB9B610S */
+#   include <mb9b610s.h>
+#endif
+
+#include "serial.h"
+
+//Internal SRAM memory size[Kbytes] <8-64>
+//product  MB9BFx16S/T  MB9BFx17S/T  MB9BFx18S/T
+//FLASH  :    512           768          1024
+//SRAM0  :    32            48           64
+//SRAM1  :    32            48           64
+#define FM3_SRAM_SIZE         128
+#define FM3_SRAM_END          (0x1FFF0000 + FM3_SRAM_SIZE * 1024)
+
+/* RT_USING_UART */
+#define RT_USING_UART0
+//#define RT_USING_UART2
+//#define RT_USING_UART4
+#define RT_UART_RX_BUFFER_SIZE        64
+
+void rt_hw_board_init(void);
+rt_uint32_t rt_hw_tick_get_millisecond(void);
+rt_uint32_t rt_hw_tick_get_microsecond(void);
+
+#endif

bsp/mb9bf618s/drivers/led.c

@@ -0,0 +1,157 @@
+#include <rtthread.h>
+#include "board.h"
+
+#define RT_DEVICE_CTRL_RTC_GET_COUNT        0x81        /**< get count                                   */
+
+#define LED_NUM                             4
+struct fm3_gpio_ctrl
+{
+    uint32_t led_num;
+    volatile uint32_t * PDOR;
+    volatile uint32_t * PDIR;
+};
+
+struct fm3_led
+{
+    /* inherit from rt_device */
+    struct rt_device parent;
+
+    struct fm3_gpio_ctrl fm3_gpio_ctrl[LED_NUM];
+};
+
+static struct fm3_led fm3_led;
+
+static rt_err_t rt_led_init (rt_device_t dev)
+{
+    uint32_t i;
+
+    /* led0 : P54 */
+    FM3_GPIO->PFR5 &= ~((1<<7) | (1<<6) | (1<<5) |(1<<4));  /* set P54 fuction is GPIO. */
+    FM3_GPIO->DDR5 |=  (1<<7) | (1<<6) | (1<<5) |(1<<4);    /* set P54 output. */
+
+    /* LED0 */
+    i = 0;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 4;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    /* LED1 */
+    i++;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 5;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    /* LED2 */
+    i++;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 6;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    /* LED3 */
+    i++;
+    fm3_led.fm3_gpio_ctrl[i].led_num = 7;
+    fm3_led.fm3_gpio_ctrl[i].PDOR = &FM3_GPIO->PDOR5;
+    fm3_led.fm3_gpio_ctrl[i].PDIR = &FM3_GPIO->PDIR5;
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK;
+}
+
+static rt_err_t rt_led_close(rt_device_t dev)
+{
+    return RT_EOK;
+}
+
+static rt_size_t rt_led_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                              rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nr = size;
+    rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm3_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nr; index++)
+    {
+        if(*fm3_led.fm3_gpio_ctrl[pos+index].PDIR & 1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num)
+        {
+            *value = 0;
+        }
+        else
+        {
+            *value = 1;
+        }
+        value++;
+    }
+    return index;
+}
+
+static rt_size_t rt_led_write (rt_device_t dev, rt_off_t pos,
+                               const void* buffer, rt_size_t size)
+{
+    rt_ubase_t index = 0;
+    rt_ubase_t nw = size;
+    const rt_uint8_t * value = buffer;
+
+    RT_ASSERT(dev == &fm3_led.parent);
+    RT_ASSERT((pos+size) <= LED_NUM );
+
+    for(index=0; index<nw; index++)
+    {
+        if(*value++)
+        {
+            *fm3_led.fm3_gpio_ctrl[pos+index].PDOR &= ~(1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num);
+        }
+        else
+        {
+            *fm3_led.fm3_gpio_ctrl[pos+index].PDOR |= (1<<fm3_led.fm3_gpio_ctrl[pos+index].led_num);
+        }
+    }
+    return index;
+}
+
+static rt_err_t rt_led_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev == &fm3_led.parent);
+
+    if(cmd == RT_DEVICE_CTRL_RTC_GET_COUNT)
+    {
+        rt_uint32_t * led_num = args;
+        *led_num = LED_NUM;
+    }
+    return RT_EOK;
+}
+
+void rt_led_hw_init(void)
+{
+    fm3_led.parent.type 		= RT_Device_Class_Char;
+    fm3_led.parent.rx_indicate  = RT_NULL;
+    fm3_led.parent.tx_complete  = RT_NULL;
+    fm3_led.parent.init 		= rt_led_init;
+    fm3_led.parent.open		    = rt_led_open;
+    fm3_led.parent.close		= rt_led_close;
+    fm3_led.parent.read         = rt_led_read;
+    fm3_led.parent.write 		= rt_led_write;
+    fm3_led.parent.control 	    = rt_led_control;
+    fm3_led.parent.user_data	= RT_NULL;
+
+    /* register a character device */
+    rt_device_register(&fm3_led.parent, "led", RT_DEVICE_FLAG_RDWR);
+    /* init led device */
+    rt_led_init(&fm3_led.parent);
+}
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+void led(rt_uint32_t led, rt_uint32_t value)
+{
+    rt_uint8_t led_value = value;
+    rt_led_write(&fm3_led.parent, led, &led_value, 1);
+}
+FINSH_FUNCTION_EXPORT(led, e.g:led(0,100).)
+#endif

bsp/mb9bf618s/drivers/serial.c

@@ -0,0 +1,437 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.
+ */
+
+#include <rtthread.h>
+
+#include "serial.h"
+
+/**
+ * @addtogroup FM3 MB9B610
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+/**
+ * This function initializes serial
+ */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+    struct serial_device* uart = (struct serial_device*) dev->user_data;
+
+    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+    {
+        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            rt_memset(uart->int_rx->rx_buffer, 0,
+                      sizeof(uart->int_rx->rx_buffer));
+            uart->int_rx->read_index = uart->int_rx->save_index = 0;
+        }
+
+        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_memset(uart->int_tx->tx_buffer, 0,
+                      sizeof(uart->int_tx->tx_buffer));
+            uart->int_tx->write_index = uart->int_tx->save_index = 0;
+        }
+
+        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+    }
+
+    return RT_EOK;
+}
+
+/* save a char to serial buffer */
+static void rt_serial_savechar(struct serial_device* uart, char ch)
+{
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
+    uart->int_rx->save_index ++;
+    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+        uart->int_rx->save_index = 0;
+
+    /* if the next position is read index, discard this 'read char' */
+    if (uart->int_rx->save_index == uart->int_rx->read_index)
+    {
+        uart->int_rx->read_index ++;
+        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+            uart->int_rx->read_index = 0;
+    }
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable interrupt */
+        UART_ENABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+    struct serial_device* uart;
+
+    RT_ASSERT(dev != RT_NULL);
+    uart = (struct serial_device*) dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        UART_DISABLE_IRQ(uart->rx_irq);
+    }
+
+    return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer,
+                                 rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    ptr = buffer;
+    err_code = RT_EOK;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        rt_base_t level;
+
+        /* interrupt mode Rx */
+        while (size)
+        {
+            if (uart->int_rx->read_index != uart->int_rx->save_index)
+            {
+                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+                size --;
+
+                /* disable interrupt */
+                level = rt_hw_interrupt_disable();
+
+                uart->int_rx->read_index ++;
+                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+                    uart->int_rx->read_index = 0;
+
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+            }
+            else
+            {
+                /* set error code */
+                err_code = -RT_EEMPTY;
+                break;
+            }
+        }
+    }
+    else
+    {
+        /* polling mode */
+        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+        {
+            while (uart->uart_device->SSR & SSR_RDRF)
+            {
+                *ptr = uart->uart_device->RDR & 0xff;
+                ptr ++;
+            }
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos,
+                                  const void* buffer, rt_size_t size)
+{
+    rt_uint8_t* ptr;
+    rt_err_t err_code;
+    struct serial_device* uart;
+
+    err_code = RT_EOK;
+    ptr = (rt_uint8_t*)buffer;
+    uart = (struct serial_device*)dev->user_data;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+    {
+        /* interrupt mode Tx */
+        while (uart->int_tx->save_index != uart->int_tx->write_index)
+        {
+            /* save on tx buffer */
+            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
+
+            -- size;
+
+            /* move to next position */
+            uart->int_tx->save_index ++;
+
+            /* wrap save index */
+            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
+                uart->int_tx->save_index = 0;
+        }
+
+        /* set error code */
+        if (size > 0)
+            err_code = -RT_EFULL;
+    }
+    else
+    {
+        /* polling mode */
+        while (size)
+        {
+            /*
+             * to be polite with serial console add a line feed
+             * to the carriage return character
+             */
+            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
+            {
+                while (!(uart->uart_device->SSR & SSR_TDRE));
+                uart->uart_device->TDR = '\r';
+            }
+
+            while (!(uart->uart_device->SSR & SSR_TDRE));
+            uart->uart_device->TDR = (*ptr & 0x1FF);
+
+            ++ptr;
+            --size;
+        }
+    }
+
+    /* set error code */
+    rt_set_errno(err_code);
+
+    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SUSPEND:
+        /* suspend device */
+        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+        break;
+
+    case RT_DEVICE_CTRL_RESUME:
+        /* resume device */
+        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+/*
+ * serial register
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name,
+                               rt_uint32_t flag, struct serial_device *serial)
+{
+    RT_ASSERT(device != RT_NULL);
+
+    device->type 		= RT_Device_Class_Char;
+    device->rx_indicate = RT_NULL;
+    device->tx_complete = RT_NULL;
+    device->init 		= rt_serial_init;
+    device->open		= rt_serial_open;
+    device->close		= rt_serial_close;
+    device->read 		= rt_serial_read;
+    device->write 		= rt_serial_write;
+    device->control 	= rt_serial_control;
+    device->user_data	= serial;
+
+    /* register a character device */
+    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+    struct serial_device* uart = (struct serial_device*) device->user_data;
+
+    /* interrupt mode receive */
+    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+    /* save on rx buffer */
+    while (uart->uart_device->SSR & SSR_RDRF)
+    {
+        rt_serial_savechar(uart, uart->uart_device->RDR & 0xff);
+    }
+
+    /* invoke callback */
+    if (device->rx_indicate != RT_NULL)
+    {
+        rt_size_t rx_length;
+
+        /* get rx length */
+        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+                    uart->int_rx->save_index - uart->int_rx->read_index;
+
+        device->rx_indicate(device, rx_length);
+    }
+}
+
+#ifdef RT_USING_UART0
+/* UART0 device driver structure */
+#define UART0	FM3_MFS0_UART
+struct serial_int_rx uart0_int_rx;
+struct serial_device uart0 =
+{
+    UART0,
+    MFS0RX_IRQn,
+    MFS0TX_IRQn,
+    &uart0_int_rx,
+    RT_NULL
+};
+struct rt_device uart0_device;
+
+void MFS0RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart0_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /**< #ifdef RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+/* UART2 device driver structure */
+#define UART2	FM3_MFS2_UART
+struct serial_int_rx uart2_int_rx;
+struct serial_device uart2 =
+{
+    UART2,
+    MFS2RX_IRQn,
+    MFS2TX_IRQn,
+    &uart2_int_rx,
+    RT_NULL
+};
+struct rt_device uart2_device;
+
+void MFS2RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart2_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /**< #ifdef RT_USING_UART2 */
+
+#ifdef RT_USING_UART4
+/* UART4 device driver structure */
+#define UART4	FM3_MFS4_UART
+struct serial_int_rx uart4_int_rx;
+struct serial_device uart4 =
+{
+    (FM3_MFS03_UART_TypeDef*)UART4,
+    MFS4RX_IRQn,
+    MFS4TX_IRQn,
+    &uart4_int_rx,
+    RT_NULL
+};
+struct rt_device uart4_device;
+
+void MFS4RX_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_hw_serial_isr(&uart4_device);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /**< #ifdef RT_USING_UART4 */
+
+void rt_hw_serial_init(void)
+{
+    uint32_t APB2_clock = (SystemCoreClock >> (APBC2_PSR_Val & 0x03));
+
+#ifdef RT_USING_UART0
+    /* initialize UART0 */
+    /* Set Uart Ch0 Port, SIN0_0:P21, SOT0_0:P22 */
+    FM3_GPIO->ADE &= ~(1UL<<31); /* disable P22 AN31 function */
+    FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | (1<<1) | (1<<2);
+    FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 & ~(3<<4 | 3<<6) | (1<<4) | (1<<6);
+
+    uart0.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart0.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart0.uart_device->ESCR = ESCR_DATABITS_8;
+    uart0.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&uart0_device,
+                          "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart0);
+#endif /**< #ifdef RT_USING_UART0 */
+
+#ifdef RT_USING_UART2
+    /* initialize UART2 */
+    /* Set Uart Ch2 Port, SIN2_2:P17, SOT2_2:P18 */
+    FM3_GPIO->ADE &= ~(1<<7 | 1<<8); /* disable P17 AN07 and P18 AN08 function */
+    FM3_GPIO->PFR1 = FM3_GPIO->PFR1 | (1<<7) | (1<<8) ;
+    FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | (3<<16) | (3<<18) ;
+
+    uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart2.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart2.uart_device->ESCR = ESCR_DATABITS_8;
+    uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&uart2_device,
+                          "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart2);
+#endif /**< #ifdef RT_USING_UART2 */
+
+#ifdef RT_USING_UART4
+    /* initialize UART4 */
+    /* Set Uart Ch4 Port, SIN4_2:P05, SOT4_2:P06 */
+    FM3_GPIO->PFR0 = FM3_GPIO->PFR0 | (1<<5) | (1<<6);
+    FM3_GPIO->EPFR08 = FM3_GPIO->EPFR08 | (3<<4) | (3<<6);
+
+    uart4.uart_device->SMR = SMR_MD_UART | SMR_SOE;;
+    uart4.uart_device->BGR = (APB2_clock + (BPS/2))/BPS - 1; /* round */
+    uart4.uart_device->ESCR = ESCR_DATABITS_8;
+    uart4.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE;
+
+    /* register UART4 device */
+    rt_hw_serial_register(&uart4_device,
+                          "uart4",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                          &uart4);
+#endif /**< #ifdef RT_USING_UART4 */
+}
+
+/*@}*/

bsp/mb9bf618s/drivers/serial.h

@@ -0,0 +1,99 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ * 2011-05-15     lgnq         modified according bernard's implementaion.      	  	
+ */
+
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#define SMR_SOE          0x01U
+#define SMR_BDS          0x04U
+#define SMR_SBL          0x08U
+#define SMR_WUCR         0x10U
+#define SMR_MD_UART      0x00U
+#define SMR_MD_UART_MP   0x20U
+#define SMR_MD_SIO       0x40U
+#define SMR_MD_LIN       0x60U
+#define SMR_MD_I2C       0x80U
+
+#define SCR_TXE          0x01U
+#define SCR_RXE          0x02U
+#define SCR_TBIE         0x04U
+#define SCR_TIE          0x08U
+#define SCR_RIE          0x10U
+#define SCR_UPGL         0x80U
+
+#define SSR_TBI          0x01U
+#define SSR_TDRE         0x02U
+#define SSR_RDRF         0x04U
+#define SSR_ORE          0x08U
+#define SSR_FRE          0x10U
+#define SSR_PE           0x20U
+#define SSR_REC          0x80U
+
+#define ESCR_P           0x08U
+#define ESCR_PEN         0x10U
+#define ESCR_INV         0x20U
+#define ESCR_ESBL        0x40U
+#define ESCR_FLWEN       0x80U
+#define ESCR_DATABITS_8  0x00U
+#define ESCR_DATABITS_5  0x01U
+#define ESCR_DATABITS_6  0x02U
+#define ESCR_DATABITS_7  0x03U
+#define ESCR_DATABITS_9  0x04U
+
+#define BPS					115200	/* serial baudrate */
+
+#define UART_RX_BUFFER_SIZE		64
+#define UART_TX_BUFFER_SIZE		64
+
+struct serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct serial_int_tx
+{
+	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
+	rt_uint32_t write_index, save_index;
+};
+
+/*
+ *  Enable/DISABLE Interrupt Controller
+ */
+/* deviation from MISRA-C:2004 Rule 19.7 */
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+struct serial_device
+{
+	FM3_MFS03_UART_TypeDef* uart_device;
+	/* irq number */
+	IRQn_Type rx_irq, tx_irq;
+
+	/* rx structure */
+	struct serial_int_rx* int_rx;
+	/* tx structure */
+	struct serial_int_tx* int_tx;
+};
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_init(void);
+
+#endif

bsp/mb9bf618s/rtconfig.h

@@ -0,0 +1,74 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX				        8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE			        4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	        32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND		        100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* SECTION: IPC */
+/* Using Semaphore */
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
+#define RT_USING_COMPONENTS_INIT
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+
+/* SECTION: Console options */
+/* #define RT_TINY_SIZE */
+#define RT_USING_CONSOLE
+/* the buffer size of console */
+#define RT_CONSOLEBUF_SIZE	128
+// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
+#define RT_CONSOLE_DEVICE_NAME	        "uart0"
+
+/* SECTION: finsh, a C-Express shell */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_STACK_SIZE         1024
+
+#endif

bsp/mb9bf618s/rtconfig.py

@@ -0,0 +1,118 @@
+# toolchains options
+ARCH='arm'
+CPU='cortex-m3'
+CROSS_TOOL='keil'
+
+#device options
+# FM3_TYPE = 
+# 'MB9B610S','MB9B610T',
+FM3_TYPE = 'MB9B610S'
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= r'F:\Program Files\CodeSourcery\Sourcery_CodeBench_Lite_for_ARM_EABI_2013.05.23\bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= r'E:/Keil'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	IAR_PATH 	= r'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T rtthread-fm3.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter rtthread-fm3.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    CFLAGS = ''
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    CFLAGS += ' --cpu=Cortex-M3' 
+    CFLAGS += ' -e' 
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+    CFLAGS += ' --use_c++_inline'    
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    AFLAGS += ' --cpu Cortex-M3' 
+    AFLAGS += ' --fpu None' 
+    AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"'
+
+    LFLAGS = ' --config mb9bf506.icf'
+    LFLAGS += ' --semihosting' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' 

bsp/mb9bf618s/rtthread-fm3.icf

@@ -0,0 +1,33 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__   = 0x000FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF0000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x000;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block CSTACK, last block HEAP };

bsp/mb9bf618s/rtthread-fm3.ld

@@ -0,0 +1,143 @@
+/*
+ * linker script for Fujitsu with GNU ld
+ * aozima 2013-07-13
+ */
+
+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH =   1M /*   1MB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128KB sram, 64KB SRAM0 + 64KB SRAM1 */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x400;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _isr_vector = .;     /* define isr_vector start address */
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/mb9bf618s/rtthread-fm3.sct

@@ -0,0 +1,15 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00100000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00100000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x1FFF0000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/mb9bf618s/template.ewp

@@ -0,0 +1,1839 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <configuration>
+    <name>Debug</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>1</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Debug\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Debug\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>Debug\List</state>
+        </option>
+        <option>
+          <name>Variant</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GEndianMode</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>3</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Input description</name>
+          <state>Automatic choice of formatter.</state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter.</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>FPU</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGCoreOrChip</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+        </option>
+        <option>
+          <name>OGProductVersion</name>
+          <state>6.50.2.4581</state>
+        </option>
+        <option>
+          <name>OGLastSavedByProductVersion</name>
+          <state>6.50.2.4581</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MB9BF618S	Fujitsu MB9BF618S</state>
+        </option>
+        <option>
+          <name>GenLowLevelInterface</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>GEndianModeBE</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OGBufferedTerminalOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GenStdoutInterface</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>RTConfigPath2</name>
+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+        </option>
+        <option>
+          <name>GFPUCoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>GBECoreSlave</name>
+          <version>20</version>
+          <state>38</state>
+        </option>
+        <option>
+          <name>OGUseCmsis</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>28</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>CCDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state>Pa050</state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>0000000</state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IEndianMode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLangConformance</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCSignedPlainChar</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state>$FILE_BNAME$.o</state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeSection</name>
+          <state>.text</state>
+        </option>
+        <option>
+          <name>IInterwork2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IProcessorMode2</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CCPosIndRopi</name>
+          <state>0</state>
+        </option>
+        <option>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPosIndNoDynInit</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccLang</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccAllowVLA</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCppDialect</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AEndian</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebug</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OOCOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>project.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\rtthread-fm3.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
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+        <option>
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+          <state>0</state>
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+          <state>0xFF</state>
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+          <name>FillerStart</name>
+          <state>0x0</state>
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+          <name>FillerEnd</name>
+          <state>0x0</state>
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+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptInline</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>ARM</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>3</archiveVersion>
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+        <version>21</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>ExePath</name>
+          <state>Release\Exe</state>
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+        <option>
+          <name>ObjPath</name>
+          <state>Release\Obj</state>
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+        <option>
+          <name>ListPath</name>
+          <state>Release\List</state>
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+        <option>
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+          <version>20</version>
+          <state>38</state>
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+          <version>3</version>
+          <state>0</state>
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+        <option>
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+          <state>Automatic choice of formatter.</state>
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+          <version>2</version>
+          <state>0</state>
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+        <option>
+          <name>Output description</name>
+          <state>Automatic choice of formatter.</state>
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+        <option>
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+          <state>0</state>
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+        <option>
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+          <version>2</version>
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+          <state>1</state>
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+          <version>0</version>
+          <state>1</state>
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+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>RTDescription</name>
+          <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+          <state>6.50.2.4581</state>
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+          <state>0</state>
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+        <option>
+          <name>OGChipSelectEditMenu</name>
+          <state>MB9BF618S	Fujitsu MB9BF618S</state>
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+          <state>1</state>
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+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+          <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
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+          <version>20</version>
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+          <version>20</version>
+          <state>38</state>
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+          <state>0</state>
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+        <option>
+          <name>OGUseCmsisDspLib</name>
+          <state>0</state>
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+          <state>NDEBUG</state>
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+          <state>0</state>
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+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
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+          <state>0</state>
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+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
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+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
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+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
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+        <option>
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+          <state></state>
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+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
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+          <state></state>
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+        <option>
+          <name>CCDiagError</name>
+          <state></state>
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+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
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+        <option>
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+          <version>1</version>
+          <state>1111111</state>
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+          <state>3</state>
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+          <state>0</state>
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+          <name>CCOptLevelSlave</name>
+          <state>1</state>
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+          <state>0</state>
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+          <name>IccCDialect</name>
+          <state>1</state>
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+          <name>IccAllowVLA</name>
+          <state>0</state>
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+          <state>1</state>
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+        <option>
+          <name>IccExceptions</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccRTTI</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccStaticDestr</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccCppInlineSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccCmsis</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IccFloatSemantics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCOptimizationNoSizeConstraints</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AARM</name>
+      <archiveVersion>2</archiveVersion>
+      <data>
+        <version>8</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
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+          <name>AEndian</name>
+          <state>1</state>
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+          <name>ACaseSensitivity</name>
+          <state>1</state>
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+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
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+          <name>AWarnEnable</name>
+          <state>0</state>
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+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
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+          <name>ADebug</name>
+          <state>0</state>
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+        <option>
+          <name>AltRegisterNames</name>
+          <state>0</state>
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+        <option>
+          <name>ADefines</name>
+          <state></state>
+        </option>
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+          <name>AList</name>
+          <state>0</state>
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+          <name>AListHeader</name>
+          <state>1</state>
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+          <state>1</state>
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+          <state>0</state>
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+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
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+          <name>OnlyAssed</name>
+          <state>0</state>
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+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
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+        <option>
+          <name>PageLength</name>
+          <state>80</state>
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+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
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+          <name>AXRef</name>
+          <state>0</state>
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+          <name>AXRefDefines</name>
+          <state>0</state>
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+          <name>AXRefInternal</name>
+          <state>0</state>
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+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
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+        <option>
+          <name>AFpuProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AMultibyteSupport</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ALimitErrorsEdit</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AIgnoreStdInclude</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AUserIncludes</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AExtraOptionsCheckV2</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AExtraOptionsV2</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>OBJCOPY</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>OOCOutputFormat</name>
+          <version>2</version>
+          <state>0</state>
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+        <option>
+          <name>OCOutputOverride</name>
+          <state>0</state>
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+          <name>OOCOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OOCCommandLineProducer</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OOCObjCopyEnable</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>CUSTOM</name>
+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
+    <settings>
+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
+      </data>
+    </settings>
+    <settings>
+      <name>ILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IlinkLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkInputFileSlave</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkOutputFile</name>
+          <state>template.out</state>
+        </option>
+        <option>
+          <name>IlinkDebugInfoEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkKeepSymbols</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkRawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkConfigDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkMapFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkLogFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogInitialization</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogModule</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogSection</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogVeneer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIcfOverride</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkIcfFile</name>
+          <state>$PROJ_DIR$\rtthread-fm3.icf</state>
+        </option>
+        <option>
+          <name>IlinkIcfFileSlave</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkSuppressDiags</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsRem</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsWarn</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkTreatAsErr</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkWarningsAreErrors</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkUseExtraOptions</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkLowLevelInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAutoLibEnable</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkAdditionalLibs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkOverrideProgramEntryLabel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabelSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkProgramEntryLabel</name>
+          <state>__iar_program_start</state>
+        </option>
+        <option>
+          <name>DoFill</name>
+          <state>0</state>
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+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <state>0x0</state>
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+          <name>FillerEnd</name>
+          <state>0x0</state>
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+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
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+        <option>
+          <name>CrcPoly</name>
+          <state>0x11021</state>
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+        <option>
+          <name>CrcCompl</name>
+          <version>0</version>
+          <state>0</state>
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+          <name>CrcBitOrder</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
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+        <option>
+          <name>DoCrc</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkBE8Slave</name>
+          <state>1</state>
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+          <name>IlinkBufferedTerminalOutput</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IlinkStdoutInterfaceSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcFullSize</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkIElfToolPostProcess</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogAutoLibSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogRedirSymbols</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkLogUnusedFragments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcReverseByteOrder</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IlinkCrcUseAsInput</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptInline</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsAllow</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptExceptionsForce</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkCmsis</name>
+          <state>1</state>
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+        <option>
+          <name>IlinkOptMergeDuplSections</name>
+          <state>0</state>
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+        <option>
+          <name>IlinkOptUseVfe</name>
+          <state>1</state>
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+          <name>IlinkOptForceVfe</name>
+          <state>0</state>
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+          <name>IlinkStackAnalysisEnable</name>
+          <state>0</state>
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+          <name>IlinkStackControlFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IlinkStackCallGraphFile</name>
+          <state></state>
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+        <option>
+          <name>CrcAlgorithm</name>
+          <version>0</version>
+          <state>1</state>
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+        <option>
+          <name>CrcUnitSize</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>IARCHIVE</name>
+      <archiveVersion>0</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>IarchiveInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IarchiveOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IarchiveOutput</name>
+          <state>###Unitialized###</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+</project>
+
+

bsp/mb9bf618s/template.uvproj

@@ -0,0 +1,394 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+  <SchemaVersion>1.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rtthread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>MB9BF618S</Device>
+          <Vendor>Fujitsu Semiconductors</Vendor>
+          <Cpu>IRAM(0x20000000-0x2000FFFF) IRAM2(0x1FFF0000-0x1FFFFFFF) IROM(0x00000000-0x000FFFFF) CLOCK(4000000) CPUTYPE("Cortex-M3")</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile>"Startup\Fujitsu\MB9BF610\startup_mb9bf61x.s" ("Fujitsu MB9BF610 Startup Code")</StartupFile>
+          <FlashDriverDll>UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx08_1024 -FS00 -FL0100000)</FlashDriverDll>
+          <DeviceId>6149</DeviceId>
+          <RegisterFile>mb9bf618s.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>SFD\Fujitsu\MB9BF610\MB9BF618S.SFR</SFDFile>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath>Fujitsu\MB9BF610\</RegisterFilePath>
+          <DBRegisterFilePath>Fujitsu\MB9BF610\</DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\</OutputDirectory>
+          <OutputName>rtthread-fm3</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>0</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments>-MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments>-MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+          <Simulator>
+            <UseSimulator>0</UseSimulator>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>1</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>1</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+          </Simulator>
+          <Target>
+            <UseTarget>1</UseTarget>
+            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+            <RunToMain>0</RunToMain>
+            <RestoreBreakpoints>1</RestoreBreakpoints>
+            <RestoreWatchpoints>1</RestoreWatchpoints>
+            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+            <RestoreFunctions>0</RestoreFunctions>
+            <RestoreToolbox>1</RestoreToolbox>
+            <RestoreTracepoints>0</RestoreTracepoints>
+          </Target>
+          <RunDebugAfterBuild>0</RunDebugAfterBuild>
+          <TargetSelection>7</TargetSelection>
+          <SimDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+          </SimDlls>
+          <TargetDlls>
+            <CpuDll></CpuDll>
+            <CpuDllArguments></CpuDllArguments>
+            <PeripheralDll></PeripheralDll>
+            <PeripheralDllArguments></PeripheralDllArguments>
+            <InitializationFile></InitializationFile>
+            <Driver>Segger\JL2CM3.dll</Driver>
+          </TargetDlls>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4099</DriverSelection>
+          </Flash1>
+          <bUseTDR>0</bUseTDR>
+          <Flash2>Segger\JL2CM3.dll</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M3"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>0</RvdsVP>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>0</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>0</EndSel>
+            <uLtcg>0</uLtcg>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x100000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1fff0000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x08000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <ScatterFile>rtthread-fm3.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+</Project>